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path: root/drivers/net/wireless/b43/phy_g.c
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Diffstat (limited to 'drivers/net/wireless/b43/phy_g.c')
-rw-r--r--drivers/net/wireless/b43/phy_g.c119
1 files changed, 39 insertions, 80 deletions
diff --git a/drivers/net/wireless/b43/phy_g.c b/drivers/net/wireless/b43/phy_g.c
index d3f2a700821f..6dcbeb9393eb 100644
--- a/drivers/net/wireless/b43/phy_g.c
+++ b/drivers/net/wireless/b43/phy_g.c
@@ -454,13 +454,13 @@ static void b43_calc_nrssi_offset(struct b43_wldev *dev)
454 backup[10] = b43_radio_read16(dev, 0x007A); 454 backup[10] = b43_radio_read16(dev, 0x007A);
455 backup[11] = b43_radio_read16(dev, 0x0043); 455 backup[11] = b43_radio_read16(dev, 0x0043);
456 456
457 b43_phy_write(dev, 0x0429, b43_phy_read(dev, 0x0429) & 0x7FFF); 457 b43_phy_mask(dev, 0x0429, 0x7FFF);
458 b43_phy_write(dev, 0x0001, 458 b43_phy_write(dev, 0x0001,
459 (b43_phy_read(dev, 0x0001) & 0x3FFF) | 0x4000); 459 (b43_phy_read(dev, 0x0001) & 0x3FFF) | 0x4000);
460 b43_phy_set(dev, 0x0811, 0x000C); 460 b43_phy_set(dev, 0x0811, 0x000C);
461 b43_phy_write(dev, 0x0812, 461 b43_phy_write(dev, 0x0812,
462 (b43_phy_read(dev, 0x0812) & 0xFFF3) | 0x0004); 462 (b43_phy_read(dev, 0x0812) & 0xFFF3) | 0x0004);
463 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) & ~(0x1 | 0x2)); 463 b43_phy_mask(dev, 0x0802, ~(0x1 | 0x2));
464 if (phy->rev >= 6) { 464 if (phy->rev >= 6) {
465 backup[12] = b43_phy_read(dev, 0x002E); 465 backup[12] = b43_phy_read(dev, 0x002E);
466 backup[13] = b43_phy_read(dev, 0x002F); 466 backup[13] = b43_phy_read(dev, 0x002F);
@@ -505,8 +505,7 @@ static void b43_calc_nrssi_offset(struct b43_wldev *dev)
505 b43_radio_read16(dev, 0x007A) & 0x007F); 505 b43_radio_read16(dev, 0x007A) & 0x007F);
506 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */ 506 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
507 b43_phy_set(dev, 0x0814, 0x0001); 507 b43_phy_set(dev, 0x0814, 0x0001);
508 b43_phy_write(dev, 0x0815, 508 b43_phy_mask(dev, 0x0815, 0xFFFE);
509 b43_phy_read(dev, 0x0815) & 0xFFFE);
510 } 509 }
511 b43_phy_set(dev, 0x0811, 0x000C); 510 b43_phy_set(dev, 0x0811, 0x000C);
512 b43_phy_set(dev, 0x0812, 0x000C); 511 b43_phy_set(dev, 0x0812, 0x000C);
@@ -522,8 +521,7 @@ static void b43_calc_nrssi_offset(struct b43_wldev *dev)
522 } 521 }
523 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */ 522 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
524 b43_phy_set(dev, 0x0814, 0x0004); 523 b43_phy_set(dev, 0x0814, 0x0004);
525 b43_phy_write(dev, 0x0815, 524 b43_phy_mask(dev, 0x0815, 0xFFFB);
526 b43_phy_read(dev, 0x0815) & 0xFFFB);
527 } 525 }
528 b43_phy_write(dev, 0x0003, (b43_phy_read(dev, 0x0003) & 0xFF9F) 526 b43_phy_write(dev, 0x0003, (b43_phy_read(dev, 0x0003) & 0xFF9F)
529 | 0x0040); 527 | 0x0040);
@@ -601,9 +599,8 @@ static void b43_calc_nrssi_slope(struct b43_wldev *dev)
601 if (phy->radio_rev == 8) 599 if (phy->radio_rev == 8)
602 b43_calc_nrssi_offset(dev); 600 b43_calc_nrssi_offset(dev);
603 601
604 b43_phy_write(dev, B43_PHY_G_CRS, 602 b43_phy_mask(dev, B43_PHY_G_CRS, 0x7FFF);
605 b43_phy_read(dev, B43_PHY_G_CRS) & 0x7FFF); 603 b43_phy_mask(dev, 0x0802, 0xFFFC);
606 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) & 0xFFFC);
607 backup[7] = b43_read16(dev, 0x03E2); 604 backup[7] = b43_read16(dev, 0x03E2);
608 b43_write16(dev, 0x03E2, b43_read16(dev, 0x03E2) | 0x8000); 605 b43_write16(dev, 0x03E2, b43_read16(dev, 0x03E2) | 0x8000);
609 backup[0] = b43_radio_read16(dev, 0x007A); 606 backup[0] = b43_radio_read16(dev, 0x007A);
@@ -635,9 +632,7 @@ static void b43_calc_nrssi_slope(struct b43_wldev *dev)
635 break; 632 break;
636 case 3: 633 case 3:
637 case 5: 634 case 5:
638 b43_phy_write(dev, 0x0801, 635 b43_phy_mask(dev, 0x0801, 0xFFBF);
639 b43_phy_read(dev, 0x0801)
640 & 0xFFBF);
641 break; 636 break;
642 } 637 }
643 b43_phy_set(dev, 0x0060, 0x0040); 638 b43_phy_set(dev, 0x0060, 0x0040);
@@ -717,10 +712,8 @@ static void b43_calc_nrssi_slope(struct b43_wldev *dev)
717 b43_phy_write(dev, B43_PHY_G_LO_CONTROL, backup[13]); 712 b43_phy_write(dev, B43_PHY_G_LO_CONTROL, backup[13]);
718 } 713 }
719 if (phy->rev >= 2) { 714 if (phy->rev >= 2) {
720 b43_phy_write(dev, 0x0812, 715 b43_phy_mask(dev, 0x0812, 0xFFCF);
721 b43_phy_read(dev, 0x0812) & 0xFFCF); 716 b43_phy_mask(dev, 0x0811, 0xFFCF);
722 b43_phy_write(dev, 0x0811,
723 b43_phy_read(dev, 0x0811) & 0xFFCF);
724 } 717 }
725 718
726 b43_radio_write16(dev, 0x007A, backup[0]); 719 b43_radio_write16(dev, 0x007A, backup[0]);
@@ -891,9 +884,7 @@ b43_radio_interference_mitigation_enable(struct b43_wldev *dev, int mode)
891 case B43_INTERFMODE_NONWLAN: 884 case B43_INTERFMODE_NONWLAN:
892 if (phy->rev != 1) { 885 if (phy->rev != 1) {
893 b43_phy_set(dev, 0x042B, 0x0800); 886 b43_phy_set(dev, 0x042B, 0x0800);
894 b43_phy_write(dev, B43_PHY_G_CRS, 887 b43_phy_mask(dev, B43_PHY_G_CRS, ~0x4000);
895 b43_phy_read(dev,
896 B43_PHY_G_CRS) & ~0x4000);
897 break; 888 break;
898 } 889 }
899 radio_stacksave(0x0078); 890 radio_stacksave(0x0078);
@@ -985,9 +976,7 @@ b43_radio_interference_mitigation_enable(struct b43_wldev *dev, int mode)
985 phy_stacksave(0x042B); 976 phy_stacksave(0x042B);
986 phy_stacksave(0x048C); 977 phy_stacksave(0x048C);
987 978
988 b43_phy_write(dev, B43_PHY_RADIO_BITFIELD, 979 b43_phy_mask(dev, B43_PHY_RADIO_BITFIELD, ~0x1000);
989 b43_phy_read(dev, B43_PHY_RADIO_BITFIELD)
990 & ~0x1000);
991 b43_phy_write(dev, B43_PHY_G_CRS, 980 b43_phy_write(dev, B43_PHY_G_CRS,
992 (b43_phy_read(dev, B43_PHY_G_CRS) 981 (b43_phy_read(dev, B43_PHY_G_CRS)
993 & 0xFFFC) | 0x0002); 982 & 0xFFFC) | 0x0002);
@@ -1041,8 +1030,7 @@ b43_radio_interference_mitigation_enable(struct b43_wldev *dev, int mode)
1041 & 0xFFF0) | 0x000B); 1030 & 0xFFF0) | 0x000B);
1042 1031
1043 if (phy->rev >= 3) { 1032 if (phy->rev >= 3) {
1044 b43_phy_write(dev, 0x048A, b43_phy_read(dev, 0x048A) 1033 b43_phy_mask(dev, 0x048A, ~0x8000);
1045 & ~0x8000);
1046 b43_phy_write(dev, 0x0415, (b43_phy_read(dev, 0x0415) 1034 b43_phy_write(dev, 0x0415, (b43_phy_read(dev, 0x0415)
1047 & 0x8000) | 0x36D8); 1035 & 0x8000) | 0x36D8);
1048 b43_phy_write(dev, 0x0416, (b43_phy_read(dev, 0x0416) 1036 b43_phy_write(dev, 0x0416, (b43_phy_read(dev, 0x0416)
@@ -1068,8 +1056,7 @@ b43_radio_interference_mitigation_enable(struct b43_wldev *dev, int mode)
1068 } else if (phy->rev >= 6) { 1056 } else if (phy->rev >= 6) {
1069 b43_ofdmtab_write16(dev, 0x1A00, 0x3, 0x007F); 1057 b43_ofdmtab_write16(dev, 0x1A00, 0x3, 0x007F);
1070 b43_ofdmtab_write16(dev, 0x1A00, 0x2, 0x007F); 1058 b43_ofdmtab_write16(dev, 0x1A00, 0x2, 0x007F);
1071 b43_phy_write(dev, 0x04AD, b43_phy_read(dev, 0x04AD) 1059 b43_phy_mask(dev, 0x04AD, 0x00FF);
1072 & 0x00FF);
1073 } 1060 }
1074 b43_calc_nrssi_slope(dev); 1061 b43_calc_nrssi_slope(dev);
1075 break; 1062 break;
@@ -1088,19 +1075,16 @@ b43_radio_interference_mitigation_disable(struct b43_wldev *dev, int mode)
1088 switch (mode) { 1075 switch (mode) {
1089 case B43_INTERFMODE_NONWLAN: 1076 case B43_INTERFMODE_NONWLAN:
1090 if (phy->rev != 1) { 1077 if (phy->rev != 1) {
1091 b43_phy_write(dev, 0x042B, 1078 b43_phy_mask(dev, 0x042B, ~0x0800);
1092 b43_phy_read(dev, 0x042B) & ~0x0800);
1093 b43_phy_set(dev, B43_PHY_G_CRS, 0x4000); 1079 b43_phy_set(dev, B43_PHY_G_CRS, 0x4000);
1094 break; 1080 break;
1095 } 1081 }
1096 radio_stackrestore(0x0078); 1082 radio_stackrestore(0x0078);
1097 b43_calc_nrssi_threshold(dev); 1083 b43_calc_nrssi_threshold(dev);
1098 phy_stackrestore(0x0406); 1084 phy_stackrestore(0x0406);
1099 b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) & ~0x0800); 1085 b43_phy_mask(dev, 0x042B, ~0x0800);
1100 if (!dev->bad_frames_preempt) { 1086 if (!dev->bad_frames_preempt) {
1101 b43_phy_write(dev, B43_PHY_RADIO_BITFIELD, 1087 b43_phy_mask(dev, B43_PHY_RADIO_BITFIELD, ~(1 << 11));
1102 b43_phy_read(dev, B43_PHY_RADIO_BITFIELD)
1103 & ~(1 << 11));
1104 } 1088 }
1105 b43_phy_set(dev, B43_PHY_G_CRS, 0x4000); 1089 b43_phy_set(dev, B43_PHY_G_CRS, 0x4000);
1106 phy_stackrestore(0x04A0); 1090 phy_stackrestore(0x04A0);
@@ -1371,14 +1355,9 @@ static u16 b43_radio_init2050(struct b43_wldev *dev)
1371 sav.phy_classctl = b43_phy_read(dev, B43_PHY_CLASSCTL); 1355 sav.phy_classctl = b43_phy_read(dev, B43_PHY_CLASSCTL);
1372 1356
1373 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0003); 1357 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0003);
1374 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, 1358 b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFC);
1375 b43_phy_read(dev, B43_PHY_ANALOGOVERVAL) 1359 b43_phy_mask(dev, B43_PHY_CRS0, 0x7FFF);
1376 & 0xFFFC); 1360 b43_phy_mask(dev, B43_PHY_CLASSCTL, 0xFFFC);
1377 b43_phy_write(dev, B43_PHY_CRS0, b43_phy_read(dev, B43_PHY_CRS0)
1378 & 0x7FFF);
1379 b43_phy_write(dev, B43_PHY_CLASSCTL,
1380 b43_phy_read(dev, B43_PHY_CLASSCTL)
1381 & 0xFFFC);
1382 if (has_loopback_gain(phy)) { 1361 if (has_loopback_gain(phy)) {
1383 sav.phy_lo_mask = b43_phy_read(dev, B43_PHY_LO_MASK); 1362 sav.phy_lo_mask = b43_phy_read(dev, B43_PHY_LO_MASK);
1384 sav.phy_lo_ctl = b43_phy_read(dev, B43_PHY_LO_CTL); 1363 sav.phy_lo_ctl = b43_phy_read(dev, B43_PHY_LO_CTL);
@@ -1399,8 +1378,7 @@ static u16 b43_radio_init2050(struct b43_wldev *dev)
1399 b43_write16(dev, 0x3E2, b43_read16(dev, 0x3E2) | 0x8000); 1378 b43_write16(dev, 0x3E2, b43_read16(dev, 0x3E2) | 0x8000);
1400 1379
1401 sav.phy_syncctl = b43_phy_read(dev, B43_PHY_SYNCCTL); 1380 sav.phy_syncctl = b43_phy_read(dev, B43_PHY_SYNCCTL);
1402 b43_phy_write(dev, B43_PHY_SYNCCTL, b43_phy_read(dev, B43_PHY_SYNCCTL) 1381 b43_phy_mask(dev, B43_PHY_SYNCCTL, 0xFF7F);
1403 & 0xFF7F);
1404 sav.reg_3E6 = b43_read16(dev, 0x3E6); 1382 sav.reg_3E6 = b43_read16(dev, 0x3E6);
1405 sav.reg_3F4 = b43_read16(dev, 0x3F4); 1383 sav.reg_3F4 = b43_read16(dev, 0x3F4);
1406 1384
@@ -1799,8 +1777,7 @@ static void b43_phy_initb6(struct b43_wldev *dev)
1799 1777
1800 if (phy->analog == 4) { 1778 if (phy->analog == 4) {
1801 b43_write16(dev, 0x3E4, 9); 1779 b43_write16(dev, 0x3E4, 9);
1802 b43_phy_write(dev, 0x61, b43_phy_read(dev, 0x61) 1780 b43_phy_mask(dev, 0x61, 0x0FFF);
1803 & 0x0FFF);
1804 } else { 1781 } else {
1805 b43_phy_write(dev, 0x0002, (b43_phy_read(dev, 0x0002) & 0xFFC0) 1782 b43_phy_write(dev, 0x0002, (b43_phy_read(dev, 0x0002) & 0xFFC0)
1806 | 0x0004); 1783 | 0x0004);
@@ -1845,24 +1822,17 @@ static void b43_calc_loopback_gain(struct b43_wldev *dev)
1845 backup_radio[1] = b43_radio_read16(dev, 0x43); 1822 backup_radio[1] = b43_radio_read16(dev, 0x43);
1846 backup_radio[2] = b43_radio_read16(dev, 0x7A); 1823 backup_radio[2] = b43_radio_read16(dev, 0x7A);
1847 1824
1848 b43_phy_write(dev, B43_PHY_CRS0, 1825 b43_phy_mask(dev, B43_PHY_CRS0, 0x3FFF);
1849 b43_phy_read(dev, B43_PHY_CRS0) & 0x3FFF);
1850 b43_phy_set(dev, B43_PHY_CCKBBANDCFG, 0x8000); 1826 b43_phy_set(dev, B43_PHY_CCKBBANDCFG, 0x8000);
1851 b43_phy_set(dev, B43_PHY_RFOVER, 0x0002); 1827 b43_phy_set(dev, B43_PHY_RFOVER, 0x0002);
1852 b43_phy_write(dev, B43_PHY_RFOVERVAL, 1828 b43_phy_mask(dev, B43_PHY_RFOVERVAL, 0xFFFD);
1853 b43_phy_read(dev, B43_PHY_RFOVERVAL) & 0xFFFD);
1854 b43_phy_set(dev, B43_PHY_RFOVER, 0x0001); 1829 b43_phy_set(dev, B43_PHY_RFOVER, 0x0001);
1855 b43_phy_write(dev, B43_PHY_RFOVERVAL, 1830 b43_phy_mask(dev, B43_PHY_RFOVERVAL, 0xFFFE);
1856 b43_phy_read(dev, B43_PHY_RFOVERVAL) & 0xFFFE);
1857 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */ 1831 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
1858 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0001); 1832 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0001);
1859 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, 1833 b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFE);
1860 b43_phy_read(dev,
1861 B43_PHY_ANALOGOVERVAL) & 0xFFFE);
1862 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0002); 1834 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0002);
1863 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, 1835 b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFD);
1864 b43_phy_read(dev,
1865 B43_PHY_ANALOGOVERVAL) & 0xFFFD);
1866 } 1836 }
1867 b43_phy_set(dev, B43_PHY_RFOVER, 0x000C); 1837 b43_phy_set(dev, B43_PHY_RFOVER, 0x000C);
1868 b43_phy_set(dev, B43_PHY_RFOVERVAL, 0x000C); 1838 b43_phy_set(dev, B43_PHY_RFOVERVAL, 0x000C);
@@ -1878,9 +1848,7 @@ static void b43_calc_loopback_gain(struct b43_wldev *dev)
1878 b43_phy_set(dev, B43_PHY_CCK(0x0A), 0x2000); 1848 b43_phy_set(dev, B43_PHY_CCK(0x0A), 0x2000);
1879 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */ 1849 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
1880 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0004); 1850 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0004);
1881 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, 1851 b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFB);
1882 b43_phy_read(dev,
1883 B43_PHY_ANALOGOVERVAL) & 0xFFFB);
1884 } 1852 }
1885 b43_phy_write(dev, B43_PHY_CCK(0x03), 1853 b43_phy_write(dev, B43_PHY_CCK(0x03),
1886 (b43_phy_read(dev, B43_PHY_CCK(0x03)) 1854 (b43_phy_read(dev, B43_PHY_CCK(0x03))
@@ -1909,8 +1877,7 @@ static void b43_calc_loopback_gain(struct b43_wldev *dev)
1909 & 0xC0FF) | 0x800); 1877 & 0xC0FF) | 0x800);
1910 1878
1911 b43_phy_set(dev, B43_PHY_RFOVER, 0x0100); 1879 b43_phy_set(dev, B43_PHY_RFOVER, 0x0100);
1912 b43_phy_write(dev, B43_PHY_RFOVERVAL, 1880 b43_phy_mask(dev, B43_PHY_RFOVERVAL, 0xCFFF);
1913 b43_phy_read(dev, B43_PHY_RFOVERVAL) & 0xCFFF);
1914 1881
1915 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_EXTLNA) { 1882 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_EXTLNA) {
1916 if (phy->rev >= 7) { 1883 if (phy->rev >= 7) {
@@ -2002,7 +1969,7 @@ static void b43_hardware_pctl_early_init(struct b43_wldev *dev)
2002 return; 1969 return;
2003 } 1970 }
2004 1971
2005 b43_phy_write(dev, 0x0036, b43_phy_read(dev, 0x0036) & 0xFEFF); 1972 b43_phy_mask(dev, 0x0036, 0xFEFF);
2006 b43_phy_write(dev, 0x002F, 0x0202); 1973 b43_phy_write(dev, 0x002F, 0x0202);
2007 b43_phy_set(dev, 0x047C, 0x0002); 1974 b43_phy_set(dev, 0x047C, 0x0002);
2008 b43_phy_set(dev, 0x047A, 0xF000); 1975 b43_phy_set(dev, 0x047A, 0xF000);
@@ -2017,10 +1984,8 @@ static void b43_hardware_pctl_early_init(struct b43_wldev *dev)
2017 } else { 1984 } else {
2018 b43_phy_set(dev, 0x0036, 0x0200); 1985 b43_phy_set(dev, 0x0036, 0x0200);
2019 b43_phy_set(dev, 0x0036, 0x0400); 1986 b43_phy_set(dev, 0x0036, 0x0400);
2020 b43_phy_write(dev, 0x005D, b43_phy_read(dev, 0x005D) 1987 b43_phy_mask(dev, 0x005D, 0x7FFF);
2021 & 0x7FFF); 1988 b43_phy_mask(dev, 0x004F, 0xFFFE);
2022 b43_phy_write(dev, 0x004F, b43_phy_read(dev, 0x004F)
2023 & 0xFFFE);
2024 b43_phy_write(dev, 0x004E, (b43_phy_read(dev, 0x004E) 1989 b43_phy_write(dev, 0x004E, (b43_phy_read(dev, 0x004E)
2025 & 0xFFC0) | 0x0010); 1990 & 0xFFC0) | 0x0010);
2026 b43_phy_write(dev, 0x002E, 0xC07F); 1991 b43_phy_write(dev, 0x002E, 0xC07F);
@@ -2047,15 +2012,13 @@ static void b43_hardware_pctl_init_gphy(struct b43_wldev *dev)
2047 | (gphy->tgt_idle_tssi - gphy->cur_idle_tssi)); 2012 | (gphy->tgt_idle_tssi - gphy->cur_idle_tssi));
2048 b43_gphy_tssi_power_lt_init(dev); 2013 b43_gphy_tssi_power_lt_init(dev);
2049 b43_gphy_gain_lt_init(dev); 2014 b43_gphy_gain_lt_init(dev);
2050 b43_phy_write(dev, 0x0060, b43_phy_read(dev, 0x0060) & 0xFFBF); 2015 b43_phy_mask(dev, 0x0060, 0xFFBF);
2051 b43_phy_write(dev, 0x0014, 0x0000); 2016 b43_phy_write(dev, 0x0014, 0x0000);
2052 2017
2053 B43_WARN_ON(phy->rev < 6); 2018 B43_WARN_ON(phy->rev < 6);
2054 b43_phy_set(dev, 0x0478, 0x0800); 2019 b43_phy_set(dev, 0x0478, 0x0800);
2055 b43_phy_write(dev, 0x0478, b43_phy_read(dev, 0x0478) 2020 b43_phy_mask(dev, 0x0478, 0xFEFF);
2056 & 0xFEFF); 2021 b43_phy_mask(dev, 0x0801, 0xFFBF);
2057 b43_phy_write(dev, 0x0801, b43_phy_read(dev, 0x0801)
2058 & 0xFFBF);
2059 2022
2060 b43_gphy_dc_lt_init(dev, 1); 2023 b43_gphy_dc_lt_init(dev, 1);
2061 2024
@@ -2245,11 +2208,8 @@ static void b43_phy_initg(struct b43_wldev *dev)
2245 but OFDM is legal everywhere */ 2208 but OFDM is legal everywhere */
2246 if ((dev->dev->bus->chip_id == 0x4306 2209 if ((dev->dev->bus->chip_id == 0x4306
2247 && dev->dev->bus->chip_package == 2) || 0) { 2210 && dev->dev->bus->chip_package == 2) || 0) {
2248 b43_phy_write(dev, B43_PHY_CRS0, b43_phy_read(dev, B43_PHY_CRS0) 2211 b43_phy_mask(dev, B43_PHY_CRS0, 0xBFFF);
2249 & 0xBFFF); 2212 b43_phy_mask(dev, B43_PHY_OFDM(0xC3), 0x7FFF);
2250 b43_phy_write(dev, B43_PHY_OFDM(0xC3),
2251 b43_phy_read(dev, B43_PHY_OFDM(0xC3))
2252 & 0x7FFF);
2253 } 2213 }
2254} 2214}
2255 2215
@@ -2451,9 +2411,8 @@ static u8 b43_gphy_aci_scan(struct b43_wldev *dev)
2451 2411
2452 b43_phy_lock(dev); 2412 b43_phy_lock(dev);
2453 b43_radio_lock(dev); 2413 b43_radio_lock(dev);
2454 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) & 0xFFFC); 2414 b43_phy_mask(dev, 0x0802, 0xFFFC);
2455 b43_phy_write(dev, B43_PHY_G_CRS, 2415 b43_phy_mask(dev, B43_PHY_G_CRS, 0x7FFF);
2456 b43_phy_read(dev, B43_PHY_G_CRS) & 0x7FFF);
2457 b43_set_all_gains(dev, 3, 8, 1); 2416 b43_set_all_gains(dev, 3, 8, 1);
2458 2417
2459 start = (channel - 5 > 0) ? channel - 5 : 1; 2418 start = (channel - 5 > 0) ? channel - 5 : 1;
@@ -2466,7 +2425,7 @@ static u8 b43_gphy_aci_scan(struct b43_wldev *dev)
2466 b43_switch_channel(dev, channel); 2425 b43_switch_channel(dev, channel);
2467 b43_phy_write(dev, 0x0802, 2426 b43_phy_write(dev, 0x0802,
2468 (b43_phy_read(dev, 0x0802) & 0xFFFC) | 0x0003); 2427 (b43_phy_read(dev, 0x0802) & 0xFFFC) | 0x0003);
2469 b43_phy_write(dev, 0x0403, b43_phy_read(dev, 0x0403) & 0xFFF8); 2428 b43_phy_mask(dev, 0x0403, 0xFFF8);
2470 b43_phy_set(dev, B43_PHY_G_CRS, 0x8000); 2429 b43_phy_set(dev, B43_PHY_G_CRS, 0x8000);
2471 b43_set_original_gains(dev); 2430 b43_set_original_gains(dev);
2472 for (i = 0; i < 13; i++) { 2431 for (i = 0; i < 13; i++) {