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-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_eeprom.c53
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_eeprom.h3
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_phy.h5
3 files changed, 50 insertions, 11 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
index 4d902657c131..c5f3c430c985 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
@@ -131,8 +131,9 @@ static const struct ar9300_eeprom ar9300_default = {
131 .thresh62 = 28, 131 .thresh62 = 28,
132 .papdRateMaskHt20 = LE32(0x0cf0e0e0), 132 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
133 .papdRateMaskHt40 = LE32(0x6cf0e0e0), 133 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
134 .xlna_bias_strength = 0,
134 .futureModal = { 135 .futureModal = {
135 0, 0, 0, 0, 0, 0, 0, 0, 136 0, 0, 0, 0, 0, 0, 0,
136 }, 137 },
137 }, 138 },
138 .base_ext1 = { 139 .base_ext1 = {
@@ -331,8 +332,9 @@ static const struct ar9300_eeprom ar9300_default = {
331 .thresh62 = 28, 332 .thresh62 = 28,
332 .papdRateMaskHt20 = LE32(0x0c80c080), 333 .papdRateMaskHt20 = LE32(0x0c80c080),
333 .papdRateMaskHt40 = LE32(0x0080c080), 334 .papdRateMaskHt40 = LE32(0x0080c080),
335 .xlna_bias_strength = 0,
334 .futureModal = { 336 .futureModal = {
335 0, 0, 0, 0, 0, 0, 0, 0, 337 0, 0, 0, 0, 0, 0, 0,
336 }, 338 },
337 }, 339 },
338 .base_ext2 = { 340 .base_ext2 = {
@@ -704,8 +706,9 @@ static const struct ar9300_eeprom ar9300_x113 = {
704 .thresh62 = 28, 706 .thresh62 = 28,
705 .papdRateMaskHt20 = LE32(0x0c80c080), 707 .papdRateMaskHt20 = LE32(0x0c80c080),
706 .papdRateMaskHt40 = LE32(0x0080c080), 708 .papdRateMaskHt40 = LE32(0x0080c080),
709 .xlna_bias_strength = 0,
707 .futureModal = { 710 .futureModal = {
708 0, 0, 0, 0, 0, 0, 0, 0, 711 0, 0, 0, 0, 0, 0, 0,
709 }, 712 },
710 }, 713 },
711 .base_ext1 = { 714 .base_ext1 = {
@@ -904,8 +907,9 @@ static const struct ar9300_eeprom ar9300_x113 = {
904 .thresh62 = 28, 907 .thresh62 = 28,
905 .papdRateMaskHt20 = LE32(0x0cf0e0e0), 908 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
906 .papdRateMaskHt40 = LE32(0x6cf0e0e0), 909 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
910 .xlna_bias_strength = 0,
907 .futureModal = { 911 .futureModal = {
908 0, 0, 0, 0, 0, 0, 0, 0, 912 0, 0, 0, 0, 0, 0, 0,
909 }, 913 },
910 }, 914 },
911 .base_ext2 = { 915 .base_ext2 = {
@@ -1278,8 +1282,9 @@ static const struct ar9300_eeprom ar9300_h112 = {
1278 .thresh62 = 28, 1282 .thresh62 = 28,
1279 .papdRateMaskHt20 = LE32(0x0c80c080), 1283 .papdRateMaskHt20 = LE32(0x0c80c080),
1280 .papdRateMaskHt40 = LE32(0x0080c080), 1284 .papdRateMaskHt40 = LE32(0x0080c080),
1285 .xlna_bias_strength = 0,
1281 .futureModal = { 1286 .futureModal = {
1282 0, 0, 0, 0, 0, 0, 0, 0, 1287 0, 0, 0, 0, 0, 0, 0,
1283 }, 1288 },
1284 }, 1289 },
1285 .base_ext1 = { 1290 .base_ext1 = {
@@ -1478,8 +1483,9 @@ static const struct ar9300_eeprom ar9300_h112 = {
1478 .thresh62 = 28, 1483 .thresh62 = 28,
1479 .papdRateMaskHt20 = LE32(0x0cf0e0e0), 1484 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
1480 .papdRateMaskHt40 = LE32(0x6cf0e0e0), 1485 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
1486 .xlna_bias_strength = 0,
1481 .futureModal = { 1487 .futureModal = {
1482 0, 0, 0, 0, 0, 0, 0, 0, 1488 0, 0, 0, 0, 0, 0, 0,
1483 }, 1489 },
1484 }, 1490 },
1485 .base_ext2 = { 1491 .base_ext2 = {
@@ -1852,8 +1858,9 @@ static const struct ar9300_eeprom ar9300_x112 = {
1852 .thresh62 = 28, 1858 .thresh62 = 28,
1853 .papdRateMaskHt20 = LE32(0x0c80c080), 1859 .papdRateMaskHt20 = LE32(0x0c80c080),
1854 .papdRateMaskHt40 = LE32(0x0080c080), 1860 .papdRateMaskHt40 = LE32(0x0080c080),
1861 .xlna_bias_strength = 0,
1855 .futureModal = { 1862 .futureModal = {
1856 0, 0, 0, 0, 0, 0, 0, 0, 1863 0, 0, 0, 0, 0, 0, 0,
1857 }, 1864 },
1858 }, 1865 },
1859 .base_ext1 = { 1866 .base_ext1 = {
@@ -2052,8 +2059,9 @@ static const struct ar9300_eeprom ar9300_x112 = {
2052 .thresh62 = 28, 2059 .thresh62 = 28,
2053 .papdRateMaskHt20 = LE32(0x0cf0e0e0), 2060 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2054 .papdRateMaskHt40 = LE32(0x6cf0e0e0), 2061 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2062 .xlna_bias_strength = 0,
2055 .futureModal = { 2063 .futureModal = {
2056 0, 0, 0, 0, 0, 0, 0, 0, 2064 0, 0, 0, 0, 0, 0, 0,
2057 }, 2065 },
2058 }, 2066 },
2059 .base_ext2 = { 2067 .base_ext2 = {
@@ -2425,8 +2433,9 @@ static const struct ar9300_eeprom ar9300_h116 = {
2425 .thresh62 = 28, 2433 .thresh62 = 28,
2426 .papdRateMaskHt20 = LE32(0x0c80C080), 2434 .papdRateMaskHt20 = LE32(0x0c80C080),
2427 .papdRateMaskHt40 = LE32(0x0080C080), 2435 .papdRateMaskHt40 = LE32(0x0080C080),
2436 .xlna_bias_strength = 0,
2428 .futureModal = { 2437 .futureModal = {
2429 0, 0, 0, 0, 0, 0, 0, 0, 2438 0, 0, 0, 0, 0, 0, 0,
2430 }, 2439 },
2431 }, 2440 },
2432 .base_ext1 = { 2441 .base_ext1 = {
@@ -2625,8 +2634,9 @@ static const struct ar9300_eeprom ar9300_h116 = {
2625 .thresh62 = 28, 2634 .thresh62 = 28,
2626 .papdRateMaskHt20 = LE32(0x0cf0e0e0), 2635 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2627 .papdRateMaskHt40 = LE32(0x6cf0e0e0), 2636 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2637 .xlna_bias_strength = 0,
2628 .futureModal = { 2638 .futureModal = {
2629 0, 0, 0, 0, 0, 0, 0, 0, 2639 0, 0, 0, 0, 0, 0, 0,
2630 }, 2640 },
2631 }, 2641 },
2632 .base_ext2 = { 2642 .base_ext2 = {
@@ -3942,6 +3952,28 @@ static void ar9003_hw_xpa_timing_control_apply(struct ath_hw *ah, bool is2ghz)
3942 AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON, xpa_ctl); 3952 AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON, xpa_ctl);
3943} 3953}
3944 3954
3955static void ar9003_hw_xlna_bias_strength_apply(struct ath_hw *ah, bool is2ghz)
3956{
3957 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3958 u8 bias;
3959
3960 if (!(eep->baseEepHeader.featureEnable & 0x40))
3961 return;
3962
3963 if (!AR_SREV_9300(ah))
3964 return;
3965
3966 bias = ar9003_modal_header(ah, is2ghz)->xlna_bias_strength;
3967 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS,
3968 bias & 0x3);
3969 bias >>= 2;
3970 REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS,
3971 bias & 0x3);
3972 bias >>= 2;
3973 REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS,
3974 bias & 0x3);
3975}
3976
3945static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah, 3977static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
3946 struct ath9k_channel *chan) 3978 struct ath9k_channel *chan)
3947{ 3979{
@@ -3950,6 +3982,7 @@ static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
3950 ar9003_hw_xpa_bias_level_apply(ah, is2ghz); 3982 ar9003_hw_xpa_bias_level_apply(ah, is2ghz);
3951 ar9003_hw_ant_ctrl_apply(ah, is2ghz); 3983 ar9003_hw_ant_ctrl_apply(ah, is2ghz);
3952 ar9003_hw_drive_strength_apply(ah); 3984 ar9003_hw_drive_strength_apply(ah);
3985 ar9003_hw_xlna_bias_strength_apply(ah, is2ghz);
3953 ar9003_hw_atten_apply(ah, chan); 3986 ar9003_hw_atten_apply(ah, chan);
3954 ar9003_hw_quick_drop_apply(ah, chan->channel); 3987 ar9003_hw_quick_drop_apply(ah, chan->channel);
3955 if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah) && !AR_SREV_9550(ah)) 3988 if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah) && !AR_SREV_9550(ah))
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
index 8396d150ce01..3a1ff55bceb9 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
@@ -231,7 +231,8 @@ struct ar9300_modal_eep_header {
231 __le32 papdRateMaskHt20; 231 __le32 papdRateMaskHt20;
232 __le32 papdRateMaskHt40; 232 __le32 papdRateMaskHt40;
233 __le16 switchcomspdt; 233 __le16 switchcomspdt;
234 u8 futureModal[8]; 234 u8 xlna_bias_strength;
235 u8 futureModal[7];
235} __packed; 236} __packed;
236 237
237struct ar9300_cal_data_per_freq_op_loop { 238struct ar9300_cal_data_per_freq_op_loop {
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.h b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
index 751c83b21493..7bfbaf065a43 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
@@ -633,6 +633,8 @@
633#define AR_PHY_65NM_CH0_BIAS2 0x160c4 633#define AR_PHY_65NM_CH0_BIAS2 0x160c4
634#define AR_PHY_65NM_CH0_BIAS4 0x160cc 634#define AR_PHY_65NM_CH0_BIAS4 0x160cc
635#define AR_PHY_65NM_CH0_RXTX4 0x1610c 635#define AR_PHY_65NM_CH0_RXTX4 0x1610c
636#define AR_PHY_65NM_CH1_RXTX4 0x1650c
637#define AR_PHY_65NM_CH2_RXTX4 0x1690c
636 638
637#define AR_CH0_TOP (AR_SREV_9300(ah) ? 0x16288 : \ 639#define AR_CH0_TOP (AR_SREV_9300(ah) ? 0x16288 : \
638 ((AR_SREV_9462(ah) ? 0x1628c : 0x16280))) 640 ((AR_SREV_9462(ah) ? 0x1628c : 0x16280)))
@@ -876,6 +878,9 @@
876#define AR_PHY_65NM_CH0_RXTX4_THERM_ON 0x10000000 878#define AR_PHY_65NM_CH0_RXTX4_THERM_ON 0x10000000
877#define AR_PHY_65NM_CH0_RXTX4_THERM_ON_S 28 879#define AR_PHY_65NM_CH0_RXTX4_THERM_ON_S 28
878 880
881#define AR_PHY_65NM_RXTX4_XLNA_BIAS 0xC0000000
882#define AR_PHY_65NM_RXTX4_XLNA_BIAS_S 30
883
879/* 884/*
880 * Channel 1 Register Map 885 * Channel 1 Register Map
881 */ 886 */