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-rw-r--r--drivers/net/wireless/ath9k/ath9k.h1
-rw-r--r--drivers/net/wireless/ath9k/beacon.c97
-rw-r--r--drivers/net/wireless/ath9k/calib.c98
-rw-r--r--drivers/net/wireless/ath9k/core.h356
-rw-r--r--drivers/net/wireless/ath9k/debug.c102
-rw-r--r--drivers/net/wireless/ath9k/eeprom.c1826
-rw-r--r--drivers/net/wireless/ath9k/hw.c115
-rw-r--r--drivers/net/wireless/ath9k/hw.h140
-rw-r--r--drivers/net/wireless/ath9k/initvals.h1363
-rw-r--r--drivers/net/wireless/ath9k/mac.c5
-rw-r--r--drivers/net/wireless/ath9k/main.c80
-rw-r--r--drivers/net/wireless/ath9k/phy.h5
-rw-r--r--drivers/net/wireless/ath9k/rc.c18
-rw-r--r--drivers/net/wireless/ath9k/recv.c121
-rw-r--r--drivers/net/wireless/ath9k/reg.h109
-rw-r--r--drivers/net/wireless/ath9k/xmit.c141
16 files changed, 3831 insertions, 746 deletions
diff --git a/drivers/net/wireless/ath9k/ath9k.h b/drivers/net/wireless/ath9k/ath9k.h
index 9520aa0898e3..d27813502953 100644
--- a/drivers/net/wireless/ath9k/ath9k.h
+++ b/drivers/net/wireless/ath9k/ath9k.h
@@ -26,6 +26,7 @@
26#define AR9160_DEVID_PCI 0x0027 26#define AR9160_DEVID_PCI 0x0027
27#define AR9280_DEVID_PCI 0x0029 27#define AR9280_DEVID_PCI 0x0029
28#define AR9280_DEVID_PCIE 0x002a 28#define AR9280_DEVID_PCIE 0x002a
29#define AR9285_DEVID_PCIE 0x002b
29 30
30#define AR5416_AR9100_DEVID 0x000b 31#define AR5416_AR9100_DEVID 0x000b
31 32
diff --git a/drivers/net/wireless/ath9k/beacon.c b/drivers/net/wireless/ath9k/beacon.c
index 507299bf0136..3ab0b43aaf93 100644
--- a/drivers/net/wireless/ath9k/beacon.c
+++ b/drivers/net/wireless/ath9k/beacon.c
@@ -26,7 +26,7 @@ static int ath_beaconq_config(struct ath_softc *sc)
26 struct ath_hal *ah = sc->sc_ah; 26 struct ath_hal *ah = sc->sc_ah;
27 struct ath9k_tx_queue_info qi; 27 struct ath9k_tx_queue_info qi;
28 28
29 ath9k_hw_get_txq_props(ah, sc->sc_bhalq, &qi); 29 ath9k_hw_get_txq_props(ah, sc->beacon.beaconq, &qi);
30 if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP) { 30 if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP) {
31 /* Always burst out beacon and CAB traffic. */ 31 /* Always burst out beacon and CAB traffic. */
32 qi.tqi_aifs = 1; 32 qi.tqi_aifs = 1;
@@ -34,17 +34,17 @@ static int ath_beaconq_config(struct ath_softc *sc)
34 qi.tqi_cwmax = 0; 34 qi.tqi_cwmax = 0;
35 } else { 35 } else {
36 /* Adhoc mode; important thing is to use 2x cwmin. */ 36 /* Adhoc mode; important thing is to use 2x cwmin. */
37 qi.tqi_aifs = sc->sc_beacon_qi.tqi_aifs; 37 qi.tqi_aifs = sc->beacon.beacon_qi.tqi_aifs;
38 qi.tqi_cwmin = 2*sc->sc_beacon_qi.tqi_cwmin; 38 qi.tqi_cwmin = 2*sc->beacon.beacon_qi.tqi_cwmin;
39 qi.tqi_cwmax = sc->sc_beacon_qi.tqi_cwmax; 39 qi.tqi_cwmax = sc->beacon.beacon_qi.tqi_cwmax;
40 } 40 }
41 41
42 if (!ath9k_hw_set_txq_props(ah, sc->sc_bhalq, &qi)) { 42 if (!ath9k_hw_set_txq_props(ah, sc->beacon.beaconq, &qi)) {
43 DPRINTF(sc, ATH_DBG_FATAL, 43 DPRINTF(sc, ATH_DBG_FATAL,
44 "unable to update h/w beacon queue parameters\n"); 44 "unable to update h/w beacon queue parameters\n");
45 return 0; 45 return 0;
46 } else { 46 } else {
47 ath9k_hw_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ 47 ath9k_hw_resettxqueue(ah, sc->beacon.beaconq); /* push to h/w */
48 return 1; 48 return 1;
49 } 49 }
50} 50}
@@ -53,7 +53,7 @@ static void ath_bstuck_process(struct ath_softc *sc)
53{ 53{
54 DPRINTF(sc, ATH_DBG_BEACON, 54 DPRINTF(sc, ATH_DBG_BEACON,
55 "stuck beacon; resetting (bmiss count %u)\n", 55 "stuck beacon; resetting (bmiss count %u)\n",
56 sc->sc_bmisscount); 56 sc->beacon.bmisscnt);
57 ath_reset(sc, false); 57 ath_reset(sc, false);
58} 58}
59 59
@@ -96,7 +96,7 @@ static void ath_beacon_setup(struct ath_softc *sc,
96 * SWBA's 96 * SWBA's
97 * XXX assumes two antenna 97 * XXX assumes two antenna
98 */ 98 */
99 antenna = ((sc->ast_be_xmit / sc->sc_nbcnvaps) & 1 ? 2 : 1); 99 antenna = ((sc->beacon.ast_be_xmit / sc->sc_nbcnvaps) & 1 ? 2 : 1);
100 } 100 }
101 101
102 ds->ds_data = bf->bf_buf_addr; 102 ds->ds_data = bf->bf_buf_addr;
@@ -106,7 +106,7 @@ static void ath_beacon_setup(struct ath_softc *sc,
106 * XXX everything at min xmit rate 106 * XXX everything at min xmit rate
107 */ 107 */
108 rix = 0; 108 rix = 0;
109 rt = sc->hw_rate_table[sc->sc_curmode]; 109 rt = sc->cur_rate_table;
110 rate = rt->info[rix].ratecode; 110 rate = rt->info[rix].ratecode;
111 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT) 111 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
112 rate |= rt->info[rix].short_preamble; 112 rate |= rt->info[rix].short_preamble;
@@ -153,7 +153,7 @@ static struct ath_buf *ath_beacon_generate(struct ath_softc *sc, int if_id)
153 ASSERT(vif); 153 ASSERT(vif);
154 154
155 avp = (void *)vif->drv_priv; 155 avp = (void *)vif->drv_priv;
156 cabq = sc->sc_cabq; 156 cabq = sc->beacon.cabq;
157 157
158 if (avp->av_bcbuf == NULL) { 158 if (avp->av_bcbuf == NULL) {
159 DPRINTF(sc, ATH_DBG_BEACON, "avp=%p av_bcbuf=%p\n", 159 DPRINTF(sc, ATH_DBG_BEACON, "avp=%p av_bcbuf=%p\n",
@@ -167,6 +167,7 @@ static struct ath_buf *ath_beacon_generate(struct ath_softc *sc, int if_id)
167 pci_unmap_single(sc->pdev, bf->bf_dmacontext, 167 pci_unmap_single(sc->pdev, bf->bf_dmacontext,
168 skb->len, 168 skb->len,
169 PCI_DMA_TODEVICE); 169 PCI_DMA_TODEVICE);
170 dev_kfree_skb_any(skb);
170 } 171 }
171 172
172 skb = ieee80211_beacon_get(sc->hw, vif); 173 skb = ieee80211_beacon_get(sc->hw, vif);
@@ -181,9 +182,9 @@ static struct ath_buf *ath_beacon_generate(struct ath_softc *sc, int if_id)
181 * TX frames) 182 * TX frames)
182 */ 183 */
183 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 184 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
184 sc->seq_no += 0x10; 185 sc->tx.seq_no += 0x10;
185 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); 186 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
186 hdr->seq_ctrl |= cpu_to_le16(sc->seq_no); 187 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
187 } 188 }
188 189
189 bf->bf_buf_addr = bf->bf_dmacontext = 190 bf->bf_buf_addr = bf->bf_dmacontext =
@@ -269,10 +270,10 @@ static void ath_beacon_start_adhoc(struct ath_softc *sc, int if_id)
269 ath_beacon_setup(sc, avp, bf); 270 ath_beacon_setup(sc, avp, bf);
270 271
271 /* NB: caller is known to have already stopped tx dma */ 272 /* NB: caller is known to have already stopped tx dma */
272 ath9k_hw_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 273 ath9k_hw_puttxbuf(ah, sc->beacon.beaconq, bf->bf_daddr);
273 ath9k_hw_txstart(ah, sc->sc_bhalq); 274 ath9k_hw_txstart(ah, sc->beacon.beaconq);
274 DPRINTF(sc, ATH_DBG_BEACON, "TXDP%u = %llx (%p)\n", 275 DPRINTF(sc, ATH_DBG_BEACON, "TXDP%u = %llx (%p)\n",
275 sc->sc_bhalq, ito64(bf->bf_daddr), bf->bf_desc); 276 sc->beacon.beaconq, ito64(bf->bf_daddr), bf->bf_desc);
276} 277}
277 278
278int ath_beaconq_setup(struct ath_hal *ah) 279int ath_beaconq_setup(struct ath_hal *ah)
@@ -305,7 +306,7 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id)
305 if (!avp->av_bcbuf) { 306 if (!avp->av_bcbuf) {
306 /* Allocate beacon state for hostap/ibss. We know 307 /* Allocate beacon state for hostap/ibss. We know
307 * a buffer is available. */ 308 * a buffer is available. */
308 avp->av_bcbuf = list_first_entry(&sc->sc_bbuf, 309 avp->av_bcbuf = list_first_entry(&sc->beacon.bbuf,
309 struct ath_buf, list); 310 struct ath_buf, list);
310 list_del(&avp->av_bcbuf->list); 311 list_del(&avp->av_bcbuf->list);
311 312
@@ -318,13 +319,13 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id)
318 */ 319 */
319 avp->av_bslot = 0; 320 avp->av_bslot = 0;
320 for (slot = 0; slot < ATH_BCBUF; slot++) 321 for (slot = 0; slot < ATH_BCBUF; slot++)
321 if (sc->sc_bslot[slot] == ATH_IF_ID_ANY) { 322 if (sc->beacon.bslot[slot] == ATH_IF_ID_ANY) {
322 /* 323 /*
323 * XXX hack, space out slots to better 324 * XXX hack, space out slots to better
324 * deal with misses 325 * deal with misses
325 */ 326 */
326 if (slot+1 < ATH_BCBUF && 327 if (slot+1 < ATH_BCBUF &&
327 sc->sc_bslot[slot+1] == 328 sc->beacon.bslot[slot+1] ==
328 ATH_IF_ID_ANY) { 329 ATH_IF_ID_ANY) {
329 avp->av_bslot = slot+1; 330 avp->av_bslot = slot+1;
330 break; 331 break;
@@ -332,8 +333,8 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id)
332 avp->av_bslot = slot; 333 avp->av_bslot = slot;
333 /* NB: keep looking for a double slot */ 334 /* NB: keep looking for a double slot */
334 } 335 }
335 BUG_ON(sc->sc_bslot[avp->av_bslot] != ATH_IF_ID_ANY); 336 BUG_ON(sc->beacon.bslot[avp->av_bslot] != ATH_IF_ID_ANY);
336 sc->sc_bslot[avp->av_bslot] = if_id; 337 sc->beacon.bslot[avp->av_bslot] = if_id;
337 sc->sc_nbcnvaps++; 338 sc->sc_nbcnvaps++;
338 } 339 }
339 } 340 }
@@ -361,7 +362,7 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id)
361 } 362 }
362 363
363 tstamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp; 364 tstamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp;
364 sc->bc_tstamp = le64_to_cpu(tstamp); 365 sc->beacon.bc_tstamp = le64_to_cpu(tstamp);
365 366
366 /* 367 /*
367 * Calculate a TSF adjustment factor required for 368 * Calculate a TSF adjustment factor required for
@@ -421,7 +422,7 @@ void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp)
421 struct ath_buf *bf; 422 struct ath_buf *bf;
422 423
423 if (avp->av_bslot != -1) { 424 if (avp->av_bslot != -1) {
424 sc->sc_bslot[avp->av_bslot] = ATH_IF_ID_ANY; 425 sc->beacon.bslot[avp->av_bslot] = ATH_IF_ID_ANY;
425 sc->sc_nbcnvaps--; 426 sc->sc_nbcnvaps--;
426 } 427 }
427 428
@@ -434,7 +435,7 @@ void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp)
434 dev_kfree_skb_any(skb); 435 dev_kfree_skb_any(skb);
435 bf->bf_mpdu = NULL; 436 bf->bf_mpdu = NULL;
436 } 437 }
437 list_add_tail(&bf->list, &sc->sc_bbuf); 438 list_add_tail(&bf->list, &sc->beacon.bbuf);
438 439
439 avp->av_bcbuf = NULL; 440 avp->av_bcbuf = NULL;
440 } 441 }
@@ -468,18 +469,18 @@ void ath9k_beacon_tasklet(unsigned long data)
468 * 469 *
469 * FIXME: Clean up this mess !! 470 * FIXME: Clean up this mess !!
470 */ 471 */
471 if (ath9k_hw_numtxpending(ah, sc->sc_bhalq) != 0) { 472 if (ath9k_hw_numtxpending(ah, sc->beacon.beaconq) != 0) {
472 sc->sc_bmisscount++; 473 sc->beacon.bmisscnt++;
473 /* XXX: doth needs the chanchange IE countdown decremented. 474 /* XXX: doth needs the chanchange IE countdown decremented.
474 * We should consider adding a mac80211 call to indicate 475 * We should consider adding a mac80211 call to indicate
475 * a beacon miss so appropriate action could be taken 476 * a beacon miss so appropriate action could be taken
476 * (in that layer). 477 * (in that layer).
477 */ 478 */
478 if (sc->sc_bmisscount < BSTUCK_THRESH) { 479 if (sc->beacon.bmisscnt < BSTUCK_THRESH) {
479 if (sc->sc_flags & SC_OP_NO_RESET) { 480 if (sc->sc_flags & SC_OP_NO_RESET) {
480 DPRINTF(sc, ATH_DBG_BEACON, 481 DPRINTF(sc, ATH_DBG_BEACON,
481 "missed %u consecutive beacons\n", 482 "missed %u consecutive beacons\n",
482 sc->sc_bmisscount); 483 sc->beacon.bmisscnt);
483 if (show_cycles) { 484 if (show_cycles) {
484 /* 485 /*
485 * Display cycle counter stats from HW 486 * Display cycle counter stats from HW
@@ -498,11 +499,11 @@ void ath9k_beacon_tasklet(unsigned long data)
498 } else { 499 } else {
499 DPRINTF(sc, ATH_DBG_BEACON, 500 DPRINTF(sc, ATH_DBG_BEACON,
500 "missed %u consecutive beacons\n", 501 "missed %u consecutive beacons\n",
501 sc->sc_bmisscount); 502 sc->beacon.bmisscnt);
502 } 503 }
503 } else if (sc->sc_bmisscount >= BSTUCK_THRESH) { 504 } else if (sc->beacon.bmisscnt >= BSTUCK_THRESH) {
504 if (sc->sc_flags & SC_OP_NO_RESET) { 505 if (sc->sc_flags & SC_OP_NO_RESET) {
505 if (sc->sc_bmisscount == BSTUCK_THRESH) { 506 if (sc->beacon.bmisscnt == BSTUCK_THRESH) {
506 DPRINTF(sc, ATH_DBG_BEACON, 507 DPRINTF(sc, ATH_DBG_BEACON,
507 "beacon is officially " 508 "beacon is officially "
508 "stuck\n"); 509 "stuck\n");
@@ -516,17 +517,17 @@ void ath9k_beacon_tasklet(unsigned long data)
516 return; 517 return;
517 } 518 }
518 519
519 if (sc->sc_bmisscount != 0) { 520 if (sc->beacon.bmisscnt != 0) {
520 if (sc->sc_flags & SC_OP_NO_RESET) { 521 if (sc->sc_flags & SC_OP_NO_RESET) {
521 DPRINTF(sc, ATH_DBG_BEACON, 522 DPRINTF(sc, ATH_DBG_BEACON,
522 "resume beacon xmit after %u misses\n", 523 "resume beacon xmit after %u misses\n",
523 sc->sc_bmisscount); 524 sc->beacon.bmisscnt);
524 } else { 525 } else {
525 DPRINTF(sc, ATH_DBG_BEACON, 526 DPRINTF(sc, ATH_DBG_BEACON,
526 "resume beacon xmit after %u misses\n", 527 "resume beacon xmit after %u misses\n",
527 sc->sc_bmisscount); 528 sc->beacon.bmisscnt);
528 } 529 }
529 sc->sc_bmisscount = 0; 530 sc->beacon.bmisscnt = 0;
530 } 531 }
531 532
532 /* 533 /*
@@ -541,7 +542,7 @@ void ath9k_beacon_tasklet(unsigned long data)
541 tsf = ath9k_hw_gettsf64(ah); 542 tsf = ath9k_hw_gettsf64(ah);
542 tsftu = TSF_TO_TU(tsf>>32, tsf); 543 tsftu = TSF_TO_TU(tsf>>32, tsf);
543 slot = ((tsftu % intval) * ATH_BCBUF) / intval; 544 slot = ((tsftu % intval) * ATH_BCBUF) / intval;
544 if_id = sc->sc_bslot[(slot + 1) % ATH_BCBUF]; 545 if_id = sc->beacon.bslot[(slot + 1) % ATH_BCBUF];
545 546
546 DPRINTF(sc, ATH_DBG_BEACON, 547 DPRINTF(sc, ATH_DBG_BEACON,
547 "slot %d [tsf %llu tsftu %u intval %u] if_id %d\n", 548 "slot %d [tsf %llu tsftu %u intval %u] if_id %d\n",
@@ -573,12 +574,12 @@ void ath9k_beacon_tasklet(unsigned long data)
573 * set to ATH_BCBUF so this check is a noop. 574 * set to ATH_BCBUF so this check is a noop.
574 */ 575 */
575 /* XXX locking */ 576 /* XXX locking */
576 if (sc->sc_updateslot == UPDATE) { 577 if (sc->beacon.updateslot == UPDATE) {
577 sc->sc_updateslot = COMMIT; /* commit next beacon */ 578 sc->beacon.updateslot = COMMIT; /* commit next beacon */
578 sc->sc_slotupdate = slot; 579 sc->beacon.slotupdate = slot;
579 } else if (sc->sc_updateslot == COMMIT && sc->sc_slotupdate == slot) { 580 } else if (sc->beacon.updateslot == COMMIT && sc->beacon.slotupdate == slot) {
580 ath9k_hw_setslottime(sc->sc_ah, sc->sc_slottime); 581 ath9k_hw_setslottime(sc->sc_ah, sc->beacon.slottime);
581 sc->sc_updateslot = OK; 582 sc->beacon.updateslot = OK;
582 } 583 }
583 if (bfaddr != 0) { 584 if (bfaddr != 0) {
584 /* 585 /*
@@ -586,17 +587,17 @@ void ath9k_beacon_tasklet(unsigned long data)
586 * This should never fail since we check above that no frames 587 * This should never fail since we check above that no frames
587 * are still pending on the queue. 588 * are still pending on the queue.
588 */ 589 */
589 if (!ath9k_hw_stoptxdma(ah, sc->sc_bhalq)) { 590 if (!ath9k_hw_stoptxdma(ah, sc->beacon.beaconq)) {
590 DPRINTF(sc, ATH_DBG_FATAL, 591 DPRINTF(sc, ATH_DBG_FATAL,
591 "beacon queue %u did not stop?\n", sc->sc_bhalq); 592 "beacon queue %u did not stop?\n", sc->beacon.beaconq);
592 /* NB: the HAL still stops DMA, so proceed */ 593 /* NB: the HAL still stops DMA, so proceed */
593 } 594 }
594 595
595 /* NB: cabq traffic should already be queued and primed */ 596 /* NB: cabq traffic should already be queued and primed */
596 ath9k_hw_puttxbuf(ah, sc->sc_bhalq, bfaddr); 597 ath9k_hw_puttxbuf(ah, sc->beacon.beaconq, bfaddr);
597 ath9k_hw_txstart(ah, sc->sc_bhalq); 598 ath9k_hw_txstart(ah, sc->beacon.beaconq);
598 599
599 sc->ast_be_xmit += bc; /* XXX per-vap? */ 600 sc->beacon.ast_be_xmit += bc; /* XXX per-vap? */
600 } 601 }
601} 602}
602 603
@@ -643,7 +644,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
643 conf.bmiss_timeout = ATH_DEFAULT_BMISS_LIMIT * conf.beacon_interval; 644 conf.bmiss_timeout = ATH_DEFAULT_BMISS_LIMIT * conf.beacon_interval;
644 645
645 /* extract tstamp from last beacon and convert to TU */ 646 /* extract tstamp from last beacon and convert to TU */
646 nexttbtt = TSF_TO_TU(sc->bc_tstamp >> 32, sc->bc_tstamp); 647 nexttbtt = TSF_TO_TU(sc->beacon.bc_tstamp >> 32, sc->beacon.bc_tstamp);
647 648
648 /* XXX conditionalize multi-bss support? */ 649 /* XXX conditionalize multi-bss support? */
649 if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP) { 650 if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP) {
@@ -830,7 +831,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
830 ath_beaconq_config(sc); 831 ath_beaconq_config(sc);
831 } 832 }
832 ath9k_hw_beaconinit(ah, nexttbtt, intval); 833 ath9k_hw_beaconinit(ah, nexttbtt, intval);
833 sc->sc_bmisscount = 0; 834 sc->beacon.bmisscnt = 0;
834 ath9k_hw_set_interrupts(ah, sc->sc_imask); 835 ath9k_hw_set_interrupts(ah, sc->sc_imask);
835 /* 836 /*
836 * When using a self-linked beacon descriptor in 837 * When using a self-linked beacon descriptor in
diff --git a/drivers/net/wireless/ath9k/calib.c b/drivers/net/wireless/ath9k/calib.c
index 51c8a3ce4e60..3c7454fc51bd 100644
--- a/drivers/net/wireless/ath9k/calib.c
+++ b/drivers/net/wireless/ath9k/calib.c
@@ -818,6 +818,101 @@ bool ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan,
818 return true; 818 return true;
819} 819}
820 820
821static inline void ath9k_hw_9285_pa_cal(struct ath_hal *ah)
822{
823
824 u32 regVal;
825 int i, offset, offs_6_1, offs_0;
826 u32 ccomp_org, reg_field;
827 u32 regList[][2] = {
828 { 0x786c, 0 },
829 { 0x7854, 0 },
830 { 0x7820, 0 },
831 { 0x7824, 0 },
832 { 0x7868, 0 },
833 { 0x783c, 0 },
834 { 0x7838, 0 },
835 };
836
837 if (AR_SREV_9285_11(ah)) {
838 REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
839 udelay(10);
840 }
841
842 for (i = 0; i < ARRAY_SIZE(regList); i++)
843 regList[i][1] = REG_READ(ah, regList[i][0]);
844
845 regVal = REG_READ(ah, 0x7834);
846 regVal &= (~(0x1));
847 REG_WRITE(ah, 0x7834, regVal);
848 regVal = REG_READ(ah, 0x9808);
849 regVal |= (0x1 << 27);
850 REG_WRITE(ah, 0x9808, regVal);
851
852 REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
853 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
854 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
855 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
856 REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
857 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
858 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
859 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 1);
860 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0);
861 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
862 REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
863 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
864 ccomp_org = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP);
865 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, 7);
866
867 REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
868 udelay(30);
869 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, 0);
870 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 0);
871
872 for (i = 6; i > 0; i--) {
873 regVal = REG_READ(ah, 0x7834);
874 regVal |= (1 << (19 + i));
875 REG_WRITE(ah, 0x7834, regVal);
876 udelay(1);
877 regVal = REG_READ(ah, 0x7834);
878 regVal &= (~(0x1 << (19 + i)));
879 reg_field = MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9);
880 regVal |= (reg_field << (19 + i));
881 REG_WRITE(ah, 0x7834, regVal);
882 }
883
884 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 1);
885 udelay(1);
886 reg_field = MS(REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9);
887 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, reg_field);
888 offs_6_1 = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS);
889 offs_0 = MS(REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP);
890
891 offset = (offs_6_1<<1) | offs_0;
892 offset = offset - 0;
893 offs_6_1 = offset>>1;
894 offs_0 = offset & 1;
895
896 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1);
897 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0);
898
899 regVal = REG_READ(ah, 0x7834);
900 regVal |= 0x1;
901 REG_WRITE(ah, 0x7834, regVal);
902 regVal = REG_READ(ah, 0x9808);
903 regVal &= (~(0x1 << 27));
904 REG_WRITE(ah, 0x9808, regVal);
905
906 for (i = 0; i < ARRAY_SIZE(regList); i++)
907 REG_WRITE(ah, regList[i][0], regList[i][1]);
908
909 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, ccomp_org);
910
911 if (AR_SREV_9285_11(ah))
912 REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);
913
914}
915
821bool ath9k_hw_init_cal(struct ath_hal *ah, 916bool ath9k_hw_init_cal(struct ath_hal *ah,
822 struct ath9k_channel *chan) 917 struct ath9k_channel *chan)
823{ 918{
@@ -835,6 +930,9 @@ bool ath9k_hw_init_cal(struct ath_hal *ah,
835 return false; 930 return false;
836 } 931 }
837 932
933 if (AR_SREV_9285(ah) && AR_SREV_9285_11_OR_LATER(ah))
934 ath9k_hw_9285_pa_cal(ah);
935
838 REG_WRITE(ah, AR_PHY_AGC_CONTROL, 936 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
839 REG_READ(ah, AR_PHY_AGC_CONTROL) | 937 REG_READ(ah, AR_PHY_AGC_CONTROL) |
840 AR_PHY_AGC_CONTROL_NF); 938 AR_PHY_AGC_CONTROL_NF);
diff --git a/drivers/net/wireless/ath9k/core.h b/drivers/net/wireless/ath9k/core.h
index a500d1770534..e38f0331cfd5 100644
--- a/drivers/net/wireless/ath9k/core.h
+++ b/drivers/net/wireless/ath9k/core.h
@@ -61,7 +61,7 @@ struct ath_node;
61#define TSF_TO_TU(_h,_l) \ 61#define TSF_TO_TU(_h,_l) \
62 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10)) 62 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
63 63
64#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 64#define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i))
65 65
66static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 66static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
67 67
@@ -88,16 +88,66 @@ enum ATH_DEBUG {
88 88
89#ifdef CONFIG_ATH9K_DEBUG 89#ifdef CONFIG_ATH9K_DEBUG
90 90
91/**
92 * struct ath_interrupt_stats - Contains statistics about interrupts
93 * @total: Total no. of interrupts generated so far
94 * @rxok: RX with no errors
95 * @rxeol: RX with no more RXDESC available
96 * @rxorn: RX FIFO overrun
97 * @txok: TX completed at the requested rate
98 * @txurn: TX FIFO underrun
99 * @mib: MIB regs reaching its threshold
100 * @rxphyerr: RX with phy errors
101 * @rx_keycache_miss: RX with key cache misses
102 * @swba: Software Beacon Alert
103 * @bmiss: Beacon Miss
104 * @bnr: Beacon Not Ready
105 * @cst: Carrier Sense TImeout
106 * @gtt: Global TX Timeout
107 * @tim: RX beacon TIM occurrence
108 * @cabend: RX End of CAB traffic
109 * @dtimsync: DTIM sync lossage
110 * @dtim: RX Beacon with DTIM
111 */
112struct ath_interrupt_stats {
113 u32 total;
114 u32 rxok;
115 u32 rxeol;
116 u32 rxorn;
117 u32 txok;
118 u32 txeol;
119 u32 txurn;
120 u32 mib;
121 u32 rxphyerr;
122 u32 rx_keycache_miss;
123 u32 swba;
124 u32 bmiss;
125 u32 bnr;
126 u32 cst;
127 u32 gtt;
128 u32 tim;
129 u32 cabend;
130 u32 dtimsync;
131 u32 dtim;
132};
133
134struct ath_stats {
135 struct ath_interrupt_stats istats;
136};
137
91struct ath9k_debug { 138struct ath9k_debug {
92 int debug_mask; 139 int debug_mask;
93 struct dentry *debugfs_root; 140 struct dentry *debugfs_root;
94 struct dentry *debugfs_phy; 141 struct dentry *debugfs_phy;
95 struct dentry *debugfs_dma; 142 struct dentry *debugfs_dma;
143 struct dentry *debugfs_interrupt;
144 struct ath_stats stats;
96}; 145};
97 146
98void DPRINTF(struct ath_softc *sc, int dbg_mask, const char *fmt, ...); 147void DPRINTF(struct ath_softc *sc, int dbg_mask, const char *fmt, ...);
99int ath9k_init_debug(struct ath_softc *sc); 148int ath9k_init_debug(struct ath_softc *sc);
100void ath9k_exit_debug(struct ath_softc *sc); 149void ath9k_exit_debug(struct ath_softc *sc);
150void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
101 151
102#else 152#else
103 153
@@ -115,6 +165,11 @@ static inline void ath9k_exit_debug(struct ath_softc *sc)
115{ 165{
116} 166}
117 167
168static inline void ath_debug_stat_interrupt(struct ath_softc *sc,
169 enum ath9k_int status)
170{
171}
172
118#endif /* CONFIG_ATH9K_DEBUG */ 173#endif /* CONFIG_ATH9K_DEBUG */
119 174
120struct ath_config { 175struct ath_config {
@@ -235,18 +290,9 @@ void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
235/* RX / TX */ 290/* RX / TX */
236/***********/ 291/***********/
237 292
238#define ATH_MAX_ANTENNA 3 293#define ATH_MAX_ANTENNA 3
239#define ATH_RXBUF 512 294#define ATH_RXBUF 512
240#define WME_NUM_TID 16 295#define WME_NUM_TID 16
241
242int ath_startrecv(struct ath_softc *sc);
243bool ath_stoprecv(struct ath_softc *sc);
244void ath_flushrecv(struct ath_softc *sc);
245u32 ath_calcrxfilter(struct ath_softc *sc);
246int ath_rx_init(struct ath_softc *sc, int nbufs);
247void ath_rx_cleanup(struct ath_softc *sc);
248int ath_rx_tasklet(struct ath_softc *sc, int flush);
249
250#define ATH_TXBUF 512 296#define ATH_TXBUF 512
251#define ATH_TXMAXTRY 13 297#define ATH_TXMAXTRY 13
252#define ATH_11N_TXMAXTRY 10 298#define ATH_11N_TXMAXTRY 10
@@ -254,19 +300,61 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush);
254#define WME_BA_BMP_SIZE 64 300#define WME_BA_BMP_SIZE 64
255#define WME_MAX_BA WME_BA_BMP_SIZE 301#define WME_MAX_BA WME_BA_BMP_SIZE
256#define ATH_TID_MAX_BUFS (2 * WME_MAX_BA) 302#define ATH_TID_MAX_BUFS (2 * WME_MAX_BA)
303
257#define TID_TO_WME_AC(_tid) \ 304#define TID_TO_WME_AC(_tid) \
258 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \ 305 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
259 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \ 306 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
260 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \ 307 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
261 WME_AC_VO) 308 WME_AC_VO)
262 309
263
264#define WME_AC_BE 0 310#define WME_AC_BE 0
265#define WME_AC_BK 1 311#define WME_AC_BK 1
266#define WME_AC_VI 2 312#define WME_AC_VI 2
267#define WME_AC_VO 3 313#define WME_AC_VO 3
268#define WME_NUM_AC 4 314#define WME_NUM_AC 4
269 315
316#define ADDBA_EXCHANGE_ATTEMPTS 10
317#define ATH_AGGR_DELIM_SZ 4
318#define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
319/* number of delimiters for encryption padding */
320#define ATH_AGGR_ENCRYPTDELIM 10
321/* minimum h/w qdepth to be sustained to maximize aggregation */
322#define ATH_AGGR_MIN_QDEPTH 2
323#define ATH_AMPDU_SUBFRAME_DEFAULT 32
324#define IEEE80211_SEQ_SEQ_SHIFT 4
325#define IEEE80211_SEQ_MAX 4096
326#define IEEE80211_MIN_AMPDU_BUF 0x8
327#define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13
328
329/* return whether a bit at index _n in bitmap _bm is set
330 * _sz is the size of the bitmap */
331#define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
332 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
333
334/* return block-ack bitmap index given sequence and starting sequence */
335#define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
336
337/* returns delimiter padding required given the packet length */
338#define ATH_AGGR_GET_NDELIM(_len) \
339 (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \
340 (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
341
342#define BAW_WITHIN(_start, _bawsz, _seqno) \
343 ((((_seqno) - (_start)) & 4095) < (_bawsz))
344
345#define ATH_DS_BA_SEQ(_ds) ((_ds)->ds_us.tx.ts_seqnum)
346#define ATH_DS_BA_BITMAP(_ds) (&(_ds)->ds_us.tx.ba_low)
347#define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA)
348#define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)])
349
350enum ATH_AGGR_STATUS {
351 ATH_AGGR_DONE,
352 ATH_AGGR_BAW_CLOSED,
353 ATH_AGGR_LIMITED,
354 ATH_AGGR_SHORTPKT,
355 ATH_AGGR_8K_LIMITED,
356};
357
270struct ath_txq { 358struct ath_txq {
271 u32 axq_qnum; /* hardware q number */ 359 u32 axq_qnum; /* hardware q number */
272 u32 *axq_link; /* link ptr in last TX desc */ 360 u32 *axq_link; /* link ptr in last TX desc */
@@ -276,7 +364,6 @@ struct ath_txq {
276 u32 axq_depth; /* queue depth */ 364 u32 axq_depth; /* queue depth */
277 u8 axq_aggr_depth; /* aggregates queued */ 365 u8 axq_aggr_depth; /* aggregates queued */
278 u32 axq_totalqueued; /* total ever queued */ 366 u32 axq_totalqueued; /* total ever queued */
279
280 bool stopped; /* Is mac80211 queue stopped ? */ 367 bool stopped; /* Is mac80211 queue stopped ? */
281 struct ath_buf *axq_linkbuf; /* virtual addr of last buffer*/ 368 struct ath_buf *axq_linkbuf; /* virtual addr of last buffer*/
282 369
@@ -322,12 +409,6 @@ struct ath_atx_ac {
322 struct list_head tid_q; /* queue of TIDs with buffers */ 409 struct list_head tid_q; /* queue of TIDs with buffers */
323}; 410};
324 411
325/* per dest tx state */
326struct ath_atx {
327 struct ath_atx_tid tid[WME_NUM_TID];
328 struct ath_atx_ac ac[WME_NUM_AC];
329};
330
331/* per-frame tx control block */ 412/* per-frame tx control block */
332struct ath_tx_control { 413struct ath_tx_control {
333 struct ath_txq *txq; 414 struct ath_txq *txq;
@@ -353,13 +434,54 @@ struct ath_tx_stat {
353 int rateKbps; 434 int rateKbps;
354 int ratecode; 435 int ratecode;
355 int flags; 436 int flags;
356/* if any of ctl,extn chain rssis are valid */
357#define ATH_TX_CHAIN_RSSI_VALID 0x01
358/* if extn chain rssis are valid */
359#define ATH_TX_RSSI_EXTN_VALID 0x02
360 u32 airtime; /* time on air per final tx rate */ 437 u32 airtime; /* time on air per final tx rate */
361}; 438};
362 439
440struct aggr_rifs_param {
441 int param_max_frames;
442 int param_max_len;
443 int param_rl;
444 int param_al;
445 struct ath_rc_series *param_rcs;
446};
447
448struct ath_node {
449 struct ath_softc *an_sc;
450 struct ath_atx_tid tid[WME_NUM_TID];
451 struct ath_atx_ac ac[WME_NUM_AC];
452 u16 maxampdu;
453 u8 mpdudensity;
454};
455
456struct ath_tx {
457 u16 seq_no;
458 u32 txqsetup;
459 int hwq_map[ATH9K_WME_AC_VO+1];
460 spinlock_t txbuflock;
461 struct list_head txbuf;
462 struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
463 struct ath_descdma txdma;
464};
465
466struct ath_rx {
467 u8 defant;
468 u8 rxotherant;
469 u32 *rxlink;
470 int bufsize;
471 unsigned int rxfilter;
472 spinlock_t rxflushlock;
473 spinlock_t rxbuflock;
474 struct list_head rxbuf;
475 struct ath_descdma rxdma;
476};
477
478int ath_startrecv(struct ath_softc *sc);
479bool ath_stoprecv(struct ath_softc *sc);
480void ath_flushrecv(struct ath_softc *sc);
481u32 ath_calcrxfilter(struct ath_softc *sc);
482int ath_rx_init(struct ath_softc *sc, int nbufs);
483void ath_rx_cleanup(struct ath_softc *sc);
484int ath_rx_tasklet(struct ath_softc *sc, int flush);
363struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype); 485struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
364void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq); 486void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
365int ath_tx_setup(struct ath_softc *sc, int haltype); 487int ath_tx_setup(struct ath_softc *sc, int haltype);
@@ -382,73 +504,6 @@ void ath_tx_tasklet(struct ath_softc *sc);
382u32 ath_txq_depth(struct ath_softc *sc, int qnum); 504u32 ath_txq_depth(struct ath_softc *sc, int qnum);
383u32 ath_txq_aggr_depth(struct ath_softc *sc, int qnum); 505u32 ath_txq_aggr_depth(struct ath_softc *sc, int qnum);
384void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb); 506void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb);
385
386/**********************/
387/* Node / Aggregation */
388/**********************/
389
390#define ADDBA_EXCHANGE_ATTEMPTS 10
391#define ATH_AGGR_DELIM_SZ 4
392#define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
393/* number of delimiters for encryption padding */
394#define ATH_AGGR_ENCRYPTDELIM 10
395/* minimum h/w qdepth to be sustained to maximize aggregation */
396#define ATH_AGGR_MIN_QDEPTH 2
397#define ATH_AMPDU_SUBFRAME_DEFAULT 32
398#define IEEE80211_SEQ_SEQ_SHIFT 4
399#define IEEE80211_SEQ_MAX 4096
400#define IEEE80211_MIN_AMPDU_BUF 0x8
401#define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13
402
403/* return whether a bit at index _n in bitmap _bm is set
404 * _sz is the size of the bitmap */
405#define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
406 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
407
408/* return block-ack bitmap index given sequence and starting sequence */
409#define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
410
411/* returns delimiter padding required given the packet length */
412#define ATH_AGGR_GET_NDELIM(_len) \
413 (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \
414 (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
415
416#define BAW_WITHIN(_start, _bawsz, _seqno) \
417 ((((_seqno) - (_start)) & 4095) < (_bawsz))
418
419#define ATH_DS_BA_SEQ(_ds) ((_ds)->ds_us.tx.ts_seqnum)
420#define ATH_DS_BA_BITMAP(_ds) (&(_ds)->ds_us.tx.ba_low)
421#define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA)
422#define ATH_AN_2_TID(_an, _tidno) (&(_an)->an_aggr.tx.tid[(_tidno)])
423
424enum ATH_AGGR_STATUS {
425 ATH_AGGR_DONE,
426 ATH_AGGR_BAW_CLOSED,
427 ATH_AGGR_LIMITED,
428 ATH_AGGR_SHORTPKT,
429 ATH_AGGR_8K_LIMITED,
430};
431
432struct aggr_rifs_param {
433 int param_max_frames;
434 int param_max_len;
435 int param_rl;
436 int param_al;
437 struct ath_rc_series *param_rcs;
438};
439
440/* Per-node aggregation state */
441struct ath_node_aggr {
442 struct ath_atx tx;
443};
444
445struct ath_node {
446 struct ath_softc *an_sc;
447 struct ath_node_aggr an_aggr;
448 u16 maxampdu;
449 u8 mpdudensity;
450};
451
452void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid); 507void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid);
453bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno); 508bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno);
454void ath_tx_aggr_teardown(struct ath_softc *sc, struct ath_node *an, u8 tidno); 509void ath_tx_aggr_teardown(struct ath_softc *sc, struct ath_node *an, u8 tidno);
@@ -489,7 +544,7 @@ struct ath_vap {
489 * number of beacon intervals, the game's up. 544 * number of beacon intervals, the game's up.
490 */ 545 */
491#define BSTUCK_THRESH (9 * ATH_BCBUF) 546#define BSTUCK_THRESH (9 * ATH_BCBUF)
492#define ATH_BCBUF 4 547#define ATH_BCBUF 1
493#define ATH_DEFAULT_BINTVAL 100 /* TU */ 548#define ATH_DEFAULT_BINTVAL 100 /* TU */
494#define ATH_DEFAULT_BMISS_LIMIT 10 549#define ATH_DEFAULT_BMISS_LIMIT 10
495#define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024) 550#define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
@@ -507,6 +562,26 @@ struct ath_beacon_config {
507 } u; /* last received beacon/probe response timestamp of this BSS. */ 562 } u; /* last received beacon/probe response timestamp of this BSS. */
508}; 563};
509 564
565struct ath_beacon {
566 enum {
567 OK, /* no change needed */
568 UPDATE, /* update pending */
569 COMMIT /* beacon sent, commit change */
570 } updateslot; /* slot time update fsm */
571
572 u32 beaconq;
573 u32 bmisscnt;
574 u32 ast_be_xmit;
575 u64 bc_tstamp;
576 int bslot[ATH_BCBUF];
577 int slottime;
578 int slotupdate;
579 struct ath9k_tx_queue_info beacon_qi;
580 struct ath_descdma bdma;
581 struct ath_txq *cabq;
582 struct list_head bbuf;
583};
584
510void ath9k_beacon_tasklet(unsigned long data); 585void ath9k_beacon_tasklet(unsigned long data);
511void ath_beacon_config(struct ath_softc *sc, int if_id); 586void ath_beacon_config(struct ath_softc *sc, int if_id);
512int ath_beaconq_setup(struct ath_hal *ah); 587int ath_beaconq_setup(struct ath_hal *ah);
@@ -577,7 +652,7 @@ struct ath_rfkill {
577#define DEFAULT_CACHELINE 32 652#define DEFAULT_CACHELINE 32
578#define ATH_DEFAULT_NOISE_FLOOR -95 653#define ATH_DEFAULT_NOISE_FLOOR -95
579#define ATH_REGCLASSIDS_MAX 10 654#define ATH_REGCLASSIDS_MAX 10
580#define ATH_CABQ_READY_TIME 80 /* % of beacon interval */ 655#define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
581#define ATH_MAX_SW_RETRIES 10 656#define ATH_MAX_SW_RETRIES 10
582#define ATH_CHAN_MAX 255 657#define ATH_CHAN_MAX 255
583#define IEEE80211_WEP_NKID 4 /* number of key ids */ 658#define IEEE80211_WEP_NKID 4 /* number of key ids */
@@ -590,7 +665,7 @@ struct ath_rfkill {
590 * Different parts have different size key caches. We handle 665 * Different parts have different size key caches. We handle
591 * up to ATH_KEYMAX entries (could dynamically allocate state). 666 * up to ATH_KEYMAX entries (could dynamically allocate state).
592 */ 667 */
593#define ATH_KEYMAX 128 /* max key cache size we handle */ 668#define ATH_KEYMAX 128 /* max key cache size we handle */
594 669
595#define ATH_IF_ID_ANY 0xff 670#define ATH_IF_ID_ANY 0xff
596#define ATH_TXPOWER_MAX 100 /* .5 dBm units */ 671#define ATH_TXPOWER_MAX 100 /* .5 dBm units */
@@ -623,108 +698,51 @@ struct ath_softc {
623 struct pci_dev *pdev; 698 struct pci_dev *pdev;
624 struct tasklet_struct intr_tq; 699 struct tasklet_struct intr_tq;
625 struct tasklet_struct bcon_tasklet; 700 struct tasklet_struct bcon_tasklet;
626 struct ath_config sc_config;
627 struct ath_hal *sc_ah; 701 struct ath_hal *sc_ah;
628 void __iomem *mem; 702 void __iomem *mem;
703 spinlock_t sc_resetlock;
629 704
630 u8 sc_curbssid[ETH_ALEN]; 705 u8 sc_curbssid[ETH_ALEN];
631 u8 sc_myaddr[ETH_ALEN]; 706 u8 sc_myaddr[ETH_ALEN];
632 u8 sc_bssidmask[ETH_ALEN]; 707 u8 sc_bssidmask[ETH_ALEN];
633
634#ifdef CONFIG_ATH9K_DEBUG
635 struct ath9k_debug sc_debug;
636#endif
637 u32 sc_intrstatus; 708 u32 sc_intrstatus;
638 u32 sc_flags; /* SC_OP_* */ 709 u32 sc_flags; /* SC_OP_* */
639 unsigned int rx_filter;
640 u16 sc_curtxpow; 710 u16 sc_curtxpow;
641 u16 sc_curaid; 711 u16 sc_curaid;
642 u16 sc_cachelsz; 712 u16 sc_cachelsz;
643 int sc_slotupdate; /* slot to next advance fsm */ 713 u8 sc_nbcnvaps;
644 int sc_slottime; 714 u16 sc_nvaps;
645 int sc_bslot[ATH_BCBUF];
646 u8 sc_tx_chainmask; 715 u8 sc_tx_chainmask;
647 u8 sc_rx_chainmask; 716 u8 sc_rx_chainmask;
717 u32 sc_keymax;
718 DECLARE_BITMAP(sc_keymap, ATH_KEYMAX);
719 u8 sc_splitmic;
720 u8 sc_protrix;
648 enum ath9k_int sc_imask; 721 enum ath9k_int sc_imask;
649 enum wireless_mode sc_curmode;
650 enum PROT_MODE sc_protmode; 722 enum PROT_MODE sc_protmode;
651
652 u8 sc_nbcnvaps;
653 u16 sc_nvaps;
654 struct ieee80211_vif *sc_vaps[ATH_BCBUF];
655
656 u8 sc_mcastantenna;
657 u8 sc_defant;
658 u8 sc_rxotherant;
659
660 struct ath9k_node_stats sc_halstats;
661 enum ath9k_ht_extprotspacing sc_ht_extprotspacing; 723 enum ath9k_ht_extprotspacing sc_ht_extprotspacing;
662 enum ath9k_ht_macmode tx_chan_width; 724 enum ath9k_ht_macmode tx_chan_width;
663 725
664#ifdef CONFIG_SLOW_ANT_DIV 726 struct ath_config sc_config;
665 struct ath_antdiv sc_antdiv; 727 struct ath_rx rx;
666#endif 728 struct ath_tx tx;
667 enum { 729 struct ath_beacon beacon;
668 OK, /* no change needed */ 730 struct ieee80211_vif *sc_vaps[ATH_BCBUF];
669 UPDATE, /* update pending */
670 COMMIT /* beacon sent, commit change */
671 } sc_updateslot; /* slot time update fsm */
672
673 /* Crypto */
674 u32 sc_keymax;
675 DECLARE_BITMAP(sc_keymap, ATH_KEYMAX);
676 u8 sc_splitmic; /* split TKIP MIC keys */
677
678 /* RX */
679 struct list_head sc_rxbuf;
680 struct ath_descdma sc_rxdma;
681 int sc_rxbufsize;
682 u32 *sc_rxlink;
683
684 /* TX */
685 struct list_head sc_txbuf;
686 struct ath_txq sc_txq[ATH9K_NUM_TX_QUEUES];
687 struct ath_descdma sc_txdma;
688 u32 sc_txqsetup;
689 int sc_haltype2q[ATH9K_WME_AC_VO+1];
690 u16 seq_no; /* TX sequence number */
691
692 /* Beacon */
693 struct ath9k_tx_queue_info sc_beacon_qi;
694 struct ath_descdma sc_bdma;
695 struct ath_txq *sc_cabq;
696 struct list_head sc_bbuf;
697 u32 sc_bhalq;
698 u32 sc_bmisscount;
699 u32 ast_be_xmit;
700 u64 bc_tstamp;
701
702 /* Rate */
703 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX]; 731 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX];
704 struct ath_rate_table *hw_rate_table[ATH9K_MODE_MAX]; 732 struct ath_rate_table *hw_rate_table[ATH9K_MODE_MAX];
705 u8 sc_protrix; 733 struct ath_rate_table *cur_rate_table;
706
707 /* Channel, Band */
708 struct ieee80211_channel channels[IEEE80211_NUM_BANDS][ATH_CHAN_MAX]; 734 struct ieee80211_channel channels[IEEE80211_NUM_BANDS][ATH_CHAN_MAX];
709 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS]; 735 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
710
711 /* Locks */
712 spinlock_t sc_rxflushlock;
713 spinlock_t sc_rxbuflock;
714 spinlock_t sc_txbuflock;
715 spinlock_t sc_resetlock;
716
717 /* LEDs */
718 struct ath_led radio_led; 736 struct ath_led radio_led;
719 struct ath_led assoc_led; 737 struct ath_led assoc_led;
720 struct ath_led tx_led; 738 struct ath_led tx_led;
721 struct ath_led rx_led; 739 struct ath_led rx_led;
722
723 /* Rfkill */
724 struct ath_rfkill rf_kill; 740 struct ath_rfkill rf_kill;
725
726 /* ANI */
727 struct ath_ani sc_ani; 741 struct ath_ani sc_ani;
742 struct ath9k_node_stats sc_halstats;
743#ifdef CONFIG_ATH9K_DEBUG
744 struct ath9k_debug sc_debug;
745#endif
728}; 746};
729 747
730int ath_reset(struct ath_softc *sc, bool retry_tx); 748int ath_reset(struct ath_softc *sc, bool retry_tx);
diff --git a/drivers/net/wireless/ath9k/debug.c b/drivers/net/wireless/ath9k/debug.c
index da52812c3a94..a80ed576830f 100644
--- a/drivers/net/wireless/ath9k/debug.c
+++ b/drivers/net/wireless/ath9k/debug.c
@@ -128,6 +128,100 @@ static const struct file_operations fops_dma = {
128 .owner = THIS_MODULE 128 .owner = THIS_MODULE
129}; 129};
130 130
131
132void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status)
133{
134 if (status)
135 sc->sc_debug.stats.istats.total++;
136 if (status & ATH9K_INT_RX)
137 sc->sc_debug.stats.istats.rxok++;
138 if (status & ATH9K_INT_RXEOL)
139 sc->sc_debug.stats.istats.rxeol++;
140 if (status & ATH9K_INT_RXORN)
141 sc->sc_debug.stats.istats.rxorn++;
142 if (status & ATH9K_INT_TX)
143 sc->sc_debug.stats.istats.txok++;
144 if (status & ATH9K_INT_TXURN)
145 sc->sc_debug.stats.istats.txurn++;
146 if (status & ATH9K_INT_MIB)
147 sc->sc_debug.stats.istats.mib++;
148 if (status & ATH9K_INT_RXPHY)
149 sc->sc_debug.stats.istats.rxphyerr++;
150 if (status & ATH9K_INT_RXKCM)
151 sc->sc_debug.stats.istats.rx_keycache_miss++;
152 if (status & ATH9K_INT_SWBA)
153 sc->sc_debug.stats.istats.swba++;
154 if (status & ATH9K_INT_BMISS)
155 sc->sc_debug.stats.istats.bmiss++;
156 if (status & ATH9K_INT_BNR)
157 sc->sc_debug.stats.istats.bnr++;
158 if (status & ATH9K_INT_CST)
159 sc->sc_debug.stats.istats.cst++;
160 if (status & ATH9K_INT_GTT)
161 sc->sc_debug.stats.istats.gtt++;
162 if (status & ATH9K_INT_TIM)
163 sc->sc_debug.stats.istats.tim++;
164 if (status & ATH9K_INT_CABEND)
165 sc->sc_debug.stats.istats.cabend++;
166 if (status & ATH9K_INT_DTIMSYNC)
167 sc->sc_debug.stats.istats.dtimsync++;
168 if (status & ATH9K_INT_DTIM)
169 sc->sc_debug.stats.istats.dtim++;
170}
171
172static ssize_t read_file_interrupt(struct file *file, char __user *user_buf,
173 size_t count, loff_t *ppos)
174{
175 struct ath_softc *sc = file->private_data;
176 char buf[512];
177 unsigned int len = 0;
178
179 len += snprintf(buf + len, sizeof(buf) - len,
180 "%8s: %10u\n", "RX", sc->sc_debug.stats.istats.rxok);
181 len += snprintf(buf + len, sizeof(buf) - len,
182 "%8s: %10u\n", "RXEOL", sc->sc_debug.stats.istats.rxeol);
183 len += snprintf(buf + len, sizeof(buf) - len,
184 "%8s: %10u\n", "RXORN", sc->sc_debug.stats.istats.rxorn);
185 len += snprintf(buf + len, sizeof(buf) - len,
186 "%8s: %10u\n", "TX", sc->sc_debug.stats.istats.txok);
187 len += snprintf(buf + len, sizeof(buf) - len,
188 "%8s: %10u\n", "TXURN", sc->sc_debug.stats.istats.txurn);
189 len += snprintf(buf + len, sizeof(buf) - len,
190 "%8s: %10u\n", "MIB", sc->sc_debug.stats.istats.mib);
191 len += snprintf(buf + len, sizeof(buf) - len,
192 "%8s: %10u\n", "RXPHY", sc->sc_debug.stats.istats.rxphyerr);
193 len += snprintf(buf + len, sizeof(buf) - len,
194 "%8s: %10u\n", "RXKCM", sc->sc_debug.stats.istats.rx_keycache_miss);
195 len += snprintf(buf + len, sizeof(buf) - len,
196 "%8s: %10u\n", "SWBA", sc->sc_debug.stats.istats.swba);
197 len += snprintf(buf + len, sizeof(buf) - len,
198 "%8s: %10u\n", "BMISS", sc->sc_debug.stats.istats.bmiss);
199 len += snprintf(buf + len, sizeof(buf) - len,
200 "%8s: %10u\n", "BNR", sc->sc_debug.stats.istats.bnr);
201 len += snprintf(buf + len, sizeof(buf) - len,
202 "%8s: %10u\n", "CST", sc->sc_debug.stats.istats.cst);
203 len += snprintf(buf + len, sizeof(buf) - len,
204 "%8s: %10u\n", "GTT", sc->sc_debug.stats.istats.gtt);
205 len += snprintf(buf + len, sizeof(buf) - len,
206 "%8s: %10u\n", "TIM", sc->sc_debug.stats.istats.tim);
207 len += snprintf(buf + len, sizeof(buf) - len,
208 "%8s: %10u\n", "CABEND", sc->sc_debug.stats.istats.cabend);
209 len += snprintf(buf + len, sizeof(buf) - len,
210 "%8s: %10u\n", "DTIMSYNC", sc->sc_debug.stats.istats.dtimsync);
211 len += snprintf(buf + len, sizeof(buf) - len,
212 "%8s: %10u\n", "DTIM", sc->sc_debug.stats.istats.dtim);
213 len += snprintf(buf + len, sizeof(buf) - len,
214 "%8s: %10u\n", "TOTAL", sc->sc_debug.stats.istats.total);
215
216 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
217}
218
219static const struct file_operations fops_interrupt = {
220 .read = read_file_interrupt,
221 .open = ath9k_debugfs_open,
222 .owner = THIS_MODULE
223};
224
131int ath9k_init_debug(struct ath_softc *sc) 225int ath9k_init_debug(struct ath_softc *sc)
132{ 226{
133 sc->sc_debug.debug_mask = ath9k_debug; 227 sc->sc_debug.debug_mask = ath9k_debug;
@@ -146,6 +240,13 @@ int ath9k_init_debug(struct ath_softc *sc)
146 if (!sc->sc_debug.debugfs_dma) 240 if (!sc->sc_debug.debugfs_dma)
147 goto err; 241 goto err;
148 242
243 sc->sc_debug.debugfs_interrupt = debugfs_create_file("interrupt",
244 S_IRUGO,
245 sc->sc_debug.debugfs_phy,
246 sc, &fops_interrupt);
247 if (!sc->sc_debug.debugfs_interrupt)
248 goto err;
249
149 return 0; 250 return 0;
150err: 251err:
151 ath9k_exit_debug(sc); 252 ath9k_exit_debug(sc);
@@ -154,6 +255,7 @@ err:
154 255
155void ath9k_exit_debug(struct ath_softc *sc) 256void ath9k_exit_debug(struct ath_softc *sc)
156{ 257{
258 debugfs_remove(sc->sc_debug.debugfs_interrupt);
157 debugfs_remove(sc->sc_debug.debugfs_dma); 259 debugfs_remove(sc->sc_debug.debugfs_dma);
158 debugfs_remove(sc->sc_debug.debugfs_phy); 260 debugfs_remove(sc->sc_debug.debugfs_phy);
159 debugfs_remove(sc->sc_debug.debugfs_root); 261 debugfs_remove(sc->sc_debug.debugfs_root);
diff --git a/drivers/net/wireless/ath9k/eeprom.c b/drivers/net/wireless/ath9k/eeprom.c
index e180c9043df6..14f8d40c1427 100644
--- a/drivers/net/wireless/ath9k/eeprom.c
+++ b/drivers/net/wireless/ath9k/eeprom.c
@@ -140,61 +140,97 @@ static inline bool ath9k_hw_nvram_read(struct ath_hal *ah, u32 off, u16 *data)
140 return ath9k_hw_eeprom_read(ah, off, data); 140 return ath9k_hw_eeprom_read(ah, off, data);
141} 141}
142 142
143static bool ath9k_hw_fill_eeprom(struct ath_hal *ah) 143static bool ath9k_hw_fill_4k_eeprom(struct ath_hal *ah)
144{ 144{
145#define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
145 struct ath_hal_5416 *ahp = AH5416(ah); 146 struct ath_hal_5416 *ahp = AH5416(ah);
146 struct ar5416_eeprom *eep = &ahp->ah_eeprom; 147 struct ar5416_eeprom_4k *eep = &ahp->ah_eeprom.map4k;
147 u16 *eep_data; 148 u16 *eep_data;
148 int addr, ar5416_eep_start_loc = 0; 149 int addr, eep_start_loc = 0;
150
151 eep_start_loc = 64;
149 152
150 if (!ath9k_hw_use_flash(ah)) { 153 if (!ath9k_hw_use_flash(ah)) {
151 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 154 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
152 "Reading from EEPROM, not flash\n"); 155 "Reading from EEPROM, not flash\n");
153 ar5416_eep_start_loc = 256;
154 } 156 }
155 157
156 if (AR_SREV_9100(ah)) 158 eep_data = (u16 *)eep;
157 ar5416_eep_start_loc = 256; 159
160 for (addr = 0; addr < SIZE_EEPROM_4K; addr++) {
161 if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data)) {
162 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
163 "Unable to read eeprom region \n");
164 return false;
165 }
166 eep_data++;
167 }
168 return true;
169#undef SIZE_EEPROM_4K
170}
171
172static bool ath9k_hw_fill_def_eeprom(struct ath_hal *ah)
173{
174#define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16))
175 struct ath_hal_5416 *ahp = AH5416(ah);
176 struct ar5416_eeprom_def *eep = &ahp->ah_eeprom.def;
177 u16 *eep_data;
178 int addr, ar5416_eep_start_loc = 0x100;
158 179
159 eep_data = (u16 *)eep; 180 eep_data = (u16 *)eep;
160 181
161 for (addr = 0; addr < sizeof(struct ar5416_eeprom) / sizeof(u16); addr++) { 182 for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) {
162 if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc, 183 if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc,
163 eep_data)) { 184 eep_data)) {
164 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 185 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
165 "Unable to read eeprom region \n"); 186 "Unable to read eeprom region\n");
166 return false; 187 return false;
167 } 188 }
168 eep_data++; 189 eep_data++;
169 } 190 }
170 return true; 191 return true;
192#undef SIZE_EEPROM_DEF
193}
194
195bool (*ath9k_fill_eeprom[]) (struct ath_hal *) = {
196 ath9k_hw_fill_def_eeprom,
197 ath9k_hw_fill_4k_eeprom
198};
199
200static inline bool ath9k_hw_fill_eeprom(struct ath_hal *ah)
201{
202 struct ath_hal_5416 *ahp = AH5416(ah);
203
204 return ath9k_fill_eeprom[ahp->ah_eep_map](ah);
171} 205}
172 206
173static int ath9k_hw_check_eeprom(struct ath_hal *ah) 207static int ath9k_hw_check_def_eeprom(struct ath_hal *ah)
174{ 208{
175 struct ath_hal_5416 *ahp = AH5416(ah); 209 struct ath_hal_5416 *ahp = AH5416(ah);
176 struct ar5416_eeprom *eep = 210 struct ar5416_eeprom_def *eep =
177 (struct ar5416_eeprom *) &ahp->ah_eeprom; 211 (struct ar5416_eeprom_def *) &ahp->ah_eeprom.def;
178 u16 *eepdata, temp, magic, magic2; 212 u16 *eepdata, temp, magic, magic2;
179 u32 sum = 0, el; 213 u32 sum = 0, el;
180 bool need_swap = false; 214 bool need_swap = false;
181 int i, addr, size; 215 int i, addr, size;
182 216
217 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
218 &magic)) {
219 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
220 "Reading Magic # failed\n");
221 return false;
222 }
223
183 if (!ath9k_hw_use_flash(ah)) { 224 if (!ath9k_hw_use_flash(ah)) {
184 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
185 &magic)) {
186 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
187 "Reading Magic # failed\n");
188 return false;
189 }
190 225
191 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "Read Magic = 0x%04X\n", magic); 226 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
227 "Read Magic = 0x%04X\n", magic);
192 228
193 if (magic != AR5416_EEPROM_MAGIC) { 229 if (magic != AR5416_EEPROM_MAGIC) {
194 magic2 = swab16(magic); 230 magic2 = swab16(magic);
195 231
196 if (magic2 == AR5416_EEPROM_MAGIC) { 232 if (magic2 == AR5416_EEPROM_MAGIC) {
197 size = sizeof(struct ar5416_eeprom); 233 size = sizeof(struct ar5416_eeprom_def);
198 need_swap = true; 234 need_swap = true;
199 eepdata = (u16 *) (&ahp->ah_eeprom); 235 eepdata = (u16 *) (&ahp->ah_eeprom);
200 236
@@ -223,12 +259,12 @@ static int ath9k_hw_check_eeprom(struct ath_hal *ah)
223 need_swap ? "True" : "False"); 259 need_swap ? "True" : "False");
224 260
225 if (need_swap) 261 if (need_swap)
226 el = swab16(ahp->ah_eeprom.baseEepHeader.length); 262 el = swab16(ahp->ah_eeprom.def.baseEepHeader.length);
227 else 263 else
228 el = ahp->ah_eeprom.baseEepHeader.length; 264 el = ahp->ah_eeprom.def.baseEepHeader.length;
229 265
230 if (el > sizeof(struct ar5416_eeprom)) 266 if (el > sizeof(struct ar5416_eeprom_def))
231 el = sizeof(struct ar5416_eeprom) / sizeof(u16); 267 el = sizeof(struct ar5416_eeprom_def) / sizeof(u16);
232 else 268 else
233 el = el / sizeof(u16); 269 el = el / sizeof(u16);
234 270
@@ -297,6 +333,145 @@ static int ath9k_hw_check_eeprom(struct ath_hal *ah)
297 return 0; 333 return 0;
298} 334}
299 335
336static int ath9k_hw_check_4k_eeprom(struct ath_hal *ah)
337{
338#define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
339 struct ath_hal_5416 *ahp = AH5416(ah);
340 struct ar5416_eeprom_4k *eep =
341 (struct ar5416_eeprom_4k *) &ahp->ah_eeprom.map4k;
342 u16 *eepdata, temp, magic, magic2;
343 u32 sum = 0, el;
344 bool need_swap = false;
345 int i, addr;
346
347
348 if (!ath9k_hw_use_flash(ah)) {
349
350 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
351 &magic)) {
352 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
353 "Reading Magic # failed\n");
354 return false;
355 }
356
357 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
358 "Read Magic = 0x%04X\n", magic);
359
360 if (magic != AR5416_EEPROM_MAGIC) {
361 magic2 = swab16(magic);
362
363 if (magic2 == AR5416_EEPROM_MAGIC) {
364 need_swap = true;
365 eepdata = (u16 *) (&ahp->ah_eeprom);
366
367 for (addr = 0; addr < EEPROM_4K_SIZE; addr++) {
368 temp = swab16(*eepdata);
369 *eepdata = temp;
370 eepdata++;
371
372 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
373 "0x%04X ", *eepdata);
374
375 if (((addr + 1) % 6) == 0)
376 DPRINTF(ah->ah_sc,
377 ATH_DBG_EEPROM, "\n");
378 }
379 } else {
380 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
381 "Invalid EEPROM Magic. "
382 "endianness mismatch.\n");
383 return -EINVAL;
384 }
385 }
386 }
387
388 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n",
389 need_swap ? "True" : "False");
390
391 if (need_swap)
392 el = swab16(ahp->ah_eeprom.map4k.baseEepHeader.length);
393 else
394 el = ahp->ah_eeprom.map4k.baseEepHeader.length;
395
396 if (el > sizeof(struct ar5416_eeprom_def))
397 el = sizeof(struct ar5416_eeprom_4k) / sizeof(u16);
398 else
399 el = el / sizeof(u16);
400
401 eepdata = (u16 *)(&ahp->ah_eeprom);
402
403 for (i = 0; i < el; i++)
404 sum ^= *eepdata++;
405
406 if (need_swap) {
407 u32 integer;
408 u16 word;
409
410 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
411 "EEPROM Endianness is not native.. Changing \n");
412
413 word = swab16(eep->baseEepHeader.length);
414 eep->baseEepHeader.length = word;
415
416 word = swab16(eep->baseEepHeader.checksum);
417 eep->baseEepHeader.checksum = word;
418
419 word = swab16(eep->baseEepHeader.version);
420 eep->baseEepHeader.version = word;
421
422 word = swab16(eep->baseEepHeader.regDmn[0]);
423 eep->baseEepHeader.regDmn[0] = word;
424
425 word = swab16(eep->baseEepHeader.regDmn[1]);
426 eep->baseEepHeader.regDmn[1] = word;
427
428 word = swab16(eep->baseEepHeader.rfSilent);
429 eep->baseEepHeader.rfSilent = word;
430
431 word = swab16(eep->baseEepHeader.blueToothOptions);
432 eep->baseEepHeader.blueToothOptions = word;
433
434 word = swab16(eep->baseEepHeader.deviceCap);
435 eep->baseEepHeader.deviceCap = word;
436
437 integer = swab32(eep->modalHeader.antCtrlCommon);
438 eep->modalHeader.antCtrlCommon = integer;
439
440 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
441 integer = swab32(eep->modalHeader.antCtrlChain[i]);
442 eep->modalHeader.antCtrlChain[i] = integer;
443 }
444
445 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
446 word = swab16(eep->modalHeader.spurChans[i].spurChan);
447 eep->modalHeader.spurChans[i].spurChan = word;
448 }
449 }
450
451 if (sum != 0xffff || ar5416_get_eep4k_ver(ahp) != AR5416_EEP_VER ||
452 ar5416_get_eep4k_rev(ahp) < AR5416_EEP_NO_BACK_VER) {
453 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
454 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
455 sum, ar5416_get_eep4k_ver(ahp));
456 return -EINVAL;
457 }
458
459 return 0;
460#undef EEPROM_4K_SIZE
461}
462
463int (*ath9k_check_eeprom[]) (struct ath_hal *) = {
464 ath9k_hw_check_def_eeprom,
465 ath9k_hw_check_4k_eeprom
466};
467
468static inline int ath9k_hw_check_eeprom(struct ath_hal *ah)
469{
470 struct ath_hal_5416 *ahp = AH5416(ah);
471
472 return ath9k_check_eeprom[ahp->ah_eep_map](ah);
473}
474
300static inline bool ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList, 475static inline bool ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
301 u8 *pVpdList, u16 numIntercepts, 476 u8 *pVpdList, u16 numIntercepts,
302 u8 *pRetVpdList) 477 u8 *pRetVpdList)
@@ -326,7 +501,175 @@ static inline bool ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
326 return true; 501 return true;
327} 502}
328 503
329static void ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hal *ah, 504static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hal *ah,
505 struct ath9k_channel *chan,
506 struct cal_data_per_freq_4k *pRawDataSet,
507 u8 *bChans, u16 availPiers,
508 u16 tPdGainOverlap, int16_t *pMinCalPower,
509 u16 *pPdGainBoundaries, u8 *pPDADCValues,
510 u16 numXpdGains)
511{
512#define TMP_VAL_VPD_TABLE \
513 ((vpdTableI[i][sizeCurrVpdTable - 1] + (ss - maxIndex + 1) * vpdStep));
514 int i, j, k;
515 int16_t ss;
516 u16 idxL = 0, idxR = 0, numPiers;
517 static u8 vpdTableL[AR5416_EEP4K_NUM_PD_GAINS]
518 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
519 static u8 vpdTableR[AR5416_EEP4K_NUM_PD_GAINS]
520 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
521 static u8 vpdTableI[AR5416_EEP4K_NUM_PD_GAINS]
522 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
523
524 u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
525 u8 minPwrT4[AR5416_EEP4K_NUM_PD_GAINS];
526 u8 maxPwrT4[AR5416_EEP4K_NUM_PD_GAINS];
527 int16_t vpdStep;
528 int16_t tmpVal;
529 u16 sizeCurrVpdTable, maxIndex, tgtIndex;
530 bool match;
531 int16_t minDelta = 0;
532 struct chan_centers centers;
533#define PD_GAIN_BOUNDARY_DEFAULT 58;
534
535 ath9k_hw_get_channel_centers(ah, chan, &centers);
536
537 for (numPiers = 0; numPiers < availPiers; numPiers++) {
538 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
539 break;
540 }
541
542 match = ath9k_hw_get_lower_upper_index(
543 (u8)FREQ2FBIN(centers.synth_center,
544 IS_CHAN_2GHZ(chan)), bChans, numPiers,
545 &idxL, &idxR);
546
547 if (match) {
548 for (i = 0; i < numXpdGains; i++) {
549 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
550 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
551 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
552 pRawDataSet[idxL].pwrPdg[i],
553 pRawDataSet[idxL].vpdPdg[i],
554 AR5416_EEP4K_PD_GAIN_ICEPTS,
555 vpdTableI[i]);
556 }
557 } else {
558 for (i = 0; i < numXpdGains; i++) {
559 pVpdL = pRawDataSet[idxL].vpdPdg[i];
560 pPwrL = pRawDataSet[idxL].pwrPdg[i];
561 pVpdR = pRawDataSet[idxR].vpdPdg[i];
562 pPwrR = pRawDataSet[idxR].pwrPdg[i];
563
564 minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
565
566 maxPwrT4[i] =
567 min(pPwrL[AR5416_EEP4K_PD_GAIN_ICEPTS - 1],
568 pPwrR[AR5416_EEP4K_PD_GAIN_ICEPTS - 1]);
569
570
571 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
572 pPwrL, pVpdL,
573 AR5416_EEP4K_PD_GAIN_ICEPTS,
574 vpdTableL[i]);
575 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
576 pPwrR, pVpdR,
577 AR5416_EEP4K_PD_GAIN_ICEPTS,
578 vpdTableR[i]);
579
580 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
581 vpdTableI[i][j] =
582 (u8)(ath9k_hw_interpolate((u16)
583 FREQ2FBIN(centers.
584 synth_center,
585 IS_CHAN_2GHZ
586 (chan)),
587 bChans[idxL], bChans[idxR],
588 vpdTableL[i][j], vpdTableR[i][j]));
589 }
590 }
591 }
592
593 *pMinCalPower = (int16_t)(minPwrT4[0] / 2);
594
595 k = 0;
596
597 for (i = 0; i < numXpdGains; i++) {
598 if (i == (numXpdGains - 1))
599 pPdGainBoundaries[i] =
600 (u16)(maxPwrT4[i] / 2);
601 else
602 pPdGainBoundaries[i] =
603 (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
604
605 pPdGainBoundaries[i] =
606 min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
607
608 if ((i == 0) && !AR_SREV_5416_V20_OR_LATER(ah)) {
609 minDelta = pPdGainBoundaries[0] - 23;
610 pPdGainBoundaries[0] = 23;
611 } else {
612 minDelta = 0;
613 }
614
615 if (i == 0) {
616 if (AR_SREV_9280_10_OR_LATER(ah))
617 ss = (int16_t)(0 - (minPwrT4[i] / 2));
618 else
619 ss = 0;
620 } else {
621 ss = (int16_t)((pPdGainBoundaries[i - 1] -
622 (minPwrT4[i] / 2)) -
623 tPdGainOverlap + 1 + minDelta);
624 }
625 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
626 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
627
628 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
629 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
630 pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
631 ss++;
632 }
633
634 sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
635 tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
636 (minPwrT4[i] / 2));
637 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
638 tgtIndex : sizeCurrVpdTable;
639
640 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1)))
641 pPDADCValues[k++] = vpdTableI[i][ss++];
642
643 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
644 vpdTableI[i][sizeCurrVpdTable - 2]);
645 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
646
647 if (tgtIndex > maxIndex) {
648 while ((ss <= tgtIndex) &&
649 (k < (AR5416_NUM_PDADC_VALUES - 1))) {
650 tmpVal = (int16_t) TMP_VAL_VPD_TABLE;
651 pPDADCValues[k++] = (u8)((tmpVal > 255) ?
652 255 : tmpVal);
653 ss++;
654 }
655 }
656 }
657
658 while (i < AR5416_EEP4K_PD_GAINS_IN_MASK) {
659 pPdGainBoundaries[i] = PD_GAIN_BOUNDARY_DEFAULT;
660 i++;
661 }
662
663 while (k < AR5416_NUM_PDADC_VALUES) {
664 pPDADCValues[k] = pPDADCValues[k - 1];
665 k++;
666 }
667
668 return;
669#undef TMP_VAL_VPD_TABLE
670}
671
672static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hal *ah,
330 struct ath9k_channel *chan, 673 struct ath9k_channel *chan,
331 struct cal_data_per_freq *pRawDataSet, 674 struct cal_data_per_freq *pRawDataSet,
332 u8 *bChans, u16 availPiers, 675 u8 *bChans, u16 availPiers,
@@ -603,12 +946,12 @@ static void ath9k_hw_get_target_powers(struct ath_hal *ah,
603 946
604static u16 ath9k_hw_get_max_edge_power(u16 freq, 947static u16 ath9k_hw_get_max_edge_power(u16 freq,
605 struct cal_ctl_edges *pRdEdgesPower, 948 struct cal_ctl_edges *pRdEdgesPower,
606 bool is2GHz) 949 bool is2GHz, int num_band_edges)
607{ 950{
608 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 951 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
609 int i; 952 int i;
610 953
611 for (i = 0; (i < AR5416_NUM_BAND_EDGES) && 954 for (i = 0; (i < num_band_edges) &&
612 (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED); i++) { 955 (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
613 if (freq == ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel, is2GHz)) { 956 if (freq == ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel, is2GHz)) {
614 twiceMaxEdgePower = pRdEdgesPower[i].tPower; 957 twiceMaxEdgePower = pRdEdgesPower[i].tPower;
@@ -629,207 +972,269 @@ static u16 ath9k_hw_get_max_edge_power(u16 freq,
629 return twiceMaxEdgePower; 972 return twiceMaxEdgePower;
630} 973}
631 974
632int ath9k_hw_set_txpower(struct ath_hal *ah, 975static bool ath9k_hw_set_def_power_cal_table(struct ath_hal *ah,
633 struct ath9k_channel *chan, 976 struct ath9k_channel *chan,
634 u16 cfgCtl, 977 int16_t *pTxPowerIndexOffset)
635 u8 twiceAntennaReduction,
636 u8 twiceMaxRegulatoryPower,
637 u8 powerLimit)
638{ 978{
639 struct ath_hal_5416 *ahp = AH5416(ah); 979 struct ath_hal_5416 *ahp = AH5416(ah);
640 struct ar5416_eeprom *pEepData = &ahp->ah_eeprom; 980 struct ar5416_eeprom_def *pEepData = &ahp->ah_eeprom.def;
641 struct modal_eep_header *pModal = 981 struct cal_data_per_freq *pRawDataset;
642 &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]); 982 u8 *pCalBChans = NULL;
643 int16_t ratesArray[Ar5416RateSize]; 983 u16 pdGainOverlap_t2;
644 int16_t txPowerIndexOffset = 0; 984 static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
645 u8 ht40PowerIncForPdadc = 2; 985 u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
646 int i; 986 u16 numPiers, i, j;
987 int16_t tMinCalPower;
988 u16 numXpdGain, xpdMask;
989 u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
990 u32 reg32, regOffset, regChainOffset;
991 int16_t modalIdx;
647 992
648 memset(ratesArray, 0, sizeof(ratesArray)); 993 modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
994 xpdMask = pEepData->modalHeader[modalIdx].xpdGain;
649 995
650 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 996 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
651 AR5416_EEP_MINOR_VER_2) { 997 AR5416_EEP_MINOR_VER_2) {
652 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; 998 pdGainOverlap_t2 =
653 } 999 pEepData->modalHeader[modalIdx].pdGainOverlap;
654 1000 } else {
655 if (!ath9k_hw_set_power_per_rate_table(ah, chan, 1001 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
656 &ratesArray[0], cfgCtl, 1002 AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
657 twiceAntennaReduction,
658 twiceMaxRegulatoryPower,
659 powerLimit)) {
660 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
661 "ath9k_hw_set_txpower: unable to set "
662 "tx power per rate table\n");
663 return -EIO;
664 } 1003 }
665 1004
666 if (!ath9k_hw_set_power_cal_table(ah, chan, &txPowerIndexOffset)) { 1005 if (IS_CHAN_2GHZ(chan)) {
667 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 1006 pCalBChans = pEepData->calFreqPier2G;
668 "ath9k_hw_set_txpower: unable to set power table\n"); 1007 numPiers = AR5416_NUM_2G_CAL_PIERS;
669 return -EIO; 1008 } else {
1009 pCalBChans = pEepData->calFreqPier5G;
1010 numPiers = AR5416_NUM_5G_CAL_PIERS;
670 } 1011 }
671 1012
672 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) { 1013 numXpdGain = 0;
673 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
674 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
675 ratesArray[i] = AR5416_MAX_RATE_POWER;
676 }
677 1014
678 if (AR_SREV_9280_10_OR_LATER(ah)) { 1015 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
679 for (i = 0; i < Ar5416RateSize; i++) 1016 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
680 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2; 1017 if (numXpdGain >= AR5416_NUM_PD_GAINS)
1018 break;
1019 xpdGainValues[numXpdGain] =
1020 (u16)(AR5416_PD_GAINS_IN_MASK - i);
1021 numXpdGain++;
1022 }
681 } 1023 }
682 1024
683 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, 1025 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
684 ATH9K_POW_SM(ratesArray[rate18mb], 24) 1026 (numXpdGain - 1) & 0x3);
685 | ATH9K_POW_SM(ratesArray[rate12mb], 16) 1027 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
686 | ATH9K_POW_SM(ratesArray[rate9mb], 8) 1028 xpdGainValues[0]);
687 | ATH9K_POW_SM(ratesArray[rate6mb], 0)); 1029 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
688 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, 1030 xpdGainValues[1]);
689 ATH9K_POW_SM(ratesArray[rate54mb], 24) 1031 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
690 | ATH9K_POW_SM(ratesArray[rate48mb], 16) 1032 xpdGainValues[2]);
691 | ATH9K_POW_SM(ratesArray[rate36mb], 8)
692 | ATH9K_POW_SM(ratesArray[rate24mb], 0));
693 1033
694 if (IS_CHAN_2GHZ(chan)) { 1034 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
695 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, 1035 if (AR_SREV_5416_V20_OR_LATER(ah) &&
696 ATH9K_POW_SM(ratesArray[rate2s], 24) 1036 (ahp->ah_rxchainmask == 5 || ahp->ah_txchainmask == 5) &&
697 | ATH9K_POW_SM(ratesArray[rate2l], 16) 1037 (i != 0)) {
698 | ATH9K_POW_SM(ratesArray[rateXr], 8) 1038 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
699 | ATH9K_POW_SM(ratesArray[rate1l], 0)); 1039 } else
700 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, 1040 regChainOffset = i * 0x1000;
701 ATH9K_POW_SM(ratesArray[rate11s], 24)
702 | ATH9K_POW_SM(ratesArray[rate11l], 16)
703 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
704 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
705 }
706 1041
707 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, 1042 if (pEepData->baseEepHeader.txMask & (1 << i)) {
708 ATH9K_POW_SM(ratesArray[rateHt20_3], 24) 1043 if (IS_CHAN_2GHZ(chan))
709 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16) 1044 pRawDataset = pEepData->calPierData2G[i];
710 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8) 1045 else
711 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0)); 1046 pRawDataset = pEepData->calPierData5G[i];
712 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
713 ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
714 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
715 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
716 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
717 1047
718 if (IS_CHAN_HT40(chan)) { 1048 ath9k_hw_get_def_gain_boundaries_pdadcs(ah, chan,
719 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, 1049 pRawDataset, pCalBChans,
720 ATH9K_POW_SM(ratesArray[rateHt40_3] + 1050 numPiers, pdGainOverlap_t2,
721 ht40PowerIncForPdadc, 24) 1051 &tMinCalPower, gainBoundaries,
722 | ATH9K_POW_SM(ratesArray[rateHt40_2] + 1052 pdadcValues, numXpdGain);
723 ht40PowerIncForPdadc, 16)
724 | ATH9K_POW_SM(ratesArray[rateHt40_1] +
725 ht40PowerIncForPdadc, 8)
726 | ATH9K_POW_SM(ratesArray[rateHt40_0] +
727 ht40PowerIncForPdadc, 0));
728 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
729 ATH9K_POW_SM(ratesArray[rateHt40_7] +
730 ht40PowerIncForPdadc, 24)
731 | ATH9K_POW_SM(ratesArray[rateHt40_6] +
732 ht40PowerIncForPdadc, 16)
733 | ATH9K_POW_SM(ratesArray[rateHt40_5] +
734 ht40PowerIncForPdadc, 8)
735 | ATH9K_POW_SM(ratesArray[rateHt40_4] +
736 ht40PowerIncForPdadc, 0));
737 1053
738 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, 1054 if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) {
739 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24) 1055 REG_WRITE(ah,
740 | ATH9K_POW_SM(ratesArray[rateExtCck], 16) 1056 AR_PHY_TPCRG5 + regChainOffset,
741 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8) 1057 SM(pdGainOverlap_t2,
742 | ATH9K_POW_SM(ratesArray[rateDupCck], 0)); 1058 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
743 } 1059 | SM(gainBoundaries[0],
1060 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
1061 | SM(gainBoundaries[1],
1062 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
1063 | SM(gainBoundaries[2],
1064 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
1065 | SM(gainBoundaries[3],
1066 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
1067 }
744 1068
745 REG_WRITE(ah, AR_PHY_POWER_TX_SUB, 1069 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
746 ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6) 1070 for (j = 0; j < 32; j++) {
747 | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0)); 1071 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) |
1072 ((pdadcValues[4 * j + 1] & 0xFF) << 8) |
1073 ((pdadcValues[4 * j + 2] & 0xFF) << 16)|
1074 ((pdadcValues[4 * j + 3] & 0xFF) << 24);
1075 REG_WRITE(ah, regOffset, reg32);
748 1076
749 i = rate6mb; 1077 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1078 "PDADC (%d,%4x): %4.4x %8.8x\n",
1079 i, regChainOffset, regOffset,
1080 reg32);
1081 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1082 "PDADC: Chain %d | PDADC %3d "
1083 "Value %3d | PDADC %3d Value %3d | "
1084 "PDADC %3d Value %3d | PDADC %3d "
1085 "Value %3d |\n",
1086 i, 4 * j, pdadcValues[4 * j],
1087 4 * j + 1, pdadcValues[4 * j + 1],
1088 4 * j + 2, pdadcValues[4 * j + 2],
1089 4 * j + 3,
1090 pdadcValues[4 * j + 3]);
750 1091
751 if (IS_CHAN_HT40(chan)) 1092 regOffset += 4;
752 i = rateHt40_0; 1093 }
753 else if (IS_CHAN_HT20(chan)) 1094 }
754 i = rateHt20_0; 1095 }
755 1096
756 if (AR_SREV_9280_10_OR_LATER(ah)) 1097 *pTxPowerIndexOffset = 0;
757 ah->ah_maxPowerLevel =
758 ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2;
759 else
760 ah->ah_maxPowerLevel = ratesArray[i];
761 1098
762 return 0; 1099 return true;
763} 1100}
764 1101
765void ath9k_hw_set_addac(struct ath_hal *ah, struct ath9k_channel *chan) 1102static bool ath9k_hw_set_4k_power_cal_table(struct ath_hal *ah,
1103 struct ath9k_channel *chan,
1104 int16_t *pTxPowerIndexOffset)
766{ 1105{
767 struct modal_eep_header *pModal;
768 struct ath_hal_5416 *ahp = AH5416(ah); 1106 struct ath_hal_5416 *ahp = AH5416(ah);
769 struct ar5416_eeprom *eep = &ahp->ah_eeprom; 1107 struct ar5416_eeprom_4k *pEepData = &ahp->ah_eeprom.map4k;
770 u8 biaslevel; 1108 struct cal_data_per_freq_4k *pRawDataset;
1109 u8 *pCalBChans = NULL;
1110 u16 pdGainOverlap_t2;
1111 static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
1112 u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
1113 u16 numPiers, i, j;
1114 int16_t tMinCalPower;
1115 u16 numXpdGain, xpdMask;
1116 u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
1117 u32 reg32, regOffset, regChainOffset;
771 1118
772 if (ah->ah_macVersion != AR_SREV_VERSION_9160) 1119 xpdMask = pEepData->modalHeader.xpdGain;
773 return;
774 1120
775 if (ar5416_get_eep_rev(ahp) < AR5416_EEP_MINOR_VER_7) 1121 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
776 return; 1122 AR5416_EEP_MINOR_VER_2) {
1123 pdGainOverlap_t2 =
1124 pEepData->modalHeader.pdGainOverlap;
1125 } else {
1126 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
1127 AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
1128 }
777 1129
778 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]); 1130 pCalBChans = pEepData->calFreqPier2G;
1131 numPiers = AR5416_NUM_2G_CAL_PIERS;
779 1132
780 if (pModal->xpaBiasLvl != 0xff) { 1133 numXpdGain = 0;
781 biaslevel = pModal->xpaBiasLvl;
782 } else {
783 u16 resetFreqBin, freqBin, freqCount = 0;
784 struct chan_centers centers;
785 1134
786 ath9k_hw_get_channel_centers(ah, chan, &centers); 1135 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
1136 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
1137 if (numXpdGain >= AR5416_NUM_PD_GAINS)
1138 break;
1139 xpdGainValues[numXpdGain] =
1140 (u16)(AR5416_PD_GAINS_IN_MASK - i);
1141 numXpdGain++;
1142 }
1143 }
787 1144
788 resetFreqBin = FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)); 1145 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
789 freqBin = pModal->xpaBiasLvlFreq[0] & 0xff; 1146 (numXpdGain - 1) & 0x3);
790 biaslevel = (u8) (pModal->xpaBiasLvlFreq[0] >> 14); 1147 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
1148 xpdGainValues[0]);
1149 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
1150 xpdGainValues[1]);
1151 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
1152 xpdGainValues[2]);
791 1153
792 freqCount++; 1154 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
1155 if (AR_SREV_5416_V20_OR_LATER(ah) &&
1156 (ahp->ah_rxchainmask == 5 || ahp->ah_txchainmask == 5) &&
1157 (i != 0)) {
1158 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
1159 } else
1160 regChainOffset = i * 0x1000;
793 1161
794 while (freqCount < 3) { 1162 if (pEepData->baseEepHeader.txMask & (1 << i)) {
795 if (pModal->xpaBiasLvlFreq[freqCount] == 0x0) 1163 pRawDataset = pEepData->calPierData2G[i];
796 break;
797 1164
798 freqBin = pModal->xpaBiasLvlFreq[freqCount] & 0xff; 1165 ath9k_hw_get_4k_gain_boundaries_pdadcs(ah, chan,
799 if (resetFreqBin >= freqBin) { 1166 pRawDataset, pCalBChans,
800 biaslevel = (u8)(pModal->xpaBiasLvlFreq[freqCount] >> 14); 1167 numPiers, pdGainOverlap_t2,
801 } else { 1168 &tMinCalPower, gainBoundaries,
802 break; 1169 pdadcValues, numXpdGain);
1170
1171 if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) {
1172 REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,
1173 SM(pdGainOverlap_t2,
1174 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
1175 | SM(gainBoundaries[0],
1176 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
1177 | SM(gainBoundaries[1],
1178 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
1179 | SM(gainBoundaries[2],
1180 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
1181 | SM(gainBoundaries[3],
1182 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
1183 }
1184
1185 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
1186 for (j = 0; j < 32; j++) {
1187 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) |
1188 ((pdadcValues[4 * j + 1] & 0xFF) << 8) |
1189 ((pdadcValues[4 * j + 2] & 0xFF) << 16)|
1190 ((pdadcValues[4 * j + 3] & 0xFF) << 24);
1191 REG_WRITE(ah, regOffset, reg32);
1192
1193 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1194 "PDADC (%d,%4x): %4.4x %8.8x\n",
1195 i, regChainOffset, regOffset,
1196 reg32);
1197 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1198 "PDADC: Chain %d | "
1199 "PDADC %3d Value %3d | "
1200 "PDADC %3d Value %3d | "
1201 "PDADC %3d Value %3d | "
1202 "PDADC %3d Value %3d |\n",
1203 i, 4 * j, pdadcValues[4 * j],
1204 4 * j + 1, pdadcValues[4 * j + 1],
1205 4 * j + 2, pdadcValues[4 * j + 2],
1206 4 * j + 3,
1207 pdadcValues[4 * j + 3]);
1208
1209 regOffset += 4;
803 } 1210 }
804 freqCount++;
805 } 1211 }
806 } 1212 }
807 1213
808 if (IS_CHAN_2GHZ(chan)) { 1214 *pTxPowerIndexOffset = 0;
809 INI_RA(&ahp->ah_iniAddac, 7, 1) = 1215
810 (INI_RA(&ahp->ah_iniAddac, 7, 1) & (~0x18)) | biaslevel << 3; 1216 return true;
811 } else {
812 INI_RA(&ahp->ah_iniAddac, 6, 1) =
813 (INI_RA(&ahp->ah_iniAddac, 6, 1) & (~0xc0)) | biaslevel << 6;
814 }
815} 1217}
816 1218
817bool ath9k_hw_set_power_per_rate_table(struct ath_hal *ah, 1219bool ath9k_hw_set_def_power_per_rate_table(struct ath_hal *ah,
818 struct ath9k_channel *chan, 1220 struct ath9k_channel *chan,
819 int16_t *ratesArray, 1221 int16_t *ratesArray,
820 u16 cfgCtl, 1222 u16 cfgCtl,
821 u8 AntennaReduction, 1223 u16 AntennaReduction,
822 u8 twiceMaxRegulatoryPower, 1224 u16 twiceMaxRegulatoryPower,
823 u8 powerLimit) 1225 u16 powerLimit)
824{ 1226{
1227#define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
1228#define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10 /* 10*log10(3)*2 */
1229
825 struct ath_hal_5416 *ahp = AH5416(ah); 1230 struct ath_hal_5416 *ahp = AH5416(ah);
826 struct ar5416_eeprom *pEepData = &ahp->ah_eeprom; 1231 struct ar5416_eeprom_def *pEepData = &ahp->ah_eeprom.def;
827 u8 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 1232 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
828 static const u16 tpScaleReductionTable[5] = 1233 static const u16 tpScaleReductionTable[5] =
829 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER }; 1234 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
830 1235
831 int i; 1236 int i;
832 int8_t twiceLargestAntenna; 1237 int16_t twiceLargestAntenna;
833 struct cal_ctl_data *rep; 1238 struct cal_ctl_data *rep;
834 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = { 1239 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
835 0, { 0, 0, 0, 0} 1240 0, { 0, 0, 0, 0}
@@ -841,7 +1246,7 @@ bool ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
841 struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = { 1246 struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
842 0, {0, 0, 0, 0} 1247 0, {0, 0, 0, 0}
843 }; 1248 };
844 u8 scaledPower = 0, minCtlPower, maxRegAllowedPower; 1249 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
845 u16 ctlModesFor11a[] = 1250 u16 ctlModesFor11a[] =
846 { CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 }; 1251 { CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 };
847 u16 ctlModesFor11g[] = 1252 u16 ctlModesFor11g[] =
@@ -851,7 +1256,7 @@ bool ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
851 u16 numCtlModes, *pCtlMode, ctlMode, freq; 1256 u16 numCtlModes, *pCtlMode, ctlMode, freq;
852 struct chan_centers centers; 1257 struct chan_centers centers;
853 int tx_chainmask; 1258 int tx_chainmask;
854 u8 twiceMinEdgePower; 1259 u16 twiceMinEdgePower;
855 1260
856 tx_chainmask = ahp->ah_txchainmask; 1261 tx_chainmask = ahp->ah_txchainmask;
857 1262
@@ -867,7 +1272,8 @@ bool ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
867 pEepData->modalHeader 1272 pEepData->modalHeader
868 [IS_CHAN_2GHZ(chan)].antennaGainCh[2]); 1273 [IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
869 1274
870 twiceLargestAntenna = (int8_t)min(AntennaReduction - twiceLargestAntenna, 0); 1275 twiceLargestAntenna = (int16_t)min(AntennaReduction -
1276 twiceLargestAntenna, 0);
871 1277
872 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna; 1278 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
873 1279
@@ -882,16 +1288,14 @@ bool ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
882 case 1: 1288 case 1:
883 break; 1289 break;
884 case 2: 1290 case 2:
885 scaledPower -= 1291 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
886 pEepData->modalHeader[IS_CHAN_2GHZ(chan)].pwrDecreaseFor2Chain;
887 break; 1292 break;
888 case 3: 1293 case 3:
889 scaledPower -= 1294 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
890 pEepData->modalHeader[IS_CHAN_2GHZ(chan)].pwrDecreaseFor3Chain;
891 break; 1295 break;
892 } 1296 }
893 1297
894 scaledPower = max(0, (int32_t) scaledPower); 1298 scaledPower = max((u16)0, scaledPower);
895 1299
896 if (IS_CHAN_2GHZ(chan)) { 1300 if (IS_CHAN_2GHZ(chan)) {
897 numCtlModes = ARRAY_SIZE(ctlModesFor11g) - 1301 numCtlModes = ARRAY_SIZE(ctlModesFor11g) -
@@ -990,7 +1394,7 @@ bool ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
990 1394
991 twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq, 1395 twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq,
992 rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1], 1396 rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1],
993 IS_CHAN_2GHZ(chan)); 1397 IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES);
994 1398
995 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, 1399 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
996 " MATCH-EE_IDX %d: ch %d is2 %d " 1400 " MATCH-EE_IDX %d: ch %d is2 %d "
@@ -1021,7 +1425,7 @@ bool ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
1021 case CTL_11B: 1425 case CTL_11B:
1022 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) { 1426 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
1023 targetPowerCck.tPow2x[i] = 1427 targetPowerCck.tPow2x[i] =
1024 min(targetPowerCck.tPow2x[i], 1428 min((u16)targetPowerCck.tPow2x[i],
1025 minCtlPower); 1429 minCtlPower);
1026 } 1430 }
1027 break; 1431 break;
@@ -1029,7 +1433,7 @@ bool ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
1029 case CTL_11G: 1433 case CTL_11G:
1030 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) { 1434 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
1031 targetPowerOfdm.tPow2x[i] = 1435 targetPowerOfdm.tPow2x[i] =
1032 min(targetPowerOfdm.tPow2x[i], 1436 min((u16)targetPowerOfdm.tPow2x[i],
1033 minCtlPower); 1437 minCtlPower);
1034 } 1438 }
1035 break; 1439 break;
@@ -1037,24 +1441,26 @@ bool ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
1037 case CTL_2GHT20: 1441 case CTL_2GHT20:
1038 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) { 1442 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
1039 targetPowerHt20.tPow2x[i] = 1443 targetPowerHt20.tPow2x[i] =
1040 min(targetPowerHt20.tPow2x[i], 1444 min((u16)targetPowerHt20.tPow2x[i],
1041 minCtlPower); 1445 minCtlPower);
1042 } 1446 }
1043 break; 1447 break;
1044 case CTL_11B_EXT: 1448 case CTL_11B_EXT:
1045 targetPowerCckExt.tPow2x[0] = 1449 targetPowerCckExt.tPow2x[0] = min((u16)
1046 min(targetPowerCckExt.tPow2x[0], minCtlPower); 1450 targetPowerCckExt.tPow2x[0],
1451 minCtlPower);
1047 break; 1452 break;
1048 case CTL_11A_EXT: 1453 case CTL_11A_EXT:
1049 case CTL_11G_EXT: 1454 case CTL_11G_EXT:
1050 targetPowerOfdmExt.tPow2x[0] = 1455 targetPowerOfdmExt.tPow2x[0] = min((u16)
1051 min(targetPowerOfdmExt.tPow2x[0], minCtlPower); 1456 targetPowerOfdmExt.tPow2x[0],
1457 minCtlPower);
1052 break; 1458 break;
1053 case CTL_5GHT40: 1459 case CTL_5GHT40:
1054 case CTL_2GHT40: 1460 case CTL_2GHT40:
1055 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) { 1461 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1056 targetPowerHt40.tPow2x[i] = 1462 targetPowerHt40.tPow2x[i] =
1057 min(targetPowerHt40.tPow2x[i], 1463 min((u16)targetPowerHt40.tPow2x[i],
1058 minCtlPower); 1464 minCtlPower);
1059 } 1465 }
1060 break; 1466 break;
@@ -1101,139 +1507,623 @@ bool ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
1101 return true; 1507 return true;
1102} 1508}
1103 1509
1104bool ath9k_hw_set_power_cal_table(struct ath_hal *ah, 1510bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hal *ah,
1105 struct ath9k_channel *chan, 1511 struct ath9k_channel *chan,
1106 int16_t *pTxPowerIndexOffset) 1512 int16_t *ratesArray,
1513 u16 cfgCtl,
1514 u16 AntennaReduction,
1515 u16 twiceMaxRegulatoryPower,
1516 u16 powerLimit)
1107{ 1517{
1108 struct ath_hal_5416 *ahp = AH5416(ah); 1518 struct ath_hal_5416 *ahp = AH5416(ah);
1109 struct ar5416_eeprom *pEepData = &ahp->ah_eeprom; 1519 struct ar5416_eeprom_4k *pEepData = &ahp->ah_eeprom.map4k;
1110 struct cal_data_per_freq *pRawDataset; 1520 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
1111 u8 *pCalBChans = NULL; 1521 static const u16 tpScaleReductionTable[5] =
1112 u16 pdGainOverlap_t2; 1522 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
1113 static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
1114 u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
1115 u16 numPiers, i, j;
1116 int16_t tMinCalPower;
1117 u16 numXpdGain, xpdMask;
1118 u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
1119 u32 reg32, regOffset, regChainOffset;
1120 int16_t modalIdx;
1121 1523
1122 modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0; 1524 int i;
1123 xpdMask = pEepData->modalHeader[modalIdx].xpdGain; 1525 int16_t twiceLargestAntenna;
1526 struct cal_ctl_data_4k *rep;
1527 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
1528 0, { 0, 0, 0, 0}
1529 };
1530 struct cal_target_power_leg targetPowerOfdmExt = {
1531 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
1532 0, { 0, 0, 0, 0 }
1533 };
1534 struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
1535 0, {0, 0, 0, 0}
1536 };
1537 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
1538 u16 ctlModesFor11g[] =
1539 { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
1540 CTL_2GHT40
1541 };
1542 u16 numCtlModes, *pCtlMode, ctlMode, freq;
1543 struct chan_centers centers;
1544 int tx_chainmask;
1545 u16 twiceMinEdgePower;
1546
1547 tx_chainmask = ahp->ah_txchainmask;
1548
1549 ath9k_hw_get_channel_centers(ah, chan, &centers);
1550
1551 twiceLargestAntenna = pEepData->modalHeader.antennaGainCh[0];
1552
1553 twiceLargestAntenna = (int16_t)min(AntennaReduction -
1554 twiceLargestAntenna, 0);
1555
1556 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
1557
1558 if (ah->ah_tpScale != ATH9K_TP_SCALE_MAX) {
1559 maxRegAllowedPower -=
1560 (tpScaleReductionTable[(ah->ah_tpScale)] * 2);
1561 }
1562
1563 scaledPower = min(powerLimit, maxRegAllowedPower);
1564 scaledPower = max((u16)0, scaledPower);
1565
1566 numCtlModes = ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40;
1567 pCtlMode = ctlModesFor11g;
1568
1569 ath9k_hw_get_legacy_target_powers(ah, chan,
1570 pEepData->calTargetPowerCck,
1571 AR5416_NUM_2G_CCK_TARGET_POWERS,
1572 &targetPowerCck, 4, false);
1573 ath9k_hw_get_legacy_target_powers(ah, chan,
1574 pEepData->calTargetPower2G,
1575 AR5416_NUM_2G_20_TARGET_POWERS,
1576 &targetPowerOfdm, 4, false);
1577 ath9k_hw_get_target_powers(ah, chan,
1578 pEepData->calTargetPower2GHT20,
1579 AR5416_NUM_2G_20_TARGET_POWERS,
1580 &targetPowerHt20, 8, false);
1581
1582 if (IS_CHAN_HT40(chan)) {
1583 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
1584 ath9k_hw_get_target_powers(ah, chan,
1585 pEepData->calTargetPower2GHT40,
1586 AR5416_NUM_2G_40_TARGET_POWERS,
1587 &targetPowerHt40, 8, true);
1588 ath9k_hw_get_legacy_target_powers(ah, chan,
1589 pEepData->calTargetPowerCck,
1590 AR5416_NUM_2G_CCK_TARGET_POWERS,
1591 &targetPowerCckExt, 4, true);
1592 ath9k_hw_get_legacy_target_powers(ah, chan,
1593 pEepData->calTargetPower2G,
1594 AR5416_NUM_2G_20_TARGET_POWERS,
1595 &targetPowerOfdmExt, 4, true);
1596 }
1597
1598 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
1599 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
1600 (pCtlMode[ctlMode] == CTL_2GHT40);
1601 if (isHt40CtlMode)
1602 freq = centers.synth_center;
1603 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
1604 freq = centers.ext_center;
1605 else
1606 freq = centers.ctl_center;
1607
1608 if (ar5416_get_eep_ver(ahp) == 14 &&
1609 ar5416_get_eep_rev(ahp) <= 2)
1610 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
1611
1612 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
1613 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, "
1614 "EXT_ADDITIVE %d\n",
1615 ctlMode, numCtlModes, isHt40CtlMode,
1616 (pCtlMode[ctlMode] & EXT_ADDITIVE));
1617
1618 for (i = 0; (i < AR5416_NUM_CTLS) &&
1619 pEepData->ctlIndex[i]; i++) {
1620 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
1621 " LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
1622 "pCtlMode 0x%2.2x ctlIndex 0x%2.2x "
1623 "chan %d\n",
1624 i, cfgCtl, pCtlMode[ctlMode],
1625 pEepData->ctlIndex[i], chan->channel);
1626
1627 if ((((cfgCtl & ~CTL_MODE_M) |
1628 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
1629 pEepData->ctlIndex[i]) ||
1630 (((cfgCtl & ~CTL_MODE_M) |
1631 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
1632 ((pEepData->ctlIndex[i] & CTL_MODE_M) |
1633 SD_NO_CTL))) {
1634 rep = &(pEepData->ctlData[i]);
1635
1636 twiceMinEdgePower =
1637 ath9k_hw_get_max_edge_power(freq,
1638 rep->ctlEdges[ar5416_get_ntxchains
1639 (tx_chainmask) - 1],
1640 IS_CHAN_2GHZ(chan),
1641 AR5416_EEP4K_NUM_BAND_EDGES);
1642
1643 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
1644 " MATCH-EE_IDX %d: ch %d is2 %d "
1645 "2xMinEdge %d chainmask %d chains %d\n",
1646 i, freq, IS_CHAN_2GHZ(chan),
1647 twiceMinEdgePower, tx_chainmask,
1648 ar5416_get_ntxchains
1649 (tx_chainmask));
1650 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
1651 twiceMaxEdgePower =
1652 min(twiceMaxEdgePower,
1653 twiceMinEdgePower);
1654 } else {
1655 twiceMaxEdgePower = twiceMinEdgePower;
1656 break;
1657 }
1658 }
1659 }
1660
1661 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
1662
1663 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
1664 " SEL-Min ctlMode %d pCtlMode %d "
1665 "2xMaxEdge %d sP %d minCtlPwr %d\n",
1666 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
1667 scaledPower, minCtlPower);
1668
1669 switch (pCtlMode[ctlMode]) {
1670 case CTL_11B:
1671 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x);
1672 i++) {
1673 targetPowerCck.tPow2x[i] =
1674 min((u16)targetPowerCck.tPow2x[i],
1675 minCtlPower);
1676 }
1677 break;
1678 case CTL_11G:
1679 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x);
1680 i++) {
1681 targetPowerOfdm.tPow2x[i] =
1682 min((u16)targetPowerOfdm.tPow2x[i],
1683 minCtlPower);
1684 }
1685 break;
1686 case CTL_2GHT20:
1687 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x);
1688 i++) {
1689 targetPowerHt20.tPow2x[i] =
1690 min((u16)targetPowerHt20.tPow2x[i],
1691 minCtlPower);
1692 }
1693 break;
1694 case CTL_11B_EXT:
1695 targetPowerCckExt.tPow2x[0] = min((u16)
1696 targetPowerCckExt.tPow2x[0],
1697 minCtlPower);
1698 break;
1699 case CTL_11G_EXT:
1700 targetPowerOfdmExt.tPow2x[0] = min((u16)
1701 targetPowerOfdmExt.tPow2x[0],
1702 minCtlPower);
1703 break;
1704 case CTL_2GHT40:
1705 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x);
1706 i++) {
1707 targetPowerHt40.tPow2x[i] =
1708 min((u16)targetPowerHt40.tPow2x[i],
1709 minCtlPower);
1710 }
1711 break;
1712 default:
1713 break;
1714 }
1715 }
1716
1717 ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] =
1718 ratesArray[rate18mb] = ratesArray[rate24mb] =
1719 targetPowerOfdm.tPow2x[0];
1720 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
1721 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
1722 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
1723 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
1724
1725 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
1726 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
1727
1728 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
1729 ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1];
1730 ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2];
1731 ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3];
1732
1733 if (IS_CHAN_HT40(chan)) {
1734 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1735 ratesArray[rateHt40_0 + i] =
1736 targetPowerHt40.tPow2x[i];
1737 }
1738 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
1739 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
1740 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
1741 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
1742 }
1743 return true;
1744}
1745
1746static int ath9k_hw_def_set_txpower(struct ath_hal *ah,
1747 struct ath9k_channel *chan,
1748 u16 cfgCtl,
1749 u8 twiceAntennaReduction,
1750 u8 twiceMaxRegulatoryPower,
1751 u8 powerLimit)
1752{
1753 struct ath_hal_5416 *ahp = AH5416(ah);
1754 struct ar5416_eeprom_def *pEepData = &ahp->ah_eeprom.def;
1755 struct modal_eep_header *pModal =
1756 &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]);
1757 int16_t ratesArray[Ar5416RateSize];
1758 int16_t txPowerIndexOffset = 0;
1759 u8 ht40PowerIncForPdadc = 2;
1760 int i;
1761
1762 memset(ratesArray, 0, sizeof(ratesArray));
1124 1763
1125 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 1764 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1126 AR5416_EEP_MINOR_VER_2) { 1765 AR5416_EEP_MINOR_VER_2) {
1127 pdGainOverlap_t2 = 1766 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
1128 pEepData->modalHeader[modalIdx].pdGainOverlap; 1767 }
1129 } else { 1768
1130 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5), 1769 if (!ath9k_hw_set_def_power_per_rate_table(ah, chan,
1131 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)); 1770 &ratesArray[0], cfgCtl,
1771 twiceAntennaReduction,
1772 twiceMaxRegulatoryPower,
1773 powerLimit)) {
1774 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1775 "ath9k_hw_set_txpower: unable to set "
1776 "tx power per rate table\n");
1777 return -EIO;
1778 }
1779
1780 if (!ath9k_hw_set_def_power_cal_table(ah, chan, &txPowerIndexOffset)) {
1781 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1782 "ath9k_hw_set_txpower: unable to set power table\n");
1783 return -EIO;
1784 }
1785
1786 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
1787 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
1788 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
1789 ratesArray[i] = AR5416_MAX_RATE_POWER;
1132 } 1790 }
1133 1791
1792 if (AR_SREV_9280_10_OR_LATER(ah)) {
1793 for (i = 0; i < Ar5416RateSize; i++)
1794 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2;
1795 }
1796
1797 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
1798 ATH9K_POW_SM(ratesArray[rate18mb], 24)
1799 | ATH9K_POW_SM(ratesArray[rate12mb], 16)
1800 | ATH9K_POW_SM(ratesArray[rate9mb], 8)
1801 | ATH9K_POW_SM(ratesArray[rate6mb], 0));
1802 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
1803 ATH9K_POW_SM(ratesArray[rate54mb], 24)
1804 | ATH9K_POW_SM(ratesArray[rate48mb], 16)
1805 | ATH9K_POW_SM(ratesArray[rate36mb], 8)
1806 | ATH9K_POW_SM(ratesArray[rate24mb], 0));
1807
1134 if (IS_CHAN_2GHZ(chan)) { 1808 if (IS_CHAN_2GHZ(chan)) {
1135 pCalBChans = pEepData->calFreqPier2G; 1809 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1136 numPiers = AR5416_NUM_2G_CAL_PIERS; 1810 ATH9K_POW_SM(ratesArray[rate2s], 24)
1137 } else { 1811 | ATH9K_POW_SM(ratesArray[rate2l], 16)
1138 pCalBChans = pEepData->calFreqPier5G; 1812 | ATH9K_POW_SM(ratesArray[rateXr], 8)
1139 numPiers = AR5416_NUM_5G_CAL_PIERS; 1813 | ATH9K_POW_SM(ratesArray[rate1l], 0));
1814 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1815 ATH9K_POW_SM(ratesArray[rate11s], 24)
1816 | ATH9K_POW_SM(ratesArray[rate11l], 16)
1817 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
1818 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
1140 } 1819 }
1141 1820
1142 numXpdGain = 0; 1821 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
1822 ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
1823 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
1824 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
1825 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
1826 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
1827 ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
1828 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
1829 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
1830 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
1143 1831
1144 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) { 1832 if (IS_CHAN_HT40(chan)) {
1145 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) { 1833 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
1146 if (numXpdGain >= AR5416_NUM_PD_GAINS) 1834 ATH9K_POW_SM(ratesArray[rateHt40_3] +
1147 break; 1835 ht40PowerIncForPdadc, 24)
1148 xpdGainValues[numXpdGain] = 1836 | ATH9K_POW_SM(ratesArray[rateHt40_2] +
1149 (u16)(AR5416_PD_GAINS_IN_MASK - i); 1837 ht40PowerIncForPdadc, 16)
1150 numXpdGain++; 1838 | ATH9K_POW_SM(ratesArray[rateHt40_1] +
1151 } 1839 ht40PowerIncForPdadc, 8)
1840 | ATH9K_POW_SM(ratesArray[rateHt40_0] +
1841 ht40PowerIncForPdadc, 0));
1842 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
1843 ATH9K_POW_SM(ratesArray[rateHt40_7] +
1844 ht40PowerIncForPdadc, 24)
1845 | ATH9K_POW_SM(ratesArray[rateHt40_6] +
1846 ht40PowerIncForPdadc, 16)
1847 | ATH9K_POW_SM(ratesArray[rateHt40_5] +
1848 ht40PowerIncForPdadc, 8)
1849 | ATH9K_POW_SM(ratesArray[rateHt40_4] +
1850 ht40PowerIncForPdadc, 0));
1851
1852 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1853 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
1854 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
1855 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
1856 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
1152 } 1857 }
1153 1858
1154 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN, 1859 REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
1155 (numXpdGain - 1) & 0x3); 1860 ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6)
1156 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1, 1861 | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0));
1157 xpdGainValues[0]);
1158 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
1159 xpdGainValues[1]);
1160 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
1161 xpdGainValues[2]);
1162 1862
1163 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 1863 i = rate6mb;
1164 if (AR_SREV_5416_V20_OR_LATER(ah) &&
1165 (ahp->ah_rxchainmask == 5 || ahp->ah_txchainmask == 5) &&
1166 (i != 0)) {
1167 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
1168 } else
1169 regChainOffset = i * 0x1000;
1170 1864
1171 if (pEepData->baseEepHeader.txMask & (1 << i)) { 1865 if (IS_CHAN_HT40(chan))
1172 if (IS_CHAN_2GHZ(chan)) 1866 i = rateHt40_0;
1173 pRawDataset = pEepData->calPierData2G[i]; 1867 else if (IS_CHAN_HT20(chan))
1174 else 1868 i = rateHt20_0;
1175 pRawDataset = pEepData->calPierData5G[i];
1176 1869
1177 ath9k_hw_get_gain_boundaries_pdadcs(ah, chan, 1870 if (AR_SREV_9280_10_OR_LATER(ah))
1178 pRawDataset, pCalBChans, 1871 ah->ah_maxPowerLevel =
1179 numPiers, pdGainOverlap_t2, 1872 ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2;
1180 &tMinCalPower, gainBoundaries, 1873 else
1181 pdadcValues, numXpdGain); 1874 ah->ah_maxPowerLevel = ratesArray[i];
1182 1875
1183 if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) { 1876 return 0;
1184 REG_WRITE(ah, 1877}
1185 AR_PHY_TPCRG5 + regChainOffset,
1186 SM(pdGainOverlap_t2,
1187 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
1188 | SM(gainBoundaries[0],
1189 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
1190 | SM(gainBoundaries[1],
1191 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
1192 | SM(gainBoundaries[2],
1193 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
1194 | SM(gainBoundaries[3],
1195 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
1196 }
1197 1878
1198 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset; 1879static int ath9k_hw_4k_set_txpower(struct ath_hal *ah,
1199 for (j = 0; j < 32; j++) { 1880 struct ath9k_channel *chan,
1200 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) | 1881 u16 cfgCtl,
1201 ((pdadcValues[4 * j + 1] & 0xFF) << 8) | 1882 u8 twiceAntennaReduction,
1202 ((pdadcValues[4 * j + 2] & 0xFF) << 16) | 1883 u8 twiceMaxRegulatoryPower,
1203 ((pdadcValues[4 * j + 3] & 0xFF) << 24); 1884 u8 powerLimit)
1204 REG_WRITE(ah, regOffset, reg32); 1885{
1886 struct ath_hal_5416 *ahp = AH5416(ah);
1887 struct ar5416_eeprom_4k *pEepData = &ahp->ah_eeprom.map4k;
1888 struct modal_eep_4k_header *pModal = &pEepData->modalHeader;
1889 int16_t ratesArray[Ar5416RateSize];
1890 int16_t txPowerIndexOffset = 0;
1891 u8 ht40PowerIncForPdadc = 2;
1892 int i;
1205 1893
1206 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, 1894 memset(ratesArray, 0, sizeof(ratesArray));
1207 "PDADC (%d,%4x): %4.4x %8.8x\n",
1208 i, regChainOffset, regOffset,
1209 reg32);
1210 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1211 "PDADC: Chain %d | PDADC %3d Value %3d | "
1212 "PDADC %3d Value %3d | PDADC %3d Value %3d | "
1213 "PDADC %3d Value %3d |\n",
1214 i, 4 * j, pdadcValues[4 * j],
1215 4 * j + 1, pdadcValues[4 * j + 1],
1216 4 * j + 2, pdadcValues[4 * j + 2],
1217 4 * j + 3,
1218 pdadcValues[4 * j + 3]);
1219 1895
1220 regOffset += 4; 1896 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1221 } 1897 AR5416_EEP_MINOR_VER_2) {
1898 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
1899 }
1900
1901 if (!ath9k_hw_set_4k_power_per_rate_table(ah, chan,
1902 &ratesArray[0], cfgCtl,
1903 twiceAntennaReduction,
1904 twiceMaxRegulatoryPower,
1905 powerLimit)) {
1906 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1907 "ath9k_hw_set_txpower: unable to set "
1908 "tx power per rate table\n");
1909 return -EIO;
1910 }
1911
1912 if (!ath9k_hw_set_4k_power_cal_table(ah, chan, &txPowerIndexOffset)) {
1913 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1914 "ath9k_hw_set_txpower: unable to set power table\n");
1915 return -EIO;
1916 }
1917
1918 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
1919 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
1920 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
1921 ratesArray[i] = AR5416_MAX_RATE_POWER;
1922 }
1923
1924 if (AR_SREV_9280_10_OR_LATER(ah)) {
1925 for (i = 0; i < Ar5416RateSize; i++)
1926 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2;
1927 }
1928
1929 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
1930 ATH9K_POW_SM(ratesArray[rate18mb], 24)
1931 | ATH9K_POW_SM(ratesArray[rate12mb], 16)
1932 | ATH9K_POW_SM(ratesArray[rate9mb], 8)
1933 | ATH9K_POW_SM(ratesArray[rate6mb], 0));
1934 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
1935 ATH9K_POW_SM(ratesArray[rate54mb], 24)
1936 | ATH9K_POW_SM(ratesArray[rate48mb], 16)
1937 | ATH9K_POW_SM(ratesArray[rate36mb], 8)
1938 | ATH9K_POW_SM(ratesArray[rate24mb], 0));
1939
1940 if (IS_CHAN_2GHZ(chan)) {
1941 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1942 ATH9K_POW_SM(ratesArray[rate2s], 24)
1943 | ATH9K_POW_SM(ratesArray[rate2l], 16)
1944 | ATH9K_POW_SM(ratesArray[rateXr], 8)
1945 | ATH9K_POW_SM(ratesArray[rate1l], 0));
1946 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1947 ATH9K_POW_SM(ratesArray[rate11s], 24)
1948 | ATH9K_POW_SM(ratesArray[rate11l], 16)
1949 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
1950 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
1951 }
1952
1953 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
1954 ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
1955 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
1956 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
1957 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
1958 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
1959 ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
1960 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
1961 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
1962 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
1963
1964 if (IS_CHAN_HT40(chan)) {
1965 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
1966 ATH9K_POW_SM(ratesArray[rateHt40_3] +
1967 ht40PowerIncForPdadc, 24)
1968 | ATH9K_POW_SM(ratesArray[rateHt40_2] +
1969 ht40PowerIncForPdadc, 16)
1970 | ATH9K_POW_SM(ratesArray[rateHt40_1] +
1971 ht40PowerIncForPdadc, 8)
1972 | ATH9K_POW_SM(ratesArray[rateHt40_0] +
1973 ht40PowerIncForPdadc, 0));
1974 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
1975 ATH9K_POW_SM(ratesArray[rateHt40_7] +
1976 ht40PowerIncForPdadc, 24)
1977 | ATH9K_POW_SM(ratesArray[rateHt40_6] +
1978 ht40PowerIncForPdadc, 16)
1979 | ATH9K_POW_SM(ratesArray[rateHt40_5] +
1980 ht40PowerIncForPdadc, 8)
1981 | ATH9K_POW_SM(ratesArray[rateHt40_4] +
1982 ht40PowerIncForPdadc, 0));
1983
1984 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1985 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
1986 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
1987 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
1988 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
1989 }
1990
1991 i = rate6mb;
1992
1993 if (IS_CHAN_HT40(chan))
1994 i = rateHt40_0;
1995 else if (IS_CHAN_HT20(chan))
1996 i = rateHt20_0;
1997
1998 if (AR_SREV_9280_10_OR_LATER(ah))
1999 ah->ah_maxPowerLevel =
2000 ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2;
2001 else
2002 ah->ah_maxPowerLevel = ratesArray[i];
2003
2004 return 0;
2005}
2006
2007int (*ath9k_set_txpower[]) (struct ath_hal *,
2008 struct ath9k_channel *,
2009 u16, u8, u8, u8) = {
2010 ath9k_hw_def_set_txpower,
2011 ath9k_hw_4k_set_txpower
2012};
2013
2014int ath9k_hw_set_txpower(struct ath_hal *ah,
2015 struct ath9k_channel *chan,
2016 u16 cfgCtl,
2017 u8 twiceAntennaReduction,
2018 u8 twiceMaxRegulatoryPower,
2019 u8 powerLimit)
2020{
2021 struct ath_hal_5416 *ahp = AH5416(ah);
2022
2023 return ath9k_set_txpower[ahp->ah_eep_map](ah, chan, cfgCtl,
2024 twiceAntennaReduction, twiceMaxRegulatoryPower,
2025 powerLimit);
2026}
2027
2028static void ath9k_hw_set_def_addac(struct ath_hal *ah,
2029 struct ath9k_channel *chan)
2030{
2031#define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt])
2032 struct modal_eep_header *pModal;
2033 struct ath_hal_5416 *ahp = AH5416(ah);
2034 struct ar5416_eeprom_def *eep = &ahp->ah_eeprom.def;
2035 u8 biaslevel;
2036
2037 if (ah->ah_macVersion != AR_SREV_VERSION_9160)
2038 return;
2039
2040 if (ar5416_get_eep_rev(ahp) < AR5416_EEP_MINOR_VER_7)
2041 return;
2042
2043 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
2044
2045 if (pModal->xpaBiasLvl != 0xff) {
2046 biaslevel = pModal->xpaBiasLvl;
2047 } else {
2048 u16 resetFreqBin, freqBin, freqCount = 0;
2049 struct chan_centers centers;
2050
2051 ath9k_hw_get_channel_centers(ah, chan, &centers);
2052
2053 resetFreqBin = FREQ2FBIN(centers.synth_center,
2054 IS_CHAN_2GHZ(chan));
2055 freqBin = XPA_LVL_FREQ(0) & 0xff;
2056 biaslevel = (u8) (XPA_LVL_FREQ(0) >> 14);
2057
2058 freqCount++;
2059
2060 while (freqCount < 3) {
2061 if (XPA_LVL_FREQ(freqCount) == 0x0)
2062 break;
2063
2064 freqBin = XPA_LVL_FREQ(freqCount) & 0xff;
2065 if (resetFreqBin >= freqBin)
2066 biaslevel = (u8)(XPA_LVL_FREQ(freqCount) >> 14);
2067 else
2068 break;
2069 freqCount++;
1222 } 2070 }
1223 } 2071 }
1224 2072
1225 *pTxPowerIndexOffset = 0; 2073 if (IS_CHAN_2GHZ(chan)) {
2074 INI_RA(&ahp->ah_iniAddac, 7, 1) = (INI_RA(&ahp->ah_iniAddac,
2075 7, 1) & (~0x18)) | biaslevel << 3;
2076 } else {
2077 INI_RA(&ahp->ah_iniAddac, 6, 1) = (INI_RA(&ahp->ah_iniAddac,
2078 6, 1) & (~0xc0)) | biaslevel << 6;
2079 }
2080#undef XPA_LVL_FREQ
2081}
1226 2082
1227 return true; 2083static void ath9k_hw_set_4k_addac(struct ath_hal *ah,
2084 struct ath9k_channel *chan)
2085{
2086 struct modal_eep_4k_header *pModal;
2087 struct ath_hal_5416 *ahp = AH5416(ah);
2088 struct ar5416_eeprom_4k *eep = &ahp->ah_eeprom.map4k;
2089 u8 biaslevel;
2090
2091 if (ah->ah_macVersion != AR_SREV_VERSION_9160)
2092 return;
2093
2094 if (ar5416_get_eep_rev(ahp) < AR5416_EEP_MINOR_VER_7)
2095 return;
2096
2097 pModal = &eep->modalHeader;
2098
2099 if (pModal->xpaBiasLvl != 0xff) {
2100 biaslevel = pModal->xpaBiasLvl;
2101 INI_RA(&ahp->ah_iniAddac, 7, 1) =
2102 (INI_RA(&ahp->ah_iniAddac, 7, 1) & (~0x18)) | biaslevel << 3;
2103 }
2104}
2105
2106void (*ath9k_set_addac[]) (struct ath_hal *, struct ath9k_channel *) = {
2107 ath9k_hw_set_def_addac,
2108 ath9k_hw_set_4k_addac
2109};
2110
2111void ath9k_hw_set_addac(struct ath_hal *ah, struct ath9k_channel *chan)
2112{
2113 struct ath_hal_5416 *ahp = AH5416(ah);
2114
2115 ath9k_set_addac[ahp->ah_eep_map](ah, chan);
1228} 2116}
1229 2117
2118
2119
1230/* XXX: Clean me up, make me more legible */ 2120/* XXX: Clean me up, make me more legible */
1231bool ath9k_hw_eeprom_set_board_values(struct ath_hal *ah, 2121static bool ath9k_hw_eeprom_set_def_board_values(struct ath_hal *ah,
1232 struct ath9k_channel *chan) 2122 struct ath9k_channel *chan)
1233{ 2123{
1234 struct modal_eep_header *pModal; 2124 struct modal_eep_header *pModal;
1235 struct ath_hal_5416 *ahp = AH5416(ah); 2125 struct ath_hal_5416 *ahp = AH5416(ah);
1236 struct ar5416_eeprom *eep = &ahp->ah_eeprom; 2126 struct ar5416_eeprom_def *eep = &ahp->ah_eeprom.def;
1237 int i, regChainOffset; 2127 int i, regChainOffset;
1238 u8 txRxAttenLocal; 2128 u8 txRxAttenLocal;
1239 u16 ant_config; 2129 u16 ant_config;
@@ -1462,12 +2352,214 @@ bool ath9k_hw_eeprom_set_board_values(struct ath_hal *ah,
1462 return true; 2352 return true;
1463} 2353}
1464 2354
1465int ath9k_hw_get_eeprom_antenna_cfg(struct ath_hal *ah, 2355static bool ath9k_hw_eeprom_set_4k_board_values(struct ath_hal *ah,
2356 struct ath9k_channel *chan)
2357{
2358 struct modal_eep_4k_header *pModal;
2359 struct ath_hal_5416 *ahp = AH5416(ah);
2360 struct ar5416_eeprom_4k *eep = &ahp->ah_eeprom.map4k;
2361 int regChainOffset;
2362 u8 txRxAttenLocal;
2363 u16 ant_config = 0;
2364 u8 ob[5], db1[5], db2[5];
2365 u8 ant_div_control1, ant_div_control2;
2366 u32 regVal;
2367
2368
2369 pModal = &eep->modalHeader;
2370
2371 txRxAttenLocal = 23;
2372
2373 ath9k_hw_get_eeprom_antenna_cfg(ah, chan, 0, &ant_config);
2374 REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
2375
2376 regChainOffset = 0;
2377 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
2378 pModal->antCtrlChain[0]);
2379
2380 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
2381 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) &
2382 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
2383 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
2384 SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
2385 SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
2386
2387 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
2388 AR5416_EEP_MINOR_VER_3) {
2389 txRxAttenLocal = pModal->txRxAttenCh[0];
2390 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
2391 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]);
2392 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
2393 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
2394 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
2395 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
2396 pModal->xatten2Margin[0]);
2397 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
2398 AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]);
2399 }
2400
2401 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
2402 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
2403 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
2404 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
2405
2406 if (AR_SREV_9285_11(ah))
2407 REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
2408
2409 /* Initialize Ant Diversity settings from EEPROM */
2410 if (pModal->version == 3) {
2411 ant_div_control1 = ((pModal->ob_234 >> 12) & 0xf);
2412 ant_div_control2 = ((pModal->db1_234 >> 12) & 0xf);
2413 regVal = REG_READ(ah, 0x99ac);
2414 regVal &= (~(0x7f000000));
2415 regVal |= ((ant_div_control1 & 0x1) << 24);
2416 regVal |= (((ant_div_control1 >> 1) & 0x1) << 29);
2417 regVal |= (((ant_div_control1 >> 2) & 0x1) << 30);
2418 regVal |= ((ant_div_control2 & 0x3) << 25);
2419 regVal |= (((ant_div_control2 >> 2) & 0x3) << 27);
2420 REG_WRITE(ah, 0x99ac, regVal);
2421 regVal = REG_READ(ah, 0x99ac);
2422 regVal = REG_READ(ah, 0xa208);
2423 regVal &= (~(0x1 << 13));
2424 regVal |= (((ant_div_control1 >> 3) & 0x1) << 13);
2425 REG_WRITE(ah, 0xa208, regVal);
2426 regVal = REG_READ(ah, 0xa208);
2427 }
2428
2429 if (pModal->version >= 2) {
2430 ob[0] = (pModal->ob_01 & 0xf);
2431 ob[1] = (pModal->ob_01 >> 4) & 0xf;
2432 ob[2] = (pModal->ob_234 & 0xf);
2433 ob[3] = ((pModal->ob_234 >> 4) & 0xf);
2434 ob[4] = ((pModal->ob_234 >> 8) & 0xf);
2435
2436 db1[0] = (pModal->db1_01 & 0xf);
2437 db1[1] = ((pModal->db1_01 >> 4) & 0xf);
2438 db1[2] = (pModal->db1_234 & 0xf);
2439 db1[3] = ((pModal->db1_234 >> 4) & 0xf);
2440 db1[4] = ((pModal->db1_234 >> 8) & 0xf);
2441
2442 db2[0] = (pModal->db2_01 & 0xf);
2443 db2[1] = ((pModal->db2_01 >> 4) & 0xf);
2444 db2[2] = (pModal->db2_234 & 0xf);
2445 db2[3] = ((pModal->db2_234 >> 4) & 0xf);
2446 db2[4] = ((pModal->db2_234 >> 8) & 0xf);
2447
2448 } else if (pModal->version == 1) {
2449
2450 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2451 "EEPROM Model version is set to 1 \n");
2452 ob[0] = (pModal->ob_01 & 0xf);
2453 ob[1] = ob[2] = ob[3] = ob[4] = (pModal->ob_01 >> 4) & 0xf;
2454 db1[0] = (pModal->db1_01 & 0xf);
2455 db1[1] = db1[2] = db1[3] =
2456 db1[4] = ((pModal->db1_01 >> 4) & 0xf);
2457 db2[0] = (pModal->db2_01 & 0xf);
2458 db2[1] = db2[2] = db2[3] =
2459 db2[4] = ((pModal->db2_01 >> 4) & 0xf);
2460 } else {
2461 int i;
2462 for (i = 0; i < 5; i++) {
2463 ob[i] = pModal->ob_01;
2464 db1[i] = pModal->db1_01;
2465 db2[i] = pModal->db1_01;
2466 }
2467 }
2468
2469 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
2470 AR9285_AN_RF2G3_OB_0, AR9285_AN_RF2G3_OB_0_S, ob[0]);
2471 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
2472 AR9285_AN_RF2G3_OB_1, AR9285_AN_RF2G3_OB_1_S, ob[1]);
2473 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
2474 AR9285_AN_RF2G3_OB_2, AR9285_AN_RF2G3_OB_2_S, ob[2]);
2475 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
2476 AR9285_AN_RF2G3_OB_3, AR9285_AN_RF2G3_OB_3_S, ob[3]);
2477 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
2478 AR9285_AN_RF2G3_OB_4, AR9285_AN_RF2G3_OB_4_S, ob[4]);
2479
2480 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
2481 AR9285_AN_RF2G3_DB1_0, AR9285_AN_RF2G3_DB1_0_S, db1[0]);
2482 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
2483 AR9285_AN_RF2G3_DB1_1, AR9285_AN_RF2G3_DB1_1_S, db1[1]);
2484 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
2485 AR9285_AN_RF2G3_DB1_2, AR9285_AN_RF2G3_DB1_2_S, db1[2]);
2486 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
2487 AR9285_AN_RF2G4_DB1_3, AR9285_AN_RF2G4_DB1_3_S, db1[3]);
2488 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
2489 AR9285_AN_RF2G4_DB1_4, AR9285_AN_RF2G4_DB1_4_S, db1[4]);
2490
2491 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
2492 AR9285_AN_RF2G4_DB2_0, AR9285_AN_RF2G4_DB2_0_S, db2[0]);
2493 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
2494 AR9285_AN_RF2G4_DB2_1, AR9285_AN_RF2G4_DB2_1_S, db2[1]);
2495 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
2496 AR9285_AN_RF2G4_DB2_2, AR9285_AN_RF2G4_DB2_2_S, db2[2]);
2497 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
2498 AR9285_AN_RF2G4_DB2_3, AR9285_AN_RF2G4_DB2_3_S, db2[3]);
2499 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
2500 AR9285_AN_RF2G4_DB2_4, AR9285_AN_RF2G4_DB2_4_S, db2[4]);
2501
2502
2503 if (AR_SREV_9285_11(ah))
2504 REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);
2505
2506 REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
2507 pModal->switchSettling);
2508 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
2509 pModal->adcDesiredSize);
2510
2511 REG_WRITE(ah, AR_PHY_RF_CTL4,
2512 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) |
2513 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) |
2514 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) |
2515 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
2516
2517 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
2518 pModal->txEndToRxOn);
2519 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
2520 pModal->thresh62);
2521 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,
2522 pModal->thresh62);
2523
2524 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
2525 AR5416_EEP_MINOR_VER_2) {
2526 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_DATA_START,
2527 pModal->txFrameToDataStart);
2528 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
2529 pModal->txFrameToPaOn);
2530 }
2531
2532 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
2533 AR5416_EEP_MINOR_VER_3) {
2534 if (IS_CHAN_HT40(chan))
2535 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
2536 AR_PHY_SETTLING_SWITCH,
2537 pModal->swSettleHt40);
2538 }
2539
2540 return true;
2541}
2542
2543bool (*ath9k_eeprom_set_board_values[])(struct ath_hal *,
2544 struct ath9k_channel *) = {
2545 ath9k_hw_eeprom_set_def_board_values,
2546 ath9k_hw_eeprom_set_4k_board_values
2547};
2548
2549bool ath9k_hw_eeprom_set_board_values(struct ath_hal *ah,
2550 struct ath9k_channel *chan)
2551{
2552 struct ath_hal_5416 *ahp = AH5416(ah);
2553
2554 return ath9k_eeprom_set_board_values[ahp->ah_eep_map](ah, chan);
2555}
2556
2557static int ath9k_hw_get_def_eeprom_antenna_cfg(struct ath_hal *ah,
1466 struct ath9k_channel *chan, 2558 struct ath9k_channel *chan,
1467 u8 index, u16 *config) 2559 u8 index, u16 *config)
1468{ 2560{
1469 struct ath_hal_5416 *ahp = AH5416(ah); 2561 struct ath_hal_5416 *ahp = AH5416(ah);
1470 struct ar5416_eeprom *eep = &ahp->ah_eeprom; 2562 struct ar5416_eeprom_def *eep = &ahp->ah_eeprom.def;
1471 struct modal_eep_header *pModal = 2563 struct modal_eep_header *pModal =
1472 &(eep->modalHeader[IS_CHAN_2GHZ(chan)]); 2564 &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
1473 struct base_eep_header *pBase = &eep->baseEepHeader; 2565 struct base_eep_header *pBase = &eep->baseEepHeader;
@@ -1492,13 +2584,54 @@ int ath9k_hw_get_eeprom_antenna_cfg(struct ath_hal *ah,
1492 return -EINVAL; 2584 return -EINVAL;
1493} 2585}
1494 2586
1495u8 ath9k_hw_get_num_ant_config(struct ath_hal *ah, 2587static int ath9k_hw_get_4k_eeprom_antenna_cfg(struct ath_hal *ah,
2588 struct ath9k_channel *chan,
2589 u8 index, u16 *config)
2590{
2591 struct ath_hal_5416 *ahp = AH5416(ah);
2592 struct ar5416_eeprom_4k *eep = &ahp->ah_eeprom.map4k;
2593 struct modal_eep_4k_header *pModal = &eep->modalHeader;
2594
2595 switch (index) {
2596 case 0:
2597 *config = pModal->antCtrlCommon & 0xFFFF;
2598 return 0;
2599 default:
2600 break;
2601 }
2602
2603 return -EINVAL;
2604}
2605
2606int (*ath9k_get_eeprom_antenna_cfg[])(struct ath_hal *, struct ath9k_channel *,
2607 u8, u16 *) = {
2608 ath9k_hw_get_def_eeprom_antenna_cfg,
2609 ath9k_hw_get_4k_eeprom_antenna_cfg
2610};
2611
2612int ath9k_hw_get_eeprom_antenna_cfg(struct ath_hal *ah,
2613 struct ath9k_channel *chan,
2614 u8 index, u16 *config)
2615{
2616 struct ath_hal_5416 *ahp = AH5416(ah);
2617
2618 return ath9k_get_eeprom_antenna_cfg[ahp->ah_eep_map](ah, chan,
2619 index, config);
2620}
2621
2622u8 ath9k_hw_get_4k_num_ant_config(struct ath_hal *ah,
2623 enum ieee80211_band freq_band)
2624{
2625 return 1;
2626}
2627
2628u8 ath9k_hw_get_def_num_ant_config(struct ath_hal *ah,
1496 enum ieee80211_band freq_band) 2629 enum ieee80211_band freq_band)
1497{ 2630{
1498 struct ath_hal_5416 *ahp = AH5416(ah); 2631 struct ath_hal_5416 *ahp = AH5416(ah);
1499 struct ar5416_eeprom *eep = &ahp->ah_eeprom; 2632 struct ar5416_eeprom_def *eep = &ahp->ah_eeprom.def;
1500 struct modal_eep_header *pModal = 2633 struct modal_eep_header *pModal =
1501 &(eep->modalHeader[IEEE80211_BAND_5GHZ == freq_band]); 2634 &(eep->modalHeader[ATH9K_HAL_FREQ_BAND_2GHZ == freq_band]);
1502 struct base_eep_header *pBase = &eep->baseEepHeader; 2635 struct base_eep_header *pBase = &eep->baseEepHeader;
1503 u8 num_ant_config; 2636 u8 num_ant_config;
1504 2637
@@ -1511,11 +2644,26 @@ u8 ath9k_hw_get_num_ant_config(struct ath_hal *ah,
1511 return num_ant_config; 2644 return num_ant_config;
1512} 2645}
1513 2646
2647u8 (*ath9k_get_num_ant_config[])(struct ath_hal *, enum ieee80211_band) = {
2648 ath9k_hw_get_def_num_ant_config,
2649 ath9k_hw_get_4k_num_ant_config
2650};
2651
2652u8 ath9k_hw_get_num_ant_config(struct ath_hal *ah,
2653 enum ieee80211_band freq_band)
2654{
2655 struct ath_hal_5416 *ahp = AH5416(ah);
2656
2657 return ath9k_get_num_ant_config[ahp->ah_eep_map](ah, freq_band);
2658}
2659
1514u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah, u16 i, bool is2GHz) 2660u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah, u16 i, bool is2GHz)
1515{ 2661{
2662#define EEP_MAP4K_SPURCHAN \
2663 (ahp->ah_eeprom.map4k.modalHeader.spurChans[i].spurChan)
2664#define EEP_DEF_SPURCHAN \
2665 (ahp->ah_eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan)
1516 struct ath_hal_5416 *ahp = AH5416(ah); 2666 struct ath_hal_5416 *ahp = AH5416(ah);
1517 struct ar5416_eeprom *eep =
1518 (struct ar5416_eeprom *) &ahp->ah_eeprom;
1519 u16 spur_val = AR_NO_SPUR; 2667 u16 spur_val = AR_NO_SPUR;
1520 2668
1521 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 2669 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
@@ -1531,19 +2679,66 @@ u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah, u16 i, bool is2GHz)
1531 "Getting spur val from new loc. %d\n", spur_val); 2679 "Getting spur val from new loc. %d\n", spur_val);
1532 break; 2680 break;
1533 case SPUR_ENABLE_EEPROM: 2681 case SPUR_ENABLE_EEPROM:
1534 spur_val = eep->modalHeader[is2GHz].spurChans[i].spurChan; 2682 if (ahp->ah_eep_map == EEP_MAP_4KBITS)
2683 spur_val = EEP_MAP4K_SPURCHAN;
2684 else
2685 spur_val = EEP_DEF_SPURCHAN;
1535 break; 2686 break;
1536 2687
1537 } 2688 }
1538 2689
1539 return spur_val; 2690 return spur_val;
2691#undef EEP_DEF_SPURCHAN
2692#undef EEP_MAP4K_SPURCHAN
1540} 2693}
1541 2694
1542u32 ath9k_hw_get_eeprom(struct ath_hal *ah, 2695static u32 ath9k_hw_get_eeprom_4k(struct ath_hal *ah,
1543 enum eeprom_param param) 2696 enum eeprom_param param)
2697{
2698 struct ath_hal_5416 *ahp = AH5416(ah);
2699 struct ar5416_eeprom_4k *eep = &ahp->ah_eeprom.map4k;
2700 struct modal_eep_4k_header *pModal = &eep->modalHeader;
2701 struct base_eep_header_4k *pBase = &eep->baseEepHeader;
2702
2703 switch (param) {
2704 case EEP_NFTHRESH_2:
2705 return pModal[1].noiseFloorThreshCh[0];
2706 case AR_EEPROM_MAC(0):
2707 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
2708 case AR_EEPROM_MAC(1):
2709 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
2710 case AR_EEPROM_MAC(2):
2711 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
2712 case EEP_REG_0:
2713 return pBase->regDmn[0];
2714 case EEP_REG_1:
2715 return pBase->regDmn[1];
2716 case EEP_OP_CAP:
2717 return pBase->deviceCap;
2718 case EEP_OP_MODE:
2719 return pBase->opCapFlags;
2720 case EEP_RF_SILENT:
2721 return pBase->rfSilent;
2722 case EEP_OB_2:
2723 return pModal->ob_01;
2724 case EEP_DB_2:
2725 return pModal->db1_01;
2726 case EEP_MINOR_REV:
2727 return pBase->version & AR5416_EEP_VER_MINOR_MASK;
2728 case EEP_TX_MASK:
2729 return pBase->txMask;
2730 case EEP_RX_MASK:
2731 return pBase->rxMask;
2732 default:
2733 return 0;
2734 }
2735}
2736
2737static u32 ath9k_hw_get_eeprom_def(struct ath_hal *ah,
2738 enum eeprom_param param)
1544{ 2739{
1545 struct ath_hal_5416 *ahp = AH5416(ah); 2740 struct ath_hal_5416 *ahp = AH5416(ah);
1546 struct ar5416_eeprom *eep = &ahp->ah_eeprom; 2741 struct ar5416_eeprom_def *eep = &ahp->ah_eeprom.def;
1547 struct modal_eep_header *pModal = eep->modalHeader; 2742 struct modal_eep_header *pModal = eep->modalHeader;
1548 struct base_eep_header *pBase = &eep->baseEepHeader; 2743 struct base_eep_header *pBase = &eep->baseEepHeader;
1549 2744
@@ -1592,13 +2787,32 @@ u32 ath9k_hw_get_eeprom(struct ath_hal *ah,
1592 } 2787 }
1593} 2788}
1594 2789
2790u32 (*ath9k_get_eeprom[])(struct ath_hal *, enum eeprom_param) = {
2791 ath9k_hw_get_eeprom_def,
2792 ath9k_hw_get_eeprom_4k
2793};
2794
2795u32 ath9k_hw_get_eeprom(struct ath_hal *ah,
2796 enum eeprom_param param)
2797{
2798 struct ath_hal_5416 *ahp = AH5416(ah);
2799
2800 return ath9k_get_eeprom[ahp->ah_eep_map](ah, param);
2801}
2802
1595int ath9k_hw_eeprom_attach(struct ath_hal *ah) 2803int ath9k_hw_eeprom_attach(struct ath_hal *ah)
1596{ 2804{
1597 int status; 2805 int status;
2806 struct ath_hal_5416 *ahp = AH5416(ah);
1598 2807
1599 if (ath9k_hw_use_flash(ah)) 2808 if (ath9k_hw_use_flash(ah))
1600 ath9k_hw_flash_map(ah); 2809 ath9k_hw_flash_map(ah);
1601 2810
2811 if (AR_SREV_9285(ah))
2812 ahp->ah_eep_map = EEP_MAP_4KBITS;
2813 else
2814 ahp->ah_eep_map = EEP_MAP_DEFAULT;
2815
1602 if (!ath9k_hw_fill_eeprom(ah)) 2816 if (!ath9k_hw_fill_eeprom(ah))
1603 return -EIO; 2817 return -EIO;
1604 2818
diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c
index 668865dce533..34474edefc97 100644
--- a/drivers/net/wireless/ath9k/hw.c
+++ b/drivers/net/wireless/ath9k/hw.c
@@ -37,7 +37,7 @@ static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type);
37static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan, 37static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
38 enum ath9k_ht_macmode macmode); 38 enum ath9k_ht_macmode macmode);
39static u32 ath9k_hw_ini_fixup(struct ath_hal *ah, 39static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
40 struct ar5416_eeprom *pEepData, 40 struct ar5416_eeprom_def *pEepData,
41 u32 reg, u32 value); 41 u32 reg, u32 value);
42static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan); 42static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan);
43static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan); 43static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan);
@@ -392,6 +392,8 @@ static const char *ath9k_hw_devname(u16 devid)
392 case AR9280_DEVID_PCI: 392 case AR9280_DEVID_PCI:
393 case AR9280_DEVID_PCIE: 393 case AR9280_DEVID_PCIE:
394 return "Atheros 9280"; 394 return "Atheros 9280";
395 case AR9285_DEVID_PCIE:
396 return "Atheros 9285";
395 } 397 }
396 398
397 return NULL; 399 return NULL;
@@ -640,10 +642,7 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
640 struct ath_hal_5416 *ahp; 642 struct ath_hal_5416 *ahp;
641 struct ath_hal *ah; 643 struct ath_hal *ah;
642 int ecode; 644 int ecode;
643#ifndef CONFIG_SLOW_ANT_DIV 645 u32 i, j;
644 u32 i;
645 u32 j;
646#endif
647 646
648 ahp = ath9k_hw_newstate(devid, sc, mem, status); 647 ahp = ath9k_hw_newstate(devid, sc, mem, status);
649 if (ahp == NULL) 648 if (ahp == NULL)
@@ -685,7 +684,7 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
685 if ((ah->ah_macVersion != AR_SREV_VERSION_5416_PCI) && 684 if ((ah->ah_macVersion != AR_SREV_VERSION_5416_PCI) &&
686 (ah->ah_macVersion != AR_SREV_VERSION_5416_PCIE) && 685 (ah->ah_macVersion != AR_SREV_VERSION_5416_PCIE) &&
687 (ah->ah_macVersion != AR_SREV_VERSION_9160) && 686 (ah->ah_macVersion != AR_SREV_VERSION_9160) &&
688 (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah))) { 687 (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) {
689 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 688 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
690 "Mac Chip Rev 0x%02x.%x is not supported by " 689 "Mac Chip Rev 0x%02x.%x is not supported by "
691 "this driver\n", ah->ah_macVersion, ah->ah_macRev); 690 "this driver\n", ah->ah_macVersion, ah->ah_macRev);
@@ -736,7 +735,38 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
736 "This Mac Chip Rev 0x%02x.%x is \n", 735 "This Mac Chip Rev 0x%02x.%x is \n",
737 ah->ah_macVersion, ah->ah_macRev); 736 ah->ah_macVersion, ah->ah_macRev);
738 737
739 if (AR_SREV_9280_20_OR_LATER(ah)) { 738 if (AR_SREV_9285_12_OR_LATER(ah)) {
739 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285_1_2,
740 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
741 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9285Common_9285_1_2,
742 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
743
744 if (ah->ah_config.pcie_clock_req) {
745 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
746 ar9285PciePhy_clkreq_off_L1_9285_1_2,
747 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
748 } else {
749 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
750 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
751 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
752 2);
753 }
754 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
755 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285,
756 ARRAY_SIZE(ar9285Modes_9285), 6);
757 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9285Common_9285,
758 ARRAY_SIZE(ar9285Common_9285), 2);
759
760 if (ah->ah_config.pcie_clock_req) {
761 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
762 ar9285PciePhy_clkreq_off_L1_9285,
763 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
764 } else {
765 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
766 ar9285PciePhy_clkreq_always_on_L1_9285,
767 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
768 }
769 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
740 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280_2, 770 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280_2,
741 ARRAY_SIZE(ar9280Modes_9280_2), 6); 771 ARRAY_SIZE(ar9280Modes_9280_2), 6);
742 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280_2, 772 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280_2,
@@ -846,14 +876,13 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
846 goto bad; 876 goto bad;
847 877
848 /* rxgain table */ 878 /* rxgain table */
849 if (AR_SREV_9280_20_OR_LATER(ah)) 879 if (AR_SREV_9280_20(ah))
850 ath9k_hw_init_rxgain_ini(ah); 880 ath9k_hw_init_rxgain_ini(ah);
851 881
852 /* txgain table */ 882 /* txgain table */
853 if (AR_SREV_9280_20_OR_LATER(ah)) 883 if (AR_SREV_9280_20(ah))
854 ath9k_hw_init_txgain_ini(ah); 884 ath9k_hw_init_txgain_ini(ah);
855 885
856#ifndef CONFIG_SLOW_ANT_DIV
857 if (ah->ah_devid == AR9280_DEVID_PCI) { 886 if (ah->ah_devid == AR9280_DEVID_PCI) {
858 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) { 887 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
859 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0); 888 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
@@ -862,12 +891,13 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
862 u32 val = INI_RA(&ahp->ah_iniModes, i, j); 891 u32 val = INI_RA(&ahp->ah_iniModes, i, j);
863 892
864 INI_RA(&ahp->ah_iniModes, i, j) = 893 INI_RA(&ahp->ah_iniModes, i, j) =
865 ath9k_hw_ini_fixup(ah, &ahp->ah_eeprom, 894 ath9k_hw_ini_fixup(ah,
895 &ahp->ah_eeprom.def,
866 reg, val); 896 reg, val);
867 } 897 }
868 } 898 }
869 } 899 }
870#endif 900
871 if (!ath9k_hw_fill_cap_info(ah)) { 901 if (!ath9k_hw_fill_cap_info(ah)) {
872 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 902 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
873 "failed ath9k_hw_fill_cap_info\n"); 903 "failed ath9k_hw_fill_cap_info\n");
@@ -1020,8 +1050,6 @@ static void ath9k_hw_init_chain_masks(struct ath_hal *ah)
1020 } 1050 }
1021 case 0x1: 1051 case 0x1:
1022 case 0x2: 1052 case 0x2:
1023 if (!AR_SREV_9280(ah))
1024 break;
1025 case 0x7: 1053 case 0x7:
1026 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); 1054 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1027 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); 1055 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
@@ -1166,12 +1194,10 @@ struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc,
1166 case AR9160_DEVID_PCI: 1194 case AR9160_DEVID_PCI:
1167 case AR9280_DEVID_PCI: 1195 case AR9280_DEVID_PCI:
1168 case AR9280_DEVID_PCIE: 1196 case AR9280_DEVID_PCIE:
1197 case AR9285_DEVID_PCIE:
1169 ah = ath9k_hw_do_attach(devid, sc, mem, error); 1198 ah = ath9k_hw_do_attach(devid, sc, mem, error);
1170 break; 1199 break;
1171 default: 1200 default:
1172 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1173 "devid=0x%x not supported.\n", devid);
1174 ah = NULL;
1175 *error = -ENXIO; 1201 *error = -ENXIO;
1176 break; 1202 break;
1177 } 1203 }
@@ -1186,6 +1212,14 @@ struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc,
1186static void ath9k_hw_override_ini(struct ath_hal *ah, 1212static void ath9k_hw_override_ini(struct ath_hal *ah,
1187 struct ath9k_channel *chan) 1213 struct ath9k_channel *chan)
1188{ 1214{
1215 /*
1216 * Set the RX_ABORT and RX_DIS and clear if off only after
1217 * RXE is set for MAC. This prevents frames with corrupted
1218 * descriptor status.
1219 */
1220 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1221
1222
1189 if (!AR_SREV_5416_V20_OR_LATER(ah) || 1223 if (!AR_SREV_5416_V20_OR_LATER(ah) ||
1190 AR_SREV_9280_10_OR_LATER(ah)) 1224 AR_SREV_9280_10_OR_LATER(ah))
1191 return; 1225 return;
@@ -1193,8 +1227,8 @@ static void ath9k_hw_override_ini(struct ath_hal *ah,
1193 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11); 1227 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1194} 1228}
1195 1229
1196static u32 ath9k_hw_ini_fixup(struct ath_hal *ah, 1230static u32 ath9k_hw_def_ini_fixup(struct ath_hal *ah,
1197 struct ar5416_eeprom *pEepData, 1231 struct ar5416_eeprom_def *pEepData,
1198 u32 reg, u32 value) 1232 u32 reg, u32 value)
1199{ 1233{
1200 struct base_eep_header *pBase = &(pEepData->baseEepHeader); 1234 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
@@ -1227,6 +1261,18 @@ static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
1227 return value; 1261 return value;
1228} 1262}
1229 1263
1264static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
1265 struct ar5416_eeprom_def *pEepData,
1266 u32 reg, u32 value)
1267{
1268 struct ath_hal_5416 *ahp = AH5416(ah);
1269
1270 if (ahp->ah_eep_map == EEP_MAP_4KBITS)
1271 return value;
1272 else
1273 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1274}
1275
1230static int ath9k_hw_process_ini(struct ath_hal *ah, 1276static int ath9k_hw_process_ini(struct ath_hal *ah,
1231 struct ath9k_channel *chan, 1277 struct ath9k_channel *chan,
1232 enum ath9k_ht_macmode macmode) 1278 enum ath9k_ht_macmode macmode)
@@ -1294,11 +1340,6 @@ static int ath9k_hw_process_ini(struct ath_hal *ah,
1294 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0); 1340 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
1295 u32 val = INI_RA(&ahp->ah_iniModes, i, modesIndex); 1341 u32 val = INI_RA(&ahp->ah_iniModes, i, modesIndex);
1296 1342
1297#ifdef CONFIG_SLOW_ANT_DIV
1298 if (ah->ah_devid == AR9280_DEVID_PCI)
1299 val = ath9k_hw_ini_fixup(ah, &ahp->ah_eeprom, reg, val);
1300#endif
1301
1302 REG_WRITE(ah, reg, val); 1343 REG_WRITE(ah, reg, val);
1303 1344
1304 if (reg >= 0x7800 && reg < 0x78a0 1345 if (reg >= 0x7800 && reg < 0x78a0
@@ -1309,10 +1350,10 @@ static int ath9k_hw_process_ini(struct ath_hal *ah,
1309 DO_DELAY(regWrites); 1350 DO_DELAY(regWrites);
1310 } 1351 }
1311 1352
1312 if (AR_SREV_9280_20_OR_LATER(ah)) 1353 if (AR_SREV_9280(ah))
1313 REG_WRITE_ARRAY(&ahp->ah_iniModesRxGain, modesIndex, regWrites); 1354 REG_WRITE_ARRAY(&ahp->ah_iniModesRxGain, modesIndex, regWrites);
1314 1355
1315 if (AR_SREV_9280_20_OR_LATER(ah)) 1356 if (AR_SREV_9280(ah))
1316 REG_WRITE_ARRAY(&ahp->ah_iniModesTxGain, modesIndex, regWrites); 1357 REG_WRITE_ARRAY(&ahp->ah_iniModesTxGain, modesIndex, regWrites);
1317 1358
1318 for (i = 0; i < ahp->ah_iniCommon.ia_rows; i++) { 1359 for (i = 0; i < ahp->ah_iniCommon.ia_rows; i++) {
@@ -1585,10 +1626,15 @@ static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
1585 enum ath9k_ht_macmode macmode) 1626 enum ath9k_ht_macmode macmode)
1586{ 1627{
1587 u32 phymode; 1628 u32 phymode;
1629 u32 enableDacFifo = 0;
1588 struct ath_hal_5416 *ahp = AH5416(ah); 1630 struct ath_hal_5416 *ahp = AH5416(ah);
1589 1631
1632 if (AR_SREV_9285_10_OR_LATER(ah))
1633 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1634 AR_PHY_FC_ENABLE_DAC_FIFO);
1635
1590 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40 1636 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1591 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH; 1637 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1592 1638
1593 if (IS_CHAN_HT40(chan)) { 1639 if (IS_CHAN_HT40(chan)) {
1594 phymode |= AR_PHY_FC_DYN2040_EN; 1640 phymode |= AR_PHY_FC_DYN2040_EN;
@@ -2771,11 +2817,14 @@ void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
2771 if (ah->ah_config.pcie_waen) { 2817 if (ah->ah_config.pcie_waen) {
2772 REG_WRITE(ah, AR_WA, ah->ah_config.pcie_waen); 2818 REG_WRITE(ah, AR_WA, ah->ah_config.pcie_waen);
2773 } else { 2819 } else {
2774 if (AR_SREV_9280(ah)) 2820 if (AR_SREV_9285(ah))
2775 REG_WRITE(ah, AR_WA, 0x0040073f); 2821 REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
2822 else if (AR_SREV_9280(ah))
2823 REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
2776 else 2824 else
2777 REG_WRITE(ah, AR_WA, 0x0000073f); 2825 REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
2778 } 2826 }
2827
2779} 2828}
2780 2829
2781/**********************/ 2830/**********************/
@@ -3326,7 +3375,7 @@ bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
3326 else 3375 else
3327 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; 3376 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3328 3377
3329 if (AR_SREV_9280(ah)) 3378 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3330 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; 3379 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3331 else 3380 else
3332 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; 3381 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
@@ -3346,9 +3395,9 @@ bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
3346 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND; 3395 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3347 3396
3348 pCap->num_antcfg_5ghz = 3397 pCap->num_antcfg_5ghz =
3349 ath9k_hw_get_num_ant_config(ah, IEEE80211_BAND_5GHZ); 3398 ath9k_hw_get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3350 pCap->num_antcfg_2ghz = 3399 pCap->num_antcfg_2ghz =
3351 ath9k_hw_get_num_ant_config(ah, IEEE80211_BAND_2GHZ); 3400 ath9k_hw_get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3352 3401
3353 return true; 3402 return true;
3354} 3403}
diff --git a/drivers/net/wireless/ath9k/hw.h b/drivers/net/wireless/ath9k/hw.h
index 02256c3ec076..91d8f594af81 100644
--- a/drivers/net/wireless/ath9k/hw.h
+++ b/drivers/net/wireless/ath9k/hw.h
@@ -448,6 +448,17 @@ struct ar5416Stats {
448#define AR5416_EEP_TXGAIN_ORIGINAL 0 448#define AR5416_EEP_TXGAIN_ORIGINAL 0
449#define AR5416_EEP_TXGAIN_HIGH_POWER 1 449#define AR5416_EEP_TXGAIN_HIGH_POWER 1
450 450
451#define AR5416_EEP4K_START_LOC 64
452#define AR5416_EEP4K_NUM_2G_CAL_PIERS 3
453#define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3
454#define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS 3
455#define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS 3
456#define AR5416_EEP4K_NUM_CTLS 12
457#define AR5416_EEP4K_NUM_BAND_EDGES 4
458#define AR5416_EEP4K_NUM_PD_GAINS 2
459#define AR5416_EEP4K_PD_GAINS_IN_MASK 4
460#define AR5416_EEP4K_PD_GAIN_ICEPTS 5
461#define AR5416_EEP4K_MAX_CHAINS 1
451 462
452enum eeprom_param { 463enum eeprom_param {
453 EEP_NFTHRESH_5, 464 EEP_NFTHRESH_5,
@@ -484,6 +495,11 @@ enum ar5416_rates {
484 Ar5416RateSize 495 Ar5416RateSize
485}; 496};
486 497
498enum ath9k_hal_freq_band {
499 ATH9K_HAL_FREQ_BAND_5GHZ = 0,
500 ATH9K_HAL_FREQ_BAND_2GHZ = 1
501};
502
487struct base_eep_header { 503struct base_eep_header {
488 u16 length; 504 u16 length;
489 u16 checksum; 505 u16 checksum;
@@ -507,6 +523,25 @@ struct base_eep_header {
507 u8 futureBase_3[25]; 523 u8 futureBase_3[25];
508} __packed; 524} __packed;
509 525
526struct base_eep_header_4k {
527 u16 length;
528 u16 checksum;
529 u16 version;
530 u8 opCapFlags;
531 u8 eepMisc;
532 u16 regDmn[2];
533 u8 macAddr[6];
534 u8 rxMask;
535 u8 txMask;
536 u16 rfSilent;
537 u16 blueToothOptions;
538 u16 deviceCap;
539 u32 binBuildNumber;
540 u8 deviceType;
541 u8 futureBase[1];
542} __packed;
543
544
510struct spur_chan { 545struct spur_chan {
511 u16 spurChan; 546 u16 spurChan;
512 u8 spurRangeLow; 547 u8 spurRangeLow;
@@ -559,11 +594,58 @@ struct modal_eep_header {
559 struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS]; 594 struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
560} __packed; 595} __packed;
561 596
597struct modal_eep_4k_header {
598 u32 antCtrlChain[AR5416_EEP4K_MAX_CHAINS];
599 u32 antCtrlCommon;
600 u8 antennaGainCh[AR5416_EEP4K_MAX_CHAINS];
601 u8 switchSettling;
602 u8 txRxAttenCh[AR5416_EEP4K_MAX_CHAINS];
603 u8 rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS];
604 u8 adcDesiredSize;
605 u8 pgaDesiredSize;
606 u8 xlnaGainCh[AR5416_EEP4K_MAX_CHAINS];
607 u8 txEndToXpaOff;
608 u8 txEndToRxOn;
609 u8 txFrameToXpaOn;
610 u8 thresh62;
611 u8 noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS];
612 u8 xpdGain;
613 u8 xpd;
614 u8 iqCalICh[AR5416_EEP4K_MAX_CHAINS];
615 u8 iqCalQCh[AR5416_EEP4K_MAX_CHAINS];
616 u8 pdGainOverlap;
617 u8 ob_01;
618 u8 db1_01;
619 u8 xpaBiasLvl;
620 u8 txFrameToDataStart;
621 u8 txFrameToPaOn;
622 u8 ht40PowerIncForPdadc;
623 u8 bswAtten[AR5416_EEP4K_MAX_CHAINS];
624 u8 bswMargin[AR5416_EEP4K_MAX_CHAINS];
625 u8 swSettleHt40;
626 u8 xatten2Db[AR5416_EEP4K_MAX_CHAINS];
627 u8 xatten2Margin[AR5416_EEP4K_MAX_CHAINS];
628 u8 db2_01;
629 u8 version;
630 u16 ob_234;
631 u16 db1_234;
632 u16 db2_234;
633 u8 futureModal[4];
634
635 struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
636} __packed;
637
638
562struct cal_data_per_freq { 639struct cal_data_per_freq {
563 u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; 640 u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
564 u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; 641 u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
565} __packed; 642} __packed;
566 643
644struct cal_data_per_freq_4k {
645 u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
646 u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
647} __packed;
648
567struct cal_target_power_leg { 649struct cal_target_power_leg {
568 u8 bChannel; 650 u8 bChannel;
569 u8 tPow2x[4]; 651 u8 tPow2x[4];
@@ -574,6 +656,7 @@ struct cal_target_power_ht {
574 u8 tPow2x[8]; 656 u8 tPow2x[8];
575} __packed; 657} __packed;
576 658
659
577#ifdef __BIG_ENDIAN_BITFIELD 660#ifdef __BIG_ENDIAN_BITFIELD
578struct cal_ctl_edges { 661struct cal_ctl_edges {
579 u8 bChannel; 662 u8 bChannel;
@@ -588,10 +671,15 @@ struct cal_ctl_edges {
588 671
589struct cal_ctl_data { 672struct cal_ctl_data {
590 struct cal_ctl_edges 673 struct cal_ctl_edges
591 ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES]; 674 ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES];
675} __packed;
676
677struct cal_ctl_data_4k {
678 struct cal_ctl_edges
679 ctlEdges[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_BAND_EDGES];
592} __packed; 680} __packed;
593 681
594struct ar5416_eeprom { 682struct ar5416_eeprom_def {
595 struct base_eep_header baseEepHeader; 683 struct base_eep_header baseEepHeader;
596 u8 custData[64]; 684 u8 custData[64];
597 struct modal_eep_header modalHeader[2]; 685 struct modal_eep_header modalHeader[2];
@@ -620,6 +708,26 @@ struct ar5416_eeprom {
620 u8 padding; 708 u8 padding;
621} __packed; 709} __packed;
622 710
711struct ar5416_eeprom_4k {
712 struct base_eep_header_4k baseEepHeader;
713 u8 custData[20];
714 struct modal_eep_4k_header modalHeader;
715 u8 calFreqPier2G[AR5416_EEP4K_NUM_2G_CAL_PIERS];
716 struct cal_data_per_freq_4k
717 calPierData2G[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_2G_CAL_PIERS];
718 struct cal_target_power_leg
719 calTargetPowerCck[AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS];
720 struct cal_target_power_leg
721 calTargetPower2G[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
722 struct cal_target_power_ht
723 calTargetPower2GHT20[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
724 struct cal_target_power_ht
725 calTargetPower2GHT40[AR5416_EEP4K_NUM_2G_40_TARGET_POWERS];
726 u8 ctlIndex[AR5416_EEP4K_NUM_CTLS];
727 struct cal_ctl_data_4k ctlData[AR5416_EEP4K_NUM_CTLS];
728 u8 padding;
729} __packed;
730
623struct ar5416IniArray { 731struct ar5416IniArray {
624 u32 *ia_array; 732 u32 *ia_array;
625 u32 ia_rows; 733 u32 ia_rows;
@@ -687,9 +795,22 @@ struct hal_cal_list {
687 struct hal_cal_list *calNext; 795 struct hal_cal_list *calNext;
688}; 796};
689 797
798/*
799 * Enum to indentify the eeprom mappings
800 */
801enum hal_eep_map {
802 EEP_MAP_DEFAULT = 0x0,
803 EEP_MAP_4KBITS,
804 EEP_MAP_MAX
805};
806
807
690struct ath_hal_5416 { 808struct ath_hal_5416 {
691 struct ath_hal ah; 809 struct ath_hal ah;
692 struct ar5416_eeprom ah_eeprom; 810 union {
811 struct ar5416_eeprom_def def;
812 struct ar5416_eeprom_4k map4k;
813 } ah_eeprom;
693 struct ar5416Stats ah_stats; 814 struct ar5416Stats ah_stats;
694 struct ath9k_tx_queue_info ah_txq[ATH9K_NUM_TX_QUEUES]; 815 struct ath9k_tx_queue_info ah_txq[ATH9K_NUM_TX_QUEUES];
695 void __iomem *ah_cal_mem; 816 void __iomem *ah_cal_mem;
@@ -813,6 +934,8 @@ struct ath_hal_5416 {
813 struct ar5416IniArray ah_iniModesAdditional; 934 struct ar5416IniArray ah_iniModesAdditional;
814 struct ar5416IniArray ah_iniModesRxGain; 935 struct ar5416IniArray ah_iniModesRxGain;
815 struct ar5416IniArray ah_iniModesTxGain; 936 struct ar5416IniArray ah_iniModesTxGain;
937 /* To indicate EEPROM mapping used */
938 enum hal_eep_map ah_eep_map;
816}; 939};
817#define AH5416(_ah) ((struct ath_hal_5416 *)(_ah)) 940#define AH5416(_ah) ((struct ath_hal_5416 *)(_ah))
818 941
@@ -854,13 +977,20 @@ struct ath_hal_5416 {
854 (AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200 977 (AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200
855#define AR5416_EEPROM_MAX 0xae0 978#define AR5416_EEPROM_MAX 0xae0
856#define ar5416_get_eep_ver(_ahp) \ 979#define ar5416_get_eep_ver(_ahp) \
857 (((_ahp)->ah_eeprom.baseEepHeader.version >> 12) & 0xF) 980 (((_ahp)->ah_eeprom.def.baseEepHeader.version >> 12) & 0xF)
858#define ar5416_get_eep_rev(_ahp) \ 981#define ar5416_get_eep_rev(_ahp) \
859 (((_ahp)->ah_eeprom.baseEepHeader.version) & 0xFFF) 982 (((_ahp)->ah_eeprom.def.baseEepHeader.version) & 0xFFF)
860#define ar5416_get_ntxchains(_txchainmask) \ 983#define ar5416_get_ntxchains(_txchainmask) \
861 (((_txchainmask >> 2) & 1) + \ 984 (((_txchainmask >> 2) & 1) + \
862 ((_txchainmask >> 1) & 1) + (_txchainmask & 1)) 985 ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
863 986
987/* EEPROM 4K bit map definations */
988#define ar5416_get_eep4k_ver(_ahp) \
989 (((_ahp)->ah_eeprom.map4k.baseEepHeader.version >> 12) & 0xF)
990#define ar5416_get_eep4k_rev(_ahp) \
991 (((_ahp)->ah_eeprom.map4k.baseEepHeader.version) & 0xFFF)
992
993
864#ifdef __BIG_ENDIAN 994#ifdef __BIG_ENDIAN
865#define AR5416_EEPROM_MAGIC 0x5aa5 995#define AR5416_EEPROM_MAGIC 0x5aa5
866#else 996#else
diff --git a/drivers/net/wireless/ath9k/initvals.h b/drivers/net/wireless/ath9k/initvals.h
index 1b08b54b31d7..f3cfa16525e4 100644
--- a/drivers/net/wireless/ath9k/initvals.h
+++ b/drivers/net/wireless/ath9k/initvals.h
@@ -3437,3 +3437,1366 @@ static const u32 ar9280PciePhy_clkreq_always_on_L1_9280[][2] = {
3437 {0x00004040, 0x00043007 }, 3437 {0x00004040, 0x00043007 },
3438 {0x00004044, 0x00000000 }, 3438 {0x00004044, 0x00000000 },
3439}; 3439};
3440
3441/* AR9285 */
3442static const u_int32_t ar9285Modes_9285[][6] = {
3443 { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
3444 { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
3445 { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
3446 { 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 },
3447 { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
3448 { 0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f },
3449 { 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 },
3450 { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
3451 { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
3452 { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
3453 { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
3454 { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
3455 { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
3456 { 0x00009840, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e },
3457 { 0x00009844, 0x0372161e, 0x0372161e, 0x03720020, 0x03720020, 0x037216a0 },
3458 { 0x00009848, 0x00001066, 0x00001066, 0x0000004e, 0x0000004e, 0x00001059 },
3459 { 0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2 },
3460 { 0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
3461 { 0x0000985c, 0x3139605e, 0x3139605e, 0x3136605e, 0x3136605e, 0x3139605e },
3462 { 0x00009860, 0x00058d18, 0x00058d18, 0x00058d20, 0x00058d20, 0x00058d18 },
3463 { 0x00009864, 0x0000fe00, 0x0000fe00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
3464 { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
3465 { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 },
3466 { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
3467 { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
3468 { 0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d, 0xd00a800d },
3469 { 0x00009944, 0xdfbc1010, 0xdfbc1010, 0xdfbc1020, 0xdfbc1020, 0xdfbc1010 },
3470 { 0x00009960, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
3471 { 0x00009964, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
3472 { 0x000099b8, 0x00cf4d1c, 0x00cf4d1c, 0x00cf4d1c, 0x00cf4d1c, 0x00cf4d1c },
3473 { 0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00 },
3474 { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
3475 { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
3476 { 0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329 },
3477 { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
3478 { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
3479 { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
3480 { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
3481 { 0x00009a00, 0x00000000, 0x00000000, 0x00068084, 0x00068084, 0x00000000 },
3482 { 0x00009a04, 0x00000000, 0x00000000, 0x00068088, 0x00068088, 0x00000000 },
3483 { 0x00009a08, 0x00000000, 0x00000000, 0x0006808c, 0x0006808c, 0x00000000 },
3484 { 0x00009a0c, 0x00000000, 0x00000000, 0x00068100, 0x00068100, 0x00000000 },
3485 { 0x00009a10, 0x00000000, 0x00000000, 0x00068104, 0x00068104, 0x00000000 },
3486 { 0x00009a14, 0x00000000, 0x00000000, 0x00068108, 0x00068108, 0x00000000 },
3487 { 0x00009a18, 0x00000000, 0x00000000, 0x0006810c, 0x0006810c, 0x00000000 },
3488 { 0x00009a1c, 0x00000000, 0x00000000, 0x00068110, 0x00068110, 0x00000000 },
3489 { 0x00009a20, 0x00000000, 0x00000000, 0x00068114, 0x00068114, 0x00000000 },
3490 { 0x00009a24, 0x00000000, 0x00000000, 0x00068180, 0x00068180, 0x00000000 },
3491 { 0x00009a28, 0x00000000, 0x00000000, 0x00068184, 0x00068184, 0x00000000 },
3492 { 0x00009a2c, 0x00000000, 0x00000000, 0x00068188, 0x00068188, 0x00000000 },
3493 { 0x00009a30, 0x00000000, 0x00000000, 0x0006818c, 0x0006818c, 0x00000000 },
3494 { 0x00009a34, 0x00000000, 0x00000000, 0x00068190, 0x00068190, 0x00000000 },
3495 { 0x00009a38, 0x00000000, 0x00000000, 0x00068194, 0x00068194, 0x00000000 },
3496 { 0x00009a3c, 0x00000000, 0x00000000, 0x000681a0, 0x000681a0, 0x00000000 },
3497 { 0x00009a40, 0x00000000, 0x00000000, 0x0006820c, 0x0006820c, 0x00000000 },
3498 { 0x00009a44, 0x00000000, 0x00000000, 0x000681a8, 0x000681a8, 0x00000000 },
3499 { 0x00009a48, 0x00000000, 0x00000000, 0x00068284, 0x00068284, 0x00000000 },
3500 { 0x00009a4c, 0x00000000, 0x00000000, 0x00068288, 0x00068288, 0x00000000 },
3501 { 0x00009a50, 0x00000000, 0x00000000, 0x00068220, 0x00068220, 0x00000000 },
3502 { 0x00009a54, 0x00000000, 0x00000000, 0x00068290, 0x00068290, 0x00000000 },
3503 { 0x00009a58, 0x00000000, 0x00000000, 0x00068300, 0x00068300, 0x00000000 },
3504 { 0x00009a5c, 0x00000000, 0x00000000, 0x00068304, 0x00068304, 0x00000000 },
3505 { 0x00009a60, 0x00000000, 0x00000000, 0x00068308, 0x00068308, 0x00000000 },
3506 { 0x00009a64, 0x00000000, 0x00000000, 0x0006830c, 0x0006830c, 0x00000000 },
3507 { 0x00009a68, 0x00000000, 0x00000000, 0x00068380, 0x00068380, 0x00000000 },
3508 { 0x00009a6c, 0x00000000, 0x00000000, 0x00068384, 0x00068384, 0x00000000 },
3509 { 0x00009a70, 0x00000000, 0x00000000, 0x00068700, 0x00068700, 0x00000000 },
3510 { 0x00009a74, 0x00000000, 0x00000000, 0x00068704, 0x00068704, 0x00000000 },
3511 { 0x00009a78, 0x00000000, 0x00000000, 0x00068708, 0x00068708, 0x00000000 },
3512 { 0x00009a7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c, 0x00000000 },
3513 { 0x00009a80, 0x00000000, 0x00000000, 0x00068780, 0x00068780, 0x00000000 },
3514 { 0x00009a84, 0x00000000, 0x00000000, 0x00068784, 0x00068784, 0x00000000 },
3515 { 0x00009a88, 0x00000000, 0x00000000, 0x00068b04, 0x00068b04, 0x00000000 },
3516 { 0x00009a8c, 0x00000000, 0x00000000, 0x00068b08, 0x00068b08, 0x00000000 },
3517 { 0x00009a90, 0x00000000, 0x00000000, 0x00068b08, 0x00068b08, 0x00000000 },
3518 { 0x00009a94, 0x00000000, 0x00000000, 0x00068b0c, 0x00068b0c, 0x00000000 },
3519 { 0x00009a98, 0x00000000, 0x00000000, 0x00068b80, 0x00068b80, 0x00000000 },
3520 { 0x00009a9c, 0x00000000, 0x00000000, 0x00068b84, 0x00068b84, 0x00000000 },
3521 { 0x00009aa0, 0x00000000, 0x00000000, 0x00068b88, 0x00068b88, 0x00000000 },
3522 { 0x00009aa4, 0x00000000, 0x00000000, 0x00068b8c, 0x00068b8c, 0x00000000 },
3523 { 0x00009aa8, 0x00000000, 0x00000000, 0x000b8b90, 0x000b8b90, 0x00000000 },
3524 { 0x00009aac, 0x00000000, 0x00000000, 0x000b8f80, 0x000b8f80, 0x00000000 },
3525 { 0x00009ab0, 0x00000000, 0x00000000, 0x000b8f84, 0x000b8f84, 0x00000000 },
3526 { 0x00009ab4, 0x00000000, 0x00000000, 0x000b8f88, 0x000b8f88, 0x00000000 },
3527 { 0x00009ab8, 0x00000000, 0x00000000, 0x000b8f8c, 0x000b8f8c, 0x00000000 },
3528 { 0x00009abc, 0x00000000, 0x00000000, 0x000b8f90, 0x000b8f90, 0x00000000 },
3529 { 0x00009ac0, 0x00000000, 0x00000000, 0x000bb30c, 0x000bb30c, 0x00000000 },
3530 { 0x00009ac4, 0x00000000, 0x00000000, 0x000bb310, 0x000bb310, 0x00000000 },
3531 { 0x00009ac8, 0x00000000, 0x00000000, 0x000bb384, 0x000bb384, 0x00000000 },
3532 { 0x00009acc, 0x00000000, 0x00000000, 0x000bb388, 0x000bb388, 0x00000000 },
3533 { 0x00009ad0, 0x00000000, 0x00000000, 0x000bb324, 0x000bb324, 0x00000000 },
3534 { 0x00009ad4, 0x00000000, 0x00000000, 0x000bb704, 0x000bb704, 0x00000000 },
3535 { 0x00009ad8, 0x00000000, 0x00000000, 0x000f96a4, 0x000f96a4, 0x00000000 },
3536 { 0x00009adc, 0x00000000, 0x00000000, 0x000f96a8, 0x000f96a8, 0x00000000 },
3537 { 0x00009ae0, 0x00000000, 0x00000000, 0x000f9710, 0x000f9710, 0x00000000 },
3538 { 0x00009ae4, 0x00000000, 0x00000000, 0x000f9714, 0x000f9714, 0x00000000 },
3539 { 0x00009ae8, 0x00000000, 0x00000000, 0x000f9720, 0x000f9720, 0x00000000 },
3540 { 0x00009aec, 0x00000000, 0x00000000, 0x000f9724, 0x000f9724, 0x00000000 },
3541 { 0x00009af0, 0x00000000, 0x00000000, 0x000f9728, 0x000f9728, 0x00000000 },
3542 { 0x00009af4, 0x00000000, 0x00000000, 0x000f972c, 0x000f972c, 0x00000000 },
3543 { 0x00009af8, 0x00000000, 0x00000000, 0x000f97a0, 0x000f97a0, 0x00000000 },
3544 { 0x00009afc, 0x00000000, 0x00000000, 0x000f97a4, 0x000f97a4, 0x00000000 },
3545 { 0x00009b00, 0x00000000, 0x00000000, 0x000fb7a8, 0x000fb7a8, 0x00000000 },
3546 { 0x00009b04, 0x00000000, 0x00000000, 0x000fb7b0, 0x000fb7b0, 0x00000000 },
3547 { 0x00009b08, 0x00000000, 0x00000000, 0x000fb7b4, 0x000fb7b4, 0x00000000 },
3548 { 0x00009b0c, 0x00000000, 0x00000000, 0x000fb7b8, 0x000fb7b8, 0x00000000 },
3549 { 0x00009b10, 0x00000000, 0x00000000, 0x000fb7a5, 0x000fb7a5, 0x00000000 },
3550 { 0x00009b14, 0x00000000, 0x00000000, 0x000fb7a9, 0x000fb7a9, 0x00000000 },
3551 { 0x00009b18, 0x00000000, 0x00000000, 0x000fb7ad, 0x000fb7ad, 0x00000000 },
3552 { 0x00009b1c, 0x00000000, 0x00000000, 0x000fb7b1, 0x000fb7b1, 0x00000000 },
3553 { 0x00009b20, 0x00000000, 0x00000000, 0x000fb7b5, 0x000fb7b5, 0x00000000 },
3554 { 0x00009b24, 0x00000000, 0x00000000, 0x000fb7b9, 0x000fb7b9, 0x00000000 },
3555 { 0x00009b28, 0x00000000, 0x00000000, 0x000fb7c5, 0x000fb7c5, 0x00000000 },
3556 { 0x00009b2c, 0x00000000, 0x00000000, 0x000fb7c9, 0x000fb7c9, 0x00000000 },
3557 { 0x00009b30, 0x00000000, 0x00000000, 0x000fb7d1, 0x000fb7d1, 0x00000000 },
3558 { 0x00009b34, 0x00000000, 0x00000000, 0x000fb7d5, 0x000fb7d5, 0x00000000 },
3559 { 0x00009b38, 0x00000000, 0x00000000, 0x000fb7d9, 0x000fb7d9, 0x00000000 },
3560 { 0x00009b3c, 0x00000000, 0x00000000, 0x000fb7c6, 0x000fb7c6, 0x00000000 },
3561 { 0x00009b40, 0x00000000, 0x00000000, 0x000fb7ca, 0x000fb7ca, 0x00000000 },
3562 { 0x00009b44, 0x00000000, 0x00000000, 0x000fb7ce, 0x000fb7ce, 0x00000000 },
3563 { 0x00009b48, 0x00000000, 0x00000000, 0x000fb7d2, 0x000fb7d2, 0x00000000 },
3564 { 0x00009b4c, 0x00000000, 0x00000000, 0x000fb7d6, 0x000fb7d6, 0x00000000 },
3565 { 0x00009b50, 0x00000000, 0x00000000, 0x000fb7c3, 0x000fb7c3, 0x00000000 },
3566 { 0x00009b54, 0x00000000, 0x00000000, 0x000fb7c7, 0x000fb7c7, 0x00000000 },
3567 { 0x00009b58, 0x00000000, 0x00000000, 0x000fb7cb, 0x000fb7cb, 0x00000000 },
3568 { 0x00009b5c, 0x00000000, 0x00000000, 0x000fb7cf, 0x000fb7cf, 0x00000000 },
3569 { 0x00009b60, 0x00000000, 0x00000000, 0x000fb7d7, 0x000fb7d7, 0x00000000 },
3570 { 0x00009b64, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
3571 { 0x00009b68, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
3572 { 0x00009b6c, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
3573 { 0x00009b70, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
3574 { 0x00009b74, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
3575 { 0x00009b78, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
3576 { 0x00009b7c, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
3577 { 0x00009b80, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
3578 { 0x00009b84, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
3579 { 0x00009b88, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
3580 { 0x00009b8c, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
3581 { 0x00009b90, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
3582 { 0x00009b94, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
3583 { 0x00009b98, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
3584 { 0x00009b9c, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
3585 { 0x00009ba0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
3586 { 0x00009ba4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
3587 { 0x00009ba8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
3588 { 0x00009bac, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
3589 { 0x00009bb0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
3590 { 0x00009bb4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
3591 { 0x00009bb8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
3592 { 0x00009bbc, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
3593 { 0x00009bc0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
3594 { 0x00009bc4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
3595 { 0x00009bc8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
3596 { 0x00009bcc, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
3597 { 0x00009bd0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
3598 { 0x00009bd4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
3599 { 0x00009bd8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
3600 { 0x00009bdc, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
3601 { 0x00009be0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
3602 { 0x00009be4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
3603 { 0x00009be8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
3604 { 0x00009bec, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
3605 { 0x00009bf0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
3606 { 0x00009bf4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
3607 { 0x00009bf8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
3608 { 0x00009bfc, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
3609 { 0x0000aa00, 0x00000000, 0x00000000, 0x0006801c, 0x0006801c, 0x00000000 },
3610 { 0x0000aa04, 0x00000000, 0x00000000, 0x00068080, 0x00068080, 0x00000000 },
3611 { 0x0000aa08, 0x00000000, 0x00000000, 0x00068084, 0x00068084, 0x00000000 },
3612 { 0x0000aa0c, 0x00000000, 0x00000000, 0x00068088, 0x00068088, 0x00000000 },
3613 { 0x0000aa10, 0x00000000, 0x00000000, 0x0006808c, 0x0006808c, 0x00000000 },
3614 { 0x0000aa14, 0x00000000, 0x00000000, 0x00068100, 0x00068100, 0x00000000 },
3615 { 0x0000aa18, 0x00000000, 0x00000000, 0x00068104, 0x00068104, 0x00000000 },
3616 { 0x0000aa1c, 0x00000000, 0x00000000, 0x00068108, 0x00068108, 0x00000000 },
3617 { 0x0000aa20, 0x00000000, 0x00000000, 0x0006810c, 0x0006810c, 0x00000000 },
3618 { 0x0000aa24, 0x00000000, 0x00000000, 0x00068110, 0x00068110, 0x00000000 },
3619 { 0x0000aa28, 0x00000000, 0x00000000, 0x00068110, 0x00068110, 0x00000000 },
3620 { 0x0000aa2c, 0x00000000, 0x00000000, 0x00068180, 0x00068180, 0x00000000 },
3621 { 0x0000aa30, 0x00000000, 0x00000000, 0x00068184, 0x00068184, 0x00000000 },
3622 { 0x0000aa34, 0x00000000, 0x00000000, 0x00068188, 0x00068188, 0x00000000 },
3623 { 0x0000aa38, 0x00000000, 0x00000000, 0x0006818c, 0x0006818c, 0x00000000 },
3624 { 0x0000aa3c, 0x00000000, 0x00000000, 0x00068190, 0x00068190, 0x00000000 },
3625 { 0x0000aa40, 0x00000000, 0x00000000, 0x00068194, 0x00068194, 0x00000000 },
3626 { 0x0000aa44, 0x00000000, 0x00000000, 0x000681a0, 0x000681a0, 0x00000000 },
3627 { 0x0000aa48, 0x00000000, 0x00000000, 0x0006820c, 0x0006820c, 0x00000000 },
3628 { 0x0000aa4c, 0x00000000, 0x00000000, 0x000681a8, 0x000681a8, 0x00000000 },
3629 { 0x0000aa50, 0x00000000, 0x00000000, 0x000681ac, 0x000681ac, 0x00000000 },
3630 { 0x0000aa54, 0x00000000, 0x00000000, 0x0006821c, 0x0006821c, 0x00000000 },
3631 { 0x0000aa58, 0x00000000, 0x00000000, 0x00068224, 0x00068224, 0x00000000 },
3632 { 0x0000aa5c, 0x00000000, 0x00000000, 0x00068290, 0x00068290, 0x00000000 },
3633 { 0x0000aa60, 0x00000000, 0x00000000, 0x00068300, 0x00068300, 0x00000000 },
3634 { 0x0000aa64, 0x00000000, 0x00000000, 0x00068308, 0x00068308, 0x00000000 },
3635 { 0x0000aa68, 0x00000000, 0x00000000, 0x0006830c, 0x0006830c, 0x00000000 },
3636 { 0x0000aa6c, 0x00000000, 0x00000000, 0x00068310, 0x00068310, 0x00000000 },
3637 { 0x0000aa70, 0x00000000, 0x00000000, 0x00068788, 0x00068788, 0x00000000 },
3638 { 0x0000aa74, 0x00000000, 0x00000000, 0x0006878c, 0x0006878c, 0x00000000 },
3639 { 0x0000aa78, 0x00000000, 0x00000000, 0x00068790, 0x00068790, 0x00000000 },
3640 { 0x0000aa7c, 0x00000000, 0x00000000, 0x00068794, 0x00068794, 0x00000000 },
3641 { 0x0000aa80, 0x00000000, 0x00000000, 0x00068798, 0x00068798, 0x00000000 },
3642 { 0x0000aa84, 0x00000000, 0x00000000, 0x0006879c, 0x0006879c, 0x00000000 },
3643 { 0x0000aa88, 0x00000000, 0x00000000, 0x00068b89, 0x00068b89, 0x00000000 },
3644 { 0x0000aa8c, 0x00000000, 0x00000000, 0x00068b8d, 0x00068b8d, 0x00000000 },
3645 { 0x0000aa90, 0x00000000, 0x00000000, 0x00068b91, 0x00068b91, 0x00000000 },
3646 { 0x0000aa94, 0x00000000, 0x00000000, 0x00068b95, 0x00068b95, 0x00000000 },
3647 { 0x0000aa98, 0x00000000, 0x00000000, 0x00068b99, 0x00068b99, 0x00000000 },
3648 { 0x0000aa9c, 0x00000000, 0x00000000, 0x00068ba5, 0x00068ba5, 0x00000000 },
3649 { 0x0000aaa0, 0x00000000, 0x00000000, 0x00068ba9, 0x00068ba9, 0x00000000 },
3650 { 0x0000aaa4, 0x00000000, 0x00000000, 0x00068bad, 0x00068bad, 0x00000000 },
3651 { 0x0000aaa8, 0x00000000, 0x00000000, 0x000b8b0c, 0x000b8b0c, 0x00000000 },
3652 { 0x0000aaac, 0x00000000, 0x00000000, 0x000b8f10, 0x000b8f10, 0x00000000 },
3653 { 0x0000aab0, 0x00000000, 0x00000000, 0x000b8f14, 0x000b8f14, 0x00000000 },
3654 { 0x0000aab4, 0x00000000, 0x00000000, 0x000b8f84, 0x000b8f84, 0x00000000 },
3655 { 0x0000aab8, 0x00000000, 0x00000000, 0x000b8f84, 0x000b8f84, 0x00000000 },
3656 { 0x0000aabc, 0x00000000, 0x00000000, 0x000b8f88, 0x000b8f88, 0x00000000 },
3657 { 0x0000aac0, 0x00000000, 0x00000000, 0x000bb380, 0x000bb380, 0x00000000 },
3658 { 0x0000aac4, 0x00000000, 0x00000000, 0x000bb384, 0x000bb384, 0x00000000 },
3659 { 0x0000aac8, 0x00000000, 0x00000000, 0x000bb388, 0x000bb388, 0x00000000 },
3660 { 0x0000aacc, 0x00000000, 0x00000000, 0x000bb38c, 0x000bb38c, 0x00000000 },
3661 { 0x0000aad0, 0x00000000, 0x00000000, 0x000bb394, 0x000bb394, 0x00000000 },
3662 { 0x0000aad4, 0x00000000, 0x00000000, 0x000bb798, 0x000bb798, 0x00000000 },
3663 { 0x0000aad8, 0x00000000, 0x00000000, 0x000f970c, 0x000f970c, 0x00000000 },
3664 { 0x0000aadc, 0x00000000, 0x00000000, 0x000f9710, 0x000f9710, 0x00000000 },
3665 { 0x0000aae0, 0x00000000, 0x00000000, 0x000f9714, 0x000f9714, 0x00000000 },
3666 { 0x0000aae4, 0x00000000, 0x00000000, 0x000f9718, 0x000f9718, 0x00000000 },
3667 { 0x0000aae8, 0x00000000, 0x00000000, 0x000f9705, 0x000f9705, 0x00000000 },
3668 { 0x0000aaec, 0x00000000, 0x00000000, 0x000f9709, 0x000f9709, 0x00000000 },
3669 { 0x0000aaf0, 0x00000000, 0x00000000, 0x000f970d, 0x000f970d, 0x00000000 },
3670 { 0x0000aaf4, 0x00000000, 0x00000000, 0x000f9711, 0x000f9711, 0x00000000 },
3671 { 0x0000aaf8, 0x00000000, 0x00000000, 0x000f9715, 0x000f9715, 0x00000000 },
3672 { 0x0000aafc, 0x00000000, 0x00000000, 0x000f9719, 0x000f9719, 0x00000000 },
3673 { 0x0000ab00, 0x00000000, 0x00000000, 0x000fb7a4, 0x000fb7a4, 0x00000000 },
3674 { 0x0000ab04, 0x00000000, 0x00000000, 0x000fb7a8, 0x000fb7a8, 0x00000000 },
3675 { 0x0000ab08, 0x00000000, 0x00000000, 0x000fb7ac, 0x000fb7ac, 0x00000000 },
3676 { 0x0000ab0c, 0x00000000, 0x00000000, 0x000fb7ac, 0x000fb7ac, 0x00000000 },
3677 { 0x0000ab10, 0x00000000, 0x00000000, 0x000fb7b0, 0x000fb7b0, 0x00000000 },
3678 { 0x0000ab14, 0x00000000, 0x00000000, 0x000fb7b8, 0x000fb7b8, 0x00000000 },
3679 { 0x0000ab18, 0x00000000, 0x00000000, 0x000fb7bc, 0x000fb7bc, 0x00000000 },
3680 { 0x0000ab1c, 0x00000000, 0x00000000, 0x000fb7a1, 0x000fb7a1, 0x00000000 },
3681 { 0x0000ab20, 0x00000000, 0x00000000, 0x000fb7a5, 0x000fb7a5, 0x00000000 },
3682 { 0x0000ab24, 0x00000000, 0x00000000, 0x000fb7a9, 0x000fb7a9, 0x00000000 },
3683 { 0x0000ab28, 0x00000000, 0x00000000, 0x000fb7b1, 0x000fb7b1, 0x00000000 },
3684 { 0x0000ab2c, 0x00000000, 0x00000000, 0x000fb7b5, 0x000fb7b5, 0x00000000 },
3685 { 0x0000ab30, 0x00000000, 0x00000000, 0x000fb7bd, 0x000fb7bd, 0x00000000 },
3686 { 0x0000ab34, 0x00000000, 0x00000000, 0x000fb7c9, 0x000fb7c9, 0x00000000 },
3687 { 0x0000ab38, 0x00000000, 0x00000000, 0x000fb7cd, 0x000fb7cd, 0x00000000 },
3688 { 0x0000ab3c, 0x00000000, 0x00000000, 0x000fb7d1, 0x000fb7d1, 0x00000000 },
3689 { 0x0000ab40, 0x00000000, 0x00000000, 0x000fb7d9, 0x000fb7d9, 0x00000000 },
3690 { 0x0000ab44, 0x00000000, 0x00000000, 0x000fb7c2, 0x000fb7c2, 0x00000000 },
3691 { 0x0000ab48, 0x00000000, 0x00000000, 0x000fb7c6, 0x000fb7c6, 0x00000000 },
3692 { 0x0000ab4c, 0x00000000, 0x00000000, 0x000fb7ca, 0x000fb7ca, 0x00000000 },
3693 { 0x0000ab50, 0x00000000, 0x00000000, 0x000fb7ce, 0x000fb7ce, 0x00000000 },
3694 { 0x0000ab54, 0x00000000, 0x00000000, 0x000fb7d2, 0x000fb7d2, 0x00000000 },
3695 { 0x0000ab58, 0x00000000, 0x00000000, 0x000fb7d6, 0x000fb7d6, 0x00000000 },
3696 { 0x0000ab5c, 0x00000000, 0x00000000, 0x000fb7c3, 0x000fb7c3, 0x00000000 },
3697 { 0x0000ab60, 0x00000000, 0x00000000, 0x000fb7cb, 0x000fb7cb, 0x00000000 },
3698 { 0x0000ab64, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
3699 { 0x0000ab68, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
3700 { 0x0000ab6c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
3701 { 0x0000ab70, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
3702 { 0x0000ab74, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
3703 { 0x0000ab78, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
3704 { 0x0000ab7c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
3705 { 0x0000ab80, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
3706 { 0x0000ab84, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
3707 { 0x0000ab88, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
3708 { 0x0000ab8c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
3709 { 0x0000ab90, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
3710 { 0x0000ab94, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
3711 { 0x0000ab98, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
3712 { 0x0000ab9c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
3713 { 0x0000aba0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
3714 { 0x0000aba4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
3715 { 0x0000aba8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
3716 { 0x0000abac, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
3717 { 0x0000abb0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
3718 { 0x0000abb4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
3719 { 0x0000abb8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
3720 { 0x0000abbc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
3721 { 0x0000abc0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
3722 { 0x0000abc4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
3723 { 0x0000abc8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
3724 { 0x0000abcc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
3725 { 0x0000abd0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
3726 { 0x0000abd4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
3727 { 0x0000abd8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
3728 { 0x0000abdc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
3729 { 0x0000abe0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
3730 { 0x0000abe4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
3731 { 0x0000abe8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
3732 { 0x0000abec, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
3733 { 0x0000abf0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
3734 { 0x0000abf4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
3735 { 0x0000abf8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
3736 { 0x0000abfc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
3737 { 0x0000a204, 0x00000004, 0x00000004, 0x00000004, 0x00000004, 0x00000004 },
3738 { 0x0000a20c, 0x00000014, 0x00000014, 0x00000000, 0x00000000, 0x0001f000 },
3739 { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
3740 { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
3741 { 0x0000a250, 0x001ff000, 0x001ff000, 0x001ca000, 0x001ca000, 0x001da000 },
3742 { 0x0000a274, 0x0a81c652, 0x0a81c652, 0x0a820652, 0x0a820652, 0x0a82a652 },
3743 { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
3744 { 0x0000a304, 0x00000000, 0x00000000, 0x00007201, 0x00007201, 0x00000000 },
3745 { 0x0000a308, 0x00000000, 0x00000000, 0x00010408, 0x00010408, 0x00000000 },
3746 { 0x0000a30c, 0x00000000, 0x00000000, 0x0001860a, 0x0001860a, 0x00000000 },
3747 { 0x0000a310, 0x00000000, 0x00000000, 0x00020818, 0x00020818, 0x00000000 },
3748 { 0x0000a314, 0x00000000, 0x00000000, 0x00024858, 0x00024858, 0x00000000 },
3749 { 0x0000a318, 0x00000000, 0x00000000, 0x00026859, 0x00026859, 0x00000000 },
3750 { 0x0000a31c, 0x00000000, 0x00000000, 0x0002985b, 0x0002985b, 0x00000000 },
3751 { 0x0000a320, 0x00000000, 0x00000000, 0x0002c89a, 0x0002c89a, 0x00000000 },
3752 { 0x0000a324, 0x00000000, 0x00000000, 0x0002e89b, 0x0002e89b, 0x00000000 },
3753 { 0x0000a328, 0x00000000, 0x00000000, 0x0003089c, 0x0003089c, 0x00000000 },
3754 { 0x0000a32c, 0x00000000, 0x00000000, 0x0003289d, 0x0003289d, 0x00000000 },
3755 { 0x0000a330, 0x00000000, 0x00000000, 0x0003489e, 0x0003489e, 0x00000000 },
3756 { 0x0000a334, 0x00000000, 0x00000000, 0x000388de, 0x000388de, 0x00000000 },
3757 { 0x0000a338, 0x00000000, 0x00000000, 0x0003b91e, 0x0003b91e, 0x00000000 },
3758 { 0x0000a33c, 0x00000000, 0x00000000, 0x0003d95e, 0x0003d95e, 0x00000000 },
3759 { 0x0000a340, 0x00000000, 0x00000000, 0x000419df, 0x000419df, 0x00000000 },
3760 { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
3761 { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
3762};
3763
3764static const u_int32_t ar9285Common_9285[][2] = {
3765 { 0x0000000c, 0x00000000 },
3766 { 0x00000030, 0x00020045 },
3767 { 0x00000034, 0x00000005 },
3768 { 0x00000040, 0x00000000 },
3769 { 0x00000044, 0x00000008 },
3770 { 0x00000048, 0x00000008 },
3771 { 0x0000004c, 0x00000010 },
3772 { 0x00000050, 0x00000000 },
3773 { 0x00000054, 0x0000001f },
3774 { 0x00000800, 0x00000000 },
3775 { 0x00000804, 0x00000000 },
3776 { 0x00000808, 0x00000000 },
3777 { 0x0000080c, 0x00000000 },
3778 { 0x00000810, 0x00000000 },
3779 { 0x00000814, 0x00000000 },
3780 { 0x00000818, 0x00000000 },
3781 { 0x0000081c, 0x00000000 },
3782 { 0x00000820, 0x00000000 },
3783 { 0x00000824, 0x00000000 },
3784 { 0x00001040, 0x002ffc0f },
3785 { 0x00001044, 0x002ffc0f },
3786 { 0x00001048, 0x002ffc0f },
3787 { 0x0000104c, 0x002ffc0f },
3788 { 0x00001050, 0x002ffc0f },
3789 { 0x00001054, 0x002ffc0f },
3790 { 0x00001058, 0x002ffc0f },
3791 { 0x0000105c, 0x002ffc0f },
3792 { 0x00001060, 0x002ffc0f },
3793 { 0x00001064, 0x002ffc0f },
3794 { 0x00001230, 0x00000000 },
3795 { 0x00001270, 0x00000000 },
3796 { 0x00001038, 0x00000000 },
3797 { 0x00001078, 0x00000000 },
3798 { 0x000010b8, 0x00000000 },
3799 { 0x000010f8, 0x00000000 },
3800 { 0x00001138, 0x00000000 },
3801 { 0x00001178, 0x00000000 },
3802 { 0x000011b8, 0x00000000 },
3803 { 0x000011f8, 0x00000000 },
3804 { 0x00001238, 0x00000000 },
3805 { 0x00001278, 0x00000000 },
3806 { 0x000012b8, 0x00000000 },
3807 { 0x000012f8, 0x00000000 },
3808 { 0x00001338, 0x00000000 },
3809 { 0x00001378, 0x00000000 },
3810 { 0x000013b8, 0x00000000 },
3811 { 0x000013f8, 0x00000000 },
3812 { 0x00001438, 0x00000000 },
3813 { 0x00001478, 0x00000000 },
3814 { 0x000014b8, 0x00000000 },
3815 { 0x000014f8, 0x00000000 },
3816 { 0x00001538, 0x00000000 },
3817 { 0x00001578, 0x00000000 },
3818 { 0x000015b8, 0x00000000 },
3819 { 0x000015f8, 0x00000000 },
3820 { 0x00001638, 0x00000000 },
3821 { 0x00001678, 0x00000000 },
3822 { 0x000016b8, 0x00000000 },
3823 { 0x000016f8, 0x00000000 },
3824 { 0x00001738, 0x00000000 },
3825 { 0x00001778, 0x00000000 },
3826 { 0x000017b8, 0x00000000 },
3827 { 0x000017f8, 0x00000000 },
3828 { 0x0000103c, 0x00000000 },
3829 { 0x0000107c, 0x00000000 },
3830 { 0x000010bc, 0x00000000 },
3831 { 0x000010fc, 0x00000000 },
3832 { 0x0000113c, 0x00000000 },
3833 { 0x0000117c, 0x00000000 },
3834 { 0x000011bc, 0x00000000 },
3835 { 0x000011fc, 0x00000000 },
3836 { 0x0000123c, 0x00000000 },
3837 { 0x0000127c, 0x00000000 },
3838 { 0x000012bc, 0x00000000 },
3839 { 0x000012fc, 0x00000000 },
3840 { 0x0000133c, 0x00000000 },
3841 { 0x0000137c, 0x00000000 },
3842 { 0x000013bc, 0x00000000 },
3843 { 0x000013fc, 0x00000000 },
3844 { 0x0000143c, 0x00000000 },
3845 { 0x0000147c, 0x00000000 },
3846 { 0x00004030, 0x00000002 },
3847 { 0x0000403c, 0x00000002 },
3848 { 0x00004024, 0x0000001f },
3849 { 0x00004060, 0x00000000 },
3850 { 0x00004064, 0x00000000 },
3851 { 0x00007010, 0x00000031 },
3852 { 0x00007034, 0x00000002 },
3853 { 0x00007038, 0x000004c2 },
3854 { 0x00008004, 0x00000000 },
3855 { 0x00008008, 0x00000000 },
3856 { 0x0000800c, 0x00000000 },
3857 { 0x00008018, 0x00000700 },
3858 { 0x00008020, 0x00000000 },
3859 { 0x00008038, 0x00000000 },
3860 { 0x0000803c, 0x00000000 },
3861 { 0x00008048, 0x00000000 },
3862 { 0x00008054, 0x00000000 },
3863 { 0x00008058, 0x00000000 },
3864 { 0x0000805c, 0x000fc78f },
3865 { 0x00008060, 0x0000000f },
3866 { 0x00008064, 0x00000000 },
3867 { 0x00008070, 0x00000000 },
3868 { 0x000080c0, 0x2a80001a },
3869 { 0x000080c4, 0x05dc01e0 },
3870 { 0x000080c8, 0x1f402710 },
3871 { 0x000080cc, 0x01f40000 },
3872 { 0x000080d0, 0x00001e00 },
3873 { 0x000080d4, 0x00000000 },
3874 { 0x000080d8, 0x00400000 },
3875 { 0x000080e0, 0xffffffff },
3876 { 0x000080e4, 0x0000ffff },
3877 { 0x000080e8, 0x003f3f3f },
3878 { 0x000080ec, 0x00000000 },
3879 { 0x000080f0, 0x00000000 },
3880 { 0x000080f4, 0x00000000 },
3881 { 0x000080f8, 0x00000000 },
3882 { 0x000080fc, 0x00020000 },
3883 { 0x00008100, 0x00020000 },
3884 { 0x00008104, 0x00000001 },
3885 { 0x00008108, 0x00000052 },
3886 { 0x0000810c, 0x00000000 },
3887 { 0x00008110, 0x00000168 },
3888 { 0x00008118, 0x000100aa },
3889 { 0x0000811c, 0x00003210 },
3890 { 0x00008120, 0x08f04800 },
3891 { 0x00008124, 0x00000000 },
3892 { 0x00008128, 0x00000000 },
3893 { 0x0000812c, 0x00000000 },
3894 { 0x00008130, 0x00000000 },
3895 { 0x00008134, 0x00000000 },
3896 { 0x00008138, 0x00000000 },
3897 { 0x0000813c, 0x00000000 },
3898 { 0x00008144, 0x00000000 },
3899 { 0x00008168, 0x00000000 },
3900 { 0x0000816c, 0x00000000 },
3901 { 0x00008170, 0x32143320 },
3902 { 0x00008174, 0xfaa4fa50 },
3903 { 0x00008178, 0x00000100 },
3904 { 0x0000817c, 0x00000000 },
3905 { 0x000081c0, 0x00000000 },
3906 { 0x000081d0, 0x00003210 },
3907 { 0x000081ec, 0x00000000 },
3908 { 0x000081f0, 0x00000000 },
3909 { 0x000081f4, 0x00000000 },
3910 { 0x000081f8, 0x00000000 },
3911 { 0x000081fc, 0x00000000 },
3912 { 0x00008200, 0x00000000 },
3913 { 0x00008204, 0x00000000 },
3914 { 0x00008208, 0x00000000 },
3915 { 0x0000820c, 0x00000000 },
3916 { 0x00008210, 0x00000000 },
3917 { 0x00008214, 0x00000000 },
3918 { 0x00008218, 0x00000000 },
3919 { 0x0000821c, 0x00000000 },
3920 { 0x00008220, 0x00000000 },
3921 { 0x00008224, 0x00000000 },
3922 { 0x00008228, 0x00000000 },
3923 { 0x0000822c, 0x00000000 },
3924 { 0x00008230, 0x00000000 },
3925 { 0x00008234, 0x00000000 },
3926 { 0x00008238, 0x00000000 },
3927 { 0x0000823c, 0x00000000 },
3928 { 0x00008240, 0x00100000 },
3929 { 0x00008244, 0x0010f400 },
3930 { 0x00008248, 0x00000100 },
3931 { 0x0000824c, 0x0001e800 },
3932 { 0x00008250, 0x00000000 },
3933 { 0x00008254, 0x00000000 },
3934 { 0x00008258, 0x00000000 },
3935 { 0x0000825c, 0x400000ff },
3936 { 0x00008260, 0x00080922 },
3937 { 0x00008264, 0xa8a00010 },
3938 { 0x00008270, 0x00000000 },
3939 { 0x00008274, 0x40000000 },
3940 { 0x00008278, 0x003e4180 },
3941 { 0x0000827c, 0x00000000 },
3942 { 0x00008284, 0x0000002c },
3943 { 0x00008288, 0x0000002c },
3944 { 0x0000828c, 0x00000000 },
3945 { 0x00008294, 0x00000000 },
3946 { 0x00008298, 0x00000000 },
3947 { 0x0000829c, 0x00000000 },
3948 { 0x00008300, 0x00000040 },
3949 { 0x00008314, 0x00000000 },
3950 { 0x00008328, 0x00000000 },
3951 { 0x0000832c, 0x00000001 },
3952 { 0x00008330, 0x00000302 },
3953 { 0x00008334, 0x00000e00 },
3954 { 0x00008338, 0x00000000 },
3955 { 0x0000833c, 0x00000000 },
3956 { 0x00008340, 0x00010380 },
3957 { 0x00008344, 0x00581043 },
3958 { 0x00009808, 0x00000000 },
3959 { 0x0000980c, 0xafe68e30 },
3960 { 0x00009810, 0xfd14e000 },
3961 { 0x00009814, 0x9c0a9f6b },
3962 { 0x0000981c, 0x00000000 },
3963 { 0x0000982c, 0x0000a000 },
3964 { 0x00009830, 0x00000000 },
3965 { 0x0000983c, 0x00200400 },
3966 { 0x0000984c, 0x0040233c },
3967 { 0x00009854, 0x00000044 },
3968 { 0x00009900, 0x00000000 },
3969 { 0x00009904, 0x00000000 },
3970 { 0x00009908, 0x00000000 },
3971 { 0x0000990c, 0x00000000 },
3972 { 0x00009910, 0x01002310 },
3973 { 0x0000991c, 0x10000fff },
3974 { 0x00009920, 0x04900000 },
3975 { 0x00009928, 0x00000001 },
3976 { 0x0000992c, 0x00000004 },
3977 { 0x00009934, 0x1e1f2022 },
3978 { 0x00009938, 0x0a0b0c0d },
3979 { 0x0000993c, 0x00000000 },
3980 { 0x00009940, 0x14750604 },
3981 { 0x00009948, 0x9280c00a },
3982 { 0x0000994c, 0x00020028 },
3983 { 0x00009954, 0x5f3ca3de },
3984 { 0x00009958, 0x2108ecff },
3985 { 0x00009968, 0x000003ce },
3986 { 0x00009970, 0x1927b515 },
3987 { 0x00009974, 0x00000000 },
3988 { 0x00009978, 0x00000001 },
3989 { 0x0000997c, 0x00000000 },
3990 { 0x00009980, 0x00000000 },
3991 { 0x00009984, 0x00000000 },
3992 { 0x00009988, 0x00000000 },
3993 { 0x0000998c, 0x00000000 },
3994 { 0x00009990, 0x00000000 },
3995 { 0x00009994, 0x00000000 },
3996 { 0x00009998, 0x00000000 },
3997 { 0x0000999c, 0x00000000 },
3998 { 0x000099a0, 0x00000000 },
3999 { 0x000099a4, 0x00000001 },
4000 { 0x000099a8, 0x201fff00 },
4001 { 0x000099ac, 0x2def0a00 },
4002 { 0x000099b0, 0x03051000 },
4003 { 0x000099b4, 0x00000820 },
4004 { 0x000099dc, 0x00000000 },
4005 { 0x000099e0, 0x00000000 },
4006 { 0x000099e4, 0xaaaaaaaa },
4007 { 0x000099e8, 0x3c466478 },
4008 { 0x000099ec, 0x0cc80caa },
4009 { 0x000099f0, 0x00000000 },
4010 { 0x0000a208, 0x803e6788 },
4011 { 0x0000a210, 0x4080a333 },
4012 { 0x0000a214, 0x00206c10 },
4013 { 0x0000a218, 0x009c4060 },
4014 { 0x0000a220, 0x01834061 },
4015 { 0x0000a224, 0x00000400 },
4016 { 0x0000a228, 0x000003b5 },
4017 { 0x0000a22c, 0x00000000 },
4018 { 0x0000a234, 0x20202020 },
4019 { 0x0000a238, 0x20202020 },
4020 { 0x0000a244, 0x00000000 },
4021 { 0x0000a248, 0xfffffffc },
4022 { 0x0000a24c, 0x00000000 },
4023 { 0x0000a254, 0x00000000 },
4024 { 0x0000a258, 0x0ccb5380 },
4025 { 0x0000a25c, 0x15151501 },
4026 { 0x0000a260, 0xdfa90f01 },
4027 { 0x0000a268, 0x00000000 },
4028 { 0x0000a26c, 0x0ebae9e6 },
4029 { 0x0000d270, 0x0d820820 },
4030 { 0x0000a278, 0x39ce739c },
4031 { 0x0000a27c, 0x050e039c },
4032 { 0x0000d35c, 0x07ffffef },
4033 { 0x0000d360, 0x0fffffe7 },
4034 { 0x0000d364, 0x17ffffe5 },
4035 { 0x0000d368, 0x1fffffe4 },
4036 { 0x0000d36c, 0x37ffffe3 },
4037 { 0x0000d370, 0x3fffffe3 },
4038 { 0x0000d374, 0x57ffffe3 },
4039 { 0x0000d378, 0x5fffffe2 },
4040 { 0x0000d37c, 0x7fffffe2 },
4041 { 0x0000d380, 0x7f3c7bba },
4042 { 0x0000d384, 0xf3307ff0 },
4043 { 0x0000a388, 0x0c000000 },
4044 { 0x0000a38c, 0x20202020 },
4045 { 0x0000a390, 0x20202020 },
4046 { 0x0000a394, 0x39ce739c },
4047 { 0x0000a398, 0x0000039c },
4048 { 0x0000a39c, 0x00000001 },
4049 { 0x0000a3a0, 0x00000000 },
4050 { 0x0000a3a4, 0x00000000 },
4051 { 0x0000a3a8, 0x00000000 },
4052 { 0x0000a3ac, 0x00000000 },
4053 { 0x0000a3b0, 0x00000000 },
4054 { 0x0000a3b4, 0x00000000 },
4055 { 0x0000a3b8, 0x00000000 },
4056 { 0x0000a3bc, 0x00000000 },
4057 { 0x0000a3c0, 0x00000000 },
4058 { 0x0000a3c4, 0x00000000 },
4059 { 0x0000a3cc, 0x20202020 },
4060 { 0x0000a3d0, 0x20202020 },
4061 { 0x0000a3d4, 0x20202020 },
4062 { 0x0000a3dc, 0x39ce739c },
4063 { 0x0000a3e0, 0x0000039c },
4064 { 0x0000a3e4, 0x00000000 },
4065 { 0x0000a3e8, 0x18c43433 },
4066 { 0x0000a3ec, 0x00f70081 },
4067 { 0x00007800, 0x00140000 },
4068 { 0x00007804, 0x0e4548d8 },
4069 { 0x00007808, 0x54214514 },
4070 { 0x0000780c, 0x02025820 },
4071 { 0x00007810, 0x71c0d388 },
4072 { 0x00007814, 0x924934a8 },
4073 { 0x0000781c, 0x00000000 },
4074 { 0x00007820, 0x00000c04 },
4075 { 0x00007824, 0x00d86fff },
4076 { 0x00007828, 0x26d2491b },
4077 { 0x0000782c, 0x6e36d97b },
4078 { 0x00007830, 0xedb6d96c },
4079 { 0x00007834, 0x71400086 },
4080 { 0x00007838, 0xfac68800 },
4081 { 0x0000783c, 0x0001fffe },
4082 { 0x00007840, 0xffeb1a20 },
4083 { 0x00007844, 0x000c0db6 },
4084 { 0x00007848, 0x6db61b6f },
4085 { 0x0000784c, 0x6d9b66db },
4086 { 0x00007850, 0x6d8c6dba },
4087 { 0x00007854, 0x00040000 },
4088 { 0x00007858, 0xdb003012 },
4089 { 0x0000785c, 0x04924914 },
4090 { 0x00007860, 0x21084210 },
4091 { 0x00007864, 0xf7d7ffde },
4092 { 0x00007868, 0xc2034080 },
4093 { 0x0000786c, 0x48609eb4 },
4094 { 0x00007870, 0x10142c00 },
4095};
4096
4097static const u_int32_t ar9285PciePhy_clkreq_always_on_L1_9285[][2] = {
4098 {0x00004040, 0x9248fd00 },
4099 {0x00004040, 0x24924924 },
4100 {0x00004040, 0xa8000019 },
4101 {0x00004040, 0x13160820 },
4102 {0x00004040, 0xe5980560 },
4103 {0x00004040, 0xc01dcffd },
4104 {0x00004040, 0x1aaabe41 },
4105 {0x00004040, 0xbe105554 },
4106 {0x00004040, 0x00043007 },
4107 {0x00004044, 0x00000000 },
4108};
4109
4110static const u_int32_t ar9285PciePhy_clkreq_off_L1_9285[][2] = {
4111 {0x00004040, 0x9248fd00 },
4112 {0x00004040, 0x24924924 },
4113 {0x00004040, 0xa8000019 },
4114 {0x00004040, 0x13160820 },
4115 {0x00004040, 0xe5980560 },
4116 {0x00004040, 0xc01dcffc },
4117 {0x00004040, 0x1aaabe41 },
4118 {0x00004040, 0xbe105554 },
4119 {0x00004040, 0x00043007 },
4120 {0x00004044, 0x00000000 },
4121};
4122
4123static const u_int32_t ar9285Modes_9285_1_2[][6] = {
4124 { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
4125 { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
4126 { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
4127 { 0x000010f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008 },
4128 { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
4129 { 0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b, 0x0988004f },
4130 { 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 },
4131 { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
4132 { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
4133 { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
4134 { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
4135 { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
4136 { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
4137 { 0x00009840, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e },
4138 { 0x00009844, 0x0372161e, 0x0372161e, 0x03720020, 0x03720020, 0x037216a0 },
4139 { 0x00009848, 0x00001066, 0x00001066, 0x00000057, 0x00000057, 0x00001059 },
4140 { 0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2 },
4141 { 0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
4142 { 0x0000985c, 0x3139605e, 0x3139605e, 0x3136605e, 0x3136605e, 0x3139605e },
4143 { 0x00009860, 0x00058d18, 0x00058d18, 0x00058d20, 0x00058d20, 0x00058d18 },
4144 { 0x00009864, 0x0000fe00, 0x0000fe00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
4145 { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
4146 { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 },
4147 { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
4148 { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
4149 { 0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d, 0xd00a800d },
4150 { 0x00009944, 0xffbc1010, 0xffbc1010, 0xffbc1020, 0xffbc1020, 0xffbc1010 },
4151 { 0x00009960, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
4152 { 0x00009964, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
4153 { 0x000099b8, 0x0000421c, 0x0000421c, 0x0000421c, 0x0000421c, 0x0000421c },
4154 { 0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00 },
4155 { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
4156 { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
4157 { 0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329 },
4158 { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
4159 { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
4160 { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
4161 { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
4162 { 0x00009a00, 0x00000000, 0x00000000, 0x00068084, 0x00068084, 0x00000000 },
4163 { 0x00009a04, 0x00000000, 0x00000000, 0x00068088, 0x00068088, 0x00000000 },
4164 { 0x00009a08, 0x00000000, 0x00000000, 0x0006808c, 0x0006808c, 0x00000000 },
4165 { 0x00009a0c, 0x00000000, 0x00000000, 0x00068100, 0x00068100, 0x00000000 },
4166 { 0x00009a10, 0x00000000, 0x00000000, 0x00068104, 0x00068104, 0x00000000 },
4167 { 0x00009a14, 0x00000000, 0x00000000, 0x00068108, 0x00068108, 0x00000000 },
4168 { 0x00009a18, 0x00000000, 0x00000000, 0x0006810c, 0x0006810c, 0x00000000 },
4169 { 0x00009a1c, 0x00000000, 0x00000000, 0x00068110, 0x00068110, 0x00000000 },
4170 { 0x00009a20, 0x00000000, 0x00000000, 0x00068114, 0x00068114, 0x00000000 },
4171 { 0x00009a24, 0x00000000, 0x00000000, 0x00068180, 0x00068180, 0x00000000 },
4172 { 0x00009a28, 0x00000000, 0x00000000, 0x00068184, 0x00068184, 0x00000000 },
4173 { 0x00009a2c, 0x00000000, 0x00000000, 0x00068188, 0x00068188, 0x00000000 },
4174 { 0x00009a30, 0x00000000, 0x00000000, 0x0006818c, 0x0006818c, 0x00000000 },
4175 { 0x00009a34, 0x00000000, 0x00000000, 0x00068190, 0x00068190, 0x00000000 },
4176 { 0x00009a38, 0x00000000, 0x00000000, 0x00068194, 0x00068194, 0x00000000 },
4177 { 0x00009a3c, 0x00000000, 0x00000000, 0x000681a0, 0x000681a0, 0x00000000 },
4178 { 0x00009a40, 0x00000000, 0x00000000, 0x0006820c, 0x0006820c, 0x00000000 },
4179 { 0x00009a44, 0x00000000, 0x00000000, 0x000681a8, 0x000681a8, 0x00000000 },
4180 { 0x00009a48, 0x00000000, 0x00000000, 0x00068284, 0x00068284, 0x00000000 },
4181 { 0x00009a4c, 0x00000000, 0x00000000, 0x00068288, 0x00068288, 0x00000000 },
4182 { 0x00009a50, 0x00000000, 0x00000000, 0x00068220, 0x00068220, 0x00000000 },
4183 { 0x00009a54, 0x00000000, 0x00000000, 0x00068290, 0x00068290, 0x00000000 },
4184 { 0x00009a58, 0x00000000, 0x00000000, 0x00068300, 0x00068300, 0x00000000 },
4185 { 0x00009a5c, 0x00000000, 0x00000000, 0x00068304, 0x00068304, 0x00000000 },
4186 { 0x00009a60, 0x00000000, 0x00000000, 0x00068308, 0x00068308, 0x00000000 },
4187 { 0x00009a64, 0x00000000, 0x00000000, 0x0006830c, 0x0006830c, 0x00000000 },
4188 { 0x00009a68, 0x00000000, 0x00000000, 0x00068380, 0x00068380, 0x00000000 },
4189 { 0x00009a6c, 0x00000000, 0x00000000, 0x00068384, 0x00068384, 0x00000000 },
4190 { 0x00009a70, 0x00000000, 0x00000000, 0x00068700, 0x00068700, 0x00000000 },
4191 { 0x00009a74, 0x00000000, 0x00000000, 0x00068704, 0x00068704, 0x00000000 },
4192 { 0x00009a78, 0x00000000, 0x00000000, 0x00068708, 0x00068708, 0x00000000 },
4193 { 0x00009a7c, 0x00000000, 0x00000000, 0x0006870c, 0x0006870c, 0x00000000 },
4194 { 0x00009a80, 0x00000000, 0x00000000, 0x00068780, 0x00068780, 0x00000000 },
4195 { 0x00009a84, 0x00000000, 0x00000000, 0x00068784, 0x00068784, 0x00000000 },
4196 { 0x00009a88, 0x00000000, 0x00000000, 0x00068b04, 0x00068b04, 0x00000000 },
4197 { 0x00009a8c, 0x00000000, 0x00000000, 0x00068b08, 0x00068b08, 0x00000000 },
4198 { 0x00009a90, 0x00000000, 0x00000000, 0x00068b08, 0x00068b08, 0x00000000 },
4199 { 0x00009a94, 0x00000000, 0x00000000, 0x00068b0c, 0x00068b0c, 0x00000000 },
4200 { 0x00009a98, 0x00000000, 0x00000000, 0x00068b80, 0x00068b80, 0x00000000 },
4201 { 0x00009a9c, 0x00000000, 0x00000000, 0x00068b84, 0x00068b84, 0x00000000 },
4202 { 0x00009aa0, 0x00000000, 0x00000000, 0x00068b88, 0x00068b88, 0x00000000 },
4203 { 0x00009aa4, 0x00000000, 0x00000000, 0x00068b8c, 0x00068b8c, 0x00000000 },
4204 { 0x00009aa8, 0x00000000, 0x00000000, 0x000b8b90, 0x000b8b90, 0x00000000 },
4205 { 0x00009aac, 0x00000000, 0x00000000, 0x000b8f80, 0x000b8f80, 0x00000000 },
4206 { 0x00009ab0, 0x00000000, 0x00000000, 0x000b8f84, 0x000b8f84, 0x00000000 },
4207 { 0x00009ab4, 0x00000000, 0x00000000, 0x000b8f88, 0x000b8f88, 0x00000000 },
4208 { 0x00009ab8, 0x00000000, 0x00000000, 0x000b8f8c, 0x000b8f8c, 0x00000000 },
4209 { 0x00009abc, 0x00000000, 0x00000000, 0x000b8f90, 0x000b8f90, 0x00000000 },
4210 { 0x00009ac0, 0x00000000, 0x00000000, 0x000bb30c, 0x000bb30c, 0x00000000 },
4211 { 0x00009ac4, 0x00000000, 0x00000000, 0x000bb310, 0x000bb310, 0x00000000 },
4212 { 0x00009ac8, 0x00000000, 0x00000000, 0x000bb384, 0x000bb384, 0x00000000 },
4213 { 0x00009acc, 0x00000000, 0x00000000, 0x000bb388, 0x000bb388, 0x00000000 },
4214 { 0x00009ad0, 0x00000000, 0x00000000, 0x000bb324, 0x000bb324, 0x00000000 },
4215 { 0x00009ad4, 0x00000000, 0x00000000, 0x000bb704, 0x000bb704, 0x00000000 },
4216 { 0x00009ad8, 0x00000000, 0x00000000, 0x000f96a4, 0x000f96a4, 0x00000000 },
4217 { 0x00009adc, 0x00000000, 0x00000000, 0x000f96a8, 0x000f96a8, 0x00000000 },
4218 { 0x00009ae0, 0x00000000, 0x00000000, 0x000f9710, 0x000f9710, 0x00000000 },
4219 { 0x00009ae4, 0x00000000, 0x00000000, 0x000f9714, 0x000f9714, 0x00000000 },
4220 { 0x00009ae8, 0x00000000, 0x00000000, 0x000f9720, 0x000f9720, 0x00000000 },
4221 { 0x00009aec, 0x00000000, 0x00000000, 0x000f9724, 0x000f9724, 0x00000000 },
4222 { 0x00009af0, 0x00000000, 0x00000000, 0x000f9728, 0x000f9728, 0x00000000 },
4223 { 0x00009af4, 0x00000000, 0x00000000, 0x000f972c, 0x000f972c, 0x00000000 },
4224 { 0x00009af8, 0x00000000, 0x00000000, 0x000f97a0, 0x000f97a0, 0x00000000 },
4225 { 0x00009afc, 0x00000000, 0x00000000, 0x000f97a4, 0x000f97a4, 0x00000000 },
4226 { 0x00009b00, 0x00000000, 0x00000000, 0x000fb7a8, 0x000fb7a8, 0x00000000 },
4227 { 0x00009b04, 0x00000000, 0x00000000, 0x000fb7b0, 0x000fb7b0, 0x00000000 },
4228 { 0x00009b08, 0x00000000, 0x00000000, 0x000fb7b4, 0x000fb7b4, 0x00000000 },
4229 { 0x00009b0c, 0x00000000, 0x00000000, 0x000fb7b8, 0x000fb7b8, 0x00000000 },
4230 { 0x00009b10, 0x00000000, 0x00000000, 0x000fb7a5, 0x000fb7a5, 0x00000000 },
4231 { 0x00009b14, 0x00000000, 0x00000000, 0x000fb7a9, 0x000fb7a9, 0x00000000 },
4232 { 0x00009b18, 0x00000000, 0x00000000, 0x000fb7ad, 0x000fb7ad, 0x00000000 },
4233 { 0x00009b1c, 0x00000000, 0x00000000, 0x000fb7b1, 0x000fb7b1, 0x00000000 },
4234 { 0x00009b20, 0x00000000, 0x00000000, 0x000fb7b5, 0x000fb7b5, 0x00000000 },
4235 { 0x00009b24, 0x00000000, 0x00000000, 0x000fb7b9, 0x000fb7b9, 0x00000000 },
4236 { 0x00009b28, 0x00000000, 0x00000000, 0x000fb7c5, 0x000fb7c5, 0x00000000 },
4237 { 0x00009b2c, 0x00000000, 0x00000000, 0x000fb7c9, 0x000fb7c9, 0x00000000 },
4238 { 0x00009b30, 0x00000000, 0x00000000, 0x000fb7d1, 0x000fb7d1, 0x00000000 },
4239 { 0x00009b34, 0x00000000, 0x00000000, 0x000fb7d5, 0x000fb7d5, 0x00000000 },
4240 { 0x00009b38, 0x00000000, 0x00000000, 0x000fb7d9, 0x000fb7d9, 0x00000000 },
4241 { 0x00009b3c, 0x00000000, 0x00000000, 0x000fb7c6, 0x000fb7c6, 0x00000000 },
4242 { 0x00009b40, 0x00000000, 0x00000000, 0x000fb7ca, 0x000fb7ca, 0x00000000 },
4243 { 0x00009b44, 0x00000000, 0x00000000, 0x000fb7ce, 0x000fb7ce, 0x00000000 },
4244 { 0x00009b48, 0x00000000, 0x00000000, 0x000fb7d2, 0x000fb7d2, 0x00000000 },
4245 { 0x00009b4c, 0x00000000, 0x00000000, 0x000fb7d6, 0x000fb7d6, 0x00000000 },
4246 { 0x00009b50, 0x00000000, 0x00000000, 0x000fb7c3, 0x000fb7c3, 0x00000000 },
4247 { 0x00009b54, 0x00000000, 0x00000000, 0x000fb7c7, 0x000fb7c7, 0x00000000 },
4248 { 0x00009b58, 0x00000000, 0x00000000, 0x000fb7cb, 0x000fb7cb, 0x00000000 },
4249 { 0x00009b5c, 0x00000000, 0x00000000, 0x000fb7cf, 0x000fb7cf, 0x00000000 },
4250 { 0x00009b60, 0x00000000, 0x00000000, 0x000fb7d7, 0x000fb7d7, 0x00000000 },
4251 { 0x00009b64, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
4252 { 0x00009b68, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
4253 { 0x00009b6c, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
4254 { 0x00009b70, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
4255 { 0x00009b74, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
4256 { 0x00009b78, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
4257 { 0x00009b7c, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
4258 { 0x00009b80, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
4259 { 0x00009b84, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
4260 { 0x00009b88, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
4261 { 0x00009b8c, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
4262 { 0x00009b90, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
4263 { 0x00009b94, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
4264 { 0x00009b98, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
4265 { 0x00009b9c, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
4266 { 0x00009ba0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
4267 { 0x00009ba4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
4268 { 0x00009ba8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
4269 { 0x00009bac, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
4270 { 0x00009bb0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
4271 { 0x00009bb4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
4272 { 0x00009bb8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
4273 { 0x00009bbc, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
4274 { 0x00009bc0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
4275 { 0x00009bc4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
4276 { 0x00009bc8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
4277 { 0x00009bcc, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
4278 { 0x00009bd0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
4279 { 0x00009bd4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
4280 { 0x00009bd8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
4281 { 0x00009bdc, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
4282 { 0x00009be0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
4283 { 0x00009be4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
4284 { 0x00009be8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
4285 { 0x00009bec, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
4286 { 0x00009bf0, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
4287 { 0x00009bf4, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
4288 { 0x00009bf8, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
4289 { 0x00009bfc, 0x00000000, 0x00000000, 0x000fb7db, 0x000fb7db, 0x00000000 },
4290 { 0x0000aa00, 0x00000000, 0x00000000, 0x0006801c, 0x0006801c, 0x00000000 },
4291 { 0x0000aa04, 0x00000000, 0x00000000, 0x0006801c, 0x0006801c, 0x00000000 },
4292 { 0x0000aa08, 0x00000000, 0x00000000, 0x0006801c, 0x0006801c, 0x00000000 },
4293 { 0x0000aa0c, 0x00000000, 0x00000000, 0x00068080, 0x00068080, 0x00000000 },
4294 { 0x0000aa10, 0x00000000, 0x00000000, 0x00068084, 0x00068084, 0x00000000 },
4295 { 0x0000aa14, 0x00000000, 0x00000000, 0x00068088, 0x00068088, 0x00000000 },
4296 { 0x0000aa18, 0x00000000, 0x00000000, 0x0006808c, 0x0006808c, 0x00000000 },
4297 { 0x0000aa1c, 0x00000000, 0x00000000, 0x00068100, 0x00068100, 0x00000000 },
4298 { 0x0000aa20, 0x00000000, 0x00000000, 0x00068104, 0x00068104, 0x00000000 },
4299 { 0x0000aa24, 0x00000000, 0x00000000, 0x00068108, 0x00068108, 0x00000000 },
4300 { 0x0000aa28, 0x00000000, 0x00000000, 0x0006810c, 0x0006810c, 0x00000000 },
4301 { 0x0000aa2c, 0x00000000, 0x00000000, 0x00068110, 0x00068110, 0x00000000 },
4302 { 0x0000aa30, 0x00000000, 0x00000000, 0x00068110, 0x00068110, 0x00000000 },
4303 { 0x0000aa34, 0x00000000, 0x00000000, 0x00068180, 0x00068180, 0x00000000 },
4304 { 0x0000aa38, 0x00000000, 0x00000000, 0x00068184, 0x00068184, 0x00000000 },
4305 { 0x0000aa3c, 0x00000000, 0x00000000, 0x00068188, 0x00068188, 0x00000000 },
4306 { 0x0000aa40, 0x00000000, 0x00000000, 0x0006818c, 0x0006818c, 0x00000000 },
4307 { 0x0000aa44, 0x00000000, 0x00000000, 0x00068190, 0x00068190, 0x00000000 },
4308 { 0x0000aa48, 0x00000000, 0x00000000, 0x00068194, 0x00068194, 0x00000000 },
4309 { 0x0000aa4c, 0x00000000, 0x00000000, 0x000681a0, 0x000681a0, 0x00000000 },
4310 { 0x0000aa50, 0x00000000, 0x00000000, 0x0006820c, 0x0006820c, 0x00000000 },
4311 { 0x0000aa54, 0x00000000, 0x00000000, 0x000681a8, 0x000681a8, 0x00000000 },
4312 { 0x0000aa58, 0x00000000, 0x00000000, 0x000681ac, 0x000681ac, 0x00000000 },
4313 { 0x0000aa5c, 0x00000000, 0x00000000, 0x0006821c, 0x0006821c, 0x00000000 },
4314 { 0x0000aa60, 0x00000000, 0x00000000, 0x00068224, 0x00068224, 0x00000000 },
4315 { 0x0000aa64, 0x00000000, 0x00000000, 0x00068290, 0x00068290, 0x00000000 },
4316 { 0x0000aa68, 0x00000000, 0x00000000, 0x00068300, 0x00068300, 0x00000000 },
4317 { 0x0000aa6c, 0x00000000, 0x00000000, 0x00068308, 0x00068308, 0x00000000 },
4318 { 0x0000aa70, 0x00000000, 0x00000000, 0x0006830c, 0x0006830c, 0x00000000 },
4319 { 0x0000aa74, 0x00000000, 0x00000000, 0x00068310, 0x00068310, 0x00000000 },
4320 { 0x0000aa78, 0x00000000, 0x00000000, 0x00068788, 0x00068788, 0x00000000 },
4321 { 0x0000aa7c, 0x00000000, 0x00000000, 0x0006878c, 0x0006878c, 0x00000000 },
4322 { 0x0000aa80, 0x00000000, 0x00000000, 0x00068790, 0x00068790, 0x00000000 },
4323 { 0x0000aa84, 0x00000000, 0x00000000, 0x00068794, 0x00068794, 0x00000000 },
4324 { 0x0000aa88, 0x00000000, 0x00000000, 0x00068798, 0x00068798, 0x00000000 },
4325 { 0x0000aa8c, 0x00000000, 0x00000000, 0x0006879c, 0x0006879c, 0x00000000 },
4326 { 0x0000aa90, 0x00000000, 0x00000000, 0x00068b89, 0x00068b89, 0x00000000 },
4327 { 0x0000aa94, 0x00000000, 0x00000000, 0x00068b8d, 0x00068b8d, 0x00000000 },
4328 { 0x0000aa98, 0x00000000, 0x00000000, 0x00068b91, 0x00068b91, 0x00000000 },
4329 { 0x0000aa9c, 0x00000000, 0x00000000, 0x00068b95, 0x00068b95, 0x00000000 },
4330 { 0x0000aaa0, 0x00000000, 0x00000000, 0x00068b99, 0x00068b99, 0x00000000 },
4331 { 0x0000aaa4, 0x00000000, 0x00000000, 0x00068ba5, 0x00068ba5, 0x00000000 },
4332 { 0x0000aaa8, 0x00000000, 0x00000000, 0x00068ba9, 0x00068ba9, 0x00000000 },
4333 { 0x0000aaac, 0x00000000, 0x00000000, 0x00068bad, 0x00068bad, 0x00000000 },
4334 { 0x0000aab0, 0x00000000, 0x00000000, 0x000b8b0c, 0x000b8b0c, 0x00000000 },
4335 { 0x0000aab4, 0x00000000, 0x00000000, 0x000b8f10, 0x000b8f10, 0x00000000 },
4336 { 0x0000aab8, 0x00000000, 0x00000000, 0x000b8f14, 0x000b8f14, 0x00000000 },
4337 { 0x0000aabc, 0x00000000, 0x00000000, 0x000b8f84, 0x000b8f84, 0x00000000 },
4338 { 0x0000aac0, 0x00000000, 0x00000000, 0x000b8f84, 0x000b8f84, 0x00000000 },
4339 { 0x0000aac4, 0x00000000, 0x00000000, 0x000b8f88, 0x000b8f88, 0x00000000 },
4340 { 0x0000aac8, 0x00000000, 0x00000000, 0x000bb380, 0x000bb380, 0x00000000 },
4341 { 0x0000aacc, 0x00000000, 0x00000000, 0x000bb384, 0x000bb384, 0x00000000 },
4342 { 0x0000aad0, 0x00000000, 0x00000000, 0x000bb388, 0x000bb388, 0x00000000 },
4343 { 0x0000aad4, 0x00000000, 0x00000000, 0x000bb38c, 0x000bb38c, 0x00000000 },
4344 { 0x0000aad8, 0x00000000, 0x00000000, 0x000bb394, 0x000bb394, 0x00000000 },
4345 { 0x0000aadc, 0x00000000, 0x00000000, 0x000bb798, 0x000bb798, 0x00000000 },
4346 { 0x0000aae0, 0x00000000, 0x00000000, 0x000f970c, 0x000f970c, 0x00000000 },
4347 { 0x0000aae4, 0x00000000, 0x00000000, 0x000f9710, 0x000f9710, 0x00000000 },
4348 { 0x0000aae8, 0x00000000, 0x00000000, 0x000f9714, 0x000f9714, 0x00000000 },
4349 { 0x0000aaec, 0x00000000, 0x00000000, 0x000f9718, 0x000f9718, 0x00000000 },
4350 { 0x0000aaf0, 0x00000000, 0x00000000, 0x000f9705, 0x000f9705, 0x00000000 },
4351 { 0x0000aaf4, 0x00000000, 0x00000000, 0x000f9709, 0x000f9709, 0x00000000 },
4352 { 0x0000aaf8, 0x00000000, 0x00000000, 0x000f970d, 0x000f970d, 0x00000000 },
4353 { 0x0000aafc, 0x00000000, 0x00000000, 0x000f9711, 0x000f9711, 0x00000000 },
4354 { 0x0000ab00, 0x00000000, 0x00000000, 0x000f9715, 0x000f9715, 0x00000000 },
4355 { 0x0000ab04, 0x00000000, 0x00000000, 0x000f9719, 0x000f9719, 0x00000000 },
4356 { 0x0000ab08, 0x00000000, 0x00000000, 0x000fb7a4, 0x000fb7a4, 0x00000000 },
4357 { 0x0000ab0c, 0x00000000, 0x00000000, 0x000fb7a8, 0x000fb7a8, 0x00000000 },
4358 { 0x0000ab10, 0x00000000, 0x00000000, 0x000fb7ac, 0x000fb7ac, 0x00000000 },
4359 { 0x0000ab14, 0x00000000, 0x00000000, 0x000fb7ac, 0x000fb7ac, 0x00000000 },
4360 { 0x0000ab18, 0x00000000, 0x00000000, 0x000fb7b0, 0x000fb7b0, 0x00000000 },
4361 { 0x0000ab1c, 0x00000000, 0x00000000, 0x000fb7b8, 0x000fb7b8, 0x00000000 },
4362 { 0x0000ab20, 0x00000000, 0x00000000, 0x000fb7bc, 0x000fb7bc, 0x00000000 },
4363 { 0x0000ab24, 0x00000000, 0x00000000, 0x000fb7a1, 0x000fb7a1, 0x00000000 },
4364 { 0x0000ab28, 0x00000000, 0x00000000, 0x000fb7a5, 0x000fb7a5, 0x00000000 },
4365 { 0x0000ab2c, 0x00000000, 0x00000000, 0x000fb7a9, 0x000fb7a9, 0x00000000 },
4366 { 0x0000ab30, 0x00000000, 0x00000000, 0x000fb7b1, 0x000fb7b1, 0x00000000 },
4367 { 0x0000ab34, 0x00000000, 0x00000000, 0x000fb7b5, 0x000fb7b5, 0x00000000 },
4368 { 0x0000ab38, 0x00000000, 0x00000000, 0x000fb7bd, 0x000fb7bd, 0x00000000 },
4369 { 0x0000ab3c, 0x00000000, 0x00000000, 0x000fb7c9, 0x000fb7c9, 0x00000000 },
4370 { 0x0000ab40, 0x00000000, 0x00000000, 0x000fb7cd, 0x000fb7cd, 0x00000000 },
4371 { 0x0000ab44, 0x00000000, 0x00000000, 0x000fb7d1, 0x000fb7d1, 0x00000000 },
4372 { 0x0000ab48, 0x00000000, 0x00000000, 0x000fb7d9, 0x000fb7d9, 0x00000000 },
4373 { 0x0000ab4c, 0x00000000, 0x00000000, 0x000fb7c2, 0x000fb7c2, 0x00000000 },
4374 { 0x0000ab50, 0x00000000, 0x00000000, 0x000fb7c6, 0x000fb7c6, 0x00000000 },
4375 { 0x0000ab54, 0x00000000, 0x00000000, 0x000fb7ca, 0x000fb7ca, 0x00000000 },
4376 { 0x0000ab58, 0x00000000, 0x00000000, 0x000fb7ce, 0x000fb7ce, 0x00000000 },
4377 { 0x0000ab5c, 0x00000000, 0x00000000, 0x000fb7d2, 0x000fb7d2, 0x00000000 },
4378 { 0x0000ab60, 0x00000000, 0x00000000, 0x000fb7d6, 0x000fb7d6, 0x00000000 },
4379 { 0x0000ab64, 0x00000000, 0x00000000, 0x000fb7c3, 0x000fb7c3, 0x00000000 },
4380 { 0x0000ab68, 0x00000000, 0x00000000, 0x000fb7cb, 0x000fb7cb, 0x00000000 },
4381 { 0x0000ab6c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
4382 { 0x0000ab70, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
4383 { 0x0000ab74, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
4384 { 0x0000ab78, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
4385 { 0x0000ab7c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
4386 { 0x0000ab80, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
4387 { 0x0000ab84, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
4388 { 0x0000ab88, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
4389 { 0x0000ab8c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
4390 { 0x0000ab90, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
4391 { 0x0000ab94, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
4392 { 0x0000ab98, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
4393 { 0x0000ab9c, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
4394 { 0x0000aba0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
4395 { 0x0000aba4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
4396 { 0x0000aba8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
4397 { 0x0000abac, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
4398 { 0x0000abb0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
4399 { 0x0000abb4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
4400 { 0x0000abb8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
4401 { 0x0000abbc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
4402 { 0x0000abc0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
4403 { 0x0000abc4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
4404 { 0x0000abc8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
4405 { 0x0000abcc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
4406 { 0x0000abd0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
4407 { 0x0000abd4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
4408 { 0x0000abd8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
4409 { 0x0000abdc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
4410 { 0x0000abe0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
4411 { 0x0000abe4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
4412 { 0x0000abe8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
4413 { 0x0000abec, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
4414 { 0x0000abf0, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
4415 { 0x0000abf4, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
4416 { 0x0000abf8, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
4417 { 0x0000abfc, 0x00000000, 0x00000000, 0x000fb7d3, 0x000fb7d3, 0x00000000 },
4418 { 0x0000a204, 0x00000004, 0x00000004, 0x00000004, 0x00000004, 0x00000004 },
4419 { 0x0000a20c, 0x00000014, 0x00000014, 0x00000000, 0x00000000, 0x0001f000 },
4420 { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
4421 { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
4422 { 0x0000a250, 0x0004f000, 0x0004f000, 0x0004a000, 0x0004a000, 0x0004a000 },
4423 { 0x0000a274, 0x0a81c652, 0x0a81c652, 0x0a820652, 0x0a820652, 0x0a82a652 },
4424 { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
4425 { 0x0000a304, 0x00000000, 0x00000000, 0x00007201, 0x00007201, 0x00000000 },
4426 { 0x0000a308, 0x00000000, 0x00000000, 0x00010408, 0x00010408, 0x00000000 },
4427 { 0x0000a30c, 0x00000000, 0x00000000, 0x0001860a, 0x0001860a, 0x00000000 },
4428 { 0x0000a310, 0x00000000, 0x00000000, 0x00020818, 0x00020818, 0x00000000 },
4429 { 0x0000a314, 0x00000000, 0x00000000, 0x00024858, 0x00024858, 0x00000000 },
4430 { 0x0000a318, 0x00000000, 0x00000000, 0x00026859, 0x00026859, 0x00000000 },
4431 { 0x0000a31c, 0x00000000, 0x00000000, 0x0002985b, 0x0002985b, 0x00000000 },
4432 { 0x0000a320, 0x00000000, 0x00000000, 0x0002b89a, 0x0002b89a, 0x00000000 },
4433 { 0x0000a324, 0x00000000, 0x00000000, 0x0002d89b, 0x0002d89b, 0x00000000 },
4434 { 0x0000a328, 0x00000000, 0x00000000, 0x0002f89c, 0x0002f89c, 0x00000000 },
4435 { 0x0000a32c, 0x00000000, 0x00000000, 0x0003189d, 0x0003189d, 0x00000000 },
4436 { 0x0000a330, 0x00000000, 0x00000000, 0x0003389e, 0x0003389e, 0x00000000 },
4437 { 0x0000a334, 0x00000000, 0x00000000, 0x000368de, 0x000368de, 0x00000000 },
4438 { 0x0000a338, 0x00000000, 0x00000000, 0x0003891e, 0x0003891e, 0x00000000 },
4439 { 0x0000a33c, 0x00000000, 0x00000000, 0x0003a95e, 0x0003a95e, 0x00000000 },
4440 { 0x0000a340, 0x00000000, 0x00000000, 0x0003e9df, 0x0003e9df, 0x00000000 },
4441 { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 },
4442 { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
4443};
4444
4445static const u_int32_t ar9285Common_9285_1_2[][2] = {
4446 { 0x0000000c, 0x00000000 },
4447 { 0x00000030, 0x00020045 },
4448 { 0x00000034, 0x00000005 },
4449 { 0x00000040, 0x00000000 },
4450 { 0x00000044, 0x00000008 },
4451 { 0x00000048, 0x00000008 },
4452 { 0x0000004c, 0x00000010 },
4453 { 0x00000050, 0x00000000 },
4454 { 0x00000054, 0x0000001f },
4455 { 0x00000800, 0x00000000 },
4456 { 0x00000804, 0x00000000 },
4457 { 0x00000808, 0x00000000 },
4458 { 0x0000080c, 0x00000000 },
4459 { 0x00000810, 0x00000000 },
4460 { 0x00000814, 0x00000000 },
4461 { 0x00000818, 0x00000000 },
4462 { 0x0000081c, 0x00000000 },
4463 { 0x00000820, 0x00000000 },
4464 { 0x00000824, 0x00000000 },
4465 { 0x00001040, 0x002ffc0f },
4466 { 0x00001044, 0x002ffc0f },
4467 { 0x00001048, 0x002ffc0f },
4468 { 0x0000104c, 0x002ffc0f },
4469 { 0x00001050, 0x002ffc0f },
4470 { 0x00001054, 0x002ffc0f },
4471 { 0x00001058, 0x002ffc0f },
4472 { 0x0000105c, 0x002ffc0f },
4473 { 0x00001060, 0x002ffc0f },
4474 { 0x00001064, 0x002ffc0f },
4475 { 0x00001230, 0x00000000 },
4476 { 0x00001270, 0x00000000 },
4477 { 0x00001038, 0x00000000 },
4478 { 0x00001078, 0x00000000 },
4479 { 0x000010b8, 0x00000000 },
4480 { 0x000010f8, 0x00000000 },
4481 { 0x00001138, 0x00000000 },
4482 { 0x00001178, 0x00000000 },
4483 { 0x000011b8, 0x00000000 },
4484 { 0x000011f8, 0x00000000 },
4485 { 0x00001238, 0x00000000 },
4486 { 0x00001278, 0x00000000 },
4487 { 0x000012b8, 0x00000000 },
4488 { 0x000012f8, 0x00000000 },
4489 { 0x00001338, 0x00000000 },
4490 { 0x00001378, 0x00000000 },
4491 { 0x000013b8, 0x00000000 },
4492 { 0x000013f8, 0x00000000 },
4493 { 0x00001438, 0x00000000 },
4494 { 0x00001478, 0x00000000 },
4495 { 0x000014b8, 0x00000000 },
4496 { 0x000014f8, 0x00000000 },
4497 { 0x00001538, 0x00000000 },
4498 { 0x00001578, 0x00000000 },
4499 { 0x000015b8, 0x00000000 },
4500 { 0x000015f8, 0x00000000 },
4501 { 0x00001638, 0x00000000 },
4502 { 0x00001678, 0x00000000 },
4503 { 0x000016b8, 0x00000000 },
4504 { 0x000016f8, 0x00000000 },
4505 { 0x00001738, 0x00000000 },
4506 { 0x00001778, 0x00000000 },
4507 { 0x000017b8, 0x00000000 },
4508 { 0x000017f8, 0x00000000 },
4509 { 0x0000103c, 0x00000000 },
4510 { 0x0000107c, 0x00000000 },
4511 { 0x000010bc, 0x00000000 },
4512 { 0x000010fc, 0x00000000 },
4513 { 0x0000113c, 0x00000000 },
4514 { 0x0000117c, 0x00000000 },
4515 { 0x000011bc, 0x00000000 },
4516 { 0x000011fc, 0x00000000 },
4517 { 0x0000123c, 0x00000000 },
4518 { 0x0000127c, 0x00000000 },
4519 { 0x000012bc, 0x00000000 },
4520 { 0x000012fc, 0x00000000 },
4521 { 0x0000133c, 0x00000000 },
4522 { 0x0000137c, 0x00000000 },
4523 { 0x000013bc, 0x00000000 },
4524 { 0x000013fc, 0x00000000 },
4525 { 0x0000143c, 0x00000000 },
4526 { 0x0000147c, 0x00000000 },
4527 { 0x00004030, 0x00000002 },
4528 { 0x0000403c, 0x00000002 },
4529 { 0x00004024, 0x0000001f },
4530 { 0x00004060, 0x00000000 },
4531 { 0x00004064, 0x00000000 },
4532 { 0x00007010, 0x00000031 },
4533 { 0x00007034, 0x00000002 },
4534 { 0x00007038, 0x000004c2 },
4535 { 0x00008004, 0x00000000 },
4536 { 0x00008008, 0x00000000 },
4537 { 0x0000800c, 0x00000000 },
4538 { 0x00008018, 0x00000700 },
4539 { 0x00008020, 0x00000000 },
4540 { 0x00008038, 0x00000000 },
4541 { 0x0000803c, 0x00000000 },
4542 { 0x00008048, 0x00000000 },
4543 { 0x00008054, 0x00000000 },
4544 { 0x00008058, 0x00000000 },
4545 { 0x0000805c, 0x000fc78f },
4546 { 0x00008060, 0x0000000f },
4547 { 0x00008064, 0x00000000 },
4548 { 0x00008070, 0x00000000 },
4549 { 0x000080c0, 0x2a80001a },
4550 { 0x000080c4, 0x05dc01e0 },
4551 { 0x000080c8, 0x1f402710 },
4552 { 0x000080cc, 0x01f40000 },
4553 { 0x000080d0, 0x00001e00 },
4554 { 0x000080d4, 0x00000000 },
4555 { 0x000080d8, 0x00400000 },
4556 { 0x000080e0, 0xffffffff },
4557 { 0x000080e4, 0x0000ffff },
4558 { 0x000080e8, 0x003f3f3f },
4559 { 0x000080ec, 0x00000000 },
4560 { 0x000080f0, 0x00000000 },
4561 { 0x000080f4, 0x00000000 },
4562 { 0x000080f8, 0x00000000 },
4563 { 0x000080fc, 0x00020000 },
4564 { 0x00008100, 0x00020000 },
4565 { 0x00008104, 0x00000001 },
4566 { 0x00008108, 0x00000052 },
4567 { 0x0000810c, 0x00000000 },
4568 { 0x00008110, 0x00000168 },
4569 { 0x00008118, 0x000100aa },
4570 { 0x0000811c, 0x00003210 },
4571 { 0x00008120, 0x08f04800 },
4572 { 0x00008124, 0x00000000 },
4573 { 0x00008128, 0x00000000 },
4574 { 0x0000812c, 0x00000000 },
4575 { 0x00008130, 0x00000000 },
4576 { 0x00008134, 0x00000000 },
4577 { 0x00008138, 0x00000000 },
4578 { 0x0000813c, 0x00000000 },
4579 { 0x00008144, 0xffffffff },
4580 { 0x00008168, 0x00000000 },
4581 { 0x0000816c, 0x00000000 },
4582 { 0x00008170, 0x32143320 },
4583 { 0x00008174, 0xfaa4fa50 },
4584 { 0x00008178, 0x00000100 },
4585 { 0x0000817c, 0x00000000 },
4586 { 0x000081c0, 0x00000000 },
4587 { 0x000081d0, 0x00003210 },
4588 { 0x000081ec, 0x00000000 },
4589 { 0x000081f0, 0x00000000 },
4590 { 0x000081f4, 0x00000000 },
4591 { 0x000081f8, 0x00000000 },
4592 { 0x000081fc, 0x00000000 },
4593 { 0x00008200, 0x00000000 },
4594 { 0x00008204, 0x00000000 },
4595 { 0x00008208, 0x00000000 },
4596 { 0x0000820c, 0x00000000 },
4597 { 0x00008210, 0x00000000 },
4598 { 0x00008214, 0x00000000 },
4599 { 0x00008218, 0x00000000 },
4600 { 0x0000821c, 0x00000000 },
4601 { 0x00008220, 0x00000000 },
4602 { 0x00008224, 0x00000000 },
4603 { 0x00008228, 0x00000000 },
4604 { 0x0000822c, 0x00000000 },
4605 { 0x00008230, 0x00000000 },
4606 { 0x00008234, 0x00000000 },
4607 { 0x00008238, 0x00000000 },
4608 { 0x0000823c, 0x00000000 },
4609 { 0x00008240, 0x00100000 },
4610 { 0x00008244, 0x0010f400 },
4611 { 0x00008248, 0x00000100 },
4612 { 0x0000824c, 0x0001e800 },
4613 { 0x00008250, 0x00000000 },
4614 { 0x00008254, 0x00000000 },
4615 { 0x00008258, 0x00000000 },
4616 { 0x0000825c, 0x400000ff },
4617 { 0x00008260, 0x00080922 },
4618 { 0x00008264, 0xa8a00010 },
4619 { 0x00008270, 0x00000000 },
4620 { 0x00008274, 0x40000000 },
4621 { 0x00008278, 0x003e4180 },
4622 { 0x0000827c, 0x00000000 },
4623 { 0x00008284, 0x0000002c },
4624 { 0x00008288, 0x0000002c },
4625 { 0x0000828c, 0x00000000 },
4626 { 0x00008294, 0x00000000 },
4627 { 0x00008298, 0x00000000 },
4628 { 0x0000829c, 0x00000000 },
4629 { 0x00008300, 0x00000040 },
4630 { 0x00008314, 0x00000000 },
4631 { 0x00008328, 0x00000000 },
4632 { 0x0000832c, 0x00000001 },
4633 { 0x00008330, 0x00000302 },
4634 { 0x00008334, 0x00000e00 },
4635 { 0x00008338, 0x00ff0000 },
4636 { 0x0000833c, 0x00000000 },
4637 { 0x00008340, 0x00010380 },
4638 { 0x00008344, 0x00581043 },
4639 { 0x00009808, 0x00000000 },
4640 { 0x0000980c, 0xafe68e30 },
4641 { 0x00009810, 0xfd14e000 },
4642 { 0x00009814, 0x9c0a9f6b },
4643 { 0x0000981c, 0x00000000 },
4644 { 0x0000982c, 0x0000a000 },
4645 { 0x00009830, 0x00000000 },
4646 { 0x0000983c, 0x00200400 },
4647 { 0x0000984c, 0x0040233c },
4648 { 0x00009854, 0x00000044 },
4649 { 0x00009900, 0x00000000 },
4650 { 0x00009904, 0x00000000 },
4651 { 0x00009908, 0x00000000 },
4652 { 0x0000990c, 0x00000000 },
4653 { 0x00009910, 0x01002310 },
4654 { 0x0000991c, 0x10000fff },
4655 { 0x00009920, 0x04900000 },
4656 { 0x00009928, 0x00000001 },
4657 { 0x0000992c, 0x00000004 },
4658 { 0x00009934, 0x1e1f2022 },
4659 { 0x00009938, 0x0a0b0c0d },
4660 { 0x0000993c, 0x00000000 },
4661 { 0x00009940, 0x14750604 },
4662 { 0x00009948, 0x9280c00a },
4663 { 0x0000994c, 0x00020028 },
4664 { 0x00009954, 0x5f3ca3de },
4665 { 0x00009958, 0x2108ecff },
4666 { 0x00009968, 0x000003ce },
4667 { 0x00009970, 0x192bb515 },
4668 { 0x00009974, 0x00000000 },
4669 { 0x00009978, 0x00000001 },
4670 { 0x0000997c, 0x00000000 },
4671 { 0x00009980, 0x00000000 },
4672 { 0x00009984, 0x00000000 },
4673 { 0x00009988, 0x00000000 },
4674 { 0x0000998c, 0x00000000 },
4675 { 0x00009990, 0x00000000 },
4676 { 0x00009994, 0x00000000 },
4677 { 0x00009998, 0x00000000 },
4678 { 0x0000999c, 0x00000000 },
4679 { 0x000099a0, 0x00000000 },
4680 { 0x000099a4, 0x00000001 },
4681 { 0x000099a8, 0x201fff00 },
4682 { 0x000099ac, 0x2def1000 },
4683 { 0x000099b0, 0x03051000 },
4684 { 0x000099b4, 0x00000820 },
4685 { 0x000099dc, 0x00000000 },
4686 { 0x000099e0, 0x00000000 },
4687 { 0x000099e4, 0xaaaaaaaa },
4688 { 0x000099e8, 0x3c466478 },
4689 { 0x000099ec, 0x0cc80caa },
4690 { 0x000099f0, 0x00000000 },
4691 { 0x0000a208, 0x803e6788 },
4692 { 0x0000a210, 0x4080a333 },
4693 { 0x0000a214, 0x00206c10 },
4694 { 0x0000a218, 0x009c4060 },
4695 { 0x0000a220, 0x01834061 },
4696 { 0x0000a224, 0x00000400 },
4697 { 0x0000a228, 0x000003b5 },
4698 { 0x0000a22c, 0x00000000 },
4699 { 0x0000a234, 0x20202020 },
4700 { 0x0000a238, 0x20202020 },
4701 { 0x0000a244, 0x00000000 },
4702 { 0x0000a248, 0xfffffffc },
4703 { 0x0000a24c, 0x00000000 },
4704 { 0x0000a254, 0x00000000 },
4705 { 0x0000a258, 0x0ccb5380 },
4706 { 0x0000a25c, 0x15151501 },
4707 { 0x0000a260, 0xdfa90f01 },
4708 { 0x0000a268, 0x00000000 },
4709 { 0x0000a26c, 0x0ebae9e6 },
4710 { 0x0000d270, 0x0d820820 },
4711 { 0x0000a278, 0x318c6318 },
4712 { 0x0000a27c, 0x050c0318 },
4713 { 0x0000d35c, 0x07ffffef },
4714 { 0x0000d360, 0x0fffffe7 },
4715 { 0x0000d364, 0x17ffffe5 },
4716 { 0x0000d368, 0x1fffffe4 },
4717 { 0x0000d36c, 0x37ffffe3 },
4718 { 0x0000d370, 0x3fffffe3 },
4719 { 0x0000d374, 0x57ffffe3 },
4720 { 0x0000d378, 0x5fffffe2 },
4721 { 0x0000d37c, 0x7fffffe2 },
4722 { 0x0000d380, 0x7f3c7bba },
4723 { 0x0000d384, 0xf3307ff0 },
4724 { 0x0000a388, 0x0c000000 },
4725 { 0x0000a38c, 0x20202020 },
4726 { 0x0000a390, 0x20202020 },
4727 { 0x0000a394, 0x318c6318 },
4728 { 0x0000a398, 0x00000318 },
4729 { 0x0000a39c, 0x00000001 },
4730 { 0x0000a3a0, 0x00000000 },
4731 { 0x0000a3a4, 0x00000000 },
4732 { 0x0000a3a8, 0x00000000 },
4733 { 0x0000a3ac, 0x00000000 },
4734 { 0x0000a3b0, 0x00000000 },
4735 { 0x0000a3b4, 0x00000000 },
4736 { 0x0000a3b8, 0x00000000 },
4737 { 0x0000a3bc, 0x00000000 },
4738 { 0x0000a3c0, 0x00000000 },
4739 { 0x0000a3c4, 0x00000000 },
4740 { 0x0000a3cc, 0x20202020 },
4741 { 0x0000a3d0, 0x20202020 },
4742 { 0x0000a3d4, 0x20202020 },
4743 { 0x0000a3dc, 0x318c6318 },
4744 { 0x0000a3e0, 0x00000318 },
4745 { 0x0000a3e4, 0x00000000 },
4746 { 0x0000a3e8, 0x18c43433 },
4747 { 0x0000a3ec, 0x00f70081 },
4748 { 0x00007800, 0x00140000 },
4749 { 0x00007804, 0x0e4548d8 },
4750 { 0x00007808, 0x54214514 },
4751 { 0x0000780c, 0x02025820 },
4752 { 0x00007810, 0x71c0d388 },
4753 { 0x00007814, 0x924934a8 },
4754 { 0x0000781c, 0x00000000 },
4755 { 0x00007820, 0x00000c04 },
4756 { 0x00007824, 0x00d86fff },
4757 { 0x00007828, 0x26d2491b },
4758 { 0x0000782c, 0x6e36d97b },
4759 { 0x00007830, 0xedb6d96e },
4760 { 0x00007834, 0x71400087 },
4761 { 0x00007838, 0xfac68801 },
4762 { 0x0000783c, 0x0001fffe },
4763 { 0x00007840, 0xffeb1a20 },
4764 { 0x00007844, 0x000c0db6 },
4765 { 0x00007848, 0x6db61b6f },
4766 { 0x0000784c, 0x6d9b66db },
4767 { 0x00007850, 0x6d8c6dba },
4768 { 0x00007854, 0x00040000 },
4769 { 0x00007858, 0xdb003012 },
4770 { 0x0000785c, 0x04924914 },
4771 { 0x00007860, 0x21084210 },
4772 { 0x00007864, 0xf7d7ffde },
4773 { 0x00007868, 0xc2034080 },
4774 { 0x0000786c, 0x48609eb4 },
4775 { 0x00007870, 0x10142c00 },
4776};
4777
4778static const u_int32_t ar9285PciePhy_clkreq_always_on_L1_9285_1_2[][2] = {
4779 {0x00004040, 0x9248fd00 },
4780 {0x00004040, 0x24924924 },
4781 {0x00004040, 0xa8000019 },
4782 {0x00004040, 0x13160820 },
4783 {0x00004040, 0xe5980560 },
4784 {0x00004040, 0xc01dcffd },
4785 {0x00004040, 0x1aaabe41 },
4786 {0x00004040, 0xbe105554 },
4787 {0x00004040, 0x00043007 },
4788 {0x00004044, 0x00000000 },
4789};
4790
4791static const u_int32_t ar9285PciePhy_clkreq_off_L1_9285_1_2[][2] = {
4792 {0x00004040, 0x9248fd00 },
4793 {0x00004040, 0x24924924 },
4794 {0x00004040, 0xa8000019 },
4795 {0x00004040, 0x13160820 },
4796 {0x00004040, 0xe5980560 },
4797 {0x00004040, 0xc01dcffc },
4798 {0x00004040, 0x1aaabe41 },
4799 {0x00004040, 0xbe105554 },
4800 {0x00004040, 0x00043007 },
4801 {0x00004044, 0x00000000 },
4802};
diff --git a/drivers/net/wireless/ath9k/mac.c b/drivers/net/wireless/ath9k/mac.c
index a4e98986dbcd..af32d091dc38 100644
--- a/drivers/net/wireless/ath9k/mac.c
+++ b/drivers/net/wireless/ath9k/mac.c
@@ -916,12 +916,11 @@ void ath9k_hw_rxena(struct ath_hal *ah)
916 916
917void ath9k_hw_startpcureceive(struct ath_hal *ah) 917void ath9k_hw_startpcureceive(struct ath_hal *ah)
918{ 918{
919 REG_CLR_BIT(ah, AR_DIAG_SW,
920 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
921
922 ath9k_enable_mib_counters(ah); 919 ath9k_enable_mib_counters(ah);
923 920
924 ath9k_ani_reset(ah); 921 ath9k_ani_reset(ah);
922
923 REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
925} 924}
926 925
927void ath9k_hw_stoppcurecv(struct ath_hal *ah) 926void ath9k_hw_stoppcurecv(struct ath_hal *ah)
diff --git a/drivers/net/wireless/ath9k/main.c b/drivers/net/wireless/ath9k/main.c
index 26c47577e183..02e1771bb274 100644
--- a/drivers/net/wireless/ath9k/main.c
+++ b/drivers/net/wireless/ath9k/main.c
@@ -34,6 +34,7 @@ static struct pci_device_id ath_pci_id_table[] __devinitdata = {
34 { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */ 34 { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
35 { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */ 35 { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
36 { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */ 36 { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
37 { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
37 { 0 } 38 { 0 }
38}; 39};
39 40
@@ -60,7 +61,8 @@ static void bus_read_cachesize(struct ath_softc *sc, int *csz)
60 61
61static void ath_setcurmode(struct ath_softc *sc, enum wireless_mode mode) 62static void ath_setcurmode(struct ath_softc *sc, enum wireless_mode mode)
62{ 63{
63 sc->sc_curmode = mode; 64 if (!sc->sc_curaid)
65 sc->cur_rate_table = sc->hw_rate_table[mode];
64 /* 66 /*
65 * All protection frames are transmited at 2Mb/s for 67 * All protection frames are transmited at 2Mb/s for
66 * 11g, otherwise at 1Mb/s. 68 * 11g, otherwise at 1Mb/s.
@@ -346,7 +348,7 @@ static void ath_ani_calibrate(unsigned long data)
346 * don't calibrate when we're scanning. 348 * don't calibrate when we're scanning.
347 * we are most likely not on our home channel. 349 * we are most likely not on our home channel.
348 */ 350 */
349 if (sc->rx_filter & FIF_BCN_PRBRESP_PROMISC) 351 if (sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)
350 return; 352 return;
351 353
352 /* Long calibration runs independently of short calibration. */ 354 /* Long calibration runs independently of short calibration. */
@@ -485,9 +487,9 @@ static void ath9k_tasklet(unsigned long data)
485 487
486 if (status & 488 if (status &
487 (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) { 489 (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
488 spin_lock_bh(&sc->sc_rxflushlock); 490 spin_lock_bh(&sc->rx.rxflushlock);
489 ath_rx_tasklet(sc, 0); 491 ath_rx_tasklet(sc, 0);
490 spin_unlock_bh(&sc->sc_rxflushlock); 492 spin_unlock_bh(&sc->rx.rxflushlock);
491 } 493 }
492 /* XXX: optimize this */ 494 /* XXX: optimize this */
493 if (status & ATH9K_INT_TX) 495 if (status & ATH9K_INT_TX)
@@ -597,6 +599,8 @@ static irqreturn_t ath_isr(int irq, void *dev)
597 } 599 }
598 } while (0); 600 } while (0);
599 601
602 ath_debug_stat_interrupt(sc, status);
603
600 if (sched) { 604 if (sched) {
601 /* turn off every interrupt except SWBA */ 605 /* turn off every interrupt except SWBA */
602 ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA)); 606 ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA));
@@ -1302,7 +1306,7 @@ static void ath_detach(struct ath_softc *sc)
1302 /* cleanup tx queues */ 1306 /* cleanup tx queues */
1303 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 1307 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1304 if (ATH_TXQ_SETUP(sc, i)) 1308 if (ATH_TXQ_SETUP(sc, i))
1305 ath_tx_cleanupq(sc, &sc->sc_txq[i]); 1309 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1306 1310
1307 ath9k_hw_detach(sc->sc_ah); 1311 ath9k_hw_detach(sc->sc_ah);
1308 ath9k_exit_debug(sc); 1312 ath9k_exit_debug(sc);
@@ -1393,15 +1397,15 @@ static int ath_init(u16 devid, struct ath_softc *sc)
1393 * priority. Note that the hal handles reseting 1397 * priority. Note that the hal handles reseting
1394 * these queues at the needed time. 1398 * these queues at the needed time.
1395 */ 1399 */
1396 sc->sc_bhalq = ath_beaconq_setup(ah); 1400 sc->beacon.beaconq = ath_beaconq_setup(ah);
1397 if (sc->sc_bhalq == -1) { 1401 if (sc->beacon.beaconq == -1) {
1398 DPRINTF(sc, ATH_DBG_FATAL, 1402 DPRINTF(sc, ATH_DBG_FATAL,
1399 "Unable to setup a beacon xmit queue\n"); 1403 "Unable to setup a beacon xmit queue\n");
1400 error = -EIO; 1404 error = -EIO;
1401 goto bad2; 1405 goto bad2;
1402 } 1406 }
1403 sc->sc_cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0); 1407 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1404 if (sc->sc_cabq == NULL) { 1408 if (sc->beacon.cabq == NULL) {
1405 DPRINTF(sc, ATH_DBG_FATAL, 1409 DPRINTF(sc, ATH_DBG_FATAL,
1406 "Unable to setup CAB xmit queue\n"); 1410 "Unable to setup CAB xmit queue\n");
1407 error = -EIO; 1411 error = -EIO;
@@ -1411,8 +1415,8 @@ static int ath_init(u16 devid, struct ath_softc *sc)
1411 sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME; 1415 sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME;
1412 ath_cabq_update(sc); 1416 ath_cabq_update(sc);
1413 1417
1414 for (i = 0; i < ARRAY_SIZE(sc->sc_haltype2q); i++) 1418 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1415 sc->sc_haltype2q[i] = -1; 1419 sc->tx.hwq_map[i] = -1;
1416 1420
1417 /* Setup data queues */ 1421 /* Setup data queues */
1418 /* NB: ensure BK queue is the lowest priority h/w queue */ 1422 /* NB: ensure BK queue is the lowest priority h/w queue */
@@ -1492,7 +1496,7 @@ static int ath_init(u16 devid, struct ath_softc *sc)
1492 sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask; 1496 sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
1493 1497
1494 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL); 1498 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1495 sc->sc_defant = ath9k_hw_getdefantenna(ah); 1499 sc->rx.defant = ath9k_hw_getdefantenna(ah);
1496 1500
1497 ath9k_hw_getmac(ah, sc->sc_myaddr); 1501 ath9k_hw_getmac(ah, sc->sc_myaddr);
1498 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) { 1502 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
@@ -1501,20 +1505,15 @@ static int ath_init(u16 devid, struct ath_softc *sc)
1501 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask); 1505 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
1502 } 1506 }
1503 1507
1504 sc->sc_slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */ 1508 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
1505 1509
1506 /* initialize beacon slots */ 1510 /* initialize beacon slots */
1507 for (i = 0; i < ARRAY_SIZE(sc->sc_bslot); i++) 1511 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
1508 sc->sc_bslot[i] = ATH_IF_ID_ANY; 1512 sc->beacon.bslot[i] = ATH_IF_ID_ANY;
1509 1513
1510 /* save MISC configurations */ 1514 /* save MISC configurations */
1511 sc->sc_config.swBeaconProcess = 1; 1515 sc->sc_config.swBeaconProcess = 1;
1512 1516
1513#ifdef CONFIG_SLOW_ANT_DIV
1514 /* range is 40 - 255, we use something in the middle */
1515 ath_slow_ant_div_init(&sc->sc_antdiv, sc, 0x127);
1516#endif
1517
1518 /* setup channels and rates */ 1517 /* setup channels and rates */
1519 1518
1520 sc->sbands[IEEE80211_BAND_2GHZ].channels = 1519 sc->sbands[IEEE80211_BAND_2GHZ].channels =
@@ -1536,7 +1535,7 @@ bad2:
1536 /* cleanup tx queues */ 1535 /* cleanup tx queues */
1537 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 1536 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1538 if (ATH_TXQ_SETUP(sc, i)) 1537 if (ATH_TXQ_SETUP(sc, i))
1539 ath_tx_cleanupq(sc, &sc->sc_txq[i]); 1538 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1540bad: 1539bad:
1541 if (ah) 1540 if (ah)
1542 ath9k_hw_detach(ah); 1541 ath9k_hw_detach(ah);
@@ -1674,9 +1673,9 @@ int ath_reset(struct ath_softc *sc, bool retry_tx)
1674 int i; 1673 int i;
1675 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1674 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1676 if (ATH_TXQ_SETUP(sc, i)) { 1675 if (ATH_TXQ_SETUP(sc, i)) {
1677 spin_lock_bh(&sc->sc_txq[i].axq_lock); 1676 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1678 ath_txq_schedule(sc, &sc->sc_txq[i]); 1677 ath_txq_schedule(sc, &sc->tx.txq[i]);
1679 spin_unlock_bh(&sc->sc_txq[i].axq_lock); 1678 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1680 } 1679 }
1681 } 1680 }
1682 } 1681 }
@@ -1811,19 +1810,19 @@ int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1811 1810
1812 switch (queue) { 1811 switch (queue) {
1813 case 0: 1812 case 0:
1814 qnum = sc->sc_haltype2q[ATH9K_WME_AC_VO]; 1813 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
1815 break; 1814 break;
1816 case 1: 1815 case 1:
1817 qnum = sc->sc_haltype2q[ATH9K_WME_AC_VI]; 1816 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
1818 break; 1817 break;
1819 case 2: 1818 case 2:
1820 qnum = sc->sc_haltype2q[ATH9K_WME_AC_BE]; 1819 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1821 break; 1820 break;
1822 case 3: 1821 case 3:
1823 qnum = sc->sc_haltype2q[ATH9K_WME_AC_BK]; 1822 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
1824 break; 1823 break;
1825 default: 1824 default:
1826 qnum = sc->sc_haltype2q[ATH9K_WME_AC_BE]; 1825 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1827 break; 1826 break;
1828 } 1827 }
1829 1828
@@ -1994,9 +1993,9 @@ static int ath9k_tx(struct ieee80211_hw *hw,
1994 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { 1993 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1995 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 1994 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1996 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) 1995 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1997 sc->seq_no += 0x10; 1996 sc->tx.seq_no += 0x10;
1998 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); 1997 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1999 hdr->seq_ctrl |= cpu_to_le16(sc->seq_no); 1998 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2000 } 1999 }
2001 2000
2002 /* Add the padding after the header if this is not already done */ 2001 /* Add the padding after the header if this is not already done */
@@ -2050,7 +2049,7 @@ static void ath9k_stop(struct ieee80211_hw *hw)
2050 ath_stoprecv(sc); 2049 ath_stoprecv(sc);
2051 ath9k_hw_phy_disable(sc->sc_ah); 2050 ath9k_hw_phy_disable(sc->sc_ah);
2052 } else 2051 } else
2053 sc->sc_rxlink = NULL; 2052 sc->rx.rxlink = NULL;
2054 2053
2055#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 2054#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2056 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 2055 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
@@ -2126,16 +2125,13 @@ static void ath9k_remove_interface(struct ieee80211_hw *hw,
2126 2125
2127 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n"); 2126 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2128 2127
2129#ifdef CONFIG_SLOW_ANT_DIV
2130 ath_slow_ant_div_stop(&sc->sc_antdiv);
2131#endif
2132 /* Stop ANI */ 2128 /* Stop ANI */
2133 del_timer_sync(&sc->sc_ani.timer); 2129 del_timer_sync(&sc->sc_ani.timer);
2134 2130
2135 /* Reclaim beacon resources */ 2131 /* Reclaim beacon resources */
2136 if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP || 2132 if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP ||
2137 sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) { 2133 sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) {
2138 ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq); 2134 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2139 ath_beacon_return(sc, avp); 2135 ath_beacon_return(sc, avp);
2140 } 2136 }
2141 2137
@@ -2254,7 +2250,7 @@ static int ath9k_config_interface(struct ieee80211_hw *hw,
2254 * causes reconfiguration; we may be called 2250 * causes reconfiguration; we may be called
2255 * with beacon transmission active. 2251 * with beacon transmission active.
2256 */ 2252 */
2257 ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq); 2253 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2258 2254
2259 error = ath_beacon_alloc(sc, 0); 2255 error = ath_beacon_alloc(sc, 0);
2260 if (error != 0) 2256 if (error != 0)
@@ -2300,7 +2296,7 @@ static void ath9k_configure_filter(struct ieee80211_hw *hw,
2300 changed_flags &= SUPPORTED_FILTERS; 2296 changed_flags &= SUPPORTED_FILTERS;
2301 *total_flags &= SUPPORTED_FILTERS; 2297 *total_flags &= SUPPORTED_FILTERS;
2302 2298
2303 sc->rx_filter = *total_flags; 2299 sc->rx.rxfilter = *total_flags;
2304 rfilt = ath_calcrxfilter(sc); 2300 rfilt = ath_calcrxfilter(sc);
2305 ath9k_hw_setrxfilter(sc->sc_ah, rfilt); 2301 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2306 2302
@@ -2309,7 +2305,7 @@ static void ath9k_configure_filter(struct ieee80211_hw *hw,
2309 ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0); 2305 ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
2310 } 2306 }
2311 2307
2312 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx_filter); 2308 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
2313} 2309}
2314 2310
2315static void ath9k_sta_notify(struct ieee80211_hw *hw, 2311static void ath9k_sta_notify(struct ieee80211_hw *hw,
@@ -2491,11 +2487,6 @@ static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2491 return ret; 2487 return ret;
2492} 2488}
2493 2489
2494static int ath9k_no_fragmentation(struct ieee80211_hw *hw, u32 value)
2495{
2496 return -EOPNOTSUPP;
2497}
2498
2499static struct ieee80211_ops ath9k_ops = { 2490static struct ieee80211_ops ath9k_ops = {
2500 .tx = ath9k_tx, 2491 .tx = ath9k_tx,
2501 .start = ath9k_start, 2492 .start = ath9k_start,
@@ -2512,7 +2503,6 @@ static struct ieee80211_ops ath9k_ops = {
2512 .get_tsf = ath9k_get_tsf, 2503 .get_tsf = ath9k_get_tsf,
2513 .reset_tsf = ath9k_reset_tsf, 2504 .reset_tsf = ath9k_reset_tsf,
2514 .ampdu_action = ath9k_ampdu_action, 2505 .ampdu_action = ath9k_ampdu_action,
2515 .set_frag_threshold = ath9k_no_fragmentation,
2516}; 2506};
2517 2507
2518static struct { 2508static struct {
diff --git a/drivers/net/wireless/ath9k/phy.h b/drivers/net/wireless/ath9k/phy.h
index 14702344448b..3a406a5c0593 100644
--- a/drivers/net/wireless/ath9k/phy.h
+++ b/drivers/net/wireless/ath9k/phy.h
@@ -50,6 +50,9 @@ bool ath9k_hw_init_rf(struct ath_hal *ah,
50#define AR_PHY_FC_SHORT_GI_40 0x00000080 50#define AR_PHY_FC_SHORT_GI_40 0x00000080
51#define AR_PHY_FC_WALSH 0x00000100 51#define AR_PHY_FC_WALSH 0x00000100
52#define AR_PHY_FC_SINGLE_HT_LTF1 0x00000200 52#define AR_PHY_FC_SINGLE_HT_LTF1 0x00000200
53#define AR_PHY_FC_ENABLE_DAC_FIFO 0x00000800
54
55#define AR_PHY_TEST2 0x9808
53 56
54#define AR_PHY_TIMING2 0x9810 57#define AR_PHY_TIMING2 0x9810
55#define AR_PHY_TIMING3 0x9814 58#define AR_PHY_TIMING3 0x9814
@@ -100,6 +103,8 @@ bool ath9k_hw_init_rf(struct ath_hal *ah,
100#define AR_PHY_RF_CTL4_FRAME_XPAA_ON 0x000000FF 103#define AR_PHY_RF_CTL4_FRAME_XPAA_ON 0x000000FF
101#define AR_PHY_RF_CTL4_FRAME_XPAA_ON_S 0 104#define AR_PHY_RF_CTL4_FRAME_XPAA_ON_S 0
102 105
106#define AR_PHY_TSTDAC_CONST 0x983c
107
103#define AR_PHY_SETTLING 0x9844 108#define AR_PHY_SETTLING 0x9844
104#define AR_PHY_SETTLING_SWITCH 0x00003F80 109#define AR_PHY_SETTLING_SWITCH 0x00003F80
105#define AR_PHY_SETTLING_SWITCH_S 7 110#define AR_PHY_SETTLING_SWITCH_S 7
diff --git a/drivers/net/wireless/ath9k/rc.c b/drivers/net/wireless/ath9k/rc.c
index 76acd2b75fcd..0ae5988e0b65 100644
--- a/drivers/net/wireless/ath9k/rc.c
+++ b/drivers/net/wireless/ath9k/rc.c
@@ -817,7 +817,7 @@ static void ath_rc_ratefind(struct ath_softc *sc,
817 struct ath_rate_table *rate_table; 817 struct ath_rate_table *rate_table;
818 struct ieee80211_tx_rate *rates = tx_info->control.rates; 818 struct ieee80211_tx_rate *rates = tx_info->control.rates;
819 819
820 rate_table = sc->hw_rate_table[sc->sc_curmode]; 820 rate_table = sc->cur_rate_table;
821 rix = ath_rc_ratefind_ht(sc, ath_rc_priv, rate_table, 1, 821 rix = ath_rc_ratefind_ht(sc, ath_rc_priv, rate_table, 1,
822 is_probe, is_retry); 822 is_probe, is_retry);
823 nrix = rix; 823 nrix = rix;
@@ -874,10 +874,9 @@ static void ath_rc_ratefind(struct ath_softc *sc,
874 * So, set fourth rate in series to be same as third one for 874 * So, set fourth rate in series to be same as third one for
875 * above conditions. 875 * above conditions.
876 */ 876 */
877 if ((sc->sc_curmode == ATH9K_MODE_11NG_HT20) || 877 if ((sc->hw->conf.channel->band == IEEE80211_BAND_2GHZ) &&
878 (sc->sc_curmode == ATH9K_MODE_11NG_HT40PLUS) || 878 (sc->hw->conf.ht.enabled)) {
879 (sc->sc_curmode == ATH9K_MODE_11NG_HT40MINUS)) { 879 u8 dot11rate = rate_table->info[rix].dot11rate;
880 u8 dot11rate = rate_table->info[rix].dot11rate;
881 u8 phy = rate_table->info[rix].phy; 880 u8 phy = rate_table->info[rix].phy;
882 if (i == 4 && 881 if (i == 4 &&
883 ((dot11rate == 2 && phy == WLAN_RC_PHY_HT_40_SS) || 882 ((dot11rate == 2 && phy == WLAN_RC_PHY_HT_40_SS) ||
@@ -1094,7 +1093,7 @@ static void ath_rc_update_ht(struct ath_softc *sc,
1094 int rate; 1093 int rate;
1095 u8 last_per; 1094 u8 last_per;
1096 bool state_change = false; 1095 bool state_change = false;
1097 struct ath_rate_table *rate_table = sc->hw_rate_table[sc->sc_curmode]; 1096 struct ath_rate_table *rate_table = sc->cur_rate_table;
1098 int size = ath_rc_priv->rate_table_size; 1097 int size = ath_rc_priv->rate_table_size;
1099 1098
1100 if ((tx_rate < 0) || (tx_rate > rate_table->rate_cnt)) 1099 if ((tx_rate < 0) || (tx_rate > rate_table->rate_cnt))
@@ -1254,7 +1253,7 @@ static void ath_rc_tx_status(struct ath_softc *sc,
1254 u8 flags; 1253 u8 flags;
1255 u32 i = 0, rix; 1254 u32 i = 0, rix;
1256 1255
1257 rate_table = sc->hw_rate_table[sc->sc_curmode]; 1256 rate_table = sc->cur_rate_table;
1258 1257
1259 /* 1258 /*
1260 * If the first rate is not the final index, there 1259 * If the first rate is not the final index, there
@@ -1354,8 +1353,8 @@ static void ath_rc_init(struct ath_softc *sc,
1354 sta->ht_cap.ht_supported, 1353 sta->ht_cap.ht_supported,
1355 is_cw_40); 1354 is_cw_40);
1356 } else if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP) { 1355 } else if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP) {
1357 /* sc_curmode would be set on init through config() */ 1356 /* cur_rate_table would be set on init through config() */
1358 rate_table = sc->hw_rate_table[sc->sc_curmode]; 1357 rate_table = sc->cur_rate_table;
1359 } 1358 }
1360 1359
1361 if (!rate_table) { 1360 if (!rate_table) {
@@ -1432,6 +1431,7 @@ static void ath_rc_init(struct ath_softc *sc,
1432 ath_rc_priv->max_valid_rate = k; 1431 ath_rc_priv->max_valid_rate = k;
1433 ath_rc_sort_validrates(rate_table, ath_rc_priv); 1432 ath_rc_sort_validrates(rate_table, ath_rc_priv);
1434 ath_rc_priv->rate_max_phy = ath_rc_priv->valid_rate_index[k-4]; 1433 ath_rc_priv->rate_max_phy = ath_rc_priv->valid_rate_index[k-4];
1434 sc->cur_rate_table = rate_table;
1435} 1435}
1436 1436
1437/* Rate Control callbacks */ 1437/* Rate Control callbacks */
diff --git a/drivers/net/wireless/ath9k/recv.c b/drivers/net/wireless/ath9k/recv.c
index 7a455468823b..f2327d8e9c28 100644
--- a/drivers/net/wireless/ath9k/recv.c
+++ b/drivers/net/wireless/ath9k/recv.c
@@ -41,20 +41,19 @@ static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf)
41 ASSERT(skb != NULL); 41 ASSERT(skb != NULL);
42 ds->ds_vdata = skb->data; 42 ds->ds_vdata = skb->data;
43 43
44 /* setup rx descriptors. The sc_rxbufsize here tells the harware 44 /* setup rx descriptors. The rx.bufsize here tells the harware
45 * how much data it can DMA to us and that we are prepared 45 * how much data it can DMA to us and that we are prepared
46 * to process */ 46 * to process */
47 ath9k_hw_setuprxdesc(ah, 47 ath9k_hw_setuprxdesc(ah, ds,
48 ds, 48 sc->rx.bufsize,
49 sc->sc_rxbufsize,
50 0); 49 0);
51 50
52 if (sc->sc_rxlink == NULL) 51 if (sc->rx.rxlink == NULL)
53 ath9k_hw_putrxbuf(ah, bf->bf_daddr); 52 ath9k_hw_putrxbuf(ah, bf->bf_daddr);
54 else 53 else
55 *sc->sc_rxlink = bf->bf_daddr; 54 *sc->rx.rxlink = bf->bf_daddr;
56 55
57 sc->sc_rxlink = &ds->ds_link; 56 sc->rx.rxlink = &ds->ds_link;
58 ath9k_hw_rxena(ah); 57 ath9k_hw_rxena(ah);
59} 58}
60 59
@@ -62,8 +61,8 @@ static void ath_setdefantenna(struct ath_softc *sc, u32 antenna)
62{ 61{
63 /* XXX block beacon interrupts */ 62 /* XXX block beacon interrupts */
64 ath9k_hw_setantenna(sc->sc_ah, antenna); 63 ath9k_hw_setantenna(sc->sc_ah, antenna);
65 sc->sc_defant = antenna; 64 sc->rx.defant = antenna;
66 sc->sc_rxotherant = 0; 65 sc->rx.rxotherant = 0;
67} 66}
68 67
69/* 68/*
@@ -148,7 +147,7 @@ static int ath_rx_prepare(struct sk_buff *skb, struct ath_desc *ds,
148 struct ieee80211_rx_status *rx_status, bool *decrypt_error, 147 struct ieee80211_rx_status *rx_status, bool *decrypt_error,
149 struct ath_softc *sc) 148 struct ath_softc *sc)
150{ 149{
151 struct ath_rate_table *rate_table = sc->hw_rate_table[sc->sc_curmode]; 150 struct ath_rate_table *rate_table = sc->cur_rate_table;
152 struct ieee80211_hdr *hdr; 151 struct ieee80211_hdr *hdr;
153 int ratekbps, rix; 152 int ratekbps, rix;
154 u8 ratecode; 153 u8 ratecode;
@@ -272,20 +271,20 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
272 int error = 0; 271 int error = 0;
273 272
274 do { 273 do {
275 spin_lock_init(&sc->sc_rxflushlock); 274 spin_lock_init(&sc->rx.rxflushlock);
276 sc->sc_flags &= ~SC_OP_RXFLUSH; 275 sc->sc_flags &= ~SC_OP_RXFLUSH;
277 spin_lock_init(&sc->sc_rxbuflock); 276 spin_lock_init(&sc->rx.rxbuflock);
278 277
279 sc->sc_rxbufsize = roundup(IEEE80211_MAX_MPDU_LEN, 278 sc->rx.bufsize = roundup(IEEE80211_MAX_MPDU_LEN,
280 min(sc->sc_cachelsz, 279 min(sc->sc_cachelsz,
281 (u16)64)); 280 (u16)64));
282 281
283 DPRINTF(sc, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n", 282 DPRINTF(sc, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n",
284 sc->sc_cachelsz, sc->sc_rxbufsize); 283 sc->sc_cachelsz, sc->rx.bufsize);
285 284
286 /* Initialize rx descriptors */ 285 /* Initialize rx descriptors */
287 286
288 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 287 error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
289 "rx", nbufs, 1); 288 "rx", nbufs, 1);
290 if (error != 0) { 289 if (error != 0) {
291 DPRINTF(sc, ATH_DBG_FATAL, 290 DPRINTF(sc, ATH_DBG_FATAL,
@@ -293,8 +292,8 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
293 break; 292 break;
294 } 293 }
295 294
296 list_for_each_entry(bf, &sc->sc_rxbuf, list) { 295 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
297 skb = ath_rxbuf_alloc(sc, sc->sc_rxbufsize); 296 skb = ath_rxbuf_alloc(sc, sc->rx.bufsize);
298 if (skb == NULL) { 297 if (skb == NULL) {
299 error = -ENOMEM; 298 error = -ENOMEM;
300 break; 299 break;
@@ -302,8 +301,8 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
302 301
303 bf->bf_mpdu = skb; 302 bf->bf_mpdu = skb;
304 bf->bf_buf_addr = pci_map_single(sc->pdev, skb->data, 303 bf->bf_buf_addr = pci_map_single(sc->pdev, skb->data,
305 sc->sc_rxbufsize, 304 sc->rx.bufsize,
306 PCI_DMA_FROMDEVICE); 305 PCI_DMA_FROMDEVICE);
307 if (unlikely(pci_dma_mapping_error(sc->pdev, 306 if (unlikely(pci_dma_mapping_error(sc->pdev,
308 bf->bf_buf_addr))) { 307 bf->bf_buf_addr))) {
309 dev_kfree_skb_any(skb); 308 dev_kfree_skb_any(skb);
@@ -315,7 +314,7 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
315 } 314 }
316 bf->bf_dmacontext = bf->bf_buf_addr; 315 bf->bf_dmacontext = bf->bf_buf_addr;
317 } 316 }
318 sc->sc_rxlink = NULL; 317 sc->rx.rxlink = NULL;
319 318
320 } while (0); 319 } while (0);
321 320
@@ -330,14 +329,14 @@ void ath_rx_cleanup(struct ath_softc *sc)
330 struct sk_buff *skb; 329 struct sk_buff *skb;
331 struct ath_buf *bf; 330 struct ath_buf *bf;
332 331
333 list_for_each_entry(bf, &sc->sc_rxbuf, list) { 332 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
334 skb = bf->bf_mpdu; 333 skb = bf->bf_mpdu;
335 if (skb) 334 if (skb)
336 dev_kfree_skb(skb); 335 dev_kfree_skb(skb);
337 } 336 }
338 337
339 if (sc->sc_rxdma.dd_desc_len != 0) 338 if (sc->rx.rxdma.dd_desc_len != 0)
340 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 339 ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf);
341} 340}
342 341
343/* 342/*
@@ -375,7 +374,7 @@ u32 ath_calcrxfilter(struct ath_softc *sc)
375 374
376 /* Can't set HOSTAP into promiscous mode */ 375 /* Can't set HOSTAP into promiscous mode */
377 if (((sc->sc_ah->ah_opmode != NL80211_IFTYPE_AP) && 376 if (((sc->sc_ah->ah_opmode != NL80211_IFTYPE_AP) &&
378 (sc->rx_filter & FIF_PROMISC_IN_BSS)) || 377 (sc->rx.rxfilter & FIF_PROMISC_IN_BSS)) ||
379 (sc->sc_ah->ah_opmode == NL80211_IFTYPE_MONITOR)) { 378 (sc->sc_ah->ah_opmode == NL80211_IFTYPE_MONITOR)) {
380 rfilt |= ATH9K_RX_FILTER_PROM; 379 rfilt |= ATH9K_RX_FILTER_PROM;
381 /* ??? To prevent from sending ACK */ 380 /* ??? To prevent from sending ACK */
@@ -401,25 +400,25 @@ int ath_startrecv(struct ath_softc *sc)
401 struct ath_hal *ah = sc->sc_ah; 400 struct ath_hal *ah = sc->sc_ah;
402 struct ath_buf *bf, *tbf; 401 struct ath_buf *bf, *tbf;
403 402
404 spin_lock_bh(&sc->sc_rxbuflock); 403 spin_lock_bh(&sc->rx.rxbuflock);
405 if (list_empty(&sc->sc_rxbuf)) 404 if (list_empty(&sc->rx.rxbuf))
406 goto start_recv; 405 goto start_recv;
407 406
408 sc->sc_rxlink = NULL; 407 sc->rx.rxlink = NULL;
409 list_for_each_entry_safe(bf, tbf, &sc->sc_rxbuf, list) { 408 list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) {
410 ath_rx_buf_link(sc, bf); 409 ath_rx_buf_link(sc, bf);
411 } 410 }
412 411
413 /* We could have deleted elements so the list may be empty now */ 412 /* We could have deleted elements so the list may be empty now */
414 if (list_empty(&sc->sc_rxbuf)) 413 if (list_empty(&sc->rx.rxbuf))
415 goto start_recv; 414 goto start_recv;
416 415
417 bf = list_first_entry(&sc->sc_rxbuf, struct ath_buf, list); 416 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
418 ath9k_hw_putrxbuf(ah, bf->bf_daddr); 417 ath9k_hw_putrxbuf(ah, bf->bf_daddr);
419 ath9k_hw_rxena(ah); 418 ath9k_hw_rxena(ah);
420 419
421start_recv: 420start_recv:
422 spin_unlock_bh(&sc->sc_rxbuflock); 421 spin_unlock_bh(&sc->rx.rxbuflock);
423 ath_opmode_init(sc); 422 ath_opmode_init(sc);
424 ath9k_hw_startpcureceive(ah); 423 ath9k_hw_startpcureceive(ah);
425 424
@@ -435,25 +434,25 @@ bool ath_stoprecv(struct ath_softc *sc)
435 ath9k_hw_setrxfilter(ah, 0); 434 ath9k_hw_setrxfilter(ah, 0);
436 stopped = ath9k_hw_stopdmarecv(ah); 435 stopped = ath9k_hw_stopdmarecv(ah);
437 mdelay(3); /* 3ms is long enough for 1 frame */ 436 mdelay(3); /* 3ms is long enough for 1 frame */
438 sc->sc_rxlink = NULL; 437 sc->rx.rxlink = NULL;
439 438
440 return stopped; 439 return stopped;
441} 440}
442 441
443void ath_flushrecv(struct ath_softc *sc) 442void ath_flushrecv(struct ath_softc *sc)
444{ 443{
445 spin_lock_bh(&sc->sc_rxflushlock); 444 spin_lock_bh(&sc->rx.rxflushlock);
446 sc->sc_flags |= SC_OP_RXFLUSH; 445 sc->sc_flags |= SC_OP_RXFLUSH;
447 ath_rx_tasklet(sc, 1); 446 ath_rx_tasklet(sc, 1);
448 sc->sc_flags &= ~SC_OP_RXFLUSH; 447 sc->sc_flags &= ~SC_OP_RXFLUSH;
449 spin_unlock_bh(&sc->sc_rxflushlock); 448 spin_unlock_bh(&sc->rx.rxflushlock);
450} 449}
451 450
452int ath_rx_tasklet(struct ath_softc *sc, int flush) 451int ath_rx_tasklet(struct ath_softc *sc, int flush)
453{ 452{
454#define PA2DESC(_sc, _pa) \ 453#define PA2DESC(_sc, _pa) \
455 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 454 ((struct ath_desc *)((caddr_t)(_sc)->rx.rxdma.dd_desc + \
456 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 455 ((_pa) - (_sc)->rx.rxdma.dd_desc_paddr)))
457 456
458 struct ath_buf *bf; 457 struct ath_buf *bf;
459 struct ath_desc *ds; 458 struct ath_desc *ds;
@@ -465,19 +464,19 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
465 bool decrypt_error = false; 464 bool decrypt_error = false;
466 u8 keyix; 465 u8 keyix;
467 466
468 spin_lock_bh(&sc->sc_rxbuflock); 467 spin_lock_bh(&sc->rx.rxbuflock);
469 468
470 do { 469 do {
471 /* If handling rx interrupt and flush is in progress => exit */ 470 /* If handling rx interrupt and flush is in progress => exit */
472 if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0)) 471 if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0))
473 break; 472 break;
474 473
475 if (list_empty(&sc->sc_rxbuf)) { 474 if (list_empty(&sc->rx.rxbuf)) {
476 sc->sc_rxlink = NULL; 475 sc->rx.rxlink = NULL;
477 break; 476 break;
478 } 477 }
479 478
480 bf = list_first_entry(&sc->sc_rxbuf, struct ath_buf, list); 479 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
481 ds = bf->bf_desc; 480 ds = bf->bf_desc;
482 481
483 /* 482 /*
@@ -499,8 +498,8 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
499 struct ath_buf *tbf; 498 struct ath_buf *tbf;
500 struct ath_desc *tds; 499 struct ath_desc *tds;
501 500
502 if (list_is_last(&bf->list, &sc->sc_rxbuf)) { 501 if (list_is_last(&bf->list, &sc->rx.rxbuf)) {
503 sc->sc_rxlink = NULL; 502 sc->rx.rxlink = NULL;
504 break; 503 break;
505 } 504 }
506 505
@@ -540,7 +539,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
540 goto requeue; 539 goto requeue;
541 540
542 /* The status portion of the descriptor could get corrupted. */ 541 /* The status portion of the descriptor could get corrupted. */
543 if (sc->sc_rxbufsize < ds->ds_rxstat.rs_datalen) 542 if (sc->rx.bufsize < ds->ds_rxstat.rs_datalen)
544 goto requeue; 543 goto requeue;
545 544
546 if (!ath_rx_prepare(skb, ds, &rx_status, &decrypt_error, sc)) 545 if (!ath_rx_prepare(skb, ds, &rx_status, &decrypt_error, sc))
@@ -548,21 +547,21 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
548 547
549 /* Ensure we always have an skb to requeue once we are done 548 /* Ensure we always have an skb to requeue once we are done
550 * processing the current buffer's skb */ 549 * processing the current buffer's skb */
551 requeue_skb = ath_rxbuf_alloc(sc, sc->sc_rxbufsize); 550 requeue_skb = ath_rxbuf_alloc(sc, sc->rx.bufsize);
552 551
553 /* If there is no memory we ignore the current RX'd frame, 552 /* If there is no memory we ignore the current RX'd frame,
554 * tell hardware it can give us a new frame using the old 553 * tell hardware it can give us a new frame using the old
555 * skb and put it at the tail of the sc->sc_rxbuf list for 554 * skb and put it at the tail of the sc->rx.rxbuf list for
556 * processing. */ 555 * processing. */
557 if (!requeue_skb) 556 if (!requeue_skb)
558 goto requeue; 557 goto requeue;
559 558
560 pci_dma_sync_single_for_cpu(sc->pdev, 559 /* Sync and unmap the frame */
561 bf->bf_buf_addr, 560 pci_dma_sync_single_for_cpu(sc->pdev, bf->bf_buf_addr,
562 sc->sc_rxbufsize, 561 sc->rx.bufsize,
563 PCI_DMA_FROMDEVICE); 562 PCI_DMA_FROMDEVICE);
564 pci_unmap_single(sc->pdev, bf->bf_buf_addr, 563 pci_unmap_single(sc->pdev, bf->bf_buf_addr,
565 sc->sc_rxbufsize, 564 sc->rx.bufsize,
566 PCI_DMA_FROMDEVICE); 565 PCI_DMA_FROMDEVICE);
567 566
568 skb_put(skb, ds->ds_rxstat.rs_datalen); 567 skb_put(skb, ds->ds_rxstat.rs_datalen);
@@ -572,8 +571,16 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
572 hdr = (struct ieee80211_hdr *)skb->data; 571 hdr = (struct ieee80211_hdr *)skb->data;
573 hdrlen = ieee80211_get_hdrlen_from_skb(skb); 572 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
574 573
575 if (hdrlen & 3) { 574 /* The MAC header is padded to have 32-bit boundary if the
576 padsize = hdrlen % 4; 575 * packet payload is non-zero. The general calculation for
576 * padsize would take into account odd header lengths:
577 * padsize = (4 - hdrlen % 4) % 4; However, since only
578 * even-length headers are used, padding can only be 0 or 2
579 * bytes and we can optimize this a bit. In addition, we must
580 * not try to remove padding from short control frames that do
581 * not have payload. */
582 padsize = hdrlen & 3;
583 if (padsize && hdrlen >= 24) {
577 memmove(skb->data + padsize, skb->data, hdrlen); 584 memmove(skb->data + padsize, skb->data, hdrlen);
578 skb_pull(skb, padsize); 585 skb_pull(skb, padsize);
579 } 586 }
@@ -596,7 +603,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
596 /* We will now give hardware our shiny new allocated skb */ 603 /* We will now give hardware our shiny new allocated skb */
597 bf->bf_mpdu = requeue_skb; 604 bf->bf_mpdu = requeue_skb;
598 bf->bf_buf_addr = pci_map_single(sc->pdev, requeue_skb->data, 605 bf->bf_buf_addr = pci_map_single(sc->pdev, requeue_skb->data,
599 sc->sc_rxbufsize, 606 sc->rx.bufsize,
600 PCI_DMA_FROMDEVICE); 607 PCI_DMA_FROMDEVICE);
601 if (unlikely(pci_dma_mapping_error(sc->pdev, 608 if (unlikely(pci_dma_mapping_error(sc->pdev,
602 bf->bf_buf_addr))) { 609 bf->bf_buf_addr))) {
@@ -612,18 +619,18 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
612 * change the default rx antenna if rx diversity chooses the 619 * change the default rx antenna if rx diversity chooses the
613 * other antenna 3 times in a row. 620 * other antenna 3 times in a row.
614 */ 621 */
615 if (sc->sc_defant != ds->ds_rxstat.rs_antenna) { 622 if (sc->rx.defant != ds->ds_rxstat.rs_antenna) {
616 if (++sc->sc_rxotherant >= 3) 623 if (++sc->rx.rxotherant >= 3)
617 ath_setdefantenna(sc, ds->ds_rxstat.rs_antenna); 624 ath_setdefantenna(sc, ds->ds_rxstat.rs_antenna);
618 } else { 625 } else {
619 sc->sc_rxotherant = 0; 626 sc->rx.rxotherant = 0;
620 } 627 }
621requeue: 628requeue:
622 list_move_tail(&bf->list, &sc->sc_rxbuf); 629 list_move_tail(&bf->list, &sc->rx.rxbuf);
623 ath_rx_buf_link(sc, bf); 630 ath_rx_buf_link(sc, bf);
624 } while (1); 631 } while (1);
625 632
626 spin_unlock_bh(&sc->sc_rxbuflock); 633 spin_unlock_bh(&sc->rx.rxbuflock);
627 634
628 return 0; 635 return 0;
629#undef PA2DESC 636#undef PA2DESC
diff --git a/drivers/net/wireless/ath9k/reg.h b/drivers/net/wireless/ath9k/reg.h
index 60617ae66209..9fedb4911bc3 100644
--- a/drivers/net/wireless/ath9k/reg.h
+++ b/drivers/net/wireless/ath9k/reg.h
@@ -671,7 +671,11 @@
671#define AR_RC_APB 0x00000002 671#define AR_RC_APB 0x00000002
672#define AR_RC_HOSTIF 0x00000100 672#define AR_RC_HOSTIF 0x00000100
673 673
674#define AR_WA 0x4004 674#define AR_WA 0x4004
675#define AR9285_WA_DEFAULT 0x004a05cb
676#define AR9280_WA_DEFAULT 0x0040073f
677#define AR_WA_DEFAULT 0x0000073f
678
675 679
676#define AR_PM_STATE 0x4008 680#define AR_PM_STATE 0x4008
677#define AR_PM_STATE_PME_D3COLD_VAUX 0x00100000 681#define AR_PM_STATE_PME_D3COLD_VAUX 0x00100000
@@ -738,6 +742,8 @@
738#define AR_SREV_REVISION_9280_21 2 742#define AR_SREV_REVISION_9280_21 2
739#define AR_SREV_VERSION_9285 0xC0 743#define AR_SREV_VERSION_9285 0xC0
740#define AR_SREV_REVISION_9285_10 0 744#define AR_SREV_REVISION_9285_10 0
745#define AR_SREV_REVISION_9285_11 1
746#define AR_SREV_REVISION_9285_12 2
741 747
742#define AR_SREV_9100_OR_LATER(_ah) \ 748#define AR_SREV_9100_OR_LATER(_ah) \
743 (((_ah)->ah_macVersion >= AR_SREV_VERSION_5416_PCIE)) 749 (((_ah)->ah_macVersion >= AR_SREV_VERSION_5416_PCIE))
@@ -768,6 +774,16 @@
768#define AR_SREV_9285(_ah) (((_ah)->ah_macVersion == AR_SREV_VERSION_9285)) 774#define AR_SREV_9285(_ah) (((_ah)->ah_macVersion == AR_SREV_VERSION_9285))
769#define AR_SREV_9285_10_OR_LATER(_ah) \ 775#define AR_SREV_9285_10_OR_LATER(_ah) \
770 (((_ah)->ah_macVersion >= AR_SREV_VERSION_9285)) 776 (((_ah)->ah_macVersion >= AR_SREV_VERSION_9285))
777#define AR_SREV_9285_11(_ah) \
778 (AR_SREV_9280(ah) && ((_ah)->ah_macRev == AR_SREV_REVISION_9285_11))
779#define AR_SREV_9285_11_OR_LATER(_ah) \
780 (((_ah)->ah_macVersion > AR_SREV_VERSION_9285) || \
781 (AR_SREV_9285(ah) && ((_ah)->ah_macRev >= AR_SREV_REVISION_9285_11)))
782#define AR_SREV_9285_12(_ah) \
783 (AR_SREV_9280(ah) && ((_ah)->ah_macRev == AR_SREV_REVISION_9285_12))
784#define AR_SREV_9285_12_OR_LATER(_ah) \
785 (((_ah)->ah_macVersion > AR_SREV_VERSION_9285) || \
786 (AR_SREV_9285(ah) && ((_ah)->ah_macRev >= AR_SREV_REVISION_9285_12)))
771 787
772#define AR_RADIO_SREV_MAJOR 0xf0 788#define AR_RADIO_SREV_MAJOR 0xf0
773#define AR_RAD5133_SREV_MAJOR 0xc0 789#define AR_RAD5133_SREV_MAJOR 0xc0
@@ -1017,6 +1033,97 @@ enum {
1017#define AR_AN_SYNTH9_REFDIVA 0xf8000000 1033#define AR_AN_SYNTH9_REFDIVA 0xf8000000
1018#define AR_AN_SYNTH9_REFDIVA_S 27 1034#define AR_AN_SYNTH9_REFDIVA_S 27
1019 1035
1036#define AR9285_AN_RF2G1 0x7820
1037#define AR9285_AN_RF2G1_ENPACAL 0x00000800
1038#define AR9285_AN_RF2G1_ENPACAL_S 11
1039#define AR9285_AN_RF2G1_PDPADRV1 0x02000000
1040#define AR9285_AN_RF2G1_PDPADRV1_S 25
1041#define AR9285_AN_RF2G1_PDPADRV2 0x01000000
1042#define AR9285_AN_RF2G1_PDPADRV2_S 24
1043#define AR9285_AN_RF2G1_PDPAOUT 0x00800000
1044#define AR9285_AN_RF2G1_PDPAOUT_S 23
1045
1046
1047#define AR9285_AN_RF2G2 0x7824
1048#define AR9285_AN_RF2G2_OFFCAL 0x00001000
1049#define AR9285_AN_RF2G2_OFFCAL_S 12
1050
1051#define AR9285_AN_RF2G3 0x7828
1052#define AR9285_AN_RF2G3_PDVCCOMP 0x02000000
1053#define AR9285_AN_RF2G3_PDVCCOMP_S 25
1054#define AR9285_AN_RF2G3_OB_0 0x00E00000
1055#define AR9285_AN_RF2G3_OB_0_S 21
1056#define AR9285_AN_RF2G3_OB_1 0x001C0000
1057#define AR9285_AN_RF2G3_OB_1_S 18
1058#define AR9285_AN_RF2G3_OB_2 0x00038000
1059#define AR9285_AN_RF2G3_OB_2_S 15
1060#define AR9285_AN_RF2G3_OB_3 0x00007000
1061#define AR9285_AN_RF2G3_OB_3_S 12
1062#define AR9285_AN_RF2G3_OB_4 0x00000E00
1063#define AR9285_AN_RF2G3_OB_4_S 9
1064
1065#define AR9285_AN_RF2G3_DB1_0 0x000001C0
1066#define AR9285_AN_RF2G3_DB1_0_S 6
1067#define AR9285_AN_RF2G3_DB1_1 0x00000038
1068#define AR9285_AN_RF2G3_DB1_1_S 3
1069#define AR9285_AN_RF2G3_DB1_2 0x00000007
1070#define AR9285_AN_RF2G3_DB1_2_S 0
1071#define AR9285_AN_RF2G4 0x782C
1072#define AR9285_AN_RF2G4_DB1_3 0xE0000000
1073#define AR9285_AN_RF2G4_DB1_3_S 29
1074#define AR9285_AN_RF2G4_DB1_4 0x1C000000
1075#define AR9285_AN_RF2G4_DB1_4_S 26
1076
1077#define AR9285_AN_RF2G4_DB2_0 0x03800000
1078#define AR9285_AN_RF2G4_DB2_0_S 23
1079#define AR9285_AN_RF2G4_DB2_1 0x00700000
1080#define AR9285_AN_RF2G4_DB2_1_S 20
1081#define AR9285_AN_RF2G4_DB2_2 0x000E0000
1082#define AR9285_AN_RF2G4_DB2_2_S 17
1083#define AR9285_AN_RF2G4_DB2_3 0x0001C000
1084#define AR9285_AN_RF2G4_DB2_3_S 14
1085#define AR9285_AN_RF2G4_DB2_4 0x00003800
1086#define AR9285_AN_RF2G4_DB2_4_S 11
1087
1088#define AR9285_AN_RF2G6 0x7834
1089#define AR9285_AN_RF2G6_CCOMP 0x00007800
1090#define AR9285_AN_RF2G6_CCOMP_S 11
1091#define AR9285_AN_RF2G6_OFFS 0x03f00000
1092#define AR9285_AN_RF2G6_OFFS_S 20
1093
1094#define AR9285_AN_RF2G7 0x7838
1095#define AR9285_AN_RF2G7_PWDDB 0x00000002
1096#define AR9285_AN_RF2G7_PWDDB_S 1
1097#define AR9285_AN_RF2G7_PADRVGN2TAB0 0xE0000000
1098#define AR9285_AN_RF2G7_PADRVGN2TAB0_S 29
1099
1100#define AR9285_AN_RF2G8 0x783C
1101#define AR9285_AN_RF2G8_PADRVGN2TAB0 0x0001C000
1102#define AR9285_AN_RF2G8_PADRVGN2TAB0_S 14
1103
1104
1105#define AR9285_AN_RF2G9 0x7840
1106#define AR9285_AN_RXTXBB1 0x7854
1107#define AR9285_AN_RXTXBB1_PDRXTXBB1 0x00000020
1108#define AR9285_AN_RXTXBB1_PDRXTXBB1_S 5
1109#define AR9285_AN_RXTXBB1_PDV2I 0x00000080
1110#define AR9285_AN_RXTXBB1_PDV2I_S 7
1111#define AR9285_AN_RXTXBB1_PDDACIF 0x00000100
1112#define AR9285_AN_RXTXBB1_PDDACIF_S 8
1113#define AR9285_AN_RXTXBB1_SPARE9 0x00000001
1114#define AR9285_AN_RXTXBB1_SPARE9_S 0
1115
1116#define AR9285_AN_TOP2 0x7868
1117
1118#define AR9285_AN_TOP3 0x786c
1119#define AR9285_AN_TOP3_XPABIAS_LVL 0x0000000C
1120#define AR9285_AN_TOP3_XPABIAS_LVL_S 2
1121#define AR9285_AN_TOP3_PWDDAC 0x00800000
1122#define AR9285_AN_TOP3_PWDDAC_S 23
1123
1124#define AR9285_AN_TOP4 0x7870
1125#define AR9285_AN_TOP4_DEFAULT 0x10142c00
1126
1020#define AR_STA_ID0 0x8000 1127#define AR_STA_ID0 0x8000
1021#define AR_STA_ID1 0x8004 1128#define AR_STA_ID1 0x8004
1022#define AR_STA_ID1_SADH_MASK 0x0000FFFF 1129#define AR_STA_ID1_SADH_MASK 0x0000FFFF
diff --git a/drivers/net/wireless/ath9k/xmit.c b/drivers/net/wireless/ath9k/xmit.c
index 9de27c681b86..f9c309ed3a2d 100644
--- a/drivers/net/wireless/ath9k/xmit.c
+++ b/drivers/net/wireless/ath9k/xmit.c
@@ -286,17 +286,17 @@ static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
286{ 286{
287 struct ath_buf *bf = NULL; 287 struct ath_buf *bf = NULL;
288 288
289 spin_lock_bh(&sc->sc_txbuflock); 289 spin_lock_bh(&sc->tx.txbuflock);
290 290
291 if (unlikely(list_empty(&sc->sc_txbuf))) { 291 if (unlikely(list_empty(&sc->tx.txbuf))) {
292 spin_unlock_bh(&sc->sc_txbuflock); 292 spin_unlock_bh(&sc->tx.txbuflock);
293 return NULL; 293 return NULL;
294 } 294 }
295 295
296 bf = list_first_entry(&sc->sc_txbuf, struct ath_buf, list); 296 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
297 list_del(&bf->list); 297 list_del(&bf->list);
298 298
299 spin_unlock_bh(&sc->sc_txbuflock); 299 spin_unlock_bh(&sc->tx.txbuflock);
300 300
301 return bf; 301 return bf;
302} 302}
@@ -310,6 +310,7 @@ static void ath_tx_complete_buf(struct ath_softc *sc,
310{ 310{
311 struct sk_buff *skb = bf->bf_mpdu; 311 struct sk_buff *skb = bf->bf_mpdu;
312 struct ath_xmit_status tx_status; 312 struct ath_xmit_status tx_status;
313 unsigned long flags;
313 314
314 /* 315 /*
315 * Set retry information. 316 * Set retry information.
@@ -340,9 +341,9 @@ static void ath_tx_complete_buf(struct ath_softc *sc,
340 /* 341 /*
341 * Return the list of ath_buf of this mpdu to free queue 342 * Return the list of ath_buf of this mpdu to free queue
342 */ 343 */
343 spin_lock_bh(&sc->sc_txbuflock); 344 spin_lock_irqsave(&sc->tx.txbuflock, flags);
344 list_splice_tail_init(bf_q, &sc->sc_txbuf); 345 list_splice_tail_init(bf_q, &sc->tx.txbuf);
345 spin_unlock_bh(&sc->sc_txbuflock); 346 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
346} 347}
347 348
348/* 349/*
@@ -383,7 +384,7 @@ static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
383 384
384static void ath_tx_pause_tid(struct ath_softc *sc, struct ath_atx_tid *tid) 385static void ath_tx_pause_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
385{ 386{
386 struct ath_txq *txq = &sc->sc_txq[tid->ac->qnum]; 387 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
387 388
388 spin_lock_bh(&txq->axq_lock); 389 spin_lock_bh(&txq->axq_lock);
389 390
@@ -396,7 +397,7 @@ static void ath_tx_pause_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
396 397
397void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid) 398void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
398{ 399{
399 struct ath_txq *txq = &sc->sc_txq[tid->ac->qnum]; 400 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
400 401
401 ASSERT(tid->paused > 0); 402 ASSERT(tid->paused > 0);
402 spin_lock_bh(&txq->axq_lock); 403 spin_lock_bh(&txq->axq_lock);
@@ -493,7 +494,7 @@ static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
493static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf, 494static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf,
494 int width, int half_gi, bool shortPreamble) 495 int width, int half_gi, bool shortPreamble)
495{ 496{
496 struct ath_rate_table *rate_table = sc->hw_rate_table[sc->sc_curmode]; 497 struct ath_rate_table *rate_table = sc->cur_rate_table;
497 u32 nbits, nsymbits, duration, nsymbols; 498 u32 nbits, nsymbits, duration, nsymbols;
498 u8 rc; 499 u8 rc;
499 int streams, pktlen; 500 int streams, pktlen;
@@ -557,7 +558,7 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
557 } 558 }
558 559
559 /* get the cix for the lowest valid rix */ 560 /* get the cix for the lowest valid rix */
560 rt = sc->hw_rate_table[sc->sc_curmode]; 561 rt = sc->cur_rate_table;
561 for (i = 3; i >= 0; i--) { 562 for (i = 3; i >= 0; i--) {
562 if (rates[i].count && (rates[i].idx >= 0)) { 563 if (rates[i].count && (rates[i].idx >= 0)) {
563 rix = rates[i].idx; 564 rix = rates[i].idx;
@@ -685,7 +686,7 @@ static int ath_tx_send_normal(struct ath_softc *sc,
685 686
686static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid) 687static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
687{ 688{
688 struct ath_txq *txq = &sc->sc_txq[tid->ac->qnum]; 689 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
689 struct ath_buf *bf; 690 struct ath_buf *bf;
690 struct list_head bf_head; 691 struct list_head bf_head;
691 INIT_LIST_HEAD(&bf_head); 692 INIT_LIST_HEAD(&bf_head);
@@ -860,12 +861,12 @@ static void ath_tx_complete_aggr_rifs(struct ath_softc *sc,
860 struct ath_buf *tbf; 861 struct ath_buf *tbf;
861 862
862 /* allocate new descriptor */ 863 /* allocate new descriptor */
863 spin_lock_bh(&sc->sc_txbuflock); 864 spin_lock_bh(&sc->tx.txbuflock);
864 ASSERT(!list_empty((&sc->sc_txbuf))); 865 ASSERT(!list_empty((&sc->tx.txbuf)));
865 tbf = list_first_entry(&sc->sc_txbuf, 866 tbf = list_first_entry(&sc->tx.txbuf,
866 struct ath_buf, list); 867 struct ath_buf, list);
867 list_del(&tbf->list); 868 list_del(&tbf->list);
868 spin_unlock_bh(&sc->sc_txbuflock); 869 spin_unlock_bh(&sc->tx.txbuflock);
869 870
870 ATH_TXBUF_RESET(tbf); 871 ATH_TXBUF_RESET(tbf);
871 872
@@ -1057,9 +1058,9 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
1057 1058
1058 if (bf_held) { 1059 if (bf_held) {
1059 list_del(&bf_held->list); 1060 list_del(&bf_held->list);
1060 spin_lock_bh(&sc->sc_txbuflock); 1061 spin_lock_bh(&sc->tx.txbuflock);
1061 list_add_tail(&bf_held->list, &sc->sc_txbuf); 1062 list_add_tail(&bf_held->list, &sc->tx.txbuf);
1062 spin_unlock_bh(&sc->sc_txbuflock); 1063 spin_unlock_bh(&sc->tx.txbuflock);
1063 } 1064 }
1064 1065
1065 if (!bf_isampdu(bf)) { 1066 if (!bf_isampdu(bf)) {
@@ -1128,11 +1129,11 @@ static void ath_drain_txdataq(struct ath_softc *sc, bool retry_tx)
1128 if (!(sc->sc_flags & SC_OP_INVALID)) { 1129 if (!(sc->sc_flags & SC_OP_INVALID)) {
1129 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1130 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1130 if (ATH_TXQ_SETUP(sc, i)) { 1131 if (ATH_TXQ_SETUP(sc, i)) {
1131 ath_tx_stopdma(sc, &sc->sc_txq[i]); 1132 ath_tx_stopdma(sc, &sc->tx.txq[i]);
1132 /* The TxDMA may not really be stopped. 1133 /* The TxDMA may not really be stopped.
1133 * Double check the hal tx pending count */ 1134 * Double check the hal tx pending count */
1134 npend += ath9k_hw_numtxpending(ah, 1135 npend += ath9k_hw_numtxpending(ah,
1135 sc->sc_txq[i].axq_qnum); 1136 sc->tx.txq[i].axq_qnum);
1136 } 1137 }
1137 } 1138 }
1138 } 1139 }
@@ -1157,7 +1158,7 @@ static void ath_drain_txdataq(struct ath_softc *sc, bool retry_tx)
1157 1158
1158 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1159 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1159 if (ATH_TXQ_SETUP(sc, i)) 1160 if (ATH_TXQ_SETUP(sc, i))
1160 ath_tx_draintxq(sc, &sc->sc_txq[i], retry_tx); 1161 ath_tx_draintxq(sc, &sc->tx.txq[i], retry_tx);
1161 } 1162 }
1162} 1163}
1163 1164
@@ -1240,7 +1241,7 @@ static u32 ath_lookup_rate(struct ath_softc *sc,
1240 struct ath_buf *bf, 1241 struct ath_buf *bf,
1241 struct ath_atx_tid *tid) 1242 struct ath_atx_tid *tid)
1242{ 1243{
1243 struct ath_rate_table *rate_table = sc->hw_rate_table[sc->sc_curmode]; 1244 struct ath_rate_table *rate_table = sc->cur_rate_table;
1244 struct sk_buff *skb; 1245 struct sk_buff *skb;
1245 struct ieee80211_tx_info *tx_info; 1246 struct ieee80211_tx_info *tx_info;
1246 struct ieee80211_tx_rate *rates; 1247 struct ieee80211_tx_rate *rates;
@@ -1308,7 +1309,7 @@ static int ath_compute_num_delims(struct ath_softc *sc,
1308 struct ath_buf *bf, 1309 struct ath_buf *bf,
1309 u16 frmlen) 1310 u16 frmlen)
1310{ 1311{
1311 struct ath_rate_table *rt = sc->hw_rate_table[sc->sc_curmode]; 1312 struct ath_rate_table *rt = sc->cur_rate_table;
1312 struct sk_buff *skb = bf->bf_mpdu; 1313 struct sk_buff *skb = bf->bf_mpdu;
1313 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1314 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1314 u32 nsymbits, nsymbols, mpdudensity; 1315 u32 nsymbits, nsymbols, mpdudensity;
@@ -1819,9 +1820,9 @@ int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb,
1819 } 1820 }
1820 spin_unlock_bh(&txq->axq_lock); 1821 spin_unlock_bh(&txq->axq_lock);
1821 1822
1822 spin_lock_bh(&sc->sc_txbuflock); 1823 spin_lock_bh(&sc->tx.txbuflock);
1823 list_add_tail(&bf->list, &sc->sc_txbuf); 1824 list_add_tail(&bf->list, &sc->tx.txbuf);
1824 spin_unlock_bh(&sc->sc_txbuflock); 1825 spin_unlock_bh(&sc->tx.txbuflock);
1825 1826
1826 return r; 1827 return r;
1827 } 1828 }
@@ -1838,10 +1839,10 @@ int ath_tx_init(struct ath_softc *sc, int nbufs)
1838 int error = 0; 1839 int error = 0;
1839 1840
1840 do { 1841 do {
1841 spin_lock_init(&sc->sc_txbuflock); 1842 spin_lock_init(&sc->tx.txbuflock);
1842 1843
1843 /* Setup tx descriptors */ 1844 /* Setup tx descriptors */
1844 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf, 1845 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
1845 "tx", nbufs, 1); 1846 "tx", nbufs, 1);
1846 if (error != 0) { 1847 if (error != 0) {
1847 DPRINTF(sc, ATH_DBG_FATAL, 1848 DPRINTF(sc, ATH_DBG_FATAL,
@@ -1851,7 +1852,7 @@ int ath_tx_init(struct ath_softc *sc, int nbufs)
1851 } 1852 }
1852 1853
1853 /* XXX allocate beacon state together with vap */ 1854 /* XXX allocate beacon state together with vap */
1854 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf, 1855 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
1855 "beacon", ATH_BCBUF, 1); 1856 "beacon", ATH_BCBUF, 1);
1856 if (error != 0) { 1857 if (error != 0) {
1857 DPRINTF(sc, ATH_DBG_FATAL, 1858 DPRINTF(sc, ATH_DBG_FATAL,
@@ -1873,12 +1874,12 @@ int ath_tx_init(struct ath_softc *sc, int nbufs)
1873int ath_tx_cleanup(struct ath_softc *sc) 1874int ath_tx_cleanup(struct ath_softc *sc)
1874{ 1875{
1875 /* cleanup beacon descriptors */ 1876 /* cleanup beacon descriptors */
1876 if (sc->sc_bdma.dd_desc_len != 0) 1877 if (sc->beacon.bdma.dd_desc_len != 0)
1877 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf); 1878 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf);
1878 1879
1879 /* cleanup tx descriptors */ 1880 /* cleanup tx descriptors */
1880 if (sc->sc_txdma.dd_desc_len != 0) 1881 if (sc->tx.txdma.dd_desc_len != 0)
1881 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 1882 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
1882 1883
1883 return 0; 1884 return 0;
1884} 1885}
@@ -1926,15 +1927,15 @@ struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1926 */ 1927 */
1927 return NULL; 1928 return NULL;
1928 } 1929 }
1929 if (qnum >= ARRAY_SIZE(sc->sc_txq)) { 1930 if (qnum >= ARRAY_SIZE(sc->tx.txq)) {
1930 DPRINTF(sc, ATH_DBG_FATAL, 1931 DPRINTF(sc, ATH_DBG_FATAL,
1931 "qnum %u out of range, max %u!\n", 1932 "qnum %u out of range, max %u!\n",
1932 qnum, (unsigned int)ARRAY_SIZE(sc->sc_txq)); 1933 qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq));
1933 ath9k_hw_releasetxqueue(ah, qnum); 1934 ath9k_hw_releasetxqueue(ah, qnum);
1934 return NULL; 1935 return NULL;
1935 } 1936 }
1936 if (!ATH_TXQ_SETUP(sc, qnum)) { 1937 if (!ATH_TXQ_SETUP(sc, qnum)) {
1937 struct ath_txq *txq = &sc->sc_txq[qnum]; 1938 struct ath_txq *txq = &sc->tx.txq[qnum];
1938 1939
1939 txq->axq_qnum = qnum; 1940 txq->axq_qnum = qnum;
1940 txq->axq_link = NULL; 1941 txq->axq_link = NULL;
@@ -1945,9 +1946,9 @@ struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1945 txq->axq_aggr_depth = 0; 1946 txq->axq_aggr_depth = 0;
1946 txq->axq_totalqueued = 0; 1947 txq->axq_totalqueued = 0;
1947 txq->axq_linkbuf = NULL; 1948 txq->axq_linkbuf = NULL;
1948 sc->sc_txqsetup |= 1<<qnum; 1949 sc->tx.txqsetup |= 1<<qnum;
1949 } 1950 }
1950 return &sc->sc_txq[qnum]; 1951 return &sc->tx.txq[qnum];
1951} 1952}
1952 1953
1953/* Reclaim resources for a setup queue */ 1954/* Reclaim resources for a setup queue */
@@ -1955,7 +1956,7 @@ struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1955void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 1956void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1956{ 1957{
1957 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum); 1958 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1958 sc->sc_txqsetup &= ~(1<<txq->axq_qnum); 1959 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1959} 1960}
1960 1961
1961/* 1962/*
@@ -1972,15 +1973,15 @@ int ath_tx_setup(struct ath_softc *sc, int haltype)
1972{ 1973{
1973 struct ath_txq *txq; 1974 struct ath_txq *txq;
1974 1975
1975 if (haltype >= ARRAY_SIZE(sc->sc_haltype2q)) { 1976 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
1976 DPRINTF(sc, ATH_DBG_FATAL, 1977 DPRINTF(sc, ATH_DBG_FATAL,
1977 "HAL AC %u out of range, max %zu!\n", 1978 "HAL AC %u out of range, max %zu!\n",
1978 haltype, ARRAY_SIZE(sc->sc_haltype2q)); 1979 haltype, ARRAY_SIZE(sc->tx.hwq_map));
1979 return 0; 1980 return 0;
1980 } 1981 }
1981 txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype); 1982 txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype);
1982 if (txq != NULL) { 1983 if (txq != NULL) {
1983 sc->sc_haltype2q[haltype] = txq->axq_qnum; 1984 sc->tx.hwq_map[haltype] = txq->axq_qnum;
1984 return 1; 1985 return 1;
1985 } else 1986 } else
1986 return 0; 1987 return 0;
@@ -1992,19 +1993,19 @@ int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
1992 1993
1993 switch (qtype) { 1994 switch (qtype) {
1994 case ATH9K_TX_QUEUE_DATA: 1995 case ATH9K_TX_QUEUE_DATA:
1995 if (haltype >= ARRAY_SIZE(sc->sc_haltype2q)) { 1996 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
1996 DPRINTF(sc, ATH_DBG_FATAL, 1997 DPRINTF(sc, ATH_DBG_FATAL,
1997 "HAL AC %u out of range, max %zu!\n", 1998 "HAL AC %u out of range, max %zu!\n",
1998 haltype, ARRAY_SIZE(sc->sc_haltype2q)); 1999 haltype, ARRAY_SIZE(sc->tx.hwq_map));
1999 return -1; 2000 return -1;
2000 } 2001 }
2001 qnum = sc->sc_haltype2q[haltype]; 2002 qnum = sc->tx.hwq_map[haltype];
2002 break; 2003 break;
2003 case ATH9K_TX_QUEUE_BEACON: 2004 case ATH9K_TX_QUEUE_BEACON:
2004 qnum = sc->sc_bhalq; 2005 qnum = sc->beacon.beaconq;
2005 break; 2006 break;
2006 case ATH9K_TX_QUEUE_CAB: 2007 case ATH9K_TX_QUEUE_CAB:
2007 qnum = sc->sc_cabq->axq_qnum; 2008 qnum = sc->beacon.cabq->axq_qnum;
2008 break; 2009 break;
2009 default: 2010 default:
2010 qnum = -1; 2011 qnum = -1;
@@ -2020,7 +2021,7 @@ struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb)
2020 int qnum; 2021 int qnum;
2021 2022
2022 qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc); 2023 qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc);
2023 txq = &sc->sc_txq[qnum]; 2024 txq = &sc->tx.txq[qnum];
2024 2025
2025 spin_lock_bh(&txq->axq_lock); 2026 spin_lock_bh(&txq->axq_lock);
2026 2027
@@ -2049,17 +2050,17 @@ int ath_txq_update(struct ath_softc *sc, int qnum,
2049 int error = 0; 2050 int error = 0;
2050 struct ath9k_tx_queue_info qi; 2051 struct ath9k_tx_queue_info qi;
2051 2052
2052 if (qnum == sc->sc_bhalq) { 2053 if (qnum == sc->beacon.beaconq) {
2053 /* 2054 /*
2054 * XXX: for beacon queue, we just save the parameter. 2055 * XXX: for beacon queue, we just save the parameter.
2055 * It will be picked up by ath_beaconq_config when 2056 * It will be picked up by ath_beaconq_config when
2056 * it's necessary. 2057 * it's necessary.
2057 */ 2058 */
2058 sc->sc_beacon_qi = *qinfo; 2059 sc->beacon.beacon_qi = *qinfo;
2059 return 0; 2060 return 0;
2060 } 2061 }
2061 2062
2062 ASSERT(sc->sc_txq[qnum].axq_qnum == qnum); 2063 ASSERT(sc->tx.txq[qnum].axq_qnum == qnum);
2063 2064
2064 ath9k_hw_get_txq_props(ah, qnum, &qi); 2065 ath9k_hw_get_txq_props(ah, qnum, &qi);
2065 qi.tqi_aifs = qinfo->tqi_aifs; 2066 qi.tqi_aifs = qinfo->tqi_aifs;
@@ -2082,7 +2083,7 @@ int ath_txq_update(struct ath_softc *sc, int qnum,
2082int ath_cabq_update(struct ath_softc *sc) 2083int ath_cabq_update(struct ath_softc *sc)
2083{ 2084{
2084 struct ath9k_tx_queue_info qi; 2085 struct ath9k_tx_queue_info qi;
2085 int qnum = sc->sc_cabq->axq_qnum; 2086 int qnum = sc->beacon.cabq->axq_qnum;
2086 struct ath_beacon_config conf; 2087 struct ath_beacon_config conf;
2087 2088
2088 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi); 2089 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
@@ -2116,7 +2117,7 @@ void ath_tx_tasklet(struct ath_softc *sc)
2116 */ 2117 */
2117 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 2118 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2118 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i))) 2119 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2119 ath_tx_processq(sc, &sc->sc_txq[i]); 2120 ath_tx_processq(sc, &sc->tx.txq[i]);
2120 } 2121 }
2121} 2122}
2122 2123
@@ -2148,9 +2149,9 @@ void ath_tx_draintxq(struct ath_softc *sc,
2148 list_del(&bf->list); 2149 list_del(&bf->list);
2149 spin_unlock_bh(&txq->axq_lock); 2150 spin_unlock_bh(&txq->axq_lock);
2150 2151
2151 spin_lock_bh(&sc->sc_txbuflock); 2152 spin_lock_bh(&sc->tx.txbuflock);
2152 list_add_tail(&bf->list, &sc->sc_txbuf); 2153 list_add_tail(&bf->list, &sc->tx.txbuf);
2153 spin_unlock_bh(&sc->sc_txbuflock); 2154 spin_unlock_bh(&sc->tx.txbuflock);
2154 continue; 2155 continue;
2155 } 2156 }
2156 2157
@@ -2188,9 +2189,9 @@ void ath_draintxq(struct ath_softc *sc, bool retry_tx)
2188 /* stop beacon queue. The beacon will be freed when 2189 /* stop beacon queue. The beacon will be freed when
2189 * we go to INIT state */ 2190 * we go to INIT state */
2190 if (!(sc->sc_flags & SC_OP_INVALID)) { 2191 if (!(sc->sc_flags & SC_OP_INVALID)) {
2191 (void) ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq); 2192 (void) ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2192 DPRINTF(sc, ATH_DBG_XMIT, "beacon queue %x\n", 2193 DPRINTF(sc, ATH_DBG_XMIT, "beacon queue %x\n",
2193 ath9k_hw_gettxbuf(sc->sc_ah, sc->sc_bhalq)); 2194 ath9k_hw_gettxbuf(sc->sc_ah, sc->beacon.beaconq));
2194 } 2195 }
2195 2196
2196 ath_drain_txdataq(sc, retry_tx); 2197 ath_drain_txdataq(sc, retry_tx);
@@ -2198,12 +2199,12 @@ void ath_draintxq(struct ath_softc *sc, bool retry_tx)
2198 2199
2199u32 ath_txq_depth(struct ath_softc *sc, int qnum) 2200u32 ath_txq_depth(struct ath_softc *sc, int qnum)
2200{ 2201{
2201 return sc->sc_txq[qnum].axq_depth; 2202 return sc->tx.txq[qnum].axq_depth;
2202} 2203}
2203 2204
2204u32 ath_txq_aggr_depth(struct ath_softc *sc, int qnum) 2205u32 ath_txq_aggr_depth(struct ath_softc *sc, int qnum)
2205{ 2206{
2206 return sc->sc_txq[qnum].axq_aggr_depth; 2207 return sc->tx.txq[qnum].axq_aggr_depth;
2207} 2208}
2208 2209
2209bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno) 2210bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno)
@@ -2284,7 +2285,7 @@ void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid
2284void ath_tx_aggr_teardown(struct ath_softc *sc, struct ath_node *an, u8 tid) 2285void ath_tx_aggr_teardown(struct ath_softc *sc, struct ath_node *an, u8 tid)
2285{ 2286{
2286 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid); 2287 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
2287 struct ath_txq *txq = &sc->sc_txq[txtid->ac->qnum]; 2288 struct ath_txq *txq = &sc->tx.txq[txtid->ac->qnum];
2288 struct ath_buf *bf; 2289 struct ath_buf *bf;
2289 struct list_head bf_head; 2290 struct list_head bf_head;
2290 INIT_LIST_HEAD(&bf_head); 2291 INIT_LIST_HEAD(&bf_head);
@@ -2405,7 +2406,7 @@ void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2405 /* 2406 /*
2406 * Init per tid tx state 2407 * Init per tid tx state
2407 */ 2408 */
2408 for (tidno = 0, tid = &an->an_aggr.tx.tid[tidno]; 2409 for (tidno = 0, tid = &an->tid[tidno];
2409 tidno < WME_NUM_TID; 2410 tidno < WME_NUM_TID;
2410 tidno++, tid++) { 2411 tidno++, tid++) {
2411 tid->an = an; 2412 tid->an = an;
@@ -2419,7 +2420,7 @@ void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2419 INIT_LIST_HEAD(&tid->buf_q); 2420 INIT_LIST_HEAD(&tid->buf_q);
2420 2421
2421 acno = TID_TO_WME_AC(tidno); 2422 acno = TID_TO_WME_AC(tidno);
2422 tid->ac = &an->an_aggr.tx.ac[acno]; 2423 tid->ac = &an->ac[acno];
2423 2424
2424 /* ADDBA state */ 2425 /* ADDBA state */
2425 tid->state &= ~AGGR_ADDBA_COMPLETE; 2426 tid->state &= ~AGGR_ADDBA_COMPLETE;
@@ -2430,7 +2431,7 @@ void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2430 /* 2431 /*
2431 * Init per ac tx state 2432 * Init per ac tx state
2432 */ 2433 */
2433 for (acno = 0, ac = &an->an_aggr.tx.ac[acno]; 2434 for (acno = 0, ac = &an->ac[acno];
2434 acno < WME_NUM_AC; acno++, ac++) { 2435 acno < WME_NUM_AC; acno++, ac++) {
2435 ac->sched = false; 2436 ac->sched = false;
2436 INIT_LIST_HEAD(&ac->tid_q); 2437 INIT_LIST_HEAD(&ac->tid_q);
@@ -2466,7 +2467,7 @@ void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2466 struct ath_txq *txq; 2467 struct ath_txq *txq;
2467 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 2468 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2468 if (ATH_TXQ_SETUP(sc, i)) { 2469 if (ATH_TXQ_SETUP(sc, i)) {
2469 txq = &sc->sc_txq[i]; 2470 txq = &sc->tx.txq[i];
2470 2471
2471 spin_lock(&txq->axq_lock); 2472 spin_lock(&txq->axq_lock);
2472 2473
@@ -2511,9 +2512,9 @@ void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb)
2511 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { 2512 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2512 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 2513 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2513 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) 2514 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2514 sc->seq_no += 0x10; 2515 sc->tx.seq_no += 0x10;
2515 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); 2516 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2516 hdr->seq_ctrl |= cpu_to_le16(sc->seq_no); 2517 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2517 } 2518 }
2518 2519
2519 /* Add the padding after the header if this is not already done */ 2520 /* Add the padding after the header if this is not already done */
@@ -2529,7 +2530,7 @@ void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb)
2529 memmove(skb->data, skb->data + padsize, hdrlen); 2530 memmove(skb->data, skb->data + padsize, hdrlen);
2530 } 2531 }
2531 2532
2532 txctl.txq = sc->sc_cabq; 2533 txctl.txq = sc->beacon.cabq;
2533 2534
2534 DPRINTF(sc, ATH_DBG_XMIT, "transmitting CABQ packet, skb: %p\n", skb); 2535 DPRINTF(sc, ATH_DBG_XMIT, "transmitting CABQ packet, skb: %p\n", skb);
2535 2536
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-20 11:29:16 -0400