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path: root/drivers/net/wireless/ath9k/main.c
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Diffstat (limited to 'drivers/net/wireless/ath9k/main.c')
-rw-r--r--drivers/net/wireless/ath9k/main.c92
1 files changed, 46 insertions, 46 deletions
diff --git a/drivers/net/wireless/ath9k/main.c b/drivers/net/wireless/ath9k/main.c
index a50f989abd6c..fc3460f8f7fc 100644
--- a/drivers/net/wireless/ath9k/main.c
+++ b/drivers/net/wireless/ath9k/main.c
@@ -267,7 +267,7 @@ static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
267 267
268 DPRINTF(sc, ATH_DBG_CONFIG, 268 DPRINTF(sc, ATH_DBG_CONFIG,
269 "(%u MHz) -> (%u MHz), chanwidth: %d\n", 269 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
270 sc->sc_ah->ah_curchan->channel, 270 sc->sc_ah->curchan->channel,
271 channel->center_freq, sc->tx_chan_width); 271 channel->center_freq, sc->tx_chan_width);
272 272
273 spin_lock_bh(&sc->sc_resetlock); 273 spin_lock_bh(&sc->sc_resetlock);
@@ -363,30 +363,30 @@ static void ath_ani_calibrate(unsigned long data)
363 /* Call ANI routine if necessary */ 363 /* Call ANI routine if necessary */
364 if (aniflag) 364 if (aniflag)
365 ath9k_hw_ani_monitor(ah, &sc->nodestats, 365 ath9k_hw_ani_monitor(ah, &sc->nodestats,
366 ah->ah_curchan); 366 ah->curchan);
367 367
368 /* Perform calibration if necessary */ 368 /* Perform calibration if necessary */
369 if (longcal || shortcal) { 369 if (longcal || shortcal) {
370 bool iscaldone = false; 370 bool iscaldone = false;
371 371
372 if (ath9k_hw_calibrate(ah, ah->ah_curchan, 372 if (ath9k_hw_calibrate(ah, ah->curchan,
373 sc->rx_chainmask, longcal, 373 sc->rx_chainmask, longcal,
374 &iscaldone)) { 374 &iscaldone)) {
375 if (longcal) 375 if (longcal)
376 sc->ani.noise_floor = 376 sc->ani.noise_floor =
377 ath9k_hw_getchan_noise(ah, 377 ath9k_hw_getchan_noise(ah,
378 ah->ah_curchan); 378 ah->curchan);
379 379
380 DPRINTF(sc, ATH_DBG_ANI, 380 DPRINTF(sc, ATH_DBG_ANI,
381 "calibrate chan %u/%x nf: %d\n", 381 "calibrate chan %u/%x nf: %d\n",
382 ah->ah_curchan->channel, 382 ah->curchan->channel,
383 ah->ah_curchan->channelFlags, 383 ah->curchan->channelFlags,
384 sc->ani.noise_floor); 384 sc->ani.noise_floor);
385 } else { 385 } else {
386 DPRINTF(sc, ATH_DBG_ANY, 386 DPRINTF(sc, ATH_DBG_ANY,
387 "calibrate chan %u/%x failed\n", 387 "calibrate chan %u/%x failed\n",
388 ah->ah_curchan->channel, 388 ah->curchan->channel,
389 ah->ah_curchan->channelFlags); 389 ah->curchan->channelFlags);
390 } 390 }
391 sc->ani.caldone = iscaldone; 391 sc->ani.caldone = iscaldone;
392 } 392 }
@@ -398,7 +398,7 @@ static void ath_ani_calibrate(unsigned long data)
398 * short calibration and long calibration. 398 * short calibration and long calibration.
399 */ 399 */
400 cal_interval = ATH_LONG_CALINTERVAL; 400 cal_interval = ATH_LONG_CALINTERVAL;
401 if (sc->sc_ah->ah_config.enable_ani) 401 if (sc->sc_ah->config.enable_ani)
402 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL); 402 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
403 if (!sc->ani.caldone) 403 if (!sc->ani.caldone)
404 cal_interval = min(cal_interval, (u32)ATH_SHORT_CALINTERVAL); 404 cal_interval = min(cal_interval, (u32)ATH_SHORT_CALINTERVAL);
@@ -416,9 +416,9 @@ static void ath_update_chainmask(struct ath_softc *sc, int is_ht)
416{ 416{
417 sc->sc_flags |= SC_OP_CHAINMASK_UPDATE; 417 sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
418 if (is_ht || 418 if (is_ht ||
419 (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) { 419 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
420 sc->tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask; 420 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
421 sc->rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask; 421 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
422 } else { 422 } else {
423 sc->tx_chainmask = 1; 423 sc->tx_chainmask = 1;
424 sc->rx_chainmask = 1; 424 sc->rx_chainmask = 1;
@@ -564,7 +564,7 @@ irqreturn_t ath_isr(int irq, void *dev)
564 ath9k_hw_set_interrupts(ah, sc->imask); 564 ath9k_hw_set_interrupts(ah, sc->imask);
565 } 565 }
566 if (status & ATH9K_INT_TIM_TIMER) { 566 if (status & ATH9K_INT_TIM_TIMER) {
567 if (!(ah->ah_caps.hw_caps & 567 if (!(ah->caps.hw_caps &
568 ATH9K_HW_CAP_AUTOSLEEP)) { 568 ATH9K_HW_CAP_AUTOSLEEP)) {
569 /* Clear RxAbort bit so that we can 569 /* Clear RxAbort bit so that we can
570 * receive frames */ 570 * receive frames */
@@ -1098,7 +1098,7 @@ static void ath_radio_enable(struct ath_softc *sc)
1098 ath9k_ps_wakeup(sc); 1098 ath9k_ps_wakeup(sc);
1099 spin_lock_bh(&sc->sc_resetlock); 1099 spin_lock_bh(&sc->sc_resetlock);
1100 1100
1101 r = ath9k_hw_reset(ah, ah->ah_curchan, false); 1101 r = ath9k_hw_reset(ah, ah->curchan, false);
1102 1102
1103 if (r) { 1103 if (r) {
1104 DPRINTF(sc, ATH_DBG_FATAL, 1104 DPRINTF(sc, ATH_DBG_FATAL,
@@ -1151,7 +1151,7 @@ static void ath_radio_disable(struct ath_softc *sc)
1151 ath_flushrecv(sc); /* flush recv queue */ 1151 ath_flushrecv(sc); /* flush recv queue */
1152 1152
1153 spin_lock_bh(&sc->sc_resetlock); 1153 spin_lock_bh(&sc->sc_resetlock);
1154 r = ath9k_hw_reset(ah, ah->ah_curchan, false); 1154 r = ath9k_hw_reset(ah, ah->curchan, false);
1155 if (r) { 1155 if (r) {
1156 DPRINTF(sc, ATH_DBG_FATAL, 1156 DPRINTF(sc, ATH_DBG_FATAL,
1157 "Unable to reset channel %u (%uMhz) " 1157 "Unable to reset channel %u (%uMhz) "
@@ -1169,8 +1169,8 @@ static bool ath_is_rfkill_set(struct ath_softc *sc)
1169{ 1169{
1170 struct ath_hw *ah = sc->sc_ah; 1170 struct ath_hw *ah = sc->sc_ah;
1171 1171
1172 return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) == 1172 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1173 ah->ah_rfkill_polarity; 1173 ah->rfkill_polarity;
1174} 1174}
1175 1175
1176/* h/w rfkill poll function */ 1176/* h/w rfkill poll function */
@@ -1267,7 +1267,7 @@ static int ath_init_sw_rfkill(struct ath_softc *sc)
1267/* Deinitialize rfkill */ 1267/* Deinitialize rfkill */
1268static void ath_deinit_rfkill(struct ath_softc *sc) 1268static void ath_deinit_rfkill(struct ath_softc *sc)
1269{ 1269{
1270 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 1270 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1271 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll); 1271 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1272 1272
1273 if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) { 1273 if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
@@ -1279,7 +1279,7 @@ static void ath_deinit_rfkill(struct ath_softc *sc)
1279 1279
1280static int ath_start_rfkill_poll(struct ath_softc *sc) 1280static int ath_start_rfkill_poll(struct ath_softc *sc)
1281{ 1281{
1282 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 1282 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1283 queue_delayed_work(sc->hw->workqueue, 1283 queue_delayed_work(sc->hw->workqueue,
1284 &sc->rf_kill.rfkill_poll, 0); 1284 &sc->rf_kill.rfkill_poll, 0);
1285 1285
@@ -1380,7 +1380,7 @@ static int ath_init(u16 devid, struct ath_softc *sc)
1380 sc->sc_ah = ah; 1380 sc->sc_ah = ah;
1381 1381
1382 /* Get the hardware key cache size. */ 1382 /* Get the hardware key cache size. */
1383 sc->keymax = ah->ah_caps.keycache_size; 1383 sc->keymax = ah->caps.keycache_size;
1384 if (sc->keymax > ATH_KEYMAX) { 1384 if (sc->keymax > ATH_KEYMAX) {
1385 DPRINTF(sc, ATH_DBG_KEYCACHE, 1385 DPRINTF(sc, ATH_DBG_KEYCACHE,
1386 "Warning, using only %u entries in %u key cache\n", 1386 "Warning, using only %u entries in %u key cache\n",
@@ -1399,7 +1399,7 @@ static int ath_init(u16 devid, struct ath_softc *sc)
1399 goto bad; 1399 goto bad;
1400 1400
1401 /* default to MONITOR mode */ 1401 /* default to MONITOR mode */
1402 sc->sc_ah->ah_opmode = NL80211_IFTYPE_MONITOR; 1402 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1403 1403
1404 /* Setup rate tables */ 1404 /* Setup rate tables */
1405 1405
@@ -1502,18 +1502,18 @@ static int ath_init(u16 devid, struct ath_softc *sc)
1502 sc->config.txpowlimit = ATH_TXPOWER_MAX; 1502 sc->config.txpowlimit = ATH_TXPOWER_MAX;
1503 1503
1504 /* 11n Capabilities */ 1504 /* 11n Capabilities */
1505 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) { 1505 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1506 sc->sc_flags |= SC_OP_TXAGGR; 1506 sc->sc_flags |= SC_OP_TXAGGR;
1507 sc->sc_flags |= SC_OP_RXAGGR; 1507 sc->sc_flags |= SC_OP_RXAGGR;
1508 } 1508 }
1509 1509
1510 sc->tx_chainmask = ah->ah_caps.tx_chainmask; 1510 sc->tx_chainmask = ah->caps.tx_chainmask;
1511 sc->rx_chainmask = ah->ah_caps.rx_chainmask; 1511 sc->rx_chainmask = ah->caps.rx_chainmask;
1512 1512
1513 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL); 1513 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1514 sc->rx.defant = ath9k_hw_getdefantenna(ah); 1514 sc->rx.defant = ath9k_hw_getdefantenna(ah);
1515 1515
1516 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) { 1516 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
1517 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN); 1517 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
1518 ATH_SET_VIF_BSSID_MASK(sc->bssidmask); 1518 ATH_SET_VIF_BSSID_MASK(sc->bssidmask);
1519 ath9k_hw_setbssidmask(sc); 1519 ath9k_hw_setbssidmask(sc);
@@ -1537,7 +1537,7 @@ static int ath_init(u16 devid, struct ath_softc *sc)
1537 sc->sbands[IEEE80211_BAND_2GHZ].n_channels = 1537 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1538 ARRAY_SIZE(ath9k_2ghz_chantable); 1538 ARRAY_SIZE(ath9k_2ghz_chantable);
1539 1539
1540 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) { 1540 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
1541 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable; 1541 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1542 sc->sbands[IEEE80211_BAND_5GHZ].bitrates = 1542 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1543 sc->rates[IEEE80211_BAND_5GHZ]; 1543 sc->rates[IEEE80211_BAND_5GHZ];
@@ -1546,7 +1546,7 @@ static int ath_init(u16 devid, struct ath_softc *sc)
1546 ARRAY_SIZE(ath9k_5ghz_chantable); 1546 ARRAY_SIZE(ath9k_5ghz_chantable);
1547 } 1547 }
1548 1548
1549 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_BT_COEX) 1549 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
1550 ath9k_hw_btcoex_enable(sc->sc_ah); 1550 ath9k_hw_btcoex_enable(sc->sc_ah);
1551 1551
1552 return 0; 1552 return 0;
@@ -1603,14 +1603,14 @@ int ath_attach(u16 devid, struct ath_softc *sc)
1603 1603
1604 hw->rate_control_algorithm = "ath9k_rate_control"; 1604 hw->rate_control_algorithm = "ath9k_rate_control";
1605 1605
1606 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) { 1606 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1607 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap); 1607 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1608 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) 1608 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1609 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap); 1609 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1610 } 1610 }
1611 1611
1612 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ]; 1612 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
1613 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) 1613 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1614 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = 1614 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1615 &sc->sbands[IEEE80211_BAND_5GHZ]; 1615 &sc->sbands[IEEE80211_BAND_5GHZ];
1616 1616
@@ -1625,7 +1625,7 @@ int ath_attach(u16 devid, struct ath_softc *sc)
1625 1625
1626#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 1626#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1627 /* Initialze h/w Rfkill */ 1627 /* Initialze h/w Rfkill */
1628 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 1628 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1629 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll); 1629 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1630 1630
1631 /* Initialize s/w rfkill */ 1631 /* Initialize s/w rfkill */
@@ -1681,7 +1681,7 @@ int ath_reset(struct ath_softc *sc, bool retry_tx)
1681 ath_flushrecv(sc); 1681 ath_flushrecv(sc);
1682 1682
1683 spin_lock_bh(&sc->sc_resetlock); 1683 spin_lock_bh(&sc->sc_resetlock);
1684 r = ath9k_hw_reset(ah, sc->sc_ah->ah_curchan, false); 1684 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1685 if (r) 1685 if (r)
1686 DPRINTF(sc, ATH_DBG_FATAL, 1686 DPRINTF(sc, ATH_DBG_FATAL,
1687 "Unable to reset hardware; reset status %u\n", r); 1687 "Unable to reset hardware; reset status %u\n", r);
@@ -1755,7 +1755,7 @@ int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1755 * descriptors that cross the 4K page boundary. Assume 1755 * descriptors that cross the 4K page boundary. Assume
1756 * one skipped descriptor per 4K page. 1756 * one skipped descriptor per 4K page.
1757 */ 1757 */
1758 if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) { 1758 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1759 u32 ndesc_skipped = 1759 u32 ndesc_skipped =
1760 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len); 1760 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1761 u32 dma_len; 1761 u32 dma_len;
@@ -1795,7 +1795,7 @@ int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1795 bf->bf_desc = ds; 1795 bf->bf_desc = ds;
1796 bf->bf_daddr = DS2PHYS(dd, ds); 1796 bf->bf_daddr = DS2PHYS(dd, ds);
1797 1797
1798 if (!(sc->sc_ah->ah_caps.hw_caps & 1798 if (!(sc->sc_ah->caps.hw_caps &
1799 ATH9K_HW_CAP_4KB_SPLITTRANS)) { 1799 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1800 /* 1800 /*
1801 * Skip descriptor addresses which can cause 4KB 1801 * Skip descriptor addresses which can cause 4KB
@@ -1939,7 +1939,7 @@ static int ath9k_start(struct ieee80211_hw *hw)
1939 1939
1940 pos = curchan->hw_value; 1940 pos = curchan->hw_value;
1941 1941
1942 init_channel = &sc->sc_ah->ah_channels[pos]; 1942 init_channel = &sc->sc_ah->channels[pos];
1943 ath9k_update_ichannel(sc, init_channel); 1943 ath9k_update_ichannel(sc, init_channel);
1944 1944
1945 /* Reset SERDES registers */ 1945 /* Reset SERDES registers */
@@ -1989,10 +1989,10 @@ static int ath9k_start(struct ieee80211_hw *hw)
1989 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN 1989 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1990 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL; 1990 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1991 1991
1992 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT) 1992 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
1993 sc->imask |= ATH9K_INT_GTT; 1993 sc->imask |= ATH9K_INT_GTT;
1994 1994
1995 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) 1995 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
1996 sc->imask |= ATH9K_INT_CST; 1996 sc->imask |= ATH9K_INT_CST;
1997 1997
1998 ath_cache_conf_rate(sc, &hw->conf); 1998 ath_cache_conf_rate(sc, &hw->conf);
@@ -2092,7 +2092,7 @@ static void ath9k_stop(struct ieee80211_hw *hw)
2092 sc->rx.rxlink = NULL; 2092 sc->rx.rxlink = NULL;
2093 2093
2094#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 2094#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2095 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 2095 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2096 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll); 2096 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2097#endif 2097#endif
2098 /* disable HAL and put h/w to sleep */ 2098 /* disable HAL and put h/w to sleep */
@@ -2149,7 +2149,7 @@ static int ath9k_add_interface(struct ieee80211_hw *hw,
2149 sc->nvifs++; 2149 sc->nvifs++;
2150 2150
2151 /* Set the device opmode */ 2151 /* Set the device opmode */
2152 sc->sc_ah->ah_opmode = ic_opmode; 2152 sc->sc_ah->opmode = ic_opmode;
2153 2153
2154 /* 2154 /*
2155 * Enable MIB interrupts when there are hardware phy counters. 2155 * Enable MIB interrupts when there are hardware phy counters.
@@ -2165,7 +2165,7 @@ static int ath9k_add_interface(struct ieee80211_hw *hw,
2165 * that does, if not overridden by configuration, 2165 * that does, if not overridden by configuration,
2166 * enable the TIM interrupt when operating as station. 2166 * enable the TIM interrupt when operating as station.
2167 */ 2167 */
2168 if ((sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) && 2168 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
2169 (conf->type == NL80211_IFTYPE_STATION) && 2169 (conf->type == NL80211_IFTYPE_STATION) &&
2170 !sc->config.swBeaconProcess) 2170 !sc->config.swBeaconProcess)
2171 sc->imask |= ATH9K_INT_TIM; 2171 sc->imask |= ATH9K_INT_TIM;
@@ -2198,8 +2198,8 @@ static void ath9k_remove_interface(struct ieee80211_hw *hw,
2198 del_timer_sync(&sc->ani.timer); 2198 del_timer_sync(&sc->ani.timer);
2199 2199
2200 /* Reclaim beacon resources */ 2200 /* Reclaim beacon resources */
2201 if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP || 2201 if (sc->sc_ah->opmode == NL80211_IFTYPE_AP ||
2202 sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) { 2202 sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) {
2203 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); 2203 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2204 ath_beacon_return(sc, avp); 2204 ath_beacon_return(sc, avp);
2205 } 2205 }
@@ -2248,11 +2248,11 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2248 curchan->center_freq); 2248 curchan->center_freq);
2249 2249
2250 /* XXX: remove me eventualy */ 2250 /* XXX: remove me eventualy */
2251 ath9k_update_ichannel(sc, &sc->sc_ah->ah_channels[pos]); 2251 ath9k_update_ichannel(sc, &sc->sc_ah->channels[pos]);
2252 2252
2253 ath_update_chainmask(sc, conf_is_ht(conf)); 2253 ath_update_chainmask(sc, conf_is_ht(conf));
2254 2254
2255 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0) { 2255 if (ath_set_channel(sc, &sc->sc_ah->channels[pos]) < 0) {
2256 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n"); 2256 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2257 mutex_unlock(&sc->mutex); 2257 mutex_unlock(&sc->mutex);
2258 return -EINVAL; 2258 return -EINVAL;
@@ -2280,8 +2280,8 @@ static int ath9k_config_interface(struct ieee80211_hw *hw,
2280 /* TODO: Need to decide which hw opmode to use for multi-interface 2280 /* TODO: Need to decide which hw opmode to use for multi-interface
2281 * cases */ 2281 * cases */
2282 if (vif->type == NL80211_IFTYPE_AP && 2282 if (vif->type == NL80211_IFTYPE_AP &&
2283 ah->ah_opmode != NL80211_IFTYPE_AP) { 2283 ah->opmode != NL80211_IFTYPE_AP) {
2284 ah->ah_opmode = NL80211_IFTYPE_STATION; 2284 ah->opmode = NL80211_IFTYPE_STATION;
2285 ath9k_hw_setopmode(ah); 2285 ath9k_hw_setopmode(ah);
2286 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN); 2286 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2287 sc->curaid = 0; 2287 sc->curaid = 0;