diff options
Diffstat (limited to 'drivers/net/wireless/ath9k/mac.c')
-rw-r--r-- | drivers/net/wireless/ath9k/mac.c | 138 |
1 files changed, 26 insertions, 112 deletions
diff --git a/drivers/net/wireless/ath9k/mac.c b/drivers/net/wireless/ath9k/mac.c index 36955e0b1849..a4e98986dbcd 100644 --- a/drivers/net/wireless/ath9k/mac.c +++ b/drivers/net/wireless/ath9k/mac.c | |||
@@ -25,10 +25,10 @@ static void ath9k_hw_set_txq_interrupts(struct ath_hal *ah, | |||
25 | struct ath_hal_5416 *ahp = AH5416(ah); | 25 | struct ath_hal_5416 *ahp = AH5416(ah); |
26 | 26 | ||
27 | DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, | 27 | DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, |
28 | "%s: tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n", | 28 | "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n", |
29 | __func__, ahp->ah_txOkInterruptMask, | 29 | ahp->ah_txOkInterruptMask, ahp->ah_txErrInterruptMask, |
30 | ahp->ah_txErrInterruptMask, ahp->ah_txDescInterruptMask, | 30 | ahp->ah_txDescInterruptMask, ahp->ah_txEolInterruptMask, |
31 | ahp->ah_txEolInterruptMask, ahp->ah_txUrnInterruptMask); | 31 | ahp->ah_txUrnInterruptMask); |
32 | 32 | ||
33 | REG_WRITE(ah, AR_IMR_S0, | 33 | REG_WRITE(ah, AR_IMR_S0, |
34 | SM(ahp->ah_txOkInterruptMask, AR_IMR_S0_QCU_TXOK) | 34 | SM(ahp->ah_txOkInterruptMask, AR_IMR_S0_QCU_TXOK) |
@@ -40,78 +40,6 @@ static void ath9k_hw_set_txq_interrupts(struct ath_hal *ah, | |||
40 | AR_IMR_S2_QCU_TXURN, ahp->ah_txUrnInterruptMask); | 40 | AR_IMR_S2_QCU_TXURN, ahp->ah_txUrnInterruptMask); |
41 | } | 41 | } |
42 | 42 | ||
43 | void ath9k_hw_dmaRegDump(struct ath_hal *ah) | ||
44 | { | ||
45 | u32 val[ATH9K_NUM_DMA_DEBUG_REGS]; | ||
46 | int qcuOffset = 0, dcuOffset = 0; | ||
47 | u32 *qcuBase = &val[0], *dcuBase = &val[4]; | ||
48 | int i; | ||
49 | |||
50 | REG_WRITE(ah, AR_MACMISC, | ||
51 | ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) | | ||
52 | (AR_MACMISC_MISC_OBS_BUS_1 << | ||
53 | AR_MACMISC_MISC_OBS_BUS_MSB_S))); | ||
54 | |||
55 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "Raw DMA Debug values:\n"); | ||
56 | |||
57 | for (i = 0; i < ATH9K_NUM_DMA_DEBUG_REGS; i++) { | ||
58 | if (i % 4 == 0) | ||
59 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "\n"); | ||
60 | |||
61 | val[i] = REG_READ(ah, AR_DMADBG_0 + (i * sizeof(u32))); | ||
62 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "%d: %08x ", i, val[i]); | ||
63 | } | ||
64 | |||
65 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "\n\n"); | ||
66 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, | ||
67 | "Num QCU: chain_st fsp_ok fsp_st DCU: chain_st\n"); | ||
68 | |||
69 | for (i = 0; i < ATH9K_NUM_QUEUES; | ||
70 | i++, qcuOffset += 4, dcuOffset += 5) { | ||
71 | if (i == 8) { | ||
72 | qcuOffset = 0; | ||
73 | qcuBase++; | ||
74 | } | ||
75 | |||
76 | if (i == 6) { | ||
77 | dcuOffset = 0; | ||
78 | dcuBase++; | ||
79 | } | ||
80 | |||
81 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, | ||
82 | "%2d %2x %1x %2x %2x\n", | ||
83 | i, (*qcuBase & (0x7 << qcuOffset)) >> qcuOffset, | ||
84 | (*qcuBase & (0x8 << qcuOffset)) >> (qcuOffset + 3), | ||
85 | val[2] & (0x7 << (i * 3)) >> (i * 3), | ||
86 | (*dcuBase & (0x1f << dcuOffset)) >> dcuOffset); | ||
87 | } | ||
88 | |||
89 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "\n"); | ||
90 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, | ||
91 | "qcu_stitch state: %2x qcu_fetch state: %2x\n", | ||
92 | (val[3] & 0x003c0000) >> 18, (val[3] & 0x03c00000) >> 22); | ||
93 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, | ||
94 | "qcu_complete state: %2x dcu_complete state: %2x\n", | ||
95 | (val[3] & 0x1c000000) >> 26, (val[6] & 0x3)); | ||
96 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, | ||
97 | "dcu_arb state: %2x dcu_fp state: %2x\n", | ||
98 | (val[5] & 0x06000000) >> 25, (val[5] & 0x38000000) >> 27); | ||
99 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, | ||
100 | "chan_idle_dur: %3d chan_idle_dur_valid: %1d\n", | ||
101 | (val[6] & 0x000003fc) >> 2, (val[6] & 0x00000400) >> 10); | ||
102 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, | ||
103 | "txfifo_valid_0: %1d txfifo_valid_1: %1d\n", | ||
104 | (val[6] & 0x00000800) >> 11, (val[6] & 0x00001000) >> 12); | ||
105 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, | ||
106 | "txfifo_dcu_num_0: %2d txfifo_dcu_num_1: %2d\n", | ||
107 | (val[6] & 0x0001e000) >> 13, (val[6] & 0x001e0000) >> 17); | ||
108 | |||
109 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "pcu observe 0x%x \n", | ||
110 | REG_READ(ah, AR_OBS_BUS_1)); | ||
111 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, | ||
112 | "AR_CR 0x%x \n", REG_READ(ah, AR_CR)); | ||
113 | } | ||
114 | |||
115 | u32 ath9k_hw_gettxbuf(struct ath_hal *ah, u32 q) | 43 | u32 ath9k_hw_gettxbuf(struct ath_hal *ah, u32 q) |
116 | { | 44 | { |
117 | return REG_READ(ah, AR_QTXDP(q)); | 45 | return REG_READ(ah, AR_QTXDP(q)); |
@@ -126,7 +54,7 @@ bool ath9k_hw_puttxbuf(struct ath_hal *ah, u32 q, u32 txdp) | |||
126 | 54 | ||
127 | bool ath9k_hw_txstart(struct ath_hal *ah, u32 q) | 55 | bool ath9k_hw_txstart(struct ath_hal *ah, u32 q) |
128 | { | 56 | { |
129 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: queue %u\n", __func__, q); | 57 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "queue %u\n", q); |
130 | 58 | ||
131 | REG_WRITE(ah, AR_Q_TXE, 1 << q); | 59 | REG_WRITE(ah, AR_Q_TXE, 1 << q); |
132 | 60 | ||
@@ -207,9 +135,8 @@ bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q) | |||
207 | break; | 135 | break; |
208 | 136 | ||
209 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, | 137 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, |
210 | "%s: TSF have moved while trying to set " | 138 | "TSF have moved while trying to set " |
211 | "quiet time TSF: 0x%08x\n", | 139 | "quiet time TSF: 0x%08x\n", tsfLow); |
212 | __func__, tsfLow); | ||
213 | } | 140 | } |
214 | 141 | ||
215 | REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); | 142 | REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); |
@@ -222,9 +149,8 @@ bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q) | |||
222 | while (ath9k_hw_numtxpending(ah, q)) { | 149 | while (ath9k_hw_numtxpending(ah, q)) { |
223 | if ((--wait) == 0) { | 150 | if ((--wait) == 0) { |
224 | DPRINTF(ah->ah_sc, ATH_DBG_XMIT, | 151 | DPRINTF(ah->ah_sc, ATH_DBG_XMIT, |
225 | "%s: Failed to stop Tx DMA in 100 " | 152 | "Failed to stop Tx DMA in 100 " |
226 | "msec after killing last frame\n", | 153 | "msec after killing last frame\n"); |
227 | __func__); | ||
228 | break; | 154 | break; |
229 | } | 155 | } |
230 | udelay(100); | 156 | udelay(100); |
@@ -523,19 +449,17 @@ bool ath9k_hw_set_txq_props(struct ath_hal *ah, int q, | |||
523 | struct ath9k_tx_queue_info *qi; | 449 | struct ath9k_tx_queue_info *qi; |
524 | 450 | ||
525 | if (q >= pCap->total_queues) { | 451 | if (q >= pCap->total_queues) { |
526 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n", | 452 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "invalid queue num %u\n", q); |
527 | __func__, q); | ||
528 | return false; | 453 | return false; |
529 | } | 454 | } |
530 | 455 | ||
531 | qi = &ahp->ah_txq[q]; | 456 | qi = &ahp->ah_txq[q]; |
532 | if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { | 457 | if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { |
533 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue\n", | 458 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue\n"); |
534 | __func__); | ||
535 | return false; | 459 | return false; |
536 | } | 460 | } |
537 | 461 | ||
538 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: queue %p\n", __func__, qi); | 462 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "queue %p\n", qi); |
539 | 463 | ||
540 | qi->tqi_ver = qinfo->tqi_ver; | 464 | qi->tqi_ver = qinfo->tqi_ver; |
541 | qi->tqi_subtype = qinfo->tqi_subtype; | 465 | qi->tqi_subtype = qinfo->tqi_subtype; |
@@ -593,15 +517,13 @@ bool ath9k_hw_get_txq_props(struct ath_hal *ah, int q, | |||
593 | struct ath9k_tx_queue_info *qi; | 517 | struct ath9k_tx_queue_info *qi; |
594 | 518 | ||
595 | if (q >= pCap->total_queues) { | 519 | if (q >= pCap->total_queues) { |
596 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n", | 520 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "invalid queue num %u\n", q); |
597 | __func__, q); | ||
598 | return false; | 521 | return false; |
599 | } | 522 | } |
600 | 523 | ||
601 | qi = &ahp->ah_txq[q]; | 524 | qi = &ahp->ah_txq[q]; |
602 | if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { | 525 | if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { |
603 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue\n", | 526 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue\n"); |
604 | __func__); | ||
605 | return false; | 527 | return false; |
606 | } | 528 | } |
607 | 529 | ||
@@ -651,22 +573,21 @@ int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type, | |||
651 | break; | 573 | break; |
652 | if (q == pCap->total_queues) { | 574 | if (q == pCap->total_queues) { |
653 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, | 575 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, |
654 | "%s: no available tx queue\n", __func__); | 576 | "no available tx queue\n"); |
655 | return -1; | 577 | return -1; |
656 | } | 578 | } |
657 | break; | 579 | break; |
658 | default: | 580 | default: |
659 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: bad tx queue type %u\n", | 581 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "bad tx queue type %u\n", type); |
660 | __func__, type); | ||
661 | return -1; | 582 | return -1; |
662 | } | 583 | } |
663 | 584 | ||
664 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: queue %u\n", __func__, q); | 585 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "queue %u\n", q); |
665 | 586 | ||
666 | qi = &ahp->ah_txq[q]; | 587 | qi = &ahp->ah_txq[q]; |
667 | if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) { | 588 | if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) { |
668 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, | 589 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, |
669 | "%s: tx queue %u already active\n", __func__, q); | 590 | "tx queue %u already active\n", q); |
670 | return -1; | 591 | return -1; |
671 | } | 592 | } |
672 | memset(qi, 0, sizeof(struct ath9k_tx_queue_info)); | 593 | memset(qi, 0, sizeof(struct ath9k_tx_queue_info)); |
@@ -697,19 +618,16 @@ bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q) | |||
697 | struct ath9k_tx_queue_info *qi; | 618 | struct ath9k_tx_queue_info *qi; |
698 | 619 | ||
699 | if (q >= pCap->total_queues) { | 620 | if (q >= pCap->total_queues) { |
700 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n", | 621 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "invalid queue num %u\n", q); |
701 | __func__, q); | ||
702 | return false; | 622 | return false; |
703 | } | 623 | } |
704 | qi = &ahp->ah_txq[q]; | 624 | qi = &ahp->ah_txq[q]; |
705 | if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { | 625 | if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { |
706 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue %u\n", | 626 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue %u\n", q); |
707 | __func__, q); | ||
708 | return false; | 627 | return false; |
709 | } | 628 | } |
710 | 629 | ||
711 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: release queue %u\n", | 630 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "release queue %u\n", q); |
712 | __func__, q); | ||
713 | 631 | ||
714 | qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE; | 632 | qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE; |
715 | ahp->ah_txOkInterruptMask &= ~(1 << q); | 633 | ahp->ah_txOkInterruptMask &= ~(1 << q); |
@@ -731,19 +649,17 @@ bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q) | |||
731 | u32 cwMin, chanCwMin, value; | 649 | u32 cwMin, chanCwMin, value; |
732 | 650 | ||
733 | if (q >= pCap->total_queues) { | 651 | if (q >= pCap->total_queues) { |
734 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n", | 652 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "invalid queue num %u\n", q); |
735 | __func__, q); | ||
736 | return false; | 653 | return false; |
737 | } | 654 | } |
738 | 655 | ||
739 | qi = &ahp->ah_txq[q]; | 656 | qi = &ahp->ah_txq[q]; |
740 | if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { | 657 | if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { |
741 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue %u\n", | 658 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue %u\n", q); |
742 | __func__, q); | ||
743 | return true; | 659 | return true; |
744 | } | 660 | } |
745 | 661 | ||
746 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: reset queue %u\n", __func__, q); | 662 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "reset queue %u\n", q); |
747 | 663 | ||
748 | if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) { | 664 | if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) { |
749 | if (chan && IS_CHAN_B(chan)) | 665 | if (chan && IS_CHAN_B(chan)) |
@@ -976,8 +892,7 @@ bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set) | |||
976 | 892 | ||
977 | reg = REG_READ(ah, AR_OBS_BUS_1); | 893 | reg = REG_READ(ah, AR_OBS_BUS_1); |
978 | DPRINTF(ah->ah_sc, ATH_DBG_FATAL, | 894 | DPRINTF(ah->ah_sc, ATH_DBG_FATAL, |
979 | "%s: rx failed to go idle in 10 ms RXSM=0x%x\n", | 895 | "rx failed to go idle in 10 ms RXSM=0x%x\n", reg); |
980 | __func__, reg); | ||
981 | 896 | ||
982 | return false; | 897 | return false; |
983 | } | 898 | } |
@@ -1022,9 +937,8 @@ bool ath9k_hw_stopdmarecv(struct ath_hal *ah) | |||
1022 | 937 | ||
1023 | if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE, 0)) { | 938 | if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE, 0)) { |
1024 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, | 939 | DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, |
1025 | "%s: dma failed to stop in 10ms\n" | 940 | "dma failed to stop in 10ms\n" |
1026 | "AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n", | 941 | "AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n", |
1027 | __func__, | ||
1028 | REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW)); | 942 | REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW)); |
1029 | return false; | 943 | return false; |
1030 | } else { | 944 | } else { |