aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/wireless/ath9k/hw.h
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/net/wireless/ath9k/hw.h')
-rw-r--r--drivers/net/wireless/ath9k/hw.h1568
1 files changed, 560 insertions, 1008 deletions
diff --git a/drivers/net/wireless/ath9k/hw.h b/drivers/net/wireless/ath9k/hw.h
index 087c5718707b..82111636c693 100644
--- a/drivers/net/wireless/ath9k/hw.h
+++ b/drivers/net/wireless/ath9k/hw.h
@@ -19,1075 +19,627 @@
19 19
20#include <linux/if_ether.h> 20#include <linux/if_ether.h>
21#include <linux/delay.h> 21#include <linux/delay.h>
22#include <linux/io.h>
23
24#include "mac.h"
25#include "ani.h"
26#include "eeprom.h"
27#include "calib.h"
28#include "regd.h"
29#include "reg.h"
30#include "phy.h"
31
32#define ATHEROS_VENDOR_ID 0x168c
33#define AR5416_DEVID_PCI 0x0023
34#define AR5416_DEVID_PCIE 0x0024
35#define AR9160_DEVID_PCI 0x0027
36#define AR9280_DEVID_PCI 0x0029
37#define AR9280_DEVID_PCIE 0x002a
38#define AR9285_DEVID_PCIE 0x002b
39#define AR5416_AR9100_DEVID 0x000b
40#define AR_SUBVENDOR_ID_NOG 0x0e11
41#define AR_SUBVENDOR_ID_NEW_A 0x7065
42#define AR5416_MAGIC 0x19641014
43
44/* Register read/write primitives */
45#define REG_WRITE(_ah, _reg, _val) iowrite32(_val, _ah->ah_sc->mem + _reg)
46#define REG_READ(_ah, _reg) ioread32(_ah->ah_sc->mem + _reg)
47
48#define SM(_v, _f) (((_v) << _f##_S) & _f)
49#define MS(_v, _f) (((_v) & _f) >> _f##_S)
50#define REG_RMW(_a, _r, _set, _clr) \
51 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
52#define REG_RMW_FIELD(_a, _r, _f, _v) \
53 REG_WRITE(_a, _r, \
54 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
55#define REG_SET_BIT(_a, _r, _f) \
56 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
57#define REG_CLR_BIT(_a, _r, _f) \
58 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
22 59
23extern const struct hal_percal_data iq_cal_multi_sample; 60#define DO_DELAY(x) do { \
24extern const struct hal_percal_data iq_cal_single_sample; 61 if ((++(x) % 64) == 0) \
25extern const struct hal_percal_data adc_gain_cal_multi_sample; 62 udelay(1); \
26extern const struct hal_percal_data adc_gain_cal_single_sample; 63 } while (0)
27extern const struct hal_percal_data adc_dc_cal_multi_sample;
28extern const struct hal_percal_data adc_dc_cal_single_sample;
29extern const struct hal_percal_data adc_init_dc_cal;
30
31struct ar5416_desc {
32 u32 ds_link;
33 u32 ds_data;
34 u32 ds_ctl0;
35 u32 ds_ctl1;
36 union {
37 struct {
38 u32 ctl2;
39 u32 ctl3;
40 u32 ctl4;
41 u32 ctl5;
42 u32 ctl6;
43 u32 ctl7;
44 u32 ctl8;
45 u32 ctl9;
46 u32 ctl10;
47 u32 ctl11;
48 u32 status0;
49 u32 status1;
50 u32 status2;
51 u32 status3;
52 u32 status4;
53 u32 status5;
54 u32 status6;
55 u32 status7;
56 u32 status8;
57 u32 status9;
58 } tx;
59 struct {
60 u32 status0;
61 u32 status1;
62 u32 status2;
63 u32 status3;
64 u32 status4;
65 u32 status5;
66 u32 status6;
67 u32 status7;
68 u32 status8;
69 } rx;
70 } u;
71} __packed;
72
73#define AR5416DESC(_ds) ((struct ar5416_desc *)(_ds))
74#define AR5416DESC_CONST(_ds) ((const struct ar5416_desc *)(_ds))
75
76#define ds_ctl2 u.tx.ctl2
77#define ds_ctl3 u.tx.ctl3
78#define ds_ctl4 u.tx.ctl4
79#define ds_ctl5 u.tx.ctl5
80#define ds_ctl6 u.tx.ctl6
81#define ds_ctl7 u.tx.ctl7
82#define ds_ctl8 u.tx.ctl8
83#define ds_ctl9 u.tx.ctl9
84#define ds_ctl10 u.tx.ctl10
85#define ds_ctl11 u.tx.ctl11
86
87#define ds_txstatus0 u.tx.status0
88#define ds_txstatus1 u.tx.status1
89#define ds_txstatus2 u.tx.status2
90#define ds_txstatus3 u.tx.status3
91#define ds_txstatus4 u.tx.status4
92#define ds_txstatus5 u.tx.status5
93#define ds_txstatus6 u.tx.status6
94#define ds_txstatus7 u.tx.status7
95#define ds_txstatus8 u.tx.status8
96#define ds_txstatus9 u.tx.status9
97
98#define ds_rxstatus0 u.rx.status0
99#define ds_rxstatus1 u.rx.status1
100#define ds_rxstatus2 u.rx.status2
101#define ds_rxstatus3 u.rx.status3
102#define ds_rxstatus4 u.rx.status4
103#define ds_rxstatus5 u.rx.status5
104#define ds_rxstatus6 u.rx.status6
105#define ds_rxstatus7 u.rx.status7
106#define ds_rxstatus8 u.rx.status8
107
108#define AR_FrameLen 0x00000fff
109#define AR_VirtMoreFrag 0x00001000
110#define AR_TxCtlRsvd00 0x0000e000
111#define AR_XmitPower 0x003f0000
112#define AR_XmitPower_S 16
113#define AR_RTSEnable 0x00400000
114#define AR_VEOL 0x00800000
115#define AR_ClrDestMask 0x01000000
116#define AR_TxCtlRsvd01 0x1e000000
117#define AR_TxIntrReq 0x20000000
118#define AR_DestIdxValid 0x40000000
119#define AR_CTSEnable 0x80000000
120
121#define AR_BufLen 0x00000fff
122#define AR_TxMore 0x00001000
123#define AR_DestIdx 0x000fe000
124#define AR_DestIdx_S 13
125#define AR_FrameType 0x00f00000
126#define AR_FrameType_S 20
127#define AR_NoAck 0x01000000
128#define AR_InsertTS 0x02000000
129#define AR_CorruptFCS 0x04000000
130#define AR_ExtOnly 0x08000000
131#define AR_ExtAndCtl 0x10000000
132#define AR_MoreAggr 0x20000000
133#define AR_IsAggr 0x40000000
134
135#define AR_BurstDur 0x00007fff
136#define AR_BurstDur_S 0
137#define AR_DurUpdateEna 0x00008000
138#define AR_XmitDataTries0 0x000f0000
139#define AR_XmitDataTries0_S 16
140#define AR_XmitDataTries1 0x00f00000
141#define AR_XmitDataTries1_S 20
142#define AR_XmitDataTries2 0x0f000000
143#define AR_XmitDataTries2_S 24
144#define AR_XmitDataTries3 0xf0000000
145#define AR_XmitDataTries3_S 28
146
147#define AR_XmitRate0 0x000000ff
148#define AR_XmitRate0_S 0
149#define AR_XmitRate1 0x0000ff00
150#define AR_XmitRate1_S 8
151#define AR_XmitRate2 0x00ff0000
152#define AR_XmitRate2_S 16
153#define AR_XmitRate3 0xff000000
154#define AR_XmitRate3_S 24
155
156#define AR_PacketDur0 0x00007fff
157#define AR_PacketDur0_S 0
158#define AR_RTSCTSQual0 0x00008000
159#define AR_PacketDur1 0x7fff0000
160#define AR_PacketDur1_S 16
161#define AR_RTSCTSQual1 0x80000000
162
163#define AR_PacketDur2 0x00007fff
164#define AR_PacketDur2_S 0
165#define AR_RTSCTSQual2 0x00008000
166#define AR_PacketDur3 0x7fff0000
167#define AR_PacketDur3_S 16
168#define AR_RTSCTSQual3 0x80000000
169
170#define AR_AggrLen 0x0000ffff
171#define AR_AggrLen_S 0
172#define AR_TxCtlRsvd60 0x00030000
173#define AR_PadDelim 0x03fc0000
174#define AR_PadDelim_S 18
175#define AR_EncrType 0x0c000000
176#define AR_EncrType_S 26
177#define AR_TxCtlRsvd61 0xf0000000
178
179#define AR_2040_0 0x00000001
180#define AR_GI0 0x00000002
181#define AR_ChainSel0 0x0000001c
182#define AR_ChainSel0_S 2
183#define AR_2040_1 0x00000020
184#define AR_GI1 0x00000040
185#define AR_ChainSel1 0x00000380
186#define AR_ChainSel1_S 7
187#define AR_2040_2 0x00000400
188#define AR_GI2 0x00000800
189#define AR_ChainSel2 0x00007000
190#define AR_ChainSel2_S 12
191#define AR_2040_3 0x00008000
192#define AR_GI3 0x00010000
193#define AR_ChainSel3 0x000e0000
194#define AR_ChainSel3_S 17
195#define AR_RTSCTSRate 0x0ff00000
196#define AR_RTSCTSRate_S 20
197#define AR_TxCtlRsvd70 0xf0000000
198
199#define AR_TxRSSIAnt00 0x000000ff
200#define AR_TxRSSIAnt00_S 0
201#define AR_TxRSSIAnt01 0x0000ff00
202#define AR_TxRSSIAnt01_S 8
203#define AR_TxRSSIAnt02 0x00ff0000
204#define AR_TxRSSIAnt02_S 16
205#define AR_TxStatusRsvd00 0x3f000000
206#define AR_TxBaStatus 0x40000000
207#define AR_TxStatusRsvd01 0x80000000
208
209#define AR_FrmXmitOK 0x00000001
210#define AR_ExcessiveRetries 0x00000002
211#define AR_FIFOUnderrun 0x00000004
212#define AR_Filtered 0x00000008
213#define AR_RTSFailCnt 0x000000f0
214#define AR_RTSFailCnt_S 4
215#define AR_DataFailCnt 0x00000f00
216#define AR_DataFailCnt_S 8
217#define AR_VirtRetryCnt 0x0000f000
218#define AR_VirtRetryCnt_S 12
219#define AR_TxDelimUnderrun 0x00010000
220#define AR_TxDataUnderrun 0x00020000
221#define AR_DescCfgErr 0x00040000
222#define AR_TxTimerExpired 0x00080000
223#define AR_TxStatusRsvd10 0xfff00000
224
225#define AR_SendTimestamp ds_txstatus2
226#define AR_BaBitmapLow ds_txstatus3
227#define AR_BaBitmapHigh ds_txstatus4
228
229#define AR_TxRSSIAnt10 0x000000ff
230#define AR_TxRSSIAnt10_S 0
231#define AR_TxRSSIAnt11 0x0000ff00
232#define AR_TxRSSIAnt11_S 8
233#define AR_TxRSSIAnt12 0x00ff0000
234#define AR_TxRSSIAnt12_S 16
235#define AR_TxRSSICombined 0xff000000
236#define AR_TxRSSICombined_S 24
237
238#define AR_TxEVM0 ds_txstatus5
239#define AR_TxEVM1 ds_txstatus6
240#define AR_TxEVM2 ds_txstatus7
241
242#define AR_TxDone 0x00000001
243#define AR_SeqNum 0x00001ffe
244#define AR_SeqNum_S 1
245#define AR_TxStatusRsvd80 0x0001e000
246#define AR_TxOpExceeded 0x00020000
247#define AR_TxStatusRsvd81 0x001c0000
248#define AR_FinalTxIdx 0x00600000
249#define AR_FinalTxIdx_S 21
250#define AR_TxStatusRsvd82 0x01800000
251#define AR_PowerMgmt 0x02000000
252#define AR_TxStatusRsvd83 0xfc000000
253
254#define AR_RxCTLRsvd00 0xffffffff
255
256#define AR_BufLen 0x00000fff
257#define AR_RxCtlRsvd00 0x00001000
258#define AR_RxIntrReq 0x00002000
259#define AR_RxCtlRsvd01 0xffffc000
260
261#define AR_RxRSSIAnt00 0x000000ff
262#define AR_RxRSSIAnt00_S 0
263#define AR_RxRSSIAnt01 0x0000ff00
264#define AR_RxRSSIAnt01_S 8
265#define AR_RxRSSIAnt02 0x00ff0000
266#define AR_RxRSSIAnt02_S 16
267#define AR_RxRate 0xff000000
268#define AR_RxRate_S 24
269#define AR_RxStatusRsvd00 0xff000000
270
271#define AR_DataLen 0x00000fff
272#define AR_RxMore 0x00001000
273#define AR_NumDelim 0x003fc000
274#define AR_NumDelim_S 14
275#define AR_RxStatusRsvd10 0xff800000
276
277#define AR_RcvTimestamp ds_rxstatus2
278
279#define AR_GI 0x00000001
280#define AR_2040 0x00000002
281#define AR_Parallel40 0x00000004
282#define AR_Parallel40_S 2
283#define AR_RxStatusRsvd30 0x000000f8
284#define AR_RxAntenna 0xffffff00
285#define AR_RxAntenna_S 8
286
287#define AR_RxRSSIAnt10 0x000000ff
288#define AR_RxRSSIAnt10_S 0
289#define AR_RxRSSIAnt11 0x0000ff00
290#define AR_RxRSSIAnt11_S 8
291#define AR_RxRSSIAnt12 0x00ff0000
292#define AR_RxRSSIAnt12_S 16
293#define AR_RxRSSICombined 0xff000000
294#define AR_RxRSSICombined_S 24
295
296#define AR_RxEVM0 ds_rxstatus4
297#define AR_RxEVM1 ds_rxstatus5
298#define AR_RxEVM2 ds_rxstatus6
299
300#define AR_RxDone 0x00000001
301#define AR_RxFrameOK 0x00000002
302#define AR_CRCErr 0x00000004
303#define AR_DecryptCRCErr 0x00000008
304#define AR_PHYErr 0x00000010
305#define AR_MichaelErr 0x00000020
306#define AR_PreDelimCRCErr 0x00000040
307#define AR_RxStatusRsvd70 0x00000080
308#define AR_RxKeyIdxValid 0x00000100
309#define AR_KeyIdx 0x0000fe00
310#define AR_KeyIdx_S 9
311#define AR_PHYErrCode 0x0000ff00
312#define AR_PHYErrCode_S 8
313#define AR_RxMoreAggr 0x00010000
314#define AR_RxAggr 0x00020000
315#define AR_PostDelimCRCErr 0x00040000
316#define AR_RxStatusRsvd71 0x3ff80000
317#define AR_DecryptBusyErr 0x40000000
318#define AR_KeyMiss 0x80000000
319
320#define AR5416_MAGIC 0x19641014
321
322#define RXSTATUS_RATE(ah, ads) (AR_SREV_5416_V20_OR_LATER(ah) ? \
323 MS(ads->ds_rxstatus0, AR_RxRate) : \
324 (ads->ds_rxstatus3 >> 2) & 0xFF)
325
326#define set11nTries(_series, _index) \
327 (SM((_series)[_index].Tries, AR_XmitDataTries##_index))
328
329#define set11nRate(_series, _index) \
330 (SM((_series)[_index].Rate, AR_XmitRate##_index))
331
332#define set11nPktDurRTSCTS(_series, _index) \
333 (SM((_series)[_index].PktDuration, AR_PacketDur##_index) | \
334 ((_series)[_index].RateFlags & ATH9K_RATESERIES_RTS_CTS ? \
335 AR_RTSCTSQual##_index : 0))
336 64
337#define set11nRateFlags(_series, _index) \ 65#define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
338 (((_series)[_index].RateFlags & ATH9K_RATESERIES_2040 ? \ 66 int r; \
339 AR_2040_##_index : 0) \ 67 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
340 |((_series)[_index].RateFlags & ATH9K_RATESERIES_HALFGI ? \ 68 REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
341 AR_GI##_index : 0) \ 69 INI_RA((iniarray), r, (column))); \
342 |SM((_series)[_index].ChSel, AR_ChainSel##_index)) 70 DO_DELAY(regWr); \
71 } \
72 } while (0)
343 73
344#define AR_SREV_9100(ah) ((ah->ah_macVersion) == AR_SREV_VERSION_9100) 74#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
75#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
76#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
77#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
78#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
79#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
345 80
346#define INIT_CONFIG_STATUS 0x00000000 81#define AR_GPIOD_MASK 0x00001FFF
347#define INIT_RSSI_THR 0x00000700 82#define AR_GPIO_BIT(_gpio) (1 << (_gpio))
348#define INIT_BCON_CNTRL_REG 0x00000000
349 83
350#define MIN_TX_FIFO_THRESHOLD 0x1 84#define BASE_ACTIVATE_DELAY 100
351#define MAX_TX_FIFO_THRESHOLD ((4096 / 64) - 1) 85#define RTC_PLL_SETTLE_DELAY 1000
352#define INIT_TX_FIFO_THRESHOLD MIN_TX_FIFO_THRESHOLD 86#define COEF_SCALE_S 24
87#define HT40_CHANNEL_CENTER_SHIFT 10
353 88
354struct ar5416AniState { 89#define ATH9K_ANTENNA0_CHAINMASK 0x1
355 struct ath9k_channel c; 90#define ATH9K_ANTENNA1_CHAINMASK 0x2
356 u8 noiseImmunityLevel; 91
357 u8 spurImmunityLevel; 92#define ATH9K_NUM_DMA_DEBUG_REGS 8
358 u8 firstepLevel; 93#define ATH9K_NUM_QUEUES 10
359 u8 ofdmWeakSigDetectOff; 94
360 u8 cckWeakSigThreshold; 95#define MAX_RATE_POWER 63
361 u32 listenTime; 96#define AH_TIMEOUT 100000
362 u32 ofdmTrigHigh; 97#define AH_TIME_QUANTUM 10
363 u32 ofdmTrigLow; 98#define AR_KEYTABLE_SIZE 128
364 int32_t cckTrigHigh; 99#define POWER_UP_TIME 200000
365 int32_t cckTrigLow; 100#define SPUR_RSSI_THRESH 40
366 int32_t rssiThrLow; 101
367 int32_t rssiThrHigh; 102#define CAB_TIMEOUT_VAL 10
368 u32 noiseFloor; 103#define BEACON_TIMEOUT_VAL 10
369 u32 txFrameCount; 104#define MIN_BEACON_TIMEOUT_VAL 1
370 u32 rxFrameCount; 105#define SLEEP_SLOP 3
371 u32 cycleCount; 106
372 u32 ofdmPhyErrCount; 107#define INIT_CONFIG_STATUS 0x00000000
373 u32 cckPhyErrCount; 108#define INIT_RSSI_THR 0x00000700
374 u32 ofdmPhyErrBase; 109#define INIT_BCON_CNTRL_REG 0x00000000
375 u32 cckPhyErrBase; 110
376 int16_t pktRssi[2]; 111#define TU_TO_USEC(_tu) ((_tu) << 10)
377 int16_t ofdmErrRssi[2]; 112
378 int16_t cckErrRssi[2]; 113enum wireless_mode {
114 ATH9K_MODE_11A = 0,
115 ATH9K_MODE_11B = 2,
116 ATH9K_MODE_11G = 3,
117 ATH9K_MODE_11NA_HT20 = 6,
118 ATH9K_MODE_11NG_HT20 = 7,
119 ATH9K_MODE_11NA_HT40PLUS = 8,
120 ATH9K_MODE_11NA_HT40MINUS = 9,
121 ATH9K_MODE_11NG_HT40PLUS = 10,
122 ATH9K_MODE_11NG_HT40MINUS = 11,
123 ATH9K_MODE_MAX
379}; 124};
380 125
381#define HAL_PROCESS_ANI 0x00000001 126enum ath9k_hw_caps {
382#define DO_ANI(ah) \ 127 ATH9K_HW_CAP_CHAN_SPREAD = BIT(0),
383 ((AH5416(ah)->ah_procPhyErr & HAL_PROCESS_ANI)) 128 ATH9K_HW_CAP_MIC_AESCCM = BIT(1),
384 129 ATH9K_HW_CAP_MIC_CKIP = BIT(2),
385struct ar5416Stats { 130 ATH9K_HW_CAP_MIC_TKIP = BIT(3),
386 u32 ast_ani_niup; 131 ATH9K_HW_CAP_CIPHER_AESCCM = BIT(4),
387 u32 ast_ani_nidown; 132 ATH9K_HW_CAP_CIPHER_CKIP = BIT(5),
388 u32 ast_ani_spurup; 133 ATH9K_HW_CAP_CIPHER_TKIP = BIT(6),
389 u32 ast_ani_spurdown; 134 ATH9K_HW_CAP_VEOL = BIT(7),
390 u32 ast_ani_ofdmon; 135 ATH9K_HW_CAP_BSSIDMASK = BIT(8),
391 u32 ast_ani_ofdmoff; 136 ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(9),
392 u32 ast_ani_cckhigh; 137 ATH9K_HW_CAP_CHAN_HALFRATE = BIT(10),
393 u32 ast_ani_ccklow; 138 ATH9K_HW_CAP_CHAN_QUARTERRATE = BIT(11),
394 u32 ast_ani_stepup; 139 ATH9K_HW_CAP_HT = BIT(12),
395 u32 ast_ani_stepdown; 140 ATH9K_HW_CAP_GTT = BIT(13),
396 u32 ast_ani_ofdmerrs; 141 ATH9K_HW_CAP_FASTCC = BIT(14),
397 u32 ast_ani_cckerrs; 142 ATH9K_HW_CAP_RFSILENT = BIT(15),
398 u32 ast_ani_reset; 143 ATH9K_HW_CAP_WOW = BIT(16),
399 u32 ast_ani_lzero; 144 ATH9K_HW_CAP_CST = BIT(17),
400 u32 ast_ani_lneg; 145 ATH9K_HW_CAP_ENHANCEDPM = BIT(18),
401 struct ath9k_mib_stats ast_mibstats; 146 ATH9K_HW_CAP_AUTOSLEEP = BIT(19),
402 struct ath9k_node_stats ast_nodestats; 147 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(20),
148 ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT = BIT(21),
149 ATH9K_HW_CAP_BT_COEX = BIT(22)
403}; 150};
404 151
405#define AR5416_OPFLAGS_11A 0x01 152enum ath9k_capability_type {
406#define AR5416_OPFLAGS_11G 0x02 153 ATH9K_CAP_CIPHER = 0,
407#define AR5416_OPFLAGS_N_5G_HT40 0x04 154 ATH9K_CAP_TKIP_MIC,
408#define AR5416_OPFLAGS_N_2G_HT40 0x08 155 ATH9K_CAP_TKIP_SPLIT,
409#define AR5416_OPFLAGS_N_5G_HT20 0x10 156 ATH9K_CAP_PHYCOUNTERS,
410#define AR5416_OPFLAGS_N_2G_HT20 0x20 157 ATH9K_CAP_DIVERSITY,
411 158 ATH9K_CAP_TXPOW,
412#define EEP_RFSILENT_ENABLED 0x0001 159 ATH9K_CAP_PHYDIAG,
413#define EEP_RFSILENT_ENABLED_S 0 160 ATH9K_CAP_MCAST_KEYSRCH,
414#define EEP_RFSILENT_POLARITY 0x0002 161 ATH9K_CAP_TSF_ADJUST,
415#define EEP_RFSILENT_POLARITY_S 1 162 ATH9K_CAP_WME_TKIPMIC,
416#define EEP_RFSILENT_GPIO_SEL 0x001c 163 ATH9K_CAP_RFSILENT,
417#define EEP_RFSILENT_GPIO_SEL_S 2 164 ATH9K_CAP_ANT_CFG_2GHZ,
418 165 ATH9K_CAP_ANT_CFG_5GHZ
419#define AR5416_EEP_NO_BACK_VER 0x1
420#define AR5416_EEP_VER 0xE
421#define AR5416_EEP_VER_MINOR_MASK 0x0FFF
422#define AR5416_EEP_MINOR_VER_2 0x2
423#define AR5416_EEP_MINOR_VER_3 0x3
424#define AR5416_EEP_MINOR_VER_7 0x7
425#define AR5416_EEP_MINOR_VER_9 0x9
426#define AR5416_EEP_MINOR_VER_16 0x10
427#define AR5416_EEP_MINOR_VER_17 0x11
428#define AR5416_EEP_MINOR_VER_19 0x13
429#define AR5416_EEP_MINOR_VER_20 0x14
430
431#define AR5416_NUM_5G_CAL_PIERS 8
432#define AR5416_NUM_2G_CAL_PIERS 4
433#define AR5416_NUM_5G_20_TARGET_POWERS 8
434#define AR5416_NUM_5G_40_TARGET_POWERS 8
435#define AR5416_NUM_2G_CCK_TARGET_POWERS 3
436#define AR5416_NUM_2G_20_TARGET_POWERS 4
437#define AR5416_NUM_2G_40_TARGET_POWERS 4
438#define AR5416_NUM_CTLS 24
439#define AR5416_NUM_BAND_EDGES 8
440#define AR5416_NUM_PD_GAINS 4
441#define AR5416_PD_GAINS_IN_MASK 4
442#define AR5416_PD_GAIN_ICEPTS 5
443#define AR5416_EEPROM_MODAL_SPURS 5
444#define AR5416_MAX_RATE_POWER 63
445#define AR5416_NUM_PDADC_VALUES 128
446#define AR5416_BCHAN_UNUSED 0xFF
447#define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
448#define AR5416_MAX_CHAINS 3
449#define AR5416_PWR_TABLE_OFFSET -5
450
451/* Rx gain type values */
452#define AR5416_EEP_RXGAIN_23DB_BACKOFF 0
453#define AR5416_EEP_RXGAIN_13DB_BACKOFF 1
454#define AR5416_EEP_RXGAIN_ORIG 2
455
456/* Tx gain type values */
457#define AR5416_EEP_TXGAIN_ORIGINAL 0
458#define AR5416_EEP_TXGAIN_HIGH_POWER 1
459
460#define AR5416_EEP4K_START_LOC 64
461#define AR5416_EEP4K_NUM_2G_CAL_PIERS 3
462#define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3
463#define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS 3
464#define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS 3
465#define AR5416_EEP4K_NUM_CTLS 12
466#define AR5416_EEP4K_NUM_BAND_EDGES 4
467#define AR5416_EEP4K_NUM_PD_GAINS 2
468#define AR5416_EEP4K_PD_GAINS_IN_MASK 4
469#define AR5416_EEP4K_PD_GAIN_ICEPTS 5
470#define AR5416_EEP4K_MAX_CHAINS 1
471
472enum eeprom_param {
473 EEP_NFTHRESH_5,
474 EEP_NFTHRESH_2,
475 EEP_MAC_MSW,
476 EEP_MAC_MID,
477 EEP_MAC_LSW,
478 EEP_REG_0,
479 EEP_REG_1,
480 EEP_OP_CAP,
481 EEP_OP_MODE,
482 EEP_RF_SILENT,
483 EEP_OB_5,
484 EEP_DB_5,
485 EEP_OB_2,
486 EEP_DB_2,
487 EEP_MINOR_REV,
488 EEP_TX_MASK,
489 EEP_RX_MASK,
490 EEP_RXGAIN_TYPE,
491 EEP_TXGAIN_TYPE,
492 EEP_DAC_HPWR_5G,
493}; 166};
494 167
495enum ar5416_rates { 168struct ath9k_hw_capabilities {
496 rate6mb, rate9mb, rate12mb, rate18mb, 169 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
497 rate24mb, rate36mb, rate48mb, rate54mb, 170 DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */
498 rate1l, rate2l, rate2s, rate5_5l, 171 u16 total_queues;
499 rate5_5s, rate11l, rate11s, rateXr, 172 u16 keycache_size;
500 rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3, 173 u16 low_5ghz_chan, high_5ghz_chan;
501 rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7, 174 u16 low_2ghz_chan, high_2ghz_chan;
502 rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3, 175 u16 num_mr_retries;
503 rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7, 176 u16 rts_aggr_limit;
504 rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm, 177 u8 tx_chainmask;
505 Ar5416RateSize 178 u8 rx_chainmask;
179 u16 tx_triglevel_max;
180 u16 reg_cap;
181 u8 num_gpio_pins;
182 u8 num_antcfg_2ghz;
183 u8 num_antcfg_5ghz;
506}; 184};
507 185
508enum ath9k_hal_freq_band { 186struct ath9k_ops_config {
509 ATH9K_HAL_FREQ_BAND_5GHZ = 0, 187 int dma_beacon_response_time;
510 ATH9K_HAL_FREQ_BAND_2GHZ = 1 188 int sw_beacon_response_time;
189 int additional_swba_backoff;
190 int ack_6mb;
191 int cwm_ignore_extcca;
192 u8 pcie_powersave_enable;
193 u8 pcie_l1skp_enable;
194 u8 pcie_clock_req;
195 u32 pcie_waen;
196 int pcie_power_reset;
197 u8 pcie_restore;
198 u8 analog_shiftreg;
199 u8 ht_enable;
200 u32 ofdm_trig_low;
201 u32 ofdm_trig_high;
202 u32 cck_trig_high;
203 u32 cck_trig_low;
204 u32 enable_ani;
205 u8 noise_immunity_level;
206 u32 ofdm_weaksignal_det;
207 u32 cck_weaksignal_thr;
208 u8 spur_immunity_level;
209 u8 firstep_level;
210 int8_t rssi_thr_high;
211 int8_t rssi_thr_low;
212 u16 diversity_control;
213 u16 antenna_switch_swap;
214 int serialize_regmode;
215 int intr_mitigation;
216#define SPUR_DISABLE 0
217#define SPUR_ENABLE_IOCTL 1
218#define SPUR_ENABLE_EEPROM 2
219#define AR_EEPROM_MODAL_SPURS 5
220#define AR_SPUR_5413_1 1640
221#define AR_SPUR_5413_2 1200
222#define AR_NO_SPUR 0x8000
223#define AR_BASE_FREQ_2GHZ 2300
224#define AR_BASE_FREQ_5GHZ 4900
225#define AR_SPUR_FEEQ_BOUND_HT40 19
226#define AR_SPUR_FEEQ_BOUND_HT20 10
227 int spurmode;
228 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
511}; 229};
512 230
513struct base_eep_header { 231enum ath9k_int {
514 u16 length; 232 ATH9K_INT_RX = 0x00000001,
515 u16 checksum; 233 ATH9K_INT_RXDESC = 0x00000002,
516 u16 version; 234 ATH9K_INT_RXNOFRM = 0x00000008,
517 u8 opCapFlags; 235 ATH9K_INT_RXEOL = 0x00000010,
518 u8 eepMisc; 236 ATH9K_INT_RXORN = 0x00000020,
519 u16 regDmn[2]; 237 ATH9K_INT_TX = 0x00000040,
520 u8 macAddr[6]; 238 ATH9K_INT_TXDESC = 0x00000080,
521 u8 rxMask; 239 ATH9K_INT_TIM_TIMER = 0x00000100,
522 u8 txMask; 240 ATH9K_INT_TXURN = 0x00000800,
523 u16 rfSilent; 241 ATH9K_INT_MIB = 0x00001000,
524 u16 blueToothOptions; 242 ATH9K_INT_RXPHY = 0x00004000,
525 u16 deviceCap; 243 ATH9K_INT_RXKCM = 0x00008000,
526 u32 binBuildNumber; 244 ATH9K_INT_SWBA = 0x00010000,
527 u8 deviceType; 245 ATH9K_INT_BMISS = 0x00040000,
528 u8 pwdclkind; 246 ATH9K_INT_BNR = 0x00100000,
529 u8 futureBase_1[2]; 247 ATH9K_INT_TIM = 0x00200000,
530 u8 rxGainType; 248 ATH9K_INT_DTIM = 0x00400000,
531 u8 dacHiPwrMode_5G; 249 ATH9K_INT_DTIMSYNC = 0x00800000,
532 u8 futureBase_2; 250 ATH9K_INT_GPIO = 0x01000000,
533 u8 dacLpMode; 251 ATH9K_INT_CABEND = 0x02000000,
534 u8 txGainType; 252 ATH9K_INT_CST = 0x10000000,
535 u8 rcChainMask; 253 ATH9K_INT_GTT = 0x20000000,
536 u8 desiredScaleCCK; 254 ATH9K_INT_FATAL = 0x40000000,
537 u8 futureBase_3[23]; 255 ATH9K_INT_GLOBAL = 0x80000000,
538} __packed; 256 ATH9K_INT_BMISC = ATH9K_INT_TIM |
539 257 ATH9K_INT_DTIM |
540struct base_eep_header_4k { 258 ATH9K_INT_DTIMSYNC |
541 u16 length; 259 ATH9K_INT_CABEND,
542 u16 checksum; 260 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
543 u16 version; 261 ATH9K_INT_RXDESC |
544 u8 opCapFlags; 262 ATH9K_INT_RXEOL |
545 u8 eepMisc; 263 ATH9K_INT_RXORN |
546 u16 regDmn[2]; 264 ATH9K_INT_TXURN |
547 u8 macAddr[6]; 265 ATH9K_INT_TXDESC |
548 u8 rxMask; 266 ATH9K_INT_MIB |
549 u8 txMask; 267 ATH9K_INT_RXPHY |
550 u16 rfSilent; 268 ATH9K_INT_RXKCM |
551 u16 blueToothOptions; 269 ATH9K_INT_SWBA |
552 u16 deviceCap; 270 ATH9K_INT_BMISS |
553 u32 binBuildNumber; 271 ATH9K_INT_GPIO,
554 u8 deviceType; 272 ATH9K_INT_NOCARD = 0xffffffff
555 u8 futureBase[1];
556} __packed;
557
558
559struct spur_chan {
560 u16 spurChan;
561 u8 spurRangeLow;
562 u8 spurRangeHigh;
563} __packed;
564
565struct modal_eep_header {
566 u32 antCtrlChain[AR5416_MAX_CHAINS];
567 u32 antCtrlCommon;
568 u8 antennaGainCh[AR5416_MAX_CHAINS];
569 u8 switchSettling;
570 u8 txRxAttenCh[AR5416_MAX_CHAINS];
571 u8 rxTxMarginCh[AR5416_MAX_CHAINS];
572 u8 adcDesiredSize;
573 u8 pgaDesiredSize;
574 u8 xlnaGainCh[AR5416_MAX_CHAINS];
575 u8 txEndToXpaOff;
576 u8 txEndToRxOn;
577 u8 txFrameToXpaOn;
578 u8 thresh62;
579 u8 noiseFloorThreshCh[AR5416_MAX_CHAINS];
580 u8 xpdGain;
581 u8 xpd;
582 u8 iqCalICh[AR5416_MAX_CHAINS];
583 u8 iqCalQCh[AR5416_MAX_CHAINS];
584 u8 pdGainOverlap;
585 u8 ob;
586 u8 db;
587 u8 xpaBiasLvl;
588 u8 pwrDecreaseFor2Chain;
589 u8 pwrDecreaseFor3Chain;
590 u8 txFrameToDataStart;
591 u8 txFrameToPaOn;
592 u8 ht40PowerIncForPdadc;
593 u8 bswAtten[AR5416_MAX_CHAINS];
594 u8 bswMargin[AR5416_MAX_CHAINS];
595 u8 swSettleHt40;
596 u8 xatten2Db[AR5416_MAX_CHAINS];
597 u8 xatten2Margin[AR5416_MAX_CHAINS];
598 u8 ob_ch1;
599 u8 db_ch1;
600 u8 useAnt1:1,
601 force_xpaon:1,
602 local_bias:1,
603 femBandSelectUsed:1, xlnabufin:1, xlnaisel:2, xlnabufmode:1;
604 u8 miscBits;
605 u16 xpaBiasLvlFreq[3];
606 u8 futureModal[6];
607
608 struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
609} __packed;
610
611struct modal_eep_4k_header {
612 u32 antCtrlChain[AR5416_EEP4K_MAX_CHAINS];
613 u32 antCtrlCommon;
614 u8 antennaGainCh[AR5416_EEP4K_MAX_CHAINS];
615 u8 switchSettling;
616 u8 txRxAttenCh[AR5416_EEP4K_MAX_CHAINS];
617 u8 rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS];
618 u8 adcDesiredSize;
619 u8 pgaDesiredSize;
620 u8 xlnaGainCh[AR5416_EEP4K_MAX_CHAINS];
621 u8 txEndToXpaOff;
622 u8 txEndToRxOn;
623 u8 txFrameToXpaOn;
624 u8 thresh62;
625 u8 noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS];
626 u8 xpdGain;
627 u8 xpd;
628 u8 iqCalICh[AR5416_EEP4K_MAX_CHAINS];
629 u8 iqCalQCh[AR5416_EEP4K_MAX_CHAINS];
630 u8 pdGainOverlap;
631 u8 ob_01;
632 u8 db1_01;
633 u8 xpaBiasLvl;
634 u8 txFrameToDataStart;
635 u8 txFrameToPaOn;
636 u8 ht40PowerIncForPdadc;
637 u8 bswAtten[AR5416_EEP4K_MAX_CHAINS];
638 u8 bswMargin[AR5416_EEP4K_MAX_CHAINS];
639 u8 swSettleHt40;
640 u8 xatten2Db[AR5416_EEP4K_MAX_CHAINS];
641 u8 xatten2Margin[AR5416_EEP4K_MAX_CHAINS];
642 u8 db2_01;
643 u8 version;
644 u16 ob_234;
645 u16 db1_234;
646 u16 db2_234;
647 u8 futureModal[4];
648
649 struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
650} __packed;
651
652
653struct cal_data_per_freq {
654 u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
655 u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
656} __packed;
657
658struct cal_data_per_freq_4k {
659 u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
660 u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
661} __packed;
662
663struct cal_target_power_leg {
664 u8 bChannel;
665 u8 tPow2x[4];
666} __packed;
667
668struct cal_target_power_ht {
669 u8 bChannel;
670 u8 tPow2x[8];
671} __packed;
672
673
674#ifdef __BIG_ENDIAN_BITFIELD
675struct cal_ctl_edges {
676 u8 bChannel;
677 u8 flag:2, tPower:6;
678} __packed;
679#else
680struct cal_ctl_edges {
681 u8 bChannel;
682 u8 tPower:6, flag:2;
683} __packed;
684#endif
685
686struct cal_ctl_data {
687 struct cal_ctl_edges
688 ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES];
689} __packed;
690
691struct cal_ctl_data_4k {
692 struct cal_ctl_edges
693 ctlEdges[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_BAND_EDGES];
694} __packed;
695
696struct ar5416_eeprom_def {
697 struct base_eep_header baseEepHeader;
698 u8 custData[64];
699 struct modal_eep_header modalHeader[2];
700 u8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS];
701 u8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS];
702 struct cal_data_per_freq
703 calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS];
704 struct cal_data_per_freq
705 calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS];
706 struct cal_target_power_leg
707 calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS];
708 struct cal_target_power_ht
709 calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS];
710 struct cal_target_power_ht
711 calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS];
712 struct cal_target_power_leg
713 calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS];
714 struct cal_target_power_leg
715 calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS];
716 struct cal_target_power_ht
717 calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS];
718 struct cal_target_power_ht
719 calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS];
720 u8 ctlIndex[AR5416_NUM_CTLS];
721 struct cal_ctl_data ctlData[AR5416_NUM_CTLS];
722 u8 padding;
723} __packed;
724
725struct ar5416_eeprom_4k {
726 struct base_eep_header_4k baseEepHeader;
727 u8 custData[20];
728 struct modal_eep_4k_header modalHeader;
729 u8 calFreqPier2G[AR5416_EEP4K_NUM_2G_CAL_PIERS];
730 struct cal_data_per_freq_4k
731 calPierData2G[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_2G_CAL_PIERS];
732 struct cal_target_power_leg
733 calTargetPowerCck[AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS];
734 struct cal_target_power_leg
735 calTargetPower2G[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
736 struct cal_target_power_ht
737 calTargetPower2GHT20[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
738 struct cal_target_power_ht
739 calTargetPower2GHT40[AR5416_EEP4K_NUM_2G_40_TARGET_POWERS];
740 u8 ctlIndex[AR5416_EEP4K_NUM_CTLS];
741 struct cal_ctl_data_4k ctlData[AR5416_EEP4K_NUM_CTLS];
742 u8 padding;
743} __packed;
744
745struct ar5416IniArray {
746 u32 *ia_array;
747 u32 ia_rows;
748 u32 ia_columns;
749}; 273};
750 274
751#define INIT_INI_ARRAY(iniarray, array, rows, columns) do { \ 275#define CHANNEL_CW_INT 0x00002
752 (iniarray)->ia_array = (u32 *)(array); \ 276#define CHANNEL_CCK 0x00020
753 (iniarray)->ia_rows = (rows); \ 277#define CHANNEL_OFDM 0x00040
754 (iniarray)->ia_columns = (columns); \ 278#define CHANNEL_2GHZ 0x00080
755 } while (0) 279#define CHANNEL_5GHZ 0x00100
756 280#define CHANNEL_PASSIVE 0x00200
757#define INI_RA(iniarray, row, column) \ 281#define CHANNEL_DYN 0x00400
758 (((iniarray)->ia_array)[(row) * ((iniarray)->ia_columns) + (column)]) 282#define CHANNEL_HALF 0x04000
283#define CHANNEL_QUARTER 0x08000
284#define CHANNEL_HT20 0x10000
285#define CHANNEL_HT40PLUS 0x20000
286#define CHANNEL_HT40MINUS 0x40000
287
288#define CHANNEL_INTERFERENCE 0x01
289#define CHANNEL_DFS 0x02
290#define CHANNEL_4MS_LIMIT 0x04
291#define CHANNEL_DFS_CLEAR 0x08
292#define CHANNEL_DISALLOW_ADHOC 0x10
293#define CHANNEL_PER_11D_ADHOC 0x20
294
295#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
296#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
297#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
298#define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
299#define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
300#define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
301#define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
302#define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
303#define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
304#define CHANNEL_ALL \
305 (CHANNEL_OFDM| \
306 CHANNEL_CCK| \
307 CHANNEL_2GHZ | \
308 CHANNEL_5GHZ | \
309 CHANNEL_HT20 | \
310 CHANNEL_HT40PLUS | \
311 CHANNEL_HT40MINUS)
312
313struct ath9k_channel {
314 struct ieee80211_channel *chan;
315 u16 channel;
316 u32 channelFlags;
317 u32 chanmode;
318 int32_t CalValid;
319 bool oneTimeCalsDone;
320 int8_t iCoff;
321 int8_t qCoff;
322 int16_t rawNoiseFloor;
323};
759 324
760#define INIT_CAL(_perCal) do { \ 325#define IS_CHAN_A(_c) ((((_c)->channelFlags & CHANNEL_A) == CHANNEL_A) || \
761 (_perCal)->calState = CAL_WAITING; \ 326 (((_c)->channelFlags & CHANNEL_A_HT20) == CHANNEL_A_HT20) || \
762 (_perCal)->calNext = NULL; \ 327 (((_c)->channelFlags & CHANNEL_A_HT40PLUS) == CHANNEL_A_HT40PLUS) || \
763 } while (0) 328 (((_c)->channelFlags & CHANNEL_A_HT40MINUS) == CHANNEL_A_HT40MINUS))
329#define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
330 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
331 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
332 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
333#define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
334#define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
335#define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
336#define IS_CHAN_PASSIVE(_c) (((_c)->channelFlags & CHANNEL_PASSIVE) != 0)
337#define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
338#define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
339#define IS_CHAN_A_5MHZ_SPACED(_c) \
340 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
341 (((_c)->channel % 20) != 0) && \
342 (((_c)->channel % 10) != 0))
343
344/* These macros check chanmode and not channelFlags */
345#define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
346#define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
347 ((_c)->chanmode == CHANNEL_G_HT20))
348#define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
349 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
350 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
351 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
352#define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
353
354enum ath9k_power_mode {
355 ATH9K_PM_AWAKE = 0,
356 ATH9K_PM_FULL_SLEEP,
357 ATH9K_PM_NETWORK_SLEEP,
358 ATH9K_PM_UNDEFINED
359};
764 360
765#define INSERT_CAL(_ahp, _perCal) \ 361enum ath9k_ant_setting {
766 do { \ 362 ATH9K_ANT_VARIABLE = 0,
767 if ((_ahp)->ah_cal_list_last == NULL) { \ 363 ATH9K_ANT_FIXED_A,
768 (_ahp)->ah_cal_list = \ 364 ATH9K_ANT_FIXED_B
769 (_ahp)->ah_cal_list_last = (_perCal); \ 365};
770 ((_ahp)->ah_cal_list_last)->calNext = (_perCal); \
771 } else { \
772 ((_ahp)->ah_cal_list_last)->calNext = (_perCal); \
773 (_ahp)->ah_cal_list_last = (_perCal); \
774 (_perCal)->calNext = (_ahp)->ah_cal_list; \
775 } \
776 } while (0)
777 366
778enum hal_cal_types { 367enum ath9k_tp_scale {
779 ADC_DC_INIT_CAL = 0x1, 368 ATH9K_TP_SCALE_MAX = 0,
780 ADC_GAIN_CAL = 0x2, 369 ATH9K_TP_SCALE_50,
781 ADC_DC_CAL = 0x4, 370 ATH9K_TP_SCALE_25,
782 IQ_MISMATCH_CAL = 0x8 371 ATH9K_TP_SCALE_12,
372 ATH9K_TP_SCALE_MIN
783}; 373};
784 374
785enum hal_cal_state { 375enum ser_reg_mode {
786 CAL_INACTIVE, 376 SER_REG_MODE_OFF = 0,
787 CAL_WAITING, 377 SER_REG_MODE_ON = 1,
788 CAL_RUNNING, 378 SER_REG_MODE_AUTO = 2,
789 CAL_DONE
790}; 379};
791 380
792#define MIN_CAL_SAMPLES 1 381struct ath9k_beacon_state {
793#define MAX_CAL_SAMPLES 64 382 u32 bs_nexttbtt;
794#define INIT_LOG_COUNT 5 383 u32 bs_nextdtim;
795#define PER_MIN_LOG_COUNT 2 384 u32 bs_intval;
796#define PER_MAX_LOG_COUNT 10 385#define ATH9K_BEACON_PERIOD 0x0000ffff
386#define ATH9K_BEACON_ENA 0x00800000
387#define ATH9K_BEACON_RESET_TSF 0x01000000
388 u32 bs_dtimperiod;
389 u16 bs_cfpperiod;
390 u16 bs_cfpmaxduration;
391 u32 bs_cfpnext;
392 u16 bs_timoffset;
393 u16 bs_bmissthreshold;
394 u32 bs_sleepduration;
395};
797 396
798struct hal_percal_data { 397struct chan_centers {
799 enum hal_cal_types calType; 398 u16 synth_center;
800 u32 calNumSamples; 399 u16 ctl_center;
801 u32 calCountMax; 400 u16 ext_center;
802 void (*calCollect) (struct ath_hal *);
803 void (*calPostProc) (struct ath_hal *, u8);
804}; 401};
805 402
806struct hal_cal_list { 403enum {
807 const struct hal_percal_data *calData; 404 ATH9K_RESET_POWER_ON,
808 enum hal_cal_state calState; 405 ATH9K_RESET_WARM,
809 struct hal_cal_list *calNext; 406 ATH9K_RESET_COLD,
810}; 407};
811 408
812/* 409struct ath9k_hw_version {
813 * Enum to indentify the eeprom mappings 410 u32 magic;
814 */ 411 u16 devid;
815enum hal_eep_map { 412 u16 subvendorid;
816 EEP_MAP_DEFAULT = 0x0, 413 u32 macVersion;
817 EEP_MAP_4KBITS, 414 u16 macRev;
818 EEP_MAP_MAX 415 u16 phyRev;
416 u16 analog5GhzRev;
417 u16 analog2GhzRev;
819}; 418};
820 419
420struct ath_hw {
421 struct ath_softc *ah_sc;
422 struct ath9k_hw_version hw_version;
423 struct ath9k_ops_config config;
424 struct ath9k_hw_capabilities caps;
425 struct ath9k_regulatory regulatory;
426 struct ath9k_channel channels[38];
427 struct ath9k_channel *curchan;
821 428
822struct ath_hal_5416 {
823 struct ath_hal ah;
824 union { 429 union {
825 struct ar5416_eeprom_def def; 430 struct ar5416_eeprom_def def;
826 struct ar5416_eeprom_4k map4k; 431 struct ar5416_eeprom_4k map4k;
827 } ah_eeprom; 432 } eeprom;
828 struct ar5416Stats ah_stats; 433 const struct eeprom_ops *eep_ops;
829 struct ath9k_tx_queue_info ah_txq[ATH9K_NUM_TX_QUEUES]; 434 enum ath9k_eep_map eep_map;
830 void __iomem *ah_cal_mem; 435
831 436 bool sw_mgmt_crypto;
832 u8 ah_macaddr[ETH_ALEN]; 437 bool is_pciexpress;
833 u8 ah_bssid[ETH_ALEN]; 438 u8 macaddr[ETH_ALEN];
834 u8 ah_bssidmask[ETH_ALEN]; 439 u16 tx_trig_level;
835 u16 ah_assocId; 440 u16 rfsilent;
836 441 u32 rfkill_gpio;
837 int16_t ah_curchanRadIndex; 442 u32 rfkill_polarity;
838 u32 ah_maskReg; 443 u32 btactive_gpio;
839 u32 ah_txOkInterruptMask; 444 u32 wlanactive_gpio;
840 u32 ah_txErrInterruptMask; 445 u32 ah_flags;
841 u32 ah_txDescInterruptMask; 446
842 u32 ah_txEolInterruptMask; 447 enum nl80211_iftype opmode;
843 u32 ah_txUrnInterruptMask; 448 enum ath9k_power_mode power_mode;
844 bool ah_chipFullSleep; 449 enum ath9k_power_mode restore_mode;
845 u32 ah_atimWindow; 450
846 u16 ah_antennaSwitchSwap; 451 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
847 enum ath9k_ant_setting ah_diversityControl; 452 struct ar5416Stats stats;
453 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
454
455 int16_t curchan_rad_index;
456 u32 mask_reg;
457 u32 txok_interrupt_mask;
458 u32 txerr_interrupt_mask;
459 u32 txdesc_interrupt_mask;
460 u32 txeol_interrupt_mask;
461 u32 txurn_interrupt_mask;
462 bool chip_fullsleep;
463 u32 atim_window;
464 u16 antenna_switch_swap;
465 enum ath9k_ant_setting diversity_control;
848 466
849 /* Calibration */ 467 /* Calibration */
850 enum hal_cal_types ah_suppCals; 468 enum hal_cal_types supp_cals;
851 struct hal_cal_list ah_iqCalData; 469 struct hal_cal_list iq_caldata;
852 struct hal_cal_list ah_adcGainCalData; 470 struct hal_cal_list adcgain_caldata;
853 struct hal_cal_list ah_adcDcCalInitData; 471 struct hal_cal_list adcdc_calinitdata;
854 struct hal_cal_list ah_adcDcCalData; 472 struct hal_cal_list adcdc_caldata;
855 struct hal_cal_list *ah_cal_list; 473 struct hal_cal_list *cal_list;
856 struct hal_cal_list *ah_cal_list_last; 474 struct hal_cal_list *cal_list_last;
857 struct hal_cal_list *ah_cal_list_curr; 475 struct hal_cal_list *cal_list_curr;
858#define ah_totalPowerMeasI ah_Meas0.unsign 476#define totalPowerMeasI meas0.unsign
859#define ah_totalPowerMeasQ ah_Meas1.unsign 477#define totalPowerMeasQ meas1.unsign
860#define ah_totalIqCorrMeas ah_Meas2.sign 478#define totalIqCorrMeas meas2.sign
861#define ah_totalAdcIOddPhase ah_Meas0.unsign 479#define totalAdcIOddPhase meas0.unsign
862#define ah_totalAdcIEvenPhase ah_Meas1.unsign 480#define totalAdcIEvenPhase meas1.unsign
863#define ah_totalAdcQOddPhase ah_Meas2.unsign 481#define totalAdcQOddPhase meas2.unsign
864#define ah_totalAdcQEvenPhase ah_Meas3.unsign 482#define totalAdcQEvenPhase meas3.unsign
865#define ah_totalAdcDcOffsetIOddPhase ah_Meas0.sign 483#define totalAdcDcOffsetIOddPhase meas0.sign
866#define ah_totalAdcDcOffsetIEvenPhase ah_Meas1.sign 484#define totalAdcDcOffsetIEvenPhase meas1.sign
867#define ah_totalAdcDcOffsetQOddPhase ah_Meas2.sign 485#define totalAdcDcOffsetQOddPhase meas2.sign
868#define ah_totalAdcDcOffsetQEvenPhase ah_Meas3.sign 486#define totalAdcDcOffsetQEvenPhase meas3.sign
869 union { 487 union {
870 u32 unsign[AR5416_MAX_CHAINS]; 488 u32 unsign[AR5416_MAX_CHAINS];
871 int32_t sign[AR5416_MAX_CHAINS]; 489 int32_t sign[AR5416_MAX_CHAINS];
872 } ah_Meas0; 490 } meas0;
873 union { 491 union {
874 u32 unsign[AR5416_MAX_CHAINS]; 492 u32 unsign[AR5416_MAX_CHAINS];
875 int32_t sign[AR5416_MAX_CHAINS]; 493 int32_t sign[AR5416_MAX_CHAINS];
876 } ah_Meas1; 494 } meas1;
877 union { 495 union {
878 u32 unsign[AR5416_MAX_CHAINS]; 496 u32 unsign[AR5416_MAX_CHAINS];
879 int32_t sign[AR5416_MAX_CHAINS]; 497 int32_t sign[AR5416_MAX_CHAINS];
880 } ah_Meas2; 498 } meas2;
881 union { 499 union {
882 u32 unsign[AR5416_MAX_CHAINS]; 500 u32 unsign[AR5416_MAX_CHAINS];
883 int32_t sign[AR5416_MAX_CHAINS]; 501 int32_t sign[AR5416_MAX_CHAINS];
884 } ah_Meas3; 502 } meas3;
885 u16 ah_CalSamples; 503 u16 cal_samples;
886 504
887 u32 ah_staId1Defaults; 505 u32 sta_id1_defaults;
888 u32 ah_miscMode; 506 u32 misc_mode;
889 enum { 507 enum {
890 AUTO_32KHZ, 508 AUTO_32KHZ,
891 USE_32KHZ, 509 USE_32KHZ,
892 DONT_USE_32KHZ, 510 DONT_USE_32KHZ,
893 } ah_enable32kHzClock; 511 } enable_32kHz_clock;
894 512
895 /* RF */ 513 /* RF */
896 u32 *ah_analogBank0Data; 514 u32 *analogBank0Data;
897 u32 *ah_analogBank1Data; 515 u32 *analogBank1Data;
898 u32 *ah_analogBank2Data; 516 u32 *analogBank2Data;
899 u32 *ah_analogBank3Data; 517 u32 *analogBank3Data;
900 u32 *ah_analogBank6Data; 518 u32 *analogBank6Data;
901 u32 *ah_analogBank6TPCData; 519 u32 *analogBank6TPCData;
902 u32 *ah_analogBank7Data; 520 u32 *analogBank7Data;
903 u32 *ah_addac5416_21; 521 u32 *addac5416_21;
904 u32 *ah_bank6Temp; 522 u32 *bank6Temp;
905 523
906 int16_t ah_txPowerIndexOffset; 524 int16_t txpower_indexoffset;
907 u32 ah_beaconInterval; 525 u32 beacon_interval;
908 u32 ah_slottime; 526 u32 slottime;
909 u32 ah_acktimeout; 527 u32 acktimeout;
910 u32 ah_ctstimeout; 528 u32 ctstimeout;
911 u32 ah_globaltxtimeout; 529 u32 globaltxtimeout;
912 u8 ah_gBeaconRate; 530 u8 gbeacon_rate;
913 u32 ah_gpioSelect;
914 u32 ah_polarity;
915 u32 ah_gpioBit;
916 531
917 /* ANI */ 532 /* ANI */
918 u32 ah_procPhyErr; 533 u32 proc_phyerr;
919 bool ah_hasHwPhyCounters; 534 bool has_hw_phycounters;
920 u32 ah_aniPeriod; 535 u32 aniperiod;
921 struct ar5416AniState *ah_curani; 536 struct ar5416AniState *curani;
922 struct ar5416AniState ah_ani[255]; 537 struct ar5416AniState ani[255];
923 int ah_totalSizeDesired[5]; 538 int totalSizeDesired[5];
924 int ah_coarseHigh[5]; 539 int coarse_high[5];
925 int ah_coarseLow[5]; 540 int coarse_low[5];
926 int ah_firpwr[5]; 541 int firpwr[5];
927 enum ath9k_ani_cmd ah_ani_function; 542 enum ath9k_ani_cmd ani_function;
928 543
929 u32 ah_intrTxqs; 544 u32 intr_txqs;
930 bool ah_intrMitigation; 545 bool intr_mitigation;
931 enum ath9k_ht_extprotspacing ah_extprotspacing; 546 enum ath9k_ht_extprotspacing extprotspacing;
932 u8 ah_txchainmask; 547 u8 txchainmask;
933 u8 ah_rxchainmask; 548 u8 rxchainmask;
934 549
935 struct ar5416IniArray ah_iniModes; 550 struct ar5416IniArray iniModes;
936 struct ar5416IniArray ah_iniCommon; 551 struct ar5416IniArray iniCommon;
937 struct ar5416IniArray ah_iniBank0; 552 struct ar5416IniArray iniBank0;
938 struct ar5416IniArray ah_iniBB_RfGain; 553 struct ar5416IniArray iniBB_RfGain;
939 struct ar5416IniArray ah_iniBank1; 554 struct ar5416IniArray iniBank1;
940 struct ar5416IniArray ah_iniBank2; 555 struct ar5416IniArray iniBank2;
941 struct ar5416IniArray ah_iniBank3; 556 struct ar5416IniArray iniBank3;
942 struct ar5416IniArray ah_iniBank6; 557 struct ar5416IniArray iniBank6;
943 struct ar5416IniArray ah_iniBank6TPC; 558 struct ar5416IniArray iniBank6TPC;
944 struct ar5416IniArray ah_iniBank7; 559 struct ar5416IniArray iniBank7;
945 struct ar5416IniArray ah_iniAddac; 560 struct ar5416IniArray iniAddac;
946 struct ar5416IniArray ah_iniPcieSerdes; 561 struct ar5416IniArray iniPcieSerdes;
947 struct ar5416IniArray ah_iniModesAdditional; 562 struct ar5416IniArray iniModesAdditional;
948 struct ar5416IniArray ah_iniModesRxGain; 563 struct ar5416IniArray iniModesRxGain;
949 struct ar5416IniArray ah_iniModesTxGain; 564 struct ar5416IniArray iniModesTxGain;
950 /* To indicate EEPROM mapping used */
951 enum hal_eep_map ah_eep_map;
952}; 565};
953#define AH5416(_ah) ((struct ath_hal_5416 *)(_ah))
954
955#define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
956
957#define ar5416RfDetach(ah) do { \
958 if (AH5416(ah)->ah_rfHal.rfDetach != NULL) \
959 AH5416(ah)->ah_rfHal.rfDetach(ah); \
960 } while (0)
961
962#define ath9k_hw_use_flash(_ah) \
963 (!(_ah->ah_flags & AH_USE_EEPROM))
964
965
966#define DO_DELAY(x) do { \
967 if ((++(x) % 64) == 0) \
968 udelay(1); \
969 } while (0)
970
971#define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
972 int r; \
973 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
974 REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
975 INI_RA((iniarray), r, (column))); \
976 DO_DELAY(regWr); \
977 } \
978 } while (0)
979
980#define BASE_ACTIVATE_DELAY 100
981#define RTC_PLL_SETTLE_DELAY 1000
982#define COEF_SCALE_S 24
983#define HT40_CHANNEL_CENTER_SHIFT 10
984
985#define AR5416_EEPROM_MAGIC_OFFSET 0x0
986
987#define AR5416_EEPROM_S 2
988#define AR5416_EEPROM_OFFSET 0x2000
989#define AR5416_EEPROM_START_ADDR \
990 (AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200
991#define AR5416_EEPROM_MAX 0xae0
992#define ar5416_get_eep_ver(_ahp) \
993 (((_ahp)->ah_eeprom.def.baseEepHeader.version >> 12) & 0xF)
994#define ar5416_get_eep_rev(_ahp) \
995 (((_ahp)->ah_eeprom.def.baseEepHeader.version) & 0xFFF)
996#define ar5416_get_ntxchains(_txchainmask) \
997 (((_txchainmask >> 2) & 1) + \
998 ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
999 566
1000/* EEPROM 4K bit map definations */ 567/* Attach, Detach, Reset */
1001#define ar5416_get_eep4k_ver(_ahp) \ 568const char *ath9k_hw_probe(u16 vendorid, u16 devid);
1002 (((_ahp)->ah_eeprom.map4k.baseEepHeader.version >> 12) & 0xF) 569void ath9k_hw_detach(struct ath_hw *ah);
1003#define ar5416_get_eep4k_rev(_ahp) \ 570struct ath_hw *ath9k_hw_attach(u16 devid, struct ath_softc *sc, int *error);
1004 (((_ahp)->ah_eeprom.map4k.baseEepHeader.version) & 0xFFF) 571void ath9k_hw_rfdetach(struct ath_hw *ah);
1005 572int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1006 573 bool bChannelChange);
1007#ifdef __BIG_ENDIAN 574bool ath9k_hw_fill_cap_info(struct ath_hw *ah);
1008#define AR5416_EEPROM_MAGIC 0x5aa5 575bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
1009#else 576 u32 capability, u32 *result);
1010#define AR5416_EEPROM_MAGIC 0xa55a 577bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
578 u32 capability, u32 setting, int *status);
579
580/* Key Cache Management */
581bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry);
582bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac);
583bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
584 const struct ath9k_keyval *k,
585 const u8 *mac, int xorKey);
586bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry);
587
588/* GPIO / RFKILL / Antennae */
589void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
590u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
591void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
592 u32 ah_signal_type);
593void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
594#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
595void ath9k_enable_rfkill(struct ath_hw *ah);
1011#endif 596#endif
1012 597u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
1013#define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s)) 598void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
1014 599bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
1015#define ATH9K_ANTENNA0_CHAINMASK 0x1 600 enum ath9k_ant_setting settings,
1016#define ATH9K_ANTENNA1_CHAINMASK 0x2 601 struct ath9k_channel *chan,
1017 602 u8 *tx_chainmask, u8 *rx_chainmask,
1018#define ATH9K_NUM_DMA_DEBUG_REGS 8 603 u8 *antenna_cfgd);
1019#define ATH9K_NUM_QUEUES 10 604
1020 605/* General Operation */
1021#define HAL_NOISE_IMMUNE_MAX 4 606bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val);
1022#define HAL_SPUR_IMMUNE_MAX 7 607u32 ath9k_hw_reverse_bits(u32 val, u32 n);
1023#define HAL_FIRST_STEP_MAX 2 608bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
1024 609u16 ath9k_hw_computetxtime(struct ath_hw *ah, struct ath_rate_table *rates,
1025#define ATH9K_ANI_OFDM_TRIG_HIGH 500 610 u32 frameLen, u16 rateix, bool shortPreamble);
1026#define ATH9K_ANI_OFDM_TRIG_LOW 200 611void ath9k_hw_get_channel_centers(struct ath_hw *ah,
1027#define ATH9K_ANI_CCK_TRIG_HIGH 200 612 struct ath9k_channel *chan,
1028#define ATH9K_ANI_CCK_TRIG_LOW 100 613 struct chan_centers *centers);
1029#define ATH9K_ANI_NOISE_IMMUNE_LVL 4 614u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
1030#define ATH9K_ANI_USE_OFDM_WEAK_SIG true 615void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
1031#define ATH9K_ANI_CCK_WEAK_SIG_THR false 616bool ath9k_hw_phy_disable(struct ath_hw *ah);
1032#define ATH9K_ANI_SPUR_IMMUNE_LVL 7 617bool ath9k_hw_disable(struct ath_hw *ah);
1033#define ATH9K_ANI_FIRSTEP_LVL 0 618bool ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit);
1034#define ATH9K_ANI_RSSI_THR_HIGH 40 619void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac);
1035#define ATH9K_ANI_RSSI_THR_LOW 7 620void ath9k_hw_setopmode(struct ath_hw *ah);
1036#define ATH9K_ANI_PERIOD 100 621void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
1037 622void ath9k_hw_setbssidmask(struct ath_softc *sc);
1038#define AR_GPIOD_MASK 0x00001FFF 623void ath9k_hw_write_associd(struct ath_softc *sc);
1039#define AR_GPIO_BIT(_gpio) (1 << (_gpio)) 624u64 ath9k_hw_gettsf64(struct ath_hw *ah);
1040 625void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
1041#define HAL_EP_RND(x, mul) \ 626void ath9k_hw_reset_tsf(struct ath_hw *ah);
1042 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 627bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
1043#define BEACON_RSSI(ahp) \ 628bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us);
1044 HAL_EP_RND(ahp->ah_stats.ast_nodestats.ns_avgbrssi, \ 629void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode);
1045 ATH9K_RSSI_EP_MULTIPLIER) 630void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
1046 631void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1047#define ah_mibStats ah_stats.ast_mibstats 632 const struct ath9k_beacon_state *bs);
1048 633bool ath9k_hw_setpower(struct ath_hw *ah,
1049#define AH_TIMEOUT 100000 634 enum ath9k_power_mode mode);
1050#define AH_TIME_QUANTUM 10 635void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore);
1051 636
1052#define AR_KEYTABLE_SIZE 128 637/* Interrupt Handling */
1053#define POWER_UP_TIME 200000 638bool ath9k_hw_intrpend(struct ath_hw *ah);
1054 639bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked);
1055#define EXT_ADDITIVE (0x8000) 640enum ath9k_int ath9k_hw_intrget(struct ath_hw *ah);
1056#define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE) 641enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints);
1057#define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE) 642
1058#define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE) 643void ath9k_hw_btcoex_enable(struct ath_hw *ah);
1059
1060#define SUB_NUM_CTL_MODES_AT_5G_40 2
1061#define SUB_NUM_CTL_MODES_AT_2G_40 3
1062#define SPUR_RSSI_THRESH 40
1063
1064#define TU_TO_USEC(_tu) ((_tu) << 10)
1065
1066#define CAB_TIMEOUT_VAL 10
1067#define BEACON_TIMEOUT_VAL 10
1068#define MIN_BEACON_TIMEOUT_VAL 1
1069#define SLEEP_SLOP 3
1070
1071#define CCK_SIFS_TIME 10
1072#define CCK_PREAMBLE_BITS 144
1073#define CCK_PLCP_BITS 48
1074
1075#define OFDM_SIFS_TIME 16
1076#define OFDM_PREAMBLE_TIME 20
1077#define OFDM_PLCP_BITS 22
1078#define OFDM_SYMBOL_TIME 4
1079
1080#define OFDM_SIFS_TIME_HALF 32
1081#define OFDM_PREAMBLE_TIME_HALF 40
1082#define OFDM_PLCP_BITS_HALF 22
1083#define OFDM_SYMBOL_TIME_HALF 8
1084
1085#define OFDM_SIFS_TIME_QUARTER 64
1086#define OFDM_PREAMBLE_TIME_QUARTER 80
1087#define OFDM_PLCP_BITS_QUARTER 22
1088#define OFDM_SYMBOL_TIME_QUARTER 16
1089
1090u32 ath9k_hw_get_eeprom(struct ath_hal *ah,
1091 enum eeprom_param param);
1092 644
1093#endif 645#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-10 18:54:37 -0500