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path: root/drivers/net/wireless/ath9k/hw.c
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-rw-r--r--drivers/net/wireless/ath9k/hw.c8490
1 files changed, 1904 insertions, 6586 deletions
diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c
index 98bc25c9b3cf..34474edefc97 100644
--- a/drivers/net/wireless/ath9k/hw.c
+++ b/drivers/net/wireless/ath9k/hw.c
@@ -23,277 +23,93 @@
23#include "phy.h" 23#include "phy.h"
24#include "initvals.h" 24#include "initvals.h"
25 25
26static void ath9k_hw_iqcal_collect(struct ath_hal *ah);
27static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u8 numChains);
28static void ath9k_hw_adc_gaincal_collect(struct ath_hal *ah);
29static void ath9k_hw_adc_gaincal_calibrate(struct ath_hal *ah,
30 u8 numChains);
31static void ath9k_hw_adc_dccal_collect(struct ath_hal *ah);
32static void ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah,
33 u8 numChains);
34
35static const u8 CLOCK_RATE[] = { 40, 80, 22, 44, 88, 40 }; 26static const u8 CLOCK_RATE[] = { 40, 80, 22, 44, 88, 40 };
36static const int16_t NOISE_FLOOR[] = { -96, -93, -98, -96, -93, -96 };
37
38static const struct hal_percal_data iq_cal_multi_sample = {
39 IQ_MISMATCH_CAL,
40 MAX_CAL_SAMPLES,
41 PER_MIN_LOG_COUNT,
42 ath9k_hw_iqcal_collect,
43 ath9k_hw_iqcalibrate
44};
45static const struct hal_percal_data iq_cal_single_sample = {
46 IQ_MISMATCH_CAL,
47 MIN_CAL_SAMPLES,
48 PER_MAX_LOG_COUNT,
49 ath9k_hw_iqcal_collect,
50 ath9k_hw_iqcalibrate
51};
52static const struct hal_percal_data adc_gain_cal_multi_sample = {
53 ADC_GAIN_CAL,
54 MAX_CAL_SAMPLES,
55 PER_MIN_LOG_COUNT,
56 ath9k_hw_adc_gaincal_collect,
57 ath9k_hw_adc_gaincal_calibrate
58};
59static const struct hal_percal_data adc_gain_cal_single_sample = {
60 ADC_GAIN_CAL,
61 MIN_CAL_SAMPLES,
62 PER_MAX_LOG_COUNT,
63 ath9k_hw_adc_gaincal_collect,
64 ath9k_hw_adc_gaincal_calibrate
65};
66static const struct hal_percal_data adc_dc_cal_multi_sample = {
67 ADC_DC_CAL,
68 MAX_CAL_SAMPLES,
69 PER_MIN_LOG_COUNT,
70 ath9k_hw_adc_dccal_collect,
71 ath9k_hw_adc_dccal_calibrate
72};
73static const struct hal_percal_data adc_dc_cal_single_sample = {
74 ADC_DC_CAL,
75 MIN_CAL_SAMPLES,
76 PER_MAX_LOG_COUNT,
77 ath9k_hw_adc_dccal_collect,
78 ath9k_hw_adc_dccal_calibrate
79};
80static const struct hal_percal_data adc_init_dc_cal = {
81 ADC_DC_INIT_CAL,
82 MIN_CAL_SAMPLES,
83 INIT_LOG_COUNT,
84 ath9k_hw_adc_dccal_collect,
85 ath9k_hw_adc_dccal_calibrate
86};
87
88static struct ath9k_rate_table ar5416_11a_table = {
89 8,
90 {0},
91 {
92 {true, PHY_OFDM, 6000, 0x0b, 0x00, (0x80 | 12), 0},
93 {true, PHY_OFDM, 9000, 0x0f, 0x00, 18, 0},
94 {true, PHY_OFDM, 12000, 0x0a, 0x00, (0x80 | 24), 2},
95 {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 2},
96 {true, PHY_OFDM, 24000, 0x09, 0x00, (0x80 | 48), 4},
97 {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 4},
98 {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 4},
99 {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 4}
100 },
101};
102
103static struct ath9k_rate_table ar5416_11b_table = {
104 4,
105 {0},
106 {
107 {true, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
108 {true, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
109 {true, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 1},
110 {true, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 1}
111 },
112};
113
114static struct ath9k_rate_table ar5416_11g_table = {
115 12,
116 {0},
117 {
118 {true, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
119 {true, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
120 {true, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 2},
121 {true, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 3},
122
123 {false, PHY_OFDM, 6000, 0x0b, 0x00, 12, 4},
124 {false, PHY_OFDM, 9000, 0x0f, 0x00, 18, 4},
125 {true, PHY_OFDM, 12000, 0x0a, 0x00, 24, 6},
126 {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 6},
127 {true, PHY_OFDM, 24000, 0x09, 0x00, 48, 8},
128 {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 8},
129 {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 8},
130 {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 8}
131 },
132};
133
134static struct ath9k_rate_table ar5416_11ng_table = {
135 28,
136 {0},
137 {
138 {true, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
139 {true, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
140 {true, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 2},
141 {true, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 3},
142
143 {false, PHY_OFDM, 6000, 0x0b, 0x00, 12, 4},
144 {false, PHY_OFDM, 9000, 0x0f, 0x00, 18, 4},
145 {true, PHY_OFDM, 12000, 0x0a, 0x00, 24, 6},
146 {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 6},
147 {true, PHY_OFDM, 24000, 0x09, 0x00, 48, 8},
148 {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 8},
149 {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 8},
150 {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 8},
151 {true, PHY_HT, 6500, 0x80, 0x00, 0, 4},
152 {true, PHY_HT, 13000, 0x81, 0x00, 1, 6},
153 {true, PHY_HT, 19500, 0x82, 0x00, 2, 6},
154 {true, PHY_HT, 26000, 0x83, 0x00, 3, 8},
155 {true, PHY_HT, 39000, 0x84, 0x00, 4, 8},
156 {true, PHY_HT, 52000, 0x85, 0x00, 5, 8},
157 {true, PHY_HT, 58500, 0x86, 0x00, 6, 8},
158 {true, PHY_HT, 65000, 0x87, 0x00, 7, 8},
159 {true, PHY_HT, 13000, 0x88, 0x00, 8, 4},
160 {true, PHY_HT, 26000, 0x89, 0x00, 9, 6},
161 {true, PHY_HT, 39000, 0x8a, 0x00, 10, 6},
162 {true, PHY_HT, 52000, 0x8b, 0x00, 11, 8},
163 {true, PHY_HT, 78000, 0x8c, 0x00, 12, 8},
164 {true, PHY_HT, 104000, 0x8d, 0x00, 13, 8},
165 {true, PHY_HT, 117000, 0x8e, 0x00, 14, 8},
166 {true, PHY_HT, 130000, 0x8f, 0x00, 15, 8},
167 },
168};
169
170static struct ath9k_rate_table ar5416_11na_table = {
171 24,
172 {0},
173 {
174 {true, PHY_OFDM, 6000, 0x0b, 0x00, (0x80 | 12), 0},
175 {true, PHY_OFDM, 9000, 0x0f, 0x00, 18, 0},
176 {true, PHY_OFDM, 12000, 0x0a, 0x00, (0x80 | 24), 2},
177 {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 2},
178 {true, PHY_OFDM, 24000, 0x09, 0x00, (0x80 | 48), 4},
179 {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 4},
180 {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 4},
181 {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 4},
182 {true, PHY_HT, 6500, 0x80, 0x00, 0, 0},
183 {true, PHY_HT, 13000, 0x81, 0x00, 1, 2},
184 {true, PHY_HT, 19500, 0x82, 0x00, 2, 2},
185 {true, PHY_HT, 26000, 0x83, 0x00, 3, 4},
186 {true, PHY_HT, 39000, 0x84, 0x00, 4, 4},
187 {true, PHY_HT, 52000, 0x85, 0x00, 5, 4},
188 {true, PHY_HT, 58500, 0x86, 0x00, 6, 4},
189 {true, PHY_HT, 65000, 0x87, 0x00, 7, 4},
190 {true, PHY_HT, 13000, 0x88, 0x00, 8, 0},
191 {true, PHY_HT, 26000, 0x89, 0x00, 9, 2},
192 {true, PHY_HT, 39000, 0x8a, 0x00, 10, 2},
193 {true, PHY_HT, 52000, 0x8b, 0x00, 11, 4},
194 {true, PHY_HT, 78000, 0x8c, 0x00, 12, 4},
195 {true, PHY_HT, 104000, 0x8d, 0x00, 13, 4},
196 {true, PHY_HT, 117000, 0x8e, 0x00, 14, 4},
197 {true, PHY_HT, 130000, 0x8f, 0x00, 15, 4},
198 },
199};
200
201static enum wireless_mode ath9k_hw_chan2wmode(struct ath_hal *ah,
202 const struct ath9k_channel *chan)
203{
204 if (IS_CHAN_CCK(chan))
205 return ATH9K_MODE_11A;
206 if (IS_CHAN_G(chan))
207 return ATH9K_MODE_11G;
208 return ATH9K_MODE_11A;
209}
210 27
211static bool ath9k_hw_wait(struct ath_hal *ah, 28extern struct hal_percal_data iq_cal_multi_sample;
212 u32 reg, 29extern struct hal_percal_data iq_cal_single_sample;
213 u32 mask, 30extern struct hal_percal_data adc_gain_cal_multi_sample;
214 u32 val) 31extern struct hal_percal_data adc_gain_cal_single_sample;
215{ 32extern struct hal_percal_data adc_dc_cal_multi_sample;
216 int i; 33extern struct hal_percal_data adc_dc_cal_single_sample;
34extern struct hal_percal_data adc_init_dc_cal;
217 35
218 for (i = 0; i < (AH_TIMEOUT / AH_TIME_QUANTUM); i++) { 36static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type);
219 if ((REG_READ(ah, reg) & mask) == val) 37static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
220 return true; 38 enum ath9k_ht_macmode macmode);
39static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
40 struct ar5416_eeprom_def *pEepData,
41 u32 reg, u32 value);
42static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan);
43static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan);
221 44
222 udelay(AH_TIME_QUANTUM); 45/********************/
223 } 46/* Helper Functions */
224 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO, 47/********************/
225 "%s: timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
226 __func__, reg, REG_READ(ah, reg), mask, val);
227 return false;
228}
229 48
230static bool ath9k_hw_eeprom_read(struct ath_hal *ah, u32 off, 49static u32 ath9k_hw_mac_usec(struct ath_hal *ah, u32 clks)
231 u16 *data)
232{ 50{
233 (void) REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S)); 51 if (ah->ah_curchan != NULL)
234 52 return clks / CLOCK_RATE[ath9k_hw_chan2wmode(ah, ah->ah_curchan)];
235 if (!ath9k_hw_wait(ah, 53 else
236 AR_EEPROM_STATUS_DATA, 54 return clks / CLOCK_RATE[ATH9K_MODE_11B];
237 AR_EEPROM_STATUS_DATA_BUSY |
238 AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0)) {
239 return false;
240 }
241
242 *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA),
243 AR_EEPROM_STATUS_DATA_VAL);
244
245 return true;
246} 55}
247 56
248static int ath9k_hw_flash_map(struct ath_hal *ah) 57static u32 ath9k_hw_mac_to_usec(struct ath_hal *ah, u32 clks)
249{ 58{
250 struct ath_hal_5416 *ahp = AH5416(ah); 59 struct ath9k_channel *chan = ah->ah_curchan;
251
252 ahp->ah_cal_mem = ioremap(AR5416_EEPROM_START_ADDR, AR5416_EEPROM_MAX);
253 60
254 if (!ahp->ah_cal_mem) { 61 if (chan && IS_CHAN_HT40(chan))
255 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 62 return ath9k_hw_mac_usec(ah, clks) / 2;
256 "%s: cannot remap eeprom region \n", __func__); 63 else
257 return -EIO; 64 return ath9k_hw_mac_usec(ah, clks);
258 } 65}
259 66
260 return 0; 67static u32 ath9k_hw_mac_clks(struct ath_hal *ah, u32 usecs)
68{
69 if (ah->ah_curchan != NULL)
70 return usecs * CLOCK_RATE[ath9k_hw_chan2wmode(ah,
71 ah->ah_curchan)];
72 else
73 return usecs * CLOCK_RATE[ATH9K_MODE_11B];
261} 74}
262 75
263static bool ath9k_hw_flash_read(struct ath_hal *ah, u32 off, 76static u32 ath9k_hw_mac_to_clks(struct ath_hal *ah, u32 usecs)
264 u16 *data)
265{ 77{
266 struct ath_hal_5416 *ahp = AH5416(ah); 78 struct ath9k_channel *chan = ah->ah_curchan;
267 79
268 *data = ioread16(ahp->ah_cal_mem + off); 80 if (chan && IS_CHAN_HT40(chan))
269 return true; 81 return ath9k_hw_mac_clks(ah, usecs) * 2;
82 else
83 return ath9k_hw_mac_clks(ah, usecs);
270} 84}
271 85
272static void ath9k_hw_read_revisions(struct ath_hal *ah) 86enum wireless_mode ath9k_hw_chan2wmode(struct ath_hal *ah,
87 const struct ath9k_channel *chan)
273{ 88{
274 u32 val; 89 if (IS_CHAN_B(chan))
275 90 return ATH9K_MODE_11B;
276 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; 91 if (IS_CHAN_G(chan))
92 return ATH9K_MODE_11G;
277 93
278 if (val == 0xFF) { 94 return ATH9K_MODE_11A;
279 val = REG_READ(ah, AR_SREV); 95}
280 96
281 ah->ah_macVersion = 97bool ath9k_hw_wait(struct ath_hal *ah, u32 reg, u32 mask, u32 val)
282 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 98{
99 int i;
283 100
284 ah->ah_macRev = MS(val, AR_SREV_REVISION2); 101 for (i = 0; i < (AH_TIMEOUT / AH_TIME_QUANTUM); i++) {
285 ah->ah_isPciExpress = 102 if ((REG_READ(ah, reg) & mask) == val)
286 (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 103 return true;
287 104
288 } else { 105 udelay(AH_TIME_QUANTUM);
289 if (!AR_SREV_9100(ah)) 106 }
290 ah->ah_macVersion = MS(val, AR_SREV_VERSION);
291 107
292 ah->ah_macRev = val & AR_SREV_REVISION; 108 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
109 "timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
110 reg, REG_READ(ah, reg), mask, val);
293 111
294 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE) 112 return false;
295 ah->ah_isPciExpress = true;
296 }
297} 113}
298 114
299u32 ath9k_hw_reverse_bits(u32 val, u32 n) 115u32 ath9k_hw_reverse_bits(u32 val, u32 n)
@@ -308,596 +124,215 @@ u32 ath9k_hw_reverse_bits(u32 val, u32 n)
308 return retval; 124 return retval;
309} 125}
310 126
311static void ath9k_hw_set_defaults(struct ath_hal *ah) 127bool ath9k_get_channel_edges(struct ath_hal *ah,
128 u16 flags, u16 *low,
129 u16 *high)
312{ 130{
313 int i; 131 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
314
315 ah->ah_config.dma_beacon_response_time = 2;
316 ah->ah_config.sw_beacon_response_time = 10;
317 ah->ah_config.additional_swba_backoff = 0;
318 ah->ah_config.ack_6mb = 0x0;
319 ah->ah_config.cwm_ignore_extcca = 0;
320 ah->ah_config.pcie_powersave_enable = 0;
321 ah->ah_config.pcie_l1skp_enable = 0;
322 ah->ah_config.pcie_clock_req = 0;
323 ah->ah_config.pcie_power_reset = 0x100;
324 ah->ah_config.pcie_restore = 0;
325 ah->ah_config.pcie_waen = 0;
326 ah->ah_config.analog_shiftreg = 1;
327 ah->ah_config.ht_enable = 1;
328 ah->ah_config.ofdm_trig_low = 200;
329 ah->ah_config.ofdm_trig_high = 500;
330 ah->ah_config.cck_trig_high = 200;
331 ah->ah_config.cck_trig_low = 100;
332 ah->ah_config.enable_ani = 1;
333 ah->ah_config.noise_immunity_level = 4;
334 ah->ah_config.ofdm_weaksignal_det = 1;
335 ah->ah_config.cck_weaksignal_thr = 0;
336 ah->ah_config.spur_immunity_level = 2;
337 ah->ah_config.firstep_level = 0;
338 ah->ah_config.rssi_thr_high = 40;
339 ah->ah_config.rssi_thr_low = 7;
340 ah->ah_config.diversity_control = 0;
341 ah->ah_config.antenna_switch_swap = 0;
342 132
343 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 133 if (flags & CHANNEL_5GHZ) {
344 ah->ah_config.spurchans[i][0] = AR_NO_SPUR; 134 *low = pCap->low_5ghz_chan;
345 ah->ah_config.spurchans[i][1] = AR_NO_SPUR; 135 *high = pCap->high_5ghz_chan;
136 return true;
346 } 137 }
347 138 if ((flags & CHANNEL_2GHZ)) {
348 ah->ah_config.intr_mitigation = 0; 139 *low = pCap->low_2ghz_chan;
349} 140 *high = pCap->high_2ghz_chan;
350 141 return true;
351static void ath9k_hw_override_ini(struct ath_hal *ah,
352 struct ath9k_channel *chan)
353{
354 if (!AR_SREV_5416_V20_OR_LATER(ah)
355 || AR_SREV_9280_10_OR_LATER(ah))
356 return;
357
358 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
359}
360
361static void ath9k_hw_init_bb(struct ath_hal *ah,
362 struct ath9k_channel *chan)
363{
364 u32 synthDelay;
365
366 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
367 if (IS_CHAN_CCK(chan))
368 synthDelay = (4 * synthDelay) / 22;
369 else
370 synthDelay /= 10;
371
372 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
373
374 udelay(synthDelay + BASE_ACTIVATE_DELAY);
375}
376
377static void ath9k_hw_init_interrupt_masks(struct ath_hal *ah,
378 enum ath9k_opmode opmode)
379{
380 struct ath_hal_5416 *ahp = AH5416(ah);
381
382 ahp->ah_maskReg = AR_IMR_TXERR |
383 AR_IMR_TXURN |
384 AR_IMR_RXERR |
385 AR_IMR_RXORN |
386 AR_IMR_BCNMISC;
387
388 if (ahp->ah_intrMitigation)
389 ahp->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
390 else
391 ahp->ah_maskReg |= AR_IMR_RXOK;
392
393 ahp->ah_maskReg |= AR_IMR_TXOK;
394
395 if (opmode == ATH9K_M_HOSTAP)
396 ahp->ah_maskReg |= AR_IMR_MIB;
397
398 REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
399 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
400
401 if (!AR_SREV_9100(ah)) {
402 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
403 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
404 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
405 } 142 }
143 return false;
406} 144}
407 145
408static void ath9k_hw_init_qos(struct ath_hal *ah) 146u16 ath9k_hw_computetxtime(struct ath_hal *ah,
409{ 147 struct ath_rate_table *rates,
410 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); 148 u32 frameLen, u16 rateix,
411 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); 149 bool shortPreamble)
412
413 REG_WRITE(ah, AR_QOS_NO_ACK,
414 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
415 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
416 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
417
418 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
419 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
420 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
421 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
422 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
423}
424
425static void ath9k_hw_analog_shift_rmw(struct ath_hal *ah,
426 u32 reg,
427 u32 mask,
428 u32 shift,
429 u32 val)
430{
431 u32 regVal;
432
433 regVal = REG_READ(ah, reg) & ~mask;
434 regVal |= (val << shift) & mask;
435
436 REG_WRITE(ah, reg, regVal);
437
438 if (ah->ah_config.analog_shiftreg)
439 udelay(100);
440
441 return;
442}
443
444static u8 ath9k_hw_get_num_ant_config(struct ath_hal_5416 *ahp,
445 enum ieee80211_band freq_band)
446{ 150{
447 struct ar5416_eeprom *eep = &ahp->ah_eeprom; 151 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
448 struct modal_eep_header *pModal = 152 u32 kbps;
449 &(eep->modalHeader[IEEE80211_BAND_5GHZ == freq_band]);
450 struct base_eep_header *pBase = &eep->baseEepHeader;
451 u8 num_ant_config;
452
453 num_ant_config = 1;
454
455 if (pBase->version >= 0x0E0D)
456 if (pModal->useAnt1)
457 num_ant_config += 1;
458
459 return num_ant_config;
460}
461 153
462static int 154 kbps = rates->info[rateix].ratekbps;
463ath9k_hw_get_eeprom_antenna_cfg(struct ath_hal_5416 *ahp,
464 struct ath9k_channel *chan,
465 u8 index,
466 u16 *config)
467{
468 struct ar5416_eeprom *eep = &ahp->ah_eeprom;
469 struct modal_eep_header *pModal =
470 &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
471 struct base_eep_header *pBase = &eep->baseEepHeader;
472 155
473 switch (index) { 156 if (kbps == 0)
474 case 0:
475 *config = pModal->antCtrlCommon & 0xFFFF;
476 return 0; 157 return 0;
477 case 1: 158
478 if (pBase->version >= 0x0E0D) { 159 switch (rates->info[rateix].phy) {
479 if (pModal->useAnt1) { 160 case WLAN_RC_PHY_CCK:
480 *config = 161 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
481 ((pModal->antCtrlCommon & 0xFFFF0000) >> 16); 162 if (shortPreamble && rates->info[rateix].short_preamble)
482 return 0; 163 phyTime >>= 1;
483 } 164 numBits = frameLen << 3;
165 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
166 break;
167 case WLAN_RC_PHY_OFDM:
168 if (ah->ah_curchan && IS_CHAN_QUARTER_RATE(ah->ah_curchan)) {
169 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
170 numBits = OFDM_PLCP_BITS + (frameLen << 3);
171 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
172 txTime = OFDM_SIFS_TIME_QUARTER
173 + OFDM_PREAMBLE_TIME_QUARTER
174 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
175 } else if (ah->ah_curchan &&
176 IS_CHAN_HALF_RATE(ah->ah_curchan)) {
177 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
178 numBits = OFDM_PLCP_BITS + (frameLen << 3);
179 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
180 txTime = OFDM_SIFS_TIME_HALF +
181 OFDM_PREAMBLE_TIME_HALF
182 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
183 } else {
184 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
185 numBits = OFDM_PLCP_BITS + (frameLen << 3);
186 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
187 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
188 + (numSymbols * OFDM_SYMBOL_TIME);
484 } 189 }
485 break; 190 break;
486 default: 191 default:
192 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
193 "Unknown phy %u (rate ix %u)\n",
194 rates->info[rateix].phy, rateix);
195 txTime = 0;
487 break; 196 break;
488 } 197 }
489 198
490 return -EINVAL; 199 return txTime;
491}
492
493static inline bool ath9k_hw_nvram_read(struct ath_hal *ah,
494 u32 off,
495 u16 *data)
496{
497 if (ath9k_hw_use_flash(ah))
498 return ath9k_hw_flash_read(ah, off, data);
499 else
500 return ath9k_hw_eeprom_read(ah, off, data);
501} 200}
502 201
503static bool ath9k_hw_fill_eeprom(struct ath_hal *ah) 202u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags)
504{ 203{
505 struct ath_hal_5416 *ahp = AH5416(ah); 204 if (flags & CHANNEL_2GHZ) {
506 struct ar5416_eeprom *eep = &ahp->ah_eeprom; 205 if (freq == 2484)
507 u16 *eep_data; 206 return 14;
508 int addr, ar5416_eep_start_loc = 0; 207 if (freq < 2484)
509 208 return (freq - 2407) / 5;
510 if (!ath9k_hw_use_flash(ah)) { 209 else
511 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 210 return 15 + ((freq - 2512) / 20);
512 "%s: Reading from EEPROM, not flash\n", __func__); 211 } else if (flags & CHANNEL_5GHZ) {
513 ar5416_eep_start_loc = 256; 212 if (ath9k_regd_is_public_safety_sku(ah) &&
514 } 213 IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
515 if (AR_SREV_9100(ah)) 214 return ((freq * 10) +
516 ar5416_eep_start_loc = 256; 215 (((freq % 5) == 2) ? 5 : 0) - 49400) / 5;
517 216 } else if ((flags & CHANNEL_A) && (freq <= 5000)) {
518 eep_data = (u16 *) eep; 217 return (freq - 4000) / 5;
519 for (addr = 0; 218 } else {
520 addr < sizeof(struct ar5416_eeprom) / sizeof(u16); 219 return (freq - 5000) / 5;
521 addr++) { 220 }
522 if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc, 221 } else {
523 eep_data)) { 222 if (freq == 2484)
524 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 223 return 14;
525 "%s: Unable to read eeprom region \n", 224 if (freq < 2484)
526 __func__); 225 return (freq - 2407) / 5;
527 return false; 226 if (freq < 5000) {
227 if (ath9k_regd_is_public_safety_sku(ah)
228 && IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
229 return ((freq * 10) +
230 (((freq % 5) ==
231 2) ? 5 : 0) - 49400) / 5;
232 } else if (freq > 4900) {
233 return (freq - 4000) / 5;
234 } else {
235 return 15 + ((freq - 2512) / 20);
236 }
528 } 237 }
529 eep_data++; 238 return (freq - 5000) / 5;
530 } 239 }
531 return true;
532} 240}
533 241
534/* XXX: Clean me up, make me more legible */ 242void ath9k_hw_get_channel_centers(struct ath_hal *ah,
535static bool 243 struct ath9k_channel *chan,
536ath9k_hw_eeprom_set_board_values(struct ath_hal *ah, 244 struct chan_centers *centers)
537 struct ath9k_channel *chan)
538{ 245{
539 struct modal_eep_header *pModal; 246 int8_t extoff;
540 int i, regChainOffset;
541 struct ath_hal_5416 *ahp = AH5416(ah); 247 struct ath_hal_5416 *ahp = AH5416(ah);
542 struct ar5416_eeprom *eep = &ahp->ah_eeprom;
543 u8 txRxAttenLocal;
544 u16 ant_config;
545 248
546 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]); 249 if (!IS_CHAN_HT40(chan)) {
250 centers->ctl_center = centers->ext_center =
251 centers->synth_center = chan->channel;
252 return;
253 }
547 254
548 txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44; 255 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
256 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
257 centers->synth_center =
258 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
259 extoff = 1;
260 } else {
261 centers->synth_center =
262 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
263 extoff = -1;
264 }
549 265
550 ath9k_hw_get_eeprom_antenna_cfg(ahp, chan, 1, &ant_config); 266 centers->ctl_center =
551 REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config); 267 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
268 centers->ext_center =
269 centers->synth_center + (extoff *
270 ((ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
271 HT40_CHANNEL_CENTER_SHIFT : 15));
552 272
553 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 273}
554 if (AR_SREV_9280(ah)) {
555 if (i >= 2)
556 break;
557 }
558 274
559 if (AR_SREV_5416_V20_OR_LATER(ah) && 275/******************/
560 (ahp->ah_rxchainmask == 5 || ahp->ah_txchainmask == 5) 276/* Chip Revisions */
561 && (i != 0)) 277/******************/
562 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
563 else
564 regChainOffset = i * 0x1000;
565
566 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
567 pModal->antCtrlChain[i]);
568
569 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
570 (REG_READ(ah,
571 AR_PHY_TIMING_CTRL4(0) +
572 regChainOffset) &
573 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
574 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
575 SM(pModal->iqCalICh[i],
576 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
577 SM(pModal->iqCalQCh[i],
578 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
579
580 if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) {
581 if ((eep->baseEepHeader.version &
582 AR5416_EEP_VER_MINOR_MASK) >=
583 AR5416_EEP_MINOR_VER_3) {
584 txRxAttenLocal = pModal->txRxAttenCh[i];
585 if (AR_SREV_9280_10_OR_LATER(ah)) {
586 REG_RMW_FIELD(ah,
587 AR_PHY_GAIN_2GHZ +
588 regChainOffset,
589 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
590 pModal->
591 bswMargin[i]);
592 REG_RMW_FIELD(ah,
593 AR_PHY_GAIN_2GHZ +
594 regChainOffset,
595 AR_PHY_GAIN_2GHZ_XATTEN1_DB,
596 pModal->
597 bswAtten[i]);
598 REG_RMW_FIELD(ah,
599 AR_PHY_GAIN_2GHZ +
600 regChainOffset,
601 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
602 pModal->
603 xatten2Margin[i]);
604 REG_RMW_FIELD(ah,
605 AR_PHY_GAIN_2GHZ +
606 regChainOffset,
607 AR_PHY_GAIN_2GHZ_XATTEN2_DB,
608 pModal->
609 xatten2Db[i]);
610 } else {
611 REG_WRITE(ah,
612 AR_PHY_GAIN_2GHZ +
613 regChainOffset,
614 (REG_READ(ah,
615 AR_PHY_GAIN_2GHZ +
616 regChainOffset) &
617 ~AR_PHY_GAIN_2GHZ_BSW_MARGIN)
618 | SM(pModal->
619 bswMargin[i],
620 AR_PHY_GAIN_2GHZ_BSW_MARGIN));
621 REG_WRITE(ah,
622 AR_PHY_GAIN_2GHZ +
623 regChainOffset,
624 (REG_READ(ah,
625 AR_PHY_GAIN_2GHZ +
626 regChainOffset) &
627 ~AR_PHY_GAIN_2GHZ_BSW_ATTEN)
628 | SM(pModal->bswAtten[i],
629 AR_PHY_GAIN_2GHZ_BSW_ATTEN));
630 }
631 }
632 if (AR_SREV_9280_10_OR_LATER(ah)) {
633 REG_RMW_FIELD(ah,
634 AR_PHY_RXGAIN +
635 regChainOffset,
636 AR9280_PHY_RXGAIN_TXRX_ATTEN,
637 txRxAttenLocal);
638 REG_RMW_FIELD(ah,
639 AR_PHY_RXGAIN +
640 regChainOffset,
641 AR9280_PHY_RXGAIN_TXRX_MARGIN,
642 pModal->rxTxMarginCh[i]);
643 } else {
644 REG_WRITE(ah,
645 AR_PHY_RXGAIN + regChainOffset,
646 (REG_READ(ah,
647 AR_PHY_RXGAIN +
648 regChainOffset) &
649 ~AR_PHY_RXGAIN_TXRX_ATTEN) |
650 SM(txRxAttenLocal,
651 AR_PHY_RXGAIN_TXRX_ATTEN));
652 REG_WRITE(ah,
653 AR_PHY_GAIN_2GHZ +
654 regChainOffset,
655 (REG_READ(ah,
656 AR_PHY_GAIN_2GHZ +
657 regChainOffset) &
658 ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
659 SM(pModal->rxTxMarginCh[i],
660 AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
661 }
662 }
663 }
664 278
665 if (AR_SREV_9280_10_OR_LATER(ah)) { 279static void ath9k_hw_read_revisions(struct ath_hal *ah)
666 if (IS_CHAN_2GHZ(chan)) { 280{
667 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0, 281 u32 val;
668 AR_AN_RF2G1_CH0_OB,
669 AR_AN_RF2G1_CH0_OB_S,
670 pModal->ob);
671 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
672 AR_AN_RF2G1_CH0_DB,
673 AR_AN_RF2G1_CH0_DB_S,
674 pModal->db);
675 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
676 AR_AN_RF2G1_CH1_OB,
677 AR_AN_RF2G1_CH1_OB_S,
678 pModal->ob_ch1);
679 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
680 AR_AN_RF2G1_CH1_DB,
681 AR_AN_RF2G1_CH1_DB_S,
682 pModal->db_ch1);
683 } else {
684 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
685 AR_AN_RF5G1_CH0_OB5,
686 AR_AN_RF5G1_CH0_OB5_S,
687 pModal->ob);
688 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
689 AR_AN_RF5G1_CH0_DB5,
690 AR_AN_RF5G1_CH0_DB5_S,
691 pModal->db);
692 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
693 AR_AN_RF5G1_CH1_OB5,
694 AR_AN_RF5G1_CH1_OB5_S,
695 pModal->ob_ch1);
696 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
697 AR_AN_RF5G1_CH1_DB5,
698 AR_AN_RF5G1_CH1_DB5_S,
699 pModal->db_ch1);
700 }
701 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
702 AR_AN_TOP2_XPABIAS_LVL,
703 AR_AN_TOP2_XPABIAS_LVL_S,
704 pModal->xpaBiasLvl);
705 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
706 AR_AN_TOP2_LOCALBIAS,
707 AR_AN_TOP2_LOCALBIAS_S,
708 pModal->local_bias);
709 DPRINTF(ah->ah_sc, ATH_DBG_ANY, "ForceXPAon: %d\n",
710 pModal->force_xpaon);
711 REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
712 pModal->force_xpaon);
713 }
714 282
715 REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, 283 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
716 pModal->switchSettling);
717 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
718 pModal->adcDesiredSize);
719 284
720 if (!AR_SREV_9280_10_OR_LATER(ah)) 285 if (val == 0xFF) {
721 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, 286 val = REG_READ(ah, AR_SREV);
722 AR_PHY_DESIRED_SZ_PGA, 287 ah->ah_macVersion = (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
723 pModal->pgaDesiredSize); 288 ah->ah_macRev = MS(val, AR_SREV_REVISION2);
724 289 ah->ah_isPciExpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
725 REG_WRITE(ah, AR_PHY_RF_CTL4,
726 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
727 | SM(pModal->txEndToXpaOff,
728 AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
729 | SM(pModal->txFrameToXpaOn,
730 AR_PHY_RF_CTL4_FRAME_XPAA_ON)
731 | SM(pModal->txFrameToXpaOn,
732 AR_PHY_RF_CTL4_FRAME_XPAB_ON));
733
734 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
735 pModal->txEndToRxOn);
736 if (AR_SREV_9280_10_OR_LATER(ah)) {
737 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
738 pModal->thresh62);
739 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
740 AR_PHY_EXT_CCA0_THRESH62,
741 pModal->thresh62);
742 } else { 290 } else {
743 REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62, 291 if (!AR_SREV_9100(ah))
744 pModal->thresh62); 292 ah->ah_macVersion = MS(val, AR_SREV_VERSION);
745 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
746 AR_PHY_EXT_CCA_THRESH62,
747 pModal->thresh62);
748 }
749 293
750 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 294 ah->ah_macRev = val & AR_SREV_REVISION;
751 AR5416_EEP_MINOR_VER_2) {
752 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
753 AR_PHY_TX_END_DATA_START,
754 pModal->txFrameToDataStart);
755 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
756 pModal->txFrameToPaOn);
757 }
758 295
759 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 296 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE)
760 AR5416_EEP_MINOR_VER_3) { 297 ah->ah_isPciExpress = true;
761 if (IS_CHAN_HT40(chan))
762 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
763 AR_PHY_SETTLING_SWITCH,
764 pModal->swSettleHt40);
765 } 298 }
766
767 return true;
768} 299}
769 300
770static int ath9k_hw_check_eeprom(struct ath_hal *ah) 301static int ath9k_hw_get_radiorev(struct ath_hal *ah)
771{ 302{
772 u32 sum = 0, el; 303 u32 val;
773 u16 *eepdata;
774 int i; 304 int i;
775 struct ath_hal_5416 *ahp = AH5416(ah);
776 bool need_swap = false;
777 struct ar5416_eeprom *eep =
778 (struct ar5416_eeprom *) &ahp->ah_eeprom;
779
780 if (!ath9k_hw_use_flash(ah)) {
781 u16 magic, magic2;
782 int addr;
783
784 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
785 &magic)) {
786 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
787 "%s: Reading Magic # failed\n", __func__);
788 return false;
789 }
790 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "%s: Read Magic = 0x%04X\n",
791 __func__, magic);
792
793 if (magic != AR5416_EEPROM_MAGIC) {
794 magic2 = swab16(magic);
795
796 if (magic2 == AR5416_EEPROM_MAGIC) {
797 need_swap = true;
798 eepdata = (u16 *) (&ahp->ah_eeprom);
799
800 for (addr = 0;
801 addr <
802 sizeof(struct ar5416_eeprom) /
803 sizeof(u16); addr++) {
804 u16 temp;
805
806 temp = swab16(*eepdata);
807 *eepdata = temp;
808 eepdata++;
809
810 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
811 "0x%04X ", *eepdata);
812 if (((addr + 1) % 6) == 0)
813 DPRINTF(ah->ah_sc,
814 ATH_DBG_EEPROM,
815 "\n");
816 }
817 } else {
818 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
819 "Invalid EEPROM Magic. "
820 "endianness missmatch.\n");
821 return -EINVAL;
822 }
823 }
824 }
825 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n",
826 need_swap ? "True" : "False");
827
828 if (need_swap)
829 el = swab16(ahp->ah_eeprom.baseEepHeader.length);
830 else
831 el = ahp->ah_eeprom.baseEepHeader.length;
832
833 if (el > sizeof(struct ar5416_eeprom))
834 el = sizeof(struct ar5416_eeprom) / sizeof(u16);
835 else
836 el = el / sizeof(u16);
837
838 eepdata = (u16 *) (&ahp->ah_eeprom);
839
840 for (i = 0; i < el; i++)
841 sum ^= *eepdata++;
842
843 if (need_swap) {
844 u32 integer, j;
845 u16 word;
846 305
847 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 306 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
848 "EEPROM Endianness is not native.. Changing \n");
849
850 word = swab16(eep->baseEepHeader.length);
851 eep->baseEepHeader.length = word;
852
853 word = swab16(eep->baseEepHeader.checksum);
854 eep->baseEepHeader.checksum = word;
855
856 word = swab16(eep->baseEepHeader.version);
857 eep->baseEepHeader.version = word;
858
859 word = swab16(eep->baseEepHeader.regDmn[0]);
860 eep->baseEepHeader.regDmn[0] = word;
861
862 word = swab16(eep->baseEepHeader.regDmn[1]);
863 eep->baseEepHeader.regDmn[1] = word;
864
865 word = swab16(eep->baseEepHeader.rfSilent);
866 eep->baseEepHeader.rfSilent = word;
867
868 word = swab16(eep->baseEepHeader.blueToothOptions);
869 eep->baseEepHeader.blueToothOptions = word;
870 307
871 word = swab16(eep->baseEepHeader.deviceCap); 308 for (i = 0; i < 8; i++)
872 eep->baseEepHeader.deviceCap = word; 309 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
310 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
311 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
873 312
874 for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) { 313 return ath9k_hw_reverse_bits(val, 8);
875 struct modal_eep_header *pModal = 314}
876 &eep->modalHeader[j];
877 integer = swab32(pModal->antCtrlCommon);
878 pModal->antCtrlCommon = integer;
879 315
880 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 316/************************************/
881 integer = swab32(pModal->antCtrlChain[i]); 317/* HW Attach, Detach, Init Routines */
882 pModal->antCtrlChain[i] = integer; 318/************************************/
883 }
884 319
885 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 320static void ath9k_hw_disablepcie(struct ath_hal *ah)
886 word = swab16(pModal->spurChans[i].spurChan); 321{
887 pModal->spurChans[i].spurChan = word; 322 if (!AR_SREV_9100(ah))
888 } 323 return;
889 }
890 }
891 324
892 if (sum != 0xffff || ar5416_get_eep_ver(ahp) != AR5416_EEP_VER || 325 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
893 ar5416_get_eep_rev(ahp) < AR5416_EEP_NO_BACK_VER) { 326 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
894 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 327 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
895 "Bad EEPROM checksum 0x%x or revision 0x%04x\n", 328 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
896 sum, ar5416_get_eep_ver(ahp)); 329 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
897 return -EINVAL; 330 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
898 } 331 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
332 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
333 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
899 334
900 return 0; 335 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
901} 336}
902 337
903static bool ath9k_hw_chip_test(struct ath_hal *ah) 338static bool ath9k_hw_chip_test(struct ath_hal *ah)
@@ -905,9 +340,9 @@ static bool ath9k_hw_chip_test(struct ath_hal *ah)
905 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) }; 340 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
906 u32 regHold[2]; 341 u32 regHold[2];
907 u32 patternData[4] = { 0x55555555, 342 u32 patternData[4] = { 0x55555555,
908 0xaaaaaaaa, 343 0xaaaaaaaa,
909 0x66666666, 344 0x66666666,
910 0x99999999 }; 345 0x99999999 };
911 int i, j; 346 int i, j;
912 347
913 for (i = 0; i < 2; i++) { 348 for (i = 0; i < 2; i++) {
@@ -921,9 +356,9 @@ static bool ath9k_hw_chip_test(struct ath_hal *ah)
921 rdData = REG_READ(ah, addr); 356 rdData = REG_READ(ah, addr);
922 if (rdData != wrData) { 357 if (rdData != wrData) {
923 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, 358 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
924 "%s: address test failed " 359 "address test failed "
925 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 360 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
926 __func__, addr, wrData, rdData); 361 addr, wrData, rdData);
927 return false; 362 return false;
928 } 363 }
929 } 364 }
@@ -933,9 +368,9 @@ static bool ath9k_hw_chip_test(struct ath_hal *ah)
933 rdData = REG_READ(ah, addr); 368 rdData = REG_READ(ah, addr);
934 if (wrData != rdData) { 369 if (wrData != rdData) {
935 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, 370 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
936 "%s: address test failed " 371 "address test failed "
937 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 372 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
938 __func__, addr, wrData, rdData); 373 addr, wrData, rdData);
939 return false; 374 return false;
940 } 375 }
941 } 376 }
@@ -945,213 +380,65 @@ static bool ath9k_hw_chip_test(struct ath_hal *ah)
945 return true; 380 return true;
946} 381}
947 382
948u32 ath9k_hw_getrxfilter(struct ath_hal *ah) 383static const char *ath9k_hw_devname(u16 devid)
949{
950 u32 bits = REG_READ(ah, AR_RX_FILTER);
951 u32 phybits = REG_READ(ah, AR_PHY_ERR);
952
953 if (phybits & AR_PHY_ERR_RADAR)
954 bits |= ATH9K_RX_FILTER_PHYRADAR;
955 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
956 bits |= ATH9K_RX_FILTER_PHYERR;
957 return bits;
958}
959
960void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits)
961{
962 u32 phybits;
963
964 REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
965 phybits = 0;
966 if (bits & ATH9K_RX_FILTER_PHYRADAR)
967 phybits |= AR_PHY_ERR_RADAR;
968 if (bits & ATH9K_RX_FILTER_PHYERR)
969 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
970 REG_WRITE(ah, AR_PHY_ERR, phybits);
971
972 if (phybits)
973 REG_WRITE(ah, AR_RXCFG,
974 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
975 else
976 REG_WRITE(ah, AR_RXCFG,
977 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
978}
979
980bool ath9k_hw_setcapability(struct ath_hal *ah,
981 enum ath9k_capability_type type,
982 u32 capability,
983 u32 setting,
984 int *status)
985{
986 struct ath_hal_5416 *ahp = AH5416(ah);
987 u32 v;
988
989 switch (type) {
990 case ATH9K_CAP_TKIP_MIC:
991 if (setting)
992 ahp->ah_staId1Defaults |=
993 AR_STA_ID1_CRPT_MIC_ENABLE;
994 else
995 ahp->ah_staId1Defaults &=
996 ~AR_STA_ID1_CRPT_MIC_ENABLE;
997 return true;
998 case ATH9K_CAP_DIVERSITY:
999 v = REG_READ(ah, AR_PHY_CCK_DETECT);
1000 if (setting)
1001 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
1002 else
1003 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
1004 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
1005 return true;
1006 case ATH9K_CAP_MCAST_KEYSRCH:
1007 if (setting)
1008 ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH;
1009 else
1010 ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH;
1011 return true;
1012 case ATH9K_CAP_TSF_ADJUST:
1013 if (setting)
1014 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
1015 else
1016 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
1017 return true;
1018 default:
1019 return false;
1020 }
1021}
1022
1023void ath9k_hw_dmaRegDump(struct ath_hal *ah)
1024{ 384{
1025 u32 val[ATH9K_NUM_DMA_DEBUG_REGS]; 385 switch (devid) {
1026 int qcuOffset = 0, dcuOffset = 0; 386 case AR5416_DEVID_PCI:
1027 u32 *qcuBase = &val[0], *dcuBase = &val[4]; 387 return "Atheros 5416";
1028 int i; 388 case AR5416_DEVID_PCIE:
1029 389 return "Atheros 5418";
1030 REG_WRITE(ah, AR_MACMISC, 390 case AR9160_DEVID_PCI:
1031 ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) | 391 return "Atheros 9160";
1032 (AR_MACMISC_MISC_OBS_BUS_1 << 392 case AR9280_DEVID_PCI:
1033 AR_MACMISC_MISC_OBS_BUS_MSB_S))); 393 case AR9280_DEVID_PCIE:
1034 394 return "Atheros 9280";
1035 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "Raw DMA Debug values:\n"); 395 case AR9285_DEVID_PCIE:
1036 for (i = 0; i < ATH9K_NUM_DMA_DEBUG_REGS; i++) { 396 return "Atheros 9285";
1037 if (i % 4 == 0)
1038 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "\n");
1039
1040 val[i] = REG_READ(ah, AR_DMADBG_0 + (i * sizeof(u32)));
1041 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "%d: %08x ", i, val[i]);
1042 }
1043
1044 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "\n\n");
1045 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1046 "Num QCU: chain_st fsp_ok fsp_st DCU: chain_st\n");
1047
1048 for (i = 0; i < ATH9K_NUM_QUEUES;
1049 i++, qcuOffset += 4, dcuOffset += 5) {
1050 if (i == 8) {
1051 qcuOffset = 0;
1052 qcuBase++;
1053 }
1054
1055 if (i == 6) {
1056 dcuOffset = 0;
1057 dcuBase++;
1058 }
1059
1060 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1061 "%2d %2x %1x %2x %2x\n",
1062 i, (*qcuBase & (0x7 << qcuOffset)) >> qcuOffset,
1063 (*qcuBase & (0x8 << qcuOffset)) >> (qcuOffset +
1064 3),
1065 val[2] & (0x7 << (i * 3)) >> (i * 3),
1066 (*dcuBase & (0x1f << dcuOffset)) >> dcuOffset);
1067 } 397 }
1068 398
1069 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "\n"); 399 return NULL;
1070 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1071 "qcu_stitch state: %2x qcu_fetch state: %2x\n",
1072 (val[3] & 0x003c0000) >> 18, (val[3] & 0x03c00000) >> 22);
1073 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1074 "qcu_complete state: %2x dcu_complete state: %2x\n",
1075 (val[3] & 0x1c000000) >> 26, (val[6] & 0x3));
1076 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1077 "dcu_arb state: %2x dcu_fp state: %2x\n",
1078 (val[5] & 0x06000000) >> 25, (val[5] & 0x38000000) >> 27);
1079 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1080 "chan_idle_dur: %3d chan_idle_dur_valid: %1d\n",
1081 (val[6] & 0x000003fc) >> 2, (val[6] & 0x00000400) >> 10);
1082 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1083 "txfifo_valid_0: %1d txfifo_valid_1: %1d\n",
1084 (val[6] & 0x00000800) >> 11, (val[6] & 0x00001000) >> 12);
1085 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1086 "txfifo_dcu_num_0: %2d txfifo_dcu_num_1: %2d\n",
1087 (val[6] & 0x0001e000) >> 13, (val[6] & 0x001e0000) >> 17);
1088
1089 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "pcu observe 0x%x \n",
1090 REG_READ(ah, AR_OBS_BUS_1));
1091 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1092 "AR_CR 0x%x \n", REG_READ(ah, AR_CR));
1093} 400}
1094 401
1095u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah, 402static void ath9k_hw_set_defaults(struct ath_hal *ah)
1096 u32 *rxc_pcnt,
1097 u32 *rxf_pcnt,
1098 u32 *txf_pcnt)
1099{ 403{
1100 static u32 cycles, rx_clear, rx_frame, tx_frame; 404 int i;
1101 u32 good = 1;
1102 405
1103 u32 rc = REG_READ(ah, AR_RCCNT); 406 ah->ah_config.dma_beacon_response_time = 2;
1104 u32 rf = REG_READ(ah, AR_RFCNT); 407 ah->ah_config.sw_beacon_response_time = 10;
1105 u32 tf = REG_READ(ah, AR_TFCNT); 408 ah->ah_config.additional_swba_backoff = 0;
1106 u32 cc = REG_READ(ah, AR_CCCNT); 409 ah->ah_config.ack_6mb = 0x0;
410 ah->ah_config.cwm_ignore_extcca = 0;
411 ah->ah_config.pcie_powersave_enable = 0;
412 ah->ah_config.pcie_l1skp_enable = 0;
413 ah->ah_config.pcie_clock_req = 0;
414 ah->ah_config.pcie_power_reset = 0x100;
415 ah->ah_config.pcie_restore = 0;
416 ah->ah_config.pcie_waen = 0;
417 ah->ah_config.analog_shiftreg = 1;
418 ah->ah_config.ht_enable = 1;
419 ah->ah_config.ofdm_trig_low = 200;
420 ah->ah_config.ofdm_trig_high = 500;
421 ah->ah_config.cck_trig_high = 200;
422 ah->ah_config.cck_trig_low = 100;
423 ah->ah_config.enable_ani = 1;
424 ah->ah_config.noise_immunity_level = 4;
425 ah->ah_config.ofdm_weaksignal_det = 1;
426 ah->ah_config.cck_weaksignal_thr = 0;
427 ah->ah_config.spur_immunity_level = 2;
428 ah->ah_config.firstep_level = 0;
429 ah->ah_config.rssi_thr_high = 40;
430 ah->ah_config.rssi_thr_low = 7;
431 ah->ah_config.diversity_control = 0;
432 ah->ah_config.antenna_switch_swap = 0;
1107 433
1108 if (cycles == 0 || cycles > cc) { 434 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1109 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, 435 ah->ah_config.spurchans[i][0] = AR_NO_SPUR;
1110 "%s: cycle counter wrap. ExtBusy = 0\n", 436 ah->ah_config.spurchans[i][1] = AR_NO_SPUR;
1111 __func__);
1112 good = 0;
1113 } else {
1114 u32 cc_d = cc - cycles;
1115 u32 rc_d = rc - rx_clear;
1116 u32 rf_d = rf - rx_frame;
1117 u32 tf_d = tf - tx_frame;
1118
1119 if (cc_d != 0) {
1120 *rxc_pcnt = rc_d * 100 / cc_d;
1121 *rxf_pcnt = rf_d * 100 / cc_d;
1122 *txf_pcnt = tf_d * 100 / cc_d;
1123 } else {
1124 good = 0;
1125 }
1126 } 437 }
1127 438
1128 cycles = cc; 439 ah->ah_config.intr_mitigation = 1;
1129 rx_frame = rf;
1130 rx_clear = rc;
1131 tx_frame = tf;
1132
1133 return good;
1134} 440}
1135 441
1136void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode)
1137{
1138 u32 macmode;
1139
1140 if (mode == ATH9K_HT_MACMODE_2040 &&
1141 !ah->ah_config.cwm_ignore_extcca)
1142 macmode = AR_2040_JOINED_RX_CLEAR;
1143 else
1144 macmode = 0;
1145
1146 REG_WRITE(ah, AR_2040_MODE, macmode);
1147}
1148
1149static void ath9k_hw_mark_phy_inactive(struct ath_hal *ah)
1150{
1151 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1152}
1153
1154
1155static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid, 442static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid,
1156 struct ath_softc *sc, 443 struct ath_softc *sc,
1157 void __iomem *mem, 444 void __iomem *mem,
@@ -1165,20 +452,16 @@ static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid,
1165 ahp = kzalloc(sizeof(struct ath_hal_5416), GFP_KERNEL); 452 ahp = kzalloc(sizeof(struct ath_hal_5416), GFP_KERNEL);
1166 if (ahp == NULL) { 453 if (ahp == NULL) {
1167 DPRINTF(sc, ATH_DBG_FATAL, 454 DPRINTF(sc, ATH_DBG_FATAL,
1168 "%s: cannot allocate memory for state block\n", 455 "Cannot allocate memory for state block\n");
1169 __func__);
1170 *status = -ENOMEM; 456 *status = -ENOMEM;
1171 return NULL; 457 return NULL;
1172 } 458 }
1173 459
1174 ah = &ahp->ah; 460 ah = &ahp->ah;
1175
1176 ah->ah_sc = sc; 461 ah->ah_sc = sc;
1177 ah->ah_sh = mem; 462 ah->ah_sh = mem;
1178
1179 ah->ah_magic = AR5416_MAGIC; 463 ah->ah_magic = AR5416_MAGIC;
1180 ah->ah_countryCode = CTRY_DEFAULT; 464 ah->ah_countryCode = CTRY_DEFAULT;
1181
1182 ah->ah_devid = devid; 465 ah->ah_devid = devid;
1183 ah->ah_subvendorid = 0; 466 ah->ah_subvendorid = 0;
1184 467
@@ -1190,12 +473,10 @@ static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid,
1190 473
1191 ah->ah_powerLimit = MAX_RATE_POWER; 474 ah->ah_powerLimit = MAX_RATE_POWER;
1192 ah->ah_tpScale = ATH9K_TP_SCALE_MAX; 475 ah->ah_tpScale = ATH9K_TP_SCALE_MAX;
1193
1194 ahp->ah_atimWindow = 0; 476 ahp->ah_atimWindow = 0;
1195 ahp->ah_diversityControl = ah->ah_config.diversity_control; 477 ahp->ah_diversityControl = ah->ah_config.diversity_control;
1196 ahp->ah_antennaSwitchSwap = 478 ahp->ah_antennaSwitchSwap =
1197 ah->ah_config.antenna_switch_swap; 479 ah->ah_config.antenna_switch_swap;
1198
1199 ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE; 480 ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
1200 ahp->ah_beaconInterval = 100; 481 ahp->ah_beaconInterval = 100;
1201 ahp->ah_enable32kHzClock = DONT_USE_32KHZ; 482 ahp->ah_enable32kHzClock = DONT_USE_32KHZ;
@@ -1210,163 +491,6 @@ static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid,
1210 return ahp; 491 return ahp;
1211} 492}
1212 493
1213static int ath9k_hw_eeprom_attach(struct ath_hal *ah)
1214{
1215 int status;
1216
1217 if (ath9k_hw_use_flash(ah))
1218 ath9k_hw_flash_map(ah);
1219
1220 if (!ath9k_hw_fill_eeprom(ah))
1221 return -EIO;
1222
1223 status = ath9k_hw_check_eeprom(ah);
1224
1225 return status;
1226}
1227
1228u32 ath9k_hw_get_eeprom(struct ath_hal_5416 *ahp,
1229 enum eeprom_param param)
1230{
1231 struct ar5416_eeprom *eep = &ahp->ah_eeprom;
1232 struct modal_eep_header *pModal = eep->modalHeader;
1233 struct base_eep_header *pBase = &eep->baseEepHeader;
1234
1235 switch (param) {
1236 case EEP_NFTHRESH_5:
1237 return -pModal[0].noiseFloorThreshCh[0];
1238 case EEP_NFTHRESH_2:
1239 return -pModal[1].noiseFloorThreshCh[0];
1240 case AR_EEPROM_MAC(0):
1241 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
1242 case AR_EEPROM_MAC(1):
1243 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
1244 case AR_EEPROM_MAC(2):
1245 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
1246 case EEP_REG_0:
1247 return pBase->regDmn[0];
1248 case EEP_REG_1:
1249 return pBase->regDmn[1];
1250 case EEP_OP_CAP:
1251 return pBase->deviceCap;
1252 case EEP_OP_MODE:
1253 return pBase->opCapFlags;
1254 case EEP_RF_SILENT:
1255 return pBase->rfSilent;
1256 case EEP_OB_5:
1257 return pModal[0].ob;
1258 case EEP_DB_5:
1259 return pModal[0].db;
1260 case EEP_OB_2:
1261 return pModal[1].ob;
1262 case EEP_DB_2:
1263 return pModal[1].db;
1264 case EEP_MINOR_REV:
1265 return pBase->version & AR5416_EEP_VER_MINOR_MASK;
1266 case EEP_TX_MASK:
1267 return pBase->txMask;
1268 case EEP_RX_MASK:
1269 return pBase->rxMask;
1270 default:
1271 return 0;
1272 }
1273}
1274
1275static int ath9k_hw_get_radiorev(struct ath_hal *ah)
1276{
1277 u32 val;
1278 int i;
1279
1280 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
1281 for (i = 0; i < 8; i++)
1282 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
1283 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
1284 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
1285 return ath9k_hw_reverse_bits(val, 8);
1286}
1287
1288static int ath9k_hw_init_macaddr(struct ath_hal *ah)
1289{
1290 u32 sum;
1291 int i;
1292 u16 eeval;
1293 struct ath_hal_5416 *ahp = AH5416(ah);
1294 DECLARE_MAC_BUF(mac);
1295
1296 sum = 0;
1297 for (i = 0; i < 3; i++) {
1298 eeval = ath9k_hw_get_eeprom(ahp, AR_EEPROM_MAC(i));
1299 sum += eeval;
1300 ahp->ah_macaddr[2 * i] = eeval >> 8;
1301 ahp->ah_macaddr[2 * i + 1] = eeval & 0xff;
1302 }
1303 if (sum == 0 || sum == 0xffff * 3) {
1304 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1305 "%s: mac address read failed: %s\n", __func__,
1306 print_mac(mac, ahp->ah_macaddr));
1307 return -EADDRNOTAVAIL;
1308 }
1309
1310 return 0;
1311}
1312
1313static inline int16_t ath9k_hw_interpolate(u16 target,
1314 u16 srcLeft,
1315 u16 srcRight,
1316 int16_t targetLeft,
1317 int16_t targetRight)
1318{
1319 int16_t rv;
1320
1321 if (srcRight == srcLeft) {
1322 rv = targetLeft;
1323 } else {
1324 rv = (int16_t) (((target - srcLeft) * targetRight +
1325 (srcRight - target) * targetLeft) /
1326 (srcRight - srcLeft));
1327 }
1328 return rv;
1329}
1330
1331static inline u16 ath9k_hw_fbin2freq(u8 fbin,
1332 bool is2GHz)
1333{
1334
1335 if (fbin == AR5416_BCHAN_UNUSED)
1336 return fbin;
1337
1338 return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
1339}
1340
1341static u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah,
1342 u16 i,
1343 bool is2GHz)
1344{
1345 struct ath_hal_5416 *ahp = AH5416(ah);
1346 struct ar5416_eeprom *eep =
1347 (struct ar5416_eeprom *) &ahp->ah_eeprom;
1348 u16 spur_val = AR_NO_SPUR;
1349
1350 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
1351 "Getting spur idx %d is2Ghz. %d val %x\n",
1352 i, is2GHz, ah->ah_config.spurchans[i][is2GHz]);
1353
1354 switch (ah->ah_config.spurmode) {
1355 case SPUR_DISABLE:
1356 break;
1357 case SPUR_ENABLE_IOCTL:
1358 spur_val = ah->ah_config.spurchans[i][is2GHz];
1359 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
1360 "Getting spur val from new loc. %d\n", spur_val);
1361 break;
1362 case SPUR_ENABLE_EEPROM:
1363 spur_val = eep->modalHeader[is2GHz].spurChans[i].spurChan;
1364 break;
1365
1366 }
1367 return spur_val;
1368}
1369
1370static int ath9k_hw_rfattach(struct ath_hal *ah) 494static int ath9k_hw_rfattach(struct ath_hal *ah)
1371{ 495{
1372 bool rfStatus = false; 496 bool rfStatus = false;
@@ -1375,8 +499,7 @@ static int ath9k_hw_rfattach(struct ath_hal *ah)
1375 rfStatus = ath9k_hw_init_rf(ah, &ecode); 499 rfStatus = ath9k_hw_init_rf(ah, &ecode);
1376 if (!rfStatus) { 500 if (!rfStatus) {
1377 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 501 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1378 "%s: RF setup failed, status %u\n", __func__, 502 "RF setup failed, status %u\n", ecode);
1379 ecode);
1380 return ecode; 503 return ecode;
1381 } 504 }
1382 505
@@ -1401,9 +524,9 @@ static int ath9k_hw_rf_claim(struct ath_hal *ah)
1401 break; 524 break;
1402 default: 525 default:
1403 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, 526 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1404 "%s: 5G Radio Chip Rev 0x%02X is not " 527 "5G Radio Chip Rev 0x%02X is not "
1405 "supported by this driver\n", 528 "supported by this driver\n",
1406 __func__, ah->ah_analog5GhzRev); 529 ah->ah_analog5GhzRev);
1407 return -EOPNOTSUPP; 530 return -EOPNOTSUPP;
1408 } 531 }
1409 532
@@ -1412,1473 +535,76 @@ static int ath9k_hw_rf_claim(struct ath_hal *ah)
1412 return 0; 535 return 0;
1413} 536}
1414 537
1415static void ath9k_hw_init_pll(struct ath_hal *ah, 538static int ath9k_hw_init_macaddr(struct ath_hal *ah)
1416 struct ath9k_channel *chan)
1417{
1418 u32 pll;
1419
1420 if (AR_SREV_9100(ah)) {
1421 if (chan && IS_CHAN_5GHZ(chan))
1422 pll = 0x1450;
1423 else
1424 pll = 0x1458;
1425 } else {
1426 if (AR_SREV_9280_10_OR_LATER(ah)) {
1427 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1428
1429 if (chan && IS_CHAN_HALF_RATE(chan))
1430 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1431 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1432 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1433
1434 if (chan && IS_CHAN_5GHZ(chan)) {
1435 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1436
1437
1438 if (AR_SREV_9280_20(ah)) {
1439 if (((chan->channel % 20) == 0)
1440 || ((chan->channel % 10) == 0))
1441 pll = 0x2850;
1442 else
1443 pll = 0x142c;
1444 }
1445 } else {
1446 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1447 }
1448
1449 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1450
1451 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1452
1453 if (chan && IS_CHAN_HALF_RATE(chan))
1454 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1455 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1456 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1457
1458 if (chan && IS_CHAN_5GHZ(chan))
1459 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1460 else
1461 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1462 } else {
1463 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1464
1465 if (chan && IS_CHAN_HALF_RATE(chan))
1466 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1467 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1468 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1469
1470 if (chan && IS_CHAN_5GHZ(chan))
1471 pll |= SM(0xa, AR_RTC_PLL_DIV);
1472 else
1473 pll |= SM(0xb, AR_RTC_PLL_DIV);
1474 }
1475 }
1476 REG_WRITE(ah, (u16) (AR_RTC_PLL_CONTROL), pll);
1477
1478 udelay(RTC_PLL_SETTLE_DELAY);
1479
1480 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1481}
1482
1483static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
1484 enum ath9k_ht_macmode macmode)
1485{
1486 u32 phymode;
1487 struct ath_hal_5416 *ahp = AH5416(ah);
1488
1489 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1490 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH;
1491
1492 if (IS_CHAN_HT40(chan)) {
1493 phymode |= AR_PHY_FC_DYN2040_EN;
1494
1495 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1496 (chan->chanmode == CHANNEL_G_HT40PLUS))
1497 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1498
1499 if (ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1500 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1501 }
1502 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1503
1504 ath9k_hw_set11nmac2040(ah, macmode);
1505
1506 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1507 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1508}
1509
1510static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode)
1511{
1512 u32 val;
1513
1514 val = REG_READ(ah, AR_STA_ID1);
1515 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1516 switch (opmode) {
1517 case ATH9K_M_HOSTAP:
1518 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1519 | AR_STA_ID1_KSRCH_MODE);
1520 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1521 break;
1522 case ATH9K_M_IBSS:
1523 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1524 | AR_STA_ID1_KSRCH_MODE);
1525 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1526 break;
1527 case ATH9K_M_STA:
1528 case ATH9K_M_MONITOR:
1529 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1530 break;
1531 }
1532}
1533
1534static void
1535ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan)
1536{
1537 u32 rfMode = 0;
1538
1539 if (chan == NULL)
1540 return;
1541
1542 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1543 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1544
1545 if (!AR_SREV_9280_10_OR_LATER(ah))
1546 rfMode |= (IS_CHAN_5GHZ(chan)) ? AR_PHY_MODE_RF5GHZ :
1547 AR_PHY_MODE_RF2GHZ;
1548
1549 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1550 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1551
1552 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1553}
1554
1555static bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
1556{
1557 u32 rst_flags;
1558 u32 tmpReg;
1559
1560 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1561 AR_RTC_FORCE_WAKE_ON_INT);
1562
1563 if (AR_SREV_9100(ah)) {
1564 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1565 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1566 } else {
1567 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1568 if (tmpReg &
1569 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1570 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1571 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1572 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1573 } else {
1574 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1575 }
1576
1577 rst_flags = AR_RTC_RC_MAC_WARM;
1578 if (type == ATH9K_RESET_COLD)
1579 rst_flags |= AR_RTC_RC_MAC_COLD;
1580 }
1581
1582 REG_WRITE(ah, (u16) (AR_RTC_RC), rst_flags);
1583 udelay(50);
1584
1585 REG_WRITE(ah, (u16) (AR_RTC_RC), 0);
1586 if (!ath9k_hw_wait(ah, (u16) (AR_RTC_RC), AR_RTC_RC_M, 0)) {
1587 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1588 "%s: RTC stuck in MAC reset\n",
1589 __func__);
1590 return false;
1591 }
1592
1593 if (!AR_SREV_9100(ah))
1594 REG_WRITE(ah, AR_RC, 0);
1595
1596 ath9k_hw_init_pll(ah, NULL);
1597
1598 if (AR_SREV_9100(ah))
1599 udelay(50);
1600
1601 return true;
1602}
1603
1604static bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
1605{
1606 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1607 AR_RTC_FORCE_WAKE_ON_INT);
1608
1609 REG_WRITE(ah, (u16) (AR_RTC_RESET), 0);
1610 REG_WRITE(ah, (u16) (AR_RTC_RESET), 1);
1611
1612 if (!ath9k_hw_wait(ah,
1613 AR_RTC_STATUS,
1614 AR_RTC_STATUS_M,
1615 AR_RTC_STATUS_ON)) {
1616 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: RTC not waking up\n",
1617 __func__);
1618 return false;
1619 }
1620
1621 ath9k_hw_read_revisions(ah);
1622
1623 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1624}
1625
1626static bool ath9k_hw_set_reset_reg(struct ath_hal *ah,
1627 u32 type)
1628{
1629 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1630 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1631
1632 switch (type) {
1633 case ATH9K_RESET_POWER_ON:
1634 return ath9k_hw_set_reset_power_on(ah);
1635 break;
1636 case ATH9K_RESET_WARM:
1637 case ATH9K_RESET_COLD:
1638 return ath9k_hw_set_reset(ah, type);
1639 break;
1640 default:
1641 return false;
1642 }
1643}
1644
1645static
1646struct ath9k_channel *ath9k_hw_check_chan(struct ath_hal *ah,
1647 struct ath9k_channel *chan)
1648{
1649 if (!(IS_CHAN_2GHZ(chan) ^ IS_CHAN_5GHZ(chan))) {
1650 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1651 "%s: invalid channel %u/0x%x; not marked as "
1652 "2GHz or 5GHz\n", __func__, chan->channel,
1653 chan->channelFlags);
1654 return NULL;
1655 }
1656
1657 if (!IS_CHAN_OFDM(chan) &&
1658 !IS_CHAN_CCK(chan) &&
1659 !IS_CHAN_HT20(chan) &&
1660 !IS_CHAN_HT40(chan)) {
1661 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1662 "%s: invalid channel %u/0x%x; not marked as "
1663 "OFDM or CCK or HT20 or HT40PLUS or HT40MINUS\n",
1664 __func__, chan->channel, chan->channelFlags);
1665 return NULL;
1666 }
1667
1668 return ath9k_regd_check_channel(ah, chan);
1669}
1670
1671static inline bool
1672ath9k_hw_get_lower_upper_index(u8 target,
1673 u8 *pList,
1674 u16 listSize,
1675 u16 *indexL,
1676 u16 *indexR)
1677{
1678 u16 i;
1679
1680 if (target <= pList[0]) {
1681 *indexL = *indexR = 0;
1682 return true;
1683 }
1684 if (target >= pList[listSize - 1]) {
1685 *indexL = *indexR = (u16) (listSize - 1);
1686 return true;
1687 }
1688
1689 for (i = 0; i < listSize - 1; i++) {
1690 if (pList[i] == target) {
1691 *indexL = *indexR = i;
1692 return true;
1693 }
1694 if (target < pList[i + 1]) {
1695 *indexL = i;
1696 *indexR = (u16) (i + 1);
1697 return false;
1698 }
1699 }
1700 return false;
1701}
1702
1703static int16_t ath9k_hw_get_nf_hist_mid(int16_t *nfCalBuffer)
1704{
1705 int16_t nfval;
1706 int16_t sort[ATH9K_NF_CAL_HIST_MAX];
1707 int i, j;
1708
1709 for (i = 0; i < ATH9K_NF_CAL_HIST_MAX; i++)
1710 sort[i] = nfCalBuffer[i];
1711
1712 for (i = 0; i < ATH9K_NF_CAL_HIST_MAX - 1; i++) {
1713 for (j = 1; j < ATH9K_NF_CAL_HIST_MAX - i; j++) {
1714 if (sort[j] > sort[j - 1]) {
1715 nfval = sort[j];
1716 sort[j] = sort[j - 1];
1717 sort[j - 1] = nfval;
1718 }
1719 }
1720 }
1721 nfval = sort[(ATH9K_NF_CAL_HIST_MAX - 1) >> 1];
1722
1723 return nfval;
1724}
1725
1726static void ath9k_hw_update_nfcal_hist_buffer(struct ath9k_nfcal_hist *h,
1727 int16_t *nfarray)
1728{ 539{
540 u32 sum;
1729 int i; 541 int i;
1730 542 u16 eeval;
1731 for (i = 0; i < NUM_NF_READINGS; i++) {
1732 h[i].nfCalBuffer[h[i].currIndex] = nfarray[i];
1733
1734 if (++h[i].currIndex >= ATH9K_NF_CAL_HIST_MAX)
1735 h[i].currIndex = 0;
1736
1737 if (h[i].invalidNFcount > 0) {
1738 if (nfarray[i] < AR_PHY_CCA_MIN_BAD_VALUE
1739 || nfarray[i] > AR_PHY_CCA_MAX_HIGH_VALUE) {
1740 h[i].invalidNFcount = ATH9K_NF_CAL_HIST_MAX;
1741 } else {
1742 h[i].invalidNFcount--;
1743 h[i].privNF = nfarray[i];
1744 }
1745 } else {
1746 h[i].privNF =
1747 ath9k_hw_get_nf_hist_mid(h[i].nfCalBuffer);
1748 }
1749 }
1750 return;
1751}
1752
1753static void ar5416GetNoiseFloor(struct ath_hal *ah,
1754 int16_t nfarray[NUM_NF_READINGS])
1755{
1756 int16_t nf;
1757
1758 if (AR_SREV_9280_10_OR_LATER(ah))
1759 nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
1760 else
1761 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
1762
1763 if (nf & 0x100)
1764 nf = 0 - ((nf ^ 0x1ff) + 1);
1765 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
1766 "NF calibrated [ctl] [chain 0] is %d\n", nf);
1767 nfarray[0] = nf;
1768
1769 if (AR_SREV_9280_10_OR_LATER(ah))
1770 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
1771 AR9280_PHY_CH1_MINCCA_PWR);
1772 else
1773 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
1774 AR_PHY_CH1_MINCCA_PWR);
1775
1776 if (nf & 0x100)
1777 nf = 0 - ((nf ^ 0x1ff) + 1);
1778 DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
1779 "NF calibrated [ctl] [chain 1] is %d\n", nf);
1780 nfarray[1] = nf;
1781
1782 if (!AR_SREV_9280(ah)) {
1783 nf = MS(REG_READ(ah, AR_PHY_CH2_CCA),
1784 AR_PHY_CH2_MINCCA_PWR);
1785 if (nf & 0x100)
1786 nf = 0 - ((nf ^ 0x1ff) + 1);
1787 DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
1788 "NF calibrated [ctl] [chain 2] is %d\n", nf);
1789 nfarray[2] = nf;
1790 }
1791
1792 if (AR_SREV_9280_10_OR_LATER(ah))
1793 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),
1794 AR9280_PHY_EXT_MINCCA_PWR);
1795 else
1796 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),
1797 AR_PHY_EXT_MINCCA_PWR);
1798
1799 if (nf & 0x100)
1800 nf = 0 - ((nf ^ 0x1ff) + 1);
1801 DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
1802 "NF calibrated [ext] [chain 0] is %d\n", nf);
1803 nfarray[3] = nf;
1804
1805 if (AR_SREV_9280_10_OR_LATER(ah))
1806 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
1807 AR9280_PHY_CH1_EXT_MINCCA_PWR);
1808 else
1809 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
1810 AR_PHY_CH1_EXT_MINCCA_PWR);
1811
1812 if (nf & 0x100)
1813 nf = 0 - ((nf ^ 0x1ff) + 1);
1814 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
1815 "NF calibrated [ext] [chain 1] is %d\n", nf);
1816 nfarray[4] = nf;
1817
1818 if (!AR_SREV_9280(ah)) {
1819 nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA),
1820 AR_PHY_CH2_EXT_MINCCA_PWR);
1821 if (nf & 0x100)
1822 nf = 0 - ((nf ^ 0x1ff) + 1);
1823 DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
1824 "NF calibrated [ext] [chain 2] is %d\n", nf);
1825 nfarray[5] = nf;
1826 }
1827}
1828
1829static bool
1830getNoiseFloorThresh(struct ath_hal *ah,
1831 const struct ath9k_channel *chan,
1832 int16_t *nft)
1833{
1834 struct ath_hal_5416 *ahp = AH5416(ah); 543 struct ath_hal_5416 *ahp = AH5416(ah);
1835 544
1836 switch (chan->chanmode) { 545 sum = 0;
1837 case CHANNEL_A: 546 for (i = 0; i < 3; i++) {
1838 case CHANNEL_A_HT20: 547 eeval = ath9k_hw_get_eeprom(ah, AR_EEPROM_MAC(i));
1839 case CHANNEL_A_HT40PLUS: 548 sum += eeval;
1840 case CHANNEL_A_HT40MINUS: 549 ahp->ah_macaddr[2 * i] = eeval >> 8;
1841 *nft = (int16_t) ath9k_hw_get_eeprom(ahp, EEP_NFTHRESH_5); 550 ahp->ah_macaddr[2 * i + 1] = eeval & 0xff;
1842 break;
1843 case CHANNEL_B:
1844 case CHANNEL_G:
1845 case CHANNEL_G_HT20:
1846 case CHANNEL_G_HT40PLUS:
1847 case CHANNEL_G_HT40MINUS:
1848 *nft = (int16_t) ath9k_hw_get_eeprom(ahp, EEP_NFTHRESH_2);
1849 break;
1850 default:
1851 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1852 "%s: invalid channel flags 0x%x\n", __func__,
1853 chan->channelFlags);
1854 return false;
1855 }
1856 return true;
1857}
1858
1859static void ath9k_hw_start_nfcal(struct ath_hal *ah)
1860{
1861 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
1862 AR_PHY_AGC_CONTROL_ENABLE_NF);
1863 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
1864 AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
1865 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
1866}
1867
1868static void
1869ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan)
1870{
1871 struct ath9k_nfcal_hist *h;
1872 int i, j;
1873 int32_t val;
1874 const u32 ar5416_cca_regs[6] = {
1875 AR_PHY_CCA,
1876 AR_PHY_CH1_CCA,
1877 AR_PHY_CH2_CCA,
1878 AR_PHY_EXT_CCA,
1879 AR_PHY_CH1_EXT_CCA,
1880 AR_PHY_CH2_EXT_CCA
1881 };
1882 u8 chainmask;
1883
1884 if (AR_SREV_9280(ah))
1885 chainmask = 0x1B;
1886 else
1887 chainmask = 0x3F;
1888
1889#ifdef ATH_NF_PER_CHAN
1890 h = chan->nfCalHist;
1891#else
1892 h = ah->nfCalHist;
1893#endif
1894
1895 for (i = 0; i < NUM_NF_READINGS; i++) {
1896 if (chainmask & (1 << i)) {
1897 val = REG_READ(ah, ar5416_cca_regs[i]);
1898 val &= 0xFFFFFE00;
1899 val |= (((u32) (h[i].privNF) << 1) & 0x1ff);
1900 REG_WRITE(ah, ar5416_cca_regs[i], val);
1901 }
1902 }
1903
1904 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
1905 AR_PHY_AGC_CONTROL_ENABLE_NF);
1906 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
1907 AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
1908 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
1909
1910 for (j = 0; j < 1000; j++) {
1911 if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
1912 AR_PHY_AGC_CONTROL_NF) == 0)
1913 break;
1914 udelay(10);
1915 }
1916
1917 for (i = 0; i < NUM_NF_READINGS; i++) {
1918 if (chainmask & (1 << i)) {
1919 val = REG_READ(ah, ar5416_cca_regs[i]);
1920 val &= 0xFFFFFE00;
1921 val |= (((u32) (-50) << 1) & 0x1ff);
1922 REG_WRITE(ah, ar5416_cca_regs[i], val);
1923 }
1924 }
1925}
1926
1927static int16_t ath9k_hw_getnf(struct ath_hal *ah,
1928 struct ath9k_channel *chan)
1929{
1930 int16_t nf, nfThresh;
1931 int16_t nfarray[NUM_NF_READINGS] = { 0 };
1932 struct ath9k_nfcal_hist *h;
1933 u8 chainmask;
1934
1935 if (AR_SREV_9280(ah))
1936 chainmask = 0x1B;
1937 else
1938 chainmask = 0x3F;
1939
1940 chan->channelFlags &= (~CHANNEL_CW_INT);
1941 if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
1942 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
1943 "%s: NF did not complete in calibration window\n",
1944 __func__);
1945 nf = 0;
1946 chan->rawNoiseFloor = nf;
1947 return chan->rawNoiseFloor;
1948 } else {
1949 ar5416GetNoiseFloor(ah, nfarray);
1950 nf = nfarray[0];
1951 if (getNoiseFloorThresh(ah, chan, &nfThresh)
1952 && nf > nfThresh) {
1953 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
1954 "%s: noise floor failed detected; "
1955 "detected %d, threshold %d\n", __func__,
1956 nf, nfThresh);
1957 chan->channelFlags |= CHANNEL_CW_INT;
1958 }
1959 } 551 }
1960 552 if (sum == 0 || sum == 0xffff * 3) {
1961#ifdef ATH_NF_PER_CHAN 553 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1962 h = chan->nfCalHist; 554 "mac address read failed: %pM\n",
1963#else 555 ahp->ah_macaddr);
1964 h = ah->nfCalHist; 556 return -EADDRNOTAVAIL;
1965#endif
1966
1967 ath9k_hw_update_nfcal_hist_buffer(h, nfarray);
1968 chan->rawNoiseFloor = h[0].privNF;
1969
1970 return chan->rawNoiseFloor;
1971}
1972
1973static void ath9k_hw_update_mibstats(struct ath_hal *ah,
1974 struct ath9k_mib_stats *stats)
1975{
1976 stats->ackrcv_bad += REG_READ(ah, AR_ACK_FAIL);
1977 stats->rts_bad += REG_READ(ah, AR_RTS_FAIL);
1978 stats->fcs_bad += REG_READ(ah, AR_FCS_FAIL);
1979 stats->rts_good += REG_READ(ah, AR_RTS_OK);
1980 stats->beacons += REG_READ(ah, AR_BEACON_CNT);
1981}
1982
1983static void ath9k_enable_mib_counters(struct ath_hal *ah)
1984{
1985 struct ath_hal_5416 *ahp = AH5416(ah);
1986
1987 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Enable mib counters\n");
1988
1989 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
1990
1991 REG_WRITE(ah, AR_FILT_OFDM, 0);
1992 REG_WRITE(ah, AR_FILT_CCK, 0);
1993 REG_WRITE(ah, AR_MIBC,
1994 ~(AR_MIBC_COW | AR_MIBC_FMC | AR_MIBC_CMC | AR_MIBC_MCS)
1995 & 0x0f);
1996 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
1997 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
1998}
1999
2000static void ath9k_hw_disable_mib_counters(struct ath_hal *ah)
2001{
2002 struct ath_hal_5416 *ahp = AH5416(ah);
2003
2004 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Disabling MIB counters\n");
2005
2006 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC | AR_MIBC_CMC);
2007
2008 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
2009
2010 REG_WRITE(ah, AR_FILT_OFDM, 0);
2011 REG_WRITE(ah, AR_FILT_CCK, 0);
2012}
2013
2014static int ath9k_hw_get_ani_channel_idx(struct ath_hal *ah,
2015 struct ath9k_channel *chan)
2016{
2017 struct ath_hal_5416 *ahp = AH5416(ah);
2018 int i;
2019
2020 for (i = 0; i < ARRAY_SIZE(ahp->ah_ani); i++) {
2021 if (ahp->ah_ani[i].c.channel == chan->channel)
2022 return i;
2023 if (ahp->ah_ani[i].c.channel == 0) {
2024 ahp->ah_ani[i].c.channel = chan->channel;
2025 ahp->ah_ani[i].c.channelFlags = chan->channelFlags;
2026 return i;
2027 }
2028 } 557 }
2029 558
2030 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2031 "No more channel states left. Using channel 0\n");
2032 return 0; 559 return 0;
2033} 560}
2034 561
2035static void ath9k_hw_ani_attach(struct ath_hal *ah) 562static void ath9k_hw_init_rxgain_ini(struct ath_hal *ah)
2036{ 563{
564 u32 rxgain_type;
2037 struct ath_hal_5416 *ahp = AH5416(ah); 565 struct ath_hal_5416 *ahp = AH5416(ah);
2038 int i;
2039 566
2040 ahp->ah_hasHwPhyCounters = 1; 567 if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
2041 568 rxgain_type = ath9k_hw_get_eeprom(ah, EEP_RXGAIN_TYPE);
2042 memset(ahp->ah_ani, 0, sizeof(ahp->ah_ani));
2043 for (i = 0; i < ARRAY_SIZE(ahp->ah_ani); i++) {
2044 ahp->ah_ani[i].ofdmTrigHigh = ATH9K_ANI_OFDM_TRIG_HIGH;
2045 ahp->ah_ani[i].ofdmTrigLow = ATH9K_ANI_OFDM_TRIG_LOW;
2046 ahp->ah_ani[i].cckTrigHigh = ATH9K_ANI_CCK_TRIG_HIGH;
2047 ahp->ah_ani[i].cckTrigLow = ATH9K_ANI_CCK_TRIG_LOW;
2048 ahp->ah_ani[i].rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH;
2049 ahp->ah_ani[i].rssiThrLow = ATH9K_ANI_RSSI_THR_LOW;
2050 ahp->ah_ani[i].ofdmWeakSigDetectOff =
2051 !ATH9K_ANI_USE_OFDM_WEAK_SIG;
2052 ahp->ah_ani[i].cckWeakSigThreshold =
2053 ATH9K_ANI_CCK_WEAK_SIG_THR;
2054 ahp->ah_ani[i].spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
2055 ahp->ah_ani[i].firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
2056 if (ahp->ah_hasHwPhyCounters) {
2057 ahp->ah_ani[i].ofdmPhyErrBase =
2058 AR_PHY_COUNTMAX - ATH9K_ANI_OFDM_TRIG_HIGH;
2059 ahp->ah_ani[i].cckPhyErrBase =
2060 AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH;
2061 }
2062 }
2063 if (ahp->ah_hasHwPhyCounters) {
2064 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2065 "Setting OfdmErrBase = 0x%08x\n",
2066 ahp->ah_ani[0].ofdmPhyErrBase);
2067 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n",
2068 ahp->ah_ani[0].cckPhyErrBase);
2069
2070 REG_WRITE(ah, AR_PHY_ERR_1, ahp->ah_ani[0].ofdmPhyErrBase);
2071 REG_WRITE(ah, AR_PHY_ERR_2, ahp->ah_ani[0].cckPhyErrBase);
2072 ath9k_enable_mib_counters(ah);
2073 }
2074 ahp->ah_aniPeriod = ATH9K_ANI_PERIOD;
2075 if (ah->ah_config.enable_ani)
2076 ahp->ah_procPhyErr |= HAL_PROCESS_ANI;
2077}
2078
2079static void ath9k_hw_ani_setup(struct ath_hal *ah)
2080{
2081 struct ath_hal_5416 *ahp = AH5416(ah);
2082 int i;
2083 569
2084 const int totalSizeDesired[] = { -55, -55, -55, -55, -62 }; 570 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
2085 const int coarseHigh[] = { -14, -14, -14, -14, -12 }; 571 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
2086 const int coarseLow[] = { -64, -64, -64, -64, -70 }; 572 ar9280Modes_backoff_13db_rxgain_9280_2,
2087 const int firpwr[] = { -78, -78, -78, -78, -80 }; 573 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
2088 574 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
2089 for (i = 0; i < 5; i++) { 575 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
2090 ahp->ah_totalSizeDesired[i] = totalSizeDesired[i]; 576 ar9280Modes_backoff_23db_rxgain_9280_2,
2091 ahp->ah_coarseHigh[i] = coarseHigh[i]; 577 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
2092 ahp->ah_coarseLow[i] = coarseLow[i];
2093 ahp->ah_firpwr[i] = firpwr[i];
2094 }
2095}
2096
2097static void ath9k_hw_ani_detach(struct ath_hal *ah)
2098{
2099 struct ath_hal_5416 *ahp = AH5416(ah);
2100
2101 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Detaching Ani\n");
2102 if (ahp->ah_hasHwPhyCounters) {
2103 ath9k_hw_disable_mib_counters(ah);
2104 REG_WRITE(ah, AR_PHY_ERR_1, 0);
2105 REG_WRITE(ah, AR_PHY_ERR_2, 0);
2106 }
2107}
2108
2109
2110static bool ath9k_hw_ani_control(struct ath_hal *ah,
2111 enum ath9k_ani_cmd cmd, int param)
2112{
2113 struct ath_hal_5416 *ahp = AH5416(ah);
2114 struct ar5416AniState *aniState = ahp->ah_curani;
2115
2116 switch (cmd & ahp->ah_ani_function) {
2117 case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
2118 u32 level = param;
2119
2120 if (level >= ARRAY_SIZE(ahp->ah_totalSizeDesired)) {
2121 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2122 "%s: level out of range (%u > %u)\n",
2123 __func__, level,
2124 (unsigned) ARRAY_SIZE(ahp->
2125 ah_totalSizeDesired));
2126 return false;
2127 }
2128
2129 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
2130 AR_PHY_DESIRED_SZ_TOT_DES,
2131 ahp->ah_totalSizeDesired[level]);
2132 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
2133 AR_PHY_AGC_CTL1_COARSE_LOW,
2134 ahp->ah_coarseLow[level]);
2135 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
2136 AR_PHY_AGC_CTL1_COARSE_HIGH,
2137 ahp->ah_coarseHigh[level]);
2138 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
2139 AR_PHY_FIND_SIG_FIRPWR,
2140 ahp->ah_firpwr[level]);
2141
2142 if (level > aniState->noiseImmunityLevel)
2143 ahp->ah_stats.ast_ani_niup++;
2144 else if (level < aniState->noiseImmunityLevel)
2145 ahp->ah_stats.ast_ani_nidown++;
2146 aniState->noiseImmunityLevel = level;
2147 break;
2148 }
2149 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
2150 const int m1ThreshLow[] = { 127, 50 };
2151 const int m2ThreshLow[] = { 127, 40 };
2152 const int m1Thresh[] = { 127, 0x4d };
2153 const int m2Thresh[] = { 127, 0x40 };
2154 const int m2CountThr[] = { 31, 16 };
2155 const int m2CountThrLow[] = { 63, 48 };
2156 u32 on = param ? 1 : 0;
2157
2158 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
2159 AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
2160 m1ThreshLow[on]);
2161 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
2162 AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
2163 m2ThreshLow[on]);
2164 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
2165 AR_PHY_SFCORR_M1_THRESH,
2166 m1Thresh[on]);
2167 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
2168 AR_PHY_SFCORR_M2_THRESH,
2169 m2Thresh[on]);
2170 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
2171 AR_PHY_SFCORR_M2COUNT_THR,
2172 m2CountThr[on]);
2173 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
2174 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
2175 m2CountThrLow[on]);
2176
2177 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2178 AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
2179 m1ThreshLow[on]);
2180 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2181 AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
2182 m2ThreshLow[on]);
2183 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2184 AR_PHY_SFCORR_EXT_M1_THRESH,
2185 m1Thresh[on]);
2186 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2187 AR_PHY_SFCORR_EXT_M2_THRESH,
2188 m2Thresh[on]);
2189
2190 if (on)
2191 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
2192 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
2193 else 578 else
2194 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, 579 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
2195 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 580 ar9280Modes_original_rxgain_9280_2,
2196 581 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
2197 if (!on != aniState->ofdmWeakSigDetectOff) { 582 } else
2198 if (on) 583 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
2199 ahp->ah_stats.ast_ani_ofdmon++; 584 ar9280Modes_original_rxgain_9280_2,
2200 else 585 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
2201 ahp->ah_stats.ast_ani_ofdmoff++;
2202 aniState->ofdmWeakSigDetectOff = !on;
2203 }
2204 break;
2205 }
2206 case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
2207 const int weakSigThrCck[] = { 8, 6 };
2208 u32 high = param ? 1 : 0;
2209
2210 REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
2211 AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
2212 weakSigThrCck[high]);
2213 if (high != aniState->cckWeakSigThreshold) {
2214 if (high)
2215 ahp->ah_stats.ast_ani_cckhigh++;
2216 else
2217 ahp->ah_stats.ast_ani_ccklow++;
2218 aniState->cckWeakSigThreshold = high;
2219 }
2220 break;
2221 }
2222 case ATH9K_ANI_FIRSTEP_LEVEL:{
2223 const int firstep[] = { 0, 4, 8 };
2224 u32 level = param;
2225
2226 if (level >= ARRAY_SIZE(firstep)) {
2227 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2228 "%s: level out of range (%u > %u)\n",
2229 __func__, level,
2230 (unsigned) ARRAY_SIZE(firstep));
2231 return false;
2232 }
2233 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
2234 AR_PHY_FIND_SIG_FIRSTEP,
2235 firstep[level]);
2236 if (level > aniState->firstepLevel)
2237 ahp->ah_stats.ast_ani_stepup++;
2238 else if (level < aniState->firstepLevel)
2239 ahp->ah_stats.ast_ani_stepdown++;
2240 aniState->firstepLevel = level;
2241 break;
2242 }
2243 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
2244 const int cycpwrThr1[] =
2245 { 2, 4, 6, 8, 10, 12, 14, 16 };
2246 u32 level = param;
2247
2248 if (level >= ARRAY_SIZE(cycpwrThr1)) {
2249 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2250 "%s: level out of range (%u > %u)\n",
2251 __func__, level,
2252 (unsigned)
2253 ARRAY_SIZE(cycpwrThr1));
2254 return false;
2255 }
2256 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
2257 AR_PHY_TIMING5_CYCPWR_THR1,
2258 cycpwrThr1[level]);
2259 if (level > aniState->spurImmunityLevel)
2260 ahp->ah_stats.ast_ani_spurup++;
2261 else if (level < aniState->spurImmunityLevel)
2262 ahp->ah_stats.ast_ani_spurdown++;
2263 aniState->spurImmunityLevel = level;
2264 break;
2265 }
2266 case ATH9K_ANI_PRESENT:
2267 break;
2268 default:
2269 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2270 "%s: invalid cmd %u\n", __func__, cmd);
2271 return false;
2272 }
2273
2274 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "%s: ANI parameters:\n", __func__);
2275 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2276 "noiseImmunityLevel=%d, spurImmunityLevel=%d, "
2277 "ofdmWeakSigDetectOff=%d\n",
2278 aniState->noiseImmunityLevel, aniState->spurImmunityLevel,
2279 !aniState->ofdmWeakSigDetectOff);
2280 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2281 "cckWeakSigThreshold=%d, "
2282 "firstepLevel=%d, listenTime=%d\n",
2283 aniState->cckWeakSigThreshold, aniState->firstepLevel,
2284 aniState->listenTime);
2285 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2286 "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
2287 aniState->cycleCount, aniState->ofdmPhyErrCount,
2288 aniState->cckPhyErrCount);
2289 return true;
2290}
2291
2292static void ath9k_ani_restart(struct ath_hal *ah)
2293{
2294 struct ath_hal_5416 *ahp = AH5416(ah);
2295 struct ar5416AniState *aniState;
2296
2297 if (!DO_ANI(ah))
2298 return;
2299
2300 aniState = ahp->ah_curani;
2301
2302 aniState->listenTime = 0;
2303 if (ahp->ah_hasHwPhyCounters) {
2304 if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) {
2305 aniState->ofdmPhyErrBase = 0;
2306 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2307 "OFDM Trigger is too high for hw counters\n");
2308 } else {
2309 aniState->ofdmPhyErrBase =
2310 AR_PHY_COUNTMAX - aniState->ofdmTrigHigh;
2311 }
2312 if (aniState->cckTrigHigh > AR_PHY_COUNTMAX) {
2313 aniState->cckPhyErrBase = 0;
2314 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2315 "CCK Trigger is too high for hw counters\n");
2316 } else {
2317 aniState->cckPhyErrBase =
2318 AR_PHY_COUNTMAX - aniState->cckTrigHigh;
2319 }
2320 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2321 "%s: Writing ofdmbase=%u cckbase=%u\n",
2322 __func__, aniState->ofdmPhyErrBase,
2323 aniState->cckPhyErrBase);
2324 REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase);
2325 REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase);
2326 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
2327 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
2328
2329 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
2330 }
2331 aniState->ofdmPhyErrCount = 0;
2332 aniState->cckPhyErrCount = 0;
2333}
2334
2335static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah)
2336{
2337 struct ath_hal_5416 *ahp = AH5416(ah);
2338 struct ath9k_channel *chan = ah->ah_curchan;
2339 struct ar5416AniState *aniState;
2340 enum wireless_mode mode;
2341 int32_t rssi;
2342
2343 if (!DO_ANI(ah))
2344 return;
2345
2346 aniState = ahp->ah_curani;
2347
2348 if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
2349 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
2350 aniState->noiseImmunityLevel + 1)) {
2351 return;
2352 }
2353 }
2354
2355 if (aniState->spurImmunityLevel < HAL_SPUR_IMMUNE_MAX) {
2356 if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
2357 aniState->spurImmunityLevel + 1)) {
2358 return;
2359 }
2360 }
2361
2362 if (ah->ah_opmode == ATH9K_M_HOSTAP) {
2363 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
2364 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2365 aniState->firstepLevel + 1);
2366 }
2367 return;
2368 }
2369 rssi = BEACON_RSSI(ahp);
2370 if (rssi > aniState->rssiThrHigh) {
2371 if (!aniState->ofdmWeakSigDetectOff) {
2372 if (ath9k_hw_ani_control(ah,
2373 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2374 false)) {
2375 ath9k_hw_ani_control(ah,
2376 ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
2377 0);
2378 return;
2379 }
2380 }
2381 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
2382 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2383 aniState->firstepLevel + 1);
2384 return;
2385 }
2386 } else if (rssi > aniState->rssiThrLow) {
2387 if (aniState->ofdmWeakSigDetectOff)
2388 ath9k_hw_ani_control(ah,
2389 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2390 true);
2391 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
2392 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2393 aniState->firstepLevel + 1);
2394 return;
2395 } else {
2396 mode = ath9k_hw_chan2wmode(ah, chan);
2397 if (mode == ATH9K_MODE_11G || mode == ATH9K_MODE_11B) {
2398 if (!aniState->ofdmWeakSigDetectOff)
2399 ath9k_hw_ani_control(ah,
2400 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2401 false);
2402 if (aniState->firstepLevel > 0)
2403 ath9k_hw_ani_control(ah,
2404 ATH9K_ANI_FIRSTEP_LEVEL,
2405 0);
2406 return;
2407 }
2408 }
2409}
2410
2411static void ath9k_hw_ani_cck_err_trigger(struct ath_hal *ah)
2412{
2413 struct ath_hal_5416 *ahp = AH5416(ah);
2414 struct ath9k_channel *chan = ah->ah_curchan;
2415 struct ar5416AniState *aniState;
2416 enum wireless_mode mode;
2417 int32_t rssi;
2418
2419 if (!DO_ANI(ah))
2420 return;
2421
2422 aniState = ahp->ah_curani;
2423 if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
2424 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
2425 aniState->noiseImmunityLevel + 1)) {
2426 return;
2427 }
2428 }
2429 if (ah->ah_opmode == ATH9K_M_HOSTAP) {
2430 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
2431 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2432 aniState->firstepLevel + 1);
2433 }
2434 return;
2435 }
2436 rssi = BEACON_RSSI(ahp);
2437 if (rssi > aniState->rssiThrLow) {
2438 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
2439 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2440 aniState->firstepLevel + 1);
2441 } else {
2442 mode = ath9k_hw_chan2wmode(ah, chan);
2443 if (mode == ATH9K_MODE_11G || mode == ATH9K_MODE_11B) {
2444 if (aniState->firstepLevel > 0)
2445 ath9k_hw_ani_control(ah,
2446 ATH9K_ANI_FIRSTEP_LEVEL,
2447 0);
2448 }
2449 }
2450}
2451
2452static void ath9k_ani_reset(struct ath_hal *ah)
2453{
2454 struct ath_hal_5416 *ahp = AH5416(ah);
2455 struct ar5416AniState *aniState;
2456 struct ath9k_channel *chan = ah->ah_curchan;
2457 int index;
2458
2459 if (!DO_ANI(ah))
2460 return;
2461
2462 index = ath9k_hw_get_ani_channel_idx(ah, chan);
2463 aniState = &ahp->ah_ani[index];
2464 ahp->ah_curani = aniState;
2465
2466 if (DO_ANI(ah) && ah->ah_opmode != ATH9K_M_STA
2467 && ah->ah_opmode != ATH9K_M_IBSS) {
2468 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2469 "%s: Reset ANI state opmode %u\n", __func__,
2470 ah->ah_opmode);
2471 ahp->ah_stats.ast_ani_reset++;
2472 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 0);
2473 ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0);
2474 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 0);
2475 ath9k_hw_ani_control(ah,
2476 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2477 !ATH9K_ANI_USE_OFDM_WEAK_SIG);
2478 ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR,
2479 ATH9K_ANI_CCK_WEAK_SIG_THR);
2480 ath9k_hw_setrxfilter(ah,
2481 ath9k_hw_getrxfilter(ah) |
2482 ATH9K_RX_FILTER_PHYERR);
2483 if (ah->ah_opmode == ATH9K_M_HOSTAP) {
2484 ahp->ah_curani->ofdmTrigHigh =
2485 ah->ah_config.ofdm_trig_high;
2486 ahp->ah_curani->ofdmTrigLow =
2487 ah->ah_config.ofdm_trig_low;
2488 ahp->ah_curani->cckTrigHigh =
2489 ah->ah_config.cck_trig_high;
2490 ahp->ah_curani->cckTrigLow =
2491 ah->ah_config.cck_trig_low;
2492 }
2493 ath9k_ani_restart(ah);
2494 return;
2495 }
2496
2497 if (aniState->noiseImmunityLevel != 0)
2498 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
2499 aniState->noiseImmunityLevel);
2500 if (aniState->spurImmunityLevel != 0)
2501 ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
2502 aniState->spurImmunityLevel);
2503 if (aniState->ofdmWeakSigDetectOff)
2504 ath9k_hw_ani_control(ah,
2505 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2506 !aniState->ofdmWeakSigDetectOff);
2507 if (aniState->cckWeakSigThreshold)
2508 ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR,
2509 aniState->cckWeakSigThreshold);
2510 if (aniState->firstepLevel != 0)
2511 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2512 aniState->firstepLevel);
2513 if (ahp->ah_hasHwPhyCounters) {
2514 ath9k_hw_setrxfilter(ah,
2515 ath9k_hw_getrxfilter(ah) &
2516 ~ATH9K_RX_FILTER_PHYERR);
2517 ath9k_ani_restart(ah);
2518 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
2519 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
2520
2521 } else {
2522 ath9k_ani_restart(ah);
2523 ath9k_hw_setrxfilter(ah,
2524 ath9k_hw_getrxfilter(ah) |
2525 ATH9K_RX_FILTER_PHYERR);
2526 }
2527}
2528
2529/*
2530 * Process a MIB interrupt. We may potentially be invoked because
2531 * any of the MIB counters overflow/trigger so don't assume we're
2532 * here because a PHY error counter triggered.
2533 */
2534void ath9k_hw_procmibevent(struct ath_hal *ah,
2535 const struct ath9k_node_stats *stats)
2536{
2537 struct ath_hal_5416 *ahp = AH5416(ah);
2538 u32 phyCnt1, phyCnt2;
2539
2540 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Processing Mib Intr\n");
2541 /* Reset these counters regardless */
2542 REG_WRITE(ah, AR_FILT_OFDM, 0);
2543 REG_WRITE(ah, AR_FILT_CCK, 0);
2544 if (!(REG_READ(ah, AR_SLP_MIB_CTRL) & AR_SLP_MIB_PENDING))
2545 REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR);
2546
2547 /* Clear the mib counters and save them in the stats */
2548 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
2549 ahp->ah_stats.ast_nodestats = *stats;
2550
2551 if (!DO_ANI(ah))
2552 return;
2553
2554 /* NB: these are not reset-on-read */
2555 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
2556 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
2557 if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) ||
2558 ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) {
2559 struct ar5416AniState *aniState = ahp->ah_curani;
2560 u32 ofdmPhyErrCnt, cckPhyErrCnt;
2561
2562 /* NB: only use ast_ani_*errs with AH_PRIVATE_DIAG */
2563 ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase;
2564 ahp->ah_stats.ast_ani_ofdmerrs +=
2565 ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
2566 aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
2567
2568 cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase;
2569 ahp->ah_stats.ast_ani_cckerrs +=
2570 cckPhyErrCnt - aniState->cckPhyErrCount;
2571 aniState->cckPhyErrCount = cckPhyErrCnt;
2572
2573 /*
2574 * NB: figure out which counter triggered. If both
2575 * trigger we'll only deal with one as the processing
2576 * clobbers the error counter so the trigger threshold
2577 * check will never be true.
2578 */
2579 if (aniState->ofdmPhyErrCount > aniState->ofdmTrigHigh)
2580 ath9k_hw_ani_ofdm_err_trigger(ah);
2581 if (aniState->cckPhyErrCount > aniState->cckTrigHigh)
2582 ath9k_hw_ani_cck_err_trigger(ah);
2583 /* NB: always restart to insure the h/w counters are reset */
2584 ath9k_ani_restart(ah);
2585 }
2586}
2587
2588static void ath9k_hw_ani_lower_immunity(struct ath_hal *ah)
2589{
2590 struct ath_hal_5416 *ahp = AH5416(ah);
2591 struct ar5416AniState *aniState;
2592 int32_t rssi;
2593
2594 aniState = ahp->ah_curani;
2595
2596 if (ah->ah_opmode == ATH9K_M_HOSTAP) {
2597 if (aniState->firstepLevel > 0) {
2598 if (ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2599 aniState->firstepLevel - 1)) {
2600 return;
2601 }
2602 }
2603 } else {
2604 rssi = BEACON_RSSI(ahp);
2605 if (rssi > aniState->rssiThrHigh) {
2606 /* XXX: Handle me */
2607 } else if (rssi > aniState->rssiThrLow) {
2608 if (aniState->ofdmWeakSigDetectOff) {
2609 if (ath9k_hw_ani_control(ah,
2610 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2611 true) ==
2612 true) {
2613 return;
2614 }
2615 }
2616 if (aniState->firstepLevel > 0) {
2617 if (ath9k_hw_ani_control
2618 (ah, ATH9K_ANI_FIRSTEP_LEVEL,
2619 aniState->firstepLevel - 1) ==
2620 true) {
2621 return;
2622 }
2623 }
2624 } else {
2625 if (aniState->firstepLevel > 0) {
2626 if (ath9k_hw_ani_control
2627 (ah, ATH9K_ANI_FIRSTEP_LEVEL,
2628 aniState->firstepLevel - 1) ==
2629 true) {
2630 return;
2631 }
2632 }
2633 }
2634 }
2635
2636 if (aniState->spurImmunityLevel > 0) {
2637 if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
2638 aniState->spurImmunityLevel - 1)) {
2639 return;
2640 }
2641 }
2642
2643 if (aniState->noiseImmunityLevel > 0) {
2644 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
2645 aniState->noiseImmunityLevel - 1);
2646 return;
2647 }
2648}
2649
2650static int32_t ath9k_hw_ani_get_listen_time(struct ath_hal *ah)
2651{
2652 struct ath_hal_5416 *ahp = AH5416(ah);
2653 struct ar5416AniState *aniState;
2654 u32 txFrameCount, rxFrameCount, cycleCount;
2655 int32_t listenTime;
2656
2657 txFrameCount = REG_READ(ah, AR_TFCNT);
2658 rxFrameCount = REG_READ(ah, AR_RFCNT);
2659 cycleCount = REG_READ(ah, AR_CCCNT);
2660
2661 aniState = ahp->ah_curani;
2662 if (aniState->cycleCount == 0 || aniState->cycleCount > cycleCount) {
2663
2664 listenTime = 0;
2665 ahp->ah_stats.ast_ani_lzero++;
2666 } else {
2667 int32_t ccdelta = cycleCount - aniState->cycleCount;
2668 int32_t rfdelta = rxFrameCount - aniState->rxFrameCount;
2669 int32_t tfdelta = txFrameCount - aniState->txFrameCount;
2670 listenTime = (ccdelta - rfdelta - tfdelta) / 44000;
2671 }
2672 aniState->cycleCount = cycleCount;
2673 aniState->txFrameCount = txFrameCount;
2674 aniState->rxFrameCount = rxFrameCount;
2675
2676 return listenTime;
2677} 586}
2678 587
2679void ath9k_hw_ani_monitor(struct ath_hal *ah, 588static void ath9k_hw_init_txgain_ini(struct ath_hal *ah)
2680 const struct ath9k_node_stats *stats,
2681 struct ath9k_channel *chan)
2682{ 589{
590 u32 txgain_type;
2683 struct ath_hal_5416 *ahp = AH5416(ah); 591 struct ath_hal_5416 *ahp = AH5416(ah);
2684 struct ar5416AniState *aniState;
2685 int32_t listenTime;
2686
2687 aniState = ahp->ah_curani;
2688 ahp->ah_stats.ast_nodestats = *stats;
2689
2690 listenTime = ath9k_hw_ani_get_listen_time(ah);
2691 if (listenTime < 0) {
2692 ahp->ah_stats.ast_ani_lneg++;
2693 ath9k_ani_restart(ah);
2694 return;
2695 }
2696
2697 aniState->listenTime += listenTime;
2698
2699 if (ahp->ah_hasHwPhyCounters) {
2700 u32 phyCnt1, phyCnt2;
2701 u32 ofdmPhyErrCnt, cckPhyErrCnt;
2702
2703 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
2704
2705 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
2706 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
2707
2708 if (phyCnt1 < aniState->ofdmPhyErrBase ||
2709 phyCnt2 < aniState->cckPhyErrBase) {
2710 if (phyCnt1 < aniState->ofdmPhyErrBase) {
2711 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2712 "%s: phyCnt1 0x%x, resetting "
2713 "counter value to 0x%x\n",
2714 __func__, phyCnt1,
2715 aniState->ofdmPhyErrBase);
2716 REG_WRITE(ah, AR_PHY_ERR_1,
2717 aniState->ofdmPhyErrBase);
2718 REG_WRITE(ah, AR_PHY_ERR_MASK_1,
2719 AR_PHY_ERR_OFDM_TIMING);
2720 }
2721 if (phyCnt2 < aniState->cckPhyErrBase) {
2722 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2723 "%s: phyCnt2 0x%x, resetting "
2724 "counter value to 0x%x\n",
2725 __func__, phyCnt2,
2726 aniState->cckPhyErrBase);
2727 REG_WRITE(ah, AR_PHY_ERR_2,
2728 aniState->cckPhyErrBase);
2729 REG_WRITE(ah, AR_PHY_ERR_MASK_2,
2730 AR_PHY_ERR_CCK_TIMING);
2731 }
2732 return;
2733 }
2734
2735 ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase;
2736 ahp->ah_stats.ast_ani_ofdmerrs +=
2737 ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
2738 aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
2739
2740 cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase;
2741 ahp->ah_stats.ast_ani_cckerrs +=
2742 cckPhyErrCnt - aniState->cckPhyErrCount;
2743 aniState->cckPhyErrCount = cckPhyErrCnt;
2744 }
2745
2746 if (!DO_ANI(ah))
2747 return;
2748
2749 if (aniState->listenTime > 5 * ahp->ah_aniPeriod) {
2750 if (aniState->ofdmPhyErrCount <= aniState->listenTime *
2751 aniState->ofdmTrigLow / 1000 &&
2752 aniState->cckPhyErrCount <= aniState->listenTime *
2753 aniState->cckTrigLow / 1000)
2754 ath9k_hw_ani_lower_immunity(ah);
2755 ath9k_ani_restart(ah);
2756 } else if (aniState->listenTime > ahp->ah_aniPeriod) {
2757 if (aniState->ofdmPhyErrCount > aniState->listenTime *
2758 aniState->ofdmTrigHigh / 1000) {
2759 ath9k_hw_ani_ofdm_err_trigger(ah);
2760 ath9k_ani_restart(ah);
2761 } else if (aniState->cckPhyErrCount >
2762 aniState->listenTime * aniState->cckTrigHigh /
2763 1000) {
2764 ath9k_hw_ani_cck_err_trigger(ah);
2765 ath9k_ani_restart(ah);
2766 }
2767 }
2768}
2769
2770#ifndef ATH_NF_PER_CHAN
2771static void ath9k_init_nfcal_hist_buffer(struct ath_hal *ah)
2772{
2773 int i, j;
2774
2775 for (i = 0; i < NUM_NF_READINGS; i++) {
2776 ah->nfCalHist[i].currIndex = 0;
2777 ah->nfCalHist[i].privNF = AR_PHY_CCA_MAX_GOOD_VALUE;
2778 ah->nfCalHist[i].invalidNFcount =
2779 AR_PHY_CCA_FILTERWINDOW_LENGTH;
2780 for (j = 0; j < ATH9K_NF_CAL_HIST_MAX; j++) {
2781 ah->nfCalHist[i].nfCalBuffer[j] =
2782 AR_PHY_CCA_MAX_GOOD_VALUE;
2783 }
2784 }
2785 return;
2786}
2787#endif
2788
2789static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah,
2790 u32 gpio, u32 type)
2791{
2792 int addr;
2793 u32 gpio_shift, tmp;
2794
2795 if (gpio > 11)
2796 addr = AR_GPIO_OUTPUT_MUX3;
2797 else if (gpio > 5)
2798 addr = AR_GPIO_OUTPUT_MUX2;
2799 else
2800 addr = AR_GPIO_OUTPUT_MUX1;
2801
2802 gpio_shift = (gpio % 6) * 5;
2803
2804 if (AR_SREV_9280_20_OR_LATER(ah)
2805 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2806 REG_RMW(ah, addr, (type << gpio_shift),
2807 (0x1f << gpio_shift));
2808 } else {
2809 tmp = REG_READ(ah, addr);
2810 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2811 tmp &= ~(0x1f << gpio_shift);
2812 tmp |= (type << gpio_shift);
2813 REG_WRITE(ah, addr, tmp);
2814 }
2815}
2816
2817void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,
2818 u32 ah_signal_type)
2819{
2820 u32 gpio_shift;
2821
2822 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2823
2824 gpio_shift = 2 * gpio;
2825
2826 REG_RMW(ah,
2827 AR_GPIO_OE_OUT,
2828 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2829 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2830}
2831
2832void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val)
2833{
2834 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2835 AR_GPIO_BIT(gpio));
2836}
2837
2838/*
2839 * Configure GPIO Input lines
2840 */
2841void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio)
2842{
2843 u32 gpio_shift;
2844
2845 ASSERT(gpio < ah->ah_caps.num_gpio_pins);
2846
2847 gpio_shift = gpio << 1;
2848
2849 REG_RMW(ah,
2850 AR_GPIO_OE_OUT,
2851 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2852 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2853}
2854
2855#ifdef CONFIG_RFKILL
2856static void ath9k_enable_rfkill(struct ath_hal *ah)
2857{
2858 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2859 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
2860
2861 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
2862 AR_GPIO_INPUT_MUX2_RFSILENT);
2863 592
2864 ath9k_hw_cfg_gpio_input(ah, ah->ah_rfkill_gpio); 593 if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
2865 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB); 594 txgain_type = ath9k_hw_get_eeprom(ah, EEP_TXGAIN_TYPE);
2866}
2867#endif
2868
2869u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio)
2870{
2871 if (gpio >= ah->ah_caps.num_gpio_pins)
2872 return 0xffffffff;
2873 595
2874 if (AR_SREV_9280_10_OR_LATER(ah)) { 596 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
2875 return (MS 597 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
2876 (REG_READ(ah, AR_GPIO_IN_OUT), 598 ar9280Modes_high_power_tx_gain_9280_2,
2877 AR928X_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) != 0; 599 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
2878 } else { 600 else
2879 return (MS(REG_READ(ah, AR_GPIO_IN_OUT), AR_GPIO_IN_VAL) & 601 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
2880 AR_GPIO_BIT(gpio)) != 0; 602 ar9280Modes_original_tx_gain_9280_2,
2881 } 603 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
604 } else
605 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
606 ar9280Modes_original_tx_gain_9280_2,
607 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
2882} 608}
2883 609
2884static int ath9k_hw_post_attach(struct ath_hal *ah) 610static int ath9k_hw_post_attach(struct ath_hal *ah)
@@ -2887,7 +613,7 @@ static int ath9k_hw_post_attach(struct ath_hal *ah)
2887 613
2888 if (!ath9k_hw_chip_test(ah)) { 614 if (!ath9k_hw_chip_test(ah)) {
2889 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, 615 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
2890 "%s: hardware self-test failed\n", __func__); 616 "hardware self-test failed\n");
2891 return -ENODEV; 617 return -ENODEV;
2892 } 618 }
2893 619
@@ -2906,365 +632,17 @@ static int ath9k_hw_post_attach(struct ath_hal *ah)
2906 ath9k_hw_ani_setup(ah); 632 ath9k_hw_ani_setup(ah);
2907 ath9k_hw_ani_attach(ah); 633 ath9k_hw_ani_attach(ah);
2908 } 634 }
2909 return 0;
2910}
2911
2912static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
2913 struct ar5416_eeprom *pEepData,
2914 u32 reg, u32 value)
2915{
2916 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
2917
2918 switch (ah->ah_devid) {
2919 case AR9280_DEVID_PCI:
2920 if (reg == 0x7894) {
2921 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2922 "ini VAL: %x EEPROM: %x\n", value,
2923 (pBase->version & 0xff));
2924
2925 if ((pBase->version & 0xff) > 0x0a) {
2926 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2927 "PWDCLKIND: %d\n",
2928 pBase->pwdclkind);
2929 value &= ~AR_AN_TOP2_PWDCLKIND;
2930 value |= AR_AN_TOP2_PWDCLKIND & (pBase->
2931 pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
2932 } else {
2933 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2934 "PWDCLKIND Earlier Rev\n");
2935 }
2936
2937 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2938 "final ini VAL: %x\n", value);
2939 }
2940 break;
2941 }
2942 return value;
2943}
2944
2945static bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
2946{
2947 struct ath_hal_5416 *ahp = AH5416(ah);
2948 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2949 u16 capField = 0, eeval;
2950
2951 eeval = ath9k_hw_get_eeprom(ahp, EEP_REG_0);
2952
2953 ah->ah_currentRD = eeval;
2954
2955 eeval = ath9k_hw_get_eeprom(ahp, EEP_REG_1);
2956 ah->ah_currentRDExt = eeval;
2957
2958 capField = ath9k_hw_get_eeprom(ahp, EEP_OP_CAP);
2959
2960 if (ah->ah_opmode != ATH9K_M_HOSTAP &&
2961 ah->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2962 if (ah->ah_currentRD == 0x64 || ah->ah_currentRD == 0x65)
2963 ah->ah_currentRD += 5;
2964 else if (ah->ah_currentRD == 0x41)
2965 ah->ah_currentRD = 0x43;
2966 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
2967 "%s: regdomain mapped to 0x%x\n", __func__,
2968 ah->ah_currentRD);
2969 }
2970
2971 eeval = ath9k_hw_get_eeprom(ahp, EEP_OP_MODE);
2972 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
2973
2974 if (eeval & AR5416_OPFLAGS_11A) {
2975 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
2976 if (ah->ah_config.ht_enable) {
2977 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
2978 set_bit(ATH9K_MODE_11NA_HT20,
2979 pCap->wireless_modes);
2980 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
2981 set_bit(ATH9K_MODE_11NA_HT40PLUS,
2982 pCap->wireless_modes);
2983 set_bit(ATH9K_MODE_11NA_HT40MINUS,
2984 pCap->wireless_modes);
2985 }
2986 }
2987 }
2988
2989 if (eeval & AR5416_OPFLAGS_11G) {
2990 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
2991 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2992 if (ah->ah_config.ht_enable) {
2993 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
2994 set_bit(ATH9K_MODE_11NG_HT20,
2995 pCap->wireless_modes);
2996 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
2997 set_bit(ATH9K_MODE_11NG_HT40PLUS,
2998 pCap->wireless_modes);
2999 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3000 pCap->wireless_modes);
3001 }
3002 }
3003 }
3004
3005 pCap->tx_chainmask = ath9k_hw_get_eeprom(ahp, EEP_TX_MASK);
3006 if ((ah->ah_isPciExpress)
3007 || (eeval & AR5416_OPFLAGS_11A)) {
3008 pCap->rx_chainmask =
3009 ath9k_hw_get_eeprom(ahp, EEP_RX_MASK);
3010 } else {
3011 pCap->rx_chainmask =
3012 (ath9k_hw_gpio_get(ah, 0)) ? 0x5 : 0x7;
3013 }
3014
3015 if (!(AR_SREV_9280(ah) && (ah->ah_macRev == 0)))
3016 ahp->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA;
3017
3018 pCap->low_2ghz_chan = 2312;
3019 pCap->high_2ghz_chan = 2732;
3020
3021 pCap->low_5ghz_chan = 4920;
3022 pCap->high_5ghz_chan = 6100;
3023
3024 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3025 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3026 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3027
3028 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3029 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3030 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3031
3032 pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD;
3033
3034 if (ah->ah_config.ht_enable)
3035 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3036 else
3037 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3038
3039 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3040 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3041 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3042 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3043
3044 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3045 pCap->total_queues =
3046 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3047 else
3048 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3049
3050 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3051 pCap->keycache_size =
3052 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3053 else
3054 pCap->keycache_size = AR_KEYTABLE_SIZE;
3055
3056 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3057 pCap->num_mr_retries = 4;
3058 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3059
3060 if (AR_SREV_9280_10_OR_LATER(ah))
3061 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3062 else
3063 pCap->num_gpio_pins = AR_NUM_GPIO;
3064
3065 if (AR_SREV_9280_10_OR_LATER(ah)) {
3066 pCap->hw_caps |= ATH9K_HW_CAP_WOW;
3067 pCap->hw_caps |= ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3068 } else {
3069 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW;
3070 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3071 }
3072
3073 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3074 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3075 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3076 } else {
3077 pCap->rts_aggr_limit = (8 * 1024);
3078 }
3079
3080 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3081
3082#ifdef CONFIG_RFKILL
3083 ah->ah_rfsilent = ath9k_hw_get_eeprom(ahp, EEP_RF_SILENT);
3084 if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) {
3085 ah->ah_rfkill_gpio =
3086 MS(ah->ah_rfsilent, EEP_RFSILENT_GPIO_SEL);
3087 ah->ah_rfkill_polarity =
3088 MS(ah->ah_rfsilent, EEP_RFSILENT_POLARITY);
3089
3090 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3091 }
3092#endif
3093
3094 if ((ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) ||
3095 (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE) ||
3096 (ah->ah_macVersion == AR_SREV_VERSION_9160) ||
3097 (ah->ah_macVersion == AR_SREV_VERSION_9100) ||
3098 (ah->ah_macVersion == AR_SREV_VERSION_9280))
3099 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3100 else
3101 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3102
3103 if (AR_SREV_9280(ah))
3104 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3105 else
3106 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3107
3108 if (ah->ah_currentRDExt & (1 << REG_EXT_JAPAN_MIDBAND)) {
3109 pCap->reg_cap =
3110 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3111 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3112 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3113 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3114 } else {
3115 pCap->reg_cap =
3116 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3117 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3118 }
3119
3120 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3121
3122 pCap->num_antcfg_5ghz =
3123 ath9k_hw_get_num_ant_config(ahp, IEEE80211_BAND_5GHZ);
3124 pCap->num_antcfg_2ghz =
3125 ath9k_hw_get_num_ant_config(ahp, IEEE80211_BAND_2GHZ);
3126
3127 return true;
3128}
3129
3130static void ar5416DisablePciePhy(struct ath_hal *ah)
3131{
3132 if (!AR_SREV_9100(ah))
3133 return;
3134
3135 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
3136 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
3137 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
3138 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
3139 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
3140 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
3141 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3142 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3143 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
3144
3145 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3146}
3147
3148static void ath9k_set_power_sleep(struct ath_hal *ah, int setChip)
3149{
3150 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
3151 if (setChip) {
3152 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
3153 AR_RTC_FORCE_WAKE_EN);
3154 if (!AR_SREV_9100(ah))
3155 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
3156
3157 REG_CLR_BIT(ah, (u16) (AR_RTC_RESET),
3158 AR_RTC_RESET_EN);
3159 }
3160}
3161
3162static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip)
3163{
3164 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
3165 if (setChip) {
3166 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3167
3168 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3169 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
3170 AR_RTC_FORCE_WAKE_ON_INT);
3171 } else {
3172 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
3173 AR_RTC_FORCE_WAKE_EN);
3174 }
3175 }
3176}
3177
3178static bool ath9k_hw_set_power_awake(struct ath_hal *ah,
3179 int setChip)
3180{
3181 u32 val;
3182 int i;
3183
3184 if (setChip) {
3185 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) ==
3186 AR_RTC_STATUS_SHUTDOWN) {
3187 if (ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)
3188 != true) {
3189 return false;
3190 }
3191 }
3192 if (AR_SREV_9100(ah))
3193 REG_SET_BIT(ah, AR_RTC_RESET,
3194 AR_RTC_RESET_EN);
3195
3196 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
3197 AR_RTC_FORCE_WAKE_EN);
3198 udelay(50);
3199
3200 for (i = POWER_UP_TIME / 50; i > 0; i--) {
3201 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
3202 if (val == AR_RTC_STATUS_ON)
3203 break;
3204 udelay(50);
3205 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
3206 AR_RTC_FORCE_WAKE_EN);
3207 }
3208 if (i == 0) {
3209 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
3210 "%s: Failed to wakeup in %uus\n",
3211 __func__, POWER_UP_TIME / 20);
3212 return false;
3213 }
3214 }
3215
3216 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
3217 return true;
3218}
3219
3220bool ath9k_hw_setpower(struct ath_hal *ah,
3221 enum ath9k_power_mode mode)
3222{
3223 struct ath_hal_5416 *ahp = AH5416(ah);
3224 static const char *modes[] = {
3225 "AWAKE",
3226 "FULL-SLEEP",
3227 "NETWORK SLEEP",
3228 "UNDEFINED"
3229 };
3230 int status = true, setChip = true;
3231 635
3232 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s: %s -> %s (%s)\n", __func__, 636 return 0;
3233 modes[ahp->ah_powerMode], modes[mode],
3234 setChip ? "set chip " : "");
3235
3236 switch (mode) {
3237 case ATH9K_PM_AWAKE:
3238 status = ath9k_hw_set_power_awake(ah, setChip);
3239 break;
3240 case ATH9K_PM_FULL_SLEEP:
3241 ath9k_set_power_sleep(ah, setChip);
3242 ahp->ah_chipFullSleep = true;
3243 break;
3244 case ATH9K_PM_NETWORK_SLEEP:
3245 ath9k_set_power_network_sleep(ah, setChip);
3246 break;
3247 default:
3248 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
3249 "%s: unknown power mode %u\n", __func__, mode);
3250 return false;
3251 }
3252 ahp->ah_powerMode = mode;
3253 return status;
3254} 637}
3255 638
3256static struct ath_hal *ath9k_hw_do_attach(u16 devid, 639static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
3257 struct ath_softc *sc, 640 void __iomem *mem, int *status)
3258 void __iomem *mem,
3259 int *status)
3260{ 641{
3261 struct ath_hal_5416 *ahp; 642 struct ath_hal_5416 *ahp;
3262 struct ath_hal *ah; 643 struct ath_hal *ah;
3263 int ecode; 644 int ecode;
3264#ifndef CONFIG_SLOW_ANT_DIV 645 u32 i, j;
3265 u32 i;
3266 u32 j;
3267#endif
3268 646
3269 ahp = ath9k_hw_newstate(devid, sc, mem, status); 647 ahp = ath9k_hw_newstate(devid, sc, mem, status);
3270 if (ahp == NULL) 648 if (ahp == NULL)
@@ -3278,15 +656,13 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid,
3278 ahp->ah_intrMitigation = true; 656 ahp->ah_intrMitigation = true;
3279 657
3280 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 658 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
3281 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: couldn't reset chip\n", 659 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Couldn't reset chip\n");
3282 __func__);
3283 ecode = -EIO; 660 ecode = -EIO;
3284 goto bad; 661 goto bad;
3285 } 662 }
3286 663
3287 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 664 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
3288 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: couldn't wakeup chip\n", 665 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Couldn't wakeup chip\n");
3289 __func__);
3290 ecode = -EIO; 666 ecode = -EIO;
3291 goto bad; 667 goto bad;
3292 } 668 }
@@ -3300,18 +676,18 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid,
3300 SER_REG_MODE_OFF; 676 SER_REG_MODE_OFF;
3301 } 677 }
3302 } 678 }
679
3303 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 680 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3304 "%s: serialize_regmode is %d\n", 681 "serialize_regmode is %d\n",
3305 __func__, ah->ah_config.serialize_regmode); 682 ah->ah_config.serialize_regmode);
3306 683
3307 if ((ah->ah_macVersion != AR_SREV_VERSION_5416_PCI) && 684 if ((ah->ah_macVersion != AR_SREV_VERSION_5416_PCI) &&
3308 (ah->ah_macVersion != AR_SREV_VERSION_5416_PCIE) && 685 (ah->ah_macVersion != AR_SREV_VERSION_5416_PCIE) &&
3309 (ah->ah_macVersion != AR_SREV_VERSION_9160) && 686 (ah->ah_macVersion != AR_SREV_VERSION_9160) &&
3310 (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah))) { 687 (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) {
3311 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 688 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3312 "%s: Mac Chip Rev 0x%02x.%x is not supported by " 689 "Mac Chip Rev 0x%02x.%x is not supported by "
3313 "this driver\n", __func__, 690 "this driver\n", ah->ah_macVersion, ah->ah_macRev);
3314 ah->ah_macVersion, ah->ah_macRev);
3315 ecode = -EOPNOTSUPP; 691 ecode = -EOPNOTSUPP;
3316 goto bad; 692 goto bad;
3317 } 693 }
@@ -3341,8 +717,7 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid,
3341 ahp->ah_adcDcCalInitData.calData = 717 ahp->ah_adcDcCalInitData.calData =
3342 &adc_init_dc_cal; 718 &adc_init_dc_cal;
3343 } 719 }
3344 ahp->ah_suppCals = 720 ahp->ah_suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
3345 ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
3346 } 721 }
3347 722
3348 if (AR_SREV_9160(ah)) { 723 if (AR_SREV_9160(ah)) {
@@ -3352,16 +727,46 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid,
3352 } else { 727 } else {
3353 ahp->ah_ani_function = ATH9K_ANI_ALL; 728 ahp->ah_ani_function = ATH9K_ANI_ALL;
3354 if (AR_SREV_9280_10_OR_LATER(ah)) { 729 if (AR_SREV_9280_10_OR_LATER(ah)) {
3355 ahp->ah_ani_function &= 730 ahp->ah_ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
3356 ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
3357 } 731 }
3358 } 732 }
3359 733
3360 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 734 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3361 "%s: This Mac Chip Rev 0x%02x.%x is \n", __func__, 735 "This Mac Chip Rev 0x%02x.%x is \n",
3362 ah->ah_macVersion, ah->ah_macRev); 736 ah->ah_macVersion, ah->ah_macRev);
3363 737
3364 if (AR_SREV_9280_20_OR_LATER(ah)) { 738 if (AR_SREV_9285_12_OR_LATER(ah)) {
739 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285_1_2,
740 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
741 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9285Common_9285_1_2,
742 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
743
744 if (ah->ah_config.pcie_clock_req) {
745 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
746 ar9285PciePhy_clkreq_off_L1_9285_1_2,
747 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
748 } else {
749 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
750 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
751 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
752 2);
753 }
754 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
755 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285,
756 ARRAY_SIZE(ar9285Modes_9285), 6);
757 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9285Common_9285,
758 ARRAY_SIZE(ar9285Common_9285), 2);
759
760 if (ah->ah_config.pcie_clock_req) {
761 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
762 ar9285PciePhy_clkreq_off_L1_9285,
763 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
764 } else {
765 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
766 ar9285PciePhy_clkreq_always_on_L1_9285,
767 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
768 }
769 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
3365 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280_2, 770 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280_2,
3366 ARRAY_SIZE(ar9280Modes_9280_2), 6); 771 ARRAY_SIZE(ar9280Modes_9280_2), 6);
3367 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280_2, 772 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280_2,
@@ -3369,21 +774,16 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid,
3369 774
3370 if (ah->ah_config.pcie_clock_req) { 775 if (ah->ah_config.pcie_clock_req) {
3371 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes, 776 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
3372 ar9280PciePhy_clkreq_off_L1_9280, 777 ar9280PciePhy_clkreq_off_L1_9280,
3373 ARRAY_SIZE 778 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
3374 (ar9280PciePhy_clkreq_off_L1_9280),
3375 2);
3376 } else { 779 } else {
3377 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes, 780 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
3378 ar9280PciePhy_clkreq_always_on_L1_9280, 781 ar9280PciePhy_clkreq_always_on_L1_9280,
3379 ARRAY_SIZE 782 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
3380 (ar9280PciePhy_clkreq_always_on_L1_9280),
3381 2);
3382 } 783 }
3383 INIT_INI_ARRAY(&ahp->ah_iniModesAdditional, 784 INIT_INI_ARRAY(&ahp->ah_iniModesAdditional,
3384 ar9280Modes_fast_clock_9280_2, 785 ar9280Modes_fast_clock_9280_2,
3385 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 786 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
3386 3);
3387 } else if (AR_SREV_9280_10_OR_LATER(ah)) { 787 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
3388 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280, 788 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280,
3389 ARRAY_SIZE(ar9280Modes_9280), 6); 789 ARRAY_SIZE(ar9280Modes_9280), 6);
@@ -3469,13 +869,20 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid,
3469 if (ah->ah_isPciExpress) 869 if (ah->ah_isPciExpress)
3470 ath9k_hw_configpcipowersave(ah, 0); 870 ath9k_hw_configpcipowersave(ah, 0);
3471 else 871 else
3472 ar5416DisablePciePhy(ah); 872 ath9k_hw_disablepcie(ah);
3473 873
3474 ecode = ath9k_hw_post_attach(ah); 874 ecode = ath9k_hw_post_attach(ah);
3475 if (ecode != 0) 875 if (ecode != 0)
3476 goto bad; 876 goto bad;
3477 877
3478#ifndef CONFIG_SLOW_ANT_DIV 878 /* rxgain table */
879 if (AR_SREV_9280_20(ah))
880 ath9k_hw_init_rxgain_ini(ah);
881
882 /* txgain table */
883 if (AR_SREV_9280_20(ah))
884 ath9k_hw_init_txgain_ini(ah);
885
3479 if (ah->ah_devid == AR9280_DEVID_PCI) { 886 if (ah->ah_devid == AR9280_DEVID_PCI) {
3480 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) { 887 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
3481 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0); 888 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
@@ -3484,16 +891,16 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid,
3484 u32 val = INI_RA(&ahp->ah_iniModes, i, j); 891 u32 val = INI_RA(&ahp->ah_iniModes, i, j);
3485 892
3486 INI_RA(&ahp->ah_iniModes, i, j) = 893 INI_RA(&ahp->ah_iniModes, i, j) =
3487 ath9k_hw_ini_fixup(ah, &ahp->ah_eeprom, 894 ath9k_hw_ini_fixup(ah,
895 &ahp->ah_eeprom.def,
3488 reg, val); 896 reg, val);
3489 } 897 }
3490 } 898 }
3491 } 899 }
3492#endif
3493 900
3494 if (!ath9k_hw_fill_cap_info(ah)) { 901 if (!ath9k_hw_fill_cap_info(ah)) {
3495 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 902 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3496 "%s:failed ath9k_hw_fill_cap_info\n", __func__); 903 "failed ath9k_hw_fill_cap_info\n");
3497 ecode = -EINVAL; 904 ecode = -EINVAL;
3498 goto bad; 905 goto bad;
3499 } 906 }
@@ -3501,8 +908,7 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid,
3501 ecode = ath9k_hw_init_macaddr(ah); 908 ecode = ath9k_hw_init_macaddr(ah);
3502 if (ecode != 0) { 909 if (ecode != 0) {
3503 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 910 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3504 "%s: failed initializing mac address\n", 911 "failed initializing mac address\n");
3505 __func__);
3506 goto bad; 912 goto bad;
3507 } 913 }
3508 914
@@ -3511,1106 +917,569 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid,
3511 else 917 else
3512 ah->ah_txTrigLevel = (AR_FTRIG_512B >> AR_FTRIG_S); 918 ah->ah_txTrigLevel = (AR_FTRIG_512B >> AR_FTRIG_S);
3513 919
3514#ifndef ATH_NF_PER_CHAN
3515
3516 ath9k_init_nfcal_hist_buffer(ah); 920 ath9k_init_nfcal_hist_buffer(ah);
3517#endif
3518 921
3519 return ah; 922 return ah;
3520
3521bad: 923bad:
3522 if (ahp) 924 if (ahp)
3523 ath9k_hw_detach((struct ath_hal *) ahp); 925 ath9k_hw_detach((struct ath_hal *) ahp);
3524 if (status) 926 if (status)
3525 *status = ecode; 927 *status = ecode;
928
3526 return NULL; 929 return NULL;
3527} 930}
3528 931
3529void ath9k_hw_detach(struct ath_hal *ah) 932static void ath9k_hw_init_bb(struct ath_hal *ah,
933 struct ath9k_channel *chan)
3530{ 934{
3531 if (!AR_SREV_9100(ah)) 935 u32 synthDelay;
3532 ath9k_hw_ani_detach(ah);
3533 ath9k_hw_rfdetach(ah);
3534 936
3535 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 937 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
3536 kfree(ah); 938 if (IS_CHAN_B(chan))
939 synthDelay = (4 * synthDelay) / 22;
940 else
941 synthDelay /= 10;
942
943 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
944
945 udelay(synthDelay + BASE_ACTIVATE_DELAY);
3537} 946}
3538 947
3539bool ath9k_get_channel_edges(struct ath_hal *ah, 948static void ath9k_hw_init_qos(struct ath_hal *ah)
3540 u16 flags, u16 *low,
3541 u16 *high)
3542{ 949{
3543 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 950 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
951 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
3544 952
3545 if (flags & CHANNEL_5GHZ) { 953 REG_WRITE(ah, AR_QOS_NO_ACK,
3546 *low = pCap->low_5ghz_chan; 954 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
3547 *high = pCap->high_5ghz_chan; 955 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
3548 return true; 956 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
3549 }
3550 if ((flags & CHANNEL_2GHZ)) {
3551 *low = pCap->low_2ghz_chan;
3552 *high = pCap->high_2ghz_chan;
3553 957
3554 return true; 958 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
3555 } 959 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
3556 return false; 960 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
961 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
962 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
3557} 963}
3558 964
3559static inline bool ath9k_hw_fill_vpd_table(u8 pwrMin, 965static void ath9k_hw_init_pll(struct ath_hal *ah,
3560 u8 pwrMax, 966 struct ath9k_channel *chan)
3561 u8 *pPwrList,
3562 u8 *pVpdList,
3563 u16
3564 numIntercepts,
3565 u8 *pRetVpdList)
3566{ 967{
3567 u16 i, k; 968 u32 pll;
3568 u8 currPwr = pwrMin;
3569 u16 idxL = 0, idxR = 0;
3570
3571 for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) {
3572 ath9k_hw_get_lower_upper_index(currPwr, pPwrList,
3573 numIntercepts, &(idxL),
3574 &(idxR));
3575 if (idxR < 1)
3576 idxR = 1;
3577 if (idxL == numIntercepts - 1)
3578 idxL = (u16) (numIntercepts - 2);
3579 if (pPwrList[idxL] == pPwrList[idxR])
3580 k = pVpdList[idxL];
3581 else
3582 k = (u16) (((currPwr -
3583 pPwrList[idxL]) *
3584 pVpdList[idxR] +
3585 (pPwrList[idxR] -
3586 currPwr) * pVpdList[idxL]) /
3587 (pPwrList[idxR] -
3588 pPwrList[idxL]));
3589 pRetVpdList[i] = (u8) k;
3590 currPwr += 2;
3591 }
3592 969
3593 return true; 970 if (AR_SREV_9100(ah)) {
3594} 971 if (chan && IS_CHAN_5GHZ(chan))
972 pll = 0x1450;
973 else
974 pll = 0x1458;
975 } else {
976 if (AR_SREV_9280_10_OR_LATER(ah)) {
977 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
3595 978
3596static void 979 if (chan && IS_CHAN_HALF_RATE(chan))
3597ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hal *ah, 980 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
3598 struct ath9k_channel *chan, 981 else if (chan && IS_CHAN_QUARTER_RATE(chan))
3599 struct cal_data_per_freq *pRawDataSet, 982 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
3600 u8 *bChans,
3601 u16 availPiers,
3602 u16 tPdGainOverlap,
3603 int16_t *pMinCalPower,
3604 u16 *pPdGainBoundaries,
3605 u8 *pPDADCValues,
3606 u16 numXpdGains)
3607{
3608 int i, j, k;
3609 int16_t ss;
3610 u16 idxL = 0, idxR = 0, numPiers;
3611 static u8 vpdTableL[AR5416_NUM_PD_GAINS]
3612 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
3613 static u8 vpdTableR[AR5416_NUM_PD_GAINS]
3614 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
3615 static u8 vpdTableI[AR5416_NUM_PD_GAINS]
3616 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
3617
3618 u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
3619 u8 minPwrT4[AR5416_NUM_PD_GAINS];
3620 u8 maxPwrT4[AR5416_NUM_PD_GAINS];
3621 int16_t vpdStep;
3622 int16_t tmpVal;
3623 u16 sizeCurrVpdTable, maxIndex, tgtIndex;
3624 bool match;
3625 int16_t minDelta = 0;
3626 struct chan_centers centers;
3627 983
3628 ath9k_hw_get_channel_centers(ah, chan, &centers); 984 if (chan && IS_CHAN_5GHZ(chan)) {
985 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
3629 986
3630 for (numPiers = 0; numPiers < availPiers; numPiers++) {
3631 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
3632 break;
3633 }
3634 987
3635 match = ath9k_hw_get_lower_upper_index((u8) 988 if (AR_SREV_9280_20(ah)) {
3636 FREQ2FBIN(centers. 989 if (((chan->channel % 20) == 0)
3637 synth_center, 990 || ((chan->channel % 10) == 0))
3638 IS_CHAN_2GHZ 991 pll = 0x2850;
3639 (chan)), bChans, 992 else
3640 numPiers, &idxL, &idxR); 993 pll = 0x142c;
3641 994 }
3642 if (match) { 995 } else {
3643 for (i = 0; i < numXpdGains; i++) { 996 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
3644 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
3645 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
3646 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
3647 pRawDataSet[idxL].
3648 pwrPdg[i],
3649 pRawDataSet[idxL].
3650 vpdPdg[i],
3651 AR5416_PD_GAIN_ICEPTS,
3652 vpdTableI[i]);
3653 }
3654 } else {
3655 for (i = 0; i < numXpdGains; i++) {
3656 pVpdL = pRawDataSet[idxL].vpdPdg[i];
3657 pPwrL = pRawDataSet[idxL].pwrPdg[i];
3658 pVpdR = pRawDataSet[idxR].vpdPdg[i];
3659 pPwrR = pRawDataSet[idxR].pwrPdg[i];
3660
3661 minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
3662
3663 maxPwrT4[i] =
3664 min(pPwrL[AR5416_PD_GAIN_ICEPTS - 1],
3665 pPwrR[AR5416_PD_GAIN_ICEPTS - 1]);
3666
3667
3668 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
3669 pPwrL, pVpdL,
3670 AR5416_PD_GAIN_ICEPTS,
3671 vpdTableL[i]);
3672 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
3673 pPwrR, pVpdR,
3674 AR5416_PD_GAIN_ICEPTS,
3675 vpdTableR[i]);
3676
3677 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
3678 vpdTableI[i][j] =
3679 (u8) (ath9k_hw_interpolate
3680 ((u16)
3681 FREQ2FBIN(centers.
3682 synth_center,
3683 IS_CHAN_2GHZ
3684 (chan)),
3685 bChans[idxL],
3686 bChans[idxR], vpdTableL[i]
3687 [j], vpdTableR[i]
3688 [j]));
3689 } 997 }
3690 }
3691 }
3692 998
3693 *pMinCalPower = (int16_t) (minPwrT4[0] / 2); 999 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
3694
3695 k = 0;
3696 for (i = 0; i < numXpdGains; i++) {
3697 if (i == (numXpdGains - 1))
3698 pPdGainBoundaries[i] =
3699 (u16) (maxPwrT4[i] / 2);
3700 else
3701 pPdGainBoundaries[i] =
3702 (u16) ((maxPwrT4[i] +
3703 minPwrT4[i + 1]) / 4);
3704 1000
3705 pPdGainBoundaries[i] = 1001 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
3706 min((u16) AR5416_MAX_RATE_POWER,
3707 pPdGainBoundaries[i]);
3708 1002
3709 if ((i == 0) && !AR_SREV_5416_V20_OR_LATER(ah)) { 1003 if (chan && IS_CHAN_HALF_RATE(chan))
3710 minDelta = pPdGainBoundaries[0] - 23; 1004 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
3711 pPdGainBoundaries[0] = 23; 1005 else if (chan && IS_CHAN_QUARTER_RATE(chan))
3712 } else { 1006 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
3713 minDelta = 0;
3714 }
3715 1007
3716 if (i == 0) { 1008 if (chan && IS_CHAN_5GHZ(chan))
3717 if (AR_SREV_9280_10_OR_LATER(ah)) 1009 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
3718 ss = (int16_t) (0 - (minPwrT4[i] / 2));
3719 else 1010 else
3720 ss = 0; 1011 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
3721 } else { 1012 } else {
3722 ss = (int16_t) ((pPdGainBoundaries[i - 1] - 1013 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
3723 (minPwrT4[i] / 2)) -
3724 tPdGainOverlap + 1 + minDelta);
3725 }
3726 vpdStep = (int16_t) (vpdTableI[i][1] - vpdTableI[i][0]);
3727 vpdStep = (int16_t) ((vpdStep < 1) ? 1 : vpdStep);
3728
3729 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
3730 tmpVal = (int16_t) (vpdTableI[i][0] + ss * vpdStep);
3731 pPDADCValues[k++] =
3732 (u8) ((tmpVal < 0) ? 0 : tmpVal);
3733 ss++;
3734 }
3735
3736 sizeCurrVpdTable =
3737 (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
3738 tgtIndex = (u8) (pPdGainBoundaries[i] + tPdGainOverlap -
3739 (minPwrT4[i] / 2));
3740 maxIndex = (tgtIndex <
3741 sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable;
3742 1014
3743 while ((ss < maxIndex) 1015 if (chan && IS_CHAN_HALF_RATE(chan))
3744 && (k < (AR5416_NUM_PDADC_VALUES - 1))) { 1016 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
3745 pPDADCValues[k++] = vpdTableI[i][ss++]; 1017 else if (chan && IS_CHAN_QUARTER_RATE(chan))
3746 } 1018 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
3747 1019
3748 vpdStep = (int16_t) (vpdTableI[i][sizeCurrVpdTable - 1] - 1020 if (chan && IS_CHAN_5GHZ(chan))
3749 vpdTableI[i][sizeCurrVpdTable - 2]); 1021 pll |= SM(0xa, AR_RTC_PLL_DIV);
3750 vpdStep = (int16_t) ((vpdStep < 1) ? 1 : vpdStep); 1022 else
3751 1023 pll |= SM(0xb, AR_RTC_PLL_DIV);
3752 if (tgtIndex > maxIndex) {
3753 while ((ss <= tgtIndex)
3754 && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
3755 tmpVal = (int16_t) ((vpdTableI[i]
3756 [sizeCurrVpdTable -
3757 1] + (ss - maxIndex +
3758 1) * vpdStep));
3759 pPDADCValues[k++] = (u8) ((tmpVal >
3760 255) ? 255 : tmpVal);
3761 ss++;
3762 }
3763 } 1024 }
3764 } 1025 }
1026 REG_WRITE(ah, (u16) (AR_RTC_PLL_CONTROL), pll);
3765 1027
3766 while (i < AR5416_PD_GAINS_IN_MASK) { 1028 udelay(RTC_PLL_SETTLE_DELAY);
3767 pPdGainBoundaries[i] = pPdGainBoundaries[i - 1];
3768 i++;
3769 }
3770 1029
3771 while (k < AR5416_NUM_PDADC_VALUES) { 1030 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
3772 pPDADCValues[k] = pPDADCValues[k - 1];
3773 k++;
3774 }
3775 return;
3776} 1031}
3777 1032
3778static bool 1033static void ath9k_hw_init_chain_masks(struct ath_hal *ah)
3779ath9k_hw_set_power_cal_table(struct ath_hal *ah,
3780 struct ar5416_eeprom *pEepData,
3781 struct ath9k_channel *chan,
3782 int16_t *pTxPowerIndexOffset)
3783{ 1034{
3784 struct cal_data_per_freq *pRawDataset;
3785 u8 *pCalBChans = NULL;
3786 u16 pdGainOverlap_t2;
3787 static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
3788 u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
3789 u16 numPiers, i, j;
3790 int16_t tMinCalPower;
3791 u16 numXpdGain, xpdMask;
3792 u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
3793 u32 reg32, regOffset, regChainOffset;
3794 int16_t modalIdx;
3795 struct ath_hal_5416 *ahp = AH5416(ah); 1035 struct ath_hal_5416 *ahp = AH5416(ah);
1036 int rx_chainmask, tx_chainmask;
3796 1037
3797 modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0; 1038 rx_chainmask = ahp->ah_rxchainmask;
3798 xpdMask = pEepData->modalHeader[modalIdx].xpdGain; 1039 tx_chainmask = ahp->ah_txchainmask;
3799
3800 if ((pEepData->baseEepHeader.
3801 version & AR5416_EEP_VER_MINOR_MASK) >=
3802 AR5416_EEP_MINOR_VER_2) {
3803 pdGainOverlap_t2 =
3804 pEepData->modalHeader[modalIdx].pdGainOverlap;
3805 } else {
3806 pdGainOverlap_t2 =
3807 (u16) (MS
3808 (REG_READ(ah, AR_PHY_TPCRG5),
3809 AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
3810 }
3811
3812 if (IS_CHAN_2GHZ(chan)) {
3813 pCalBChans = pEepData->calFreqPier2G;
3814 numPiers = AR5416_NUM_2G_CAL_PIERS;
3815 } else {
3816 pCalBChans = pEepData->calFreqPier5G;
3817 numPiers = AR5416_NUM_5G_CAL_PIERS;
3818 }
3819
3820 numXpdGain = 0;
3821 1040
3822 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) { 1041 switch (rx_chainmask) {
3823 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) { 1042 case 0x5:
3824 if (numXpdGain >= AR5416_NUM_PD_GAINS) 1043 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
3825 break; 1044 AR_PHY_SWAP_ALT_CHAIN);
3826 xpdGainValues[numXpdGain] = 1045 case 0x3:
3827 (u16) (AR5416_PD_GAINS_IN_MASK - i); 1046 if (((ah)->ah_macVersion <= AR_SREV_VERSION_9160)) {
3828 numXpdGain++; 1047 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1048 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1049 break;
3829 } 1050 }
1051 case 0x1:
1052 case 0x2:
1053 case 0x7:
1054 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1055 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1056 break;
1057 default:
1058 break;
3830 } 1059 }
3831 1060
3832 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN, 1061 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
3833 (numXpdGain - 1) & 0x3); 1062 if (tx_chainmask == 0x5) {
3834 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1, 1063 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
3835 xpdGainValues[0]); 1064 AR_PHY_SWAP_ALT_CHAIN);
3836 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
3837 xpdGainValues[1]);
3838 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
3839 xpdGainValues[2]);
3840
3841 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
3842 if (AR_SREV_5416_V20_OR_LATER(ah) &&
3843 (ahp->ah_rxchainmask == 5 || ahp->ah_txchainmask == 5)
3844 && (i != 0)) {
3845 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
3846 } else
3847 regChainOffset = i * 0x1000;
3848 if (pEepData->baseEepHeader.txMask & (1 << i)) {
3849 if (IS_CHAN_2GHZ(chan))
3850 pRawDataset = pEepData->calPierData2G[i];
3851 else
3852 pRawDataset = pEepData->calPierData5G[i];
3853
3854 ath9k_hw_get_gain_boundaries_pdadcs(ah, chan,
3855 pRawDataset,
3856 pCalBChans,
3857 numPiers,
3858 pdGainOverlap_t2,
3859 &tMinCalPower,
3860 gainBoundaries,
3861 pdadcValues,
3862 numXpdGain);
3863
3864 if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) {
3865
3866 REG_WRITE(ah,
3867 AR_PHY_TPCRG5 + regChainOffset,
3868 SM(pdGainOverlap_t2,
3869 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
3870 | SM(gainBoundaries[0],
3871 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
3872 | SM(gainBoundaries[1],
3873 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
3874 | SM(gainBoundaries[2],
3875 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
3876 | SM(gainBoundaries[3],
3877 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
3878 }
3879
3880 regOffset =
3881 AR_PHY_BASE + (672 << 2) + regChainOffset;
3882 for (j = 0; j < 32; j++) {
3883 reg32 =
3884 ((pdadcValues[4 * j + 0] & 0xFF) << 0)
3885 | ((pdadcValues[4 * j + 1] & 0xFF) <<
3886 8) | ((pdadcValues[4 * j + 2] &
3887 0xFF) << 16) |
3888 ((pdadcValues[4 * j + 3] & 0xFF) <<
3889 24);
3890 REG_WRITE(ah, regOffset, reg32);
3891
3892 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
3893 "PDADC (%d,%4x): %4.4x %8.8x\n",
3894 i, regChainOffset, regOffset,
3895 reg32);
3896 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
3897 "PDADC: Chain %d | PDADC %3d Value %3d | "
3898 "PDADC %3d Value %3d | PDADC %3d Value %3d | "
3899 "PDADC %3d Value %3d |\n",
3900 i, 4 * j, pdadcValues[4 * j],
3901 4 * j + 1, pdadcValues[4 * j + 1],
3902 4 * j + 2, pdadcValues[4 * j + 2],
3903 4 * j + 3,
3904 pdadcValues[4 * j + 3]);
3905
3906 regOffset += 4;
3907 }
3908 }
3909 } 1065 }
3910 *pTxPowerIndexOffset = 0; 1066 if (AR_SREV_9100(ah))
3911 1067 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
3912 return true; 1068 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
3913} 1069}
3914 1070
3915void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore) 1071static void ath9k_hw_init_interrupt_masks(struct ath_hal *ah,
1072 enum nl80211_iftype opmode)
3916{ 1073{
3917 struct ath_hal_5416 *ahp = AH5416(ah); 1074 struct ath_hal_5416 *ahp = AH5416(ah);
3918 u8 i;
3919
3920 if (ah->ah_isPciExpress != true)
3921 return;
3922 1075
3923 if (ah->ah_config.pcie_powersave_enable == 2) 1076 ahp->ah_maskReg = AR_IMR_TXERR |
3924 return; 1077 AR_IMR_TXURN |
1078 AR_IMR_RXERR |
1079 AR_IMR_RXORN |
1080 AR_IMR_BCNMISC;
3925 1081
3926 if (restore) 1082 if (ahp->ah_intrMitigation)
3927 return; 1083 ahp->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1084 else
1085 ahp->ah_maskReg |= AR_IMR_RXOK;
3928 1086
3929 if (AR_SREV_9280_20_OR_LATER(ah)) { 1087 ahp->ah_maskReg |= AR_IMR_TXOK;
3930 for (i = 0; i < ahp->ah_iniPcieSerdes.ia_rows; i++) {
3931 REG_WRITE(ah, INI_RA(&ahp->ah_iniPcieSerdes, i, 0),
3932 INI_RA(&ahp->ah_iniPcieSerdes, i, 1));
3933 }
3934 udelay(1000);
3935 } else if (AR_SREV_9280(ah)
3936 && (ah->ah_macRev == AR_SREV_REVISION_9280_10)) {
3937 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
3938 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
3939 1088
3940 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019); 1089 if (opmode == NL80211_IFTYPE_AP)
3941 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820); 1090 ahp->ah_maskReg |= AR_IMR_MIB;
3942 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
3943 1091
3944 if (ah->ah_config.pcie_clock_req) 1092 REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
3945 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc); 1093 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
3946 else
3947 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
3948 1094
3949 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 1095 if (!AR_SREV_9100(ah)) {
3950 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 1096 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
3951 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007); 1097 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1098 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1099 }
1100}
3952 1101
3953 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 1102static bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u32 us)
1103{
1104 struct ath_hal_5416 *ahp = AH5416(ah);
3954 1105
3955 udelay(1000); 1106 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1107 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1108 ahp->ah_acktimeout = (u32) -1;
1109 return false;
3956 } else { 1110 } else {
3957 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 1111 REG_RMW_FIELD(ah, AR_TIME_OUT,
3958 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 1112 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
3959 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039); 1113 ahp->ah_acktimeout = us;
3960 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824); 1114 return true;
3961 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
3962 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
3963 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3964 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3965 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
3966 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3967 } 1115 }
1116}
3968 1117
3969 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 1118static bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u32 us)
1119{
1120 struct ath_hal_5416 *ahp = AH5416(ah);
3970 1121
3971 if (ah->ah_config.pcie_waen) { 1122 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
3972 REG_WRITE(ah, AR_WA, ah->ah_config.pcie_waen); 1123 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1124 ahp->ah_ctstimeout = (u32) -1;
1125 return false;
3973 } else { 1126 } else {
3974 if (AR_SREV_9280(ah)) 1127 REG_RMW_FIELD(ah, AR_TIME_OUT,
3975 REG_WRITE(ah, AR_WA, 0x0040073f); 1128 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
3976 else 1129 ahp->ah_ctstimeout = us;
3977 REG_WRITE(ah, AR_WA, 0x0000073f); 1130 return true;
3978 } 1131 }
3979} 1132}
3980 1133
3981static void 1134static bool ath9k_hw_set_global_txtimeout(struct ath_hal *ah, u32 tu)
3982ath9k_hw_get_legacy_target_powers(struct ath_hal *ah,
3983 struct ath9k_channel *chan,
3984 struct cal_target_power_leg *powInfo,
3985 u16 numChannels,
3986 struct cal_target_power_leg *pNewPower,
3987 u16 numRates,
3988 bool isExtTarget)
3989{ 1135{
3990 u16 clo, chi; 1136 struct ath_hal_5416 *ahp = AH5416(ah);
3991 int i;
3992 int matchIndex = -1, lowIndex = -1;
3993 u16 freq;
3994 struct chan_centers centers;
3995
3996 ath9k_hw_get_channel_centers(ah, chan, &centers);
3997 freq = (isExtTarget) ? centers.ext_center : centers.ctl_center;
3998 1137
3999 if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel, 1138 if (tu > 0xFFFF) {
4000 IS_CHAN_2GHZ(chan))) { 1139 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
4001 matchIndex = 0; 1140 "bad global tx timeout %u\n", tu);
1141 ahp->ah_globaltxtimeout = (u32) -1;
1142 return false;
4002 } else { 1143 } else {
4003 for (i = 0; (i < numChannels) 1144 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
4004 && (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) { 1145 ahp->ah_globaltxtimeout = tu;
4005 if (freq == 1146 return true;
4006 ath9k_hw_fbin2freq(powInfo[i].bChannel,
4007 IS_CHAN_2GHZ(chan))) {
4008 matchIndex = i;
4009 break;
4010 } else if ((freq <
4011 ath9k_hw_fbin2freq(powInfo[i].bChannel,
4012 IS_CHAN_2GHZ(chan)))
4013 && (freq >
4014 ath9k_hw_fbin2freq(powInfo[i - 1].
4015 bChannel,
4016 IS_CHAN_2GHZ
4017 (chan)))) {
4018 lowIndex = i - 1;
4019 break;
4020 }
4021 }
4022 if ((matchIndex == -1) && (lowIndex == -1))
4023 matchIndex = i - 1;
4024 } 1147 }
1148}
4025 1149
4026 if (matchIndex != -1) { 1150static void ath9k_hw_init_user_settings(struct ath_hal *ah)
4027 *pNewPower = powInfo[matchIndex]; 1151{
4028 } else { 1152 struct ath_hal_5416 *ahp = AH5416(ah);
4029 clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel, 1153
4030 IS_CHAN_2GHZ(chan)); 1154 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ahp->ah_miscMode 0x%x\n",
4031 chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel, 1155 ahp->ah_miscMode);
4032 IS_CHAN_2GHZ(chan)); 1156
4033 1157 if (ahp->ah_miscMode != 0)
4034 for (i = 0; i < numRates; i++) { 1158 REG_WRITE(ah, AR_PCU_MISC,
4035 pNewPower->tPow2x[i] = 1159 REG_READ(ah, AR_PCU_MISC) | ahp->ah_miscMode);
4036 (u8) ath9k_hw_interpolate(freq, clo, chi, 1160 if (ahp->ah_slottime != (u32) -1)
4037 powInfo 1161 ath9k_hw_setslottime(ah, ahp->ah_slottime);
4038 [lowIndex]. 1162 if (ahp->ah_acktimeout != (u32) -1)
4039 tPow2x[i], 1163 ath9k_hw_set_ack_timeout(ah, ahp->ah_acktimeout);
4040 powInfo 1164 if (ahp->ah_ctstimeout != (u32) -1)
4041 [lowIndex + 1165 ath9k_hw_set_cts_timeout(ah, ahp->ah_ctstimeout);
4042 1].tPow2x[i]); 1166 if (ahp->ah_globaltxtimeout != (u32) -1)
4043 } 1167 ath9k_hw_set_global_txtimeout(ah, ahp->ah_globaltxtimeout);
4044 }
4045} 1168}
4046 1169
4047static void 1170const char *ath9k_hw_probe(u16 vendorid, u16 devid)
4048ath9k_hw_get_target_powers(struct ath_hal *ah,
4049 struct ath9k_channel *chan,
4050 struct cal_target_power_ht *powInfo,
4051 u16 numChannels,
4052 struct cal_target_power_ht *pNewPower,
4053 u16 numRates,
4054 bool isHt40Target)
4055{ 1171{
4056 u16 clo, chi; 1172 return vendorid == ATHEROS_VENDOR_ID ?
4057 int i; 1173 ath9k_hw_devname(devid) : NULL;
4058 int matchIndex = -1, lowIndex = -1; 1174}
4059 u16 freq;
4060 struct chan_centers centers;
4061 1175
4062 ath9k_hw_get_channel_centers(ah, chan, &centers); 1176void ath9k_hw_detach(struct ath_hal *ah)
4063 freq = isHt40Target ? centers.synth_center : centers.ctl_center; 1177{
1178 if (!AR_SREV_9100(ah))
1179 ath9k_hw_ani_detach(ah);
4064 1180
4065 if (freq <= 1181 ath9k_hw_rfdetach(ah);
4066 ath9k_hw_fbin2freq(powInfo[0].bChannel, IS_CHAN_2GHZ(chan))) { 1182 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
4067 matchIndex = 0; 1183 kfree(ah);
4068 } else { 1184}
4069 for (i = 0; (i < numChannels)
4070 && (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
4071 if (freq ==
4072 ath9k_hw_fbin2freq(powInfo[i].bChannel,
4073 IS_CHAN_2GHZ(chan))) {
4074 matchIndex = i;
4075 break;
4076 } else
4077 if ((freq <
4078 ath9k_hw_fbin2freq(powInfo[i].bChannel,
4079 IS_CHAN_2GHZ(chan)))
4080 && (freq >
4081 ath9k_hw_fbin2freq(powInfo[i - 1].
4082 bChannel,
4083 IS_CHAN_2GHZ
4084 (chan)))) {
4085 lowIndex = i - 1;
4086 break;
4087 }
4088 }
4089 if ((matchIndex == -1) && (lowIndex == -1))
4090 matchIndex = i - 1;
4091 }
4092 1185
4093 if (matchIndex != -1) { 1186struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc,
4094 *pNewPower = powInfo[matchIndex]; 1187 void __iomem *mem, int *error)
4095 } else { 1188{
4096 clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel, 1189 struct ath_hal *ah = NULL;
4097 IS_CHAN_2GHZ(chan)); 1190
4098 chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel, 1191 switch (devid) {
4099 IS_CHAN_2GHZ(chan)); 1192 case AR5416_DEVID_PCI:
4100 1193 case AR5416_DEVID_PCIE:
4101 for (i = 0; i < numRates; i++) { 1194 case AR9160_DEVID_PCI:
4102 pNewPower->tPow2x[i] = 1195 case AR9280_DEVID_PCI:
4103 (u8) ath9k_hw_interpolate(freq, clo, chi, 1196 case AR9280_DEVID_PCIE:
4104 powInfo 1197 case AR9285_DEVID_PCIE:
4105 [lowIndex]. 1198 ah = ath9k_hw_do_attach(devid, sc, mem, error);
4106 tPow2x[i], 1199 break;
4107 powInfo 1200 default:
4108 [lowIndex + 1201 *error = -ENXIO;
4109 1].tPow2x[i]); 1202 break;
4110 }
4111 } 1203 }
1204
1205 return ah;
4112} 1206}
4113 1207
4114static u16 1208/*******/
4115ath9k_hw_get_max_edge_power(u16 freq, 1209/* INI */
4116 struct cal_ctl_edges *pRdEdgesPower, 1210/*******/
4117 bool is2GHz) 1211
1212static void ath9k_hw_override_ini(struct ath_hal *ah,
1213 struct ath9k_channel *chan)
4118{ 1214{
4119 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 1215 /*
4120 int i; 1216 * Set the RX_ABORT and RX_DIS and clear if off only after
1217 * RXE is set for MAC. This prevents frames with corrupted
1218 * descriptor status.
1219 */
1220 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
4121 1221
4122 for (i = 0; (i < AR5416_NUM_BAND_EDGES) 1222
4123 && (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED); i++) { 1223 if (!AR_SREV_5416_V20_OR_LATER(ah) ||
4124 if (freq == ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel, 1224 AR_SREV_9280_10_OR_LATER(ah))
4125 is2GHz)) { 1225 return;
4126 twiceMaxEdgePower = pRdEdgesPower[i].tPower; 1226
4127 break; 1227 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
4128 } else if ((i > 0) 1228}
4129 && (freq < 1229
4130 ath9k_hw_fbin2freq(pRdEdgesPower[i]. 1230static u32 ath9k_hw_def_ini_fixup(struct ath_hal *ah,
4131 bChannel, is2GHz))) { 1231 struct ar5416_eeprom_def *pEepData,
4132 if (ath9k_hw_fbin2freq 1232 u32 reg, u32 value)
4133 (pRdEdgesPower[i - 1].bChannel, is2GHz) < freq 1233{
4134 && pRdEdgesPower[i - 1].flag) { 1234 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
4135 twiceMaxEdgePower = 1235
4136 pRdEdgesPower[i - 1].tPower; 1236 switch (ah->ah_devid) {
1237 case AR9280_DEVID_PCI:
1238 if (reg == 0x7894) {
1239 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1240 "ini VAL: %x EEPROM: %x\n", value,
1241 (pBase->version & 0xff));
1242
1243 if ((pBase->version & 0xff) > 0x0a) {
1244 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1245 "PWDCLKIND: %d\n",
1246 pBase->pwdclkind);
1247 value &= ~AR_AN_TOP2_PWDCLKIND;
1248 value |= AR_AN_TOP2_PWDCLKIND &
1249 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1250 } else {
1251 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1252 "PWDCLKIND Earlier Rev\n");
4137 } 1253 }
4138 break; 1254
1255 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1256 "final ini VAL: %x\n", value);
4139 } 1257 }
1258 break;
4140 } 1259 }
4141 return twiceMaxEdgePower; 1260
1261 return value;
4142} 1262}
4143 1263
4144static bool 1264static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
4145ath9k_hw_set_power_per_rate_table(struct ath_hal *ah, 1265 struct ar5416_eeprom_def *pEepData,
4146 struct ar5416_eeprom *pEepData, 1266 u32 reg, u32 value)
4147 struct ath9k_channel *chan,
4148 int16_t *ratesArray,
4149 u16 cfgCtl,
4150 u8 AntennaReduction,
4151 u8 twiceMaxRegulatoryPower,
4152 u8 powerLimit)
4153{ 1267{
4154 u8 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 1268 struct ath_hal_5416 *ahp = AH5416(ah);
4155 static const u16 tpScaleReductionTable[5] =
4156 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
4157 1269
4158 int i; 1270 if (ahp->ah_eep_map == EEP_MAP_4KBITS)
4159 int8_t twiceLargestAntenna; 1271 return value;
4160 struct cal_ctl_data *rep; 1272 else
4161 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = { 1273 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
4162 0, { 0, 0, 0, 0} 1274}
4163 }; 1275
4164 struct cal_target_power_leg targetPowerOfdmExt = { 1276static int ath9k_hw_process_ini(struct ath_hal *ah,
4165 0, { 0, 0, 0, 0} }, targetPowerCckExt = { 1277 struct ath9k_channel *chan,
4166 0, { 0, 0, 0, 0 } 1278 enum ath9k_ht_macmode macmode)
4167 }; 1279{
4168 struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = { 1280 int i, regWrites = 0;
4169 0, {0, 0, 0, 0}
4170 };
4171 u8 scaledPower = 0, minCtlPower, maxRegAllowedPower;
4172 u16 ctlModesFor11a[] =
4173 { CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 };
4174 u16 ctlModesFor11g[] =
4175 { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
4176 CTL_2GHT40
4177 };
4178 u16 numCtlModes, *pCtlMode, ctlMode, freq;
4179 struct chan_centers centers;
4180 int tx_chainmask;
4181 u8 twiceMinEdgePower;
4182 struct ath_hal_5416 *ahp = AH5416(ah); 1281 struct ath_hal_5416 *ahp = AH5416(ah);
1282 u32 modesIndex, freqIndex;
1283 int status;
4183 1284
4184 tx_chainmask = ahp->ah_txchainmask; 1285 switch (chan->chanmode) {
1286 case CHANNEL_A:
1287 case CHANNEL_A_HT20:
1288 modesIndex = 1;
1289 freqIndex = 1;
1290 break;
1291 case CHANNEL_A_HT40PLUS:
1292 case CHANNEL_A_HT40MINUS:
1293 modesIndex = 2;
1294 freqIndex = 1;
1295 break;
1296 case CHANNEL_G:
1297 case CHANNEL_G_HT20:
1298 case CHANNEL_B:
1299 modesIndex = 4;
1300 freqIndex = 2;
1301 break;
1302 case CHANNEL_G_HT40PLUS:
1303 case CHANNEL_G_HT40MINUS:
1304 modesIndex = 3;
1305 freqIndex = 2;
1306 break;
4185 1307
4186 ath9k_hw_get_channel_centers(ah, chan, &centers); 1308 default:
1309 return -EINVAL;
1310 }
4187 1311
4188 twiceLargestAntenna = max( 1312 REG_WRITE(ah, AR_PHY(0), 0x00000007);
4189 pEepData->modalHeader
4190 [IS_CHAN_2GHZ(chan)].antennaGainCh[0],
4191 pEepData->modalHeader
4192 [IS_CHAN_2GHZ(chan)].antennaGainCh[1]);
4193 1313
4194 twiceLargestAntenna = max((u8) twiceLargestAntenna, 1314 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
4195 pEepData->modalHeader
4196 [IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
4197 1315
4198 twiceLargestAntenna = 1316 ath9k_hw_set_addac(ah, chan);
4199 (int8_t) min(AntennaReduction - twiceLargestAntenna, 0);
4200 1317
4201 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna; 1318 if (AR_SREV_5416_V22_OR_LATER(ah)) {
1319 REG_WRITE_ARRAY(&ahp->ah_iniAddac, 1, regWrites);
1320 } else {
1321 struct ar5416IniArray temp;
1322 u32 addacSize =
1323 sizeof(u32) * ahp->ah_iniAddac.ia_rows *
1324 ahp->ah_iniAddac.ia_columns;
4202 1325
4203 if (ah->ah_tpScale != ATH9K_TP_SCALE_MAX) { 1326 memcpy(ahp->ah_addac5416_21,
4204 maxRegAllowedPower -= 1327 ahp->ah_iniAddac.ia_array, addacSize);
4205 (tpScaleReductionTable[(ah->ah_tpScale)] * 2);
4206 }
4207 1328
4208 scaledPower = min(powerLimit, maxRegAllowedPower); 1329 (ahp->ah_addac5416_21)[31 * ahp->ah_iniAddac.ia_columns + 1] = 0;
4209 1330
4210 switch (ar5416_get_ntxchains(tx_chainmask)) { 1331 temp.ia_array = ahp->ah_addac5416_21;
4211 case 1: 1332 temp.ia_columns = ahp->ah_iniAddac.ia_columns;
4212 break; 1333 temp.ia_rows = ahp->ah_iniAddac.ia_rows;
4213 case 2: 1334 REG_WRITE_ARRAY(&temp, 1, regWrites);
4214 scaledPower -=
4215 pEepData->modalHeader[IS_CHAN_2GHZ(chan)].
4216 pwrDecreaseFor2Chain;
4217 break;
4218 case 3:
4219 scaledPower -=
4220 pEepData->modalHeader[IS_CHAN_2GHZ(chan)].
4221 pwrDecreaseFor3Chain;
4222 break;
4223 } 1335 }
4224 1336
4225 scaledPower = max(0, (int32_t) scaledPower); 1337 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
4226
4227 if (IS_CHAN_2GHZ(chan)) {
4228 numCtlModes =
4229 ARRAY_SIZE(ctlModesFor11g) -
4230 SUB_NUM_CTL_MODES_AT_2G_40;
4231 pCtlMode = ctlModesFor11g;
4232
4233 ath9k_hw_get_legacy_target_powers(ah, chan,
4234 pEepData->
4235 calTargetPowerCck,
4236 AR5416_NUM_2G_CCK_TARGET_POWERS,
4237 &targetPowerCck, 4,
4238 false);
4239 ath9k_hw_get_legacy_target_powers(ah, chan,
4240 pEepData->
4241 calTargetPower2G,
4242 AR5416_NUM_2G_20_TARGET_POWERS,
4243 &targetPowerOfdm, 4,
4244 false);
4245 ath9k_hw_get_target_powers(ah, chan,
4246 pEepData->calTargetPower2GHT20,
4247 AR5416_NUM_2G_20_TARGET_POWERS,
4248 &targetPowerHt20, 8, false);
4249 1338
4250 if (IS_CHAN_HT40(chan)) { 1339 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
4251 numCtlModes = ARRAY_SIZE(ctlModesFor11g); 1340 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
4252 ath9k_hw_get_target_powers(ah, chan, 1341 u32 val = INI_RA(&ahp->ah_iniModes, i, modesIndex);
4253 pEepData->
4254 calTargetPower2GHT40,
4255 AR5416_NUM_2G_40_TARGET_POWERS,
4256 &targetPowerHt40, 8,
4257 true);
4258 ath9k_hw_get_legacy_target_powers(ah, chan,
4259 pEepData->
4260 calTargetPowerCck,
4261 AR5416_NUM_2G_CCK_TARGET_POWERS,
4262 &targetPowerCckExt,
4263 4, true);
4264 ath9k_hw_get_legacy_target_powers(ah, chan,
4265 pEepData->
4266 calTargetPower2G,
4267 AR5416_NUM_2G_20_TARGET_POWERS,
4268 &targetPowerOfdmExt,
4269 4, true);
4270 }
4271 } else {
4272 1342
4273 numCtlModes = 1343 REG_WRITE(ah, reg, val);
4274 ARRAY_SIZE(ctlModesFor11a) -
4275 SUB_NUM_CTL_MODES_AT_5G_40;
4276 pCtlMode = ctlModesFor11a;
4277
4278 ath9k_hw_get_legacy_target_powers(ah, chan,
4279 pEepData->
4280 calTargetPower5G,
4281 AR5416_NUM_5G_20_TARGET_POWERS,
4282 &targetPowerOfdm, 4,
4283 false);
4284 ath9k_hw_get_target_powers(ah, chan,
4285 pEepData->calTargetPower5GHT20,
4286 AR5416_NUM_5G_20_TARGET_POWERS,
4287 &targetPowerHt20, 8, false);
4288 1344
4289 if (IS_CHAN_HT40(chan)) { 1345 if (reg >= 0x7800 && reg < 0x78a0
4290 numCtlModes = ARRAY_SIZE(ctlModesFor11a); 1346 && ah->ah_config.analog_shiftreg) {
4291 ath9k_hw_get_target_powers(ah, chan, 1347 udelay(100);
4292 pEepData->
4293 calTargetPower5GHT40,
4294 AR5416_NUM_5G_40_TARGET_POWERS,
4295 &targetPowerHt40, 8,
4296 true);
4297 ath9k_hw_get_legacy_target_powers(ah, chan,
4298 pEepData->
4299 calTargetPower5G,
4300 AR5416_NUM_5G_20_TARGET_POWERS,
4301 &targetPowerOfdmExt,
4302 4, true);
4303 } 1348 }
1349
1350 DO_DELAY(regWrites);
4304 } 1351 }
4305 1352
4306 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) { 1353 if (AR_SREV_9280(ah))
4307 bool isHt40CtlMode = 1354 REG_WRITE_ARRAY(&ahp->ah_iniModesRxGain, modesIndex, regWrites);
4308 (pCtlMode[ctlMode] == CTL_5GHT40)
4309 || (pCtlMode[ctlMode] == CTL_2GHT40);
4310 if (isHt40CtlMode)
4311 freq = centers.synth_center;
4312 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
4313 freq = centers.ext_center;
4314 else
4315 freq = centers.ctl_center;
4316 1355
4317 if (ar5416_get_eep_ver(ahp) == 14 1356 if (AR_SREV_9280(ah))
4318 && ar5416_get_eep_rev(ahp) <= 2) 1357 REG_WRITE_ARRAY(&ahp->ah_iniModesTxGain, modesIndex, regWrites);
4319 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
4320 1358
4321 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, 1359 for (i = 0; i < ahp->ah_iniCommon.ia_rows; i++) {
4322 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, " 1360 u32 reg = INI_RA(&ahp->ah_iniCommon, i, 0);
4323 "EXT_ADDITIVE %d\n", 1361 u32 val = INI_RA(&ahp->ah_iniCommon, i, 1);
4324 ctlMode, numCtlModes, isHt40CtlMode,
4325 (pCtlMode[ctlMode] & EXT_ADDITIVE));
4326 1362
4327 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; 1363 REG_WRITE(ah, reg, val);
4328 i++) { 1364
4329 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, 1365 if (reg >= 0x7800 && reg < 0x78a0
4330 " LOOP-Ctlidx %d: cfgCtl 0x%2.2x " 1366 && ah->ah_config.analog_shiftreg) {
4331 "pCtlMode 0x%2.2x ctlIndex 0x%2.2x " 1367 udelay(100);
4332 "chan %d\n",
4333 i, cfgCtl, pCtlMode[ctlMode],
4334 pEepData->ctlIndex[i], chan->channel);
4335
4336 if ((((cfgCtl & ~CTL_MODE_M) |
4337 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4338 pEepData->ctlIndex[i])
4339 ||
4340 (((cfgCtl & ~CTL_MODE_M) |
4341 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4342 ((pEepData->
4343 ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) {
4344 rep = &(pEepData->ctlData[i]);
4345
4346 twiceMinEdgePower =
4347 ath9k_hw_get_max_edge_power(freq,
4348 rep->
4349 ctlEdges
4350 [ar5416_get_ntxchains
4351 (tx_chainmask)
4352 - 1],
4353 IS_CHAN_2GHZ
4354 (chan));
4355
4356 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
4357 " MATCH-EE_IDX %d: ch %d is2 %d "
4358 "2xMinEdge %d chainmask %d chains %d\n",
4359 i, freq, IS_CHAN_2GHZ(chan),
4360 twiceMinEdgePower, tx_chainmask,
4361 ar5416_get_ntxchains
4362 (tx_chainmask));
4363 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
4364 twiceMaxEdgePower =
4365 min(twiceMaxEdgePower,
4366 twiceMinEdgePower);
4367 } else {
4368 twiceMaxEdgePower =
4369 twiceMinEdgePower;
4370 break;
4371 }
4372 }
4373 } 1368 }
4374 1369
4375 minCtlPower = min(twiceMaxEdgePower, scaledPower); 1370 DO_DELAY(regWrites);
1371 }
1372
1373 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
4376 1374
4377 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, 1375 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
4378 " SEL-Min ctlMode %d pCtlMode %d " 1376 REG_WRITE_ARRAY(&ahp->ah_iniModesAdditional, modesIndex,
4379 "2xMaxEdge %d sP %d minCtlPwr %d\n", 1377 regWrites);
4380 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
4381 scaledPower, minCtlPower);
4382
4383 switch (pCtlMode[ctlMode]) {
4384 case CTL_11B:
4385 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x);
4386 i++) {
4387 targetPowerCck.tPow2x[i] =
4388 min(targetPowerCck.tPow2x[i],
4389 minCtlPower);
4390 }
4391 break;
4392 case CTL_11A:
4393 case CTL_11G:
4394 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x);
4395 i++) {
4396 targetPowerOfdm.tPow2x[i] =
4397 min(targetPowerOfdm.tPow2x[i],
4398 minCtlPower);
4399 }
4400 break;
4401 case CTL_5GHT20:
4402 case CTL_2GHT20:
4403 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x);
4404 i++) {
4405 targetPowerHt20.tPow2x[i] =
4406 min(targetPowerHt20.tPow2x[i],
4407 minCtlPower);
4408 }
4409 break;
4410 case CTL_11B_EXT:
4411 targetPowerCckExt.tPow2x[0] =
4412 min(targetPowerCckExt.tPow2x[0], minCtlPower);
4413 break;
4414 case CTL_11A_EXT:
4415 case CTL_11G_EXT:
4416 targetPowerOfdmExt.tPow2x[0] =
4417 min(targetPowerOfdmExt.tPow2x[0], minCtlPower);
4418 break;
4419 case CTL_5GHT40:
4420 case CTL_2GHT40:
4421 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x);
4422 i++) {
4423 targetPowerHt40.tPow2x[i] =
4424 min(targetPowerHt40.tPow2x[i],
4425 minCtlPower);
4426 }
4427 break;
4428 default:
4429 break;
4430 }
4431 } 1378 }
4432 1379
4433 ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] = 1380 ath9k_hw_override_ini(ah, chan);
4434 ratesArray[rate18mb] = ratesArray[rate24mb] = 1381 ath9k_hw_set_regs(ah, chan, macmode);
4435 targetPowerOfdm.tPow2x[0]; 1382 ath9k_hw_init_chain_masks(ah);
4436 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1]; 1383
4437 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2]; 1384 status = ath9k_hw_set_txpower(ah, chan,
4438 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3]; 1385 ath9k_regd_get_ctl(ah, chan),
4439 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0]; 1386 ath9k_regd_get_antenna_allowed(ah,
4440 1387 chan),
4441 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) 1388 chan->maxRegTxPower * 2,
4442 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i]; 1389 min((u32) MAX_RATE_POWER,
4443 1390 (u32) ah->ah_powerLimit));
4444 if (IS_CHAN_2GHZ(chan)) { 1391 if (status != 0) {
4445 ratesArray[rate1l] = targetPowerCck.tPow2x[0]; 1392 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
4446 ratesArray[rate2s] = ratesArray[rate2l] = 1393 "error init'ing transmit power\n");
4447 targetPowerCck.tPow2x[1]; 1394 return -EIO;
4448 ratesArray[rate5_5s] = ratesArray[rate5_5l] =
4449 targetPowerCck.tPow2x[2];
4450 ;
4451 ratesArray[rate11s] = ratesArray[rate11l] =
4452 targetPowerCck.tPow2x[3];
4453 ;
4454 } 1395 }
4455 if (IS_CHAN_HT40(chan)) { 1396
4456 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) { 1397 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
4457 ratesArray[rateHt40_0 + i] = 1398 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
4458 targetPowerHt40.tPow2x[i]; 1399 "ar5416SetRfRegs failed\n");
4459 } 1400 return -EIO;
4460 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
4461 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
4462 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
4463 if (IS_CHAN_2GHZ(chan)) {
4464 ratesArray[rateExtCck] =
4465 targetPowerCckExt.tPow2x[0];
4466 }
4467 } 1401 }
4468 return true; 1402
1403 return 0;
4469} 1404}
4470 1405
4471static int 1406/****************************************/
4472ath9k_hw_set_txpower(struct ath_hal *ah, 1407/* Reset and Channel Switching Routines */
4473 struct ar5416_eeprom *pEepData, 1408/****************************************/
4474 struct ath9k_channel *chan, 1409
4475 u16 cfgCtl, 1410static void ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan)
4476 u8 twiceAntennaReduction,
4477 u8 twiceMaxRegulatoryPower,
4478 u8 powerLimit)
4479{ 1411{
4480 struct modal_eep_header *pModal = 1412 u32 rfMode = 0;
4481 &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]);
4482 int16_t ratesArray[Ar5416RateSize];
4483 int16_t txPowerIndexOffset = 0;
4484 u8 ht40PowerIncForPdadc = 2;
4485 int i;
4486 1413
4487 memset(ratesArray, 0, sizeof(ratesArray)); 1414 if (chan == NULL)
1415 return;
4488 1416
4489 if ((pEepData->baseEepHeader. 1417 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
4490 version & AR5416_EEP_VER_MINOR_MASK) >= 1418 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
4491 AR5416_EEP_MINOR_VER_2) {
4492 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
4493 }
4494 1419
4495 if (!ath9k_hw_set_power_per_rate_table(ah, pEepData, chan, 1420 if (!AR_SREV_9280_10_OR_LATER(ah))
4496 &ratesArray[0], cfgCtl, 1421 rfMode |= (IS_CHAN_5GHZ(chan)) ?
4497 twiceAntennaReduction, 1422 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
4498 twiceMaxRegulatoryPower,
4499 powerLimit)) {
4500 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
4501 "ath9k_hw_set_txpower: unable to set "
4502 "tx power per rate table\n");
4503 return -EIO;
4504 }
4505 1423
4506 if (!ath9k_hw_set_power_cal_table 1424 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
4507 (ah, pEepData, chan, &txPowerIndexOffset)) { 1425 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
4508 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
4509 "ath9k_hw_set_txpower: unable to set power table\n");
4510 return -EIO;
4511 }
4512 1426
4513 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) { 1427 REG_WRITE(ah, AR_PHY_MODE, rfMode);
4514 ratesArray[i] = 1428}
4515 (int16_t) (txPowerIndexOffset + ratesArray[i]);
4516 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
4517 ratesArray[i] = AR5416_MAX_RATE_POWER;
4518 }
4519 1429
4520 if (AR_SREV_9280_10_OR_LATER(ah)) { 1430static void ath9k_hw_mark_phy_inactive(struct ath_hal *ah)
4521 for (i = 0; i < Ar5416RateSize; i++) 1431{
4522 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2; 1432 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
4523 } 1433}
4524 1434
4525 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, 1435static inline void ath9k_hw_set_dma(struct ath_hal *ah)
4526 ATH9K_POW_SM(ratesArray[rate18mb], 24) 1436{
4527 | ATH9K_POW_SM(ratesArray[rate12mb], 16) 1437 u32 regval;
4528 | ATH9K_POW_SM(ratesArray[rate9mb], 8)
4529 | ATH9K_POW_SM(ratesArray[rate6mb], 0)
4530 );
4531 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
4532 ATH9K_POW_SM(ratesArray[rate54mb], 24)
4533 | ATH9K_POW_SM(ratesArray[rate48mb], 16)
4534 | ATH9K_POW_SM(ratesArray[rate36mb], 8)
4535 | ATH9K_POW_SM(ratesArray[rate24mb], 0)
4536 );
4537
4538 if (IS_CHAN_2GHZ(chan)) {
4539 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
4540 ATH9K_POW_SM(ratesArray[rate2s], 24)
4541 | ATH9K_POW_SM(ratesArray[rate2l], 16)
4542 | ATH9K_POW_SM(ratesArray[rateXr], 8)
4543 | ATH9K_POW_SM(ratesArray[rate1l], 0)
4544 );
4545 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
4546 ATH9K_POW_SM(ratesArray[rate11s], 24)
4547 | ATH9K_POW_SM(ratesArray[rate11l], 16)
4548 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
4549 | ATH9K_POW_SM(ratesArray[rate5_5l], 0)
4550 );
4551 }
4552 1438
4553 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, 1439 regval = REG_READ(ah, AR_AHB_MODE);
4554 ATH9K_POW_SM(ratesArray[rateHt20_3], 24) 1440 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
4555 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
4556 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
4557 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0)
4558 );
4559 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
4560 ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
4561 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
4562 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
4563 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0)
4564 );
4565 1441
4566 if (IS_CHAN_HT40(chan)) { 1442 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
4567 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, 1443 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
4568 ATH9K_POW_SM(ratesArray[rateHt40_3] +
4569 ht40PowerIncForPdadc, 24)
4570 | ATH9K_POW_SM(ratesArray[rateHt40_2] +
4571 ht40PowerIncForPdadc, 16)
4572 | ATH9K_POW_SM(ratesArray[rateHt40_1] +
4573 ht40PowerIncForPdadc, 8)
4574 | ATH9K_POW_SM(ratesArray[rateHt40_0] +
4575 ht40PowerIncForPdadc, 0)
4576 );
4577 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
4578 ATH9K_POW_SM(ratesArray[rateHt40_7] +
4579 ht40PowerIncForPdadc, 24)
4580 | ATH9K_POW_SM(ratesArray[rateHt40_6] +
4581 ht40PowerIncForPdadc, 16)
4582 | ATH9K_POW_SM(ratesArray[rateHt40_5] +
4583 ht40PowerIncForPdadc, 8)
4584 | ATH9K_POW_SM(ratesArray[rateHt40_4] +
4585 ht40PowerIncForPdadc, 0)
4586 );
4587
4588 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
4589 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
4590 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
4591 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
4592 | ATH9K_POW_SM(ratesArray[rateDupCck], 0)
4593 );
4594 }
4595 1444
4596 REG_WRITE(ah, AR_PHY_POWER_TX_SUB, 1445 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->ah_txTrigLevel);
4597 ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6)
4598 | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0)
4599 );
4600 1446
4601 i = rate6mb; 1447 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
4602 if (IS_CHAN_HT40(chan)) 1448 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
4603 i = rateHt40_0;
4604 else if (IS_CHAN_HT20(chan))
4605 i = rateHt20_0;
4606 1449
4607 if (AR_SREV_9280_10_OR_LATER(ah)) 1450 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
4608 ah->ah_maxPowerLevel =
4609 ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2;
4610 else
4611 ah->ah_maxPowerLevel = ratesArray[i];
4612 1451
4613 return 0; 1452 if (AR_SREV_9285(ah)) {
1453 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1454 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1455 } else {
1456 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1457 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1458 }
1459}
1460
1461static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode)
1462{
1463 u32 val;
1464
1465 val = REG_READ(ah, AR_STA_ID1);
1466 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1467 switch (opmode) {
1468 case NL80211_IFTYPE_AP:
1469 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1470 | AR_STA_ID1_KSRCH_MODE);
1471 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1472 break;
1473 case NL80211_IFTYPE_ADHOC:
1474 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1475 | AR_STA_ID1_KSRCH_MODE);
1476 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1477 break;
1478 case NL80211_IFTYPE_STATION:
1479 case NL80211_IFTYPE_MONITOR:
1480 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1481 break;
1482 }
4614} 1483}
4615 1484
4616static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah, 1485static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah,
@@ -4632,9 +1501,8 @@ static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah,
4632 *coef_exponent = coef_exp - 16; 1501 *coef_exponent = coef_exp - 16;
4633} 1502}
4634 1503
4635static void 1504static void ath9k_hw_set_delta_slope(struct ath_hal *ah,
4636ath9k_hw_set_delta_slope(struct ath_hal *ah, 1505 struct ath9k_channel *chan)
4637 struct ath9k_channel *chan)
4638{ 1506{
4639 u32 coef_scaled, ds_coef_exp, ds_coef_man; 1507 u32 coef_scaled, ds_coef_exp, ds_coef_man;
4640 u32 clockMhzScaled = 0x64000000; 1508 u32 clockMhzScaled = 0x64000000;
@@ -4667,8 +1535,243 @@ ath9k_hw_set_delta_slope(struct ath_hal *ah,
4667 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp); 1535 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
4668} 1536}
4669 1537
4670static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, 1538static bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
4671 struct ath9k_channel *chan) 1539{
1540 u32 rst_flags;
1541 u32 tmpReg;
1542
1543 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1544 AR_RTC_FORCE_WAKE_ON_INT);
1545
1546 if (AR_SREV_9100(ah)) {
1547 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1548 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1549 } else {
1550 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1551 if (tmpReg &
1552 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1553 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1554 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1555 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1556 } else {
1557 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1558 }
1559
1560 rst_flags = AR_RTC_RC_MAC_WARM;
1561 if (type == ATH9K_RESET_COLD)
1562 rst_flags |= AR_RTC_RC_MAC_COLD;
1563 }
1564
1565 REG_WRITE(ah, (u16) (AR_RTC_RC), rst_flags);
1566 udelay(50);
1567
1568 REG_WRITE(ah, (u16) (AR_RTC_RC), 0);
1569 if (!ath9k_hw_wait(ah, (u16) (AR_RTC_RC), AR_RTC_RC_M, 0)) {
1570 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1571 "RTC stuck in MAC reset\n");
1572 return false;
1573 }
1574
1575 if (!AR_SREV_9100(ah))
1576 REG_WRITE(ah, AR_RC, 0);
1577
1578 ath9k_hw_init_pll(ah, NULL);
1579
1580 if (AR_SREV_9100(ah))
1581 udelay(50);
1582
1583 return true;
1584}
1585
1586static bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
1587{
1588 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1589 AR_RTC_FORCE_WAKE_ON_INT);
1590
1591 REG_WRITE(ah, (u16) (AR_RTC_RESET), 0);
1592 REG_WRITE(ah, (u16) (AR_RTC_RESET), 1);
1593
1594 if (!ath9k_hw_wait(ah,
1595 AR_RTC_STATUS,
1596 AR_RTC_STATUS_M,
1597 AR_RTC_STATUS_ON)) {
1598 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
1599 return false;
1600 }
1601
1602 ath9k_hw_read_revisions(ah);
1603
1604 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1605}
1606
1607static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type)
1608{
1609 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1610 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1611
1612 switch (type) {
1613 case ATH9K_RESET_POWER_ON:
1614 return ath9k_hw_set_reset_power_on(ah);
1615 break;
1616 case ATH9K_RESET_WARM:
1617 case ATH9K_RESET_COLD:
1618 return ath9k_hw_set_reset(ah, type);
1619 break;
1620 default:
1621 return false;
1622 }
1623}
1624
1625static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
1626 enum ath9k_ht_macmode macmode)
1627{
1628 u32 phymode;
1629 u32 enableDacFifo = 0;
1630 struct ath_hal_5416 *ahp = AH5416(ah);
1631
1632 if (AR_SREV_9285_10_OR_LATER(ah))
1633 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1634 AR_PHY_FC_ENABLE_DAC_FIFO);
1635
1636 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1637 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1638
1639 if (IS_CHAN_HT40(chan)) {
1640 phymode |= AR_PHY_FC_DYN2040_EN;
1641
1642 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1643 (chan->chanmode == CHANNEL_G_HT40PLUS))
1644 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1645
1646 if (ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1647 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1648 }
1649 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1650
1651 ath9k_hw_set11nmac2040(ah, macmode);
1652
1653 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1654 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1655}
1656
1657static bool ath9k_hw_chip_reset(struct ath_hal *ah,
1658 struct ath9k_channel *chan)
1659{
1660 struct ath_hal_5416 *ahp = AH5416(ah);
1661
1662 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1663 return false;
1664
1665 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1666 return false;
1667
1668 ahp->ah_chipFullSleep = false;
1669
1670 ath9k_hw_init_pll(ah, chan);
1671
1672 ath9k_hw_set_rfmode(ah, chan);
1673
1674 return true;
1675}
1676
1677static struct ath9k_channel *ath9k_hw_check_chan(struct ath_hal *ah,
1678 struct ath9k_channel *chan)
1679{
1680 if (!(IS_CHAN_2GHZ(chan) ^ IS_CHAN_5GHZ(chan))) {
1681 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1682 "invalid channel %u/0x%x; not marked as "
1683 "2GHz or 5GHz\n", chan->channel, chan->channelFlags);
1684 return NULL;
1685 }
1686
1687 if (!IS_CHAN_OFDM(chan) &&
1688 !IS_CHAN_B(chan) &&
1689 !IS_CHAN_HT20(chan) &&
1690 !IS_CHAN_HT40(chan)) {
1691 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1692 "invalid channel %u/0x%x; not marked as "
1693 "OFDM or CCK or HT20 or HT40PLUS or HT40MINUS\n",
1694 chan->channel, chan->channelFlags);
1695 return NULL;
1696 }
1697
1698 return ath9k_regd_check_channel(ah, chan);
1699}
1700
1701static bool ath9k_hw_channel_change(struct ath_hal *ah,
1702 struct ath9k_channel *chan,
1703 enum ath9k_ht_macmode macmode)
1704{
1705 u32 synthDelay, qnum;
1706
1707 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1708 if (ath9k_hw_numtxpending(ah, qnum)) {
1709 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1710 "Transmit frames pending on queue %d\n", qnum);
1711 return false;
1712 }
1713 }
1714
1715 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1716 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1717 AR_PHY_RFBUS_GRANT_EN)) {
1718 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1719 "Could not kill baseband RX\n");
1720 return false;
1721 }
1722
1723 ath9k_hw_set_regs(ah, chan, macmode);
1724
1725 if (AR_SREV_9280_10_OR_LATER(ah)) {
1726 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
1727 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1728 "failed to set channel\n");
1729 return false;
1730 }
1731 } else {
1732 if (!(ath9k_hw_set_channel(ah, chan))) {
1733 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1734 "failed to set channel\n");
1735 return false;
1736 }
1737 }
1738
1739 if (ath9k_hw_set_txpower(ah, chan,
1740 ath9k_regd_get_ctl(ah, chan),
1741 ath9k_regd_get_antenna_allowed(ah, chan),
1742 chan->maxRegTxPower * 2,
1743 min((u32) MAX_RATE_POWER,
1744 (u32) ah->ah_powerLimit)) != 0) {
1745 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1746 "error init'ing transmit power\n");
1747 return false;
1748 }
1749
1750 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1751 if (IS_CHAN_B(chan))
1752 synthDelay = (4 * synthDelay) / 22;
1753 else
1754 synthDelay /= 10;
1755
1756 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1757
1758 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1759
1760 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1761 ath9k_hw_set_delta_slope(ah, chan);
1762
1763 if (AR_SREV_9280_10_OR_LATER(ah))
1764 ath9k_hw_9280_spur_mitigate(ah, chan);
1765 else
1766 ath9k_hw_spur_mitigate(ah, chan);
1767
1768 if (!chan->oneTimeCalsDone)
1769 chan->oneTimeCalsDone = true;
1770
1771 return true;
1772}
1773
1774static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan)
4672{ 1775{
4673 int bb_spur = AR_NO_SPUR; 1776 int bb_spur = AR_NO_SPUR;
4674 int freq; 1777 int freq;
@@ -4918,8 +2021,7 @@ static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah,
4918 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 2021 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
4919} 2022}
4920 2023
4921static void ath9k_hw_spur_mitigate(struct ath_hal *ah, 2024static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan)
4922 struct ath9k_channel *chan)
4923{ 2025{
4924 int bb_spur = AR_NO_SPUR; 2026 int bb_spur = AR_NO_SPUR;
4925 int bin, cur_bin; 2027 int bin, cur_bin;
@@ -5120,752 +2222,11 @@ static void ath9k_hw_spur_mitigate(struct ath_hal *ah,
5120 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 2222 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
5121} 2223}
5122 2224
5123static void ath9k_hw_init_chain_masks(struct ath_hal *ah) 2225bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
5124{
5125 struct ath_hal_5416 *ahp = AH5416(ah);
5126 int rx_chainmask, tx_chainmask;
5127
5128 rx_chainmask = ahp->ah_rxchainmask;
5129 tx_chainmask = ahp->ah_txchainmask;
5130
5131 switch (rx_chainmask) {
5132 case 0x5:
5133 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
5134 AR_PHY_SWAP_ALT_CHAIN);
5135 case 0x3:
5136 if (((ah)->ah_macVersion <= AR_SREV_VERSION_9160)) {
5137 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
5138 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
5139 break;
5140 }
5141 case 0x1:
5142 case 0x2:
5143 if (!AR_SREV_9280(ah))
5144 break;
5145 case 0x7:
5146 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
5147 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
5148 break;
5149 default:
5150 break;
5151 }
5152
5153 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
5154 if (tx_chainmask == 0x5) {
5155 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
5156 AR_PHY_SWAP_ALT_CHAIN);
5157 }
5158 if (AR_SREV_9100(ah))
5159 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
5160 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
5161}
5162
5163static void ath9k_hw_set_addac(struct ath_hal *ah,
5164 struct ath9k_channel *chan)
5165{
5166 struct modal_eep_header *pModal;
5167 struct ath_hal_5416 *ahp = AH5416(ah);
5168 struct ar5416_eeprom *eep = &ahp->ah_eeprom;
5169 u8 biaslevel;
5170
5171 if (ah->ah_macVersion != AR_SREV_VERSION_9160)
5172 return;
5173
5174 if (ar5416_get_eep_rev(ahp) < AR5416_EEP_MINOR_VER_7)
5175 return;
5176
5177 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
5178
5179 if (pModal->xpaBiasLvl != 0xff) {
5180 biaslevel = pModal->xpaBiasLvl;
5181 } else {
5182
5183 u16 resetFreqBin, freqBin, freqCount = 0;
5184 struct chan_centers centers;
5185
5186 ath9k_hw_get_channel_centers(ah, chan, &centers);
5187
5188 resetFreqBin =
5189 FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan));
5190 freqBin = pModal->xpaBiasLvlFreq[0] & 0xff;
5191 biaslevel = (u8) (pModal->xpaBiasLvlFreq[0] >> 14);
5192
5193 freqCount++;
5194
5195 while (freqCount < 3) {
5196 if (pModal->xpaBiasLvlFreq[freqCount] == 0x0)
5197 break;
5198
5199 freqBin = pModal->xpaBiasLvlFreq[freqCount] & 0xff;
5200 if (resetFreqBin >= freqBin) {
5201 biaslevel =
5202 (u8) (pModal->
5203 xpaBiasLvlFreq[freqCount]
5204 >> 14);
5205 } else {
5206 break;
5207 }
5208 freqCount++;
5209 }
5210 }
5211
5212 if (IS_CHAN_2GHZ(chan)) {
5213 INI_RA(&ahp->ah_iniAddac, 7, 1) =
5214 (INI_RA(&ahp->ah_iniAddac, 7, 1) & (~0x18)) | biaslevel
5215 << 3;
5216 } else {
5217 INI_RA(&ahp->ah_iniAddac, 6, 1) =
5218 (INI_RA(&ahp->ah_iniAddac, 6, 1) & (~0xc0)) | biaslevel
5219 << 6;
5220 }
5221}
5222
5223static u32 ath9k_hw_mac_usec(struct ath_hal *ah, u32 clks)
5224{
5225 if (ah->ah_curchan != NULL)
5226 return clks /
5227 CLOCK_RATE[ath9k_hw_chan2wmode(ah, ah->ah_curchan)];
5228 else
5229 return clks / CLOCK_RATE[ATH9K_MODE_11B];
5230}
5231
5232static u32 ath9k_hw_mac_to_usec(struct ath_hal *ah, u32 clks)
5233{
5234 struct ath9k_channel *chan = ah->ah_curchan;
5235
5236 if (chan && IS_CHAN_HT40(chan))
5237 return ath9k_hw_mac_usec(ah, clks) / 2;
5238 else
5239 return ath9k_hw_mac_usec(ah, clks);
5240}
5241
5242static u32 ath9k_hw_mac_clks(struct ath_hal *ah, u32 usecs)
5243{
5244 if (ah->ah_curchan != NULL)
5245 return usecs * CLOCK_RATE[ath9k_hw_chan2wmode(ah,
5246 ah->ah_curchan)];
5247 else
5248 return usecs * CLOCK_RATE[ATH9K_MODE_11B];
5249}
5250
5251static u32 ath9k_hw_mac_to_clks(struct ath_hal *ah, u32 usecs)
5252{
5253 struct ath9k_channel *chan = ah->ah_curchan;
5254
5255 if (chan && IS_CHAN_HT40(chan))
5256 return ath9k_hw_mac_clks(ah, usecs) * 2;
5257 else
5258 return ath9k_hw_mac_clks(ah, usecs);
5259}
5260
5261static bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u32 us)
5262{
5263 struct ath_hal_5416 *ahp = AH5416(ah);
5264
5265 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
5266 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad ack timeout %u\n",
5267 __func__, us);
5268 ahp->ah_acktimeout = (u32) -1;
5269 return false;
5270 } else {
5271 REG_RMW_FIELD(ah, AR_TIME_OUT,
5272 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
5273 ahp->ah_acktimeout = us;
5274 return true;
5275 }
5276}
5277
5278static bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u32 us)
5279{
5280 struct ath_hal_5416 *ahp = AH5416(ah);
5281
5282 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
5283 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad cts timeout %u\n",
5284 __func__, us);
5285 ahp->ah_ctstimeout = (u32) -1;
5286 return false;
5287 } else {
5288 REG_RMW_FIELD(ah, AR_TIME_OUT,
5289 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
5290 ahp->ah_ctstimeout = us;
5291 return true;
5292 }
5293}
5294static bool ath9k_hw_set_global_txtimeout(struct ath_hal *ah,
5295 u32 tu)
5296{
5297 struct ath_hal_5416 *ahp = AH5416(ah);
5298
5299 if (tu > 0xFFFF) {
5300 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
5301 "%s: bad global tx timeout %u\n", __func__, tu);
5302 ahp->ah_globaltxtimeout = (u32) -1;
5303 return false;
5304 } else {
5305 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
5306 ahp->ah_globaltxtimeout = tu;
5307 return true;
5308 }
5309}
5310
5311bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us)
5312{
5313 struct ath_hal_5416 *ahp = AH5416(ah);
5314
5315 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
5316 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad slot time %u\n",
5317 __func__, us);
5318 ahp->ah_slottime = (u32) -1;
5319 return false;
5320 } else {
5321 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
5322 ahp->ah_slottime = us;
5323 return true;
5324 }
5325}
5326
5327static void ath9k_hw_init_user_settings(struct ath_hal *ah)
5328{
5329 struct ath_hal_5416 *ahp = AH5416(ah);
5330
5331 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "--AP %s ahp->ah_miscMode 0x%x\n",
5332 __func__, ahp->ah_miscMode);
5333 if (ahp->ah_miscMode != 0)
5334 REG_WRITE(ah, AR_PCU_MISC,
5335 REG_READ(ah, AR_PCU_MISC) | ahp->ah_miscMode);
5336 if (ahp->ah_slottime != (u32) -1)
5337 ath9k_hw_setslottime(ah, ahp->ah_slottime);
5338 if (ahp->ah_acktimeout != (u32) -1)
5339 ath9k_hw_set_ack_timeout(ah, ahp->ah_acktimeout);
5340 if (ahp->ah_ctstimeout != (u32) -1)
5341 ath9k_hw_set_cts_timeout(ah, ahp->ah_ctstimeout);
5342 if (ahp->ah_globaltxtimeout != (u32) -1)
5343 ath9k_hw_set_global_txtimeout(ah, ahp->ah_globaltxtimeout);
5344}
5345
5346static int
5347ath9k_hw_process_ini(struct ath_hal *ah,
5348 struct ath9k_channel *chan,
5349 enum ath9k_ht_macmode macmode)
5350{
5351 int i, regWrites = 0;
5352 struct ath_hal_5416 *ahp = AH5416(ah);
5353 u32 modesIndex, freqIndex;
5354 int status;
5355
5356 switch (chan->chanmode) {
5357 case CHANNEL_A:
5358 case CHANNEL_A_HT20:
5359 modesIndex = 1;
5360 freqIndex = 1;
5361 break;
5362 case CHANNEL_A_HT40PLUS:
5363 case CHANNEL_A_HT40MINUS:
5364 modesIndex = 2;
5365 freqIndex = 1;
5366 break;
5367 case CHANNEL_G:
5368 case CHANNEL_G_HT20:
5369 case CHANNEL_B:
5370 modesIndex = 4;
5371 freqIndex = 2;
5372 break;
5373 case CHANNEL_G_HT40PLUS:
5374 case CHANNEL_G_HT40MINUS:
5375 modesIndex = 3;
5376 freqIndex = 2;
5377 break;
5378
5379 default:
5380 return -EINVAL;
5381 }
5382
5383 REG_WRITE(ah, AR_PHY(0), 0x00000007);
5384
5385 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
5386
5387 ath9k_hw_set_addac(ah, chan);
5388
5389 if (AR_SREV_5416_V22_OR_LATER(ah)) {
5390 REG_WRITE_ARRAY(&ahp->ah_iniAddac, 1, regWrites);
5391 } else {
5392 struct ar5416IniArray temp;
5393 u32 addacSize =
5394 sizeof(u32) * ahp->ah_iniAddac.ia_rows *
5395 ahp->ah_iniAddac.ia_columns;
5396
5397 memcpy(ahp->ah_addac5416_21,
5398 ahp->ah_iniAddac.ia_array, addacSize);
5399
5400 (ahp->ah_addac5416_21)[31 *
5401 ahp->ah_iniAddac.ia_columns + 1] = 0;
5402
5403 temp.ia_array = ahp->ah_addac5416_21;
5404 temp.ia_columns = ahp->ah_iniAddac.ia_columns;
5405 temp.ia_rows = ahp->ah_iniAddac.ia_rows;
5406 REG_WRITE_ARRAY(&temp, 1, regWrites);
5407 }
5408 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
5409
5410 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
5411 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
5412 u32 val = INI_RA(&ahp->ah_iniModes, i, modesIndex);
5413
5414#ifdef CONFIG_SLOW_ANT_DIV
5415 if (ah->ah_devid == AR9280_DEVID_PCI)
5416 val = ath9k_hw_ini_fixup(ah, &ahp->ah_eeprom, reg,
5417 val);
5418#endif
5419
5420 REG_WRITE(ah, reg, val);
5421
5422 if (reg >= 0x7800 && reg < 0x78a0
5423 && ah->ah_config.analog_shiftreg) {
5424 udelay(100);
5425 }
5426
5427 DO_DELAY(regWrites);
5428 }
5429
5430 for (i = 0; i < ahp->ah_iniCommon.ia_rows; i++) {
5431 u32 reg = INI_RA(&ahp->ah_iniCommon, i, 0);
5432 u32 val = INI_RA(&ahp->ah_iniCommon, i, 1);
5433
5434 REG_WRITE(ah, reg, val);
5435
5436 if (reg >= 0x7800 && reg < 0x78a0
5437 && ah->ah_config.analog_shiftreg) {
5438 udelay(100);
5439 }
5440
5441 DO_DELAY(regWrites);
5442 }
5443
5444 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
5445
5446 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
5447 REG_WRITE_ARRAY(&ahp->ah_iniModesAdditional, modesIndex,
5448 regWrites);
5449 }
5450
5451 ath9k_hw_override_ini(ah, chan);
5452 ath9k_hw_set_regs(ah, chan, macmode);
5453 ath9k_hw_init_chain_masks(ah);
5454
5455 status = ath9k_hw_set_txpower(ah, &ahp->ah_eeprom, chan,
5456 ath9k_regd_get_ctl(ah, chan),
5457 ath9k_regd_get_antenna_allowed(ah,
5458 chan),
5459 chan->maxRegTxPower * 2,
5460 min((u32) MAX_RATE_POWER,
5461 (u32) ah->ah_powerLimit));
5462 if (status != 0) {
5463 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
5464 "%s: error init'ing transmit power\n", __func__);
5465 return -EIO;
5466 }
5467
5468 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
5469 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
5470 "%s: ar5416SetRfRegs failed\n", __func__);
5471 return -EIO;
5472 }
5473
5474 return 0;
5475}
5476
5477static void ath9k_hw_setup_calibration(struct ath_hal *ah,
5478 struct hal_cal_list *currCal)
5479{
5480 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
5481 AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
5482 currCal->calData->calCountMax);
5483
5484 switch (currCal->calData->calType) {
5485 case IQ_MISMATCH_CAL:
5486 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
5487 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5488 "%s: starting IQ Mismatch Calibration\n",
5489 __func__);
5490 break;
5491 case ADC_GAIN_CAL:
5492 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
5493 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5494 "%s: starting ADC Gain Calibration\n", __func__);
5495 break;
5496 case ADC_DC_CAL:
5497 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
5498 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5499 "%s: starting ADC DC Calibration\n", __func__);
5500 break;
5501 case ADC_DC_INIT_CAL:
5502 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
5503 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5504 "%s: starting Init ADC DC Calibration\n",
5505 __func__);
5506 break;
5507 }
5508
5509 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
5510 AR_PHY_TIMING_CTRL4_DO_CAL);
5511}
5512
5513static void ath9k_hw_reset_calibration(struct ath_hal *ah,
5514 struct hal_cal_list *currCal)
5515{
5516 struct ath_hal_5416 *ahp = AH5416(ah);
5517 int i;
5518
5519 ath9k_hw_setup_calibration(ah, currCal);
5520
5521 currCal->calState = CAL_RUNNING;
5522
5523 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
5524 ahp->ah_Meas0.sign[i] = 0;
5525 ahp->ah_Meas1.sign[i] = 0;
5526 ahp->ah_Meas2.sign[i] = 0;
5527 ahp->ah_Meas3.sign[i] = 0;
5528 }
5529
5530 ahp->ah_CalSamples = 0;
5531}
5532
5533static void
5534ath9k_hw_per_calibration(struct ath_hal *ah,
5535 struct ath9k_channel *ichan,
5536 u8 rxchainmask,
5537 struct hal_cal_list *currCal,
5538 bool *isCalDone)
5539{
5540 struct ath_hal_5416 *ahp = AH5416(ah);
5541
5542 *isCalDone = false;
5543
5544 if (currCal->calState == CAL_RUNNING) {
5545 if (!(REG_READ(ah,
5546 AR_PHY_TIMING_CTRL4(0)) &
5547 AR_PHY_TIMING_CTRL4_DO_CAL)) {
5548
5549 currCal->calData->calCollect(ah);
5550
5551 ahp->ah_CalSamples++;
5552
5553 if (ahp->ah_CalSamples >=
5554 currCal->calData->calNumSamples) {
5555 int i, numChains = 0;
5556 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
5557 if (rxchainmask & (1 << i))
5558 numChains++;
5559 }
5560
5561 currCal->calData->calPostProc(ah,
5562 numChains);
5563
5564 ichan->CalValid |=
5565 currCal->calData->calType;
5566 currCal->calState = CAL_DONE;
5567 *isCalDone = true;
5568 } else {
5569 ath9k_hw_setup_calibration(ah, currCal);
5570 }
5571 }
5572 } else if (!(ichan->CalValid & currCal->calData->calType)) {
5573 ath9k_hw_reset_calibration(ah, currCal);
5574 }
5575}
5576
5577static inline bool ath9k_hw_run_init_cals(struct ath_hal *ah,
5578 int init_cal_count)
5579{
5580 struct ath_hal_5416 *ahp = AH5416(ah);
5581 struct ath9k_channel ichan;
5582 bool isCalDone;
5583 struct hal_cal_list *currCal = ahp->ah_cal_list_curr;
5584 const struct hal_percal_data *calData = currCal->calData;
5585 int i;
5586
5587 if (currCal == NULL)
5588 return false;
5589
5590 ichan.CalValid = 0;
5591
5592 for (i = 0; i < init_cal_count; i++) {
5593 ath9k_hw_reset_calibration(ah, currCal);
5594
5595 if (!ath9k_hw_wait(ah, AR_PHY_TIMING_CTRL4(0),
5596 AR_PHY_TIMING_CTRL4_DO_CAL, 0)) {
5597 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5598 "%s: Cal %d failed to complete in 100ms.\n",
5599 __func__, calData->calType);
5600
5601 ahp->ah_cal_list = ahp->ah_cal_list_last =
5602 ahp->ah_cal_list_curr = NULL;
5603 return false;
5604 }
5605
5606 ath9k_hw_per_calibration(ah, &ichan, ahp->ah_rxchainmask,
5607 currCal, &isCalDone);
5608 if (!isCalDone) {
5609 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5610 "%s: Not able to run Init Cal %d.\n",
5611 __func__, calData->calType);
5612 }
5613 if (currCal->calNext) {
5614 currCal = currCal->calNext;
5615 calData = currCal->calData;
5616 }
5617 }
5618
5619 ahp->ah_cal_list = ahp->ah_cal_list_last = ahp->ah_cal_list_curr = NULL;
5620 return true;
5621}
5622
5623static bool
5624ath9k_hw_channel_change(struct ath_hal *ah,
5625 struct ath9k_channel *chan,
5626 enum ath9k_ht_macmode macmode)
5627{
5628 u32 synthDelay, qnum;
5629 struct ath_hal_5416 *ahp = AH5416(ah);
5630
5631 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
5632 if (ath9k_hw_numtxpending(ah, qnum)) {
5633 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
5634 "%s: Transmit frames pending on queue %d\n",
5635 __func__, qnum);
5636 return false;
5637 }
5638 }
5639
5640 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
5641 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
5642 AR_PHY_RFBUS_GRANT_EN)) {
5643 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
5644 "%s: Could not kill baseband RX\n", __func__);
5645 return false;
5646 }
5647
5648 ath9k_hw_set_regs(ah, chan, macmode);
5649
5650 if (AR_SREV_9280_10_OR_LATER(ah)) {
5651 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
5652 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
5653 "%s: failed to set channel\n", __func__);
5654 return false;
5655 }
5656 } else {
5657 if (!(ath9k_hw_set_channel(ah, chan))) {
5658 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
5659 "%s: failed to set channel\n", __func__);
5660 return false;
5661 }
5662 }
5663
5664 if (ath9k_hw_set_txpower(ah, &ahp->ah_eeprom, chan,
5665 ath9k_regd_get_ctl(ah, chan),
5666 ath9k_regd_get_antenna_allowed(ah, chan),
5667 chan->maxRegTxPower * 2,
5668 min((u32) MAX_RATE_POWER,
5669 (u32) ah->ah_powerLimit)) != 0) {
5670 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
5671 "%s: error init'ing transmit power\n", __func__);
5672 return false;
5673 }
5674
5675 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
5676 if (IS_CHAN_CCK(chan))
5677 synthDelay = (4 * synthDelay) / 22;
5678 else
5679 synthDelay /= 10;
5680
5681 udelay(synthDelay + BASE_ACTIVATE_DELAY);
5682
5683 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
5684
5685 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
5686 ath9k_hw_set_delta_slope(ah, chan);
5687
5688 if (AR_SREV_9280_10_OR_LATER(ah))
5689 ath9k_hw_9280_spur_mitigate(ah, chan);
5690 else
5691 ath9k_hw_spur_mitigate(ah, chan);
5692
5693 if (!chan->oneTimeCalsDone)
5694 chan->oneTimeCalsDone = true;
5695
5696 return true;
5697}
5698
5699static bool ath9k_hw_chip_reset(struct ath_hal *ah,
5700 struct ath9k_channel *chan)
5701{
5702 struct ath_hal_5416 *ahp = AH5416(ah);
5703
5704 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
5705 return false;
5706
5707 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
5708 return false;
5709
5710 ahp->ah_chipFullSleep = false;
5711
5712 ath9k_hw_init_pll(ah, chan);
5713
5714 ath9k_hw_set_rfmode(ah, chan);
5715
5716 return true;
5717}
5718
5719static inline void ath9k_hw_set_dma(struct ath_hal *ah)
5720{
5721 u32 regval;
5722
5723 regval = REG_READ(ah, AR_AHB_MODE);
5724 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
5725
5726 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
5727 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
5728
5729 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->ah_txTrigLevel);
5730
5731 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
5732 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
5733
5734 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
5735
5736 if (AR_SREV_9285(ah)) {
5737 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
5738 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
5739 } else {
5740 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
5741 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
5742 }
5743}
5744
5745bool ath9k_hw_stopdmarecv(struct ath_hal *ah)
5746{
5747 REG_WRITE(ah, AR_CR, AR_CR_RXD);
5748 if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE, 0)) {
5749 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
5750 "%s: dma failed to stop in 10ms\n"
5751 "AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n",
5752 __func__,
5753 REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW));
5754 return false;
5755 } else {
5756 return true;
5757 }
5758}
5759
5760void ath9k_hw_startpcureceive(struct ath_hal *ah)
5761{
5762 REG_CLR_BIT(ah, AR_DIAG_SW,
5763 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
5764
5765 ath9k_enable_mib_counters(ah);
5766
5767 ath9k_ani_reset(ah);
5768}
5769
5770void ath9k_hw_stoppcurecv(struct ath_hal *ah)
5771{
5772 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
5773
5774 ath9k_hw_disable_mib_counters(ah);
5775}
5776
5777static bool ath9k_hw_iscal_supported(struct ath_hal *ah,
5778 struct ath9k_channel *chan,
5779 enum hal_cal_types calType)
5780{
5781 struct ath_hal_5416 *ahp = AH5416(ah);
5782 bool retval = false;
5783
5784 switch (calType & ahp->ah_suppCals) {
5785 case IQ_MISMATCH_CAL:
5786 if (!IS_CHAN_B(chan))
5787 retval = true;
5788 break;
5789 case ADC_GAIN_CAL:
5790 case ADC_DC_CAL:
5791 if (!IS_CHAN_B(chan)
5792 && !(IS_CHAN_2GHZ(chan) && IS_CHAN_HT20(chan)))
5793 retval = true;
5794 break;
5795 }
5796
5797 return retval;
5798}
5799
5800static bool ath9k_hw_init_cal(struct ath_hal *ah,
5801 struct ath9k_channel *chan)
5802{
5803 struct ath_hal_5416 *ahp = AH5416(ah);
5804 struct ath9k_channel *ichan =
5805 ath9k_regd_check_channel(ah, chan);
5806
5807 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
5808 REG_READ(ah, AR_PHY_AGC_CONTROL) |
5809 AR_PHY_AGC_CONTROL_CAL);
5810
5811 if (!ath9k_hw_wait
5812 (ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) {
5813 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5814 "%s: offset calibration failed to complete in 1ms; "
5815 "noisy environment?\n", __func__);
5816 return false;
5817 }
5818
5819 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
5820 REG_READ(ah, AR_PHY_AGC_CONTROL) |
5821 AR_PHY_AGC_CONTROL_NF);
5822
5823 ahp->ah_cal_list = ahp->ah_cal_list_last = ahp->ah_cal_list_curr =
5824 NULL;
5825
5826 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
5827 if (ath9k_hw_iscal_supported(ah, chan, ADC_GAIN_CAL)) {
5828 INIT_CAL(&ahp->ah_adcGainCalData);
5829 INSERT_CAL(ahp, &ahp->ah_adcGainCalData);
5830 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5831 "%s: enabling ADC Gain Calibration.\n",
5832 __func__);
5833 }
5834 if (ath9k_hw_iscal_supported(ah, chan, ADC_DC_CAL)) {
5835 INIT_CAL(&ahp->ah_adcDcCalData);
5836 INSERT_CAL(ahp, &ahp->ah_adcDcCalData);
5837 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5838 "%s: enabling ADC DC Calibration.\n",
5839 __func__);
5840 }
5841 if (ath9k_hw_iscal_supported(ah, chan, IQ_MISMATCH_CAL)) {
5842 INIT_CAL(&ahp->ah_iqCalData);
5843 INSERT_CAL(ahp, &ahp->ah_iqCalData);
5844 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
5845 "%s: enabling IQ Calibration.\n",
5846 __func__);
5847 }
5848
5849 ahp->ah_cal_list_curr = ahp->ah_cal_list;
5850
5851 if (ahp->ah_cal_list_curr)
5852 ath9k_hw_reset_calibration(ah,
5853 ahp->ah_cal_list_curr);
5854 }
5855
5856 ichan->CalValid = 0;
5857
5858 return true;
5859}
5860
5861
5862bool ath9k_hw_reset(struct ath_hal *ah,
5863 struct ath9k_channel *chan,
5864 enum ath9k_ht_macmode macmode, 2226 enum ath9k_ht_macmode macmode,
5865 u8 txchainmask, u8 rxchainmask, 2227 u8 txchainmask, u8 rxchainmask,
5866 enum ath9k_ht_extprotspacing extprotspacing, 2228 enum ath9k_ht_extprotspacing extprotspacing,
5867 bool bChannelChange, 2229 bool bChannelChange, int *status)
5868 int *status)
5869{ 2230{
5870 u32 saveLedState; 2231 u32 saveLedState;
5871 struct ath_hal_5416 *ahp = AH5416(ah); 2232 struct ath_hal_5416 *ahp = AH5416(ah);
@@ -5886,8 +2247,8 @@ bool ath9k_hw_reset(struct ath_hal *ah,
5886 2247
5887 if (ath9k_hw_check_chan(ah, chan) == NULL) { 2248 if (ath9k_hw_check_chan(ah, chan) == NULL) {
5888 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, 2249 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
5889 "%s: invalid channel %u/0x%x; no mapping\n", 2250 "invalid channel %u/0x%x; no mapping\n",
5890 __func__, chan->channel, chan->channelFlags); 2251 chan->channel, chan->channelFlags);
5891 ecode = -EINVAL; 2252 ecode = -EINVAL;
5892 goto bad; 2253 goto bad;
5893 } 2254 }
@@ -5907,8 +2268,7 @@ bool ath9k_hw_reset(struct ath_hal *ah,
5907 ((chan->channelFlags & CHANNEL_ALL) == 2268 ((chan->channelFlags & CHANNEL_ALL) ==
5908 (ah->ah_curchan->channelFlags & CHANNEL_ALL)) && 2269 (ah->ah_curchan->channelFlags & CHANNEL_ALL)) &&
5909 (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) && 2270 (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
5910 !IS_CHAN_A_5MHZ_SPACED(ah-> 2271 !IS_CHAN_A_5MHZ_SPACED(ah->ah_curchan)))) {
5911 ah_curchan)))) {
5912 2272
5913 if (ath9k_hw_channel_change(ah, chan, macmode)) { 2273 if (ath9k_hw_channel_change(ah, chan, macmode)) {
5914 ath9k_hw_loadnf(ah, ah->ah_curchan); 2274 ath9k_hw_loadnf(ah, ah->ah_curchan);
@@ -5930,8 +2290,7 @@ bool ath9k_hw_reset(struct ath_hal *ah,
5930 ath9k_hw_mark_phy_inactive(ah); 2290 ath9k_hw_mark_phy_inactive(ah);
5931 2291
5932 if (!ath9k_hw_chip_reset(ah, chan)) { 2292 if (!ath9k_hw_chip_reset(ah, chan)) {
5933 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: chip reset failed\n", 2293 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "chip reset failed\n");
5934 __func__);
5935 ecode = -EINVAL; 2294 ecode = -EINVAL;
5936 goto bad; 2295 goto bad;
5937 } 2296 }
@@ -5965,7 +2324,7 @@ bool ath9k_hw_reset(struct ath_hal *ah,
5965 2324
5966 if (!ath9k_hw_eeprom_set_board_values(ah, chan)) { 2325 if (!ath9k_hw_eeprom_set_board_values(ah, chan)) {
5967 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 2326 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
5968 "%s: error setting board options\n", __func__); 2327 "error setting board options\n");
5969 ecode = -EIO; 2328 ecode = -EIO;
5970 goto bad; 2329 goto bad;
5971 } 2330 }
@@ -6016,7 +2375,7 @@ bool ath9k_hw_reset(struct ath_hal *ah,
6016 ath9k_hw_init_interrupt_masks(ah, ah->ah_opmode); 2375 ath9k_hw_init_interrupt_masks(ah, ah->ah_opmode);
6017 ath9k_hw_init_qos(ah); 2376 ath9k_hw_init_qos(ah);
6018 2377
6019#ifdef CONFIG_RFKILL 2378#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
6020 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 2379 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
6021 ath9k_enable_rfkill(ah); 2380 ath9k_enable_rfkill(ah);
6022#endif 2381#endif
@@ -6055,15 +2414,13 @@ bool ath9k_hw_reset(struct ath_hal *ah,
6055 mask = REG_READ(ah, AR_CFG); 2414 mask = REG_READ(ah, AR_CFG);
6056 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 2415 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
6057 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 2416 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
6058 "%s CFG Byte Swap Set 0x%x\n", __func__, 2417 "CFG Byte Swap Set 0x%x\n", mask);
6059 mask);
6060 } else { 2418 } else {
6061 mask = 2419 mask =
6062 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 2420 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
6063 REG_WRITE(ah, AR_CFG, mask); 2421 REG_WRITE(ah, AR_CFG, mask);
6064 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 2422 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
6065 "%s Setting CFG 0x%x\n", __func__, 2423 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
6066 REG_READ(ah, AR_CFG));
6067 } 2424 }
6068 } else { 2425 } else {
6069#ifdef __BIG_ENDIAN 2426#ifdef __BIG_ENDIAN
@@ -6078,693 +2435,402 @@ bad:
6078 return false; 2435 return false;
6079} 2436}
6080 2437
6081bool ath9k_hw_phy_disable(struct ath_hal *ah) 2438/************************/
6082{ 2439/* Key Cache Management */
6083 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM); 2440/************************/
6084}
6085
6086bool ath9k_hw_disable(struct ath_hal *ah)
6087{
6088 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
6089 return false;
6090
6091 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
6092}
6093 2441
6094bool 2442bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry)
6095ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan,
6096 u8 rxchainmask, bool longcal,
6097 bool *isCalDone)
6098{ 2443{
6099 struct ath_hal_5416 *ahp = AH5416(ah); 2444 u32 keyType;
6100 struct hal_cal_list *currCal = ahp->ah_cal_list_curr;
6101 struct ath9k_channel *ichan =
6102 ath9k_regd_check_channel(ah, chan);
6103
6104 *isCalDone = true;
6105 2445
6106 if (ichan == NULL) { 2446 if (entry >= ah->ah_caps.keycache_size) {
6107 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, 2447 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
6108 "%s: invalid channel %u/0x%x; no mapping\n", 2448 "entry %u out of range\n", entry);
6109 __func__, chan->channel, chan->channelFlags);
6110 return false; 2449 return false;
6111 } 2450 }
6112 2451
6113 if (currCal && 2452 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
6114 (currCal->calState == CAL_RUNNING ||
6115 currCal->calState == CAL_WAITING)) {
6116 ath9k_hw_per_calibration(ah, ichan, rxchainmask, currCal,
6117 isCalDone);
6118 if (*isCalDone) {
6119 ahp->ah_cal_list_curr = currCal = currCal->calNext;
6120
6121 if (currCal->calState == CAL_WAITING) {
6122 *isCalDone = false;
6123 ath9k_hw_reset_calibration(ah, currCal);
6124 }
6125 }
6126 }
6127 2453
6128 if (longcal) { 2454 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
6129 ath9k_hw_getnf(ah, ichan); 2455 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
6130 ath9k_hw_loadnf(ah, ah->ah_curchan); 2456 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
6131 ath9k_hw_start_nfcal(ah); 2457 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2458 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2459 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2460 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2461 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
6132 2462
6133 if ((ichan->channelFlags & CHANNEL_CW_INT) != 0) { 2463 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2464 u16 micentry = entry + 64;
2465
2466 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2467 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2468 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2469 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
6134 2470
6135 chan->channelFlags |= CHANNEL_CW_INT;
6136 ichan->channelFlags &= ~CHANNEL_CW_INT;
6137 }
6138 } 2471 }
6139 2472
2473 if (ah->ah_curchan == NULL)
2474 return true;
2475
6140 return true; 2476 return true;
6141} 2477}
6142 2478
6143static void ath9k_hw_iqcal_collect(struct ath_hal *ah) 2479bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac)
6144{ 2480{
6145 struct ath_hal_5416 *ahp = AH5416(ah); 2481 u32 macHi, macLo;
6146 int i;
6147 2482
6148 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 2483 if (entry >= ah->ah_caps.keycache_size) {
6149 ahp->ah_totalPowerMeasI[i] += 2484 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
6150 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); 2485 "entry %u out of range\n", entry);
6151 ahp->ah_totalPowerMeasQ[i] += 2486 return false;
6152 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
6153 ahp->ah_totalIqCorrMeas[i] +=
6154 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
6155 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6156 "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
6157 ahp->ah_CalSamples, i, ahp->ah_totalPowerMeasI[i],
6158 ahp->ah_totalPowerMeasQ[i],
6159 ahp->ah_totalIqCorrMeas[i]);
6160 } 2487 }
6161}
6162 2488
6163static void ath9k_hw_adc_gaincal_collect(struct ath_hal *ah) 2489 if (mac != NULL) {
6164{ 2490 macHi = (mac[5] << 8) | mac[4];
6165 struct ath_hal_5416 *ahp = AH5416(ah); 2491 macLo = (mac[3] << 24) |
6166 int i; 2492 (mac[2] << 16) |
6167 2493 (mac[1] << 8) |
6168 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 2494 mac[0];
6169 ahp->ah_totalAdcIOddPhase[i] += 2495 macLo >>= 1;
6170 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); 2496 macLo |= (macHi & 1) << 31;
6171 ahp->ah_totalAdcIEvenPhase[i] += 2497 macHi >>= 1;
6172 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); 2498 } else {
6173 ahp->ah_totalAdcQOddPhase[i] += 2499 macLo = macHi = 0;
6174 REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
6175 ahp->ah_totalAdcQEvenPhase[i] +=
6176 REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
6177
6178 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6179 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
6180 "oddq=0x%08x; evenq=0x%08x;\n",
6181 ahp->ah_CalSamples, i,
6182 ahp->ah_totalAdcIOddPhase[i],
6183 ahp->ah_totalAdcIEvenPhase[i],
6184 ahp->ah_totalAdcQOddPhase[i],
6185 ahp->ah_totalAdcQEvenPhase[i]);
6186 } 2500 }
6187} 2501 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
6188 2502 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
6189static void ath9k_hw_adc_dccal_collect(struct ath_hal *ah)
6190{
6191 struct ath_hal_5416 *ahp = AH5416(ah);
6192 int i;
6193 2503
6194 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 2504 return true;
6195 ahp->ah_totalAdcDcOffsetIOddPhase[i] +=
6196 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
6197 ahp->ah_totalAdcDcOffsetIEvenPhase[i] +=
6198 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
6199 ahp->ah_totalAdcDcOffsetQOddPhase[i] +=
6200 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
6201 ahp->ah_totalAdcDcOffsetQEvenPhase[i] +=
6202 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
6203
6204 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6205 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
6206 "oddq=0x%08x; evenq=0x%08x;\n",
6207 ahp->ah_CalSamples, i,
6208 ahp->ah_totalAdcDcOffsetIOddPhase[i],
6209 ahp->ah_totalAdcDcOffsetIEvenPhase[i],
6210 ahp->ah_totalAdcDcOffsetQOddPhase[i],
6211 ahp->ah_totalAdcDcOffsetQEvenPhase[i]);
6212 }
6213} 2505}
6214 2506
6215static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u8 numChains) 2507bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
2508 const struct ath9k_keyval *k,
2509 const u8 *mac, int xorKey)
6216{ 2510{
2511 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2512 u32 key0, key1, key2, key3, key4;
2513 u32 keyType;
2514 u32 xorMask = xorKey ?
2515 (ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 | ATH9K_KEY_XOR << 8
2516 | ATH9K_KEY_XOR) : 0;
6217 struct ath_hal_5416 *ahp = AH5416(ah); 2517 struct ath_hal_5416 *ahp = AH5416(ah);
6218 u32 powerMeasQ, powerMeasI, iqCorrMeas;
6219 u32 qCoffDenom, iCoffDenom;
6220 int32_t qCoff, iCoff;
6221 int iqCorrNeg, i;
6222
6223 for (i = 0; i < numChains; i++) {
6224 powerMeasI = ahp->ah_totalPowerMeasI[i];
6225 powerMeasQ = ahp->ah_totalPowerMeasQ[i];
6226 iqCorrMeas = ahp->ah_totalIqCorrMeas[i];
6227
6228 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6229 "Starting IQ Cal and Correction for Chain %d\n",
6230 i);
6231
6232 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6233 "Orignal: Chn %diq_corr_meas = 0x%08x\n",
6234 i, ahp->ah_totalIqCorrMeas[i]);
6235
6236 iqCorrNeg = 0;
6237 2518
2519 if (entry >= pCap->keycache_size) {
2520 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2521 "entry %u out of range\n", entry);
2522 return false;
2523 }
6238 2524
6239 if (iqCorrMeas > 0x80000000) { 2525 switch (k->kv_type) {
6240 iqCorrMeas = (0xffffffff - iqCorrMeas) + 1; 2526 case ATH9K_CIPHER_AES_OCB:
6241 iqCorrNeg = 1; 2527 keyType = AR_KEYTABLE_TYPE_AES;
2528 break;
2529 case ATH9K_CIPHER_AES_CCM:
2530 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2531 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2532 "AES-CCM not supported by mac rev 0x%x\n",
2533 ah->ah_macRev);
2534 return false;
6242 } 2535 }
6243 2536 keyType = AR_KEYTABLE_TYPE_CCM;
6244 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 2537 break;
6245 "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI); 2538 case ATH9K_CIPHER_TKIP:
6246 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 2539 keyType = AR_KEYTABLE_TYPE_TKIP;
6247 "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ); 2540 if (ATH9K_IS_MIC_ENABLED(ah)
6248 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n", 2541 && entry + 64 >= pCap->keycache_size) {
6249 iqCorrNeg); 2542 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
6250 2543 "entry %u inappropriate for TKIP\n", entry);
6251 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128; 2544 return false;
6252 qCoffDenom = powerMeasQ / 64;
6253
6254 if (powerMeasQ != 0) {
6255
6256 iCoff = iqCorrMeas / iCoffDenom;
6257 qCoff = powerMeasI / qCoffDenom - 64;
6258 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6259 "Chn %d iCoff = 0x%08x\n", i, iCoff);
6260 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6261 "Chn %d qCoff = 0x%08x\n", i, qCoff);
6262
6263
6264 iCoff = iCoff & 0x3f;
6265 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6266 "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
6267 if (iqCorrNeg == 0x0)
6268 iCoff = 0x40 - iCoff;
6269
6270 if (qCoff > 15)
6271 qCoff = 15;
6272 else if (qCoff <= -16)
6273 qCoff = 16;
6274
6275 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6276 "Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
6277 i, iCoff, qCoff);
6278
6279 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
6280 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
6281 iCoff);
6282 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
6283 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
6284 qCoff);
6285 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6286 "IQ Cal and Correction done for Chain %d\n",
6287 i);
6288 } 2545 }
6289 } 2546 break;
6290 2547 case ATH9K_CIPHER_WEP:
6291 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0), 2548 if (k->kv_len < LEN_WEP40) {
6292 AR_PHY_TIMING_CTRL4_IQCORR_ENABLE); 2549 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
6293} 2550 "WEP key length %u too small\n", k->kv_len);
6294 2551 return false;
6295static void
6296ath9k_hw_adc_gaincal_calibrate(struct ath_hal *ah, u8 numChains)
6297{
6298 struct ath_hal_5416 *ahp = AH5416(ah);
6299 u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset,
6300 qEvenMeasOffset;
6301 u32 qGainMismatch, iGainMismatch, val, i;
6302
6303 for (i = 0; i < numChains; i++) {
6304 iOddMeasOffset = ahp->ah_totalAdcIOddPhase[i];
6305 iEvenMeasOffset = ahp->ah_totalAdcIEvenPhase[i];
6306 qOddMeasOffset = ahp->ah_totalAdcQOddPhase[i];
6307 qEvenMeasOffset = ahp->ah_totalAdcQEvenPhase[i];
6308
6309 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6310 "Starting ADC Gain Cal for Chain %d\n", i);
6311
6312 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6313 "Chn %d pwr_meas_odd_i = 0x%08x\n", i,
6314 iOddMeasOffset);
6315 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6316 "Chn %d pwr_meas_even_i = 0x%08x\n", i,
6317 iEvenMeasOffset);
6318 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6319 "Chn %d pwr_meas_odd_q = 0x%08x\n", i,
6320 qOddMeasOffset);
6321 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6322 "Chn %d pwr_meas_even_q = 0x%08x\n", i,
6323 qEvenMeasOffset);
6324
6325 if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) {
6326 iGainMismatch =
6327 ((iEvenMeasOffset * 32) /
6328 iOddMeasOffset) & 0x3f;
6329 qGainMismatch =
6330 ((qOddMeasOffset * 32) /
6331 qEvenMeasOffset) & 0x3f;
6332
6333 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6334 "Chn %d gain_mismatch_i = 0x%08x\n", i,
6335 iGainMismatch);
6336 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6337 "Chn %d gain_mismatch_q = 0x%08x\n", i,
6338 qGainMismatch);
6339
6340 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
6341 val &= 0xfffff000;
6342 val |= (qGainMismatch) | (iGainMismatch << 6);
6343 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
6344
6345 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6346 "ADC Gain Cal done for Chain %d\n", i);
6347 } 2552 }
2553 if (k->kv_len <= LEN_WEP40)
2554 keyType = AR_KEYTABLE_TYPE_40;
2555 else if (k->kv_len <= LEN_WEP104)
2556 keyType = AR_KEYTABLE_TYPE_104;
2557 else
2558 keyType = AR_KEYTABLE_TYPE_128;
2559 break;
2560 case ATH9K_CIPHER_CLR:
2561 keyType = AR_KEYTABLE_TYPE_CLR;
2562 break;
2563 default:
2564 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2565 "cipher %u not supported\n", k->kv_type);
2566 return false;
6348 } 2567 }
6349 2568
6350 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0), 2569 key0 = get_unaligned_le32(k->kv_val + 0) ^ xorMask;
6351 REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) | 2570 key1 = (get_unaligned_le16(k->kv_val + 4) ^ xorMask) & 0xffff;
6352 AR_PHY_NEW_ADC_GAIN_CORR_ENABLE); 2571 key2 = get_unaligned_le32(k->kv_val + 6) ^ xorMask;
6353} 2572 key3 = (get_unaligned_le16(k->kv_val + 10) ^ xorMask) & 0xffff;
6354 2573 key4 = get_unaligned_le32(k->kv_val + 12) ^ xorMask;
6355static void 2574 if (k->kv_len <= LEN_WEP104)
6356ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah, u8 numChains) 2575 key4 &= 0xff;
6357{
6358 struct ath_hal_5416 *ahp = AH5416(ah);
6359 u32 iOddMeasOffset, iEvenMeasOffset, val, i;
6360 int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch;
6361 const struct hal_percal_data *calData =
6362 ahp->ah_cal_list_curr->calData;
6363 u32 numSamples =
6364 (1 << (calData->calCountMax + 5)) * calData->calNumSamples;
6365
6366 for (i = 0; i < numChains; i++) {
6367 iOddMeasOffset = ahp->ah_totalAdcDcOffsetIOddPhase[i];
6368 iEvenMeasOffset = ahp->ah_totalAdcDcOffsetIEvenPhase[i];
6369 qOddMeasOffset = ahp->ah_totalAdcDcOffsetQOddPhase[i];
6370 qEvenMeasOffset = ahp->ah_totalAdcDcOffsetQEvenPhase[i];
6371
6372 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6373 "Starting ADC DC Offset Cal for Chain %d\n", i);
6374
6375 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6376 "Chn %d pwr_meas_odd_i = %d\n", i,
6377 iOddMeasOffset);
6378 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6379 "Chn %d pwr_meas_even_i = %d\n", i,
6380 iEvenMeasOffset);
6381 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6382 "Chn %d pwr_meas_odd_q = %d\n", i,
6383 qOddMeasOffset);
6384 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6385 "Chn %d pwr_meas_even_q = %d\n", i,
6386 qEvenMeasOffset);
6387
6388 iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
6389 numSamples) & 0x1ff;
6390 qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
6391 numSamples) & 0x1ff;
6392
6393 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6394 "Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
6395 iDcMismatch);
6396 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6397 "Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
6398 qDcMismatch);
6399
6400 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
6401 val &= 0xc0000fff;
6402 val |= (qDcMismatch << 12) | (iDcMismatch << 21);
6403 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
6404
6405 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6406 "ADC DC Offset Cal done for Chain %d\n", i);
6407 }
6408
6409 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
6410 REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
6411 AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
6412}
6413
6414bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit)
6415{
6416 struct ath_hal_5416 *ahp = AH5416(ah);
6417 struct ath9k_channel *chan = ah->ah_curchan;
6418 2576
6419 ah->ah_powerLimit = min(limit, (u32) MAX_RATE_POWER); 2577 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2578 u16 micentry = entry + 64;
6420 2579
6421 if (ath9k_hw_set_txpower(ah, &ahp->ah_eeprom, chan, 2580 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
6422 ath9k_regd_get_ctl(ah, chan), 2581 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
6423 ath9k_regd_get_antenna_allowed(ah, 2582 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
6424 chan), 2583 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
6425 chan->maxRegTxPower * 2, 2584 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
6426 min((u32) MAX_RATE_POWER, 2585 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
6427 (u32) ah->ah_powerLimit)) != 0) 2586 (void) ath9k_hw_keysetmac(ah, entry, mac);
6428 return false;
6429 2587
6430 return true; 2588 if (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) {
6431} 2589 u32 mic0, mic1, mic2, mic3, mic4;
6432 2590
6433void 2591 mic0 = get_unaligned_le32(k->kv_mic + 0);
6434ath9k_hw_get_channel_centers(struct ath_hal *ah, 2592 mic2 = get_unaligned_le32(k->kv_mic + 4);
6435 struct ath9k_channel *chan, 2593 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
6436 struct chan_centers *centers) 2594 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
6437{ 2595 mic4 = get_unaligned_le32(k->kv_txmic + 4);
6438 int8_t extoff; 2596 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
6439 struct ath_hal_5416 *ahp = AH5416(ah); 2597 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2598 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2599 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2600 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2601 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2602 AR_KEYTABLE_TYPE_CLR);
6440 2603
6441 if (!IS_CHAN_HT40(chan)) { 2604 } else {
6442 centers->ctl_center = centers->ext_center = 2605 u32 mic0, mic2;
6443 centers->synth_center = chan->channel;
6444 return;
6445 }
6446 2606
6447 if ((chan->chanmode == CHANNEL_A_HT40PLUS) || 2607 mic0 = get_unaligned_le32(k->kv_mic + 0);
6448 (chan->chanmode == CHANNEL_G_HT40PLUS)) { 2608 mic2 = get_unaligned_le32(k->kv_mic + 4);
6449 centers->synth_center = 2609 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
6450 chan->channel + HT40_CHANNEL_CENTER_SHIFT; 2610 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
6451 extoff = 1; 2611 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2612 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2613 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2614 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2615 AR_KEYTABLE_TYPE_CLR);
2616 }
2617 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2618 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2619 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2620 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
6452 } else { 2621 } else {
6453 centers->synth_center = 2622 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
6454 chan->channel - HT40_CHANNEL_CENTER_SHIFT; 2623 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
6455 extoff = -1; 2624 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2625 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2626 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2627 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2628
2629 (void) ath9k_hw_keysetmac(ah, entry, mac);
6456 } 2630 }
6457 2631
6458 centers->ctl_center = centers->synth_center - (extoff * 2632 if (ah->ah_curchan == NULL)
6459 HT40_CHANNEL_CENTER_SHIFT); 2633 return true;
6460 centers->ext_center = centers->synth_center + (extoff *
6461 ((ahp->
6462 ah_extprotspacing
6463 ==
6464 ATH9K_HT_EXTPROTSPACING_20)
6465 ?
6466 HT40_CHANNEL_CENTER_SHIFT
6467 : 15));
6468 2634
2635 return true;
6469} 2636}
6470 2637
6471void 2638bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry)
6472ath9k_hw_reset_calvalid(struct ath_hal *ah, struct ath9k_channel *chan,
6473 bool *isCalDone)
6474{ 2639{
6475 struct ath_hal_5416 *ahp = AH5416(ah); 2640 if (entry < ah->ah_caps.keycache_size) {
6476 struct ath9k_channel *ichan = 2641 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
6477 ath9k_regd_check_channel(ah, chan); 2642 if (val & AR_KEYTABLE_VALID)
6478 struct hal_cal_list *currCal = ahp->ah_cal_list_curr; 2643 return true;
6479
6480 *isCalDone = true;
6481
6482 if (!AR_SREV_9100(ah) && !AR_SREV_9160_10_OR_LATER(ah))
6483 return;
6484
6485 if (currCal == NULL)
6486 return;
6487
6488 if (ichan == NULL) {
6489 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6490 "%s: invalid channel %u/0x%x; no mapping\n",
6491 __func__, chan->channel, chan->channelFlags);
6492 return;
6493 }
6494
6495
6496 if (currCal->calState != CAL_DONE) {
6497 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6498 "%s: Calibration state incorrect, %d\n",
6499 __func__, currCal->calState);
6500 return;
6501 } 2644 }
6502 2645 return false;
6503
6504 if (!ath9k_hw_iscal_supported(ah, chan, currCal->calData->calType))
6505 return;
6506
6507 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
6508 "%s: Resetting Cal %d state for channel %u/0x%x\n",
6509 __func__, currCal->calData->calType, chan->channel,
6510 chan->channelFlags);
6511
6512 ichan->CalValid &= ~currCal->calData->calType;
6513 currCal->calState = CAL_WAITING;
6514
6515 *isCalDone = false;
6516} 2646}
6517 2647
6518void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac) 2648/******************************/
2649/* Power Management (Chipset) */
2650/******************************/
2651
2652static void ath9k_set_power_sleep(struct ath_hal *ah, int setChip)
6519{ 2653{
6520 struct ath_hal_5416 *ahp = AH5416(ah); 2654 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2655 if (setChip) {
2656 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2657 AR_RTC_FORCE_WAKE_EN);
2658 if (!AR_SREV_9100(ah))
2659 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
6521 2660
6522 memcpy(mac, ahp->ah_macaddr, ETH_ALEN); 2661 REG_CLR_BIT(ah, (u16) (AR_RTC_RESET),
2662 AR_RTC_RESET_EN);
2663 }
6523} 2664}
6524 2665
6525bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac) 2666static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip)
6526{ 2667{
6527 struct ath_hal_5416 *ahp = AH5416(ah); 2668 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2669 if (setChip) {
2670 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
6528 2671
6529 memcpy(ahp->ah_macaddr, mac, ETH_ALEN); 2672 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
6530 return true; 2673 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2674 AR_RTC_FORCE_WAKE_ON_INT);
2675 } else {
2676 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2677 AR_RTC_FORCE_WAKE_EN);
2678 }
2679 }
6531} 2680}
6532 2681
6533void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask) 2682static bool ath9k_hw_set_power_awake(struct ath_hal *ah,
2683 int setChip)
6534{ 2684{
6535 struct ath_hal_5416 *ahp = AH5416(ah); 2685 u32 val;
2686 int i;
6536 2687
6537 memcpy(mask, ahp->ah_bssidmask, ETH_ALEN); 2688 if (setChip) {
6538} 2689 if ((REG_READ(ah, AR_RTC_STATUS) &
2690 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2691 if (ath9k_hw_set_reset_reg(ah,
2692 ATH9K_RESET_POWER_ON) != true) {
2693 return false;
2694 }
2695 }
2696 if (AR_SREV_9100(ah))
2697 REG_SET_BIT(ah, AR_RTC_RESET,
2698 AR_RTC_RESET_EN);
6539 2699
6540bool 2700 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
6541ath9k_hw_setbssidmask(struct ath_hal *ah, const u8 *mask) 2701 AR_RTC_FORCE_WAKE_EN);
6542{ 2702 udelay(50);
6543 struct ath_hal_5416 *ahp = AH5416(ah);
6544 2703
6545 memcpy(ahp->ah_bssidmask, mask, ETH_ALEN); 2704 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2705 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2706 if (val == AR_RTC_STATUS_ON)
2707 break;
2708 udelay(50);
2709 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2710 AR_RTC_FORCE_WAKE_EN);
2711 }
2712 if (i == 0) {
2713 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2714 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2715 return false;
2716 }
2717 }
6546 2718
6547 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask)); 2719 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
6548 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
6549 2720
6550 return true; 2721 return true;
6551} 2722}
6552 2723
6553void 2724bool ath9k_hw_setpower(struct ath_hal *ah,
6554ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid, 2725 enum ath9k_power_mode mode)
6555 u16 assocId)
6556{ 2726{
6557 struct ath_hal_5416 *ahp = AH5416(ah); 2727 struct ath_hal_5416 *ahp = AH5416(ah);
2728 static const char *modes[] = {
2729 "AWAKE",
2730 "FULL-SLEEP",
2731 "NETWORK SLEEP",
2732 "UNDEFINED"
2733 };
2734 int status = true, setChip = true;
6558 2735
6559 memcpy(ahp->ah_bssid, bssid, ETH_ALEN); 2736 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s -> %s (%s)\n",
6560 ahp->ah_assocId = assocId; 2737 modes[ahp->ah_powerMode], modes[mode],
6561 2738 setChip ? "set chip " : "");
6562 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
6563 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
6564 ((assocId & 0x3fff) << AR_BSS_ID1_AID_S));
6565}
6566
6567u64 ath9k_hw_gettsf64(struct ath_hal *ah)
6568{
6569 u64 tsf;
6570
6571 tsf = REG_READ(ah, AR_TSF_U32);
6572 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
6573 return tsf;
6574}
6575
6576void ath9k_hw_reset_tsf(struct ath_hal *ah)
6577{
6578 int count;
6579 2739
6580 count = 0; 2740 switch (mode) {
6581 while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) { 2741 case ATH9K_PM_AWAKE:
6582 count++; 2742 status = ath9k_hw_set_power_awake(ah, setChip);
6583 if (count > 10) { 2743 break;
6584 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 2744 case ATH9K_PM_FULL_SLEEP:
6585 "%s: AR_SLP32_TSF_WRITE_STATUS limit exceeded\n", 2745 ath9k_set_power_sleep(ah, setChip);
6586 __func__); 2746 ahp->ah_chipFullSleep = true;
6587 break; 2747 break;
6588 } 2748 case ATH9K_PM_NETWORK_SLEEP:
6589 udelay(10); 2749 ath9k_set_power_network_sleep(ah, setChip);
2750 break;
2751 default:
2752 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2753 "Unknown power mode %u\n", mode);
2754 return false;
6590 } 2755 }
6591 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 2756 ahp->ah_powerMode = mode;
6592}
6593
6594u32 ath9k_hw_getdefantenna(struct ath_hal *ah)
6595{
6596 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
6597}
6598 2757
6599void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna) 2758 return status;
6600{
6601 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
6602} 2759}
6603 2760
6604bool 2761void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
6605ath9k_hw_setantennaswitch(struct ath_hal *ah,
6606 enum ath9k_ant_setting settings,
6607 struct ath9k_channel *chan,
6608 u8 *tx_chainmask,
6609 u8 *rx_chainmask,
6610 u8 *antenna_cfgd)
6611{ 2762{
6612 struct ath_hal_5416 *ahp = AH5416(ah); 2763 struct ath_hal_5416 *ahp = AH5416(ah);
6613 static u8 tx_chainmask_cfg, rx_chainmask_cfg; 2764 u8 i;
6614 2765
6615 if (AR_SREV_9280(ah)) { 2766 if (ah->ah_isPciExpress != true)
6616 if (!tx_chainmask_cfg) { 2767 return;
6617 2768
6618 tx_chainmask_cfg = *tx_chainmask; 2769 if (ah->ah_config.pcie_powersave_enable == 2)
6619 rx_chainmask_cfg = *rx_chainmask; 2770 return;
6620 }
6621 2771
6622 switch (settings) { 2772 if (restore)
6623 case ATH9K_ANT_FIXED_A: 2773 return;
6624 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK; 2774
6625 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK; 2775 if (AR_SREV_9280_20_OR_LATER(ah)) {
6626 *antenna_cfgd = true; 2776 for (i = 0; i < ahp->ah_iniPcieSerdes.ia_rows; i++) {
6627 break; 2777 REG_WRITE(ah, INI_RA(&ahp->ah_iniPcieSerdes, i, 0),
6628 case ATH9K_ANT_FIXED_B: 2778 INI_RA(&ahp->ah_iniPcieSerdes, i, 1));
6629 if (ah->ah_caps.tx_chainmask >
6630 ATH9K_ANTENNA1_CHAINMASK) {
6631 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
6632 }
6633 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
6634 *antenna_cfgd = true;
6635 break;
6636 case ATH9K_ANT_VARIABLE:
6637 *tx_chainmask = tx_chainmask_cfg;
6638 *rx_chainmask = rx_chainmask_cfg;
6639 *antenna_cfgd = true;
6640 break;
6641 default:
6642 break;
6643 } 2779 }
6644 } else { 2780 udelay(1000);
6645 ahp->ah_diversityControl = settings; 2781 } else if (AR_SREV_9280(ah) &&
6646 } 2782 (ah->ah_macRev == AR_SREV_REVISION_9280_10)) {
2783 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2784 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
6647 2785
6648 return true; 2786 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
6649} 2787 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2788 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
6650 2789
6651void ath9k_hw_setopmode(struct ath_hal *ah) 2790 if (ah->ah_config.pcie_clock_req)
6652{ 2791 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
6653 ath9k_hw_set_operating_mode(ah, ah->ah_opmode); 2792 else
6654} 2793 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
6655 2794
6656bool 2795 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
6657ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type, 2796 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
6658 u32 capability, u32 *result) 2797 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
6659{
6660 struct ath_hal_5416 *ahp = AH5416(ah);
6661 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
6662 2798
6663 switch (type) { 2799 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
6664 case ATH9K_CAP_CIPHER:
6665 switch (capability) {
6666 case ATH9K_CIPHER_AES_CCM:
6667 case ATH9K_CIPHER_AES_OCB:
6668 case ATH9K_CIPHER_TKIP:
6669 case ATH9K_CIPHER_WEP:
6670 case ATH9K_CIPHER_MIC:
6671 case ATH9K_CIPHER_CLR:
6672 return true;
6673 default:
6674 return false;
6675 }
6676 case ATH9K_CAP_TKIP_MIC:
6677 switch (capability) {
6678 case 0:
6679 return true;
6680 case 1:
6681 return (ahp->ah_staId1Defaults &
6682 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
6683 false;
6684 }
6685 case ATH9K_CAP_TKIP_SPLIT:
6686 return (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ?
6687 false : true;
6688 case ATH9K_CAP_WME_TKIPMIC:
6689 return 0;
6690 case ATH9K_CAP_PHYCOUNTERS:
6691 return ahp->ah_hasHwPhyCounters ? 0 : -ENXIO;
6692 case ATH9K_CAP_DIVERSITY:
6693 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
6694 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
6695 true : false;
6696 case ATH9K_CAP_PHYDIAG:
6697 return true;
6698 case ATH9K_CAP_MCAST_KEYSRCH:
6699 switch (capability) {
6700 case 0:
6701 return true;
6702 case 1:
6703 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
6704 return false;
6705 } else {
6706 return (ahp->ah_staId1Defaults &
6707 AR_STA_ID1_MCAST_KSRCH) ? true :
6708 false;
6709 }
6710 }
6711 return false;
6712 case ATH9K_CAP_TSF_ADJUST:
6713 return (ahp->ah_miscMode & AR_PCU_TX_ADD_TSF) ?
6714 true : false;
6715 case ATH9K_CAP_RFSILENT:
6716 if (capability == 3)
6717 return false;
6718 case ATH9K_CAP_ANT_CFG_2GHZ:
6719 *result = pCap->num_antcfg_2ghz;
6720 return true;
6721 case ATH9K_CAP_ANT_CFG_5GHZ:
6722 *result = pCap->num_antcfg_5ghz;
6723 return true;
6724 case ATH9K_CAP_TXPOW:
6725 switch (capability) {
6726 case 0:
6727 return 0;
6728 case 1:
6729 *result = ah->ah_powerLimit;
6730 return 0;
6731 case 2:
6732 *result = ah->ah_maxPowerLevel;
6733 return 0;
6734 case 3:
6735 *result = ah->ah_tpScale;
6736 return 0;
6737 }
6738 return false;
6739 default:
6740 return false;
6741 }
6742}
6743 2800
6744int 2801 udelay(1000);
6745ath9k_hw_select_antconfig(struct ath_hal *ah, u32 cfg) 2802 } else {
6746{ 2803 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
6747 struct ath_hal_5416 *ahp = AH5416(ah); 2804 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
6748 struct ath9k_channel *chan = ah->ah_curchan; 2805 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
6749 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 2806 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
6750 u16 ant_config; 2807 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
6751 u32 halNumAntConfig; 2808 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2809 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2810 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2811 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2812 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2813 }
6752 2814
6753 halNumAntConfig = 2815 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
6754 IS_CHAN_2GHZ(chan) ? pCap->num_antcfg_2ghz : pCap->
6755 num_antcfg_5ghz;
6756 2816
6757 if (cfg < halNumAntConfig) { 2817 if (ah->ah_config.pcie_waen) {
6758 if (!ath9k_hw_get_eeprom_antenna_cfg(ahp, chan, 2818 REG_WRITE(ah, AR_WA, ah->ah_config.pcie_waen);
6759 cfg, &ant_config)) { 2819 } else {
6760 REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config); 2820 if (AR_SREV_9285(ah))
6761 return 0; 2821 REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
6762 } 2822 else if (AR_SREV_9280(ah))
2823 REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
2824 else
2825 REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
6763 } 2826 }
6764 2827
6765 return -EINVAL;
6766} 2828}
6767 2829
2830/**********************/
2831/* Interrupt Handling */
2832/**********************/
2833
6768bool ath9k_hw_intrpend(struct ath_hal *ah) 2834bool ath9k_hw_intrpend(struct ath_hal *ah)
6769{ 2835{
6770 u32 host_isr; 2836 u32 host_isr;
@@ -6791,6 +2857,7 @@ bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
6791 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 2857 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
6792 u32 sync_cause = 0; 2858 u32 sync_cause = 0;
6793 bool fatal_int = false; 2859 bool fatal_int = false;
2860 struct ath_hal_5416 *ahp = AH5416(ah);
6794 2861
6795 if (!AR_SREV_9100(ah)) { 2862 if (!AR_SREV_9100(ah)) {
6796 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) { 2863 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
@@ -6800,9 +2867,8 @@ bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
6800 } 2867 }
6801 } 2868 }
6802 2869
6803 sync_cause = 2870 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
6804 REG_READ(ah, 2871 AR_INTR_SYNC_DEFAULT;
6805 AR_INTR_SYNC_CAUSE) & AR_INTR_SYNC_DEFAULT;
6806 2872
6807 *masked = 0; 2873 *masked = 0;
6808 2874
@@ -6814,8 +2880,6 @@ bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
6814 } 2880 }
6815 2881
6816 if (isr) { 2882 if (isr) {
6817 struct ath_hal_5416 *ahp = AH5416(ah);
6818
6819 if (isr & AR_ISR_BCNMISC) { 2883 if (isr & AR_ISR_BCNMISC) {
6820 u32 isr2; 2884 u32 isr2;
6821 isr2 = REG_READ(ah, AR_ISR_S2); 2885 isr2 = REG_READ(ah, AR_ISR_S2);
@@ -6842,7 +2906,6 @@ bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
6842 *masked = isr & ATH9K_INT_COMMON; 2906 *masked = isr & ATH9K_INT_COMMON;
6843 2907
6844 if (ahp->ah_intrMitigation) { 2908 if (ahp->ah_intrMitigation) {
6845
6846 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) 2909 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
6847 *masked |= ATH9K_INT_RX; 2910 *masked |= ATH9K_INT_RX;
6848 } 2911 }
@@ -6867,8 +2930,7 @@ bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
6867 2930
6868 if (isr & AR_ISR_RXORN) { 2931 if (isr & AR_ISR_RXORN) {
6869 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, 2932 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
6870 "%s: receive FIFO overrun interrupt\n", 2933 "receive FIFO overrun interrupt\n");
6871 __func__);
6872 } 2934 }
6873 2935
6874 if (!AR_SREV_9100(ah)) { 2936 if (!AR_SREV_9100(ah)) {
@@ -6881,8 +2943,10 @@ bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
6881 2943
6882 *masked |= mask2; 2944 *masked |= mask2;
6883 } 2945 }
2946
6884 if (AR_SREV_9100(ah)) 2947 if (AR_SREV_9100(ah))
6885 return true; 2948 return true;
2949
6886 if (sync_cause) { 2950 if (sync_cause) {
6887 fatal_int = 2951 fatal_int =
6888 (sync_cause & 2952 (sync_cause &
@@ -6892,32 +2956,29 @@ bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
6892 if (fatal_int) { 2956 if (fatal_int) {
6893 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) { 2957 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
6894 DPRINTF(ah->ah_sc, ATH_DBG_ANY, 2958 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
6895 "%s: received PCI FATAL interrupt\n", 2959 "received PCI FATAL interrupt\n");
6896 __func__);
6897 } 2960 }
6898 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) { 2961 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
6899 DPRINTF(ah->ah_sc, ATH_DBG_ANY, 2962 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
6900 "%s: received PCI PERR interrupt\n", 2963 "received PCI PERR interrupt\n");
6901 __func__);
6902 } 2964 }
6903 } 2965 }
6904 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { 2966 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
6905 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, 2967 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
6906 "%s: AR_INTR_SYNC_RADM_CPL_TIMEOUT\n", 2968 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
6907 __func__);
6908 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); 2969 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
6909 REG_WRITE(ah, AR_RC, 0); 2970 REG_WRITE(ah, AR_RC, 0);
6910 *masked |= ATH9K_INT_FATAL; 2971 *masked |= ATH9K_INT_FATAL;
6911 } 2972 }
6912 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) { 2973 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
6913 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, 2974 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
6914 "%s: AR_INTR_SYNC_LOCAL_TIMEOUT\n", 2975 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
6915 __func__);
6916 } 2976 }
6917 2977
6918 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); 2978 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
6919 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR); 2979 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
6920 } 2980 }
2981
6921 return true; 2982 return true;
6922} 2983}
6923 2984
@@ -6933,12 +2994,10 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
6933 u32 mask, mask2; 2994 u32 mask, mask2;
6934 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 2995 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
6935 2996
6936 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: 0x%x => 0x%x\n", __func__, 2997 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
6937 omask, ints);
6938 2998
6939 if (omask & ATH9K_INT_GLOBAL) { 2999 if (omask & ATH9K_INT_GLOBAL) {
6940 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: disable IER\n", 3000 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
6941 __func__);
6942 REG_WRITE(ah, AR_IER, AR_IER_DISABLE); 3001 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
6943 (void) REG_READ(ah, AR_IER); 3002 (void) REG_READ(ah, AR_IER);
6944 if (!AR_SREV_9100(ah)) { 3003 if (!AR_SREV_9100(ah)) {
@@ -6993,8 +3052,7 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
6993 mask2 |= AR_IMR_S2_CST; 3052 mask2 |= AR_IMR_S2_CST;
6994 } 3053 }
6995 3054
6996 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, 3055 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
6997 mask);
6998 REG_WRITE(ah, AR_IMR, mask); 3056 REG_WRITE(ah, AR_IMR, mask);
6999 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM | 3057 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
7000 AR_IMR_S2_DTIM | 3058 AR_IMR_S2_DTIM |
@@ -7014,8 +3072,7 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
7014 } 3072 }
7015 3073
7016 if (ints & ATH9K_INT_GLOBAL) { 3074 if (ints & ATH9K_INT_GLOBAL) {
7017 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: enable IER\n", 3075 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
7018 __func__);
7019 REG_WRITE(ah, AR_IER, AR_IER_ENABLE); 3076 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
7020 if (!AR_SREV_9100(ah)) { 3077 if (!AR_SREV_9100(ah)) {
7021 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 3078 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
@@ -7035,9 +3092,11 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
7035 return omask; 3092 return omask;
7036} 3093}
7037 3094
7038void 3095/*******************/
7039ath9k_hw_beaconinit(struct ath_hal *ah, 3096/* Beacon Handling */
7040 u32 next_beacon, u32 beacon_period) 3097/*******************/
3098
3099void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period)
7041{ 3100{
7042 struct ath_hal_5416 *ahp = AH5416(ah); 3101 struct ath_hal_5416 *ahp = AH5416(ah);
7043 int flags = 0; 3102 int flags = 0;
@@ -7045,14 +3104,14 @@ ath9k_hw_beaconinit(struct ath_hal *ah,
7045 ahp->ah_beaconInterval = beacon_period; 3104 ahp->ah_beaconInterval = beacon_period;
7046 3105
7047 switch (ah->ah_opmode) { 3106 switch (ah->ah_opmode) {
7048 case ATH9K_M_STA: 3107 case NL80211_IFTYPE_STATION:
7049 case ATH9K_M_MONITOR: 3108 case NL80211_IFTYPE_MONITOR:
7050 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); 3109 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
7051 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff); 3110 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
7052 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff); 3111 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
7053 flags |= AR_TBTT_TIMER_EN; 3112 flags |= AR_TBTT_TIMER_EN;
7054 break; 3113 break;
7055 case ATH9K_M_IBSS: 3114 case NL80211_IFTYPE_ADHOC:
7056 REG_SET_BIT(ah, AR_TXCFG, 3115 REG_SET_BIT(ah, AR_TXCFG,
7057 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); 3116 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
7058 REG_WRITE(ah, AR_NEXT_NDP_TIMER, 3117 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
@@ -7060,7 +3119,7 @@ ath9k_hw_beaconinit(struct ath_hal *ah,
7060 (ahp->ah_atimWindow ? ahp-> 3119 (ahp->ah_atimWindow ? ahp->
7061 ah_atimWindow : 1))); 3120 ah_atimWindow : 1)));
7062 flags |= AR_NDP_TIMER_EN; 3121 flags |= AR_NDP_TIMER_EN;
7063 case ATH9K_M_HOSTAP: 3122 case NL80211_IFTYPE_AP:
7064 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); 3123 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
7065 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 3124 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
7066 TU_TO_USEC(next_beacon - 3125 TU_TO_USEC(next_beacon -
@@ -7073,6 +3132,12 @@ ath9k_hw_beaconinit(struct ath_hal *ah,
7073 flags |= 3132 flags |=
7074 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 3133 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
7075 break; 3134 break;
3135 default:
3136 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3137 "%s: unsupported opmode: %d\n",
3138 __func__, ah->ah_opmode);
3139 return;
3140 break;
7076 } 3141 }
7077 3142
7078 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period)); 3143 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
@@ -7089,9 +3154,8 @@ ath9k_hw_beaconinit(struct ath_hal *ah,
7089 REG_SET_BIT(ah, AR_TIMER_MODE, flags); 3154 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
7090} 3155}
7091 3156
7092void 3157void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
7093ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah, 3158 const struct ath9k_beacon_state *bs)
7094 const struct ath9k_beacon_state *bs)
7095{ 3159{
7096 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; 3160 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
7097 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 3161 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
@@ -7120,14 +3184,10 @@ ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
7120 else 3184 else
7121 nextTbtt = bs->bs_nexttbtt; 3185 nextTbtt = bs->bs_nexttbtt;
7122 3186
7123 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: next DTIM %d\n", __func__, 3187 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
7124 bs->bs_nextdtim); 3188 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
7125 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: next beacon %d\n", __func__, 3189 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
7126 nextTbtt); 3190 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
7127 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: beacon period %d\n", __func__,
7128 beaconintval);
7129 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: DTIM period %d\n", __func__,
7130 dtimperiod);
7131 3191
7132 REG_WRITE(ah, AR_NEXT_DTIM, 3192 REG_WRITE(ah, AR_NEXT_DTIM,
7133 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); 3193 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
@@ -7154,1424 +3214,682 @@ ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
7154 3214
7155} 3215}
7156 3216
7157bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry) 3217/*******************/
7158{ 3218/* HW Capabilities */
7159 if (entry < ah->ah_caps.keycache_size) { 3219/*******************/
7160 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
7161 if (val & AR_KEYTABLE_VALID)
7162 return true;
7163 }
7164 return false;
7165}
7166 3220
7167bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry) 3221bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
7168{ 3222{
7169 u32 keyType; 3223 struct ath_hal_5416 *ahp = AH5416(ah);
3224 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3225 u16 capField = 0, eeval;
7170 3226
7171 if (entry >= ah->ah_caps.keycache_size) { 3227 eeval = ath9k_hw_get_eeprom(ah, EEP_REG_0);
7172 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
7173 "%s: entry %u out of range\n", __func__, entry);
7174 return false;
7175 }
7176 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
7177 3228
7178 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0); 3229 ah->ah_currentRD = eeval;
7179 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
7180 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
7181 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
7182 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
7183 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
7184 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
7185 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
7186 3230
7187 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) { 3231 eeval = ath9k_hw_get_eeprom(ah, EEP_REG_1);
7188 u16 micentry = entry + 64; 3232 ah->ah_currentRDExt = eeval;
7189 3233
7190 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0); 3234 capField = ath9k_hw_get_eeprom(ah, EEP_OP_CAP);
7191 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
7192 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
7193 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
7194 3235
3236 if (ah->ah_opmode != NL80211_IFTYPE_AP &&
3237 ah->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3238 if (ah->ah_currentRD == 0x64 || ah->ah_currentRD == 0x65)
3239 ah->ah_currentRD += 5;
3240 else if (ah->ah_currentRD == 0x41)
3241 ah->ah_currentRD = 0x43;
3242 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3243 "regdomain mapped to 0x%x\n", ah->ah_currentRD);
7195 } 3244 }
7196 3245
7197 if (ah->ah_curchan == NULL) 3246 eeval = ath9k_hw_get_eeprom(ah, EEP_OP_MODE);
7198 return true; 3247 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
7199
7200 return true;
7201}
7202
7203bool
7204ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry,
7205 const u8 *mac)
7206{
7207 u32 macHi, macLo;
7208
7209 if (entry >= ah->ah_caps.keycache_size) {
7210 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
7211 "%s: entry %u out of range\n", __func__, entry);
7212 return false;
7213 }
7214 3248
7215 if (mac != NULL) { 3249 if (eeval & AR5416_OPFLAGS_11A) {
7216 macHi = (mac[5] << 8) | mac[4]; 3250 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
7217 macLo = (mac[3] << 24) | (mac[2] << 16) 3251 if (ah->ah_config.ht_enable) {
7218 | (mac[1] << 8) | mac[0]; 3252 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
7219 macLo >>= 1; 3253 set_bit(ATH9K_MODE_11NA_HT20,
7220 macLo |= (macHi & 1) << 31; 3254 pCap->wireless_modes);
7221 macHi >>= 1; 3255 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
7222 } else { 3256 set_bit(ATH9K_MODE_11NA_HT40PLUS,
7223 macLo = macHi = 0; 3257 pCap->wireless_modes);
3258 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3259 pCap->wireless_modes);
3260 }
3261 }
7224 } 3262 }
7225 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
7226 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
7227 3263
7228 return true; 3264 if (eeval & AR5416_OPFLAGS_11G) {
7229} 3265 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
7230 3266 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
7231bool 3267 if (ah->ah_config.ht_enable) {
7232ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry, 3268 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
7233 const struct ath9k_keyval *k, 3269 set_bit(ATH9K_MODE_11NG_HT20,
7234 const u8 *mac, int xorKey) 3270 pCap->wireless_modes);
7235{ 3271 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
7236 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 3272 set_bit(ATH9K_MODE_11NG_HT40PLUS,
7237 u32 key0, key1, key2, key3, key4; 3273 pCap->wireless_modes);
7238 u32 keyType; 3274 set_bit(ATH9K_MODE_11NG_HT40MINUS,
7239 u32 xorMask = xorKey ? 3275 pCap->wireless_modes);
7240 (ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 | ATH9K_KEY_XOR << 8 3276 }
7241 | ATH9K_KEY_XOR) : 0;
7242 struct ath_hal_5416 *ahp = AH5416(ah);
7243
7244 if (entry >= pCap->keycache_size) {
7245 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
7246 "%s: entry %u out of range\n", __func__, entry);
7247 return false;
7248 }
7249 switch (k->kv_type) {
7250 case ATH9K_CIPHER_AES_OCB:
7251 keyType = AR_KEYTABLE_TYPE_AES;
7252 break;
7253 case ATH9K_CIPHER_AES_CCM:
7254 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
7255 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
7256 "%s: AES-CCM not supported by "
7257 "mac rev 0x%x\n", __func__,
7258 ah->ah_macRev);
7259 return false;
7260 }
7261 keyType = AR_KEYTABLE_TYPE_CCM;
7262 break;
7263 case ATH9K_CIPHER_TKIP:
7264 keyType = AR_KEYTABLE_TYPE_TKIP;
7265 if (ATH9K_IS_MIC_ENABLED(ah)
7266 && entry + 64 >= pCap->keycache_size) {
7267 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
7268 "%s: entry %u inappropriate for TKIP\n",
7269 __func__, entry);
7270 return false;
7271 }
7272 break;
7273 case ATH9K_CIPHER_WEP:
7274 if (k->kv_len < LEN_WEP40) {
7275 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
7276 "%s: WEP key length %u too small\n",
7277 __func__, k->kv_len);
7278 return false;
7279 } 3277 }
7280 if (k->kv_len <= LEN_WEP40)
7281 keyType = AR_KEYTABLE_TYPE_40;
7282 else if (k->kv_len <= LEN_WEP104)
7283 keyType = AR_KEYTABLE_TYPE_104;
7284 else
7285 keyType = AR_KEYTABLE_TYPE_128;
7286 break;
7287 case ATH9K_CIPHER_CLR:
7288 keyType = AR_KEYTABLE_TYPE_CLR;
7289 break;
7290 default:
7291 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
7292 "%s: cipher %u not supported\n", __func__,
7293 k->kv_type);
7294 return false;
7295 } 3278 }
7296 3279
7297 key0 = get_unaligned_le32(k->kv_val + 0) ^ xorMask; 3280 pCap->tx_chainmask = ath9k_hw_get_eeprom(ah, EEP_TX_MASK);
7298 key1 = (get_unaligned_le16(k->kv_val + 4) ^ xorMask) & 0xffff; 3281 if ((ah->ah_isPciExpress)
7299 key2 = get_unaligned_le32(k->kv_val + 6) ^ xorMask; 3282 || (eeval & AR5416_OPFLAGS_11A)) {
7300 key3 = (get_unaligned_le16(k->kv_val + 10) ^ xorMask) & 0xffff; 3283 pCap->rx_chainmask =
7301 key4 = get_unaligned_le32(k->kv_val + 12) ^ xorMask; 3284 ath9k_hw_get_eeprom(ah, EEP_RX_MASK);
7302 if (k->kv_len <= LEN_WEP104)
7303 key4 &= 0xff;
7304
7305 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
7306 u16 micentry = entry + 64;
7307
7308 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
7309 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
7310 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
7311 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
7312 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
7313 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
7314 (void) ath9k_hw_keysetmac(ah, entry, mac);
7315
7316 if (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) {
7317 u32 mic0, mic1, mic2, mic3, mic4;
7318
7319 mic0 = get_unaligned_le32(k->kv_mic + 0);
7320 mic2 = get_unaligned_le32(k->kv_mic + 4);
7321 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
7322 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
7323 mic4 = get_unaligned_le32(k->kv_txmic + 4);
7324 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
7325 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
7326 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
7327 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
7328 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
7329 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
7330 AR_KEYTABLE_TYPE_CLR);
7331
7332 } else {
7333 u32 mic0, mic2;
7334
7335 mic0 = get_unaligned_le32(k->kv_mic + 0);
7336 mic2 = get_unaligned_le32(k->kv_mic + 4);
7337 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
7338 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
7339 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
7340 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
7341 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
7342 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
7343 AR_KEYTABLE_TYPE_CLR);
7344 }
7345 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
7346 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
7347 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
7348 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
7349 } else { 3285 } else {
7350 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0); 3286 pCap->rx_chainmask =
7351 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1); 3287 (ath9k_hw_gpio_get(ah, 0)) ? 0x5 : 0x7;
7352 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
7353 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
7354 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
7355 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
7356
7357 (void) ath9k_hw_keysetmac(ah, entry, mac);
7358 } 3288 }
7359 3289
7360 if (ah->ah_curchan == NULL) 3290 if (!(AR_SREV_9280(ah) && (ah->ah_macRev == 0)))
7361 return true; 3291 ahp->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA;
7362
7363 return true;
7364}
7365
7366bool
7367ath9k_hw_updatetxtriglevel(struct ath_hal *ah, bool bIncTrigLevel)
7368{
7369 struct ath_hal_5416 *ahp = AH5416(ah);
7370 u32 txcfg, curLevel, newLevel;
7371 enum ath9k_int omask;
7372
7373 if (ah->ah_txTrigLevel >= MAX_TX_FIFO_THRESHOLD)
7374 return false;
7375
7376 omask = ath9k_hw_set_interrupts(ah,
7377 ahp->ah_maskReg & ~ATH9K_INT_GLOBAL);
7378
7379 txcfg = REG_READ(ah, AR_TXCFG);
7380 curLevel = MS(txcfg, AR_FTRIG);
7381 newLevel = curLevel;
7382 if (bIncTrigLevel) {
7383 if (curLevel < MAX_TX_FIFO_THRESHOLD)
7384 newLevel++;
7385 } else if (curLevel > MIN_TX_FIFO_THRESHOLD)
7386 newLevel--;
7387 if (newLevel != curLevel)
7388 REG_WRITE(ah, AR_TXCFG,
7389 (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG));
7390 3292
7391 ath9k_hw_set_interrupts(ah, omask); 3293 pCap->low_2ghz_chan = 2312;
3294 pCap->high_2ghz_chan = 2732;
7392 3295
7393 ah->ah_txTrigLevel = newLevel; 3296 pCap->low_5ghz_chan = 4920;
3297 pCap->high_5ghz_chan = 6100;
7394 3298
7395 return newLevel != curLevel; 3299 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
7396} 3300 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3301 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
7397 3302
7398bool ath9k_hw_set_txq_props(struct ath_hal *ah, int q, 3303 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
7399 const struct ath9k_tx_queue_info *qinfo) 3304 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
7400{ 3305 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
7401 u32 cw;
7402 struct ath_hal_5416 *ahp = AH5416(ah);
7403 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
7404 struct ath9k_tx_queue_info *qi;
7405 3306
7406 if (q >= pCap->total_queues) { 3307 pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD;
7407 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n",
7408 __func__, q);
7409 return false;
7410 }
7411 3308
7412 qi = &ahp->ah_txq[q]; 3309 if (ah->ah_config.ht_enable)
7413 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 3310 pCap->hw_caps |= ATH9K_HW_CAP_HT;
7414 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue\n", 3311 else
7415 __func__); 3312 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
7416 return false;
7417 }
7418 3313
7419 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: queue %p\n", __func__, qi); 3314 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3315 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3316 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3317 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
7420 3318
7421 qi->tqi_ver = qinfo->tqi_ver; 3319 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
7422 qi->tqi_subtype = qinfo->tqi_subtype; 3320 pCap->total_queues =
7423 qi->tqi_qflags = qinfo->tqi_qflags; 3321 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
7424 qi->tqi_priority = qinfo->tqi_priority;
7425 if (qinfo->tqi_aifs != ATH9K_TXQ_USEDEFAULT)
7426 qi->tqi_aifs = min(qinfo->tqi_aifs, 255U);
7427 else 3322 else
7428 qi->tqi_aifs = INIT_AIFS; 3323 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
7429 if (qinfo->tqi_cwmin != ATH9K_TXQ_USEDEFAULT) {
7430 cw = min(qinfo->tqi_cwmin, 1024U);
7431 qi->tqi_cwmin = 1;
7432 while (qi->tqi_cwmin < cw)
7433 qi->tqi_cwmin = (qi->tqi_cwmin << 1) | 1;
7434 } else
7435 qi->tqi_cwmin = qinfo->tqi_cwmin;
7436 if (qinfo->tqi_cwmax != ATH9K_TXQ_USEDEFAULT) {
7437 cw = min(qinfo->tqi_cwmax, 1024U);
7438 qi->tqi_cwmax = 1;
7439 while (qi->tqi_cwmax < cw)
7440 qi->tqi_cwmax = (qi->tqi_cwmax << 1) | 1;
7441 } else
7442 qi->tqi_cwmax = INIT_CWMAX;
7443 3324
7444 if (qinfo->tqi_shretry != 0) 3325 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
7445 qi->tqi_shretry = min((u32) qinfo->tqi_shretry, 15U); 3326 pCap->keycache_size =
7446 else 3327 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
7447 qi->tqi_shretry = INIT_SH_RETRY;
7448 if (qinfo->tqi_lgretry != 0)
7449 qi->tqi_lgretry = min((u32) qinfo->tqi_lgretry, 15U);
7450 else 3328 else
7451 qi->tqi_lgretry = INIT_LG_RETRY; 3329 pCap->keycache_size = AR_KEYTABLE_SIZE;
7452 qi->tqi_cbrPeriod = qinfo->tqi_cbrPeriod;
7453 qi->tqi_cbrOverflowLimit = qinfo->tqi_cbrOverflowLimit;
7454 qi->tqi_burstTime = qinfo->tqi_burstTime;
7455 qi->tqi_readyTime = qinfo->tqi_readyTime;
7456
7457 switch (qinfo->tqi_subtype) {
7458 case ATH9K_WME_UPSD:
7459 if (qi->tqi_type == ATH9K_TX_QUEUE_DATA)
7460 qi->tqi_intFlags = ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS;
7461 break;
7462 default:
7463 break;
7464 }
7465 return true;
7466}
7467 3330
7468bool ath9k_hw_get_txq_props(struct ath_hal *ah, int q, 3331 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
7469 struct ath9k_tx_queue_info *qinfo) 3332 pCap->num_mr_retries = 4;
7470{ 3333 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
7471 struct ath_hal_5416 *ahp = AH5416(ah);
7472 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
7473 struct ath9k_tx_queue_info *qi;
7474 3334
7475 if (q >= pCap->total_queues) { 3335 if (AR_SREV_9280_10_OR_LATER(ah))
7476 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n", 3336 pCap->num_gpio_pins = AR928X_NUM_GPIO;
7477 __func__, q); 3337 else
7478 return false; 3338 pCap->num_gpio_pins = AR_NUM_GPIO;
7479 }
7480 3339
7481 qi = &ahp->ah_txq[q]; 3340 if (AR_SREV_9280_10_OR_LATER(ah)) {
7482 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 3341 pCap->hw_caps |= ATH9K_HW_CAP_WOW;
7483 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue\n", 3342 pCap->hw_caps |= ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
7484 __func__); 3343 } else {
7485 return false; 3344 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW;
3345 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
7486 } 3346 }
7487 3347
7488 qinfo->tqi_qflags = qi->tqi_qflags; 3348 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
7489 qinfo->tqi_ver = qi->tqi_ver; 3349 pCap->hw_caps |= ATH9K_HW_CAP_CST;
7490 qinfo->tqi_subtype = qi->tqi_subtype; 3350 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
7491 qinfo->tqi_qflags = qi->tqi_qflags; 3351 } else {
7492 qinfo->tqi_priority = qi->tqi_priority; 3352 pCap->rts_aggr_limit = (8 * 1024);
7493 qinfo->tqi_aifs = qi->tqi_aifs; 3353 }
7494 qinfo->tqi_cwmin = qi->tqi_cwmin;
7495 qinfo->tqi_cwmax = qi->tqi_cwmax;
7496 qinfo->tqi_shretry = qi->tqi_shretry;
7497 qinfo->tqi_lgretry = qi->tqi_lgretry;
7498 qinfo->tqi_cbrPeriod = qi->tqi_cbrPeriod;
7499 qinfo->tqi_cbrOverflowLimit = qi->tqi_cbrOverflowLimit;
7500 qinfo->tqi_burstTime = qi->tqi_burstTime;
7501 qinfo->tqi_readyTime = qi->tqi_readyTime;
7502 3354
7503 return true; 3355 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
7504}
7505 3356
7506int 3357#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
7507ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type, 3358 ah->ah_rfsilent = ath9k_hw_get_eeprom(ah, EEP_RF_SILENT);
7508 const struct ath9k_tx_queue_info *qinfo) 3359 if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) {
7509{ 3360 ah->ah_rfkill_gpio =
7510 struct ath_hal_5416 *ahp = AH5416(ah); 3361 MS(ah->ah_rfsilent, EEP_RFSILENT_GPIO_SEL);
7511 struct ath9k_tx_queue_info *qi; 3362 ah->ah_rfkill_polarity =
7512 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 3363 MS(ah->ah_rfsilent, EEP_RFSILENT_POLARITY);
7513 int q;
7514 3364
7515 switch (type) { 3365 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
7516 case ATH9K_TX_QUEUE_BEACON:
7517 q = pCap->total_queues - 1;
7518 break;
7519 case ATH9K_TX_QUEUE_CAB:
7520 q = pCap->total_queues - 2;
7521 break;
7522 case ATH9K_TX_QUEUE_PSPOLL:
7523 q = 1;
7524 break;
7525 case ATH9K_TX_QUEUE_UAPSD:
7526 q = pCap->total_queues - 3;
7527 break;
7528 case ATH9K_TX_QUEUE_DATA:
7529 for (q = 0; q < pCap->total_queues; q++)
7530 if (ahp->ah_txq[q].tqi_type ==
7531 ATH9K_TX_QUEUE_INACTIVE)
7532 break;
7533 if (q == pCap->total_queues) {
7534 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
7535 "%s: no available tx queue\n", __func__);
7536 return -1;
7537 }
7538 break;
7539 default:
7540 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: bad tx queue type %u\n",
7541 __func__, type);
7542 return -1;
7543 } 3366 }
3367#endif
3368
3369 if ((ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) ||
3370 (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE) ||
3371 (ah->ah_macVersion == AR_SREV_VERSION_9160) ||
3372 (ah->ah_macVersion == AR_SREV_VERSION_9100) ||
3373 (ah->ah_macVersion == AR_SREV_VERSION_9280))
3374 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3375 else
3376 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
7544 3377
7545 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: queue %u\n", __func__, q); 3378 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3379 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3380 else
3381 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
7546 3382
7547 qi = &ahp->ah_txq[q]; 3383 if (ah->ah_currentRDExt & (1 << REG_EXT_JAPAN_MIDBAND)) {
7548 if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) { 3384 pCap->reg_cap =
7549 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, 3385 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
7550 "%s: tx queue %u already active\n", __func__, q); 3386 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
7551 return -1; 3387 AR_EEPROM_EEREGCAP_EN_KK_U2 |
7552 } 3388 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
7553 memset(qi, 0, sizeof(struct ath9k_tx_queue_info));
7554 qi->tqi_type = type;
7555 if (qinfo == NULL) {
7556 qi->tqi_qflags =
7557 TXQ_FLAG_TXOKINT_ENABLE
7558 | TXQ_FLAG_TXERRINT_ENABLE
7559 | TXQ_FLAG_TXDESCINT_ENABLE | TXQ_FLAG_TXURNINT_ENABLE;
7560 qi->tqi_aifs = INIT_AIFS;
7561 qi->tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
7562 qi->tqi_cwmax = INIT_CWMAX;
7563 qi->tqi_shretry = INIT_SH_RETRY;
7564 qi->tqi_lgretry = INIT_LG_RETRY;
7565 qi->tqi_physCompBuf = 0;
7566 } else { 3389 } else {
7567 qi->tqi_physCompBuf = qinfo->tqi_physCompBuf; 3390 pCap->reg_cap =
7568 (void) ath9k_hw_set_txq_props(ah, q, qinfo); 3391 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3392 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
7569 } 3393 }
7570 3394
7571 return q; 3395 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
7572}
7573 3396
7574static void 3397 pCap->num_antcfg_5ghz =
7575ath9k_hw_set_txq_interrupts(struct ath_hal *ah, 3398 ath9k_hw_get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
7576 struct ath9k_tx_queue_info *qi) 3399 pCap->num_antcfg_2ghz =
7577{ 3400 ath9k_hw_get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
7578 struct ath_hal_5416 *ahp = AH5416(ah);
7579 3401
7580 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, 3402 return true;
7581 "%s: tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
7582 __func__, ahp->ah_txOkInterruptMask,
7583 ahp->ah_txErrInterruptMask, ahp->ah_txDescInterruptMask,
7584 ahp->ah_txEolInterruptMask, ahp->ah_txUrnInterruptMask);
7585
7586 REG_WRITE(ah, AR_IMR_S0,
7587 SM(ahp->ah_txOkInterruptMask, AR_IMR_S0_QCU_TXOK)
7588 | SM(ahp->ah_txDescInterruptMask, AR_IMR_S0_QCU_TXDESC));
7589 REG_WRITE(ah, AR_IMR_S1,
7590 SM(ahp->ah_txErrInterruptMask, AR_IMR_S1_QCU_TXERR)
7591 | SM(ahp->ah_txEolInterruptMask, AR_IMR_S1_QCU_TXEOL));
7592 REG_RMW_FIELD(ah, AR_IMR_S2,
7593 AR_IMR_S2_QCU_TXURN, ahp->ah_txUrnInterruptMask);
7594} 3403}
7595 3404
7596bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q) 3405bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3406 u32 capability, u32 *result)
7597{ 3407{
7598 struct ath_hal_5416 *ahp = AH5416(ah); 3408 struct ath_hal_5416 *ahp = AH5416(ah);
7599 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 3409 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
7600 struct ath9k_tx_queue_info *qi;
7601 3410
7602 if (q >= pCap->total_queues) { 3411 switch (type) {
7603 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n", 3412 case ATH9K_CAP_CIPHER:
7604 __func__, q); 3413 switch (capability) {
3414 case ATH9K_CIPHER_AES_CCM:
3415 case ATH9K_CIPHER_AES_OCB:
3416 case ATH9K_CIPHER_TKIP:
3417 case ATH9K_CIPHER_WEP:
3418 case ATH9K_CIPHER_MIC:
3419 case ATH9K_CIPHER_CLR:
3420 return true;
3421 default:
3422 return false;
3423 }
3424 case ATH9K_CAP_TKIP_MIC:
3425 switch (capability) {
3426 case 0:
3427 return true;
3428 case 1:
3429 return (ahp->ah_staId1Defaults &
3430 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3431 false;
3432 }
3433 case ATH9K_CAP_TKIP_SPLIT:
3434 return (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ?
3435 false : true;
3436 case ATH9K_CAP_WME_TKIPMIC:
3437 return 0;
3438 case ATH9K_CAP_PHYCOUNTERS:
3439 return ahp->ah_hasHwPhyCounters ? 0 : -ENXIO;
3440 case ATH9K_CAP_DIVERSITY:
3441 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3442 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3443 true : false;
3444 case ATH9K_CAP_PHYDIAG:
3445 return true;
3446 case ATH9K_CAP_MCAST_KEYSRCH:
3447 switch (capability) {
3448 case 0:
3449 return true;
3450 case 1:
3451 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3452 return false;
3453 } else {
3454 return (ahp->ah_staId1Defaults &
3455 AR_STA_ID1_MCAST_KSRCH) ? true :
3456 false;
3457 }
3458 }
7605 return false; 3459 return false;
7606 } 3460 case ATH9K_CAP_TSF_ADJUST:
7607 qi = &ahp->ah_txq[q]; 3461 return (ahp->ah_miscMode & AR_PCU_TX_ADD_TSF) ?
7608 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 3462 true : false;
7609 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue %u\n", 3463 case ATH9K_CAP_RFSILENT:
7610 __func__, q); 3464 if (capability == 3)
3465 return false;
3466 case ATH9K_CAP_ANT_CFG_2GHZ:
3467 *result = pCap->num_antcfg_2ghz;
3468 return true;
3469 case ATH9K_CAP_ANT_CFG_5GHZ:
3470 *result = pCap->num_antcfg_5ghz;
3471 return true;
3472 case ATH9K_CAP_TXPOW:
3473 switch (capability) {
3474 case 0:
3475 return 0;
3476 case 1:
3477 *result = ah->ah_powerLimit;
3478 return 0;
3479 case 2:
3480 *result = ah->ah_maxPowerLevel;
3481 return 0;
3482 case 3:
3483 *result = ah->ah_tpScale;
3484 return 0;
3485 }
3486 return false;
3487 default:
7611 return false; 3488 return false;
7612 } 3489 }
7613
7614 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: release queue %u\n",
7615 __func__, q);
7616
7617 qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE;
7618 ahp->ah_txOkInterruptMask &= ~(1 << q);
7619 ahp->ah_txErrInterruptMask &= ~(1 << q);
7620 ahp->ah_txDescInterruptMask &= ~(1 << q);
7621 ahp->ah_txEolInterruptMask &= ~(1 << q);
7622 ahp->ah_txUrnInterruptMask &= ~(1 << q);
7623 ath9k_hw_set_txq_interrupts(ah, qi);
7624
7625 return true;
7626} 3490}
7627 3491
7628bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q) 3492bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3493 u32 capability, u32 setting, int *status)
7629{ 3494{
7630 struct ath_hal_5416 *ahp = AH5416(ah); 3495 struct ath_hal_5416 *ahp = AH5416(ah);
7631 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 3496 u32 v;
7632 struct ath9k_channel *chan = ah->ah_curchan;
7633 struct ath9k_tx_queue_info *qi;
7634 u32 cwMin, chanCwMin, value;
7635 3497
7636 if (q >= pCap->total_queues) { 3498 switch (type) {
7637 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n", 3499 case ATH9K_CAP_TKIP_MIC:
7638 __func__, q); 3500 if (setting)
7639 return false; 3501 ahp->ah_staId1Defaults |=
7640 } 3502 AR_STA_ID1_CRPT_MIC_ENABLE;
7641 qi = &ahp->ah_txq[q]; 3503 else
7642 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 3504 ahp->ah_staId1Defaults &=
7643 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue %u\n", 3505 ~AR_STA_ID1_CRPT_MIC_ENABLE;
7644 __func__, q);
7645 return true; 3506 return true;
7646 } 3507 case ATH9K_CAP_DIVERSITY:
7647 3508 v = REG_READ(ah, AR_PHY_CCK_DETECT);
7648 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: reset queue %u\n", __func__, q); 3509 if (setting)
7649 3510 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
7650 if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) {
7651 if (chan && IS_CHAN_B(chan))
7652 chanCwMin = INIT_CWMIN_11B;
7653 else 3511 else
7654 chanCwMin = INIT_CWMIN; 3512 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
7655 3513 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
7656 for (cwMin = 1; cwMin < chanCwMin; cwMin = (cwMin << 1) | 1); 3514 return true;
7657 } else 3515 case ATH9K_CAP_MCAST_KEYSRCH:
7658 cwMin = qi->tqi_cwmin; 3516 if (setting)
7659 3517 ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH;
7660 REG_WRITE(ah, AR_DLCL_IFS(q), SM(cwMin, AR_D_LCL_IFS_CWMIN) 3518 else
7661 | SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) 3519 ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH;
7662 | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS)); 3520 return true;
7663 3521 case ATH9K_CAP_TSF_ADJUST:
7664 REG_WRITE(ah, AR_DRETRY_LIMIT(q), 3522 if (setting)
7665 SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) 3523 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
7666 | SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) 3524 else
7667 | SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH)); 3525 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
7668 3526 return true;
7669 REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);
7670 REG_WRITE(ah, AR_DMISC(q),
7671 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2);
7672
7673 if (qi->tqi_cbrPeriod) {
7674 REG_WRITE(ah, AR_QCBRCFG(q),
7675 SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL)
7676 | SM(qi->tqi_cbrOverflowLimit,
7677 AR_Q_CBRCFG_OVF_THRESH));
7678 REG_WRITE(ah, AR_QMISC(q),
7679 REG_READ(ah,
7680 AR_QMISC(q)) | AR_Q_MISC_FSP_CBR | (qi->
7681 tqi_cbrOverflowLimit
7682 ?
7683 AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN
7684 :
7685 0));
7686 }
7687 if (qi->tqi_readyTime && (qi->tqi_type != ATH9K_TX_QUEUE_CAB)) {
7688 REG_WRITE(ah, AR_QRDYTIMECFG(q),
7689 SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) |
7690 AR_Q_RDYTIMECFG_EN);
7691 }
7692
7693 REG_WRITE(ah, AR_DCHNTIME(q),
7694 SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |
7695 (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
7696
7697 if (qi->tqi_burstTime
7698 && (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)) {
7699 REG_WRITE(ah, AR_QMISC(q),
7700 REG_READ(ah,
7701 AR_QMISC(q)) |
7702 AR_Q_MISC_RDYTIME_EXP_POLICY);
7703
7704 }
7705
7706 if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE) {
7707 REG_WRITE(ah, AR_DMISC(q),
7708 REG_READ(ah, AR_DMISC(q)) |
7709 AR_D_MISC_POST_FR_BKOFF_DIS);
7710 }
7711 if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) {
7712 REG_WRITE(ah, AR_DMISC(q),
7713 REG_READ(ah, AR_DMISC(q)) |
7714 AR_D_MISC_FRAG_BKOFF_EN);
7715 }
7716 switch (qi->tqi_type) {
7717 case ATH9K_TX_QUEUE_BEACON:
7718 REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
7719 | AR_Q_MISC_FSP_DBA_GATED
7720 | AR_Q_MISC_BEACON_USE
7721 | AR_Q_MISC_CBR_INCR_DIS1);
7722
7723 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
7724 | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
7725 AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
7726 | AR_D_MISC_BEACON_USE
7727 | AR_D_MISC_POST_FR_BKOFF_DIS);
7728 break;
7729 case ATH9K_TX_QUEUE_CAB:
7730 REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
7731 | AR_Q_MISC_FSP_DBA_GATED
7732 | AR_Q_MISC_CBR_INCR_DIS1
7733 | AR_Q_MISC_CBR_INCR_DIS0);
7734 value = (qi->tqi_readyTime
7735 - (ah->ah_config.sw_beacon_response_time -
7736 ah->ah_config.dma_beacon_response_time)
7737 -
7738 ah->ah_config.additional_swba_backoff) *
7739 1024;
7740 REG_WRITE(ah, AR_QRDYTIMECFG(q),
7741 value | AR_Q_RDYTIMECFG_EN);
7742 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
7743 | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
7744 AR_D_MISC_ARB_LOCKOUT_CNTRL_S));
7745 break;
7746 case ATH9K_TX_QUEUE_PSPOLL:
7747 REG_WRITE(ah, AR_QMISC(q),
7748 REG_READ(ah,
7749 AR_QMISC(q)) | AR_Q_MISC_CBR_INCR_DIS1);
7750 break;
7751 case ATH9K_TX_QUEUE_UAPSD:
7752 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
7753 | AR_D_MISC_POST_FR_BKOFF_DIS);
7754 break;
7755 default: 3527 default:
7756 break; 3528 return false;
7757 }
7758
7759 if (qi->tqi_intFlags & ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS) {
7760 REG_WRITE(ah, AR_DMISC(q),
7761 REG_READ(ah, AR_DMISC(q)) |
7762 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
7763 AR_D_MISC_ARB_LOCKOUT_CNTRL) |
7764 AR_D_MISC_POST_FR_BKOFF_DIS);
7765 } 3529 }
7766
7767 if (qi->tqi_qflags & TXQ_FLAG_TXOKINT_ENABLE)
7768 ahp->ah_txOkInterruptMask |= 1 << q;
7769 else
7770 ahp->ah_txOkInterruptMask &= ~(1 << q);
7771 if (qi->tqi_qflags & TXQ_FLAG_TXERRINT_ENABLE)
7772 ahp->ah_txErrInterruptMask |= 1 << q;
7773 else
7774 ahp->ah_txErrInterruptMask &= ~(1 << q);
7775 if (qi->tqi_qflags & TXQ_FLAG_TXDESCINT_ENABLE)
7776 ahp->ah_txDescInterruptMask |= 1 << q;
7777 else
7778 ahp->ah_txDescInterruptMask &= ~(1 << q);
7779 if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE)
7780 ahp->ah_txEolInterruptMask |= 1 << q;
7781 else
7782 ahp->ah_txEolInterruptMask &= ~(1 << q);
7783 if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE)
7784 ahp->ah_txUrnInterruptMask |= 1 << q;
7785 else
7786 ahp->ah_txUrnInterruptMask &= ~(1 << q);
7787 ath9k_hw_set_txq_interrupts(ah, qi);
7788
7789 return true;
7790} 3530}
7791 3531
7792void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u32 *txqs) 3532/****************************/
7793{ 3533/* GPIO / RFKILL / Antennae */
7794 struct ath_hal_5416 *ahp = AH5416(ah); 3534/****************************/
7795 *txqs &= ahp->ah_intrTxqs;
7796 ahp->ah_intrTxqs &= ~(*txqs);
7797}
7798 3535
7799bool 3536static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah,
7800ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds, 3537 u32 gpio, u32 type)
7801 u32 segLen, bool firstSeg,
7802 bool lastSeg, const struct ath_desc *ds0)
7803{
7804 struct ar5416_desc *ads = AR5416DESC(ds);
7805
7806 if (firstSeg) {
7807 ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_TxMore);
7808 } else if (lastSeg) {
7809 ads->ds_ctl0 = 0;
7810 ads->ds_ctl1 = segLen;
7811 ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
7812 ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
7813 } else {
7814 ads->ds_ctl0 = 0;
7815 ads->ds_ctl1 = segLen | AR_TxMore;
7816 ads->ds_ctl2 = 0;
7817 ads->ds_ctl3 = 0;
7818 }
7819 ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
7820 ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
7821 ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
7822 ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
7823 ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
7824 return true;
7825}
7826
7827void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds)
7828{ 3538{
7829 struct ar5416_desc *ads = AR5416DESC(ds); 3539 int addr;
3540 u32 gpio_shift, tmp;
7830 3541
7831 ads->ds_txstatus0 = ads->ds_txstatus1 = 0; 3542 if (gpio > 11)
7832 ads->ds_txstatus2 = ads->ds_txstatus3 = 0; 3543 addr = AR_GPIO_OUTPUT_MUX3;
7833 ads->ds_txstatus4 = ads->ds_txstatus5 = 0; 3544 else if (gpio > 5)
7834 ads->ds_txstatus6 = ads->ds_txstatus7 = 0; 3545 addr = AR_GPIO_OUTPUT_MUX2;
7835 ads->ds_txstatus8 = ads->ds_txstatus9 = 0; 3546 else
7836} 3547 addr = AR_GPIO_OUTPUT_MUX1;
7837 3548
7838int 3549 gpio_shift = (gpio % 6) * 5;
7839ath9k_hw_txprocdesc(struct ath_hal *ah, struct ath_desc *ds)
7840{
7841 struct ar5416_desc *ads = AR5416DESC(ds);
7842
7843 if ((ads->ds_txstatus9 & AR_TxDone) == 0)
7844 return -EINPROGRESS;
7845
7846 ds->ds_txstat.ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
7847 ds->ds_txstat.ts_tstamp = ads->AR_SendTimestamp;
7848 ds->ds_txstat.ts_status = 0;
7849 ds->ds_txstat.ts_flags = 0;
7850
7851 if (ads->ds_txstatus1 & AR_ExcessiveRetries)
7852 ds->ds_txstat.ts_status |= ATH9K_TXERR_XRETRY;
7853 if (ads->ds_txstatus1 & AR_Filtered)
7854 ds->ds_txstat.ts_status |= ATH9K_TXERR_FILT;
7855 if (ads->ds_txstatus1 & AR_FIFOUnderrun)
7856 ds->ds_txstat.ts_status |= ATH9K_TXERR_FIFO;
7857 if (ads->ds_txstatus9 & AR_TxOpExceeded)
7858 ds->ds_txstat.ts_status |= ATH9K_TXERR_XTXOP;
7859 if (ads->ds_txstatus1 & AR_TxTimerExpired)
7860 ds->ds_txstat.ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
7861
7862 if (ads->ds_txstatus1 & AR_DescCfgErr)
7863 ds->ds_txstat.ts_flags |= ATH9K_TX_DESC_CFG_ERR;
7864 if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
7865 ds->ds_txstat.ts_flags |= ATH9K_TX_DATA_UNDERRUN;
7866 ath9k_hw_updatetxtriglevel(ah, true);
7867 }
7868 if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
7869 ds->ds_txstat.ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
7870 ath9k_hw_updatetxtriglevel(ah, true);
7871 }
7872 if (ads->ds_txstatus0 & AR_TxBaStatus) {
7873 ds->ds_txstat.ts_flags |= ATH9K_TX_BA;
7874 ds->ds_txstat.ba_low = ads->AR_BaBitmapLow;
7875 ds->ds_txstat.ba_high = ads->AR_BaBitmapHigh;
7876 }
7877 3550
7878 ds->ds_txstat.ts_rateindex = MS(ads->ds_txstatus9, AR_FinalTxIdx); 3551 if (AR_SREV_9280_20_OR_LATER(ah)
7879 switch (ds->ds_txstat.ts_rateindex) { 3552 || (addr != AR_GPIO_OUTPUT_MUX1)) {
7880 case 0: 3553 REG_RMW(ah, addr, (type << gpio_shift),
7881 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate0); 3554 (0x1f << gpio_shift));
7882 break; 3555 } else {
7883 case 1: 3556 tmp = REG_READ(ah, addr);
7884 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate1); 3557 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
7885 break; 3558 tmp &= ~(0x1f << gpio_shift);
7886 case 2: 3559 tmp |= (type << gpio_shift);
7887 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate2); 3560 REG_WRITE(ah, addr, tmp);
7888 break;
7889 case 3:
7890 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate3);
7891 break;
7892 } 3561 }
7893
7894 ds->ds_txstat.ts_rssi = MS(ads->ds_txstatus5, AR_TxRSSICombined);
7895 ds->ds_txstat.ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
7896 ds->ds_txstat.ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
7897 ds->ds_txstat.ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
7898 ds->ds_txstat.ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
7899 ds->ds_txstat.ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
7900 ds->ds_txstat.ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
7901 ds->ds_txstat.evm0 = ads->AR_TxEVM0;
7902 ds->ds_txstat.evm1 = ads->AR_TxEVM1;
7903 ds->ds_txstat.evm2 = ads->AR_TxEVM2;
7904 ds->ds_txstat.ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
7905 ds->ds_txstat.ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
7906 ds->ds_txstat.ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
7907 ds->ds_txstat.ts_antenna = 1;
7908
7909 return 0;
7910} 3562}
7911 3563
7912void 3564void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio)
7913ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds,
7914 u32 pktLen, enum ath9k_pkt_type type, u32 txPower,
7915 u32 keyIx, enum ath9k_key_type keyType, u32 flags)
7916{ 3565{
7917 struct ar5416_desc *ads = AR5416DESC(ds); 3566 u32 gpio_shift;
7918 struct ath_hal_5416 *ahp = AH5416(ah);
7919
7920 txPower += ahp->ah_txPowerIndexOffset;
7921 if (txPower > 63)
7922 txPower = 63;
7923
7924 ads->ds_ctl0 = (pktLen & AR_FrameLen)
7925 | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
7926 | SM(txPower, AR_XmitPower)
7927 | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
7928 | (flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
7929 | (flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0)
7930 | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0);
7931
7932 ads->ds_ctl1 =
7933 (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
7934 | SM(type, AR_FrameType)
7935 | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
7936 | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
7937 | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
7938 3567
7939 ads->ds_ctl6 = SM(keyType, AR_EncrType); 3568 ASSERT(gpio < ah->ah_caps.num_gpio_pins);
7940 3569
7941 if (AR_SREV_9285(ah)) { 3570 gpio_shift = gpio << 1;
7942 3571
7943 ads->ds_ctl8 = 0; 3572 REG_RMW(ah,
7944 ads->ds_ctl9 = 0; 3573 AR_GPIO_OE_OUT,
7945 ads->ds_ctl10 = 0; 3574 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
7946 ads->ds_ctl11 = 0; 3575 (AR_GPIO_OE_OUT_DRV << gpio_shift));
7947 }
7948} 3576}
7949 3577
7950void 3578u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio)
7951ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds,
7952 struct ath_desc *lastds,
7953 u32 durUpdateEn, u32 rtsctsRate,
7954 u32 rtsctsDuration,
7955 struct ath9k_11n_rate_series series[],
7956 u32 nseries, u32 flags)
7957{ 3579{
7958 struct ar5416_desc *ads = AR5416DESC(ds); 3580 if (gpio >= ah->ah_caps.num_gpio_pins)
7959 struct ar5416_desc *last_ads = AR5416DESC(lastds); 3581 return 0xffffffff;
7960 u32 ds_ctl0;
7961
7962 (void) nseries;
7963 (void) rtsctsDuration;
7964
7965 if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
7966 ds_ctl0 = ads->ds_ctl0;
7967
7968 if (flags & ATH9K_TXDESC_RTSENA) {
7969 ds_ctl0 &= ~AR_CTSEnable;
7970 ds_ctl0 |= AR_RTSEnable;
7971 } else {
7972 ds_ctl0 &= ~AR_RTSEnable;
7973 ds_ctl0 |= AR_CTSEnable;
7974 }
7975 3582
7976 ads->ds_ctl0 = ds_ctl0; 3583 if (AR_SREV_9280_10_OR_LATER(ah)) {
3584 return (MS
3585 (REG_READ(ah, AR_GPIO_IN_OUT),
3586 AR928X_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) != 0;
7977 } else { 3587 } else {
7978 ads->ds_ctl0 = 3588 return (MS(REG_READ(ah, AR_GPIO_IN_OUT), AR_GPIO_IN_VAL) &
7979 (ads->ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable)); 3589 AR_GPIO_BIT(gpio)) != 0;
7980 } 3590 }
7981
7982 ads->ds_ctl2 = set11nTries(series, 0)
7983 | set11nTries(series, 1)
7984 | set11nTries(series, 2)
7985 | set11nTries(series, 3)
7986 | (durUpdateEn ? AR_DurUpdateEna : 0)
7987 | SM(0, AR_BurstDur);
7988
7989 ads->ds_ctl3 = set11nRate(series, 0)
7990 | set11nRate(series, 1)
7991 | set11nRate(series, 2)
7992 | set11nRate(series, 3);
7993
7994 ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
7995 | set11nPktDurRTSCTS(series, 1);
7996
7997 ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
7998 | set11nPktDurRTSCTS(series, 3);
7999
8000 ads->ds_ctl7 = set11nRateFlags(series, 0)
8001 | set11nRateFlags(series, 1)
8002 | set11nRateFlags(series, 2)
8003 | set11nRateFlags(series, 3)
8004 | SM(rtsctsRate, AR_RTSCTSRate);
8005 last_ads->ds_ctl2 = ads->ds_ctl2;
8006 last_ads->ds_ctl3 = ads->ds_ctl3;
8007} 3591}
8008 3592
8009void 3593void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,
8010ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds, 3594 u32 ah_signal_type)
8011 u32 aggrLen)
8012{ 3595{
8013 struct ar5416_desc *ads = AR5416DESC(ds); 3596 u32 gpio_shift;
8014
8015 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
8016
8017 ads->ds_ctl6 &= ~AR_AggrLen;
8018 ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen);
8019}
8020 3597
8021void 3598 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
8022ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds,
8023 u32 numDelims)
8024{
8025 struct ar5416_desc *ads = AR5416DESC(ds);
8026 unsigned int ctl6;
8027 3599
8028 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr); 3600 gpio_shift = 2 * gpio;
8029 3601
8030 ctl6 = ads->ds_ctl6; 3602 REG_RMW(ah,
8031 ctl6 &= ~AR_PadDelim; 3603 AR_GPIO_OE_OUT,
8032 ctl6 |= SM(numDelims, AR_PadDelim); 3604 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
8033 ads->ds_ctl6 = ctl6; 3605 (AR_GPIO_OE_OUT_DRV << gpio_shift));
8034} 3606}
8035 3607
8036void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds) 3608void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val)
8037{ 3609{
8038 struct ar5416_desc *ads = AR5416DESC(ds); 3610 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
8039 3611 AR_GPIO_BIT(gpio));
8040 ads->ds_ctl1 |= AR_IsAggr;
8041 ads->ds_ctl1 &= ~AR_MoreAggr;
8042 ads->ds_ctl6 &= ~AR_PadDelim;
8043} 3612}
8044 3613
8045void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds) 3614#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3615void ath9k_enable_rfkill(struct ath_hal *ah)
8046{ 3616{
8047 struct ar5416_desc *ads = AR5416DESC(ds); 3617 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3618 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
8048 3619
8049 ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr); 3620 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
3621 AR_GPIO_INPUT_MUX2_RFSILENT);
3622
3623 ath9k_hw_cfg_gpio_input(ah, ah->ah_rfkill_gpio);
3624 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
8050} 3625}
3626#endif
8051 3627
8052void 3628int ath9k_hw_select_antconfig(struct ath_hal *ah, u32 cfg)
8053ath9k_hw_set11n_burstduration(struct ath_hal *ah, struct ath_desc *ds,
8054 u32 burstDuration)
8055{ 3629{
8056 struct ar5416_desc *ads = AR5416DESC(ds); 3630 struct ath9k_channel *chan = ah->ah_curchan;
3631 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3632 u16 ant_config;
3633 u32 halNumAntConfig;
8057 3634
8058 ads->ds_ctl2 &= ~AR_BurstDur; 3635 halNumAntConfig = IS_CHAN_2GHZ(chan) ?
8059 ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur); 3636 pCap->num_antcfg_2ghz : pCap->num_antcfg_5ghz;
8060}
8061 3637
8062void 3638 if (cfg < halNumAntConfig) {
8063ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah, struct ath_desc *ds, 3639 if (!ath9k_hw_get_eeprom_antenna_cfg(ah, chan,
8064 u32 vmf) 3640 cfg, &ant_config)) {
8065{ 3641 REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
8066 struct ar5416_desc *ads = AR5416DESC(ds); 3642 return 0;
3643 }
3644 }
8067 3645
8068 if (vmf) 3646 return -EINVAL;
8069 ads->ds_ctl0 |= AR_VirtMoreFrag;
8070 else
8071 ads->ds_ctl0 &= ~AR_VirtMoreFrag;
8072} 3647}
8073 3648
8074void ath9k_hw_putrxbuf(struct ath_hal *ah, u32 rxdp) 3649u32 ath9k_hw_getdefantenna(struct ath_hal *ah)
8075{ 3650{
8076 REG_WRITE(ah, AR_RXDP, rxdp); 3651 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
8077} 3652}
8078 3653
8079void ath9k_hw_rxena(struct ath_hal *ah) 3654void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna)
8080{ 3655{
8081 REG_WRITE(ah, AR_CR, AR_CR_RXE); 3656 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
8082} 3657}
8083 3658
8084bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set) 3659bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
3660 enum ath9k_ant_setting settings,
3661 struct ath9k_channel *chan,
3662 u8 *tx_chainmask,
3663 u8 *rx_chainmask,
3664 u8 *antenna_cfgd)
8085{ 3665{
8086 if (set) { 3666 struct ath_hal_5416 *ahp = AH5416(ah);
8087 3667 static u8 tx_chainmask_cfg, rx_chainmask_cfg;
8088 REG_SET_BIT(ah, AR_DIAG_SW,
8089 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
8090
8091 if (!ath9k_hw_wait
8092 (ah, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE, 0)) {
8093 u32 reg;
8094 3668
8095 REG_CLR_BIT(ah, AR_DIAG_SW, 3669 if (AR_SREV_9280(ah)) {
8096 (AR_DIAG_RX_DIS | 3670 if (!tx_chainmask_cfg) {
8097 AR_DIAG_RX_ABORT));
8098 3671
8099 reg = REG_READ(ah, AR_OBS_BUS_1); 3672 tx_chainmask_cfg = *tx_chainmask;
8100 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 3673 rx_chainmask_cfg = *rx_chainmask;
8101 "%s: rx failed to go idle in 10 ms RXSM=0x%x\n", 3674 }
8102 __func__, reg);
8103 3675
8104 return false; 3676 switch (settings) {
3677 case ATH9K_ANT_FIXED_A:
3678 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3679 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3680 *antenna_cfgd = true;
3681 break;
3682 case ATH9K_ANT_FIXED_B:
3683 if (ah->ah_caps.tx_chainmask >
3684 ATH9K_ANTENNA1_CHAINMASK) {
3685 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3686 }
3687 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3688 *antenna_cfgd = true;
3689 break;
3690 case ATH9K_ANT_VARIABLE:
3691 *tx_chainmask = tx_chainmask_cfg;
3692 *rx_chainmask = rx_chainmask_cfg;
3693 *antenna_cfgd = true;
3694 break;
3695 default:
3696 break;
8105 } 3697 }
8106 } else { 3698 } else {
8107 REG_CLR_BIT(ah, AR_DIAG_SW, 3699 ahp->ah_diversityControl = settings;
8108 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
8109 } 3700 }
8110 3701
8111 return true; 3702 return true;
8112} 3703}
8113 3704
8114void 3705/*********************/
8115ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0, 3706/* General Operation */
8116 u32 filter1) 3707/*********************/
8117{
8118 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
8119 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
8120}
8121 3708
8122bool 3709u32 ath9k_hw_getrxfilter(struct ath_hal *ah)
8123ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds,
8124 u32 size, u32 flags)
8125{ 3710{
8126 struct ar5416_desc *ads = AR5416DESC(ds); 3711 u32 bits = REG_READ(ah, AR_RX_FILTER);
8127 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 3712 u32 phybits = REG_READ(ah, AR_PHY_ERR);
8128 3713
8129 ads->ds_ctl1 = size & AR_BufLen; 3714 if (phybits & AR_PHY_ERR_RADAR)
8130 if (flags & ATH9K_RXDESC_INTREQ) 3715 bits |= ATH9K_RX_FILTER_PHYRADAR;
8131 ads->ds_ctl1 |= AR_RxIntrReq; 3716 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3717 bits |= ATH9K_RX_FILTER_PHYERR;
8132 3718
8133 ads->ds_rxstatus8 &= ~AR_RxDone; 3719 return bits;
8134 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
8135 memset(&(ads->u), 0, sizeof(ads->u));
8136 return true;
8137} 3720}
8138 3721
8139int 3722void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits)
8140ath9k_hw_rxprocdesc(struct ath_hal *ah, struct ath_desc *ds,
8141 u32 pa, struct ath_desc *nds, u64 tsf)
8142{ 3723{
8143 struct ar5416_desc ads; 3724 u32 phybits;
8144 struct ar5416_desc *adsp = AR5416DESC(ds);
8145
8146 if ((adsp->ds_rxstatus8 & AR_RxDone) == 0)
8147 return -EINPROGRESS;
8148
8149 ads.u.rx = adsp->u.rx;
8150
8151 ds->ds_rxstat.rs_status = 0;
8152 ds->ds_rxstat.rs_flags = 0;
8153 3725
8154 ds->ds_rxstat.rs_datalen = ads.ds_rxstatus1 & AR_DataLen; 3726 REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
8155 ds->ds_rxstat.rs_tstamp = ads.AR_RcvTimestamp; 3727 phybits = 0;
3728 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3729 phybits |= AR_PHY_ERR_RADAR;
3730 if (bits & ATH9K_RX_FILTER_PHYERR)
3731 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3732 REG_WRITE(ah, AR_PHY_ERR, phybits);
8156 3733
8157 ds->ds_rxstat.rs_rssi = MS(ads.ds_rxstatus4, AR_RxRSSICombined); 3734 if (phybits)
8158 ds->ds_rxstat.rs_rssi_ctl0 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt00); 3735 REG_WRITE(ah, AR_RXCFG,
8159 ds->ds_rxstat.rs_rssi_ctl1 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt01); 3736 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
8160 ds->ds_rxstat.rs_rssi_ctl2 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt02);
8161 ds->ds_rxstat.rs_rssi_ext0 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt10);
8162 ds->ds_rxstat.rs_rssi_ext1 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt11);
8163 ds->ds_rxstat.rs_rssi_ext2 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt12);
8164 if (ads.ds_rxstatus8 & AR_RxKeyIdxValid)
8165 ds->ds_rxstat.rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx);
8166 else 3737 else
8167 ds->ds_rxstat.rs_keyix = ATH9K_RXKEYIX_INVALID; 3738 REG_WRITE(ah, AR_RXCFG,
8168 3739 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
8169 ds->ds_rxstat.rs_rate = RXSTATUS_RATE(ah, (&ads));
8170 ds->ds_rxstat.rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0;
8171
8172 ds->ds_rxstat.rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
8173 ds->ds_rxstat.rs_moreaggr =
8174 (ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
8175 ds->ds_rxstat.rs_antenna = MS(ads.ds_rxstatus3, AR_RxAntenna);
8176 ds->ds_rxstat.rs_flags =
8177 (ads.ds_rxstatus3 & AR_GI) ? ATH9K_RX_GI : 0;
8178 ds->ds_rxstat.rs_flags |=
8179 (ads.ds_rxstatus3 & AR_2040) ? ATH9K_RX_2040 : 0;
8180
8181 if (ads.ds_rxstatus8 & AR_PreDelimCRCErr)
8182 ds->ds_rxstat.rs_flags |= ATH9K_RX_DELIM_CRC_PRE;
8183 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr)
8184 ds->ds_rxstat.rs_flags |= ATH9K_RX_DELIM_CRC_POST;
8185 if (ads.ds_rxstatus8 & AR_DecryptBusyErr)
8186 ds->ds_rxstat.rs_flags |= ATH9K_RX_DECRYPT_BUSY;
8187
8188 if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) {
8189
8190 if (ads.ds_rxstatus8 & AR_CRCErr)
8191 ds->ds_rxstat.rs_status |= ATH9K_RXERR_CRC;
8192 else if (ads.ds_rxstatus8 & AR_PHYErr) {
8193 u32 phyerr;
8194
8195 ds->ds_rxstat.rs_status |= ATH9K_RXERR_PHY;
8196 phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode);
8197 ds->ds_rxstat.rs_phyerr = phyerr;
8198 } else if (ads.ds_rxstatus8 & AR_DecryptCRCErr)
8199 ds->ds_rxstat.rs_status |= ATH9K_RXERR_DECRYPT;
8200 else if (ads.ds_rxstatus8 & AR_MichaelErr)
8201 ds->ds_rxstat.rs_status |= ATH9K_RXERR_MIC;
8202 }
8203
8204 return 0;
8205} 3740}
8206 3741
8207static void ath9k_hw_setup_rate_table(struct ath_hal *ah, 3742bool ath9k_hw_phy_disable(struct ath_hal *ah)
8208 struct ath9k_rate_table *rt)
8209{ 3743{
8210 int i; 3744 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
8211
8212 if (rt->rateCodeToIndex[0] != 0)
8213 return;
8214 for (i = 0; i < 256; i++)
8215 rt->rateCodeToIndex[i] = (u8) -1;
8216 for (i = 0; i < rt->rateCount; i++) {
8217 u8 code = rt->info[i].rateCode;
8218 u8 cix = rt->info[i].controlRate;
8219
8220 rt->rateCodeToIndex[code] = i;
8221 rt->rateCodeToIndex[code | rt->info[i].shortPreamble] = i;
8222
8223 rt->info[i].lpAckDuration =
8224 ath9k_hw_computetxtime(ah, rt,
8225 WLAN_CTRL_FRAME_SIZE,
8226 cix,
8227 false);
8228 rt->info[i].spAckDuration =
8229 ath9k_hw_computetxtime(ah, rt,
8230 WLAN_CTRL_FRAME_SIZE,
8231 cix,
8232 true);
8233 }
8234} 3745}
8235 3746
8236const struct ath9k_rate_table *ath9k_hw_getratetable(struct ath_hal *ah, 3747bool ath9k_hw_disable(struct ath_hal *ah)
8237 u32 mode)
8238{ 3748{
8239 struct ath9k_rate_table *rt; 3749 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
8240 switch (mode) { 3750 return false;
8241 case ATH9K_MODE_11A:
8242 rt = &ar5416_11a_table;
8243 break;
8244 case ATH9K_MODE_11B:
8245 rt = &ar5416_11b_table;
8246 break;
8247 case ATH9K_MODE_11G:
8248 rt = &ar5416_11g_table;
8249 break;
8250 case ATH9K_MODE_11NG_HT20:
8251 case ATH9K_MODE_11NG_HT40PLUS:
8252 case ATH9K_MODE_11NG_HT40MINUS:
8253 rt = &ar5416_11ng_table;
8254 break;
8255 case ATH9K_MODE_11NA_HT20:
8256 case ATH9K_MODE_11NA_HT40PLUS:
8257 case ATH9K_MODE_11NA_HT40MINUS:
8258 rt = &ar5416_11na_table;
8259 break;
8260 default:
8261 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, "%s: invalid mode 0x%x\n",
8262 __func__, mode);
8263 return NULL;
8264 }
8265 ath9k_hw_setup_rate_table(ah, rt);
8266 return rt;
8267}
8268 3751
8269static const char *ath9k_hw_devname(u16 devid) 3752 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
8270{
8271 switch (devid) {
8272 case AR5416_DEVID_PCI:
8273 case AR5416_DEVID_PCIE:
8274 return "Atheros 5416";
8275 case AR9160_DEVID_PCI:
8276 return "Atheros 9160";
8277 case AR9280_DEVID_PCI:
8278 case AR9280_DEVID_PCIE:
8279 return "Atheros 9280";
8280 }
8281 return NULL;
8282} 3753}
8283 3754
8284const char *ath9k_hw_probe(u16 vendorid, u16 devid) 3755bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit)
8285{ 3756{
8286 return vendorid == ATHEROS_VENDOR_ID ? 3757 struct ath9k_channel *chan = ah->ah_curchan;
8287 ath9k_hw_devname(devid) : NULL;
8288}
8289 3758
8290struct ath_hal *ath9k_hw_attach(u16 devid, 3759 ah->ah_powerLimit = min(limit, (u32) MAX_RATE_POWER);
8291 struct ath_softc *sc,
8292 void __iomem *mem,
8293 int *error)
8294{
8295 struct ath_hal *ah = NULL;
8296 3760
8297 switch (devid) { 3761 if (ath9k_hw_set_txpower(ah, chan,
8298 case AR5416_DEVID_PCI: 3762 ath9k_regd_get_ctl(ah, chan),
8299 case AR5416_DEVID_PCIE: 3763 ath9k_regd_get_antenna_allowed(ah, chan),
8300 case AR9160_DEVID_PCI: 3764 chan->maxRegTxPower * 2,
8301 case AR9280_DEVID_PCI: 3765 min((u32) MAX_RATE_POWER,
8302 case AR9280_DEVID_PCIE: 3766 (u32) ah->ah_powerLimit)) != 0)
8303 ah = ath9k_hw_do_attach(devid, sc, mem, error); 3767 return false;
8304 break;
8305 default:
8306 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
8307 "devid=0x%x not supported.\n", devid);
8308 ah = NULL;
8309 *error = -ENXIO;
8310 break;
8311 }
8312 3768
8313 return ah; 3769 return true;
8314} 3770}
8315 3771
8316u16 3772void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac)
8317ath9k_hw_computetxtime(struct ath_hal *ah,
8318 const struct ath9k_rate_table *rates,
8319 u32 frameLen, u16 rateix,
8320 bool shortPreamble)
8321{ 3773{
8322 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; 3774 struct ath_hal_5416 *ahp = AH5416(ah);
8323 u32 kbps;
8324
8325 kbps = rates->info[rateix].rateKbps;
8326
8327 if (kbps == 0)
8328 return 0;
8329 switch (rates->info[rateix].phy) {
8330
8331 case PHY_CCK:
8332 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
8333 if (shortPreamble && rates->info[rateix].shortPreamble)
8334 phyTime >>= 1;
8335 numBits = frameLen << 3;
8336 txTime = CCK_SIFS_TIME + phyTime
8337 + ((numBits * 1000) / kbps);
8338 break;
8339 case PHY_OFDM:
8340 if (ah->ah_curchan && IS_CHAN_QUARTER_RATE(ah->ah_curchan)) {
8341 bitsPerSymbol =
8342 (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
8343
8344 numBits = OFDM_PLCP_BITS + (frameLen << 3);
8345 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
8346 txTime = OFDM_SIFS_TIME_QUARTER
8347 + OFDM_PREAMBLE_TIME_QUARTER
8348 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
8349 } else if (ah->ah_curchan &&
8350 IS_CHAN_HALF_RATE(ah->ah_curchan)) {
8351 bitsPerSymbol =
8352 (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
8353
8354 numBits = OFDM_PLCP_BITS + (frameLen << 3);
8355 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
8356 txTime = OFDM_SIFS_TIME_HALF +
8357 OFDM_PREAMBLE_TIME_HALF
8358 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
8359 } else {
8360 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
8361
8362 numBits = OFDM_PLCP_BITS + (frameLen << 3);
8363 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
8364 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
8365 + (numSymbols * OFDM_SYMBOL_TIME);
8366 }
8367 break;
8368 3775
8369 default: 3776 memcpy(mac, ahp->ah_macaddr, ETH_ALEN);
8370 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
8371 "%s: unknown phy %u (rate ix %u)\n", __func__,
8372 rates->info[rateix].phy, rateix);
8373 txTime = 0;
8374 break;
8375 }
8376 return txTime;
8377} 3777}
8378 3778
8379u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags) 3779bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac)
8380{ 3780{
8381 if (flags & CHANNEL_2GHZ) { 3781 struct ath_hal_5416 *ahp = AH5416(ah);
8382 if (freq == 2484)
8383 return 14;
8384 if (freq < 2484)
8385 return (freq - 2407) / 5;
8386 else
8387 return 15 + ((freq - 2512) / 20);
8388 } else if (flags & CHANNEL_5GHZ) {
8389 if (ath9k_regd_is_public_safety_sku(ah) &&
8390 IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
8391 return ((freq * 10) +
8392 (((freq % 5) == 2) ? 5 : 0) - 49400) / 5;
8393 } else if ((flags & CHANNEL_A) && (freq <= 5000)) {
8394 return (freq - 4000) / 5;
8395 } else {
8396 return (freq - 5000) / 5;
8397 }
8398 } else {
8399 if (freq == 2484)
8400 return 14;
8401 if (freq < 2484)
8402 return (freq - 2407) / 5;
8403 if (freq < 5000) {
8404 if (ath9k_regd_is_public_safety_sku(ah)
8405 && IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
8406 return ((freq * 10) +
8407 (((freq % 5) ==
8408 2) ? 5 : 0) - 49400) / 5;
8409 } else if (freq > 4900) {
8410 return (freq - 4000) / 5;
8411 } else {
8412 return 15 + ((freq - 2512) / 20);
8413 }
8414 }
8415 return (freq - 5000) / 5;
8416 }
8417}
8418 3782
8419/* We can tune this as we go by monitoring really low values */ 3783 memcpy(ahp->ah_macaddr, mac, ETH_ALEN);
8420#define ATH9K_NF_TOO_LOW -60
8421 3784
8422/* AR5416 may return very high value (like -31 dBm), in those cases the nf
8423 * is incorrect and we should use the static NF value. Later we can try to
8424 * find out why they are reporting these values */
8425static bool ath9k_hw_nf_in_range(struct ath_hal *ah, s16 nf)
8426{
8427 if (nf > ATH9K_NF_TOO_LOW) {
8428 DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
8429 "%s: noise floor value detected (%d) is "
8430 "lower than what we think is a "
8431 "reasonable value (%d)\n",
8432 __func__, nf, ATH9K_NF_TOO_LOW);
8433 return false;
8434 }
8435 return true; 3785 return true;
8436} 3786}
8437 3787
8438s16 3788void ath9k_hw_setopmode(struct ath_hal *ah)
8439ath9k_hw_getchan_noise(struct ath_hal *ah, struct ath9k_channel *chan)
8440{ 3789{
8441 struct ath9k_channel *ichan; 3790 ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
8442 s16 nf;
8443
8444 ichan = ath9k_regd_check_channel(ah, chan);
8445 if (ichan == NULL) {
8446 DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
8447 "%s: invalid channel %u/0x%x; no mapping\n",
8448 __func__, chan->channel, chan->channelFlags);
8449 return ATH_DEFAULT_NOISE_FLOOR;
8450 }
8451 if (ichan->rawNoiseFloor == 0) {
8452 enum wireless_mode mode = ath9k_hw_chan2wmode(ah, chan);
8453 nf = NOISE_FLOOR[mode];
8454 } else
8455 nf = ichan->rawNoiseFloor;
8456
8457 if (!ath9k_hw_nf_in_range(ah, nf))
8458 nf = ATH_DEFAULT_NOISE_FLOOR;
8459
8460 return nf;
8461} 3791}
8462 3792
8463bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting) 3793void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0, u32 filter1)
8464{ 3794{
8465 struct ath_hal_5416 *ahp = AH5416(ah); 3795 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
8466 3796 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
8467 if (setting)
8468 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
8469 else
8470 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
8471 return true;
8472} 3797}
8473 3798
8474bool ath9k_hw_phycounters(struct ath_hal *ah) 3799void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask)
8475{ 3800{
8476 struct ath_hal_5416 *ahp = AH5416(ah); 3801 struct ath_hal_5416 *ahp = AH5416(ah);
8477 3802
8478 return ahp->ah_hasHwPhyCounters ? true : false; 3803 memcpy(mask, ahp->ah_bssidmask, ETH_ALEN);
8479} 3804}
8480 3805
8481u32 ath9k_hw_gettxbuf(struct ath_hal *ah, u32 q) 3806bool ath9k_hw_setbssidmask(struct ath_hal *ah, const u8 *mask)
8482{ 3807{
8483 return REG_READ(ah, AR_QTXDP(q)); 3808 struct ath_hal_5416 *ahp = AH5416(ah);
8484}
8485 3809
8486bool ath9k_hw_puttxbuf(struct ath_hal *ah, u32 q, 3810 memcpy(ahp->ah_bssidmask, mask, ETH_ALEN);
8487 u32 txdp) 3811
8488{ 3812 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));
8489 REG_WRITE(ah, AR_QTXDP(q), txdp); 3813 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
8490 3814
8491 return true; 3815 return true;
8492} 3816}
8493 3817
8494bool ath9k_hw_txstart(struct ath_hal *ah, u32 q) 3818void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid, u16 assocId)
8495{ 3819{
8496 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: queue %u\n", __func__, q); 3820 struct ath_hal_5416 *ahp = AH5416(ah);
8497 3821
8498 REG_WRITE(ah, AR_Q_TXE, 1 << q); 3822 memcpy(ahp->ah_bssid, bssid, ETH_ALEN);
3823 ahp->ah_assocId = assocId;
8499 3824
8500 return true; 3825 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
3826 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
3827 ((assocId & 0x3fff) << AR_BSS_ID1_AID_S));
8501} 3828}
8502 3829
8503u32 ath9k_hw_numtxpending(struct ath_hal *ah, u32 q) 3830u64 ath9k_hw_gettsf64(struct ath_hal *ah)
8504{ 3831{
8505 u32 npend; 3832 u64 tsf;
8506 3833
8507 npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT; 3834 tsf = REG_READ(ah, AR_TSF_U32);
8508 if (npend == 0) { 3835 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
8509 3836
8510 if (REG_READ(ah, AR_Q_TXE) & (1 << q)) 3837 return tsf;
8511 npend = 1;
8512 }
8513 return npend;
8514} 3838}
8515 3839
8516bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q) 3840void ath9k_hw_reset_tsf(struct ath_hal *ah)
8517{ 3841{
8518 u32 wait; 3842 int count;
8519
8520 REG_WRITE(ah, AR_Q_TXD, 1 << q);
8521 3843
8522 for (wait = 1000; wait != 0; wait--) { 3844 count = 0;
8523 if (ath9k_hw_numtxpending(ah, q) == 0) 3845 while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
3846 count++;
3847 if (count > 10) {
3848 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3849 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
8524 break; 3850 break;
8525 udelay(100); 3851 }
3852 udelay(10);
8526 } 3853 }
3854 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3855}
8527 3856
8528 if (ath9k_hw_numtxpending(ah, q)) { 3857bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting)
8529 u32 tsfLow, j; 3858{
8530 3859 struct ath_hal_5416 *ahp = AH5416(ah);
8531 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
8532 "%s: Num of pending TX Frames %d on Q %d\n",
8533 __func__, ath9k_hw_numtxpending(ah, q), q);
8534
8535 for (j = 0; j < 2; j++) {
8536 tsfLow = REG_READ(ah, AR_TSF_L32);
8537 REG_WRITE(ah, AR_QUIET2,
8538 SM(10, AR_QUIET2_QUIET_DUR));
8539 REG_WRITE(ah, AR_QUIET_PERIOD, 100);
8540 REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsfLow >> 10);
8541 REG_SET_BIT(ah, AR_TIMER_MODE,
8542 AR_QUIET_TIMER_EN);
8543 3860
8544 if ((REG_READ(ah, AR_TSF_L32) >> 10) == 3861 if (setting)
8545 (tsfLow >> 10)) { 3862 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
8546 break; 3863 else
8547 } 3864 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
8548 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
8549 "%s: TSF have moved while trying to set "
8550 "quiet time TSF: 0x%08x\n",
8551 __func__, tsfLow);
8552 }
8553 3865
8554 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 3866 return true;
3867}
8555 3868
8556 udelay(200); 3869bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us)
8557 REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 3870{
3871 struct ath_hal_5416 *ahp = AH5416(ah);
8558 3872
8559 wait = 1000; 3873 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3874 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
3875 ahp->ah_slottime = (u32) -1;
3876 return false;
3877 } else {
3878 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3879 ahp->ah_slottime = us;
3880 return true;
3881 }
3882}
8560 3883
8561 while (ath9k_hw_numtxpending(ah, q)) { 3884void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode)
8562 if ((--wait) == 0) { 3885{
8563 DPRINTF(ah->ah_sc, ATH_DBG_XMIT, 3886 u32 macmode;
8564 "%s: Failed to stop Tx DMA in 100 "
8565 "msec after killing last frame\n",
8566 __func__);
8567 break;
8568 }
8569 udelay(100);
8570 }
8571 3887
8572 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 3888 if (mode == ATH9K_HT_MACMODE_2040 &&
8573 } 3889 !ah->ah_config.cwm_ignore_extcca)
3890 macmode = AR_2040_JOINED_RX_CLEAR;
3891 else
3892 macmode = 0;
8574 3893
8575 REG_WRITE(ah, AR_Q_TXD, 0); 3894 REG_WRITE(ah, AR_2040_MODE, macmode);
8576 return wait != 0;
8577} 3895}
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-20 02:51:55 -0400