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path: root/drivers/net/wireless/ath9k/eeprom.c
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Diffstat (limited to 'drivers/net/wireless/ath9k/eeprom.c')
-rw-r--r--drivers/net/wireless/ath9k/eeprom.c308
1 files changed, 126 insertions, 182 deletions
diff --git a/drivers/net/wireless/ath9k/eeprom.c b/drivers/net/wireless/ath9k/eeprom.c
index 183c949bcca1..ffc36b0361c7 100644
--- a/drivers/net/wireless/ath9k/eeprom.c
+++ b/drivers/net/wireless/ath9k/eeprom.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2008 Atheros Communications Inc. 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 * 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any 4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above 5 * purpose with or without fee is hereby granted, provided that the above
@@ -342,8 +342,7 @@ static int ath9k_hw_4k_get_eeprom_rev(struct ath_hw *ah)
342static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah) 342static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
343{ 343{
344#define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16)) 344#define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
345 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k; 345 u16 *eep_data = (u16 *)&ah->eeprom.map4k;
346 u16 *eep_data;
347 int addr, eep_start_loc = 0; 346 int addr, eep_start_loc = 0;
348 347
349 eep_start_loc = 64; 348 eep_start_loc = 64;
@@ -353,8 +352,6 @@ static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
353 "Reading from EEPROM, not flash\n"); 352 "Reading from EEPROM, not flash\n");
354 } 353 }
355 354
356 eep_data = (u16 *)eep;
357
358 for (addr = 0; addr < SIZE_EEPROM_4K; addr++) { 355 for (addr = 0; addr < SIZE_EEPROM_4K; addr++) {
359 if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data)) { 356 if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data)) {
360 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 357 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
@@ -363,6 +360,7 @@ static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
363 } 360 }
364 eep_data++; 361 eep_data++;
365 } 362 }
363
366 return true; 364 return true;
367#undef SIZE_EEPROM_4K 365#undef SIZE_EEPROM_4K
368} 366}
@@ -379,16 +377,15 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
379 377
380 378
381 if (!ath9k_hw_use_flash(ah)) { 379 if (!ath9k_hw_use_flash(ah)) {
382
383 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET, 380 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
384 &magic)) { 381 &magic)) {
385 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 382 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
386 "Reading Magic # failed\n"); 383 "Reading Magic # failed\n");
387 return false; 384 return false;
388 } 385 }
389 386
390 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 387 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
391 "Read Magic = 0x%04X\n", magic); 388 "Read Magic = 0x%04X\n", magic);
392 389
393 if (magic != AR5416_EEPROM_MAGIC) { 390 if (magic != AR5416_EEPROM_MAGIC) {
394 magic2 = swab16(magic); 391 magic2 = swab16(magic);
@@ -401,16 +398,9 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
401 temp = swab16(*eepdata); 398 temp = swab16(*eepdata);
402 *eepdata = temp; 399 *eepdata = temp;
403 eepdata++; 400 eepdata++;
404
405 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
406 "0x%04X ", *eepdata);
407
408 if (((addr + 1) % 6) == 0)
409 DPRINTF(ah->ah_sc,
410 ATH_DBG_EEPROM, "\n");
411 } 401 }
412 } else { 402 } else {
413 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 403 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
414 "Invalid EEPROM Magic. " 404 "Invalid EEPROM Magic. "
415 "endianness mismatch.\n"); 405 "endianness mismatch.\n");
416 return -EINVAL; 406 return -EINVAL;
@@ -426,7 +416,7 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
426 else 416 else
427 el = ah->eeprom.map4k.baseEepHeader.length; 417 el = ah->eeprom.map4k.baseEepHeader.length;
428 418
429 if (el > sizeof(struct ar5416_eeprom_def)) 419 if (el > sizeof(struct ar5416_eeprom_4k))
430 el = sizeof(struct ar5416_eeprom_4k) / sizeof(u16); 420 el = sizeof(struct ar5416_eeprom_4k) / sizeof(u16);
431 else 421 else
432 el = el / sizeof(u16); 422 el = el / sizeof(u16);
@@ -441,7 +431,7 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
441 u16 word; 431 u16 word;
442 432
443 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 433 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
444 "EEPROM Endianness is not native.. Changing \n"); 434 "EEPROM Endianness is not native.. Changing\n");
445 435
446 word = swab16(eep->baseEepHeader.length); 436 word = swab16(eep->baseEepHeader.length);
447 eep->baseEepHeader.length = word; 437 eep->baseEepHeader.length = word;
@@ -483,7 +473,7 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
483 473
484 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER || 474 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
485 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) { 475 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
486 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 476 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
487 "Bad EEPROM checksum 0x%x or revision 0x%04x\n", 477 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
488 sum, ah->eep_ops->get_eeprom_ver(ah)); 478 sum, ah->eep_ops->get_eeprom_ver(ah));
489 return -EINVAL; 479 return -EINVAL;
@@ -1203,57 +1193,63 @@ static void ath9k_hw_4k_set_addac(struct ath_hw *ah,
1203 } 1193 }
1204} 1194}
1205 1195
1206static bool ath9k_hw_4k_set_board_values(struct ath_hw *ah, 1196static void ath9k_hw_4k_set_gain(struct ath_hw *ah,
1207 struct ath9k_channel *chan) 1197 struct modal_eep_4k_header *pModal,
1198 struct ar5416_eeprom_4k *eep,
1199 u8 txRxAttenLocal, int regChainOffset)
1208{ 1200{
1209 struct modal_eep_4k_header *pModal;
1210 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
1211 int regChainOffset;
1212 u8 txRxAttenLocal;
1213 u8 ob[5], db1[5], db2[5];
1214 u8 ant_div_control1, ant_div_control2;
1215 u32 regVal;
1216
1217
1218 pModal = &eep->modalHeader;
1219
1220 txRxAttenLocal = 23;
1221
1222 REG_WRITE(ah, AR_PHY_SWITCH_COM,
1223 ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
1224
1225 regChainOffset = 0;
1226 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset, 1201 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
1227 pModal->antCtrlChain[0]); 1202 pModal->antCtrlChain[0]);
1228 1203
1229 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset, 1204 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
1230 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) & 1205 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) &
1231 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | 1206 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
1232 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) | 1207 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
1233 SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | 1208 SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
1234 SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); 1209 SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
1235 1210
1236 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 1211 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1237 AR5416_EEP_MINOR_VER_3) { 1212 AR5416_EEP_MINOR_VER_3) {
1238 txRxAttenLocal = pModal->txRxAttenCh[0]; 1213 txRxAttenLocal = pModal->txRxAttenCh[0];
1214
1239 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 1215 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1240 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]); 1216 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]);
1241 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 1217 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1242 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]); 1218 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
1243 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 1219 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1244 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, 1220 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
1245 pModal->xatten2Margin[0]); 1221 pModal->xatten2Margin[0]);
1246 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 1222 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1247 AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]); 1223 AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]);
1248 } 1224 }
1249 1225
1250 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset, 1226 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
1251 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); 1227 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
1252 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset, 1228 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
1253 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]); 1229 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
1254 1230
1255 if (AR_SREV_9285_11(ah)) 1231 if (AR_SREV_9285_11(ah))
1256 REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14)); 1232 REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
1233}
1234
1235static void ath9k_hw_4k_set_board_values(struct ath_hw *ah,
1236 struct ath9k_channel *chan)
1237{
1238 struct modal_eep_4k_header *pModal;
1239 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
1240 u8 txRxAttenLocal;
1241 u8 ob[5], db1[5], db2[5];
1242 u8 ant_div_control1, ant_div_control2;
1243 u32 regVal;
1244
1245 pModal = &eep->modalHeader;
1246 txRxAttenLocal = 23;
1247
1248 REG_WRITE(ah, AR_PHY_SWITCH_COM,
1249 ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
1250
1251 /* Single chain for 4K EEPROM*/
1252 ath9k_hw_4k_set_gain(ah, pModal, eep, txRxAttenLocal, 0);
1257 1253
1258 /* Initialize Ant Diversity settings from EEPROM */ 1254 /* Initialize Ant Diversity settings from EEPROM */
1259 if (pModal->version == 3) { 1255 if (pModal->version == 3) {
@@ -1295,9 +1291,6 @@ static bool ath9k_hw_4k_set_board_values(struct ath_hw *ah,
1295 db2[4] = ((pModal->db2_234 >> 8) & 0xf); 1291 db2[4] = ((pModal->db2_234 >> 8) & 0xf);
1296 1292
1297 } else if (pModal->version == 1) { 1293 } else if (pModal->version == 1) {
1298
1299 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1300 "EEPROM Model version is set to 1 \n");
1301 ob[0] = (pModal->ob_01 & 0xf); 1294 ob[0] = (pModal->ob_01 & 0xf);
1302 ob[1] = ob[2] = ob[3] = ob[4] = (pModal->ob_01 >> 4) & 0xf; 1295 ob[1] = ob[2] = ob[3] = ob[4] = (pModal->ob_01 >> 4) & 0xf;
1303 db1[0] = (pModal->db1_01 & 0xf); 1296 db1[0] = (pModal->db1_01 & 0xf);
@@ -1385,8 +1378,6 @@ static bool ath9k_hw_4k_set_board_values(struct ath_hw *ah,
1385 AR_PHY_SETTLING_SWITCH, 1378 AR_PHY_SETTLING_SWITCH,
1386 pModal->swSettleHt40); 1379 pModal->swSettleHt40);
1387 } 1380 }
1388
1389 return true;
1390} 1381}
1391 1382
1392static u16 ath9k_hw_4k_get_eeprom_antenna_cfg(struct ath_hw *ah, 1383static u16 ath9k_hw_4k_get_eeprom_antenna_cfg(struct ath_hw *ah,
@@ -1464,16 +1455,13 @@ static int ath9k_hw_def_get_eeprom_rev(struct ath_hw *ah)
1464static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah) 1455static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
1465{ 1456{
1466#define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16)) 1457#define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16))
1467 struct ar5416_eeprom_def *eep = &ah->eeprom.def; 1458 u16 *eep_data = (u16 *)&ah->eeprom.def;
1468 u16 *eep_data;
1469 int addr, ar5416_eep_start_loc = 0x100; 1459 int addr, ar5416_eep_start_loc = 0x100;
1470 1460
1471 eep_data = (u16 *)eep;
1472
1473 for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) { 1461 for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) {
1474 if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc, 1462 if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc,
1475 eep_data)) { 1463 eep_data)) {
1476 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 1464 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1477 "Unable to read eeprom region\n"); 1465 "Unable to read eeprom region\n");
1478 return false; 1466 return false;
1479 } 1467 }
@@ -1492,17 +1480,14 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
1492 bool need_swap = false; 1480 bool need_swap = false;
1493 int i, addr, size; 1481 int i, addr, size;
1494 1482
1495 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET, 1483 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
1496 &magic)) { 1484 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Reading Magic # failed\n");
1497 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1498 "Reading Magic # failed\n");
1499 return false; 1485 return false;
1500 } 1486 }
1501 1487
1502 if (!ath9k_hw_use_flash(ah)) { 1488 if (!ath9k_hw_use_flash(ah)) {
1503
1504 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 1489 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1505 "Read Magic = 0x%04X\n", magic); 1490 "Read Magic = 0x%04X\n", magic);
1506 1491
1507 if (magic != AR5416_EEPROM_MAGIC) { 1492 if (magic != AR5416_EEPROM_MAGIC) {
1508 magic2 = swab16(magic); 1493 magic2 = swab16(magic);
@@ -1516,18 +1501,11 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
1516 temp = swab16(*eepdata); 1501 temp = swab16(*eepdata);
1517 *eepdata = temp; 1502 *eepdata = temp;
1518 eepdata++; 1503 eepdata++;
1519
1520 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1521 "0x%04X ", *eepdata);
1522
1523 if (((addr + 1) % 6) == 0)
1524 DPRINTF(ah->ah_sc,
1525 ATH_DBG_EEPROM, "\n");
1526 } 1504 }
1527 } else { 1505 } else {
1528 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 1506 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1529 "Invalid EEPROM Magic. " 1507 "Invalid EEPROM Magic. "
1530 "endianness mismatch.\n"); 1508 "Endianness mismatch.\n");
1531 return -EINVAL; 1509 return -EINVAL;
1532 } 1510 }
1533 } 1511 }
@@ -1556,7 +1534,7 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
1556 u16 word; 1534 u16 word;
1557 1535
1558 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 1536 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1559 "EEPROM Endianness is not native.. Changing \n"); 1537 "EEPROM Endianness is not native.. Changing.\n");
1560 1538
1561 word = swab16(eep->baseEepHeader.length); 1539 word = swab16(eep->baseEepHeader.length);
1562 eep->baseEepHeader.length = word; 1540 eep->baseEepHeader.length = word;
@@ -1602,7 +1580,7 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
1602 1580
1603 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER || 1581 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
1604 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) { 1582 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
1605 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 1583 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1606 "Bad EEPROM checksum 0x%x or revision 0x%04x\n", 1584 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
1607 sum, ah->eep_ops->get_eeprom_ver(ah)); 1585 sum, ah->eep_ops->get_eeprom_ver(ah));
1608 return -EINVAL; 1586 return -EINVAL;
@@ -1614,7 +1592,6 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
1614static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah, 1592static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
1615 enum eeprom_param param) 1593 enum eeprom_param param)
1616{ 1594{
1617#define AR5416_VER_MASK (pBase->version & AR5416_EEP_VER_MINOR_MASK)
1618 struct ar5416_eeprom_def *eep = &ah->eeprom.def; 1595 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1619 struct modal_eep_header *pModal = eep->modalHeader; 1596 struct modal_eep_header *pModal = eep->modalHeader;
1620 struct base_eep_header *pBase = &eep->baseEepHeader; 1597 struct base_eep_header *pBase = &eep->baseEepHeader;
@@ -1681,21 +1658,73 @@ static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
1681 default: 1658 default:
1682 return 0; 1659 return 0;
1683 } 1660 }
1684#undef AR5416_VER_MASK
1685} 1661}
1686 1662
1687/* XXX: Clean me up, make me more legible */ 1663static void ath9k_hw_def_set_gain(struct ath_hw *ah,
1688static bool ath9k_hw_def_set_board_values(struct ath_hw *ah, 1664 struct modal_eep_header *pModal,
1665 struct ar5416_eeprom_def *eep,
1666 u8 txRxAttenLocal, int regChainOffset, int i)
1667{
1668 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
1669 txRxAttenLocal = pModal->txRxAttenCh[i];
1670
1671 if (AR_SREV_9280_10_OR_LATER(ah)) {
1672 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1673 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
1674 pModal->bswMargin[i]);
1675 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1676 AR_PHY_GAIN_2GHZ_XATTEN1_DB,
1677 pModal->bswAtten[i]);
1678 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1679 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
1680 pModal->xatten2Margin[i]);
1681 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1682 AR_PHY_GAIN_2GHZ_XATTEN2_DB,
1683 pModal->xatten2Db[i]);
1684 } else {
1685 REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1686 (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
1687 ~AR_PHY_GAIN_2GHZ_BSW_MARGIN)
1688 | SM(pModal-> bswMargin[i],
1689 AR_PHY_GAIN_2GHZ_BSW_MARGIN));
1690 REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1691 (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
1692 ~AR_PHY_GAIN_2GHZ_BSW_ATTEN)
1693 | SM(pModal->bswAtten[i],
1694 AR_PHY_GAIN_2GHZ_BSW_ATTEN));
1695 }
1696 }
1697
1698 if (AR_SREV_9280_10_OR_LATER(ah)) {
1699 REG_RMW_FIELD(ah,
1700 AR_PHY_RXGAIN + regChainOffset,
1701 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
1702 REG_RMW_FIELD(ah,
1703 AR_PHY_RXGAIN + regChainOffset,
1704 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[i]);
1705 } else {
1706 REG_WRITE(ah,
1707 AR_PHY_RXGAIN + regChainOffset,
1708 (REG_READ(ah, AR_PHY_RXGAIN + regChainOffset) &
1709 ~AR_PHY_RXGAIN_TXRX_ATTEN)
1710 | SM(txRxAttenLocal, AR_PHY_RXGAIN_TXRX_ATTEN));
1711 REG_WRITE(ah,
1712 AR_PHY_GAIN_2GHZ + regChainOffset,
1713 (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
1714 ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
1715 SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
1716 }
1717}
1718
1719static void ath9k_hw_def_set_board_values(struct ath_hw *ah,
1689 struct ath9k_channel *chan) 1720 struct ath9k_channel *chan)
1690{ 1721{
1691#define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK)
1692 struct modal_eep_header *pModal; 1722 struct modal_eep_header *pModal;
1693 struct ar5416_eeprom_def *eep = &ah->eeprom.def; 1723 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1694 int i, regChainOffset; 1724 int i, regChainOffset;
1695 u8 txRxAttenLocal; 1725 u8 txRxAttenLocal;
1696 1726
1697 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]); 1727 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
1698
1699 txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44; 1728 txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44;
1700 1729
1701 REG_WRITE(ah, AR_PHY_SWITCH_COM, 1730 REG_WRITE(ah, AR_PHY_SWITCH_COM,
@@ -1708,8 +1737,7 @@ static bool ath9k_hw_def_set_board_values(struct ath_hw *ah,
1708 } 1737 }
1709 1738
1710 if (AR_SREV_5416_20_OR_LATER(ah) && 1739 if (AR_SREV_5416_20_OR_LATER(ah) &&
1711 (ah->rxchainmask == 5 || ah->txchainmask == 5) 1740 (ah->rxchainmask == 5 || ah->txchainmask == 5) && (i != 0))
1712 && (i != 0))
1713 regChainOffset = (i == 1) ? 0x2000 : 0x1000; 1741 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
1714 else 1742 else
1715 regChainOffset = i * 0x1000; 1743 regChainOffset = i * 0x1000;
@@ -1718,9 +1746,7 @@ static bool ath9k_hw_def_set_board_values(struct ath_hw *ah,
1718 pModal->antCtrlChain[i]); 1746 pModal->antCtrlChain[i]);
1719 1747
1720 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset, 1748 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
1721 (REG_READ(ah, 1749 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) &
1722 AR_PHY_TIMING_CTRL4(0) +
1723 regChainOffset) &
1724 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | 1750 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
1725 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) | 1751 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
1726 SM(pModal->iqCalICh[i], 1752 SM(pModal->iqCalICh[i],
@@ -1728,87 +1754,9 @@ static bool ath9k_hw_def_set_board_values(struct ath_hw *ah,
1728 SM(pModal->iqCalQCh[i], 1754 SM(pModal->iqCalQCh[i],
1729 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); 1755 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
1730 1756
1731 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) { 1757 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah))
1732 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) { 1758 ath9k_hw_def_set_gain(ah, pModal, eep, txRxAttenLocal,
1733 txRxAttenLocal = pModal->txRxAttenCh[i]; 1759 regChainOffset, i);
1734 if (AR_SREV_9280_10_OR_LATER(ah)) {
1735 REG_RMW_FIELD(ah,
1736 AR_PHY_GAIN_2GHZ +
1737 regChainOffset,
1738 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
1739 pModal->
1740 bswMargin[i]);
1741 REG_RMW_FIELD(ah,
1742 AR_PHY_GAIN_2GHZ +
1743 regChainOffset,
1744 AR_PHY_GAIN_2GHZ_XATTEN1_DB,
1745 pModal->
1746 bswAtten[i]);
1747 REG_RMW_FIELD(ah,
1748 AR_PHY_GAIN_2GHZ +
1749 regChainOffset,
1750 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
1751 pModal->
1752 xatten2Margin[i]);
1753 REG_RMW_FIELD(ah,
1754 AR_PHY_GAIN_2GHZ +
1755 regChainOffset,
1756 AR_PHY_GAIN_2GHZ_XATTEN2_DB,
1757 pModal->
1758 xatten2Db[i]);
1759 } else {
1760 REG_WRITE(ah,
1761 AR_PHY_GAIN_2GHZ +
1762 regChainOffset,
1763 (REG_READ(ah,
1764 AR_PHY_GAIN_2GHZ +
1765 regChainOffset) &
1766 ~AR_PHY_GAIN_2GHZ_BSW_MARGIN)
1767 | SM(pModal->
1768 bswMargin[i],
1769 AR_PHY_GAIN_2GHZ_BSW_MARGIN));
1770 REG_WRITE(ah,
1771 AR_PHY_GAIN_2GHZ +
1772 regChainOffset,
1773 (REG_READ(ah,
1774 AR_PHY_GAIN_2GHZ +
1775 regChainOffset) &
1776 ~AR_PHY_GAIN_2GHZ_BSW_ATTEN)
1777 | SM(pModal->bswAtten[i],
1778 AR_PHY_GAIN_2GHZ_BSW_ATTEN));
1779 }
1780 }
1781 if (AR_SREV_9280_10_OR_LATER(ah)) {
1782 REG_RMW_FIELD(ah,
1783 AR_PHY_RXGAIN +
1784 regChainOffset,
1785 AR9280_PHY_RXGAIN_TXRX_ATTEN,
1786 txRxAttenLocal);
1787 REG_RMW_FIELD(ah,
1788 AR_PHY_RXGAIN +
1789 regChainOffset,
1790 AR9280_PHY_RXGAIN_TXRX_MARGIN,
1791 pModal->rxTxMarginCh[i]);
1792 } else {
1793 REG_WRITE(ah,
1794 AR_PHY_RXGAIN + regChainOffset,
1795 (REG_READ(ah,
1796 AR_PHY_RXGAIN +
1797 regChainOffset) &
1798 ~AR_PHY_RXGAIN_TXRX_ATTEN) |
1799 SM(txRxAttenLocal,
1800 AR_PHY_RXGAIN_TXRX_ATTEN));
1801 REG_WRITE(ah,
1802 AR_PHY_GAIN_2GHZ +
1803 regChainOffset,
1804 (REG_READ(ah,
1805 AR_PHY_GAIN_2GHZ +
1806 regChainOffset) &
1807 ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
1808 SM(pModal->rxTxMarginCh[i],
1809 AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
1810 }
1811 }
1812 } 1760 }
1813 1761
1814 if (AR_SREV_9280_10_OR_LATER(ah)) { 1762 if (AR_SREV_9280_10_OR_LATER(ah)) {
@@ -1855,8 +1803,6 @@ static bool ath9k_hw_def_set_board_values(struct ath_hw *ah,
1855 AR_AN_TOP2_LOCALBIAS, 1803 AR_AN_TOP2_LOCALBIAS,
1856 AR_AN_TOP2_LOCALBIAS_S, 1804 AR_AN_TOP2_LOCALBIAS_S,
1857 pModal->local_bias); 1805 pModal->local_bias);
1858 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "ForceXPAon: %d\n",
1859 pModal->force_xpaon);
1860 REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG, 1806 REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
1861 pModal->force_xpaon); 1807 pModal->force_xpaon);
1862 } 1808 }
@@ -1882,6 +1828,7 @@ static bool ath9k_hw_def_set_board_values(struct ath_hw *ah,
1882 1828
1883 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, 1829 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
1884 pModal->txEndToRxOn); 1830 pModal->txEndToRxOn);
1831
1885 if (AR_SREV_9280_10_OR_LATER(ah)) { 1832 if (AR_SREV_9280_10_OR_LATER(ah)) {
1886 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62, 1833 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
1887 pModal->thresh62); 1834 pModal->thresh62);
@@ -1912,10 +1859,10 @@ static bool ath9k_hw_def_set_board_values(struct ath_hw *ah,
1912 } 1859 }
1913 1860
1914 if (AR_SREV_9280_20_OR_LATER(ah) && 1861 if (AR_SREV_9280_20_OR_LATER(ah) &&
1915 AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19) 1862 AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
1916 REG_RMW_FIELD(ah, AR_PHY_CCK_TX_CTRL, 1863 REG_RMW_FIELD(ah, AR_PHY_CCK_TX_CTRL,
1917 AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK, 1864 AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK,
1918 pModal->miscBits); 1865 pModal->miscBits);
1919 1866
1920 1867
1921 if (AR_SREV_9280_20(ah) && AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20) { 1868 if (AR_SREV_9280_20(ah) && AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20) {
@@ -1926,18 +1873,15 @@ static bool ath9k_hw_def_set_board_values(struct ath_hw *ah,
1926 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 0); 1873 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 0);
1927 else 1874 else
1928 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 1875 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
1929 eep->baseEepHeader.dacLpMode); 1876 eep->baseEepHeader.dacLpMode);
1930 1877
1931 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP, 1878 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP,
1932 pModal->miscBits >> 2); 1879 pModal->miscBits >> 2);
1933 1880
1934 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL9, 1881 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL9,
1935 AR_PHY_TX_DESIRED_SCALE_CCK, 1882 AR_PHY_TX_DESIRED_SCALE_CCK,
1936 eep->baseEepHeader.desiredScaleCCK); 1883 eep->baseEepHeader.desiredScaleCCK);
1937 } 1884 }
1938
1939 return true;
1940#undef AR5416_VER_MASK
1941} 1885}
1942 1886
1943static void ath9k_hw_def_set_addac(struct ath_hw *ah, 1887static void ath9k_hw_def_set_addac(struct ath_hw *ah,
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-03 21:12:10 -0500