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path: root/drivers/net/wireless/ath9k/calib.c
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Diffstat (limited to 'drivers/net/wireless/ath9k/calib.c')
-rw-r--r--drivers/net/wireless/ath9k/calib.c175
1 files changed, 80 insertions, 95 deletions
diff --git a/drivers/net/wireless/ath9k/calib.c b/drivers/net/wireless/ath9k/calib.c
index 016302c53cc5..8c44d5a439e7 100644
--- a/drivers/net/wireless/ath9k/calib.c
+++ b/drivers/net/wireless/ath9k/calib.c
@@ -23,7 +23,7 @@
23 * is incorrect and we should use the static NF value. Later we can try to 23 * is incorrect and we should use the static NF value. Later we can try to
24 * find out why they are reporting these values */ 24 * find out why they are reporting these values */
25 25
26static bool ath9k_hw_nf_in_range(struct ath_hal *ah, s16 nf) 26static bool ath9k_hw_nf_in_range(struct ath_hw *ah, s16 nf)
27{ 27{
28 if (nf > ATH9K_NF_TOO_LOW) { 28 if (nf > ATH9K_NF_TOO_LOW) {
29 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 29 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
@@ -86,7 +86,7 @@ static void ath9k_hw_update_nfcal_hist_buffer(struct ath9k_nfcal_hist *h,
86 return; 86 return;
87} 87}
88 88
89static void ath9k_hw_do_getnf(struct ath_hal *ah, 89static void ath9k_hw_do_getnf(struct ath_hw *ah,
90 int16_t nfarray[NUM_NF_READINGS]) 90 int16_t nfarray[NUM_NF_READINGS])
91{ 91{
92 int16_t nf; 92 int16_t nf;
@@ -166,7 +166,7 @@ static void ath9k_hw_do_getnf(struct ath_hal *ah,
166 } 166 }
167} 167}
168 168
169static bool getNoiseFloorThresh(struct ath_hal *ah, 169static bool getNoiseFloorThresh(struct ath_hw *ah,
170 enum ieee80211_band band, 170 enum ieee80211_band band,
171 int16_t *nft) 171 int16_t *nft)
172{ 172{
@@ -185,7 +185,7 @@ static bool getNoiseFloorThresh(struct ath_hal *ah,
185 return true; 185 return true;
186} 186}
187 187
188static void ath9k_hw_setup_calibration(struct ath_hal *ah, 188static void ath9k_hw_setup_calibration(struct ath_hw *ah,
189 struct hal_cal_list *currCal) 189 struct hal_cal_list *currCal)
190{ 190{
191 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0), 191 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
@@ -219,10 +219,9 @@ static void ath9k_hw_setup_calibration(struct ath_hal *ah,
219 AR_PHY_TIMING_CTRL4_DO_CAL); 219 AR_PHY_TIMING_CTRL4_DO_CAL);
220} 220}
221 221
222static void ath9k_hw_reset_calibration(struct ath_hal *ah, 222static void ath9k_hw_reset_calibration(struct ath_hw *ah,
223 struct hal_cal_list *currCal) 223 struct hal_cal_list *currCal)
224{ 224{
225 struct ath_hal_5416 *ahp = AH5416(ah);
226 int i; 225 int i;
227 226
228 ath9k_hw_setup_calibration(ah, currCal); 227 ath9k_hw_setup_calibration(ah, currCal);
@@ -230,23 +229,21 @@ static void ath9k_hw_reset_calibration(struct ath_hal *ah,
230 currCal->calState = CAL_RUNNING; 229 currCal->calState = CAL_RUNNING;
231 230
232 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 231 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
233 ahp->ah_Meas0.sign[i] = 0; 232 ah->ah_Meas0.sign[i] = 0;
234 ahp->ah_Meas1.sign[i] = 0; 233 ah->ah_Meas1.sign[i] = 0;
235 ahp->ah_Meas2.sign[i] = 0; 234 ah->ah_Meas2.sign[i] = 0;
236 ahp->ah_Meas3.sign[i] = 0; 235 ah->ah_Meas3.sign[i] = 0;
237 } 236 }
238 237
239 ahp->ah_CalSamples = 0; 238 ah->ah_CalSamples = 0;
240} 239}
241 240
242static void ath9k_hw_per_calibration(struct ath_hal *ah, 241static void ath9k_hw_per_calibration(struct ath_hw *ah,
243 struct ath9k_channel *ichan, 242 struct ath9k_channel *ichan,
244 u8 rxchainmask, 243 u8 rxchainmask,
245 struct hal_cal_list *currCal, 244 struct hal_cal_list *currCal,
246 bool *isCalDone) 245 bool *isCalDone)
247{ 246{
248 struct ath_hal_5416 *ahp = AH5416(ah);
249
250 *isCalDone = false; 247 *isCalDone = false;
251 248
252 if (currCal->calState == CAL_RUNNING) { 249 if (currCal->calState == CAL_RUNNING) {
@@ -254,9 +251,9 @@ static void ath9k_hw_per_calibration(struct ath_hal *ah,
254 AR_PHY_TIMING_CTRL4_DO_CAL)) { 251 AR_PHY_TIMING_CTRL4_DO_CAL)) {
255 252
256 currCal->calData->calCollect(ah); 253 currCal->calData->calCollect(ah);
257 ahp->ah_CalSamples++; 254 ah->ah_CalSamples++;
258 255
259 if (ahp->ah_CalSamples >= currCal->calData->calNumSamples) { 256 if (ah->ah_CalSamples >= currCal->calData->calNumSamples) {
260 int i, numChains = 0; 257 int i, numChains = 0;
261 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 258 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
262 if (rxchainmask & (1 << i)) 259 if (rxchainmask & (1 << i))
@@ -277,13 +274,12 @@ static void ath9k_hw_per_calibration(struct ath_hal *ah,
277} 274}
278 275
279/* Assumes you are talking about the currently configured channel */ 276/* Assumes you are talking about the currently configured channel */
280static bool ath9k_hw_iscal_supported(struct ath_hal *ah, 277static bool ath9k_hw_iscal_supported(struct ath_hw *ah,
281 enum hal_cal_types calType) 278 enum hal_cal_types calType)
282{ 279{
283 struct ath_hal_5416 *ahp = AH5416(ah);
284 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; 280 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
285 281
286 switch (calType & ahp->ah_suppCals) { 282 switch (calType & ah->ah_suppCals) {
287 case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */ 283 case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */
288 return true; 284 return true;
289 case ADC_GAIN_CAL: 285 case ADC_GAIN_CAL:
@@ -296,90 +292,86 @@ static bool ath9k_hw_iscal_supported(struct ath_hal *ah,
296 return false; 292 return false;
297} 293}
298 294
299static void ath9k_hw_iqcal_collect(struct ath_hal *ah) 295static void ath9k_hw_iqcal_collect(struct ath_hw *ah)
300{ 296{
301 struct ath_hal_5416 *ahp = AH5416(ah);
302 int i; 297 int i;
303 298
304 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 299 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
305 ahp->ah_totalPowerMeasI[i] += 300 ah->ah_totalPowerMeasI[i] +=
306 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); 301 REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
307 ahp->ah_totalPowerMeasQ[i] += 302 ah->ah_totalPowerMeasQ[i] +=
308 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); 303 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
309 ahp->ah_totalIqCorrMeas[i] += 304 ah->ah_totalIqCorrMeas[i] +=
310 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); 305 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
311 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 306 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
312 "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n", 307 "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
313 ahp->ah_CalSamples, i, ahp->ah_totalPowerMeasI[i], 308 ah->ah_CalSamples, i, ah->ah_totalPowerMeasI[i],
314 ahp->ah_totalPowerMeasQ[i], 309 ah->ah_totalPowerMeasQ[i],
315 ahp->ah_totalIqCorrMeas[i]); 310 ah->ah_totalIqCorrMeas[i]);
316 } 311 }
317} 312}
318 313
319static void ath9k_hw_adc_gaincal_collect(struct ath_hal *ah) 314static void ath9k_hw_adc_gaincal_collect(struct ath_hw *ah)
320{ 315{
321 struct ath_hal_5416 *ahp = AH5416(ah);
322 int i; 316 int i;
323 317
324 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 318 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
325 ahp->ah_totalAdcIOddPhase[i] += 319 ah->ah_totalAdcIOddPhase[i] +=
326 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); 320 REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
327 ahp->ah_totalAdcIEvenPhase[i] += 321 ah->ah_totalAdcIEvenPhase[i] +=
328 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); 322 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
329 ahp->ah_totalAdcQOddPhase[i] += 323 ah->ah_totalAdcQOddPhase[i] +=
330 REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); 324 REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
331 ahp->ah_totalAdcQEvenPhase[i] += 325 ah->ah_totalAdcQEvenPhase[i] +=
332 REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); 326 REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
333 327
334 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 328 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
335 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; " 329 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
336 "oddq=0x%08x; evenq=0x%08x;\n", 330 "oddq=0x%08x; evenq=0x%08x;\n",
337 ahp->ah_CalSamples, i, 331 ah->ah_CalSamples, i,
338 ahp->ah_totalAdcIOddPhase[i], 332 ah->ah_totalAdcIOddPhase[i],
339 ahp->ah_totalAdcIEvenPhase[i], 333 ah->ah_totalAdcIEvenPhase[i],
340 ahp->ah_totalAdcQOddPhase[i], 334 ah->ah_totalAdcQOddPhase[i],
341 ahp->ah_totalAdcQEvenPhase[i]); 335 ah->ah_totalAdcQEvenPhase[i]);
342 } 336 }
343} 337}
344 338
345static void ath9k_hw_adc_dccal_collect(struct ath_hal *ah) 339static void ath9k_hw_adc_dccal_collect(struct ath_hw *ah)
346{ 340{
347 struct ath_hal_5416 *ahp = AH5416(ah);
348 int i; 341 int i;
349 342
350 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 343 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
351 ahp->ah_totalAdcDcOffsetIOddPhase[i] += 344 ah->ah_totalAdcDcOffsetIOddPhase[i] +=
352 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); 345 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
353 ahp->ah_totalAdcDcOffsetIEvenPhase[i] += 346 ah->ah_totalAdcDcOffsetIEvenPhase[i] +=
354 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); 347 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
355 ahp->ah_totalAdcDcOffsetQOddPhase[i] += 348 ah->ah_totalAdcDcOffsetQOddPhase[i] +=
356 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); 349 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
357 ahp->ah_totalAdcDcOffsetQEvenPhase[i] += 350 ah->ah_totalAdcDcOffsetQEvenPhase[i] +=
358 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); 351 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
359 352
360 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 353 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
361 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; " 354 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
362 "oddq=0x%08x; evenq=0x%08x;\n", 355 "oddq=0x%08x; evenq=0x%08x;\n",
363 ahp->ah_CalSamples, i, 356 ah->ah_CalSamples, i,
364 ahp->ah_totalAdcDcOffsetIOddPhase[i], 357 ah->ah_totalAdcDcOffsetIOddPhase[i],
365 ahp->ah_totalAdcDcOffsetIEvenPhase[i], 358 ah->ah_totalAdcDcOffsetIEvenPhase[i],
366 ahp->ah_totalAdcDcOffsetQOddPhase[i], 359 ah->ah_totalAdcDcOffsetQOddPhase[i],
367 ahp->ah_totalAdcDcOffsetQEvenPhase[i]); 360 ah->ah_totalAdcDcOffsetQEvenPhase[i]);
368 } 361 }
369} 362}
370 363
371static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u8 numChains) 364static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
372{ 365{
373 struct ath_hal_5416 *ahp = AH5416(ah);
374 u32 powerMeasQ, powerMeasI, iqCorrMeas; 366 u32 powerMeasQ, powerMeasI, iqCorrMeas;
375 u32 qCoffDenom, iCoffDenom; 367 u32 qCoffDenom, iCoffDenom;
376 int32_t qCoff, iCoff; 368 int32_t qCoff, iCoff;
377 int iqCorrNeg, i; 369 int iqCorrNeg, i;
378 370
379 for (i = 0; i < numChains; i++) { 371 for (i = 0; i < numChains; i++) {
380 powerMeasI = ahp->ah_totalPowerMeasI[i]; 372 powerMeasI = ah->ah_totalPowerMeasI[i];
381 powerMeasQ = ahp->ah_totalPowerMeasQ[i]; 373 powerMeasQ = ah->ah_totalPowerMeasQ[i];
382 iqCorrMeas = ahp->ah_totalIqCorrMeas[i]; 374 iqCorrMeas = ah->ah_totalIqCorrMeas[i];
383 375
384 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 376 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
385 "Starting IQ Cal and Correction for Chain %d\n", 377 "Starting IQ Cal and Correction for Chain %d\n",
@@ -387,7 +379,7 @@ static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u8 numChains)
387 379
388 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 380 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
389 "Orignal: Chn %diq_corr_meas = 0x%08x\n", 381 "Orignal: Chn %diq_corr_meas = 0x%08x\n",
390 i, ahp->ah_totalIqCorrMeas[i]); 382 i, ah->ah_totalIqCorrMeas[i]);
391 383
392 iqCorrNeg = 0; 384 iqCorrNeg = 0;
393 385
@@ -445,17 +437,16 @@ static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u8 numChains)
445 AR_PHY_TIMING_CTRL4_IQCORR_ENABLE); 437 AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);
446} 438}
447 439
448static void ath9k_hw_adc_gaincal_calibrate(struct ath_hal *ah, u8 numChains) 440static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
449{ 441{
450 struct ath_hal_5416 *ahp = AH5416(ah);
451 u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset, qEvenMeasOffset; 442 u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset, qEvenMeasOffset;
452 u32 qGainMismatch, iGainMismatch, val, i; 443 u32 qGainMismatch, iGainMismatch, val, i;
453 444
454 for (i = 0; i < numChains; i++) { 445 for (i = 0; i < numChains; i++) {
455 iOddMeasOffset = ahp->ah_totalAdcIOddPhase[i]; 446 iOddMeasOffset = ah->ah_totalAdcIOddPhase[i];
456 iEvenMeasOffset = ahp->ah_totalAdcIEvenPhase[i]; 447 iEvenMeasOffset = ah->ah_totalAdcIEvenPhase[i];
457 qOddMeasOffset = ahp->ah_totalAdcQOddPhase[i]; 448 qOddMeasOffset = ah->ah_totalAdcQOddPhase[i];
458 qEvenMeasOffset = ahp->ah_totalAdcQEvenPhase[i]; 449 qEvenMeasOffset = ah->ah_totalAdcQEvenPhase[i];
459 450
460 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 451 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
461 "Starting ADC Gain Cal for Chain %d\n", i); 452 "Starting ADC Gain Cal for Chain %d\n", i);
@@ -503,21 +494,20 @@ static void ath9k_hw_adc_gaincal_calibrate(struct ath_hal *ah, u8 numChains)
503 AR_PHY_NEW_ADC_GAIN_CORR_ENABLE); 494 AR_PHY_NEW_ADC_GAIN_CORR_ENABLE);
504} 495}
505 496
506static void ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah, u8 numChains) 497static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
507{ 498{
508 struct ath_hal_5416 *ahp = AH5416(ah);
509 u32 iOddMeasOffset, iEvenMeasOffset, val, i; 499 u32 iOddMeasOffset, iEvenMeasOffset, val, i;
510 int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch; 500 int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch;
511 const struct hal_percal_data *calData = 501 const struct hal_percal_data *calData =
512 ahp->ah_cal_list_curr->calData; 502 ah->ah_cal_list_curr->calData;
513 u32 numSamples = 503 u32 numSamples =
514 (1 << (calData->calCountMax + 5)) * calData->calNumSamples; 504 (1 << (calData->calCountMax + 5)) * calData->calNumSamples;
515 505
516 for (i = 0; i < numChains; i++) { 506 for (i = 0; i < numChains; i++) {
517 iOddMeasOffset = ahp->ah_totalAdcDcOffsetIOddPhase[i]; 507 iOddMeasOffset = ah->ah_totalAdcDcOffsetIOddPhase[i];
518 iEvenMeasOffset = ahp->ah_totalAdcDcOffsetIEvenPhase[i]; 508 iEvenMeasOffset = ah->ah_totalAdcDcOffsetIEvenPhase[i];
519 qOddMeasOffset = ahp->ah_totalAdcDcOffsetQOddPhase[i]; 509 qOddMeasOffset = ah->ah_totalAdcDcOffsetQOddPhase[i];
520 qEvenMeasOffset = ahp->ah_totalAdcDcOffsetQEvenPhase[i]; 510 qEvenMeasOffset = ah->ah_totalAdcDcOffsetQEvenPhase[i];
521 511
522 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 512 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
523 "Starting ADC DC Offset Cal for Chain %d\n", i); 513 "Starting ADC DC Offset Cal for Chain %d\n", i);
@@ -562,11 +552,10 @@ static void ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah, u8 numChains)
562} 552}
563 553
564/* This is done for the currently configured channel */ 554/* This is done for the currently configured channel */
565bool ath9k_hw_reset_calvalid(struct ath_hal *ah) 555bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
566{ 556{
567 struct ath_hal_5416 *ahp = AH5416(ah);
568 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; 557 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
569 struct hal_cal_list *currCal = ahp->ah_cal_list_curr; 558 struct hal_cal_list *currCal = ah->ah_cal_list_curr;
570 559
571 if (!ah->ah_curchan) 560 if (!ah->ah_curchan)
572 return true; 561 return true;
@@ -597,7 +586,7 @@ bool ath9k_hw_reset_calvalid(struct ath_hal *ah)
597 return false; 586 return false;
598} 587}
599 588
600void ath9k_hw_start_nfcal(struct ath_hal *ah) 589void ath9k_hw_start_nfcal(struct ath_hw *ah)
601{ 590{
602 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, 591 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
603 AR_PHY_AGC_CONTROL_ENABLE_NF); 592 AR_PHY_AGC_CONTROL_ENABLE_NF);
@@ -606,7 +595,7 @@ void ath9k_hw_start_nfcal(struct ath_hal *ah)
606 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); 595 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
607} 596}
608 597
609void ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan) 598void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
610{ 599{
611 struct ath9k_nfcal_hist *h; 600 struct ath9k_nfcal_hist *h;
612 int i, j; 601 int i, j;
@@ -662,7 +651,7 @@ void ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan)
662 } 651 }
663} 652}
664 653
665int16_t ath9k_hw_getnf(struct ath_hal *ah, 654int16_t ath9k_hw_getnf(struct ath_hw *ah,
666 struct ath9k_channel *chan) 655 struct ath9k_channel *chan)
667{ 656{
668 int16_t nf, nfThresh; 657 int16_t nf, nfThresh;
@@ -698,7 +687,7 @@ int16_t ath9k_hw_getnf(struct ath_hal *ah,
698 return chan->rawNoiseFloor; 687 return chan->rawNoiseFloor;
699} 688}
700 689
701void ath9k_init_nfcal_hist_buffer(struct ath_hal *ah) 690void ath9k_init_nfcal_hist_buffer(struct ath_hw *ah)
702{ 691{
703 int i, j; 692 int i, j;
704 693
@@ -712,10 +701,9 @@ void ath9k_init_nfcal_hist_buffer(struct ath_hal *ah)
712 AR_PHY_CCA_MAX_GOOD_VALUE; 701 AR_PHY_CCA_MAX_GOOD_VALUE;
713 } 702 }
714 } 703 }
715 return;
716} 704}
717 705
718s16 ath9k_hw_getchan_noise(struct ath_hal *ah, struct ath9k_channel *chan) 706s16 ath9k_hw_getchan_noise(struct ath_hw *ah, struct ath9k_channel *chan)
719{ 707{
720 s16 nf; 708 s16 nf;
721 709
@@ -730,12 +718,11 @@ s16 ath9k_hw_getchan_noise(struct ath_hal *ah, struct ath9k_channel *chan)
730 return nf; 718 return nf;
731} 719}
732 720
733bool ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan, 721bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
734 u8 rxchainmask, bool longcal, 722 u8 rxchainmask, bool longcal,
735 bool *isCalDone) 723 bool *isCalDone)
736{ 724{
737 struct ath_hal_5416 *ahp = AH5416(ah); 725 struct hal_cal_list *currCal = ah->ah_cal_list_curr;
738 struct hal_cal_list *currCal = ahp->ah_cal_list_curr;
739 726
740 *isCalDone = true; 727 *isCalDone = true;
741 728
@@ -745,7 +732,7 @@ bool ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan,
745 ath9k_hw_per_calibration(ah, chan, rxchainmask, currCal, 732 ath9k_hw_per_calibration(ah, chan, rxchainmask, currCal,
746 isCalDone); 733 isCalDone);
747 if (*isCalDone) { 734 if (*isCalDone) {
748 ahp->ah_cal_list_curr = currCal = currCal->calNext; 735 ah->ah_cal_list_curr = currCal = currCal->calNext;
749 736
750 if (currCal->calState == CAL_WAITING) { 737 if (currCal->calState == CAL_WAITING) {
751 *isCalDone = false; 738 *isCalDone = false;
@@ -766,7 +753,7 @@ bool ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan,
766 return true; 753 return true;
767} 754}
768 755
769static inline void ath9k_hw_9285_pa_cal(struct ath_hal *ah) 756static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah)
770{ 757{
771 758
772 u32 regVal; 759 u32 regVal;
@@ -861,11 +848,9 @@ static inline void ath9k_hw_9285_pa_cal(struct ath_hal *ah)
861 848
862} 849}
863 850
864bool ath9k_hw_init_cal(struct ath_hal *ah, 851bool ath9k_hw_init_cal(struct ath_hw *ah,
865 struct ath9k_channel *chan) 852 struct ath9k_channel *chan)
866{ 853{
867 struct ath_hal_5416 *ahp = AH5416(ah);
868
869 REG_WRITE(ah, AR_PHY_AGC_CONTROL, 854 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
870 REG_READ(ah, AR_PHY_AGC_CONTROL) | 855 REG_READ(ah, AR_PHY_AGC_CONTROL) |
871 AR_PHY_AGC_CONTROL_CAL); 856 AR_PHY_AGC_CONTROL_CAL);
@@ -884,32 +869,32 @@ bool ath9k_hw_init_cal(struct ath_hal *ah,
884 REG_READ(ah, AR_PHY_AGC_CONTROL) | 869 REG_READ(ah, AR_PHY_AGC_CONTROL) |
885 AR_PHY_AGC_CONTROL_NF); 870 AR_PHY_AGC_CONTROL_NF);
886 871
887 ahp->ah_cal_list = ahp->ah_cal_list_last = ahp->ah_cal_list_curr = NULL; 872 ah->ah_cal_list = ah->ah_cal_list_last = ah->ah_cal_list_curr = NULL;
888 873
889 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) { 874 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
890 if (ath9k_hw_iscal_supported(ah, ADC_GAIN_CAL)) { 875 if (ath9k_hw_iscal_supported(ah, ADC_GAIN_CAL)) {
891 INIT_CAL(&ahp->ah_adcGainCalData); 876 INIT_CAL(&ah->ah_adcGainCalData);
892 INSERT_CAL(ahp, &ahp->ah_adcGainCalData); 877 INSERT_CAL(ah, &ah->ah_adcGainCalData);
893 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 878 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
894 "enabling ADC Gain Calibration.\n"); 879 "enabling ADC Gain Calibration.\n");
895 } 880 }
896 if (ath9k_hw_iscal_supported(ah, ADC_DC_CAL)) { 881 if (ath9k_hw_iscal_supported(ah, ADC_DC_CAL)) {
897 INIT_CAL(&ahp->ah_adcDcCalData); 882 INIT_CAL(&ah->ah_adcDcCalData);
898 INSERT_CAL(ahp, &ahp->ah_adcDcCalData); 883 INSERT_CAL(ah, &ah->ah_adcDcCalData);
899 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 884 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
900 "enabling ADC DC Calibration.\n"); 885 "enabling ADC DC Calibration.\n");
901 } 886 }
902 if (ath9k_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) { 887 if (ath9k_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {
903 INIT_CAL(&ahp->ah_iqCalData); 888 INIT_CAL(&ah->ah_iqCalData);
904 INSERT_CAL(ahp, &ahp->ah_iqCalData); 889 INSERT_CAL(ah, &ah->ah_iqCalData);
905 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 890 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
906 "enabling IQ Calibration.\n"); 891 "enabling IQ Calibration.\n");
907 } 892 }
908 893
909 ahp->ah_cal_list_curr = ahp->ah_cal_list; 894 ah->ah_cal_list_curr = ah->ah_cal_list;
910 895
911 if (ahp->ah_cal_list_curr) 896 if (ah->ah_cal_list_curr)
912 ath9k_hw_reset_calibration(ah, ahp->ah_cal_list_curr); 897 ath9k_hw_reset_calibration(ah, ah->ah_cal_list_curr);
913 } 898 }
914 899
915 chan->CalValid = 0; 900 chan->CalValid = 0;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-19 15:50:44 -0500