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Diffstat (limited to 'drivers/net/wireless/ath9k/ath9k.h')
-rw-r--r--drivers/net/wireless/ath9k/ath9k.h1653
1 files changed, 654 insertions, 999 deletions
diff --git a/drivers/net/wireless/ath9k/ath9k.h b/drivers/net/wireless/ath9k/ath9k.h
index 5289d2878111..3cb7bf86410e 100644
--- a/drivers/net/wireless/ath9k/ath9k.h
+++ b/drivers/net/wireless/ath9k/ath9k.h
@@ -17,1028 +17,683 @@
17#ifndef ATH9K_H 17#ifndef ATH9K_H
18#define ATH9K_H 18#define ATH9K_H
19 19
20#include <linux/io.h> 20#include <linux/etherdevice.h>
21 21#include <linux/device.h>
22#define ATHEROS_VENDOR_ID 0x168c 22#include <net/mac80211.h>
23 23#include <linux/leds.h>
24#define AR5416_DEVID_PCI 0x0023 24#include <linux/rfkill.h>
25#define AR5416_DEVID_PCIE 0x0024 25
26#define AR9160_DEVID_PCI 0x0027 26#include "hw.h"
27#define AR9280_DEVID_PCI 0x0029 27#include "rc.h"
28#define AR9280_DEVID_PCIE 0x002a 28#include "debug.h"
29#define AR9285_DEVID_PCIE 0x002b 29
30 30struct ath_node;
31#define AR5416_AR9100_DEVID 0x000b 31
32 32/* Macro to expand scalars to 64-bit objects */
33#define AR_SUBVENDOR_ID_NOG 0x0e11 33
34#define AR_SUBVENDOR_ID_NEW_A 0x7065 34#define ito64(x) (sizeof(x) == 8) ? \
35 35 (((unsigned long long int)(x)) & (0xff)) : \
36#define ATH9K_TXERR_XRETRY 0x01 36 (sizeof(x) == 16) ? \
37#define ATH9K_TXERR_FILT 0x02 37 (((unsigned long long int)(x)) & 0xffff) : \
38#define ATH9K_TXERR_FIFO 0x04 38 ((sizeof(x) == 32) ? \
39#define ATH9K_TXERR_XTXOP 0x08 39 (((unsigned long long int)(x)) & 0xffffffff) : \
40#define ATH9K_TXERR_TIMER_EXPIRED 0x10 40 (unsigned long long int)(x))
41 41
42#define ATH9K_TX_BA 0x01 42/* increment with wrap-around */
43#define ATH9K_TX_PWRMGMT 0x02 43#define INCR(_l, _sz) do { \
44#define ATH9K_TX_DESC_CFG_ERR 0x04 44 (_l)++; \
45#define ATH9K_TX_DATA_UNDERRUN 0x08 45 (_l) &= ((_sz) - 1); \
46#define ATH9K_TX_DELIM_UNDERRUN 0x10 46 } while (0)
47#define ATH9K_TX_SW_ABORTED 0x40 47
48#define ATH9K_TX_SW_FILTERED 0x80 48/* decrement with wrap-around */
49 49#define DECR(_l, _sz) do { \
50#define NBBY 8 50 (_l)--; \
51 51 (_l) &= ((_sz) - 1); \
52struct ath_tx_status { 52 } while (0)
53 u32 ts_tstamp; 53
54 u16 ts_seqnum; 54#define A_MAX(a, b) ((a) > (b) ? (a) : (b))
55 u8 ts_status; 55
56 u8 ts_ratecode; 56#define ASSERT(exp) do { \
57 u8 ts_rateindex; 57 if (unlikely(!(exp))) { \
58 int8_t ts_rssi; 58 BUG(); \
59 u8 ts_shortretry; 59 } \
60 u8 ts_longretry; 60 } while (0)
61 u8 ts_virtcol; 61
62 u8 ts_antenna; 62#define TSF_TO_TU(_h,_l) \
63 u8 ts_flags; 63 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
64 int8_t ts_rssi_ctl0; 64
65 int8_t ts_rssi_ctl1; 65#define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i))
66 int8_t ts_rssi_ctl2; 66
67 int8_t ts_rssi_ext0; 67static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
68 int8_t ts_rssi_ext1; 68
69 int8_t ts_rssi_ext2; 69struct ath_config {
70 u8 pad[3]; 70 u32 ath_aggr_prot;
71 u32 ba_low; 71 u16 txpowlimit;
72 u32 ba_high; 72 u8 cabqReadytime;
73 u32 evm0; 73 u8 swBeaconProcess;
74 u32 evm1; 74};
75 u32 evm2; 75
76}; 76/*************************/
77 77/* Descriptor Management */
78struct ath_rx_status { 78/*************************/
79 u32 rs_tstamp; 79
80 u16 rs_datalen; 80#define ATH_TXBUF_RESET(_bf) do { \
81 u8 rs_status; 81 (_bf)->bf_status = 0; \
82 u8 rs_phyerr; 82 (_bf)->bf_lastbf = NULL; \
83 int8_t rs_rssi; 83 (_bf)->bf_next = NULL; \
84 u8 rs_keyix; 84 memset(&((_bf)->bf_state), 0, \
85 u8 rs_rate; 85 sizeof(struct ath_buf_state)); \
86 u8 rs_antenna; 86 } while (0)
87 u8 rs_more; 87
88 int8_t rs_rssi_ctl0; 88/**
89 int8_t rs_rssi_ctl1; 89 * enum buffer_type - Buffer type flags
90 int8_t rs_rssi_ctl2; 90 *
91 int8_t rs_rssi_ext0; 91 * @BUF_HT: Send this buffer using HT capabilities
92 int8_t rs_rssi_ext1; 92 * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
93 int8_t rs_rssi_ext2; 93 * @BUF_AGGR: Indicates whether the buffer can be aggregated
94 u8 rs_isaggr; 94 * (used in aggregation scheduling)
95 u8 rs_moreaggr; 95 * @BUF_RETRY: Indicates whether the buffer is retried
96 u8 rs_num_delims; 96 * @BUF_XRETRY: To denote excessive retries of the buffer
97 u8 rs_flags; 97 */
98 u32 evm0; 98enum buffer_type {
99 u32 evm1; 99 BUF_HT = BIT(1),
100 u32 evm2; 100 BUF_AMPDU = BIT(2),
101}; 101 BUF_AGGR = BIT(3),
102 102 BUF_RETRY = BIT(4),
103#define ATH9K_RXERR_CRC 0x01 103 BUF_XRETRY = BIT(5),
104#define ATH9K_RXERR_PHY 0x02 104};
105#define ATH9K_RXERR_FIFO 0x04 105
106#define ATH9K_RXERR_DECRYPT 0x08 106struct ath_buf_state {
107#define ATH9K_RXERR_MIC 0x10 107 int bfs_nframes; /* # frames in aggregate */
108 108 u16 bfs_al; /* length of aggregate */
109#define ATH9K_RX_MORE 0x01 109 u16 bfs_frmlen; /* length of frame */
110#define ATH9K_RX_MORE_AGGR 0x02 110 int bfs_seqno; /* sequence number */
111#define ATH9K_RX_GI 0x04 111 int bfs_tidno; /* tid of this frame */
112#define ATH9K_RX_2040 0x08 112 int bfs_retries; /* current retries */
113#define ATH9K_RX_DELIM_CRC_PRE 0x10 113 u32 bf_type; /* BUF_* (enum buffer_type) */
114#define ATH9K_RX_DELIM_CRC_POST 0x20 114 u32 bfs_keyix;
115#define ATH9K_RX_DECRYPT_BUSY 0x40 115 enum ath9k_key_type bfs_keytype;
116 116};
117#define ATH9K_RXKEYIX_INVALID ((u8)-1) 117
118#define ATH9K_TXKEYIX_INVALID ((u32)-1) 118#define bf_nframes bf_state.bfs_nframes
119 119#define bf_al bf_state.bfs_al
120struct ath_desc { 120#define bf_frmlen bf_state.bfs_frmlen
121 u32 ds_link; 121#define bf_retries bf_state.bfs_retries
122 u32 ds_data; 122#define bf_seqno bf_state.bfs_seqno
123 u32 ds_ctl0; 123#define bf_tidno bf_state.bfs_tidno
124 u32 ds_ctl1; 124#define bf_keyix bf_state.bfs_keyix
125 u32 ds_hw[20]; 125#define bf_keytype bf_state.bfs_keytype
126 union { 126#define bf_isht(bf) (bf->bf_state.bf_type & BUF_HT)
127 struct ath_tx_status tx; 127#define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
128 struct ath_rx_status rx; 128#define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
129 void *stats; 129#define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY)
130 } ds_us; 130#define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY)
131 void *ds_vdata;
132} __packed;
133
134#define ds_txstat ds_us.tx
135#define ds_rxstat ds_us.rx
136#define ds_stat ds_us.stats
137
138#define ATH9K_TXDESC_CLRDMASK 0x0001
139#define ATH9K_TXDESC_NOACK 0x0002
140#define ATH9K_TXDESC_RTSENA 0x0004
141#define ATH9K_TXDESC_CTSENA 0x0008
142/* ATH9K_TXDESC_INTREQ forces a tx interrupt to be generated for
143 * the descriptor its marked on. We take a tx interrupt to reap
144 * descriptors when the h/w hits an EOL condition or
145 * when the descriptor is specifically marked to generate
146 * an interrupt with this flag. Descriptors should be
147 * marked periodically to insure timely replenishing of the
148 * supply needed for sending frames. Defering interrupts
149 * reduces system load and potentially allows more concurrent
150 * work to be done but if done to aggressively can cause
151 * senders to backup. When the hardware queue is left too
152 * large rate control information may also be too out of
153 * date. An Alternative for this is TX interrupt mitigation
154 * but this needs more testing. */
155#define ATH9K_TXDESC_INTREQ 0x0010
156#define ATH9K_TXDESC_VEOL 0x0020
157#define ATH9K_TXDESC_EXT_ONLY 0x0040
158#define ATH9K_TXDESC_EXT_AND_CTL 0x0080
159#define ATH9K_TXDESC_VMF 0x0100
160#define ATH9K_TXDESC_FRAG_IS_ON 0x0200
161#define ATH9K_TXDESC_CAB 0x0400
162
163#define ATH9K_RXDESC_INTREQ 0x0020
164
165enum wireless_mode {
166 ATH9K_MODE_11A = 0,
167 ATH9K_MODE_11B = 2,
168 ATH9K_MODE_11G = 3,
169 ATH9K_MODE_11NA_HT20 = 6,
170 ATH9K_MODE_11NG_HT20 = 7,
171 ATH9K_MODE_11NA_HT40PLUS = 8,
172 ATH9K_MODE_11NA_HT40MINUS = 9,
173 ATH9K_MODE_11NG_HT40PLUS = 10,
174 ATH9K_MODE_11NG_HT40MINUS = 11,
175 ATH9K_MODE_MAX
176};
177
178enum ath9k_hw_caps {
179 ATH9K_HW_CAP_CHAN_SPREAD = BIT(0),
180 ATH9K_HW_CAP_MIC_AESCCM = BIT(1),
181 ATH9K_HW_CAP_MIC_CKIP = BIT(2),
182 ATH9K_HW_CAP_MIC_TKIP = BIT(3),
183 ATH9K_HW_CAP_CIPHER_AESCCM = BIT(4),
184 ATH9K_HW_CAP_CIPHER_CKIP = BIT(5),
185 ATH9K_HW_CAP_CIPHER_TKIP = BIT(6),
186 ATH9K_HW_CAP_VEOL = BIT(7),
187 ATH9K_HW_CAP_BSSIDMASK = BIT(8),
188 ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(9),
189 ATH9K_HW_CAP_CHAN_HALFRATE = BIT(10),
190 ATH9K_HW_CAP_CHAN_QUARTERRATE = BIT(11),
191 ATH9K_HW_CAP_HT = BIT(12),
192 ATH9K_HW_CAP_GTT = BIT(13),
193 ATH9K_HW_CAP_FASTCC = BIT(14),
194 ATH9K_HW_CAP_RFSILENT = BIT(15),
195 ATH9K_HW_CAP_WOW = BIT(16),
196 ATH9K_HW_CAP_CST = BIT(17),
197 ATH9K_HW_CAP_ENHANCEDPM = BIT(18),
198 ATH9K_HW_CAP_AUTOSLEEP = BIT(19),
199 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(20),
200 ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT = BIT(21),
201 ATH9K_HW_CAP_BT_COEX = BIT(22)
202};
203
204enum ath9k_capability_type {
205 ATH9K_CAP_CIPHER = 0,
206 ATH9K_CAP_TKIP_MIC,
207 ATH9K_CAP_TKIP_SPLIT,
208 ATH9K_CAP_PHYCOUNTERS,
209 ATH9K_CAP_DIVERSITY,
210 ATH9K_CAP_TXPOW,
211 ATH9K_CAP_PHYDIAG,
212 ATH9K_CAP_MCAST_KEYSRCH,
213 ATH9K_CAP_TSF_ADJUST,
214 ATH9K_CAP_WME_TKIPMIC,
215 ATH9K_CAP_RFSILENT,
216 ATH9K_CAP_ANT_CFG_2GHZ,
217 ATH9K_CAP_ANT_CFG_5GHZ
218};
219
220struct ath9k_hw_capabilities {
221 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
222 DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */
223 u16 total_queues;
224 u16 keycache_size;
225 u16 low_5ghz_chan, high_5ghz_chan;
226 u16 low_2ghz_chan, high_2ghz_chan;
227 u16 num_mr_retries;
228 u16 rts_aggr_limit;
229 u8 tx_chainmask;
230 u8 rx_chainmask;
231 u16 tx_triglevel_max;
232 u16 reg_cap;
233 u8 num_gpio_pins;
234 u8 num_antcfg_2ghz;
235 u8 num_antcfg_5ghz;
236};
237
238struct ath9k_ops_config {
239 int dma_beacon_response_time;
240 int sw_beacon_response_time;
241 int additional_swba_backoff;
242 int ack_6mb;
243 int cwm_ignore_extcca;
244 u8 pcie_powersave_enable;
245 u8 pcie_l1skp_enable;
246 u8 pcie_clock_req;
247 u32 pcie_waen;
248 int pcie_power_reset;
249 u8 pcie_restore;
250 u8 analog_shiftreg;
251 u8 ht_enable;
252 u32 ofdm_trig_low;
253 u32 ofdm_trig_high;
254 u32 cck_trig_high;
255 u32 cck_trig_low;
256 u32 enable_ani;
257 u8 noise_immunity_level;
258 u32 ofdm_weaksignal_det;
259 u32 cck_weaksignal_thr;
260 u8 spur_immunity_level;
261 u8 firstep_level;
262 int8_t rssi_thr_high;
263 int8_t rssi_thr_low;
264 u16 diversity_control;
265 u16 antenna_switch_swap;
266 int serialize_regmode;
267 int intr_mitigation;
268#define SPUR_DISABLE 0
269#define SPUR_ENABLE_IOCTL 1
270#define SPUR_ENABLE_EEPROM 2
271#define AR_EEPROM_MODAL_SPURS 5
272#define AR_SPUR_5413_1 1640
273#define AR_SPUR_5413_2 1200
274#define AR_NO_SPUR 0x8000
275#define AR_BASE_FREQ_2GHZ 2300
276#define AR_BASE_FREQ_5GHZ 4900
277#define AR_SPUR_FEEQ_BOUND_HT40 19
278#define AR_SPUR_FEEQ_BOUND_HT20 10
279 int spurmode;
280 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
281};
282
283enum ath9k_tx_queue {
284 ATH9K_TX_QUEUE_INACTIVE = 0,
285 ATH9K_TX_QUEUE_DATA,
286 ATH9K_TX_QUEUE_BEACON,
287 ATH9K_TX_QUEUE_CAB,
288 ATH9K_TX_QUEUE_UAPSD,
289 ATH9K_TX_QUEUE_PSPOLL
290};
291
292#define ATH9K_NUM_TX_QUEUES 10
293
294enum ath9k_tx_queue_subtype {
295 ATH9K_WME_AC_BK = 0,
296 ATH9K_WME_AC_BE,
297 ATH9K_WME_AC_VI,
298 ATH9K_WME_AC_VO,
299 ATH9K_WME_UPSD
300};
301
302enum ath9k_tx_queue_flags {
303 TXQ_FLAG_TXOKINT_ENABLE = 0x0001,
304 TXQ_FLAG_TXERRINT_ENABLE = 0x0001,
305 TXQ_FLAG_TXDESCINT_ENABLE = 0x0002,
306 TXQ_FLAG_TXEOLINT_ENABLE = 0x0004,
307 TXQ_FLAG_TXURNINT_ENABLE = 0x0008,
308 TXQ_FLAG_BACKOFF_DISABLE = 0x0010,
309 TXQ_FLAG_COMPRESSION_ENABLE = 0x0020,
310 TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE = 0x0040,
311 TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE = 0x0080,
312};
313
314#define ATH9K_TXQ_USEDEFAULT ((u32) -1)
315
316#define ATH9K_DECOMP_MASK_SIZE 128
317#define ATH9K_READY_TIME_LO_BOUND 50
318#define ATH9K_READY_TIME_HI_BOUND 96
319
320enum ath9k_pkt_type {
321 ATH9K_PKT_TYPE_NORMAL = 0,
322 ATH9K_PKT_TYPE_ATIM,
323 ATH9K_PKT_TYPE_PSPOLL,
324 ATH9K_PKT_TYPE_BEACON,
325 ATH9K_PKT_TYPE_PROBE_RESP,
326 ATH9K_PKT_TYPE_CHIRP,
327 ATH9K_PKT_TYPE_GRP_POLL,
328};
329
330struct ath9k_tx_queue_info {
331 u32 tqi_ver;
332 enum ath9k_tx_queue tqi_type;
333 enum ath9k_tx_queue_subtype tqi_subtype;
334 enum ath9k_tx_queue_flags tqi_qflags;
335 u32 tqi_priority;
336 u32 tqi_aifs;
337 u32 tqi_cwmin;
338 u32 tqi_cwmax;
339 u16 tqi_shretry;
340 u16 tqi_lgretry;
341 u32 tqi_cbrPeriod;
342 u32 tqi_cbrOverflowLimit;
343 u32 tqi_burstTime;
344 u32 tqi_readyTime;
345 u32 tqi_physCompBuf;
346 u32 tqi_intFlags;
347};
348
349enum ath9k_rx_filter {
350 ATH9K_RX_FILTER_UCAST = 0x00000001,
351 ATH9K_RX_FILTER_MCAST = 0x00000002,
352 ATH9K_RX_FILTER_BCAST = 0x00000004,
353 ATH9K_RX_FILTER_CONTROL = 0x00000008,
354 ATH9K_RX_FILTER_BEACON = 0x00000010,
355 ATH9K_RX_FILTER_PROM = 0x00000020,
356 ATH9K_RX_FILTER_PROBEREQ = 0x00000080,
357 ATH9K_RX_FILTER_PSPOLL = 0x00004000,
358 ATH9K_RX_FILTER_PHYERR = 0x00000100,
359 ATH9K_RX_FILTER_PHYRADAR = 0x00002000,
360};
361
362enum ath9k_int {
363 ATH9K_INT_RX = 0x00000001,
364 ATH9K_INT_RXDESC = 0x00000002,
365 ATH9K_INT_RXNOFRM = 0x00000008,
366 ATH9K_INT_RXEOL = 0x00000010,
367 ATH9K_INT_RXORN = 0x00000020,
368 ATH9K_INT_TX = 0x00000040,
369 ATH9K_INT_TXDESC = 0x00000080,
370 ATH9K_INT_TIM_TIMER = 0x00000100,
371 ATH9K_INT_TXURN = 0x00000800,
372 ATH9K_INT_MIB = 0x00001000,
373 ATH9K_INT_RXPHY = 0x00004000,
374 ATH9K_INT_RXKCM = 0x00008000,
375 ATH9K_INT_SWBA = 0x00010000,
376 ATH9K_INT_BMISS = 0x00040000,
377 ATH9K_INT_BNR = 0x00100000,
378 ATH9K_INT_TIM = 0x00200000,
379 ATH9K_INT_DTIM = 0x00400000,
380 ATH9K_INT_DTIMSYNC = 0x00800000,
381 ATH9K_INT_GPIO = 0x01000000,
382 ATH9K_INT_CABEND = 0x02000000,
383 ATH9K_INT_CST = 0x10000000,
384 ATH9K_INT_GTT = 0x20000000,
385 ATH9K_INT_FATAL = 0x40000000,
386 ATH9K_INT_GLOBAL = 0x80000000,
387 ATH9K_INT_BMISC = ATH9K_INT_TIM |
388 ATH9K_INT_DTIM |
389 ATH9K_INT_DTIMSYNC |
390 ATH9K_INT_CABEND,
391 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
392 ATH9K_INT_RXDESC |
393 ATH9K_INT_RXEOL |
394 ATH9K_INT_RXORN |
395 ATH9K_INT_TXURN |
396 ATH9K_INT_TXDESC |
397 ATH9K_INT_MIB |
398 ATH9K_INT_RXPHY |
399 ATH9K_INT_RXKCM |
400 ATH9K_INT_SWBA |
401 ATH9K_INT_BMISS |
402 ATH9K_INT_GPIO,
403 ATH9K_INT_NOCARD = 0xffffffff
404};
405
406#define ATH9K_RATESERIES_RTS_CTS 0x0001
407#define ATH9K_RATESERIES_2040 0x0002
408#define ATH9K_RATESERIES_HALFGI 0x0004
409
410struct ath9k_11n_rate_series {
411 u32 Tries;
412 u32 Rate;
413 u32 PktDuration;
414 u32 ChSel;
415 u32 RateFlags;
416};
417
418#define CHANNEL_CW_INT 0x00002
419#define CHANNEL_CCK 0x00020
420#define CHANNEL_OFDM 0x00040
421#define CHANNEL_2GHZ 0x00080
422#define CHANNEL_5GHZ 0x00100
423#define CHANNEL_PASSIVE 0x00200
424#define CHANNEL_DYN 0x00400
425#define CHANNEL_HALF 0x04000
426#define CHANNEL_QUARTER 0x08000
427#define CHANNEL_HT20 0x10000
428#define CHANNEL_HT40PLUS 0x20000
429#define CHANNEL_HT40MINUS 0x40000
430
431#define CHANNEL_INTERFERENCE 0x01
432#define CHANNEL_DFS 0x02
433#define CHANNEL_4MS_LIMIT 0x04
434#define CHANNEL_DFS_CLEAR 0x08
435#define CHANNEL_DISALLOW_ADHOC 0x10
436#define CHANNEL_PER_11D_ADHOC 0x20
437
438#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
439#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
440#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
441#define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
442#define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
443#define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
444#define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
445#define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
446#define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
447#define CHANNEL_ALL \
448 (CHANNEL_OFDM| \
449 CHANNEL_CCK| \
450 CHANNEL_2GHZ | \
451 CHANNEL_5GHZ | \
452 CHANNEL_HT20 | \
453 CHANNEL_HT40PLUS | \
454 CHANNEL_HT40MINUS)
455
456struct ath9k_channel {
457 struct ieee80211_channel *chan;
458 u16 channel;
459 u32 channelFlags;
460 u32 chanmode;
461 int32_t CalValid;
462 bool oneTimeCalsDone;
463 int8_t iCoff;
464 int8_t qCoff;
465 int16_t rawNoiseFloor;
466};
467
468#define IS_CHAN_A(_c) ((((_c)->channelFlags & CHANNEL_A) == CHANNEL_A) || \
469 (((_c)->channelFlags & CHANNEL_A_HT20) == CHANNEL_A_HT20) || \
470 (((_c)->channelFlags & CHANNEL_A_HT40PLUS) == CHANNEL_A_HT40PLUS) || \
471 (((_c)->channelFlags & CHANNEL_A_HT40MINUS) == CHANNEL_A_HT40MINUS))
472#define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
473 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
474 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
475 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
476#define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
477#define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
478#define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
479#define IS_CHAN_PASSIVE(_c) (((_c)->channelFlags & CHANNEL_PASSIVE) != 0)
480#define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
481#define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
482
483/* These macros check chanmode and not channelFlags */
484#define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
485#define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
486 ((_c)->chanmode == CHANNEL_G_HT20))
487#define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
488 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
489 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
490 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
491#define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
492
493#define IS_CHAN_A_5MHZ_SPACED(_c) \
494 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
495 (((_c)->channel % 20) != 0) && \
496 (((_c)->channel % 10) != 0))
497
498struct ath9k_keyval {
499 u8 kv_type;
500 u8 kv_pad;
501 u16 kv_len;
502 u8 kv_val[16];
503 u8 kv_mic[8];
504 u8 kv_txmic[8];
505};
506
507enum ath9k_key_type {
508 ATH9K_KEY_TYPE_CLEAR,
509 ATH9K_KEY_TYPE_WEP,
510 ATH9K_KEY_TYPE_AES,
511 ATH9K_KEY_TYPE_TKIP,
512};
513
514enum ath9k_cipher {
515 ATH9K_CIPHER_WEP = 0,
516 ATH9K_CIPHER_AES_OCB = 1,
517 ATH9K_CIPHER_AES_CCM = 2,
518 ATH9K_CIPHER_CKIP = 3,
519 ATH9K_CIPHER_TKIP = 4,
520 ATH9K_CIPHER_CLR = 5,
521 ATH9K_CIPHER_MIC = 127
522};
523
524#define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001
525#define AR_EEPROM_EEPCAP_AES_DIS 0x0002
526#define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004
527#define AR_EEPROM_EEPCAP_BURST_DIS 0x0008
528#define AR_EEPROM_EEPCAP_MAXQCU 0x01F0
529#define AR_EEPROM_EEPCAP_MAXQCU_S 4
530#define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200
531#define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000
532#define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12
533
534#define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040
535#define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080
536#define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100
537#define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200
538#define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400
539#define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800
540
541#define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000
542#define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000
543
544#define SD_NO_CTL 0xE0
545#define NO_CTL 0xff
546#define CTL_MODE_M 7
547#define CTL_11A 0
548#define CTL_11B 1
549#define CTL_11G 2
550#define CTL_2GHT20 5
551#define CTL_5GHT20 6
552#define CTL_2GHT40 7
553#define CTL_5GHT40 8
554
555#define AR_EEPROM_MAC(i) (0x1d+(i))
556
557#define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c
558#define AR_EEPROM_RFSILENT_GPIO_SEL_S 2
559#define AR_EEPROM_RFSILENT_POLARITY 0x0002
560#define AR_EEPROM_RFSILENT_POLARITY_S 1
561
562#define CTRY_DEBUG 0x1ff
563#define CTRY_DEFAULT 0
564
565enum reg_ext_bitmap {
566 REG_EXT_JAPAN_MIDBAND = 1,
567 REG_EXT_FCC_DFS_HT40 = 2,
568 REG_EXT_JAPAN_NONDFS_HT40 = 3,
569 REG_EXT_JAPAN_DFS_HT40 = 4
570};
571
572struct ath9k_country_entry {
573 u16 countryCode;
574 u16 regDmnEnum;
575 u16 regDmn5G;
576 u16 regDmn2G;
577 u8 isMultidomain;
578 u8 iso[3];
579};
580
581#define REG_WRITE(_ah, _reg, _val) iowrite32(_val, _ah->ah_sh + _reg)
582#define REG_READ(_ah, _reg) ioread32(_ah->ah_sh + _reg)
583
584#define SM(_v, _f) (((_v) << _f##_S) & _f)
585#define MS(_v, _f) (((_v) & _f) >> _f##_S)
586#define REG_RMW(_a, _r, _set, _clr) \
587 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
588#define REG_RMW_FIELD(_a, _r, _f, _v) \
589 REG_WRITE(_a, _r, \
590 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
591#define REG_SET_BIT(_a, _r, _f) \
592 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
593#define REG_CLR_BIT(_a, _r, _f) \
594 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
595
596#define ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001
597
598#define INIT_AIFS 2
599#define INIT_CWMIN 15
600#define INIT_CWMIN_11B 31
601#define INIT_CWMAX 1023
602#define INIT_SH_RETRY 10
603#define INIT_LG_RETRY 10
604#define INIT_SSH_RETRY 32
605#define INIT_SLG_RETRY 32
606
607#define WLAN_CTRL_FRAME_SIZE (2+2+6+4)
608
609#define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
610#define ATH_AMPDU_LIMIT_DEFAULT ATH_AMPDU_LIMIT_MAX
611
612#define IEEE80211_WEP_IVLEN 3
613#define IEEE80211_WEP_KIDLEN 1
614#define IEEE80211_WEP_CRCLEN 4
615#define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \
616 (IEEE80211_WEP_IVLEN + \
617 IEEE80211_WEP_KIDLEN + \
618 IEEE80211_WEP_CRCLEN))
619#define MAX_RATE_POWER 63
620
621enum ath9k_power_mode {
622 ATH9K_PM_AWAKE = 0,
623 ATH9K_PM_FULL_SLEEP,
624 ATH9K_PM_NETWORK_SLEEP,
625 ATH9K_PM_UNDEFINED
626};
627
628struct ath9k_mib_stats {
629 u32 ackrcv_bad;
630 u32 rts_bad;
631 u32 rts_good;
632 u32 fcs_bad;
633 u32 beacons;
634};
635 131
636enum ath9k_ant_setting { 132/*
637 ATH9K_ANT_VARIABLE = 0, 133 * Abstraction of a contiguous buffer to transmit/receive. There is only
638 ATH9K_ANT_FIXED_A, 134 * a single hw descriptor encapsulated here.
639 ATH9K_ANT_FIXED_B 135 */
640}; 136struct ath_buf {
137 struct list_head list;
138 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
139 an aggregate) */
140 struct ath_buf *bf_next; /* next subframe in the aggregate */
141 void *bf_mpdu; /* enclosing frame structure */
142 struct ath_desc *bf_desc; /* virtual addr of desc */
143 dma_addr_t bf_daddr; /* physical addr of desc */
144 dma_addr_t bf_buf_addr; /* physical addr of data buffer */
145 u32 bf_status;
146 u16 bf_flags; /* tx descriptor flags */
147 struct ath_buf_state bf_state; /* buffer state */
148 dma_addr_t bf_dmacontext;
149};
150
151#define ATH_RXBUF_RESET(_bf) ((_bf)->bf_status = 0)
152#define ATH_BUFSTATUS_STALE 0x00000002
153
154/* DMA state for tx/rx descriptors */
155
156struct ath_descdma {
157 const char *dd_name;
158 struct ath_desc *dd_desc; /* descriptors */
159 dma_addr_t dd_desc_paddr; /* physical addr of dd_desc */
160 u32 dd_desc_len; /* size of dd_desc */
161 struct ath_buf *dd_bufptr; /* associated buffers */
162 dma_addr_t dd_dmacontext;
163};
164
165int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
166 struct list_head *head, const char *name,
167 int nbuf, int ndesc);
168void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
169 struct list_head *head);
170
171/***********/
172/* RX / TX */
173/***********/
174
175#define ATH_MAX_ANTENNA 3
176#define ATH_RXBUF 512
177#define WME_NUM_TID 16
178#define ATH_TXBUF 512
179#define ATH_TXMAXTRY 13
180#define ATH_11N_TXMAXTRY 10
181#define ATH_MGT_TXMAXTRY 4
182#define WME_BA_BMP_SIZE 64
183#define WME_MAX_BA WME_BA_BMP_SIZE
184#define ATH_TID_MAX_BUFS (2 * WME_MAX_BA)
185
186#define TID_TO_WME_AC(_tid) \
187 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
188 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
189 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
190 WME_AC_VO)
191
192#define WME_AC_BE 0
193#define WME_AC_BK 1
194#define WME_AC_VI 2
195#define WME_AC_VO 3
196#define WME_NUM_AC 4
197
198#define ADDBA_EXCHANGE_ATTEMPTS 10
199#define ATH_AGGR_DELIM_SZ 4
200#define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
201/* number of delimiters for encryption padding */
202#define ATH_AGGR_ENCRYPTDELIM 10
203/* minimum h/w qdepth to be sustained to maximize aggregation */
204#define ATH_AGGR_MIN_QDEPTH 2
205#define ATH_AMPDU_SUBFRAME_DEFAULT 32
206#define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
207#define ATH_AMPDU_LIMIT_DEFAULT ATH_AMPDU_LIMIT_MAX
208
209#define IEEE80211_SEQ_SEQ_SHIFT 4
210#define IEEE80211_SEQ_MAX 4096
211#define IEEE80211_MIN_AMPDU_BUF 0x8
212#define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13
213#define IEEE80211_WEP_IVLEN 3
214#define IEEE80211_WEP_KIDLEN 1
215#define IEEE80211_WEP_CRCLEN 4
216#define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \
217 (IEEE80211_WEP_IVLEN + \
218 IEEE80211_WEP_KIDLEN + \
219 IEEE80211_WEP_CRCLEN))
220
221/* return whether a bit at index _n in bitmap _bm is set
222 * _sz is the size of the bitmap */
223#define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
224 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
225
226/* return block-ack bitmap index given sequence and starting sequence */
227#define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
228
229/* returns delimiter padding required given the packet length */
230#define ATH_AGGR_GET_NDELIM(_len) \
231 (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \
232 (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
233
234#define BAW_WITHIN(_start, _bawsz, _seqno) \
235 ((((_seqno) - (_start)) & 4095) < (_bawsz))
236
237#define ATH_DS_BA_SEQ(_ds) ((_ds)->ds_us.tx.ts_seqnum)
238#define ATH_DS_BA_BITMAP(_ds) (&(_ds)->ds_us.tx.ba_low)
239#define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA)
240#define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)])
241
242enum ATH_AGGR_STATUS {
243 ATH_AGGR_DONE,
244 ATH_AGGR_BAW_CLOSED,
245 ATH_AGGR_LIMITED,
246};
247
248struct ath_txq {
249 u32 axq_qnum; /* hardware q number */
250 u32 *axq_link; /* link ptr in last TX desc */
251 struct list_head axq_q; /* transmit queue */
252 spinlock_t axq_lock;
253 u32 axq_depth; /* queue depth */
254 u8 axq_aggr_depth; /* aggregates queued */
255 u32 axq_totalqueued; /* total ever queued */
256 bool stopped; /* Is mac80211 queue stopped ? */
257 struct ath_buf *axq_linkbuf; /* virtual addr of last buffer*/
258
259 /* first desc of the last descriptor that contains CTS */
260 struct ath_desc *axq_lastdsWithCTS;
261
262 /* final desc of the gating desc that determines whether
263 lastdsWithCTS has been DMA'ed or not */
264 struct ath_desc *axq_gatingds;
265
266 struct list_head axq_acq;
267};
268
269#define AGGR_CLEANUP BIT(1)
270#define AGGR_ADDBA_COMPLETE BIT(2)
271#define AGGR_ADDBA_PROGRESS BIT(3)
272
273/* per TID aggregate tx state for a destination */
274struct ath_atx_tid {
275 struct list_head list; /* round-robin tid entry */
276 struct list_head buf_q; /* pending buffers */
277 struct ath_node *an;
278 struct ath_atx_ac *ac;
279 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; /* active tx frames */
280 u16 seq_start;
281 u16 seq_next;
282 u16 baw_size;
283 int tidno;
284 int baw_head; /* first un-acked tx buffer */
285 int baw_tail; /* next unused tx buffer slot */
286 int sched;
287 int paused;
288 u8 state;
289 int addba_exchangeattempts;
290};
291
292/* per access-category aggregate tx state for a destination */
293struct ath_atx_ac {
294 int sched; /* dest-ac is scheduled */
295 int qnum; /* H/W queue number associated
296 with this AC */
297 struct list_head list; /* round-robin txq entry */
298 struct list_head tid_q; /* queue of TIDs with buffers */
299};
300
301/* per-frame tx control block */
302struct ath_tx_control {
303 struct ath_txq *txq;
304 int if_id;
305};
306
307/* per frame tx status block */
308struct ath_xmit_status {
309 int retries; /* number of retries to successufully
310 transmit this frame */
311 int flags; /* status of transmit */
312#define ATH_TX_ERROR 0x01
313#define ATH_TX_XRETRY 0x02
314#define ATH_TX_BAR 0x04
315};
316
317/* All RSSI values are noise floor adjusted */
318struct ath_tx_stat {
319 int rssi;
320 int rssictl[ATH_MAX_ANTENNA];
321 int rssiextn[ATH_MAX_ANTENNA];
322 int rateieee;
323 int rateKbps;
324 int ratecode;
325 int flags;
326 u32 airtime; /* time on air per final tx rate */
327};
328
329struct aggr_rifs_param {
330 int param_max_frames;
331 int param_max_len;
332 int param_rl;
333 int param_al;
334 struct ath_rc_series *param_rcs;
335};
336
337struct ath_node {
338 struct ath_softc *an_sc;
339 struct ath_atx_tid tid[WME_NUM_TID];
340 struct ath_atx_ac ac[WME_NUM_AC];
341 u16 maxampdu;
342 u8 mpdudensity;
343};
344
345struct ath_tx {
346 u16 seq_no;
347 u32 txqsetup;
348 int hwq_map[ATH9K_WME_AC_VO+1];
349 spinlock_t txbuflock;
350 struct list_head txbuf;
351 struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
352 struct ath_descdma txdma;
353};
354
355struct ath_rx {
356 u8 defant;
357 u8 rxotherant;
358 u32 *rxlink;
359 int bufsize;
360 unsigned int rxfilter;
361 spinlock_t rxflushlock;
362 spinlock_t rxbuflock;
363 struct list_head rxbuf;
364 struct ath_descdma rxdma;
365};
366
367int ath_startrecv(struct ath_softc *sc);
368bool ath_stoprecv(struct ath_softc *sc);
369void ath_flushrecv(struct ath_softc *sc);
370u32 ath_calcrxfilter(struct ath_softc *sc);
371int ath_rx_init(struct ath_softc *sc, int nbufs);
372void ath_rx_cleanup(struct ath_softc *sc);
373int ath_rx_tasklet(struct ath_softc *sc, int flush);
374struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
375void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
376int ath_tx_setup(struct ath_softc *sc, int haltype);
377void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx);
378void ath_draintxq(struct ath_softc *sc,
379 struct ath_txq *txq, bool retry_tx);
380void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
381void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
382void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
383int ath_tx_init(struct ath_softc *sc, int nbufs);
384int ath_tx_cleanup(struct ath_softc *sc);
385struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb);
386int ath_txq_update(struct ath_softc *sc, int qnum,
387 struct ath9k_tx_queue_info *q);
388int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb,
389 struct ath_tx_control *txctl);
390void ath_tx_tasklet(struct ath_softc *sc);
391void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb);
392bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno);
393int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
394 u16 tid, u16 *ssn);
395int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
396void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
397
398/********/
399/* VAPs */
400/********/
641 401
642#define ATH9K_SLOT_TIME_6 6 402/*
643#define ATH9K_SLOT_TIME_9 9 403 * Define the scheme that we select MAC address for multiple
644#define ATH9K_SLOT_TIME_20 20 404 * BSS on the same radio. The very first VAP will just use the MAC
405 * address from the EEPROM. For the next 3 VAPs, we set the
406 * U/L bit (bit 1) in MAC address, and use the next two bits as the
407 * index of the VAP.
408 */
645 409
646enum ath9k_ht_macmode { 410#define ATH_SET_VAP_BSSID_MASK(bssid_mask) \
647 ATH9K_HT_MACMODE_20 = 0, 411 ((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02))
648 ATH9K_HT_MACMODE_2040 = 1,
649};
650 412
651enum ath9k_ht_extprotspacing { 413struct ath_vap {
652 ATH9K_HT_EXTPROTSPACING_20 = 0, 414 int av_bslot;
653 ATH9K_HT_EXTPROTSPACING_25 = 1, 415 enum nl80211_iftype av_opmode;
416 struct ath_buf *av_bcbuf;
417 struct ath_tx_control av_btxctl;
654}; 418};
655 419
656struct ath9k_ht_cwm { 420/*******************/
657 enum ath9k_ht_macmode ht_macmode; 421/* Beacon Handling */
658 enum ath9k_ht_extprotspacing ht_extprotspacing; 422/*******************/
659};
660 423
661enum ath9k_ani_cmd { 424/*
662 ATH9K_ANI_PRESENT = 0x1, 425 * Regardless of the number of beacons we stagger, (i.e. regardless of the
663 ATH9K_ANI_NOISE_IMMUNITY_LEVEL = 0x2, 426 * number of BSSIDs) if a given beacon does not go out even after waiting this
664 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION = 0x4, 427 * number of beacon intervals, the game's up.
665 ATH9K_ANI_CCK_WEAK_SIGNAL_THR = 0x8, 428 */
666 ATH9K_ANI_FIRSTEP_LEVEL = 0x10, 429#define BSTUCK_THRESH (9 * ATH_BCBUF)
667 ATH9K_ANI_SPUR_IMMUNITY_LEVEL = 0x20, 430#define ATH_BCBUF 1
668 ATH9K_ANI_MODE = 0x40, 431#define ATH_DEFAULT_BINTVAL 100 /* TU */
669 ATH9K_ANI_PHYERR_RESET = 0x80, 432#define ATH_DEFAULT_BMISS_LIMIT 10
670 ATH9K_ANI_ALL = 0xff 433#define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
671}; 434
435struct ath_beacon_config {
436 u16 beacon_interval;
437 u16 listen_interval;
438 u16 dtim_period;
439 u16 bmiss_timeout;
440 u8 dtim_count;
441 u8 tim_offset;
442 union {
443 u64 last_tsf;
444 u8 last_tstamp[8];
445 } u; /* last received beacon/probe response timestamp of this BSS. */
446};
447
448struct ath_beacon {
449 enum {
450 OK, /* no change needed */
451 UPDATE, /* update pending */
452 COMMIT /* beacon sent, commit change */
453 } updateslot; /* slot time update fsm */
454
455 u32 beaconq;
456 u32 bmisscnt;
457 u32 ast_be_xmit;
458 u64 bc_tstamp;
459 int bslot[ATH_BCBUF];
460 int slottime;
461 int slotupdate;
462 struct ath9k_tx_queue_info beacon_qi;
463 struct ath_descdma bdma;
464 struct ath_txq *cabq;
465 struct list_head bbuf;
466};
467
468void ath9k_beacon_tasklet(unsigned long data);
469void ath_beacon_config(struct ath_softc *sc, int if_id);
470int ath_beaconq_setup(struct ath_hal *ah);
471int ath_beacon_alloc(struct ath_softc *sc, int if_id);
472void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp);
473void ath_beacon_sync(struct ath_softc *sc, int if_id);
474
475/*******/
476/* ANI */
477/*******/
672 478
673enum { 479/* ANI values for STA only.
674 WLAN_RC_PHY_OFDM, 480 FIXME: Add appropriate values for AP later */
675 WLAN_RC_PHY_CCK,
676 WLAN_RC_PHY_HT_20_SS,
677 WLAN_RC_PHY_HT_20_DS,
678 WLAN_RC_PHY_HT_40_SS,
679 WLAN_RC_PHY_HT_40_DS,
680 WLAN_RC_PHY_HT_20_SS_HGI,
681 WLAN_RC_PHY_HT_20_DS_HGI,
682 WLAN_RC_PHY_HT_40_SS_HGI,
683 WLAN_RC_PHY_HT_40_DS_HGI,
684 WLAN_RC_PHY_MAX
685};
686 481
687enum ath9k_tp_scale { 482#define ATH_ANI_POLLINTERVAL 100 /* 100 milliseconds between ANI poll */
688 ATH9K_TP_SCALE_MAX = 0, 483#define ATH_SHORT_CALINTERVAL 1000 /* 1 second between calibrations */
689 ATH9K_TP_SCALE_50, 484#define ATH_LONG_CALINTERVAL 30000 /* 30 seconds between calibrations */
690 ATH9K_TP_SCALE_25, 485#define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes between calibrations */
691 ATH9K_TP_SCALE_12,
692 ATH9K_TP_SCALE_MIN
693};
694 486
695enum ser_reg_mode { 487struct ath_ani {
696 SER_REG_MODE_OFF = 0, 488 bool sc_caldone;
697 SER_REG_MODE_ON = 1, 489 int16_t sc_noise_floor;
698 SER_REG_MODE_AUTO = 2, 490 unsigned int sc_longcal_timer;
491 unsigned int sc_shortcal_timer;
492 unsigned int sc_resetcal_timer;
493 unsigned int sc_checkani_timer;
494 struct timer_list timer;
699}; 495};
700 496
701#define AR_PHY_CCA_MAX_GOOD_VALUE -85 497/********************/
702#define AR_PHY_CCA_MAX_HIGH_VALUE -62 498/* LED Control */
703#define AR_PHY_CCA_MIN_BAD_VALUE -121 499/********************/
704#define AR_PHY_CCA_FILTERWINDOW_LENGTH_INIT 3
705#define AR_PHY_CCA_FILTERWINDOW_LENGTH 5
706 500
707#define ATH9K_NF_CAL_HIST_MAX 5 501#define ATH_LED_PIN 1
708#define NUM_NF_READINGS 6 502#define ATH_LED_ON_DURATION_IDLE 350 /* in msecs */
503#define ATH_LED_OFF_DURATION_IDLE 250 /* in msecs */
709 504
710struct ath9k_nfcal_hist { 505enum ath_led_type {
711 int16_t nfCalBuffer[ATH9K_NF_CAL_HIST_MAX]; 506 ATH_LED_RADIO,
712 u8 currIndex; 507 ATH_LED_ASSOC,
713 int16_t privNF; 508 ATH_LED_TX,
714 u8 invalidNFcount; 509 ATH_LED_RX
715}; 510};
716 511
717struct ath9k_beacon_state { 512struct ath_led {
718 u32 bs_nexttbtt; 513 struct ath_softc *sc;
719 u32 bs_nextdtim; 514 struct led_classdev led_cdev;
720 u32 bs_intval; 515 enum ath_led_type led_type;
721#define ATH9K_BEACON_PERIOD 0x0000ffff 516 char name[32];
722#define ATH9K_BEACON_ENA 0x00800000 517 bool registered;
723#define ATH9K_BEACON_RESET_TSF 0x01000000
724 u32 bs_dtimperiod;
725 u16 bs_cfpperiod;
726 u16 bs_cfpmaxduration;
727 u32 bs_cfpnext;
728 u16 bs_timoffset;
729 u16 bs_bmissthreshold;
730 u32 bs_sleepduration;
731}; 518};
732 519
733struct ath9k_node_stats { 520/* Rfkill */
734 u32 ns_avgbrssi; 521#define ATH_RFKILL_POLL_INTERVAL 2000 /* msecs */
735 u32 ns_avgrssi;
736 u32 ns_avgtxrssi;
737 u32 ns_avgtxrate;
738};
739
740#define ATH9K_RSSI_EP_MULTIPLIER (1<<7)
741
742#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
743#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
744#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
745#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
746#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
747#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
748 522
749enum { 523struct ath_rfkill {
750 ATH9K_RESET_POWER_ON, 524 struct rfkill *rfkill;
751 ATH9K_RESET_WARM, 525 struct delayed_work rfkill_poll;
752 ATH9K_RESET_COLD, 526 char rfkill_name[32];
753}; 527};
754 528
755#define AH_USE_EEPROM 0x1 529/********************/
756 530/* Main driver core */
757struct ath_hal { 531/********************/
758 u32 ah_magic;
759 u16 ah_devid;
760 u16 ah_subvendorid;
761 u32 ah_macVersion;
762 u16 ah_macRev;
763 u16 ah_phyRev;
764 u16 ah_analog5GhzRev;
765 u16 ah_analog2GhzRev;
766
767 void __iomem *ah_sh;
768 struct ath_softc *ah_sc;
769
770 enum nl80211_iftype ah_opmode;
771 struct ath9k_ops_config ah_config;
772 struct ath9k_hw_capabilities ah_caps;
773
774 u16 ah_countryCode;
775 u32 ah_flags;
776 int16_t ah_powerLimit;
777 u16 ah_maxPowerLevel;
778 u32 ah_tpScale;
779 u16 ah_currentRD;
780 u16 ah_currentRDExt;
781 u16 ah_currentRDInUse;
782 char alpha2[2];
783 struct reg_dmn_pair_mapping *regpair;
784 enum ath9k_power_mode ah_power_mode;
785 enum ath9k_power_mode ah_restore_mode;
786
787 struct ath9k_channel ah_channels[38];
788 struct ath9k_channel *ah_curchan;
789
790 bool ah_isPciExpress;
791 u16 ah_txTrigLevel;
792 u16 ah_rfsilent;
793 u32 ah_rfkill_gpio;
794 u32 ah_rfkill_polarity;
795 u32 ah_btactive_gpio;
796 u32 ah_wlanactive_gpio;
797 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
798
799 bool sw_mgmt_crypto;
800};
801
802struct chan_centers {
803 u16 synth_center;
804 u16 ctl_center;
805 u16 ext_center;
806};
807 532
808struct ath_rate_table; 533/*
809 534 * Default cache line size, in bytes.
810/* Helpers */ 535 * Used when PCI device not fully initialized by bootrom/BIOS
811 536*/
812bool ath9k_hw_wait(struct ath_hal *ah, u32 reg, u32 mask, u32 val); 537#define DEFAULT_CACHELINE 32
813u32 ath9k_hw_reverse_bits(u32 val, u32 n); 538#define ATH_DEFAULT_NOISE_FLOOR -95
814bool ath9k_get_channel_edges(struct ath_hal *ah, 539#define ATH_REGCLASSIDS_MAX 10
815 u16 flags, u16 *low, 540#define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
816 u16 *high); 541#define ATH_MAX_SW_RETRIES 10
817u16 ath9k_hw_computetxtime(struct ath_hal *ah, 542#define ATH_CHAN_MAX 255
818 struct ath_rate_table *rates, 543#define IEEE80211_WEP_NKID 4 /* number of key ids */
819 u32 frameLen, u16 rateix,
820 bool shortPreamble);
821void ath9k_hw_get_channel_centers(struct ath_hal *ah,
822 struct ath9k_channel *chan,
823 struct chan_centers *centers);
824
825/* Attach, Detach */
826
827const char *ath9k_hw_probe(u16 vendorid, u16 devid);
828void ath9k_hw_detach(struct ath_hal *ah);
829struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc,
830 void __iomem *mem, int *error);
831void ath9k_hw_rfdetach(struct ath_hal *ah);
832
833
834/* HW Reset */
835
836int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
837 bool bChannelChange);
838
839/* Key Cache Management */
840
841bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry);
842bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac);
843bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
844 const struct ath9k_keyval *k,
845 const u8 *mac, int xorKey);
846bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry);
847
848/* Power Management */
849
850bool ath9k_hw_setpower(struct ath_hal *ah,
851 enum ath9k_power_mode mode);
852void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore);
853
854/* Beacon timers */
855
856void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period);
857void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
858 const struct ath9k_beacon_state *bs);
859/* HW Capabilities */
860
861bool ath9k_hw_fill_cap_info(struct ath_hal *ah);
862bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type,
863 u32 capability, u32 *result);
864bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type,
865 u32 capability, u32 setting, int *status);
866
867/* GPIO / RFKILL / Antennae */
868 544
869void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio); 545/*
870u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio); 546 * The key cache is used for h/w cipher state and also for
871void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio, 547 * tracking station state such as the current tx antenna.
872 u32 ah_signal_type); 548 * We also setup a mapping table between key cache slot indices
873void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val); 549 * and station state to short-circuit node lookups on rx.
874#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 550 * Different parts have different size key caches. We handle
875void ath9k_enable_rfkill(struct ath_hal *ah); 551 * up to ATH_KEYMAX entries (could dynamically allocate state).
552 */
553#define ATH_KEYMAX 128 /* max key cache size we handle */
554
555#define ATH_IF_ID_ANY 0xff
556#define ATH_TXPOWER_MAX 100 /* .5 dBm units */
557#define ATH_RSSI_DUMMY_MARKER 0x127
558#define ATH_RATE_DUMMY_MARKER 0
559
560#define SC_OP_INVALID BIT(0)
561#define SC_OP_BEACONS BIT(1)
562#define SC_OP_RXAGGR BIT(2)
563#define SC_OP_TXAGGR BIT(3)
564#define SC_OP_CHAINMASK_UPDATE BIT(4)
565#define SC_OP_FULL_RESET BIT(5)
566#define SC_OP_NO_RESET BIT(6)
567#define SC_OP_PREAMBLE_SHORT BIT(7)
568#define SC_OP_PROTECT_ENABLE BIT(8)
569#define SC_OP_RXFLUSH BIT(9)
570#define SC_OP_LED_ASSOCIATED BIT(10)
571#define SC_OP_RFKILL_REGISTERED BIT(11)
572#define SC_OP_RFKILL_SW_BLOCKED BIT(12)
573#define SC_OP_RFKILL_HW_BLOCKED BIT(13)
574#define SC_OP_WAIT_FOR_BEACON BIT(14)
575#define SC_OP_LED_ON BIT(15)
576
577struct ath_bus_ops {
578 void (*read_cachesize)(struct ath_softc *sc, int *csz);
579 void (*cleanup)(struct ath_softc *sc);
580 bool (*eeprom_read)(struct ath_hal *ah, u32 off, u16 *data);
581};
582
583struct ath_softc {
584 struct ieee80211_hw *hw;
585 struct device *dev;
586 struct tasklet_struct intr_tq;
587 struct tasklet_struct bcon_tasklet;
588 struct ath_hal *sc_ah;
589 void __iomem *mem;
590 int irq;
591 spinlock_t sc_resetlock;
592 struct mutex mutex;
593
594 u8 sc_curbssid[ETH_ALEN];
595 u8 sc_myaddr[ETH_ALEN];
596 u8 sc_bssidmask[ETH_ALEN];
597 u32 sc_intrstatus;
598 u32 sc_flags; /* SC_OP_* */
599 u16 sc_curtxpow;
600 u16 sc_curaid;
601 u16 sc_cachelsz;
602 u8 sc_nbcnvaps;
603 u16 sc_nvaps;
604 u8 sc_tx_chainmask;
605 u8 sc_rx_chainmask;
606 u32 sc_keymax;
607 DECLARE_BITMAP(sc_keymap, ATH_KEYMAX);
608 u8 sc_splitmic;
609 atomic_t ps_usecount;
610 enum ath9k_int sc_imask;
611 enum ath9k_ht_extprotspacing sc_ht_extprotspacing;
612 enum ath9k_ht_macmode tx_chan_width;
613
614 struct ath_config sc_config;
615 struct ath_rx rx;
616 struct ath_tx tx;
617 struct ath_beacon beacon;
618 struct ieee80211_vif *sc_vaps[ATH_BCBUF];
619 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX];
620 struct ath_rate_table *hw_rate_table[ATH9K_MODE_MAX];
621 struct ath_rate_table *cur_rate_table;
622 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
623
624 struct ath_led radio_led;
625 struct ath_led assoc_led;
626 struct ath_led tx_led;
627 struct ath_led rx_led;
628 struct delayed_work ath_led_blink_work;
629 int led_on_duration;
630 int led_off_duration;
631 int led_on_cnt;
632 int led_off_cnt;
633
634 struct ath_rfkill rf_kill;
635 struct ath_ani sc_ani;
636 struct ath9k_node_stats sc_halstats;
637#ifdef CONFIG_ATH9K_DEBUG
638 struct ath9k_debug sc_debug;
639#endif
640 struct ath_bus_ops *bus_ops;
641};
642
643int ath_reset(struct ath_softc *sc, bool retry_tx);
644int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
645int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
646int ath_cabq_update(struct ath_softc *);
647
648static inline void ath_read_cachesize(struct ath_softc *sc, int *csz)
649{
650 sc->bus_ops->read_cachesize(sc, csz);
651}
652
653static inline void ath_bus_cleanup(struct ath_softc *sc)
654{
655 sc->bus_ops->cleanup(sc);
656}
657
658extern struct ieee80211_ops ath9k_ops;
659
660irqreturn_t ath_isr(int irq, void *dev);
661void ath_cleanup(struct ath_softc *sc);
662int ath_attach(u16 devid, struct ath_softc *sc);
663void ath_detach(struct ath_softc *sc);
664const char *ath_mac_bb_name(u32 mac_bb_version);
665const char *ath_rf_name(u16 rf_version);
666
667#ifdef CONFIG_PCI
668int ath_pci_init(void);
669void ath_pci_exit(void);
670#else
671static inline int ath_pci_init(void) { return 0; };
672static inline void ath_pci_exit(void) {};
876#endif 673#endif
877u32 ath9k_hw_getdefantenna(struct ath_hal *ah);
878void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna);
879bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
880 enum ath9k_ant_setting settings,
881 struct ath9k_channel *chan,
882 u8 *tx_chainmask,
883 u8 *rx_chainmask,
884 u8 *antenna_cfgd);
885
886/* General Operation */
887
888u32 ath9k_hw_getrxfilter(struct ath_hal *ah);
889void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits);
890bool ath9k_hw_phy_disable(struct ath_hal *ah);
891bool ath9k_hw_disable(struct ath_hal *ah);
892bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit);
893void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac);
894bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac);
895void ath9k_hw_setopmode(struct ath_hal *ah);
896void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0, u32 filter1);
897void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask);
898bool ath9k_hw_setbssidmask(struct ath_hal *ah, const u8 *mask);
899void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid, u16 assocId);
900u64 ath9k_hw_gettsf64(struct ath_hal *ah);
901void ath9k_hw_settsf64(struct ath_hal *ah, u64 tsf64);
902void ath9k_hw_reset_tsf(struct ath_hal *ah);
903bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting);
904bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us);
905void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode);
906
907/* Regulatory */
908u16 ath9k_regd_get_rd(struct ath_hal *ah);
909bool ath9k_is_world_regd(struct ath_hal *ah);
910const struct ieee80211_regdomain *ath9k_world_regdomain(struct ath_hal *ah);
911const struct ieee80211_regdomain *ath9k_default_world_regdomain(void);
912
913void ath9k_reg_apply_world_flags(struct wiphy *wiphy, enum reg_set_by setby);
914void ath9k_reg_apply_radar_flags(struct wiphy *wiphy);
915
916int ath9k_regd_init(struct ath_hal *ah);
917bool ath9k_regd_is_eeprom_valid(struct ath_hal *ah);
918u32 ath9k_regd_get_ctl(struct ath_hal *ah, struct ath9k_channel *chan);
919int ath9k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request);
920
921/* ANI */
922
923void ath9k_ani_reset(struct ath_hal *ah);
924void ath9k_hw_ani_monitor(struct ath_hal *ah,
925 const struct ath9k_node_stats *stats,
926 struct ath9k_channel *chan);
927bool ath9k_hw_phycounters(struct ath_hal *ah);
928void ath9k_enable_mib_counters(struct ath_hal *ah);
929void ath9k_hw_disable_mib_counters(struct ath_hal *ah);
930u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
931 u32 *rxc_pcnt,
932 u32 *rxf_pcnt,
933 u32 *txf_pcnt);
934void ath9k_hw_procmibevent(struct ath_hal *ah,
935 const struct ath9k_node_stats *stats);
936void ath9k_hw_ani_setup(struct ath_hal *ah);
937void ath9k_hw_ani_attach(struct ath_hal *ah);
938void ath9k_hw_ani_detach(struct ath_hal *ah);
939
940/* Calibration */
941
942bool ath9k_hw_reset_calvalid(struct ath_hal *ah);
943void ath9k_hw_start_nfcal(struct ath_hal *ah);
944void ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan);
945int16_t ath9k_hw_getnf(struct ath_hal *ah,
946 struct ath9k_channel *chan);
947void ath9k_init_nfcal_hist_buffer(struct ath_hal *ah);
948s16 ath9k_hw_getchan_noise(struct ath_hal *ah, struct ath9k_channel *chan);
949bool ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan,
950 u8 rxchainmask, bool longcal,
951 bool *isCalDone);
952bool ath9k_hw_init_cal(struct ath_hal *ah,
953 struct ath9k_channel *chan);
954
955
956/* EEPROM */
957
958int ath9k_hw_set_txpower(struct ath_hal *ah,
959 struct ath9k_channel *chan,
960 u16 cfgCtl,
961 u8 twiceAntennaReduction,
962 u8 twiceMaxRegulatoryPower,
963 u8 powerLimit);
964void ath9k_hw_set_addac(struct ath_hal *ah, struct ath9k_channel *chan);
965bool ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
966 struct ath9k_channel *chan,
967 int16_t *ratesArray,
968 u16 cfgCtl,
969 u8 AntennaReduction,
970 u8 twiceMaxRegulatoryPower,
971 u8 powerLimit);
972bool ath9k_hw_set_power_cal_table(struct ath_hal *ah,
973 struct ath9k_channel *chan,
974 int16_t *pTxPowerIndexOffset);
975bool ath9k_hw_eeprom_set_board_values(struct ath_hal *ah,
976 struct ath9k_channel *chan);
977u16 ath9k_hw_get_eeprom_antenna_cfg(struct ath_hal *ah,
978 struct ath9k_channel *chan);
979u8 ath9k_hw_get_num_ant_config(struct ath_hal *ah,
980 enum ieee80211_band freq_band);
981u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah, u16 i, bool is2GHz);
982int ath9k_hw_eeprom_attach(struct ath_hal *ah);
983
984/* Interrupt Handling */
985
986bool ath9k_hw_intrpend(struct ath_hal *ah);
987bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked);
988enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah);
989enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints);
990
991/* MAC (PCU/QCU) */
992
993u32 ath9k_hw_gettxbuf(struct ath_hal *ah, u32 q);
994bool ath9k_hw_puttxbuf(struct ath_hal *ah, u32 q, u32 txdp);
995bool ath9k_hw_txstart(struct ath_hal *ah, u32 q);
996u32 ath9k_hw_numtxpending(struct ath_hal *ah, u32 q);
997bool ath9k_hw_updatetxtriglevel(struct ath_hal *ah, bool bIncTrigLevel);
998bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q);
999bool ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds,
1000 u32 segLen, bool firstSeg,
1001 bool lastSeg, const struct ath_desc *ds0);
1002void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds);
1003int ath9k_hw_txprocdesc(struct ath_hal *ah, struct ath_desc *ds);
1004void ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds,
1005 u32 pktLen, enum ath9k_pkt_type type, u32 txPower,
1006 u32 keyIx, enum ath9k_key_type keyType, u32 flags);
1007void ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds,
1008 struct ath_desc *lastds,
1009 u32 durUpdateEn, u32 rtsctsRate,
1010 u32 rtsctsDuration,
1011 struct ath9k_11n_rate_series series[],
1012 u32 nseries, u32 flags);
1013void ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds,
1014 u32 aggrLen);
1015void ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds,
1016 u32 numDelims);
1017void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds);
1018void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds);
1019void ath9k_hw_set11n_burstduration(struct ath_hal *ah, struct ath_desc *ds,
1020 u32 burstDuration);
1021void ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah, struct ath_desc *ds,
1022 u32 vmf);
1023void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u32 *txqs);
1024bool ath9k_hw_set_txq_props(struct ath_hal *ah, int q,
1025 const struct ath9k_tx_queue_info *qinfo);
1026bool ath9k_hw_get_txq_props(struct ath_hal *ah, int q,
1027 struct ath9k_tx_queue_info *qinfo);
1028int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type,
1029 const struct ath9k_tx_queue_info *qinfo);
1030bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q);
1031bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q);
1032int ath9k_hw_rxprocdesc(struct ath_hal *ah, struct ath_desc *ds,
1033 u32 pa, struct ath_desc *nds, u64 tsf);
1034bool ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds,
1035 u32 size, u32 flags);
1036bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set);
1037void ath9k_hw_putrxbuf(struct ath_hal *ah, u32 rxdp);
1038void ath9k_hw_rxena(struct ath_hal *ah);
1039void ath9k_hw_startpcureceive(struct ath_hal *ah);
1040void ath9k_hw_stoppcurecv(struct ath_hal *ah);
1041bool ath9k_hw_stopdmarecv(struct ath_hal *ah);
1042void ath9k_hw_btcoex_enable(struct ath_hal *ah);
1043 674
675#ifdef CONFIG_ATHEROS_AR71XX
676int ath_ahb_init(void);
677void ath_ahb_exit(void);
678#else
679static inline int ath_ahb_init(void) { return 0; };
680static inline void ath_ahb_exit(void) {};
1044#endif 681#endif
682
683static inline void ath9k_ps_wakeup(struct ath_softc *sc)
684{
685 if (atomic_inc_return(&sc->ps_usecount) == 1)
686 if (sc->sc_ah->ah_power_mode != ATH9K_PM_AWAKE) {
687 sc->sc_ah->ah_restore_mode = sc->sc_ah->ah_power_mode;
688 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
689 }
690}
691
692static inline void ath9k_ps_restore(struct ath_softc *sc)
693{
694 if (atomic_dec_and_test(&sc->ps_usecount))
695 if (sc->hw->conf.flags & IEEE80211_CONF_PS)
696 ath9k_hw_setpower(sc->sc_ah,
697 sc->sc_ah->ah_restore_mode);
698}
699#endif /* ATH9K_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 08:34:54 -0500