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path: root/drivers/net/wireless/ath9k/ath9k.h
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Diffstat (limited to 'drivers/net/wireless/ath9k/ath9k.h')
-rw-r--r--drivers/net/wireless/ath9k/ath9k.h144
1 files changed, 66 insertions, 78 deletions
diff --git a/drivers/net/wireless/ath9k/ath9k.h b/drivers/net/wireless/ath9k/ath9k.h
index 3cb7bf86410e..d60b2e726414 100644
--- a/drivers/net/wireless/ath9k/ath9k.h
+++ b/drivers/net/wireless/ath9k/ath9k.h
@@ -104,13 +104,13 @@ enum buffer_type {
104}; 104};
105 105
106struct ath_buf_state { 106struct ath_buf_state {
107 int bfs_nframes; /* # frames in aggregate */ 107 int bfs_nframes;
108 u16 bfs_al; /* length of aggregate */ 108 u16 bfs_al;
109 u16 bfs_frmlen; /* length of frame */ 109 u16 bfs_frmlen;
110 int bfs_seqno; /* sequence number */ 110 int bfs_seqno;
111 int bfs_tidno; /* tid of this frame */ 111 int bfs_tidno;
112 int bfs_retries; /* current retries */ 112 int bfs_retries;
113 u32 bf_type; /* BUF_* (enum buffer_type) */ 113 u32 bf_type;
114 u32 bfs_keyix; 114 u32 bfs_keyix;
115 enum ath9k_key_type bfs_keytype; 115 enum ath9k_key_type bfs_keytype;
116}; 116};
@@ -129,10 +129,6 @@ struct ath_buf_state {
129#define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY) 129#define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY)
130#define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY) 130#define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY)
131 131
132/*
133 * Abstraction of a contiguous buffer to transmit/receive. There is only
134 * a single hw descriptor encapsulated here.
135 */
136struct ath_buf { 132struct ath_buf {
137 struct list_head list; 133 struct list_head list;
138 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or 134 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
@@ -143,22 +139,20 @@ struct ath_buf {
143 dma_addr_t bf_daddr; /* physical addr of desc */ 139 dma_addr_t bf_daddr; /* physical addr of desc */
144 dma_addr_t bf_buf_addr; /* physical addr of data buffer */ 140 dma_addr_t bf_buf_addr; /* physical addr of data buffer */
145 u32 bf_status; 141 u32 bf_status;
146 u16 bf_flags; /* tx descriptor flags */ 142 u16 bf_flags;
147 struct ath_buf_state bf_state; /* buffer state */ 143 struct ath_buf_state bf_state;
148 dma_addr_t bf_dmacontext; 144 dma_addr_t bf_dmacontext;
149}; 145};
150 146
151#define ATH_RXBUF_RESET(_bf) ((_bf)->bf_status = 0) 147#define ATH_RXBUF_RESET(_bf) ((_bf)->bf_status = 0)
152#define ATH_BUFSTATUS_STALE 0x00000002 148#define ATH_BUFSTATUS_STALE 0x00000002
153 149
154/* DMA state for tx/rx descriptors */
155
156struct ath_descdma { 150struct ath_descdma {
157 const char *dd_name; 151 const char *dd_name;
158 struct ath_desc *dd_desc; /* descriptors */ 152 struct ath_desc *dd_desc;
159 dma_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 153 dma_addr_t dd_desc_paddr;
160 u32 dd_desc_len; /* size of dd_desc */ 154 u32 dd_desc_len;
161 struct ath_buf *dd_bufptr; /* associated buffers */ 155 struct ath_buf *dd_bufptr;
162 dma_addr_t dd_dmacontext; 156 dma_addr_t dd_dmacontext;
163}; 157};
164 158
@@ -246,15 +240,15 @@ enum ATH_AGGR_STATUS {
246}; 240};
247 241
248struct ath_txq { 242struct ath_txq {
249 u32 axq_qnum; /* hardware q number */ 243 u32 axq_qnum;
250 u32 *axq_link; /* link ptr in last TX desc */ 244 u32 *axq_link;
251 struct list_head axq_q; /* transmit queue */ 245 struct list_head axq_q;
252 spinlock_t axq_lock; 246 spinlock_t axq_lock;
253 u32 axq_depth; /* queue depth */ 247 u32 axq_depth;
254 u8 axq_aggr_depth; /* aggregates queued */ 248 u8 axq_aggr_depth;
255 u32 axq_totalqueued; /* total ever queued */ 249 u32 axq_totalqueued;
256 bool stopped; /* Is mac80211 queue stopped ? */ 250 bool stopped;
257 struct ath_buf *axq_linkbuf; /* virtual addr of last buffer*/ 251 struct ath_buf *axq_linkbuf;
258 252
259 /* first desc of the last descriptor that contains CTS */ 253 /* first desc of the last descriptor that contains CTS */
260 struct ath_desc *axq_lastdsWithCTS; 254 struct ath_desc *axq_lastdsWithCTS;
@@ -270,45 +264,39 @@ struct ath_txq {
270#define AGGR_ADDBA_COMPLETE BIT(2) 264#define AGGR_ADDBA_COMPLETE BIT(2)
271#define AGGR_ADDBA_PROGRESS BIT(3) 265#define AGGR_ADDBA_PROGRESS BIT(3)
272 266
273/* per TID aggregate tx state for a destination */
274struct ath_atx_tid { 267struct ath_atx_tid {
275 struct list_head list; /* round-robin tid entry */ 268 struct list_head list;
276 struct list_head buf_q; /* pending buffers */ 269 struct list_head buf_q;
277 struct ath_node *an; 270 struct ath_node *an;
278 struct ath_atx_ac *ac; 271 struct ath_atx_ac *ac;
279 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; /* active tx frames */ 272 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS];
280 u16 seq_start; 273 u16 seq_start;
281 u16 seq_next; 274 u16 seq_next;
282 u16 baw_size; 275 u16 baw_size;
283 int tidno; 276 int tidno;
284 int baw_head; /* first un-acked tx buffer */ 277 int baw_head; /* first un-acked tx buffer */
285 int baw_tail; /* next unused tx buffer slot */ 278 int baw_tail; /* next unused tx buffer slot */
286 int sched; 279 int sched;
287 int paused; 280 int paused;
288 u8 state; 281 u8 state;
289 int addba_exchangeattempts; 282 int addba_exchangeattempts;
290}; 283};
291 284
292/* per access-category aggregate tx state for a destination */
293struct ath_atx_ac { 285struct ath_atx_ac {
294 int sched; /* dest-ac is scheduled */ 286 int sched;
295 int qnum; /* H/W queue number associated 287 int qnum;
296 with this AC */ 288 struct list_head list;
297 struct list_head list; /* round-robin txq entry */ 289 struct list_head tid_q;
298 struct list_head tid_q; /* queue of TIDs with buffers */
299}; 290};
300 291
301/* per-frame tx control block */
302struct ath_tx_control { 292struct ath_tx_control {
303 struct ath_txq *txq; 293 struct ath_txq *txq;
304 int if_id; 294 int if_id;
305}; 295};
306 296
307/* per frame tx status block */
308struct ath_xmit_status { 297struct ath_xmit_status {
309 int retries; /* number of retries to successufully 298 int retries;
310 transmit this frame */ 299 int flags;
311 int flags; /* status of transmit */
312#define ATH_TX_ERROR 0x01 300#define ATH_TX_ERROR 0x01
313#define ATH_TX_XRETRY 0x02 301#define ATH_TX_XRETRY 0x02
314#define ATH_TX_BAR 0x04 302#define ATH_TX_BAR 0x04
@@ -396,21 +384,21 @@ int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
396void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); 384void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
397 385
398/********/ 386/********/
399/* VAPs */ 387/* VIFs */
400/********/ 388/********/
401 389
402/* 390/*
403 * Define the scheme that we select MAC address for multiple 391 * Define the scheme that we select MAC address for multiple
404 * BSS on the same radio. The very first VAP will just use the MAC 392 * BSS on the same radio. The very first VIF will just use the MAC
405 * address from the EEPROM. For the next 3 VAPs, we set the 393 * address from the EEPROM. For the next 3 VIFs, we set the
406 * U/L bit (bit 1) in MAC address, and use the next two bits as the 394 * U/L bit (bit 1) in MAC address, and use the next two bits as the
407 * index of the VAP. 395 * index of the VIF.
408 */ 396 */
409 397
410#define ATH_SET_VAP_BSSID_MASK(bssid_mask) \ 398#define ATH_SET_VIF_BSSID_MASK(bssid_mask) \
411 ((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02)) 399 ((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02))
412 400
413struct ath_vap { 401struct ath_vif {
414 int av_bslot; 402 int av_bslot;
415 enum nl80211_iftype av_opmode; 403 enum nl80211_iftype av_opmode;
416 struct ath_buf *av_bcbuf; 404 struct ath_buf *av_bcbuf;
@@ -469,7 +457,7 @@ void ath9k_beacon_tasklet(unsigned long data);
469void ath_beacon_config(struct ath_softc *sc, int if_id); 457void ath_beacon_config(struct ath_softc *sc, int if_id);
470int ath_beaconq_setup(struct ath_hal *ah); 458int ath_beaconq_setup(struct ath_hal *ah);
471int ath_beacon_alloc(struct ath_softc *sc, int if_id); 459int ath_beacon_alloc(struct ath_softc *sc, int if_id);
472void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp); 460void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp);
473void ath_beacon_sync(struct ath_softc *sc, int if_id); 461void ath_beacon_sync(struct ath_softc *sc, int if_id);
474 462
475/*******/ 463/*******/
@@ -485,12 +473,12 @@ void ath_beacon_sync(struct ath_softc *sc, int if_id);
485#define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes between calibrations */ 473#define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes between calibrations */
486 474
487struct ath_ani { 475struct ath_ani {
488 bool sc_caldone; 476 bool caldone;
489 int16_t sc_noise_floor; 477 int16_t noise_floor;
490 unsigned int sc_longcal_timer; 478 unsigned int longcal_timer;
491 unsigned int sc_shortcal_timer; 479 unsigned int shortcal_timer;
492 unsigned int sc_resetcal_timer; 480 unsigned int resetcal_timer;
493 unsigned int sc_checkani_timer; 481 unsigned int checkani_timer;
494 struct timer_list timer; 482 struct timer_list timer;
495}; 483};
496 484
@@ -591,31 +579,31 @@ struct ath_softc {
591 spinlock_t sc_resetlock; 579 spinlock_t sc_resetlock;
592 struct mutex mutex; 580 struct mutex mutex;
593 581
594 u8 sc_curbssid[ETH_ALEN]; 582 u8 curbssid[ETH_ALEN];
595 u8 sc_myaddr[ETH_ALEN]; 583 u8 macaddr[ETH_ALEN];
596 u8 sc_bssidmask[ETH_ALEN]; 584 u8 bssidmask[ETH_ALEN];
597 u32 sc_intrstatus; 585 u32 intrstatus;
598 u32 sc_flags; /* SC_OP_* */ 586 u32 sc_flags; /* SC_OP_* */
599 u16 sc_curtxpow; 587 u16 curtxpow;
600 u16 sc_curaid; 588 u16 curaid;
601 u16 sc_cachelsz; 589 u16 cachelsz;
602 u8 sc_nbcnvaps; 590 u8 nbcnvifs;
603 u16 sc_nvaps; 591 u16 nvifs;
604 u8 sc_tx_chainmask; 592 u8 tx_chainmask;
605 u8 sc_rx_chainmask; 593 u8 rx_chainmask;
606 u32 sc_keymax; 594 u32 keymax;
607 DECLARE_BITMAP(sc_keymap, ATH_KEYMAX); 595 DECLARE_BITMAP(keymap, ATH_KEYMAX);
608 u8 sc_splitmic; 596 u8 splitmic;
609 atomic_t ps_usecount; 597 atomic_t ps_usecount;
610 enum ath9k_int sc_imask; 598 enum ath9k_int imask;
611 enum ath9k_ht_extprotspacing sc_ht_extprotspacing; 599 enum ath9k_ht_extprotspacing ht_extprotspacing;
612 enum ath9k_ht_macmode tx_chan_width; 600 enum ath9k_ht_macmode tx_chan_width;
613 601
614 struct ath_config sc_config; 602 struct ath_config config;
615 struct ath_rx rx; 603 struct ath_rx rx;
616 struct ath_tx tx; 604 struct ath_tx tx;
617 struct ath_beacon beacon; 605 struct ath_beacon beacon;
618 struct ieee80211_vif *sc_vaps[ATH_BCBUF]; 606 struct ieee80211_vif *vifs[ATH_BCBUF];
619 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX]; 607 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX];
620 struct ath_rate_table *hw_rate_table[ATH9K_MODE_MAX]; 608 struct ath_rate_table *hw_rate_table[ATH9K_MODE_MAX];
621 struct ath_rate_table *cur_rate_table; 609 struct ath_rate_table *cur_rate_table;
@@ -632,10 +620,10 @@ struct ath_softc {
632 int led_off_cnt; 620 int led_off_cnt;
633 621
634 struct ath_rfkill rf_kill; 622 struct ath_rfkill rf_kill;
635 struct ath_ani sc_ani; 623 struct ath_ani ani;
636 struct ath9k_node_stats sc_halstats; 624 struct ath9k_node_stats nodestats;
637#ifdef CONFIG_ATH9K_DEBUG 625#ifdef CONFIG_ATH9K_DEBUG
638 struct ath9k_debug sc_debug; 626 struct ath9k_debug debug;
639#endif 627#endif
640 struct ath_bus_ops *bus_ops; 628 struct ath_bus_ops *bus_ops;
641}; 629};