diff options
Diffstat (limited to 'drivers/net/wireless/ath5k')
-rw-r--r-- | drivers/net/wireless/ath5k/Makefile | 2 | ||||
-rw-r--r-- | drivers/net/wireless/ath5k/ath5k.h | 100 | ||||
-rw-r--r-- | drivers/net/wireless/ath5k/base.c | 346 | ||||
-rw-r--r-- | drivers/net/wireless/ath5k/base.h | 14 | ||||
-rw-r--r-- | drivers/net/wireless/ath5k/hw.c | 170 | ||||
-rw-r--r-- | drivers/net/wireless/ath5k/initvals.c | 2 | ||||
-rw-r--r-- | drivers/net/wireless/ath5k/phy.c | 66 |
7 files changed, 329 insertions, 371 deletions
diff --git a/drivers/net/wireless/ath5k/Makefile b/drivers/net/wireless/ath5k/Makefile index 321641f99e13..ada1095d4ef1 100644 --- a/drivers/net/wireless/ath5k/Makefile +++ b/drivers/net/wireless/ath5k/Makefile | |||
@@ -1,2 +1,2 @@ | |||
1 | ath5k-objs = base.o hw.o regdom.o initvals.o phy.o debug.o | 1 | ath5k-objs = base.o hw.o initvals.o phy.o debug.o |
2 | obj-$(CONFIG_ATH5K) += ath5k.o | 2 | obj-$(CONFIG_ATH5K) += ath5k.o |
diff --git a/drivers/net/wireless/ath5k/ath5k.h b/drivers/net/wireless/ath5k/ath5k.h index 69dea3392612..9ea8c549b781 100644 --- a/drivers/net/wireless/ath5k/ath5k.h +++ b/drivers/net/wireless/ath5k/ath5k.h | |||
@@ -30,7 +30,6 @@ | |||
30 | #include <net/mac80211.h> | 30 | #include <net/mac80211.h> |
31 | 31 | ||
32 | #include "hw.h" | 32 | #include "hw.h" |
33 | #include "regdom.h" | ||
34 | 33 | ||
35 | /* PCI IDs */ | 34 | /* PCI IDs */ |
36 | #define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */ | 35 | #define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */ |
@@ -251,18 +250,20 @@ struct ath5k_srev_name { | |||
251 | */ | 250 | */ |
252 | #define MODULATION_TURBO 0x00000080 | 251 | #define MODULATION_TURBO 0x00000080 |
253 | 252 | ||
254 | enum ath5k_vendor_mode { | 253 | enum ath5k_driver_mode { |
255 | MODE_ATHEROS_TURBO = NUM_IEEE80211_MODES+1, | 254 | AR5K_MODE_11A = 0, |
256 | MODE_ATHEROS_TURBOG | 255 | AR5K_MODE_11A_TURBO = 1, |
256 | AR5K_MODE_11B = 2, | ||
257 | AR5K_MODE_11G = 3, | ||
258 | AR5K_MODE_11G_TURBO = 4, | ||
259 | AR5K_MODE_XR = 0, | ||
260 | AR5K_MODE_MAX = 5 | ||
257 | }; | 261 | }; |
258 | 262 | ||
259 | /* Number of supported mac80211 enum ieee80211_phymode modes by this driver */ | ||
260 | #define NUM_DRIVER_MODES 3 | ||
261 | |||
262 | /* adding this flag to rate_code enables short preamble, see ar5212_reg.h */ | 263 | /* adding this flag to rate_code enables short preamble, see ar5212_reg.h */ |
263 | #define AR5K_SET_SHORT_PREAMBLE 0x04 | 264 | #define AR5K_SET_SHORT_PREAMBLE 0x04 |
264 | 265 | ||
265 | #define HAS_SHPREAMBLE(_ix) (rt->rates[_ix].modulation == IEEE80211_RATE_CCK_2) | 266 | #define HAS_SHPREAMBLE(_ix) (rt->rates[_ix].modulation == IEEE80211_RATE_SHORT_PREAMBLE) |
266 | #define SHPREAMBLE_FLAG(_ix) (HAS_SHPREAMBLE(_ix) ? AR5K_SET_SHORT_PREAMBLE : 0) | 267 | #define SHPREAMBLE_FLAG(_ix) (HAS_SHPREAMBLE(_ix) ? AR5K_SET_SHORT_PREAMBLE : 0) |
267 | 268 | ||
268 | /****************\ | 269 | /****************\ |
@@ -560,8 +561,8 @@ struct ath5k_desc { | |||
560 | * Used internaly in OpenHAL (ar5211.c/ar5212.c | 561 | * Used internaly in OpenHAL (ar5211.c/ar5212.c |
561 | * for reset_tx_queue). Also see struct struct ieee80211_channel. | 562 | * for reset_tx_queue). Also see struct struct ieee80211_channel. |
562 | */ | 563 | */ |
563 | #define IS_CHAN_XR(_c) ((_c.val & CHANNEL_XR) != 0) | 564 | #define IS_CHAN_XR(_c) ((_c.hw_value & CHANNEL_XR) != 0) |
564 | #define IS_CHAN_B(_c) ((_c.val & CHANNEL_B) != 0) | 565 | #define IS_CHAN_B(_c) ((_c.hw_value & CHANNEL_B) != 0) |
565 | 566 | ||
566 | /* | 567 | /* |
567 | * The following structure will be used to map 2GHz channels to | 568 | * The following structure will be used to map 2GHz channels to |
@@ -584,7 +585,7 @@ struct ath5k_athchan_2ghz { | |||
584 | 585 | ||
585 | /** | 586 | /** |
586 | * struct ath5k_rate - rate structure | 587 | * struct ath5k_rate - rate structure |
587 | * @valid: is this a valid rate for the current mode | 588 | * @valid: is this a valid rate for rate control (remove) |
588 | * @modulation: respective mac80211 modulation | 589 | * @modulation: respective mac80211 modulation |
589 | * @rate_kbps: rate in kbit/s | 590 | * @rate_kbps: rate in kbit/s |
590 | * @rate_code: hardware rate value, used in &struct ath5k_desc, on RX on | 591 | * @rate_code: hardware rate value, used in &struct ath5k_desc, on RX on |
@@ -643,47 +644,48 @@ struct ath5k_rate_table { | |||
643 | 644 | ||
644 | /* | 645 | /* |
645 | * Rate tables... | 646 | * Rate tables... |
647 | * TODO: CLEAN THIS !!! | ||
646 | */ | 648 | */ |
647 | #define AR5K_RATES_11A { 8, { \ | 649 | #define AR5K_RATES_11A { 8, { \ |
648 | 255, 255, 255, 255, 255, 255, 255, 255, 6, 4, 2, 0, \ | 650 | 255, 255, 255, 255, 255, 255, 255, 255, 6, 4, 2, 0, \ |
649 | 7, 5, 3, 1, 255, 255, 255, 255, 255, 255, 255, 255, \ | 651 | 7, 5, 3, 1, 255, 255, 255, 255, 255, 255, 255, 255, \ |
650 | 255, 255, 255, 255, 255, 255, 255, 255 }, { \ | 652 | 255, 255, 255, 255, 255, 255, 255, 255 }, { \ |
651 | { 1, IEEE80211_RATE_OFDM, 6000, 11, 140, 0 }, \ | 653 | { 1, 0, 6000, 11, 140, 0 }, \ |
652 | { 1, IEEE80211_RATE_OFDM, 9000, 15, 18, 0 }, \ | 654 | { 1, 0, 9000, 15, 18, 0 }, \ |
653 | { 1, IEEE80211_RATE_OFDM, 12000, 10, 152, 2 }, \ | 655 | { 1, 0, 12000, 10, 152, 2 }, \ |
654 | { 1, IEEE80211_RATE_OFDM, 18000, 14, 36, 2 }, \ | 656 | { 1, 0, 18000, 14, 36, 2 }, \ |
655 | { 1, IEEE80211_RATE_OFDM, 24000, 9, 176, 4 }, \ | 657 | { 1, 0, 24000, 9, 176, 4 }, \ |
656 | { 1, IEEE80211_RATE_OFDM, 36000, 13, 72, 4 }, \ | 658 | { 1, 0, 36000, 13, 72, 4 }, \ |
657 | { 1, IEEE80211_RATE_OFDM, 48000, 8, 96, 4 }, \ | 659 | { 1, 0, 48000, 8, 96, 4 }, \ |
658 | { 1, IEEE80211_RATE_OFDM, 54000, 12, 108, 4 } } \ | 660 | { 1, 0, 54000, 12, 108, 4 } } \ |
659 | } | 661 | } |
660 | 662 | ||
661 | #define AR5K_RATES_11B { 4, { \ | 663 | #define AR5K_RATES_11B { 4, { \ |
662 | 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, \ | 664 | 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, \ |
663 | 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, \ | 665 | 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, \ |
664 | 3, 2, 1, 0, 255, 255, 255, 255 }, { \ | 666 | 3, 2, 1, 0, 255, 255, 255, 255 }, { \ |
665 | { 1, IEEE80211_RATE_CCK, 1000, 27, 130, 0 }, \ | 667 | { 1, 0, 1000, 27, 130, 0 }, \ |
666 | { 1, IEEE80211_RATE_CCK_2, 2000, 26, 132, 1 }, \ | 668 | { 1, IEEE80211_RATE_SHORT_PREAMBLE, 2000, 26, 132, 1 }, \ |
667 | { 1, IEEE80211_RATE_CCK_2, 5500, 25, 139, 1 }, \ | 669 | { 1, IEEE80211_RATE_SHORT_PREAMBLE, 5500, 25, 139, 1 }, \ |
668 | { 1, IEEE80211_RATE_CCK_2, 11000, 24, 150, 1 } } \ | 670 | { 1, IEEE80211_RATE_SHORT_PREAMBLE, 11000, 24, 150, 1 } } \ |
669 | } | 671 | } |
670 | 672 | ||
671 | #define AR5K_RATES_11G { 12, { \ | 673 | #define AR5K_RATES_11G { 12, { \ |
672 | 255, 255, 255, 255, 255, 255, 255, 255, 10, 8, 6, 4, \ | 674 | 255, 255, 255, 255, 255, 255, 255, 255, 10, 8, 6, 4, \ |
673 | 11, 9, 7, 5, 255, 255, 255, 255, 255, 255, 255, 255, \ | 675 | 11, 9, 7, 5, 255, 255, 255, 255, 255, 255, 255, 255, \ |
674 | 3, 2, 1, 0, 255, 255, 255, 255 }, { \ | 676 | 3, 2, 1, 0, 255, 255, 255, 255 }, { \ |
675 | { 1, IEEE80211_RATE_CCK, 1000, 27, 2, 0 }, \ | 677 | { 1, 0, 1000, 27, 2, 0 }, \ |
676 | { 1, IEEE80211_RATE_CCK_2, 2000, 26, 4, 1 }, \ | 678 | { 1, IEEE80211_RATE_SHORT_PREAMBLE, 2000, 26, 4, 1 }, \ |
677 | { 1, IEEE80211_RATE_CCK_2, 5500, 25, 11, 1 }, \ | 679 | { 1, IEEE80211_RATE_SHORT_PREAMBLE, 5500, 25, 11, 1 }, \ |
678 | { 1, IEEE80211_RATE_CCK_2, 11000, 24, 22, 1 }, \ | 680 | { 1, IEEE80211_RATE_SHORT_PREAMBLE, 11000, 24, 22, 1 }, \ |
679 | { 0, IEEE80211_RATE_OFDM, 6000, 11, 12, 4 }, \ | 681 | { 0, 0, 6000, 11, 12, 4 }, \ |
680 | { 0, IEEE80211_RATE_OFDM, 9000, 15, 18, 4 }, \ | 682 | { 0, 0, 9000, 15, 18, 4 }, \ |
681 | { 1, IEEE80211_RATE_OFDM, 12000, 10, 24, 6 }, \ | 683 | { 1, 0, 12000, 10, 24, 6 }, \ |
682 | { 1, IEEE80211_RATE_OFDM, 18000, 14, 36, 6 }, \ | 684 | { 1, 0, 18000, 14, 36, 6 }, \ |
683 | { 1, IEEE80211_RATE_OFDM, 24000, 9, 48, 8 }, \ | 685 | { 1, 0, 24000, 9, 48, 8 }, \ |
684 | { 1, IEEE80211_RATE_OFDM, 36000, 13, 72, 8 }, \ | 686 | { 1, 0, 36000, 13, 72, 8 }, \ |
685 | { 1, IEEE80211_RATE_OFDM, 48000, 8, 96, 8 }, \ | 687 | { 1, 0, 48000, 8, 96, 8 }, \ |
686 | { 1, IEEE80211_RATE_OFDM, 54000, 12, 108, 8 } } \ | 688 | { 1, 0, 54000, 12, 108, 8 } } \ |
687 | } | 689 | } |
688 | 690 | ||
689 | #define AR5K_RATES_TURBO { 8, { \ | 691 | #define AR5K_RATES_TURBO { 8, { \ |
@@ -708,14 +710,14 @@ struct ath5k_rate_table { | |||
708 | { 1, MODULATION_XR, 1000, 2, 139, 1 }, \ | 710 | { 1, MODULATION_XR, 1000, 2, 139, 1 }, \ |
709 | { 1, MODULATION_XR, 2000, 6, 150, 2 }, \ | 711 | { 1, MODULATION_XR, 2000, 6, 150, 2 }, \ |
710 | { 1, MODULATION_XR, 3000, 1, 150, 3 }, \ | 712 | { 1, MODULATION_XR, 3000, 1, 150, 3 }, \ |
711 | { 1, IEEE80211_RATE_OFDM, 6000, 11, 140, 4 }, \ | 713 | { 1, 0, 6000, 11, 140, 4 }, \ |
712 | { 1, IEEE80211_RATE_OFDM, 9000, 15, 18, 4 }, \ | 714 | { 1, 0, 9000, 15, 18, 4 }, \ |
713 | { 1, IEEE80211_RATE_OFDM, 12000, 10, 152, 6 }, \ | 715 | { 1, 0, 12000, 10, 152, 6 }, \ |
714 | { 1, IEEE80211_RATE_OFDM, 18000, 14, 36, 6 }, \ | 716 | { 1, 0, 18000, 14, 36, 6 }, \ |
715 | { 1, IEEE80211_RATE_OFDM, 24000, 9, 176, 8 }, \ | 717 | { 1, 0, 24000, 9, 176, 8 }, \ |
716 | { 1, IEEE80211_RATE_OFDM, 36000, 13, 72, 8 }, \ | 718 | { 1, 0, 36000, 13, 72, 8 }, \ |
717 | { 1, IEEE80211_RATE_OFDM, 48000, 8, 96, 8 }, \ | 719 | { 1, 0, 48000, 8, 96, 8 }, \ |
718 | { 1, IEEE80211_RATE_OFDM, 54000, 12, 108, 8 } } \ | 720 | { 1, 0, 54000, 12, 108, 8 } } \ |
719 | } | 721 | } |
720 | 722 | ||
721 | /* | 723 | /* |
@@ -895,7 +897,7 @@ struct ath5k_capabilities { | |||
895 | * Supported PHY modes | 897 | * Supported PHY modes |
896 | * (ie. CHANNEL_A, CHANNEL_B, ...) | 898 | * (ie. CHANNEL_A, CHANNEL_B, ...) |
897 | */ | 899 | */ |
898 | DECLARE_BITMAP(cap_mode, NUM_DRIVER_MODES); | 900 | DECLARE_BITMAP(cap_mode, AR5K_MODE_MAX); |
899 | 901 | ||
900 | /* | 902 | /* |
901 | * Frequency range (without regulation restrictions) | 903 | * Frequency range (without regulation restrictions) |
@@ -908,14 +910,6 @@ struct ath5k_capabilities { | |||
908 | } cap_range; | 910 | } cap_range; |
909 | 911 | ||
910 | /* | 912 | /* |
911 | * Active regulation domain settings | ||
912 | */ | ||
913 | struct { | ||
914 | enum ath5k_regdom reg_current; | ||
915 | enum ath5k_regdom reg_hw; | ||
916 | } cap_regdomain; | ||
917 | |||
918 | /* | ||
919 | * Values stored in the EEPROM (some of them...) | 913 | * Values stored in the EEPROM (some of them...) |
920 | */ | 914 | */ |
921 | struct ath5k_eeprom_info cap_eeprom; | 915 | struct ath5k_eeprom_info cap_eeprom; |
@@ -1129,8 +1123,6 @@ extern int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio); | |||
1129 | extern u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio); | 1123 | extern u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio); |
1130 | extern int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val); | 1124 | extern int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val); |
1131 | extern void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio, u32 interrupt_level); | 1125 | extern void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio, u32 interrupt_level); |
1132 | /* Regulatory Domain/Channels Setup */ | ||
1133 | extern u16 ath5k_get_regdomain(struct ath5k_hw *ah); | ||
1134 | /* Misc functions */ | 1126 | /* Misc functions */ |
1135 | extern int ath5k_hw_get_capability(struct ath5k_hw *ah, enum ath5k_capability_type cap_type, u32 capability, u32 *result); | 1127 | extern int ath5k_hw_get_capability(struct ath5k_hw *ah, enum ath5k_capability_type cap_type, u32 capability, u32 *result); |
1136 | 1128 | ||
diff --git a/drivers/net/wireless/ath5k/base.c b/drivers/net/wireless/ath5k/base.c index bef967ce34a6..52e55f67b735 100644 --- a/drivers/net/wireless/ath5k/base.c +++ b/drivers/net/wireless/ath5k/base.c | |||
@@ -240,6 +240,8 @@ static int ath5k_chan_set(struct ath5k_softc *sc, | |||
240 | static void ath5k_setcurmode(struct ath5k_softc *sc, | 240 | static void ath5k_setcurmode(struct ath5k_softc *sc, |
241 | unsigned int mode); | 241 | unsigned int mode); |
242 | static void ath5k_mode_setup(struct ath5k_softc *sc); | 242 | static void ath5k_mode_setup(struct ath5k_softc *sc); |
243 | static void ath5k_set_total_hw_rates(struct ath5k_softc *sc); | ||
244 | |||
243 | /* Descriptor setup */ | 245 | /* Descriptor setup */ |
244 | static int ath5k_desc_alloc(struct ath5k_softc *sc, | 246 | static int ath5k_desc_alloc(struct ath5k_softc *sc, |
245 | struct pci_dev *pdev); | 247 | struct pci_dev *pdev); |
@@ -515,12 +517,12 @@ ath5k_pci_probe(struct pci_dev *pdev, | |||
515 | /* Single chip radio (!RF5111) */ | 517 | /* Single chip radio (!RF5111) */ |
516 | if(sc->ah->ah_radio_5ghz_revision && !sc->ah->ah_radio_2ghz_revision) { | 518 | if(sc->ah->ah_radio_5ghz_revision && !sc->ah->ah_radio_2ghz_revision) { |
517 | /* No 5GHz support -> report 2GHz radio */ | 519 | /* No 5GHz support -> report 2GHz radio */ |
518 | if(!test_bit(MODE_IEEE80211A, sc->ah->ah_capabilities.cap_mode)){ | 520 | if(!test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)){ |
519 | ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n", | 521 | ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n", |
520 | ath5k_chip_name(AR5K_VERSION_RAD,sc->ah->ah_radio_5ghz_revision), | 522 | ath5k_chip_name(AR5K_VERSION_RAD,sc->ah->ah_radio_5ghz_revision), |
521 | sc->ah->ah_radio_5ghz_revision); | 523 | sc->ah->ah_radio_5ghz_revision); |
522 | /* No 2GHz support (5110 and some 5Ghz only cards) -> report 5Ghz radio */ | 524 | /* No 2GHz support (5110 and some 5Ghz only cards) -> report 5Ghz radio */ |
523 | } else if(!test_bit(MODE_IEEE80211B, sc->ah->ah_capabilities.cap_mode)){ | 525 | } else if(!test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)){ |
524 | ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n", | 526 | ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n", |
525 | ath5k_chip_name(AR5K_VERSION_RAD,sc->ah->ah_radio_5ghz_revision), | 527 | ath5k_chip_name(AR5K_VERSION_RAD,sc->ah->ah_radio_5ghz_revision), |
526 | sc->ah->ah_radio_5ghz_revision); | 528 | sc->ah->ah_radio_5ghz_revision); |
@@ -693,11 +695,14 @@ ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) | |||
693 | goto err; | 695 | goto err; |
694 | } | 696 | } |
695 | 697 | ||
698 | /* Set *_rates so we can map hw rate index */ | ||
699 | ath5k_set_total_hw_rates(sc); | ||
700 | |||
696 | /* NB: setup here so ath5k_rate_update is happy */ | 701 | /* NB: setup here so ath5k_rate_update is happy */ |
697 | if (test_bit(MODE_IEEE80211A, ah->ah_modes)) | 702 | if (test_bit(AR5K_MODE_11A, ah->ah_modes)) |
698 | ath5k_setcurmode(sc, MODE_IEEE80211A); | 703 | ath5k_setcurmode(sc, AR5K_MODE_11A); |
699 | else | 704 | else |
700 | ath5k_setcurmode(sc, MODE_IEEE80211B); | 705 | ath5k_setcurmode(sc, AR5K_MODE_11B); |
701 | 706 | ||
702 | /* | 707 | /* |
703 | * Allocate tx+rx descriptors and populate the lists. | 708 | * Allocate tx+rx descriptors and populate the lists. |
@@ -837,12 +842,9 @@ ath5k_copy_rates(struct ieee80211_rate *rates, | |||
837 | return 0; | 842 | return 0; |
838 | 843 | ||
839 | for (i = 0, count = 0; i < rt->rate_count && max > 0; i++) { | 844 | for (i = 0, count = 0; i < rt->rate_count && max > 0; i++) { |
840 | if (!rt->rates[i].valid) | 845 | rates[count].bitrate = rt->rates[i].rate_kbps / 100; |
841 | continue; | 846 | rates[count].hw_value = rt->rates[i].rate_code; |
842 | rates->rate = rt->rates[i].rate_kbps / 100; | 847 | rates[count].flags = rt->rates[i].modulation; |
843 | rates->val = rt->rates[i].rate_code; | ||
844 | rates->flags = rt->rates[i].modulation; | ||
845 | rates++; | ||
846 | count++; | 848 | count++; |
847 | max--; | 849 | max--; |
848 | } | 850 | } |
@@ -856,43 +858,22 @@ ath5k_copy_channels(struct ath5k_hw *ah, | |||
856 | unsigned int mode, | 858 | unsigned int mode, |
857 | unsigned int max) | 859 | unsigned int max) |
858 | { | 860 | { |
859 | static const struct { unsigned int mode, mask, chan; } map[] = { | 861 | unsigned int i, count, size, chfreq, freq, ch; |
860 | [MODE_IEEE80211A] = { CHANNEL_OFDM, CHANNEL_OFDM | CHANNEL_TURBO, CHANNEL_A }, | ||
861 | [MODE_ATHEROS_TURBO] = { CHANNEL_OFDM|CHANNEL_TURBO, CHANNEL_OFDM | CHANNEL_TURBO, CHANNEL_T }, | ||
862 | [MODE_IEEE80211B] = { CHANNEL_CCK, CHANNEL_CCK, CHANNEL_B }, | ||
863 | [MODE_IEEE80211G] = { CHANNEL_OFDM, CHANNEL_OFDM, CHANNEL_G }, | ||
864 | [MODE_ATHEROS_TURBOG] = { CHANNEL_OFDM | CHANNEL_TURBO, CHANNEL_OFDM | CHANNEL_TURBO, CHANNEL_TG }, | ||
865 | }; | ||
866 | static const struct ath5k_regchannel chans_2ghz[] = | ||
867 | IEEE80211_CHANNELS_2GHZ; | ||
868 | static const struct ath5k_regchannel chans_5ghz[] = | ||
869 | IEEE80211_CHANNELS_5GHZ; | ||
870 | const struct ath5k_regchannel *chans; | ||
871 | enum ath5k_regdom dmn; | ||
872 | unsigned int i, count, size, chfreq, all, f, ch; | ||
873 | 862 | ||
874 | if (!test_bit(mode, ah->ah_modes)) | 863 | if (!test_bit(mode, ah->ah_modes)) |
875 | return 0; | 864 | return 0; |
876 | 865 | ||
877 | all = ah->ah_regdomain == DMN_DEFAULT || CHAN_DEBUG == 1; | ||
878 | |||
879 | switch (mode) { | 866 | switch (mode) { |
880 | case MODE_IEEE80211A: | 867 | case AR5K_MODE_11A: |
881 | case MODE_ATHEROS_TURBO: | 868 | case AR5K_MODE_11A_TURBO: |
882 | /* 1..220, but 2GHz frequencies are filtered by check_channel */ | 869 | /* 1..220, but 2GHz frequencies are filtered by check_channel */ |
883 | size = all ? 220 : ARRAY_SIZE(chans_5ghz); | 870 | size = 220 ; |
884 | chans = chans_5ghz; | ||
885 | dmn = ath5k_regdom2flag(ah->ah_regdomain, | ||
886 | IEEE80211_CHANNELS_5GHZ_MIN); | ||
887 | chfreq = CHANNEL_5GHZ; | 871 | chfreq = CHANNEL_5GHZ; |
888 | break; | 872 | break; |
889 | case MODE_IEEE80211B: | 873 | case AR5K_MODE_11B: |
890 | case MODE_IEEE80211G: | 874 | case AR5K_MODE_11G: |
891 | case MODE_ATHEROS_TURBOG: | 875 | case AR5K_MODE_11G_TURBO: |
892 | size = all ? 26 : ARRAY_SIZE(chans_2ghz); | 876 | size = 26; |
893 | chans = chans_2ghz; | ||
894 | dmn = ath5k_regdom2flag(ah->ah_regdomain, | ||
895 | IEEE80211_CHANNELS_2GHZ_MIN); | ||
896 | chfreq = CHANNEL_2GHZ; | 877 | chfreq = CHANNEL_2GHZ; |
897 | break; | 878 | break; |
898 | default: | 879 | default: |
@@ -901,25 +882,26 @@ ath5k_copy_channels(struct ath5k_hw *ah, | |||
901 | } | 882 | } |
902 | 883 | ||
903 | for (i = 0, count = 0; i < size && max > 0; i++) { | 884 | for (i = 0, count = 0; i < size && max > 0; i++) { |
904 | ch = all ? i + 1 : chans[i].chan; | 885 | ch = i + 1 ; |
905 | f = ath5k_ieee2mhz(ch); | 886 | freq = ath5k_ieee2mhz(ch); |
906 | /* Check if channel is supported by the chipset */ | ||
907 | if (!ath5k_channel_ok(ah, f, chfreq)) | ||
908 | continue; | ||
909 | 887 | ||
910 | /* Match regulation domain */ | 888 | /* Check if channel is supported by the chipset */ |
911 | if (!all && !(IEEE80211_DMN(chans[i].domain) & | 889 | if (!ath5k_channel_ok(ah, freq, chfreq)) |
912 | IEEE80211_DMN(dmn))) | ||
913 | continue; | 890 | continue; |
914 | 891 | ||
915 | if (!all && (chans[i].mode & map[mode].mask) != map[mode].mode) | 892 | /* Write channel info and increment counter */ |
916 | continue; | 893 | channels[count].center_freq = freq; |
894 | |||
895 | if((mode == AR5K_MODE_11A) || | ||
896 | (mode == AR5K_MODE_11G)){ | ||
897 | channels[count].hw_value = chfreq|CHANNEL_OFDM; | ||
898 | } else if((mode == AR5K_MODE_11A_TURBO) || | ||
899 | (mode == AR5K_MODE_11G_TURBO)){ | ||
900 | channels[count].hw_value = chfreq|CHANNEL_OFDM|CHANNEL_TURBO; | ||
901 | }if(mode == AR5K_MODE_11B) { | ||
902 | channels[count].hw_value = CHANNEL_B; | ||
903 | } | ||
917 | 904 | ||
918 | /* Write channel and increment counter */ | ||
919 | channels->chan = ch; | ||
920 | channels->freq = f; | ||
921 | channels->val = map[mode].chan; | ||
922 | channels++; | ||
923 | count++; | 905 | count++; |
924 | max--; | 906 | max--; |
925 | } | 907 | } |
@@ -927,95 +909,76 @@ ath5k_copy_channels(struct ath5k_hw *ah, | |||
927 | return count; | 909 | return count; |
928 | } | 910 | } |
929 | 911 | ||
930 | /* Only tries to register modes our EEPROM says it can support */ | 912 | static int |
931 | #define REGISTER_MODE(m) do { \ | 913 | ath5k_getchannels(struct ieee80211_hw *hw) |
932 | ret = ath5k_register_mode(hw, m); \ | ||
933 | if (ret) \ | ||
934 | return ret; \ | ||
935 | } while (0) \ | ||
936 | |||
937 | static inline int | ||
938 | ath5k_register_mode(struct ieee80211_hw *hw, u8 m) | ||
939 | { | 914 | { |
940 | struct ath5k_softc *sc = hw->priv; | 915 | struct ath5k_softc *sc = hw->priv; |
941 | struct ieee80211_hw_mode *modes = sc->modes; | 916 | struct ath5k_hw *ah = sc->ah; |
942 | unsigned int i; | 917 | struct ieee80211_supported_band *sbands = sc->sbands; |
943 | int ret; | 918 | const struct ath5k_rate_table *hw_rates; |
919 | unsigned int max_r, max_c, count_r, count_c; | ||
920 | int mode2g = AR5K_MODE_11G; | ||
944 | 921 | ||
945 | if (!test_bit(m, sc->ah->ah_capabilities.cap_mode)) | 922 | BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS); |
946 | return 0; | ||
947 | 923 | ||
948 | for (i = 0; i < NUM_DRIVER_MODES; i++) { | 924 | max_r = ARRAY_SIZE(sc->rates); |
949 | if (modes[i].mode != m || !modes[i].num_channels) | 925 | max_c = ARRAY_SIZE(sc->channels); |
950 | continue; | 926 | count_r = count_c = 0; |
951 | ret = ieee80211_register_hwmode(hw, &modes[i]); | 927 | |
952 | if (ret) { | 928 | /* 2GHz band */ |
953 | ATH5K_ERR(sc, "can't register hwmode %u\n", m); | 929 | if(!test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)){ |
954 | return ret; | 930 | mode2g = AR5K_MODE_11B; |
931 | if(!test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)){ | ||
932 | mode2g = -1; | ||
955 | } | 933 | } |
956 | return 0; | ||
957 | } | 934 | } |
958 | BUG(); | ||
959 | } | ||
960 | 935 | ||
961 | static int | 936 | if(mode2g > 0){ |
962 | ath5k_getchannels(struct ieee80211_hw *hw) | 937 | struct ieee80211_supported_band *sband = &sbands[IEEE80211_BAND_2GHZ]; |
963 | { | ||
964 | struct ath5k_softc *sc = hw->priv; | ||
965 | struct ath5k_hw *ah = sc->ah; | ||
966 | struct ieee80211_hw_mode *modes = sc->modes; | ||
967 | unsigned int i, max_r, max_c; | ||
968 | int ret; | ||
969 | 938 | ||
970 | BUILD_BUG_ON(ARRAY_SIZE(sc->modes) < 3); | 939 | sband->bitrates = sc->rates; |
940 | sband->channels = sc->channels; | ||
971 | 941 | ||
972 | /* The order here does not matter */ | 942 | sband->band = IEEE80211_BAND_2GHZ; |
973 | modes[0].mode = MODE_IEEE80211G; | 943 | sband->n_channels = ath5k_copy_channels(ah, sband->channels, |
974 | modes[1].mode = MODE_IEEE80211B; | 944 | mode2g, max_c); |
975 | modes[2].mode = MODE_IEEE80211A; | ||
976 | 945 | ||
977 | max_r = ARRAY_SIZE(sc->rates); | 946 | hw_rates = ath5k_hw_get_rate_table(ah, mode2g); |
978 | max_c = ARRAY_SIZE(sc->channels); | 947 | sband->n_bitrates = ath5k_copy_rates(sband->bitrates, |
948 | hw_rates,max_r); | ||
979 | 949 | ||
980 | for (i = 0; i < NUM_DRIVER_MODES; i++) { | 950 | count_c = sband->n_channels; |
981 | struct ieee80211_hw_mode *mode = &modes[i]; | 951 | count_r = sband->n_bitrates; |
982 | const struct ath5k_rate_table *hw_rates; | ||
983 | 952 | ||
984 | if (i == 0) { | 953 | hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband; |
985 | modes[0].rates = sc->rates; | 954 | |
986 | modes->channels = sc->channels; | 955 | max_r -= count_r; |
987 | } else { | 956 | max_c -= count_c; |
988 | struct ieee80211_hw_mode *prev_mode = &modes[i-1]; | ||
989 | int prev_num_r = prev_mode->num_rates; | ||
990 | int prev_num_c = prev_mode->num_channels; | ||
991 | mode->rates = &prev_mode->rates[prev_num_r]; | ||
992 | mode->channels = &prev_mode->channels[prev_num_c]; | ||
993 | } | ||
994 | 957 | ||
995 | hw_rates = ath5k_hw_get_rate_table(ah, mode->mode); | ||
996 | mode->num_rates = ath5k_copy_rates(mode->rates, hw_rates, | ||
997 | max_r); | ||
998 | mode->num_channels = ath5k_copy_channels(ah, mode->channels, | ||
999 | mode->mode, max_c); | ||
1000 | max_r -= mode->num_rates; | ||
1001 | max_c -= mode->num_channels; | ||
1002 | } | 958 | } |
1003 | 959 | ||
1004 | /* We try to register all modes this driver supports. We don't bother | 960 | /* 5GHz band */ |
1005 | * with MODE_IEEE80211B for AR5212 as MODE_IEEE80211G already accounts | ||
1006 | * for that as per mac80211. Then, REGISTER_MODE() will will actually | ||
1007 | * check the eeprom reading for more reliable capability information. | ||
1008 | * Order matters here as per mac80211's latest preference. This will | ||
1009 | * all hopefullly soon go away. */ | ||
1010 | 961 | ||
1011 | REGISTER_MODE(MODE_IEEE80211G); | 962 | if(test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)){ |
1012 | if (ah->ah_version != AR5K_AR5212) | 963 | struct ieee80211_supported_band *sband = &sbands[IEEE80211_BAND_5GHZ]; |
1013 | REGISTER_MODE(MODE_IEEE80211B); | ||
1014 | REGISTER_MODE(MODE_IEEE80211A); | ||
1015 | 964 | ||
1016 | ath5k_debug_dump_modes(sc, modes); | 965 | sband->bitrates = &sc->rates[count_r]; |
966 | sband->channels = &sc->channels[count_c]; | ||
1017 | 967 | ||
1018 | return ret; | 968 | sband->band = IEEE80211_BAND_5GHZ; |
969 | sband->n_channels = ath5k_copy_channels(ah, sband->channels, | ||
970 | AR5K_MODE_11A, max_c); | ||
971 | |||
972 | hw_rates = ath5k_hw_get_rate_table(ah, AR5K_MODE_11A); | ||
973 | sband->n_bitrates = ath5k_copy_rates(sband->bitrates, | ||
974 | hw_rates,max_r); | ||
975 | |||
976 | hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband; | ||
977 | } | ||
978 | |||
979 | /* FIXME: ath5k_debug_dump_modes(sc, modes); */ | ||
980 | |||
981 | return 0; | ||
1019 | } | 982 | } |
1020 | 983 | ||
1021 | /* | 984 | /* |
@@ -1030,11 +993,15 @@ ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan) | |||
1030 | struct ath5k_hw *ah = sc->ah; | 993 | struct ath5k_hw *ah = sc->ah; |
1031 | int ret; | 994 | int ret; |
1032 | 995 | ||
1033 | ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "%u (%u MHz) -> %u (%u MHz)\n", | 996 | ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n", |
1034 | sc->curchan->chan, sc->curchan->freq, | 997 | sc->curchan->center_freq, chan->center_freq); |
1035 | chan->chan, chan->freq); | 998 | |
999 | if (chan->center_freq != sc->curchan->center_freq || | ||
1000 | chan->hw_value != sc->curchan->hw_value) { | ||
1001 | |||
1002 | sc->curchan = chan; | ||
1003 | sc->curband = &sc->sbands[chan->band]; | ||
1036 | 1004 | ||
1037 | if (chan->freq != sc->curchan->freq || chan->val != sc->curchan->val) { | ||
1038 | /* | 1005 | /* |
1039 | * To switch channels clear any pending DMA operations; | 1006 | * To switch channels clear any pending DMA operations; |
1040 | * wait long enough for the RX fifo to drain, reset the | 1007 | * wait long enough for the RX fifo to drain, reset the |
@@ -1044,13 +1011,13 @@ ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan) | |||
1044 | ath5k_hw_set_intr(ah, 0); /* disable interrupts */ | 1011 | ath5k_hw_set_intr(ah, 0); /* disable interrupts */ |
1045 | ath5k_txq_cleanup(sc); /* clear pending tx frames */ | 1012 | ath5k_txq_cleanup(sc); /* clear pending tx frames */ |
1046 | ath5k_rx_stop(sc); /* turn off frame recv */ | 1013 | ath5k_rx_stop(sc); /* turn off frame recv */ |
1047 | ret = ath5k_hw_reset(ah, sc->opmode, chan, true); | 1014 | ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true); |
1048 | if (ret) { | 1015 | if (ret) { |
1049 | ATH5K_ERR(sc, "%s: unable to reset channel %u " | 1016 | ATH5K_ERR(sc, "%s: unable to reset channel " |
1050 | "(%u Mhz)\n", __func__, chan->chan, chan->freq); | 1017 | "(%u Mhz)\n", __func__, chan->center_freq); |
1051 | return ret; | 1018 | return ret; |
1052 | } | 1019 | } |
1053 | sc->curchan = chan; | 1020 | |
1054 | ath5k_hw_set_txpower_limit(sc->ah, 0); | 1021 | ath5k_hw_set_txpower_limit(sc->ah, 0); |
1055 | 1022 | ||
1056 | /* | 1023 | /* |
@@ -1081,6 +1048,9 @@ ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan) | |||
1081 | return 0; | 1048 | return 0; |
1082 | } | 1049 | } |
1083 | 1050 | ||
1051 | /* | ||
1052 | * TODO: CLEAN THIS !!! | ||
1053 | */ | ||
1084 | static void | 1054 | static void |
1085 | ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode) | 1055 | ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode) |
1086 | { | 1056 | { |
@@ -1121,10 +1091,6 @@ ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode) | |||
1121 | continue; | 1091 | continue; |
1122 | } | 1092 | } |
1123 | sc->hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; | 1093 | sc->hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; |
1124 | if (SHPREAMBLE_FLAG(ix) || rt->rates[ix].modulation == | ||
1125 | IEEE80211_RATE_OFDM) | ||
1126 | sc->hwmap[i].txflags |= | ||
1127 | IEEE80211_RADIOTAP_F_SHORTPRE; | ||
1128 | /* receive frames include FCS */ | 1094 | /* receive frames include FCS */ |
1129 | sc->hwmap[i].rxflags = sc->hwmap[i].txflags | | 1095 | sc->hwmap[i].rxflags = sc->hwmap[i].txflags | |
1130 | IEEE80211_RADIOTAP_F_FCS; | 1096 | IEEE80211_RADIOTAP_F_FCS; |
@@ -1142,6 +1108,12 @@ ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode) | |||
1142 | } | 1108 | } |
1143 | 1109 | ||
1144 | sc->curmode = mode; | 1110 | sc->curmode = mode; |
1111 | |||
1112 | if(mode == AR5K_MODE_11A){ | ||
1113 | sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ]; | ||
1114 | } else { | ||
1115 | sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ]; | ||
1116 | } | ||
1145 | } | 1117 | } |
1146 | 1118 | ||
1147 | static void | 1119 | static void |
@@ -1164,6 +1136,72 @@ ath5k_mode_setup(struct ath5k_softc *sc) | |||
1164 | ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt); | 1136 | ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt); |
1165 | } | 1137 | } |
1166 | 1138 | ||
1139 | /* | ||
1140 | * Match the hw provided rate index (through descriptors) | ||
1141 | * to an index for sc->curband->bitrates, so it can be used | ||
1142 | * by the stack. | ||
1143 | * | ||
1144 | * This one is a little bit tricky but i think i'm right | ||
1145 | * about this... | ||
1146 | * | ||
1147 | * We have 4 rate tables in the following order: | ||
1148 | * XR (4 rates) | ||
1149 | * 802.11a (8 rates) | ||
1150 | * 802.11b (4 rates) | ||
1151 | * 802.11g (12 rates) | ||
1152 | * that make the hw rate table. | ||
1153 | * | ||
1154 | * Lets take a 5211 for example that supports a and b modes only. | ||
1155 | * First comes the 802.11a table and then 802.11b (total 12 rates). | ||
1156 | * When hw returns eg. 11 it points to the last 802.11b rate (11Mbit), | ||
1157 | * if it returns 2 it points to the second 802.11a rate etc. | ||
1158 | * | ||
1159 | * Same goes for 5212 who has xr/a/b/g support (total 28 rates). | ||
1160 | * First comes the XR table, then 802.11a, 802.11b and 802.11g. | ||
1161 | * When hw returns eg. 27 it points to the last 802.11g rate (54Mbits) etc | ||
1162 | */ | ||
1163 | static void | ||
1164 | ath5k_set_total_hw_rates(struct ath5k_softc *sc){ | ||
1165 | |||
1166 | struct ath5k_hw *ah = sc->ah; | ||
1167 | |||
1168 | if(test_bit(AR5K_MODE_11A, ah->ah_modes)) | ||
1169 | sc->a_rates = 8; | ||
1170 | |||
1171 | if(test_bit(AR5K_MODE_11B, ah->ah_modes)) | ||
1172 | sc->b_rates = 4; | ||
1173 | |||
1174 | if(test_bit(AR5K_MODE_11G, ah->ah_modes)) | ||
1175 | sc->g_rates = 12; | ||
1176 | |||
1177 | /* XXX: Need to see what what happens when | ||
1178 | xr disable bits in eeprom are set */ | ||
1179 | if(ah->ah_version >= AR5K_AR5212) | ||
1180 | sc->xr_rates = 4; | ||
1181 | |||
1182 | } | ||
1183 | |||
1184 | static inline int | ||
1185 | ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix){ | ||
1186 | |||
1187 | int mac80211_rix; | ||
1188 | |||
1189 | if(sc->curband->band == IEEE80211_BAND_2GHZ){ | ||
1190 | /* We setup a g ratetable for both b/g modes */ | ||
1191 | mac80211_rix = hw_rix - sc->b_rates - sc->a_rates - sc->xr_rates; | ||
1192 | } else { | ||
1193 | mac80211_rix = hw_rix - sc->xr_rates; | ||
1194 | } | ||
1195 | |||
1196 | /* Something went wrong, fallback to basic rate for this band */ | ||
1197 | if((mac80211_rix >= sc->curband->n_bitrates) || | ||
1198 | (mac80211_rix <= 0 )){ | ||
1199 | mac80211_rix = 1; | ||
1200 | } | ||
1201 | |||
1202 | return mac80211_rix; | ||
1203 | } | ||
1204 | |||
1167 | 1205 | ||
1168 | 1206 | ||
1169 | 1207 | ||
@@ -1268,7 +1306,7 @@ ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf, | |||
1268 | 1306 | ||
1269 | ret = ah->ah_setup_tx_desc(ah, ds, pktlen, | 1307 | ret = ah->ah_setup_tx_desc(ah, ds, pktlen, |
1270 | ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL, | 1308 | ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL, |
1271 | (ctl->power_level * 2), ctl->tx_rate, ctl->retry_limit, keyidx, 0, flags, 0, 0); | 1309 | (sc->power_level * 2), ctl->tx_rate->hw_value, ctl->retry_limit, keyidx, 0, flags, 0, 0); |
1272 | if (ret) | 1310 | if (ret) |
1273 | goto err_unmap; | 1311 | goto err_unmap; |
1274 | 1312 | ||
@@ -1791,9 +1829,8 @@ accept: | |||
1791 | rxs.mactime = ath5k_extend_tsf(sc->ah, ds->ds_rxstat.rs_tstamp); | 1829 | rxs.mactime = ath5k_extend_tsf(sc->ah, ds->ds_rxstat.rs_tstamp); |
1792 | rxs.flag |= RX_FLAG_TSFT; | 1830 | rxs.flag |= RX_FLAG_TSFT; |
1793 | 1831 | ||
1794 | rxs.freq = sc->curchan->freq; | 1832 | rxs.freq = sc->curchan->center_freq; |
1795 | rxs.channel = sc->curchan->chan; | 1833 | rxs.band = sc->curband->band; |
1796 | rxs.phymode = sc->curmode; | ||
1797 | 1834 | ||
1798 | /* | 1835 | /* |
1799 | * signal quality: | 1836 | * signal quality: |
@@ -1811,7 +1848,7 @@ accept: | |||
1811 | rxs.signal = ds->ds_rxstat.rs_rssi * 100 / 64; | 1848 | rxs.signal = ds->ds_rxstat.rs_rssi * 100 / 64; |
1812 | 1849 | ||
1813 | rxs.antenna = ds->ds_rxstat.rs_antenna; | 1850 | rxs.antenna = ds->ds_rxstat.rs_antenna; |
1814 | rxs.rate = ds->ds_rxstat.rs_rate; | 1851 | rxs.rate_idx = ath5k_hw_to_driver_rix(sc,ds->ds_rxstat.rs_rate); |
1815 | rxs.flag |= ath5k_rx_decrypted(sc, ds, skb); | 1852 | rxs.flag |= ath5k_rx_decrypted(sc, ds, skb); |
1816 | 1853 | ||
1817 | ath5k_debug_dump_skb(sc, skb, "RX ", 0); | 1854 | ath5k_debug_dump_skb(sc, skb, "RX ", 0); |
@@ -1958,7 +1995,7 @@ ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf, | |||
1958 | ds->ds_data = bf->skbaddr; | 1995 | ds->ds_data = bf->skbaddr; |
1959 | ret = ah->ah_setup_tx_desc(ah, ds, skb->len, | 1996 | ret = ah->ah_setup_tx_desc(ah, ds, skb->len, |
1960 | ieee80211_get_hdrlen_from_skb(skb), | 1997 | ieee80211_get_hdrlen_from_skb(skb), |
1961 | AR5K_PKT_TYPE_BEACON, (ctl->power_level * 2), ctl->tx_rate, 1, | 1998 | AR5K_PKT_TYPE_BEACON, (sc->power_level * 2), ctl->tx_rate->hw_value, 1, |
1962 | AR5K_TXKEYIX_INVALID, antenna, flags, 0, 0); | 1999 | AR5K_TXKEYIX_INVALID, antenna, flags, 0, 0); |
1963 | if (ret) | 2000 | if (ret) |
1964 | goto err_unmap; | 2001 | goto err_unmap; |
@@ -2211,7 +2248,8 @@ ath5k_init(struct ath5k_softc *sc) | |||
2211 | * be followed by initialization of the appropriate bits | 2248 | * be followed by initialization of the appropriate bits |
2212 | * and then setup of the interrupt mask. | 2249 | * and then setup of the interrupt mask. |
2213 | */ | 2250 | */ |
2214 | sc->curchan = sc->hw->conf.chan; | 2251 | sc->curchan = sc->hw->conf.channel; |
2252 | sc->curband = &sc->sbands[sc->curchan->band]; | ||
2215 | ret = ath5k_hw_reset(sc->ah, sc->opmode, sc->curchan, false); | 2253 | ret = ath5k_hw_reset(sc->ah, sc->opmode, sc->curchan, false); |
2216 | if (ret) { | 2254 | if (ret) { |
2217 | ATH5K_ERR(sc, "unable to reset hardware: %d\n", ret); | 2255 | ATH5K_ERR(sc, "unable to reset hardware: %d\n", ret); |
@@ -2448,7 +2486,7 @@ ath5k_calibrate(unsigned long data) | |||
2448 | struct ath5k_hw *ah = sc->ah; | 2486 | struct ath5k_hw *ah = sc->ah; |
2449 | 2487 | ||
2450 | ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n", | 2488 | ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n", |
2451 | sc->curchan->chan, sc->curchan->val); | 2489 | ieee80211_frequency_to_channel(sc->curchan->center_freq), sc->curchan->hw_value); |
2452 | 2490 | ||
2453 | if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) { | 2491 | if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) { |
2454 | /* | 2492 | /* |
@@ -2460,7 +2498,7 @@ ath5k_calibrate(unsigned long data) | |||
2460 | } | 2498 | } |
2461 | if (ath5k_hw_phy_calibrate(ah, sc->curchan)) | 2499 | if (ath5k_hw_phy_calibrate(ah, sc->curchan)) |
2462 | ATH5K_ERR(sc, "calibration of channel %u failed\n", | 2500 | ATH5K_ERR(sc, "calibration of channel %u failed\n", |
2463 | sc->curchan->chan); | 2501 | ieee80211_frequency_to_channel(sc->curchan->center_freq)); |
2464 | 2502 | ||
2465 | mod_timer(&sc->calib_tim, round_jiffies(jiffies + | 2503 | mod_timer(&sc->calib_tim, round_jiffies(jiffies + |
2466 | msecs_to_jiffies(ath5k_calinterval * 1000))); | 2504 | msecs_to_jiffies(ath5k_calinterval * 1000))); |
@@ -2558,7 +2596,7 @@ ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb, | |||
2558 | memmove(skb->data, skb->data+pad, hdrlen); | 2596 | memmove(skb->data, skb->data+pad, hdrlen); |
2559 | } | 2597 | } |
2560 | 2598 | ||
2561 | sc->led_txrate = ctl->tx_rate; | 2599 | sc->led_txrate = ctl->tx_rate->hw_value; |
2562 | 2600 | ||
2563 | spin_lock_irqsave(&sc->txbuflock, flags); | 2601 | spin_lock_irqsave(&sc->txbuflock, flags); |
2564 | if (list_empty(&sc->txbuf)) { | 2602 | if (list_empty(&sc->txbuf)) { |
@@ -2597,11 +2635,6 @@ ath5k_reset(struct ieee80211_hw *hw) | |||
2597 | int ret; | 2635 | int ret; |
2598 | 2636 | ||
2599 | ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n"); | 2637 | ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n"); |
2600 | /* | ||
2601 | * Convert to a hw channel description with the flags | ||
2602 | * constrained to reflect the current operating mode. | ||
2603 | */ | ||
2604 | sc->curchan = hw->conf.chan; | ||
2605 | 2638 | ||
2606 | ath5k_hw_set_intr(ah, 0); | 2639 | ath5k_hw_set_intr(ah, 0); |
2607 | ath5k_txq_cleanup(sc); | 2640 | ath5k_txq_cleanup(sc); |
@@ -2692,6 +2725,9 @@ end: | |||
2692 | mutex_unlock(&sc->lock); | 2725 | mutex_unlock(&sc->lock); |
2693 | } | 2726 | } |
2694 | 2727 | ||
2728 | /* | ||
2729 | * TODO: Phy disable/diversity etc | ||
2730 | */ | ||
2695 | static int | 2731 | static int |
2696 | ath5k_config(struct ieee80211_hw *hw, | 2732 | ath5k_config(struct ieee80211_hw *hw, |
2697 | struct ieee80211_conf *conf) | 2733 | struct ieee80211_conf *conf) |
@@ -2699,9 +2735,9 @@ ath5k_config(struct ieee80211_hw *hw, | |||
2699 | struct ath5k_softc *sc = hw->priv; | 2735 | struct ath5k_softc *sc = hw->priv; |
2700 | 2736 | ||
2701 | sc->bintval = conf->beacon_int; | 2737 | sc->bintval = conf->beacon_int; |
2702 | ath5k_setcurmode(sc, conf->phymode); | 2738 | sc->power_level = conf->power_level; |
2703 | 2739 | ||
2704 | return ath5k_chan_set(sc, conf->chan); | 2740 | return ath5k_chan_set(sc, conf->channel); |
2705 | } | 2741 | } |
2706 | 2742 | ||
2707 | static int | 2743 | static int |
diff --git a/drivers/net/wireless/ath5k/base.h b/drivers/net/wireless/ath5k/base.h index 8287ae787f12..bbe7a5438154 100644 --- a/drivers/net/wireless/ath5k/base.h +++ b/drivers/net/wireless/ath5k/base.h | |||
@@ -83,7 +83,7 @@ struct ath5k_txq { | |||
83 | #if CHAN_DEBUG | 83 | #if CHAN_DEBUG |
84 | #define ATH_CHAN_MAX (26+26+26+200+200) | 84 | #define ATH_CHAN_MAX (26+26+26+200+200) |
85 | #else | 85 | #else |
86 | #define ATH_CHAN_MAX (14+14+14+252+20) /* XXX what's the max? */ | 86 | #define ATH_CHAN_MAX (14+14+14+252+20) |
87 | #endif | 87 | #endif |
88 | 88 | ||
89 | /* Software Carrier, keeps track of the driver state | 89 | /* Software Carrier, keeps track of the driver state |
@@ -95,12 +95,19 @@ struct ath5k_softc { | |||
95 | struct ieee80211_tx_queue_stats tx_stats; | 95 | struct ieee80211_tx_queue_stats tx_stats; |
96 | struct ieee80211_low_level_stats ll_stats; | 96 | struct ieee80211_low_level_stats ll_stats; |
97 | struct ieee80211_hw *hw; /* IEEE 802.11 common */ | 97 | struct ieee80211_hw *hw; /* IEEE 802.11 common */ |
98 | struct ieee80211_hw_mode modes[NUM_DRIVER_MODES]; | 98 | struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS]; |
99 | struct ieee80211_channel channels[ATH_CHAN_MAX]; | 99 | struct ieee80211_channel channels[ATH_CHAN_MAX]; |
100 | struct ieee80211_rate rates[AR5K_MAX_RATES * NUM_DRIVER_MODES]; | 100 | struct ieee80211_rate rates[AR5K_MAX_RATES * IEEE80211_NUM_BANDS]; |
101 | enum ieee80211_if_types opmode; | 101 | enum ieee80211_if_types opmode; |
102 | struct ath5k_hw *ah; /* Atheros HW */ | 102 | struct ath5k_hw *ah; /* Atheros HW */ |
103 | 103 | ||
104 | struct ieee80211_supported_band *curband; | ||
105 | |||
106 | u8 a_rates; | ||
107 | u8 b_rates; | ||
108 | u8 g_rates; | ||
109 | u8 xr_rates; | ||
110 | |||
104 | #if ATH5K_DEBUG | 111 | #if ATH5K_DEBUG |
105 | struct ath5k_dbg_info debug; /* debug info */ | 112 | struct ath5k_dbg_info debug; /* debug info */ |
106 | #endif | 113 | #endif |
@@ -169,6 +176,7 @@ struct ath5k_softc { | |||
169 | unsigned int nexttbtt; /* next beacon time in TU */ | 176 | unsigned int nexttbtt; /* next beacon time in TU */ |
170 | 177 | ||
171 | struct timer_list calib_tim; /* calibration timer */ | 178 | struct timer_list calib_tim; /* calibration timer */ |
179 | int power_level; /* Requested tx power in dbm */ | ||
172 | }; | 180 | }; |
173 | 181 | ||
174 | #define ath5k_hw_hasbssidmask(_ah) \ | 182 | #define ath5k_hw_hasbssidmask(_ah) \ |
diff --git a/drivers/net/wireless/ath5k/hw.c b/drivers/net/wireless/ath5k/hw.c index c2de2d958e8e..998da6be2be3 100644 --- a/drivers/net/wireless/ath5k/hw.c +++ b/drivers/net/wireless/ath5k/hw.c | |||
@@ -140,9 +140,6 @@ struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version) | |||
140 | * HW information | 140 | * HW information |
141 | */ | 141 | */ |
142 | 142 | ||
143 | /* Get reg domain from eeprom */ | ||
144 | ath5k_get_regdomain(ah); | ||
145 | |||
146 | ah->ah_op_mode = IEEE80211_IF_TYPE_STA; | 143 | ah->ah_op_mode = IEEE80211_IF_TYPE_STA; |
147 | ah->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT; | 144 | ah->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT; |
148 | ah->ah_turbo = false; | 145 | ah->ah_turbo = false; |
@@ -405,15 +402,15 @@ const struct ath5k_rate_table *ath5k_hw_get_rate_table(struct ath5k_hw *ah, | |||
405 | 402 | ||
406 | /* Get rate tables */ | 403 | /* Get rate tables */ |
407 | switch (mode) { | 404 | switch (mode) { |
408 | case MODE_IEEE80211A: | 405 | case AR5K_MODE_11A: |
409 | return &ath5k_rt_11a; | 406 | return &ath5k_rt_11a; |
410 | case MODE_ATHEROS_TURBO: | 407 | case AR5K_MODE_11A_TURBO: |
411 | return &ath5k_rt_turbo; | 408 | return &ath5k_rt_turbo; |
412 | case MODE_IEEE80211B: | 409 | case AR5K_MODE_11B: |
413 | return &ath5k_rt_11b; | 410 | return &ath5k_rt_11b; |
414 | case MODE_IEEE80211G: | 411 | case AR5K_MODE_11G: |
415 | return &ath5k_rt_11g; | 412 | return &ath5k_rt_11g; |
416 | case MODE_ATHEROS_TURBOG: | 413 | case AR5K_MODE_11G_TURBO: |
417 | return &ath5k_rt_xr; | 414 | return &ath5k_rt_xr; |
418 | } | 415 | } |
419 | 416 | ||
@@ -457,15 +454,15 @@ static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah, | |||
457 | ds_coef_exp, ds_coef_man, clock; | 454 | ds_coef_exp, ds_coef_man, clock; |
458 | 455 | ||
459 | if (!(ah->ah_version == AR5K_AR5212) || | 456 | if (!(ah->ah_version == AR5K_AR5212) || |
460 | !(channel->val & CHANNEL_OFDM)) | 457 | !(channel->hw_value & CHANNEL_OFDM)) |
461 | BUG(); | 458 | BUG(); |
462 | 459 | ||
463 | /* Seems there are two PLLs, one for baseband sampling and one | 460 | /* Seems there are two PLLs, one for baseband sampling and one |
464 | * for tuning. Tuning basebands are 40 MHz or 80MHz when in | 461 | * for tuning. Tuning basebands are 40 MHz or 80MHz when in |
465 | * turbo. */ | 462 | * turbo. */ |
466 | clock = channel->val & CHANNEL_TURBO ? 80 : 40; | 463 | clock = channel->hw_value & CHANNEL_TURBO ? 80 : 40; |
467 | coef_scaled = ((5 * (clock << 24)) / 2) / | 464 | coef_scaled = ((5 * (clock << 24)) / 2) / |
468 | channel->freq; | 465 | channel->center_freq; |
469 | 466 | ||
470 | for (coef_exp = 31; coef_exp > 0; coef_exp--) | 467 | for (coef_exp = 31; coef_exp > 0; coef_exp--) |
471 | if ((coef_scaled >> coef_exp) & 0x1) | 468 | if ((coef_scaled >> coef_exp) & 0x1) |
@@ -492,8 +489,7 @@ static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah, | |||
492 | * ath5k_hw_write_rate_duration - set rate duration during hw resets | 489 | * ath5k_hw_write_rate_duration - set rate duration during hw resets |
493 | * | 490 | * |
494 | * @ah: the &struct ath5k_hw | 491 | * @ah: the &struct ath5k_hw |
495 | * @driver_mode: one of enum ieee80211_phymode or our one of our own | 492 | * @mode: one of enum ath5k_driver_mode |
496 | * vendor modes | ||
497 | * | 493 | * |
498 | * Write the rate duration table for the current mode upon hw reset. This | 494 | * Write the rate duration table for the current mode upon hw reset. This |
499 | * is a helper for ath5k_hw_reset(). It seems all this is doing is setting | 495 | * is a helper for ath5k_hw_reset(). It seems all this is doing is setting |
@@ -504,19 +500,20 @@ static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah, | |||
504 | * | 500 | * |
505 | */ | 501 | */ |
506 | static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah, | 502 | static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah, |
507 | unsigned int driver_mode) | 503 | unsigned int mode) |
508 | { | 504 | { |
509 | struct ath5k_softc *sc = ah->ah_sc; | 505 | struct ath5k_softc *sc = ah->ah_sc; |
510 | const struct ath5k_rate_table *rt; | 506 | const struct ath5k_rate_table *rt; |
507 | struct ieee80211_rate srate = {}; | ||
511 | unsigned int i; | 508 | unsigned int i; |
512 | 509 | ||
513 | /* Get rate table for the current operating mode */ | 510 | /* Get rate table for the current operating mode */ |
514 | rt = ath5k_hw_get_rate_table(ah, | 511 | rt = ath5k_hw_get_rate_table(ah, mode); |
515 | driver_mode); | ||
516 | 512 | ||
517 | /* Write rate duration table */ | 513 | /* Write rate duration table */ |
518 | for (i = 0; i < rt->rate_count; i++) { | 514 | for (i = 0; i < rt->rate_count; i++) { |
519 | const struct ath5k_rate *rate, *control_rate; | 515 | const struct ath5k_rate *rate, *control_rate; |
516 | |||
520 | u32 reg; | 517 | u32 reg; |
521 | u16 tx_time; | 518 | u16 tx_time; |
522 | 519 | ||
@@ -526,6 +523,8 @@ static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah, | |||
526 | /* Set ACK timeout */ | 523 | /* Set ACK timeout */ |
527 | reg = AR5K_RATE_DUR(rate->rate_code); | 524 | reg = AR5K_RATE_DUR(rate->rate_code); |
528 | 525 | ||
526 | srate.bitrate = control_rate->rate_kbps/100; | ||
527 | |||
529 | /* An ACK frame consists of 10 bytes. If you add the FCS, | 528 | /* An ACK frame consists of 10 bytes. If you add the FCS, |
530 | * which ieee80211_generic_frame_duration() adds, | 529 | * which ieee80211_generic_frame_duration() adds, |
531 | * its 14 bytes. Note we use the control rate and not the | 530 | * its 14 bytes. Note we use the control rate and not the |
@@ -533,7 +532,7 @@ static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah, | |||
533 | * ieee80211_duration() for a brief description of | 532 | * ieee80211_duration() for a brief description of |
534 | * what rate we should choose to TX ACKs. */ | 533 | * what rate we should choose to TX ACKs. */ |
535 | tx_time = ieee80211_generic_frame_duration(sc->hw, | 534 | tx_time = ieee80211_generic_frame_duration(sc->hw, |
536 | sc->vif, 10, control_rate->rate_kbps/100); | 535 | sc->vif, 10, &srate); |
537 | 536 | ||
538 | ath5k_hw_reg_write(ah, tx_time, reg); | 537 | ath5k_hw_reg_write(ah, tx_time, reg); |
539 | 538 | ||
@@ -567,7 +566,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode, | |||
567 | { | 566 | { |
568 | struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; | 567 | struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; |
569 | u32 data, s_seq, s_ant, s_led[3]; | 568 | u32 data, s_seq, s_ant, s_led[3]; |
570 | unsigned int i, mode, freq, ee_mode, ant[2], driver_mode = -1; | 569 | unsigned int i, mode, freq, ee_mode, ant[2]; |
571 | int ret; | 570 | int ret; |
572 | 571 | ||
573 | ATH5K_TRACE(ah->ah_sc); | 572 | ATH5K_TRACE(ah->ah_sc); |
@@ -602,7 +601,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode, | |||
602 | 601 | ||
603 | 602 | ||
604 | /*Wakeup the device*/ | 603 | /*Wakeup the device*/ |
605 | ret = ath5k_hw_nic_wakeup(ah, channel->val, false); | 604 | ret = ath5k_hw_nic_wakeup(ah, channel->hw_value, false); |
606 | if (ret) | 605 | if (ret) |
607 | return ret; | 606 | return ret; |
608 | 607 | ||
@@ -624,37 +623,32 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode, | |||
624 | return -EINVAL; | 623 | return -EINVAL; |
625 | } | 624 | } |
626 | 625 | ||
627 | switch (channel->val & CHANNEL_MODES) { | 626 | switch (channel->hw_value & CHANNEL_MODES) { |
628 | case CHANNEL_A: | 627 | case CHANNEL_A: |
629 | mode = AR5K_INI_VAL_11A; | 628 | mode = AR5K_MODE_11A; |
630 | freq = AR5K_INI_RFGAIN_5GHZ; | 629 | freq = AR5K_INI_RFGAIN_5GHZ; |
631 | ee_mode = AR5K_EEPROM_MODE_11A; | 630 | ee_mode = AR5K_EEPROM_MODE_11A; |
632 | driver_mode = MODE_IEEE80211A; | ||
633 | break; | 631 | break; |
634 | case CHANNEL_G: | 632 | case CHANNEL_G: |
635 | mode = AR5K_INI_VAL_11G; | 633 | mode = AR5K_MODE_11G; |
636 | freq = AR5K_INI_RFGAIN_2GHZ; | 634 | freq = AR5K_INI_RFGAIN_2GHZ; |
637 | ee_mode = AR5K_EEPROM_MODE_11G; | 635 | ee_mode = AR5K_EEPROM_MODE_11G; |
638 | driver_mode = MODE_IEEE80211G; | ||
639 | break; | 636 | break; |
640 | case CHANNEL_B: | 637 | case CHANNEL_B: |
641 | mode = AR5K_INI_VAL_11B; | 638 | mode = AR5K_MODE_11B; |
642 | freq = AR5K_INI_RFGAIN_2GHZ; | 639 | freq = AR5K_INI_RFGAIN_2GHZ; |
643 | ee_mode = AR5K_EEPROM_MODE_11B; | 640 | ee_mode = AR5K_EEPROM_MODE_11B; |
644 | driver_mode = MODE_IEEE80211B; | ||
645 | break; | 641 | break; |
646 | case CHANNEL_T: | 642 | case CHANNEL_T: |
647 | mode = AR5K_INI_VAL_11A_TURBO; | 643 | mode = AR5K_MODE_11A_TURBO; |
648 | freq = AR5K_INI_RFGAIN_5GHZ; | 644 | freq = AR5K_INI_RFGAIN_5GHZ; |
649 | ee_mode = AR5K_EEPROM_MODE_11A; | 645 | ee_mode = AR5K_EEPROM_MODE_11A; |
650 | driver_mode = MODE_ATHEROS_TURBO; | ||
651 | break; | 646 | break; |
652 | /*Is this ok on 5211 too ?*/ | 647 | /*Is this ok on 5211 too ?*/ |
653 | case CHANNEL_TG: | 648 | case CHANNEL_TG: |
654 | mode = AR5K_INI_VAL_11G_TURBO; | 649 | mode = AR5K_MODE_11G_TURBO; |
655 | freq = AR5K_INI_RFGAIN_2GHZ; | 650 | freq = AR5K_INI_RFGAIN_2GHZ; |
656 | ee_mode = AR5K_EEPROM_MODE_11G; | 651 | ee_mode = AR5K_EEPROM_MODE_11G; |
657 | driver_mode = MODE_ATHEROS_TURBOG; | ||
658 | break; | 652 | break; |
659 | case CHANNEL_XR: | 653 | case CHANNEL_XR: |
660 | if (ah->ah_version == AR5K_AR5211) { | 654 | if (ah->ah_version == AR5K_AR5211) { |
@@ -662,14 +656,13 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode, | |||
662 | "XR mode not available on 5211"); | 656 | "XR mode not available on 5211"); |
663 | return -EINVAL; | 657 | return -EINVAL; |
664 | } | 658 | } |
665 | mode = AR5K_INI_VAL_XR; | 659 | mode = AR5K_MODE_XR; |
666 | freq = AR5K_INI_RFGAIN_5GHZ; | 660 | freq = AR5K_INI_RFGAIN_5GHZ; |
667 | ee_mode = AR5K_EEPROM_MODE_11A; | 661 | ee_mode = AR5K_EEPROM_MODE_11A; |
668 | driver_mode = MODE_IEEE80211A; | ||
669 | break; | 662 | break; |
670 | default: | 663 | default: |
671 | ATH5K_ERR(ah->ah_sc, | 664 | ATH5K_ERR(ah->ah_sc, |
672 | "invalid channel: %d\n", channel->freq); | 665 | "invalid channel: %d\n", channel->center_freq); |
673 | return -EINVAL; | 666 | return -EINVAL; |
674 | } | 667 | } |
675 | 668 | ||
@@ -702,7 +695,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode, | |||
702 | if (ah->ah_version > AR5K_AR5211){ /* found on 5213+ */ | 695 | if (ah->ah_version > AR5K_AR5211){ /* found on 5213+ */ |
703 | ath5k_hw_reg_write(ah, 0x0002a002, AR5K_PHY(11)); | 696 | ath5k_hw_reg_write(ah, 0x0002a002, AR5K_PHY(11)); |
704 | 697 | ||
705 | if (channel->val == CHANNEL_G) | 698 | if (channel->hw_value == CHANNEL_G) |
706 | ath5k_hw_reg_write(ah, 0x00f80d80, AR5K_PHY(83)); /* 0x00fc0ec0 */ | 699 | ath5k_hw_reg_write(ah, 0x00f80d80, AR5K_PHY(83)); /* 0x00fc0ec0 */ |
707 | else | 700 | else |
708 | ath5k_hw_reg_write(ah, 0x00000000, AR5K_PHY(83)); | 701 | ath5k_hw_reg_write(ah, 0x00000000, AR5K_PHY(83)); |
@@ -720,7 +713,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode, | |||
720 | AR5K_SREV_RAD_5112A) { | 713 | AR5K_SREV_RAD_5112A) { |
721 | ath5k_hw_reg_write(ah, AR5K_PHY_CCKTXCTL_WORLD, | 714 | ath5k_hw_reg_write(ah, AR5K_PHY_CCKTXCTL_WORLD, |
722 | AR5K_PHY_CCKTXCTL); | 715 | AR5K_PHY_CCKTXCTL); |
723 | if (channel->val & CHANNEL_5GHZ) | 716 | if (channel->hw_value & CHANNEL_5GHZ) |
724 | data = 0xffb81020; | 717 | data = 0xffb81020; |
725 | else | 718 | else |
726 | data = 0xffb80d20; | 719 | data = 0xffb80d20; |
@@ -740,7 +733,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode, | |||
740 | * mac80211 are integrated */ | 733 | * mac80211 are integrated */ |
741 | if (ah->ah_version == AR5K_AR5212 && | 734 | if (ah->ah_version == AR5K_AR5212 && |
742 | ah->ah_sc->vif != NULL) | 735 | ah->ah_sc->vif != NULL) |
743 | ath5k_hw_write_rate_duration(ah, driver_mode); | 736 | ath5k_hw_write_rate_duration(ah, mode); |
744 | 737 | ||
745 | /* | 738 | /* |
746 | * Write RF registers | 739 | * Write RF registers |
@@ -756,7 +749,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode, | |||
756 | 749 | ||
757 | /* Write OFDM timings on 5212*/ | 750 | /* Write OFDM timings on 5212*/ |
758 | if (ah->ah_version == AR5K_AR5212 && | 751 | if (ah->ah_version == AR5K_AR5212 && |
759 | channel->val & CHANNEL_OFDM) { | 752 | channel->hw_value & CHANNEL_OFDM) { |
760 | ret = ath5k_hw_write_ofdm_timings(ah, channel); | 753 | ret = ath5k_hw_write_ofdm_timings(ah, channel); |
761 | if (ret) | 754 | if (ret) |
762 | return ret; | 755 | return ret; |
@@ -765,7 +758,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode, | |||
765 | /*Enable/disable 802.11b mode on 5111 | 758 | /*Enable/disable 802.11b mode on 5111 |
766 | (enable 2111 frequency converter + CCK)*/ | 759 | (enable 2111 frequency converter + CCK)*/ |
767 | if (ah->ah_radio == AR5K_RF5111) { | 760 | if (ah->ah_radio == AR5K_RF5111) { |
768 | if (driver_mode == MODE_IEEE80211B) | 761 | if (mode == AR5K_MODE_11B) |
769 | AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, | 762 | AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, |
770 | AR5K_TXCFG_B_MODE); | 763 | AR5K_TXCFG_B_MODE); |
771 | else | 764 | else |
@@ -903,7 +896,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode, | |||
903 | if (ah->ah_version != AR5K_AR5210) { | 896 | if (ah->ah_version != AR5K_AR5210) { |
904 | data = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) & | 897 | data = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) & |
905 | AR5K_PHY_RX_DELAY_M; | 898 | AR5K_PHY_RX_DELAY_M; |
906 | data = (channel->val & CHANNEL_CCK) ? | 899 | data = (channel->hw_value & CHANNEL_CCK) ? |
907 | ((data << 2) / 22) : (data / 10); | 900 | ((data << 2) / 22) : (data / 10); |
908 | 901 | ||
909 | udelay(100 + data); | 902 | udelay(100 + data); |
@@ -920,11 +913,11 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode, | |||
920 | if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, | 913 | if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, |
921 | AR5K_PHY_AGCCTL_CAL, 0, false)) { | 914 | AR5K_PHY_AGCCTL_CAL, 0, false)) { |
922 | ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n", | 915 | ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n", |
923 | channel->freq); | 916 | channel->center_freq); |
924 | return -EAGAIN; | 917 | return -EAGAIN; |
925 | } | 918 | } |
926 | 919 | ||
927 | ret = ath5k_hw_noise_floor_calibration(ah, channel->freq); | 920 | ret = ath5k_hw_noise_floor_calibration(ah, channel->center_freq); |
928 | if (ret) | 921 | if (ret) |
929 | return ret; | 922 | return ret; |
930 | 923 | ||
@@ -932,7 +925,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode, | |||
932 | 925 | ||
933 | /* A and G modes can use QAM modulation which requires enabling | 926 | /* A and G modes can use QAM modulation which requires enabling |
934 | * I and Q calibration. Don't bother in B mode. */ | 927 | * I and Q calibration. Don't bother in B mode. */ |
935 | if (!(driver_mode == MODE_IEEE80211B)) { | 928 | if (!(mode == AR5K_MODE_11B)) { |
936 | ah->ah_calibration = true; | 929 | ah->ah_calibration = true; |
937 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, | 930 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, |
938 | AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); | 931 | AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); |
@@ -1590,9 +1583,10 @@ static int ath5k_hw_eeprom_read(struct ath5k_hw *ah, u32 offset, u16 *data) | |||
1590 | /* | 1583 | /* |
1591 | * Write to eeprom - currently disabled, use at your own risk | 1584 | * Write to eeprom - currently disabled, use at your own risk |
1592 | */ | 1585 | */ |
1586 | #if 0 | ||
1593 | static int ath5k_hw_eeprom_write(struct ath5k_hw *ah, u32 offset, u16 data) | 1587 | static int ath5k_hw_eeprom_write(struct ath5k_hw *ah, u32 offset, u16 data) |
1594 | { | 1588 | { |
1595 | #if 0 | 1589 | |
1596 | u32 status, timeout; | 1590 | u32 status, timeout; |
1597 | 1591 | ||
1598 | ATH5K_TRACE(ah->ah_sc); | 1592 | ATH5K_TRACE(ah->ah_sc); |
@@ -1634,10 +1628,11 @@ static int ath5k_hw_eeprom_write(struct ath5k_hw *ah, u32 offset, u16 data) | |||
1634 | } | 1628 | } |
1635 | udelay(15); | 1629 | udelay(15); |
1636 | } | 1630 | } |
1637 | #endif | 1631 | |
1638 | ATH5K_ERR(ah->ah_sc, "EEPROM Write is disabled!"); | 1632 | ATH5K_ERR(ah->ah_sc, "EEPROM Write is disabled!"); |
1639 | return -EIO; | 1633 | return -EIO; |
1640 | } | 1634 | } |
1635 | #endif | ||
1641 | 1636 | ||
1642 | /* | 1637 | /* |
1643 | * Translate binary channel representation in EEPROM to frequency | 1638 | * Translate binary channel representation in EEPROM to frequency |
@@ -2043,50 +2038,6 @@ static int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac) | |||
2043 | } | 2038 | } |
2044 | 2039 | ||
2045 | /* | 2040 | /* |
2046 | * Read/Write regulatory domain | ||
2047 | */ | ||
2048 | static bool ath5k_eeprom_regulation_domain(struct ath5k_hw *ah, bool write, | ||
2049 | enum ath5k_regdom *regdomain) | ||
2050 | { | ||
2051 | u16 ee_regdomain; | ||
2052 | |||
2053 | /* Read current value */ | ||
2054 | if (write != true) { | ||
2055 | ee_regdomain = ah->ah_capabilities.cap_eeprom.ee_regdomain; | ||
2056 | *regdomain = ath5k_regdom_to_ieee(ee_regdomain); | ||
2057 | return true; | ||
2058 | } | ||
2059 | |||
2060 | ee_regdomain = ath5k_regdom_from_ieee(*regdomain); | ||
2061 | |||
2062 | /* Try to write a new value */ | ||
2063 | if (ah->ah_capabilities.cap_eeprom.ee_protect & | ||
2064 | AR5K_EEPROM_PROTECT_WR_128_191) | ||
2065 | return false; | ||
2066 | if (ath5k_hw_eeprom_write(ah, AR5K_EEPROM_REG_DOMAIN, ee_regdomain)!=0) | ||
2067 | return false; | ||
2068 | |||
2069 | ah->ah_capabilities.cap_eeprom.ee_regdomain = ee_regdomain; | ||
2070 | |||
2071 | return true; | ||
2072 | } | ||
2073 | |||
2074 | /* | ||
2075 | * Use the above to write a new regulatory domain | ||
2076 | */ | ||
2077 | int ath5k_hw_set_regdomain(struct ath5k_hw *ah, u16 regdomain) | ||
2078 | { | ||
2079 | enum ath5k_regdom ieee_regdomain; | ||
2080 | |||
2081 | ieee_regdomain = ath5k_regdom_to_ieee(regdomain); | ||
2082 | |||
2083 | if (ath5k_eeprom_regulation_domain(ah, true, &ieee_regdomain) == true) | ||
2084 | return 0; | ||
2085 | |||
2086 | return -EIO; | ||
2087 | } | ||
2088 | |||
2089 | /* | ||
2090 | * Fill the capabilities struct | 2041 | * Fill the capabilities struct |
2091 | */ | 2042 | */ |
2092 | static int ath5k_hw_get_capabilities(struct ath5k_hw *ah) | 2043 | static int ath5k_hw_get_capabilities(struct ath5k_hw *ah) |
@@ -2108,8 +2059,8 @@ static int ath5k_hw_get_capabilities(struct ath5k_hw *ah) | |||
2108 | ah->ah_capabilities.cap_range.range_2ghz_max = 0; | 2059 | ah->ah_capabilities.cap_range.range_2ghz_max = 0; |
2109 | 2060 | ||
2110 | /* Set supported modes */ | 2061 | /* Set supported modes */ |
2111 | __set_bit(MODE_IEEE80211A, ah->ah_capabilities.cap_mode); | 2062 | __set_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode); |
2112 | __set_bit(MODE_ATHEROS_TURBO, ah->ah_capabilities.cap_mode); | 2063 | __set_bit(AR5K_MODE_11A_TURBO, ah->ah_capabilities.cap_mode); |
2113 | } else { | 2064 | } else { |
2114 | /* | 2065 | /* |
2115 | * XXX The tranceiver supports frequencies from 4920 to 6100GHz | 2066 | * XXX The tranceiver supports frequencies from 4920 to 6100GHz |
@@ -2131,12 +2082,12 @@ static int ath5k_hw_get_capabilities(struct ath5k_hw *ah) | |||
2131 | ah->ah_capabilities.cap_range.range_5ghz_max = 6100; | 2082 | ah->ah_capabilities.cap_range.range_5ghz_max = 6100; |
2132 | 2083 | ||
2133 | /* Set supported modes */ | 2084 | /* Set supported modes */ |
2134 | __set_bit(MODE_IEEE80211A, | 2085 | __set_bit(AR5K_MODE_11A, |
2135 | ah->ah_capabilities.cap_mode); | 2086 | ah->ah_capabilities.cap_mode); |
2136 | __set_bit(MODE_ATHEROS_TURBO, | 2087 | __set_bit(AR5K_MODE_11A_TURBO, |
2137 | ah->ah_capabilities.cap_mode); | 2088 | ah->ah_capabilities.cap_mode); |
2138 | if (ah->ah_version == AR5K_AR5212) | 2089 | if (ah->ah_version == AR5K_AR5212) |
2139 | __set_bit(MODE_ATHEROS_TURBOG, | 2090 | __set_bit(AR5K_MODE_11G_TURBO, |
2140 | ah->ah_capabilities.cap_mode); | 2091 | ah->ah_capabilities.cap_mode); |
2141 | } | 2092 | } |
2142 | 2093 | ||
@@ -2148,11 +2099,11 @@ static int ath5k_hw_get_capabilities(struct ath5k_hw *ah) | |||
2148 | ah->ah_capabilities.cap_range.range_2ghz_max = 2732; | 2099 | ah->ah_capabilities.cap_range.range_2ghz_max = 2732; |
2149 | 2100 | ||
2150 | if (AR5K_EEPROM_HDR_11B(ee_header)) | 2101 | if (AR5K_EEPROM_HDR_11B(ee_header)) |
2151 | __set_bit(MODE_IEEE80211B, | 2102 | __set_bit(AR5K_MODE_11B, |
2152 | ah->ah_capabilities.cap_mode); | 2103 | ah->ah_capabilities.cap_mode); |
2153 | 2104 | ||
2154 | if (AR5K_EEPROM_HDR_11G(ee_header)) | 2105 | if (AR5K_EEPROM_HDR_11G(ee_header)) |
2155 | __set_bit(MODE_IEEE80211G, | 2106 | __set_bit(AR5K_MODE_11G, |
2156 | ah->ah_capabilities.cap_mode); | 2107 | ah->ah_capabilities.cap_mode); |
2157 | } | 2108 | } |
2158 | } | 2109 | } |
@@ -4248,35 +4199,6 @@ void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio, | |||
4248 | } | 4199 | } |
4249 | 4200 | ||
4250 | 4201 | ||
4251 | /*********************************\ | ||
4252 | Regulatory Domain/Channels Setup | ||
4253 | \*********************************/ | ||
4254 | |||
4255 | u16 ath5k_get_regdomain(struct ath5k_hw *ah) | ||
4256 | { | ||
4257 | u16 regdomain; | ||
4258 | enum ath5k_regdom ieee_regdomain; | ||
4259 | #ifdef COUNTRYCODE | ||
4260 | u16 code; | ||
4261 | #endif | ||
4262 | |||
4263 | ath5k_eeprom_regulation_domain(ah, false, &ieee_regdomain); | ||
4264 | ah->ah_capabilities.cap_regdomain.reg_hw = ieee_regdomain; | ||
4265 | |||
4266 | #ifdef COUNTRYCODE | ||
4267 | /* | ||
4268 | * Get the regulation domain by country code. This will ignore | ||
4269 | * the settings found in the EEPROM. | ||
4270 | */ | ||
4271 | code = ieee80211_name2countrycode(COUNTRYCODE); | ||
4272 | ieee_regdomain = ieee80211_countrycode2regdomain(code); | ||
4273 | #endif | ||
4274 | |||
4275 | regdomain = ath5k_regdom_from_ieee(ieee_regdomain); | ||
4276 | ah->ah_capabilities.cap_regdomain.reg_current = regdomain; | ||
4277 | |||
4278 | return regdomain; | ||
4279 | } | ||
4280 | 4202 | ||
4281 | 4203 | ||
4282 | /****************\ | 4204 | /****************\ |
diff --git a/drivers/net/wireless/ath5k/initvals.c b/drivers/net/wireless/ath5k/initvals.c index 2c22f1d4ee64..a255d8bfa949 100644 --- a/drivers/net/wireless/ath5k/initvals.c +++ b/drivers/net/wireless/ath5k/initvals.c | |||
@@ -1317,7 +1317,7 @@ int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel) | |||
1317 | /* For AR5211 */ | 1317 | /* For AR5211 */ |
1318 | } else if (ah->ah_version == AR5K_AR5211) { | 1318 | } else if (ah->ah_version == AR5K_AR5211) { |
1319 | 1319 | ||
1320 | if(mode > 2){ /* AR5K_INI_VAL_11B */ | 1320 | if(mode > 2){ /* AR5K_MODE_11B */ |
1321 | ATH5K_ERR(ah->ah_sc,"unsupported channel mode: %d\n", mode); | 1321 | ATH5K_ERR(ah->ah_sc,"unsupported channel mode: %d\n", mode); |
1322 | return -EINVAL; | 1322 | return -EINVAL; |
1323 | } | 1323 | } |
diff --git a/drivers/net/wireless/ath5k/phy.c b/drivers/net/wireless/ath5k/phy.c index b95941797141..8b576b314cf5 100644 --- a/drivers/net/wireless/ath5k/phy.c +++ b/drivers/net/wireless/ath5k/phy.c | |||
@@ -1018,7 +1018,7 @@ static int ath5k_hw_rf5111_rfregs(struct ath5k_hw *ah, | |||
1018 | int obdb = -1, bank = -1; | 1018 | int obdb = -1, bank = -1; |
1019 | u32 ee_mode; | 1019 | u32 ee_mode; |
1020 | 1020 | ||
1021 | AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX); | 1021 | AR5K_ASSERT_ENTRY(mode, AR5K_MODE_MAX); |
1022 | 1022 | ||
1023 | rf = ah->ah_rf_banks; | 1023 | rf = ah->ah_rf_banks; |
1024 | 1024 | ||
@@ -1038,8 +1038,8 @@ static int ath5k_hw_rf5111_rfregs(struct ath5k_hw *ah, | |||
1038 | } | 1038 | } |
1039 | 1039 | ||
1040 | /* Modify bank 0 */ | 1040 | /* Modify bank 0 */ |
1041 | if (channel->val & CHANNEL_2GHZ) { | 1041 | if (channel->hw_value & CHANNEL_2GHZ) { |
1042 | if (channel->val & CHANNEL_CCK) | 1042 | if (channel->hw_value & CHANNEL_CCK) |
1043 | ee_mode = AR5K_EEPROM_MODE_11B; | 1043 | ee_mode = AR5K_EEPROM_MODE_11B; |
1044 | else | 1044 | else |
1045 | ee_mode = AR5K_EEPROM_MODE_11G; | 1045 | ee_mode = AR5K_EEPROM_MODE_11G; |
@@ -1058,10 +1058,10 @@ static int ath5k_hw_rf5111_rfregs(struct ath5k_hw *ah, | |||
1058 | } else { | 1058 | } else { |
1059 | /* For 11a, Turbo and XR */ | 1059 | /* For 11a, Turbo and XR */ |
1060 | ee_mode = AR5K_EEPROM_MODE_11A; | 1060 | ee_mode = AR5K_EEPROM_MODE_11A; |
1061 | obdb = channel->freq >= 5725 ? 3 : | 1061 | obdb = channel->center_freq >= 5725 ? 3 : |
1062 | (channel->freq >= 5500 ? 2 : | 1062 | (channel->center_freq >= 5500 ? 2 : |
1063 | (channel->freq >= 5260 ? 1 : | 1063 | (channel->center_freq >= 5260 ? 1 : |
1064 | (channel->freq > 4000 ? 0 : -1))); | 1064 | (channel->center_freq > 4000 ? 0 : -1))); |
1065 | 1065 | ||
1066 | if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6], | 1066 | if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6], |
1067 | ee->ee_pwd_84, 1, 51, 3, true)) | 1067 | ee->ee_pwd_84, 1, 51, 3, true)) |
@@ -1119,12 +1119,12 @@ static int ath5k_hw_rf5112_rfregs(struct ath5k_hw *ah, | |||
1119 | int obdb = -1, bank = -1; | 1119 | int obdb = -1, bank = -1; |
1120 | u32 ee_mode; | 1120 | u32 ee_mode; |
1121 | 1121 | ||
1122 | AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX); | 1122 | AR5K_ASSERT_ENTRY(mode, AR5K_MODE_MAX); |
1123 | 1123 | ||
1124 | rf = ah->ah_rf_banks; | 1124 | rf = ah->ah_rf_banks; |
1125 | 1125 | ||
1126 | if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_2112A | 1126 | if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_2112A |
1127 | && !test_bit(MODE_IEEE80211A, ah->ah_capabilities.cap_mode)){ | 1127 | && !test_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode)){ |
1128 | rf_ini = rfregs_2112a; | 1128 | rf_ini = rfregs_2112a; |
1129 | rf_size = ARRAY_SIZE(rfregs_5112a); | 1129 | rf_size = ARRAY_SIZE(rfregs_5112a); |
1130 | if (mode < 2) { | 1130 | if (mode < 2) { |
@@ -1156,8 +1156,8 @@ static int ath5k_hw_rf5112_rfregs(struct ath5k_hw *ah, | |||
1156 | } | 1156 | } |
1157 | 1157 | ||
1158 | /* Modify bank 6 */ | 1158 | /* Modify bank 6 */ |
1159 | if (channel->val & CHANNEL_2GHZ) { | 1159 | if (channel->hw_value & CHANNEL_2GHZ) { |
1160 | if (channel->val & CHANNEL_OFDM) | 1160 | if (channel->hw_value & CHANNEL_OFDM) |
1161 | ee_mode = AR5K_EEPROM_MODE_11G; | 1161 | ee_mode = AR5K_EEPROM_MODE_11G; |
1162 | else | 1162 | else |
1163 | ee_mode = AR5K_EEPROM_MODE_11B; | 1163 | ee_mode = AR5K_EEPROM_MODE_11B; |
@@ -1173,10 +1173,10 @@ static int ath5k_hw_rf5112_rfregs(struct ath5k_hw *ah, | |||
1173 | } else { | 1173 | } else { |
1174 | /* For 11a, Turbo and XR */ | 1174 | /* For 11a, Turbo and XR */ |
1175 | ee_mode = AR5K_EEPROM_MODE_11A; | 1175 | ee_mode = AR5K_EEPROM_MODE_11A; |
1176 | obdb = channel->freq >= 5725 ? 3 : | 1176 | obdb = channel->center_freq >= 5725 ? 3 : |
1177 | (channel->freq >= 5500 ? 2 : | 1177 | (channel->center_freq >= 5500 ? 2 : |
1178 | (channel->freq >= 5260 ? 1 : | 1178 | (channel->center_freq >= 5260 ? 1 : |
1179 | (channel->freq > 4000 ? 0 : -1))); | 1179 | (channel->center_freq > 4000 ? 0 : -1))); |
1180 | 1180 | ||
1181 | if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6], | 1181 | if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6], |
1182 | ee->ee_ob[ee_mode][obdb], 3, 279, 0, true)) | 1182 | ee->ee_ob[ee_mode][obdb], 3, 279, 0, true)) |
@@ -1219,7 +1219,7 @@ static int ath5k_hw_rf5413_rfregs(struct ath5k_hw *ah, | |||
1219 | unsigned int rf_size, i; | 1219 | unsigned int rf_size, i; |
1220 | int bank = -1; | 1220 | int bank = -1; |
1221 | 1221 | ||
1222 | AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX); | 1222 | AR5K_ASSERT_ENTRY(mode, AR5K_MODE_MAX); |
1223 | 1223 | ||
1224 | rf = ah->ah_rf_banks; | 1224 | rf = ah->ah_rf_banks; |
1225 | 1225 | ||
@@ -1445,7 +1445,7 @@ static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel) | |||
1445 | * newer chipsets like the AR5212A who have a completely | 1445 | * newer chipsets like the AR5212A who have a completely |
1446 | * different RF/PHY part. | 1446 | * different RF/PHY part. |
1447 | */ | 1447 | */ |
1448 | athchan = (ath5k_hw_bitswap((channel->chan - 24) / 2, 5) << 1) | | 1448 | athchan = (ath5k_hw_bitswap((ieee80211_frequency_to_channel(channel->center_freq) - 24) / 2, 5) << 1) | |
1449 | (1 << 6) | 0x1; | 1449 | (1 << 6) | 0x1; |
1450 | 1450 | ||
1451 | return athchan; | 1451 | return athchan; |
@@ -1506,7 +1506,7 @@ static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah, | |||
1506 | struct ieee80211_channel *channel) | 1506 | struct ieee80211_channel *channel) |
1507 | { | 1507 | { |
1508 | struct ath5k_athchan_2ghz ath5k_channel_2ghz; | 1508 | struct ath5k_athchan_2ghz ath5k_channel_2ghz; |
1509 | unsigned int ath5k_channel = channel->chan; | 1509 | unsigned int ath5k_channel = ieee80211_frequency_to_channel(channel->center_freq); |
1510 | u32 data0, data1, clock; | 1510 | u32 data0, data1, clock; |
1511 | int ret; | 1511 | int ret; |
1512 | 1512 | ||
@@ -1515,9 +1515,9 @@ static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah, | |||
1515 | */ | 1515 | */ |
1516 | data0 = data1 = 0; | 1516 | data0 = data1 = 0; |
1517 | 1517 | ||
1518 | if (channel->val & CHANNEL_2GHZ) { | 1518 | if (channel->hw_value & CHANNEL_2GHZ) { |
1519 | /* Map 2GHz channel to 5GHz Atheros channel ID */ | 1519 | /* Map 2GHz channel to 5GHz Atheros channel ID */ |
1520 | ret = ath5k_hw_rf5111_chan2athchan(channel->chan, | 1520 | ret = ath5k_hw_rf5111_chan2athchan(ieee80211_frequency_to_channel(channel->center_freq), |
1521 | &ath5k_channel_2ghz); | 1521 | &ath5k_channel_2ghz); |
1522 | if (ret) | 1522 | if (ret) |
1523 | return ret; | 1523 | return ret; |
@@ -1555,7 +1555,7 @@ static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah, | |||
1555 | u16 c; | 1555 | u16 c; |
1556 | 1556 | ||
1557 | data = data0 = data1 = data2 = 0; | 1557 | data = data0 = data1 = data2 = 0; |
1558 | c = channel->freq; | 1558 | c = channel->center_freq; |
1559 | 1559 | ||
1560 | /* | 1560 | /* |
1561 | * Set the channel on the RF5112 or newer | 1561 | * Set the channel on the RF5112 or newer |
@@ -1604,13 +1604,13 @@ int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel) | |||
1604 | * Check bounds supported by the PHY | 1604 | * Check bounds supported by the PHY |
1605 | * (don't care about regulation restrictions at this point) | 1605 | * (don't care about regulation restrictions at this point) |
1606 | */ | 1606 | */ |
1607 | if ((channel->freq < ah->ah_capabilities.cap_range.range_2ghz_min || | 1607 | if ((channel->center_freq < ah->ah_capabilities.cap_range.range_2ghz_min || |
1608 | channel->freq > ah->ah_capabilities.cap_range.range_2ghz_max) && | 1608 | channel->center_freq > ah->ah_capabilities.cap_range.range_2ghz_max) && |
1609 | (channel->freq < ah->ah_capabilities.cap_range.range_5ghz_min || | 1609 | (channel->center_freq < ah->ah_capabilities.cap_range.range_5ghz_min || |
1610 | channel->freq > ah->ah_capabilities.cap_range.range_5ghz_max)) { | 1610 | channel->center_freq > ah->ah_capabilities.cap_range.range_5ghz_max)) { |
1611 | ATH5K_ERR(ah->ah_sc, | 1611 | ATH5K_ERR(ah->ah_sc, |
1612 | "channel out of supported range (%u MHz)\n", | 1612 | "channel out of supported range (%u MHz)\n", |
1613 | channel->freq); | 1613 | channel->center_freq); |
1614 | return -EINVAL; | 1614 | return -EINVAL; |
1615 | } | 1615 | } |
1616 | 1616 | ||
@@ -1632,9 +1632,9 @@ int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel) | |||
1632 | if (ret) | 1632 | if (ret) |
1633 | return ret; | 1633 | return ret; |
1634 | 1634 | ||
1635 | ah->ah_current_channel.freq = channel->freq; | 1635 | ah->ah_current_channel.center_freq = channel->center_freq; |
1636 | ah->ah_current_channel.val = channel->val; | 1636 | ah->ah_current_channel.hw_value = channel->hw_value; |
1637 | ah->ah_turbo = channel->val == CHANNEL_T ? true : false; | 1637 | ah->ah_turbo = channel->hw_value == CHANNEL_T ? true : false; |
1638 | 1638 | ||
1639 | return 0; | 1639 | return 0; |
1640 | } | 1640 | } |
@@ -1797,11 +1797,11 @@ static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah, | |||
1797 | 1797 | ||
1798 | if (ret) { | 1798 | if (ret) { |
1799 | ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n", | 1799 | ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n", |
1800 | channel->freq); | 1800 | channel->center_freq); |
1801 | return ret; | 1801 | return ret; |
1802 | } | 1802 | } |
1803 | 1803 | ||
1804 | ret = ath5k_hw_noise_floor_calibration(ah, channel->freq); | 1804 | ret = ath5k_hw_noise_floor_calibration(ah, channel->center_freq); |
1805 | if (ret) | 1805 | if (ret) |
1806 | return ret; | 1806 | return ret; |
1807 | 1807 | ||
@@ -1848,10 +1848,10 @@ static int ath5k_hw_rf511x_calibrate(struct ath5k_hw *ah, | |||
1848 | ((u32)q_coff) | ((u32)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S)); | 1848 | ((u32)q_coff) | ((u32)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S)); |
1849 | 1849 | ||
1850 | done: | 1850 | done: |
1851 | ath5k_hw_noise_floor_calibration(ah, channel->freq); | 1851 | ath5k_hw_noise_floor_calibration(ah, channel->center_freq); |
1852 | 1852 | ||
1853 | /* Request RF gain */ | 1853 | /* Request RF gain */ |
1854 | if (channel->val & CHANNEL_5GHZ) { | 1854 | if (channel->hw_value & CHANNEL_5GHZ) { |
1855 | ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_max, | 1855 | ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_max, |
1856 | AR5K_PHY_PAPD_PROBE_TXPOWER) | | 1856 | AR5K_PHY_PAPD_PROBE_TXPOWER) | |
1857 | AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE); | 1857 | AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE); |