diff options
Diffstat (limited to 'drivers/net/wireless/ath5k/reg.h')
| -rw-r--r-- | drivers/net/wireless/ath5k/reg.h | 102 |
1 files changed, 5 insertions, 97 deletions
diff --git a/drivers/net/wireless/ath5k/reg.h b/drivers/net/wireless/ath5k/reg.h index 7562bf173d3e..a98832364448 100644 --- a/drivers/net/wireless/ath5k/reg.h +++ b/drivers/net/wireless/ath5k/reg.h | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright (c) 2007 Nick Kossifidis <mickflemm@gmail.com> | 2 | * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com> |
| 3 | * Copyright (c) 2004, 2005, 2006, 2007 Reyk Floeter <reyk@openbsd.org> | 3 | * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> |
| 4 | * Copyright (c) 2007 Michael Taylor <mike.taylor@apprion.com> | 4 | * Copyright (c) 2007-2008 Michael Taylor <mike.taylor@apprion.com> |
| 5 | * | 5 | * |
| 6 | * Permission to use, copy, modify, and distribute this software for any | 6 | * Permission to use, copy, modify, and distribute this software for any |
| 7 | * purpose with or without fee is hereby granted, provided that the above | 7 | * purpose with or without fee is hereby granted, provided that the above |
| @@ -977,98 +977,6 @@ | |||
| 977 | #define AR5K_EEPROM_BASE 0x6000 | 977 | #define AR5K_EEPROM_BASE 0x6000 |
| 978 | 978 | ||
| 979 | /* | 979 | /* |
| 980 | * Common ar5xxx EEPROM data offsets (set these on AR5K_EEPROM_BASE) | ||
| 981 | */ | ||
| 982 | #define AR5K_EEPROM_MAGIC 0x003d /* EEPROM Magic number */ | ||
| 983 | #define AR5K_EEPROM_MAGIC_VALUE 0x5aa5 /* Default - found on EEPROM */ | ||
| 984 | #define AR5K_EEPROM_MAGIC_5212 0x0000145c /* 5212 */ | ||
| 985 | #define AR5K_EEPROM_MAGIC_5211 0x0000145b /* 5211 */ | ||
| 986 | #define AR5K_EEPROM_MAGIC_5210 0x0000145a /* 5210 */ | ||
| 987 | |||
| 988 | #define AR5K_EEPROM_PROTECT 0x003f /* EEPROM protect status */ | ||
| 989 | #define AR5K_EEPROM_PROTECT_RD_0_31 0x0001 /* Read protection bit for offsets 0x0 - 0x1f */ | ||
| 990 | #define AR5K_EEPROM_PROTECT_WR_0_31 0x0002 /* Write protection bit for offsets 0x0 - 0x1f */ | ||
| 991 | #define AR5K_EEPROM_PROTECT_RD_32_63 0x0004 /* 0x20 - 0x3f */ | ||
| 992 | #define AR5K_EEPROM_PROTECT_WR_32_63 0x0008 | ||
| 993 | #define AR5K_EEPROM_PROTECT_RD_64_127 0x0010 /* 0x40 - 0x7f */ | ||
| 994 | #define AR5K_EEPROM_PROTECT_WR_64_127 0x0020 | ||
| 995 | #define AR5K_EEPROM_PROTECT_RD_128_191 0x0040 /* 0x80 - 0xbf (regdom) */ | ||
| 996 | #define AR5K_EEPROM_PROTECT_WR_128_191 0x0080 | ||
| 997 | #define AR5K_EEPROM_PROTECT_RD_192_207 0x0100 /* 0xc0 - 0xcf */ | ||
| 998 | #define AR5K_EEPROM_PROTECT_WR_192_207 0x0200 | ||
| 999 | #define AR5K_EEPROM_PROTECT_RD_208_223 0x0400 /* 0xd0 - 0xdf */ | ||
| 1000 | #define AR5K_EEPROM_PROTECT_WR_208_223 0x0800 | ||
| 1001 | #define AR5K_EEPROM_PROTECT_RD_224_239 0x1000 /* 0xe0 - 0xef */ | ||
| 1002 | #define AR5K_EEPROM_PROTECT_WR_224_239 0x2000 | ||
| 1003 | #define AR5K_EEPROM_PROTECT_RD_240_255 0x4000 /* 0xf0 - 0xff */ | ||
| 1004 | #define AR5K_EEPROM_PROTECT_WR_240_255 0x8000 | ||
| 1005 | #define AR5K_EEPROM_REG_DOMAIN 0x00bf /* EEPROM regdom */ | ||
| 1006 | #define AR5K_EEPROM_INFO_BASE 0x00c0 /* EEPROM header */ | ||
| 1007 | #define AR5K_EEPROM_INFO_MAX (0x400 - AR5K_EEPROM_INFO_BASE) | ||
| 1008 | #define AR5K_EEPROM_INFO_CKSUM 0xffff | ||
| 1009 | #define AR5K_EEPROM_INFO(_n) (AR5K_EEPROM_INFO_BASE + (_n)) | ||
| 1010 | |||
| 1011 | #define AR5K_EEPROM_VERSION AR5K_EEPROM_INFO(1) /* EEPROM Version */ | ||
| 1012 | #define AR5K_EEPROM_VERSION_3_0 0x3000 /* No idea what's going on before this version */ | ||
| 1013 | #define AR5K_EEPROM_VERSION_3_1 0x3001 /* ob/db values for 2Ghz (ar5211_rfregs) */ | ||
| 1014 | #define AR5K_EEPROM_VERSION_3_2 0x3002 /* different frequency representation (eeprom_bin2freq) */ | ||
| 1015 | #define AR5K_EEPROM_VERSION_3_3 0x3003 /* offsets changed, has 32 CTLs (see below) and ee_false_detect (eeprom_read_modes) */ | ||
| 1016 | #define AR5K_EEPROM_VERSION_3_4 0x3004 /* has ee_i_gain ee_cck_ofdm_power_delta (eeprom_read_modes) */ | ||
| 1017 | #define AR5K_EEPROM_VERSION_4_0 0x4000 /* has ee_misc*, ee_cal_pier, ee_turbo_max_power and ee_xr_power (eeprom_init) */ | ||
| 1018 | #define AR5K_EEPROM_VERSION_4_1 0x4001 /* has ee_margin_tx_rx (eeprom_init) */ | ||
| 1019 | #define AR5K_EEPROM_VERSION_4_2 0x4002 /* has ee_cck_ofdm_gain_delta (eeprom_init) */ | ||
| 1020 | #define AR5K_EEPROM_VERSION_4_3 0x4003 | ||
| 1021 | #define AR5K_EEPROM_VERSION_4_4 0x4004 | ||
| 1022 | #define AR5K_EEPROM_VERSION_4_5 0x4005 | ||
| 1023 | #define AR5K_EEPROM_VERSION_4_6 0x4006 /* has ee_scaled_cck_delta */ | ||
| 1024 | #define AR5K_EEPROM_VERSION_4_7 0x4007 | ||
| 1025 | |||
| 1026 | #define AR5K_EEPROM_MODE_11A 0 | ||
| 1027 | #define AR5K_EEPROM_MODE_11B 1 | ||
| 1028 | #define AR5K_EEPROM_MODE_11G 2 | ||
| 1029 | |||
| 1030 | #define AR5K_EEPROM_HDR AR5K_EEPROM_INFO(2) /* Header that contains the device caps */ | ||
| 1031 | #define AR5K_EEPROM_HDR_11A(_v) (((_v) >> AR5K_EEPROM_MODE_11A) & 0x1) | ||
| 1032 | #define AR5K_EEPROM_HDR_11B(_v) (((_v) >> AR5K_EEPROM_MODE_11B) & 0x1) | ||
| 1033 | #define AR5K_EEPROM_HDR_11G(_v) (((_v) >> AR5K_EEPROM_MODE_11G) & 0x1) | ||
| 1034 | #define AR5K_EEPROM_HDR_T_2GHZ_DIS(_v) (((_v) >> 3) & 0x1) /* Disable turbo for 2Ghz (?) */ | ||
| 1035 | #define AR5K_EEPROM_HDR_T_5GHZ_DBM(_v) (((_v) >> 4) & 0x7f) /* Max turbo power for a/XR mode (eeprom_init) */ | ||
| 1036 | #define AR5K_EEPROM_HDR_DEVICE(_v) (((_v) >> 11) & 0x7) | ||
| 1037 | #define AR5K_EEPROM_HDR_T_5GHZ_DIS(_v) (((_v) >> 15) & 0x1) /* Disable turbo for 5Ghz (?) */ | ||
| 1038 | #define AR5K_EEPROM_HDR_RFKILL(_v) (((_v) >> 14) & 0x1) /* Device has RFKill support */ | ||
| 1039 | |||
| 1040 | #define AR5K_EEPROM_RFKILL_GPIO_SEL 0x0000001c | ||
| 1041 | #define AR5K_EEPROM_RFKILL_GPIO_SEL_S 2 | ||
| 1042 | #define AR5K_EEPROM_RFKILL_POLARITY 0x00000002 | ||
| 1043 | #define AR5K_EEPROM_RFKILL_POLARITY_S 1 | ||
| 1044 | |||
| 1045 | /* Newer EEPROMs are using a different offset */ | ||
| 1046 | #define AR5K_EEPROM_OFF(_v, _v3_0, _v3_3) \ | ||
| 1047 | (((_v) >= AR5K_EEPROM_VERSION_3_3) ? _v3_3 : _v3_0) | ||
| 1048 | |||
| 1049 | #define AR5K_EEPROM_ANT_GAIN(_v) AR5K_EEPROM_OFF(_v, 0x00c4, 0x00c3) | ||
| 1050 | #define AR5K_EEPROM_ANT_GAIN_5GHZ(_v) ((int8_t)(((_v) >> 8) & 0xff)) | ||
| 1051 | #define AR5K_EEPROM_ANT_GAIN_2GHZ(_v) ((int8_t)((_v) & 0xff)) | ||
| 1052 | |||
| 1053 | /* calibration settings */ | ||
| 1054 | #define AR5K_EEPROM_MODES_11A(_v) AR5K_EEPROM_OFF(_v, 0x00c5, 0x00d4) | ||
| 1055 | #define AR5K_EEPROM_MODES_11B(_v) AR5K_EEPROM_OFF(_v, 0x00d0, 0x00f2) | ||
| 1056 | #define AR5K_EEPROM_MODES_11G(_v) AR5K_EEPROM_OFF(_v, 0x00da, 0x010d) | ||
| 1057 | #define AR5K_EEPROM_CTL(_v) AR5K_EEPROM_OFF(_v, 0x00e4, 0x0128) /* Conformance test limits */ | ||
| 1058 | |||
| 1059 | /* [3.1 - 3.3] */ | ||
| 1060 | #define AR5K_EEPROM_OBDB0_2GHZ 0x00ec | ||
| 1061 | #define AR5K_EEPROM_OBDB1_2GHZ 0x00ed | ||
| 1062 | |||
| 1063 | /* Misc values available since EEPROM 4.0 */ | ||
| 1064 | #define AR5K_EEPROM_MISC0 0x00c4 | ||
| 1065 | #define AR5K_EEPROM_EARSTART(_v) ((_v) & 0xfff) | ||
| 1066 | #define AR5K_EEPROM_EEMAP(_v) (((_v) >> 14) & 0x3) | ||
| 1067 | #define AR5K_EEPROM_MISC1 0x00c5 | ||
| 1068 | #define AR5K_EEPROM_TARGET_PWRSTART(_v) ((_v) & 0xfff) | ||
| 1069 | #define AR5K_EEPROM_HAS32KHZCRYSTAL(_v) (((_v) >> 14) & 0x1) | ||
| 1070 | |||
| 1071 | /* | ||
| 1072 | * EEPROM data register | 980 | * EEPROM data register |
| 1073 | */ | 981 | */ |
| 1074 | #define AR5K_EEPROM_DATA_5211 0x6004 | 982 | #define AR5K_EEPROM_DATA_5211 0x6004 |
| @@ -1950,13 +1858,13 @@ | |||
| 1950 | #define AR5K_PHY_GAIN_OFFSET_RXTX_FLAG 0x00020000 /* RX-TX flag (?) */ | 1858 | #define AR5K_PHY_GAIN_OFFSET_RXTX_FLAG 0x00020000 /* RX-TX flag (?) */ |
| 1951 | 1859 | ||
| 1952 | /* | 1860 | /* |
| 1953 | * Desired size register | 1861 | * Desired ADC/PGA size register |
| 1954 | * (for more infos read ANI patent) | 1862 | * (for more infos read ANI patent) |
| 1955 | */ | 1863 | */ |
| 1956 | #define AR5K_PHY_DESIRED_SIZE 0x9850 /* Register Address */ | 1864 | #define AR5K_PHY_DESIRED_SIZE 0x9850 /* Register Address */ |
| 1957 | #define AR5K_PHY_DESIRED_SIZE_ADC 0x000000ff /* Mask for ADC desired size */ | 1865 | #define AR5K_PHY_DESIRED_SIZE_ADC 0x000000ff /* Mask for ADC desired size */ |
| 1958 | #define AR5K_PHY_DESIRED_SIZE_PGA 0x0000ff00 /* Mask for PGA desired size */ | 1866 | #define AR5K_PHY_DESIRED_SIZE_PGA 0x0000ff00 /* Mask for PGA desired size */ |
| 1959 | #define AR5K_PHY_DESIRED_SIZE_TOT 0x0ff00000 /* Mask for Total desired size (?) */ | 1867 | #define AR5K_PHY_DESIRED_SIZE_TOT 0x0ff00000 /* Mask for Total desired size */ |
| 1960 | 1868 | ||
| 1961 | /* | 1869 | /* |
| 1962 | * PHY signal register | 1870 | * PHY signal register |