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-rw-r--r--drivers/net/wireless/ath/ath9k/Makefile4
-rw-r--r--drivers/net/wireless/ath/ath9k/ahb.c6
-rw-r--r--drivers/net/wireless/ath/ath9k/ani.c489
-rw-r--r--drivers/net/wireless/ath/ath9k/ani.h32
-rw-r--r--drivers/net/wireless/ath/ath9k/antenna.c776
-rw-r--r--drivers/net/wireless/ath/ath9k/ar5008_phy.c176
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9002_hw.c4
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h1
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_calib.c33
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_eeprom.c16
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_hw.c87
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_mac.c7
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_mci.c734
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_mci.h40
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_paprd.c2
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_phy.c120
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_phy.h38
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9330_1p1_initvals.h53
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9330_1p2_initvals.h882
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9340_initvals.h755
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h12
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9485_initvals.h1404
-rw-r--r--drivers/net/wireless/ath/ath9k/ar955x_1p0_initvals.h1284
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h772
-rw-r--r--drivers/net/wireless/ath/ath9k/ath9k.h55
-rw-r--r--drivers/net/wireless/ath/ath9k/beacon.c23
-rw-r--r--drivers/net/wireless/ath/ath9k/btcoex.c10
-rw-r--r--drivers/net/wireless/ath/ath9k/btcoex.h4
-rw-r--r--drivers/net/wireless/ath/ath9k/debug.c11
-rw-r--r--drivers/net/wireless/ath/ath9k/debug.h1
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_4k.c5
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_9287.c2
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_def.c7
-rw-r--r--drivers/net/wireless/ath/ath9k/gpio.c69
-rw-r--r--drivers/net/wireless/ath/ath9k/htc.h4
-rw-r--r--drivers/net/wireless/ath/ath9k/htc_drv_beacon.c10
-rw-r--r--drivers/net/wireless/ath/ath9k/htc_drv_gpio.c122
-rw-r--r--drivers/net/wireless/ath/ath9k/htc_drv_init.c4
-rw-r--r--drivers/net/wireless/ath/ath9k/htc_drv_main.c78
-rw-r--r--drivers/net/wireless/ath/ath9k/htc_drv_txrx.c2
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.c269
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.h23
-rw-r--r--drivers/net/wireless/ath/ath9k/init.c18
-rw-r--r--drivers/net/wireless/ath/ath9k/link.c510
-rw-r--r--drivers/net/wireless/ath/ath9k/mac.c2
-rw-r--r--drivers/net/wireless/ath/ath9k/mac.h1
-rw-r--r--drivers/net/wireless/ath/ath9k/main.c753
-rw-r--r--drivers/net/wireless/ath/ath9k/mci.c244
-rw-r--r--drivers/net/wireless/ath/ath9k/mci.h11
-rw-r--r--drivers/net/wireless/ath/ath9k/pci.c7
-rw-r--r--drivers/net/wireless/ath/ath9k/rc.c17
-rw-r--r--drivers/net/wireless/ath/ath9k/recv.c771
-rw-r--r--drivers/net/wireless/ath/ath9k/reg.h26
-rw-r--r--drivers/net/wireless/ath/ath9k/xmit.c63
54 files changed, 4951 insertions, 5898 deletions
diff --git a/drivers/net/wireless/ath/ath9k/Makefile b/drivers/net/wireless/ath/ath9k/Makefile
index 3f0b84723789..9c41232b0cd0 100644
--- a/drivers/net/wireless/ath/ath9k/Makefile
+++ b/drivers/net/wireless/ath/ath9k/Makefile
@@ -3,7 +3,9 @@ ath9k-y += beacon.o \
3 init.o \ 3 init.o \
4 main.o \ 4 main.o \
5 recv.o \ 5 recv.o \
6 xmit.o 6 xmit.o \
7 link.o \
8 antenna.o
7 9
8ath9k-$(CONFIG_ATH9K_BTCOEX_SUPPORT) += mci.o 10ath9k-$(CONFIG_ATH9K_BTCOEX_SUPPORT) += mci.o
9ath9k-$(CONFIG_ATH9K_RATE_CONTROL) += rc.o 11ath9k-$(CONFIG_ATH9K_RATE_CONTROL) += rc.o
diff --git a/drivers/net/wireless/ath/ath9k/ahb.c b/drivers/net/wireless/ath/ath9k/ahb.c
index 5e47ca6d16a8..3a69804f4c16 100644
--- a/drivers/net/wireless/ath/ath9k/ahb.c
+++ b/drivers/net/wireless/ath/ath9k/ahb.c
@@ -35,6 +35,10 @@ static const struct platform_device_id ath9k_platform_id_table[] = {
35 .name = "ar934x_wmac", 35 .name = "ar934x_wmac",
36 .driver_data = AR9300_DEVID_AR9340, 36 .driver_data = AR9300_DEVID_AR9340,
37 }, 37 },
38 {
39 .name = "qca955x_wmac",
40 .driver_data = AR9300_DEVID_QCA955X,
41 },
38 {}, 42 {},
39}; 43};
40 44
@@ -126,7 +130,7 @@ static int ath_ahb_probe(struct platform_device *pdev)
126 sc->irq = irq; 130 sc->irq = irq;
127 131
128 /* Will be cleared in ath9k_start() */ 132 /* Will be cleared in ath9k_start() */
129 sc->sc_flags |= SC_OP_INVALID; 133 set_bit(SC_OP_INVALID, &sc->sc_flags);
130 134
131 ret = request_irq(irq, ath_isr, IRQF_SHARED, "ath9k", sc); 135 ret = request_irq(irq, ath_isr, IRQF_SHARED, "ath9k", sc);
132 if (ret) { 136 if (ret) {
diff --git a/drivers/net/wireless/ath/ath9k/ani.c b/drivers/net/wireless/ath/ath9k/ani.c
index b4c77f9d7470..ff007f500feb 100644
--- a/drivers/net/wireless/ath/ath9k/ani.c
+++ b/drivers/net/wireless/ath/ath9k/ani.c
@@ -104,11 +104,6 @@ static const struct ani_cck_level_entry cck_level_table[] = {
104#define ATH9K_ANI_CCK_DEF_LEVEL \ 104#define ATH9K_ANI_CCK_DEF_LEVEL \
105 2 /* default level - matches the INI settings */ 105 2 /* default level - matches the INI settings */
106 106
107static bool use_new_ani(struct ath_hw *ah)
108{
109 return AR_SREV_9300_20_OR_LATER(ah) || modparam_force_new_ani;
110}
111
112static void ath9k_hw_update_mibstats(struct ath_hw *ah, 107static void ath9k_hw_update_mibstats(struct ath_hw *ah,
113 struct ath9k_mib_stats *stats) 108 struct ath9k_mib_stats *stats)
114{ 109{
@@ -122,8 +117,6 @@ static void ath9k_hw_update_mibstats(struct ath_hw *ah,
122static void ath9k_ani_restart(struct ath_hw *ah) 117static void ath9k_ani_restart(struct ath_hw *ah)
123{ 118{
124 struct ar5416AniState *aniState; 119 struct ar5416AniState *aniState;
125 struct ath_common *common = ath9k_hw_common(ah);
126 u32 ofdm_base = 0, cck_base = 0;
127 120
128 if (!DO_ANI(ah)) 121 if (!DO_ANI(ah))
129 return; 122 return;
@@ -131,18 +124,10 @@ static void ath9k_ani_restart(struct ath_hw *ah)
131 aniState = &ah->curchan->ani; 124 aniState = &ah->curchan->ani;
132 aniState->listenTime = 0; 125 aniState->listenTime = 0;
133 126
134 if (!use_new_ani(ah)) {
135 ofdm_base = AR_PHY_COUNTMAX - ah->config.ofdm_trig_high;
136 cck_base = AR_PHY_COUNTMAX - ah->config.cck_trig_high;
137 }
138
139 ath_dbg(common, ANI, "Writing ofdmbase=%u cckbase=%u\n",
140 ofdm_base, cck_base);
141
142 ENABLE_REGWRITE_BUFFER(ah); 127 ENABLE_REGWRITE_BUFFER(ah);
143 128
144 REG_WRITE(ah, AR_PHY_ERR_1, ofdm_base); 129 REG_WRITE(ah, AR_PHY_ERR_1, 0);
145 REG_WRITE(ah, AR_PHY_ERR_2, cck_base); 130 REG_WRITE(ah, AR_PHY_ERR_2, 0);
146 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 131 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
147 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 132 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
148 133
@@ -154,129 +139,23 @@ static void ath9k_ani_restart(struct ath_hw *ah)
154 aniState->cckPhyErrCount = 0; 139 aniState->cckPhyErrCount = 0;
155} 140}
156 141
157static void ath9k_hw_ani_ofdm_err_trigger_old(struct ath_hw *ah)
158{
159 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
160 struct ar5416AniState *aniState;
161 int32_t rssi;
162
163 aniState = &ah->curchan->ani;
164
165 if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
166 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
167 aniState->noiseImmunityLevel + 1)) {
168 return;
169 }
170 }
171
172 if (aniState->spurImmunityLevel < HAL_SPUR_IMMUNE_MAX) {
173 if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
174 aniState->spurImmunityLevel + 1)) {
175 return;
176 }
177 }
178
179 if (ah->opmode == NL80211_IFTYPE_AP) {
180 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
181 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
182 aniState->firstepLevel + 1);
183 }
184 return;
185 }
186 rssi = BEACON_RSSI(ah);
187 if (rssi > aniState->rssiThrHigh) {
188 if (!aniState->ofdmWeakSigDetectOff) {
189 if (ath9k_hw_ani_control(ah,
190 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
191 false)) {
192 ath9k_hw_ani_control(ah,
193 ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0);
194 return;
195 }
196 }
197 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
198 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
199 aniState->firstepLevel + 1);
200 return;
201 }
202 } else if (rssi > aniState->rssiThrLow) {
203 if (aniState->ofdmWeakSigDetectOff)
204 ath9k_hw_ani_control(ah,
205 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
206 true);
207 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
208 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
209 aniState->firstepLevel + 1);
210 return;
211 } else {
212 if ((conf->channel->band == IEEE80211_BAND_2GHZ) &&
213 !conf_is_ht(conf)) {
214 if (!aniState->ofdmWeakSigDetectOff)
215 ath9k_hw_ani_control(ah,
216 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
217 false);
218 if (aniState->firstepLevel > 0)
219 ath9k_hw_ani_control(ah,
220 ATH9K_ANI_FIRSTEP_LEVEL, 0);
221 return;
222 }
223 }
224}
225
226static void ath9k_hw_ani_cck_err_trigger_old(struct ath_hw *ah)
227{
228 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
229 struct ar5416AniState *aniState;
230 int32_t rssi;
231
232 aniState = &ah->curchan->ani;
233 if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
234 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
235 aniState->noiseImmunityLevel + 1)) {
236 return;
237 }
238 }
239 if (ah->opmode == NL80211_IFTYPE_AP) {
240 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
241 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
242 aniState->firstepLevel + 1);
243 }
244 return;
245 }
246 rssi = BEACON_RSSI(ah);
247 if (rssi > aniState->rssiThrLow) {
248 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
249 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
250 aniState->firstepLevel + 1);
251 } else {
252 if ((conf->channel->band == IEEE80211_BAND_2GHZ) &&
253 !conf_is_ht(conf)) {
254 if (aniState->firstepLevel > 0)
255 ath9k_hw_ani_control(ah,
256 ATH9K_ANI_FIRSTEP_LEVEL, 0);
257 }
258 }
259}
260
261/* Adjust the OFDM Noise Immunity Level */ 142/* Adjust the OFDM Noise Immunity Level */
262static void ath9k_hw_set_ofdm_nil(struct ath_hw *ah, u8 immunityLevel) 143static void ath9k_hw_set_ofdm_nil(struct ath_hw *ah, u8 immunityLevel,
144 bool scan)
263{ 145{
264 struct ar5416AniState *aniState = &ah->curchan->ani; 146 struct ar5416AniState *aniState = &ah->curchan->ani;
265 struct ath_common *common = ath9k_hw_common(ah); 147 struct ath_common *common = ath9k_hw_common(ah);
266 const struct ani_ofdm_level_entry *entry_ofdm; 148 const struct ani_ofdm_level_entry *entry_ofdm;
267 const struct ani_cck_level_entry *entry_cck; 149 const struct ani_cck_level_entry *entry_cck;
268 150 bool weak_sig;
269 aniState->noiseFloor = BEACON_RSSI(ah);
270 151
271 ath_dbg(common, ANI, "**** ofdmlevel %d=>%d, rssi=%d[lo=%d hi=%d]\n", 152 ath_dbg(common, ANI, "**** ofdmlevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",
272 aniState->ofdmNoiseImmunityLevel, 153 aniState->ofdmNoiseImmunityLevel,
273 immunityLevel, aniState->noiseFloor, 154 immunityLevel, BEACON_RSSI(ah),
274 aniState->rssiThrLow, aniState->rssiThrHigh); 155 aniState->rssiThrLow, aniState->rssiThrHigh);
275 156
276 if (aniState->update_ani) 157 if (!scan)
277 aniState->ofdmNoiseImmunityLevel = 158 aniState->ofdmNoiseImmunityLevel = immunityLevel;
278 (immunityLevel > ATH9K_ANI_OFDM_DEF_LEVEL) ?
279 immunityLevel : ATH9K_ANI_OFDM_DEF_LEVEL;
280 159
281 entry_ofdm = &ofdm_level_table[aniState->ofdmNoiseImmunityLevel]; 160 entry_ofdm = &ofdm_level_table[aniState->ofdmNoiseImmunityLevel];
282 entry_cck = &cck_level_table[aniState->cckNoiseImmunityLevel]; 161 entry_cck = &cck_level_table[aniState->cckNoiseImmunityLevel];
@@ -292,12 +171,22 @@ static void ath9k_hw_set_ofdm_nil(struct ath_hw *ah, u8 immunityLevel)
292 ATH9K_ANI_FIRSTEP_LEVEL, 171 ATH9K_ANI_FIRSTEP_LEVEL,
293 entry_ofdm->fir_step_level); 172 entry_ofdm->fir_step_level);
294 173
295 if ((aniState->noiseFloor >= aniState->rssiThrHigh) && 174 weak_sig = entry_ofdm->ofdm_weak_signal_on;
296 (!aniState->ofdmWeakSigDetectOff != 175 if (ah->opmode == NL80211_IFTYPE_STATION &&
297 entry_ofdm->ofdm_weak_signal_on)) { 176 BEACON_RSSI(ah) <= aniState->rssiThrHigh)
177 weak_sig = true;
178
179 if (aniState->ofdmWeakSigDetect != weak_sig)
298 ath9k_hw_ani_control(ah, 180 ath9k_hw_ani_control(ah,
299 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION, 181 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
300 entry_ofdm->ofdm_weak_signal_on); 182 entry_ofdm->ofdm_weak_signal_on);
183
184 if (aniState->ofdmNoiseImmunityLevel >= ATH9K_ANI_OFDM_DEF_LEVEL) {
185 ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH;
186 ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW_ABOVE_INI;
187 } else {
188 ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_BELOW_INI;
189 ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW;
301 } 190 }
302} 191}
303 192
@@ -308,43 +197,35 @@ static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hw *ah)
308 if (!DO_ANI(ah)) 197 if (!DO_ANI(ah))
309 return; 198 return;
310 199
311 if (!use_new_ani(ah)) {
312 ath9k_hw_ani_ofdm_err_trigger_old(ah);
313 return;
314 }
315
316 aniState = &ah->curchan->ani; 200 aniState = &ah->curchan->ani;
317 201
318 if (aniState->ofdmNoiseImmunityLevel < ATH9K_ANI_OFDM_MAX_LEVEL) 202 if (aniState->ofdmNoiseImmunityLevel < ATH9K_ANI_OFDM_MAX_LEVEL)
319 ath9k_hw_set_ofdm_nil(ah, aniState->ofdmNoiseImmunityLevel + 1); 203 ath9k_hw_set_ofdm_nil(ah, aniState->ofdmNoiseImmunityLevel + 1, false);
320} 204}
321 205
322/* 206/*
323 * Set the ANI settings to match an CCK level. 207 * Set the ANI settings to match an CCK level.
324 */ 208 */
325static void ath9k_hw_set_cck_nil(struct ath_hw *ah, u_int8_t immunityLevel) 209static void ath9k_hw_set_cck_nil(struct ath_hw *ah, u_int8_t immunityLevel,
210 bool scan)
326{ 211{
327 struct ar5416AniState *aniState = &ah->curchan->ani; 212 struct ar5416AniState *aniState = &ah->curchan->ani;
328 struct ath_common *common = ath9k_hw_common(ah); 213 struct ath_common *common = ath9k_hw_common(ah);
329 const struct ani_ofdm_level_entry *entry_ofdm; 214 const struct ani_ofdm_level_entry *entry_ofdm;
330 const struct ani_cck_level_entry *entry_cck; 215 const struct ani_cck_level_entry *entry_cck;
331 216
332 aniState->noiseFloor = BEACON_RSSI(ah);
333 ath_dbg(common, ANI, "**** ccklevel %d=>%d, rssi=%d[lo=%d hi=%d]\n", 217 ath_dbg(common, ANI, "**** ccklevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",
334 aniState->cckNoiseImmunityLevel, immunityLevel, 218 aniState->cckNoiseImmunityLevel, immunityLevel,
335 aniState->noiseFloor, aniState->rssiThrLow, 219 BEACON_RSSI(ah), aniState->rssiThrLow,
336 aniState->rssiThrHigh); 220 aniState->rssiThrHigh);
337 221
338 if ((ah->opmode == NL80211_IFTYPE_STATION || 222 if (ah->opmode == NL80211_IFTYPE_STATION &&
339 ah->opmode == NL80211_IFTYPE_ADHOC) && 223 BEACON_RSSI(ah) <= aniState->rssiThrLow &&
340 aniState->noiseFloor <= aniState->rssiThrLow &&
341 immunityLevel > ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI) 224 immunityLevel > ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI)
342 immunityLevel = ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI; 225 immunityLevel = ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI;
343 226
344 if (aniState->update_ani) 227 if (!scan)
345 aniState->cckNoiseImmunityLevel = 228 aniState->cckNoiseImmunityLevel = immunityLevel;
346 (immunityLevel > ATH9K_ANI_CCK_DEF_LEVEL) ?
347 immunityLevel : ATH9K_ANI_CCK_DEF_LEVEL;
348 229
349 entry_ofdm = &ofdm_level_table[aniState->ofdmNoiseImmunityLevel]; 230 entry_ofdm = &ofdm_level_table[aniState->ofdmNoiseImmunityLevel];
350 entry_cck = &cck_level_table[aniState->cckNoiseImmunityLevel]; 231 entry_cck = &cck_level_table[aniState->cckNoiseImmunityLevel];
@@ -359,7 +240,7 @@ static void ath9k_hw_set_cck_nil(struct ath_hw *ah, u_int8_t immunityLevel)
359 if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9485(ah)) 240 if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9485(ah))
360 return; 241 return;
361 242
362 if (aniState->mrcCCKOff == entry_cck->mrc_cck_on) 243 if (aniState->mrcCCK != entry_cck->mrc_cck_on)
363 ath9k_hw_ani_control(ah, 244 ath9k_hw_ani_control(ah,
364 ATH9K_ANI_MRC_CCK, 245 ATH9K_ANI_MRC_CCK,
365 entry_cck->mrc_cck_on); 246 entry_cck->mrc_cck_on);
@@ -372,68 +253,11 @@ static void ath9k_hw_ani_cck_err_trigger(struct ath_hw *ah)
372 if (!DO_ANI(ah)) 253 if (!DO_ANI(ah))
373 return; 254 return;
374 255
375 if (!use_new_ani(ah)) {
376 ath9k_hw_ani_cck_err_trigger_old(ah);
377 return;
378 }
379
380 aniState = &ah->curchan->ani; 256 aniState = &ah->curchan->ani;
381 257
382 if (aniState->cckNoiseImmunityLevel < ATH9K_ANI_CCK_MAX_LEVEL) 258 if (aniState->cckNoiseImmunityLevel < ATH9K_ANI_CCK_MAX_LEVEL)
383 ath9k_hw_set_cck_nil(ah, aniState->cckNoiseImmunityLevel + 1); 259 ath9k_hw_set_cck_nil(ah, aniState->cckNoiseImmunityLevel + 1,
384} 260 false);
385
386static void ath9k_hw_ani_lower_immunity_old(struct ath_hw *ah)
387{
388 struct ar5416AniState *aniState;
389 int32_t rssi;
390
391 aniState = &ah->curchan->ani;
392
393 if (ah->opmode == NL80211_IFTYPE_AP) {
394 if (aniState->firstepLevel > 0) {
395 if (ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
396 aniState->firstepLevel - 1))
397 return;
398 }
399 } else {
400 rssi = BEACON_RSSI(ah);
401 if (rssi > aniState->rssiThrHigh) {
402 /* XXX: Handle me */
403 } else if (rssi > aniState->rssiThrLow) {
404 if (aniState->ofdmWeakSigDetectOff) {
405 if (ath9k_hw_ani_control(ah,
406 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
407 true))
408 return;
409 }
410 if (aniState->firstepLevel > 0) {
411 if (ath9k_hw_ani_control(ah,
412 ATH9K_ANI_FIRSTEP_LEVEL,
413 aniState->firstepLevel - 1))
414 return;
415 }
416 } else {
417 if (aniState->firstepLevel > 0) {
418 if (ath9k_hw_ani_control(ah,
419 ATH9K_ANI_FIRSTEP_LEVEL,
420 aniState->firstepLevel - 1))
421 return;
422 }
423 }
424 }
425
426 if (aniState->spurImmunityLevel > 0) {
427 if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
428 aniState->spurImmunityLevel - 1))
429 return;
430 }
431
432 if (aniState->noiseImmunityLevel > 0) {
433 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
434 aniState->noiseImmunityLevel - 1);
435 return;
436 }
437} 261}
438 262
439/* 263/*
@@ -446,87 +270,18 @@ static void ath9k_hw_ani_lower_immunity(struct ath_hw *ah)
446 270
447 aniState = &ah->curchan->ani; 271 aniState = &ah->curchan->ani;
448 272
449 if (!use_new_ani(ah)) {
450 ath9k_hw_ani_lower_immunity_old(ah);
451 return;
452 }
453
454 /* lower OFDM noise immunity */ 273 /* lower OFDM noise immunity */
455 if (aniState->ofdmNoiseImmunityLevel > 0 && 274 if (aniState->ofdmNoiseImmunityLevel > 0 &&
456 (aniState->ofdmsTurn || aniState->cckNoiseImmunityLevel == 0)) { 275 (aniState->ofdmsTurn || aniState->cckNoiseImmunityLevel == 0)) {
457 ath9k_hw_set_ofdm_nil(ah, aniState->ofdmNoiseImmunityLevel - 1); 276 ath9k_hw_set_ofdm_nil(ah, aniState->ofdmNoiseImmunityLevel - 1,
277 false);
458 return; 278 return;
459 } 279 }
460 280
461 /* lower CCK noise immunity */ 281 /* lower CCK noise immunity */
462 if (aniState->cckNoiseImmunityLevel > 0) 282 if (aniState->cckNoiseImmunityLevel > 0)
463 ath9k_hw_set_cck_nil(ah, aniState->cckNoiseImmunityLevel - 1); 283 ath9k_hw_set_cck_nil(ah, aniState->cckNoiseImmunityLevel - 1,
464} 284 false);
465
466static void ath9k_ani_reset_old(struct ath_hw *ah, bool is_scanning)
467{
468 struct ar5416AniState *aniState;
469 struct ath9k_channel *chan = ah->curchan;
470 struct ath_common *common = ath9k_hw_common(ah);
471
472 if (!DO_ANI(ah))
473 return;
474
475 aniState = &ah->curchan->ani;
476
477 if (ah->opmode != NL80211_IFTYPE_STATION
478 && ah->opmode != NL80211_IFTYPE_ADHOC) {
479 ath_dbg(common, ANI, "Reset ANI state opmode %u\n", ah->opmode);
480 ah->stats.ast_ani_reset++;
481
482 if (ah->opmode == NL80211_IFTYPE_AP) {
483 /*
484 * ath9k_hw_ani_control() will only process items set on
485 * ah->ani_function
486 */
487 if (IS_CHAN_2GHZ(chan))
488 ah->ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
489 ATH9K_ANI_FIRSTEP_LEVEL);
490 else
491 ah->ani_function = 0;
492 }
493
494 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 0);
495 ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0);
496 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 0);
497 ath9k_hw_ani_control(ah, ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
498 !ATH9K_ANI_USE_OFDM_WEAK_SIG);
499 ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR,
500 ATH9K_ANI_CCK_WEAK_SIG_THR);
501
502 ath9k_ani_restart(ah);
503 return;
504 }
505
506 if (aniState->noiseImmunityLevel != 0)
507 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
508 aniState->noiseImmunityLevel);
509 if (aniState->spurImmunityLevel != 0)
510 ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
511 aniState->spurImmunityLevel);
512 if (aniState->ofdmWeakSigDetectOff)
513 ath9k_hw_ani_control(ah, ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
514 !aniState->ofdmWeakSigDetectOff);
515 if (aniState->cckWeakSigThreshold)
516 ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR,
517 aniState->cckWeakSigThreshold);
518 if (aniState->firstepLevel != 0)
519 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
520 aniState->firstepLevel);
521
522 ath9k_ani_restart(ah);
523
524 ENABLE_REGWRITE_BUFFER(ah);
525
526 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
527 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
528
529 REGWRITE_BUFFER_FLUSH(ah);
530} 285}
531 286
532/* 287/*
@@ -539,13 +294,11 @@ void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning)
539 struct ar5416AniState *aniState = &ah->curchan->ani; 294 struct ar5416AniState *aniState = &ah->curchan->ani;
540 struct ath9k_channel *chan = ah->curchan; 295 struct ath9k_channel *chan = ah->curchan;
541 struct ath_common *common = ath9k_hw_common(ah); 296 struct ath_common *common = ath9k_hw_common(ah);
297 int ofdm_nil, cck_nil;
542 298
543 if (!DO_ANI(ah)) 299 if (!DO_ANI(ah))
544 return; 300 return;
545 301
546 if (!use_new_ani(ah))
547 return ath9k_ani_reset_old(ah, is_scanning);
548
549 BUG_ON(aniState == NULL); 302 BUG_ON(aniState == NULL);
550 ah->stats.ast_ani_reset++; 303 ah->stats.ast_ani_reset++;
551 304
@@ -563,6 +316,11 @@ void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning)
563 /* always allow mode (on/off) to be controlled */ 316 /* always allow mode (on/off) to be controlled */
564 ah->ani_function |= ATH9K_ANI_MODE; 317 ah->ani_function |= ATH9K_ANI_MODE;
565 318
319 ofdm_nil = max_t(int, ATH9K_ANI_OFDM_DEF_LEVEL,
320 aniState->ofdmNoiseImmunityLevel);
321 cck_nil = max_t(int, ATH9K_ANI_CCK_DEF_LEVEL,
322 aniState->cckNoiseImmunityLevel);
323
566 if (is_scanning || 324 if (is_scanning ||
567 (ah->opmode != NL80211_IFTYPE_STATION && 325 (ah->opmode != NL80211_IFTYPE_STATION &&
568 ah->opmode != NL80211_IFTYPE_ADHOC)) { 326 ah->opmode != NL80211_IFTYPE_ADHOC)) {
@@ -585,9 +343,8 @@ void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning)
585 aniState->ofdmNoiseImmunityLevel, 343 aniState->ofdmNoiseImmunityLevel,
586 aniState->cckNoiseImmunityLevel); 344 aniState->cckNoiseImmunityLevel);
587 345
588 aniState->update_ani = false; 346 ofdm_nil = ATH9K_ANI_OFDM_DEF_LEVEL;
589 ath9k_hw_set_ofdm_nil(ah, ATH9K_ANI_OFDM_DEF_LEVEL); 347 cck_nil = ATH9K_ANI_CCK_DEF_LEVEL;
590 ath9k_hw_set_cck_nil(ah, ATH9K_ANI_CCK_DEF_LEVEL);
591 } 348 }
592 } else { 349 } else {
593 /* 350 /*
@@ -601,13 +358,9 @@ void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning)
601 is_scanning, 358 is_scanning,
602 aniState->ofdmNoiseImmunityLevel, 359 aniState->ofdmNoiseImmunityLevel,
603 aniState->cckNoiseImmunityLevel); 360 aniState->cckNoiseImmunityLevel);
604
605 aniState->update_ani = true;
606 ath9k_hw_set_ofdm_nil(ah,
607 aniState->ofdmNoiseImmunityLevel);
608 ath9k_hw_set_cck_nil(ah,
609 aniState->cckNoiseImmunityLevel);
610 } 361 }
362 ath9k_hw_set_ofdm_nil(ah, ofdm_nil, is_scanning);
363 ath9k_hw_set_cck_nil(ah, cck_nil, is_scanning);
611 364
612 /* 365 /*
613 * enable phy counters if hw supports or if not, enable phy 366 * enable phy counters if hw supports or if not, enable phy
@@ -627,9 +380,6 @@ static bool ath9k_hw_ani_read_counters(struct ath_hw *ah)
627{ 380{
628 struct ath_common *common = ath9k_hw_common(ah); 381 struct ath_common *common = ath9k_hw_common(ah);
629 struct ar5416AniState *aniState = &ah->curchan->ani; 382 struct ar5416AniState *aniState = &ah->curchan->ani;
630 u32 ofdm_base = 0;
631 u32 cck_base = 0;
632 u32 ofdmPhyErrCnt, cckPhyErrCnt;
633 u32 phyCnt1, phyCnt2; 383 u32 phyCnt1, phyCnt2;
634 int32_t listenTime; 384 int32_t listenTime;
635 385
@@ -642,11 +392,6 @@ static bool ath9k_hw_ani_read_counters(struct ath_hw *ah)
642 return false; 392 return false;
643 } 393 }
644 394
645 if (!use_new_ani(ah)) {
646 ofdm_base = AR_PHY_COUNTMAX - ah->config.ofdm_trig_high;
647 cck_base = AR_PHY_COUNTMAX - ah->config.cck_trig_high;
648 }
649
650 aniState->listenTime += listenTime; 395 aniState->listenTime += listenTime;
651 396
652 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); 397 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
@@ -654,35 +399,12 @@ static bool ath9k_hw_ani_read_counters(struct ath_hw *ah)
654 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1); 399 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
655 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2); 400 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
656 401
657 if (!use_new_ani(ah) && (phyCnt1 < ofdm_base || phyCnt2 < cck_base)) { 402 ah->stats.ast_ani_ofdmerrs += phyCnt1 - aniState->ofdmPhyErrCount;
658 if (phyCnt1 < ofdm_base) { 403 aniState->ofdmPhyErrCount = phyCnt1;
659 ath_dbg(common, ANI,
660 "phyCnt1 0x%x, resetting counter value to 0x%x\n",
661 phyCnt1, ofdm_base);
662 REG_WRITE(ah, AR_PHY_ERR_1, ofdm_base);
663 REG_WRITE(ah, AR_PHY_ERR_MASK_1,
664 AR_PHY_ERR_OFDM_TIMING);
665 }
666 if (phyCnt2 < cck_base) {
667 ath_dbg(common, ANI,
668 "phyCnt2 0x%x, resetting counter value to 0x%x\n",
669 phyCnt2, cck_base);
670 REG_WRITE(ah, AR_PHY_ERR_2, cck_base);
671 REG_WRITE(ah, AR_PHY_ERR_MASK_2,
672 AR_PHY_ERR_CCK_TIMING);
673 }
674 return false;
675 }
676 404
677 ofdmPhyErrCnt = phyCnt1 - ofdm_base; 405 ah->stats.ast_ani_cckerrs += phyCnt2 - aniState->cckPhyErrCount;
678 ah->stats.ast_ani_ofdmerrs += 406 aniState->cckPhyErrCount = phyCnt2;
679 ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
680 aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
681 407
682 cckPhyErrCnt = phyCnt2 - cck_base;
683 ah->stats.ast_ani_cckerrs +=
684 cckPhyErrCnt - aniState->cckPhyErrCount;
685 aniState->cckPhyErrCount = cckPhyErrCnt;
686 return true; 408 return true;
687} 409}
688 410
@@ -716,21 +438,10 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan)
716 438
717 if (aniState->listenTime > ah->aniperiod) { 439 if (aniState->listenTime > ah->aniperiod) {
718 if (cckPhyErrRate < ah->config.cck_trig_low && 440 if (cckPhyErrRate < ah->config.cck_trig_low &&
719 ((ofdmPhyErrRate < ah->config.ofdm_trig_low && 441 ofdmPhyErrRate < ah->config.ofdm_trig_low) {
720 aniState->ofdmNoiseImmunityLevel <
721 ATH9K_ANI_OFDM_DEF_LEVEL) ||
722 (ofdmPhyErrRate < ATH9K_ANI_OFDM_TRIG_LOW_ABOVE_INI &&
723 aniState->ofdmNoiseImmunityLevel >=
724 ATH9K_ANI_OFDM_DEF_LEVEL))) {
725 ath9k_hw_ani_lower_immunity(ah); 442 ath9k_hw_ani_lower_immunity(ah);
726 aniState->ofdmsTurn = !aniState->ofdmsTurn; 443 aniState->ofdmsTurn = !aniState->ofdmsTurn;
727 } else if ((ofdmPhyErrRate > ah->config.ofdm_trig_high && 444 } else if (ofdmPhyErrRate > ah->config.ofdm_trig_high) {
728 aniState->ofdmNoiseImmunityLevel >=
729 ATH9K_ANI_OFDM_DEF_LEVEL) ||
730 (ofdmPhyErrRate >
731 ATH9K_ANI_OFDM_TRIG_HIGH_BELOW_INI &&
732 aniState->ofdmNoiseImmunityLevel <
733 ATH9K_ANI_OFDM_DEF_LEVEL)) {
734 ath9k_hw_ani_ofdm_err_trigger(ah); 445 ath9k_hw_ani_ofdm_err_trigger(ah);
735 aniState->ofdmsTurn = false; 446 aniState->ofdmsTurn = false;
736 } else if (cckPhyErrRate > ah->config.cck_trig_high) { 447 } else if (cckPhyErrRate > ah->config.cck_trig_high) {
@@ -778,49 +489,6 @@ void ath9k_hw_disable_mib_counters(struct ath_hw *ah)
778} 489}
779EXPORT_SYMBOL(ath9k_hw_disable_mib_counters); 490EXPORT_SYMBOL(ath9k_hw_disable_mib_counters);
780 491
781/*
782 * Process a MIB interrupt. We may potentially be invoked because
783 * any of the MIB counters overflow/trigger so don't assume we're
784 * here because a PHY error counter triggered.
785 */
786void ath9k_hw_proc_mib_event(struct ath_hw *ah)
787{
788 u32 phyCnt1, phyCnt2;
789
790 /* Reset these counters regardless */
791 REG_WRITE(ah, AR_FILT_OFDM, 0);
792 REG_WRITE(ah, AR_FILT_CCK, 0);
793 if (!(REG_READ(ah, AR_SLP_MIB_CTRL) & AR_SLP_MIB_PENDING))
794 REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR);
795
796 /* Clear the mib counters and save them in the stats */
797 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
798
799 if (!DO_ANI(ah)) {
800 /*
801 * We must always clear the interrupt cause by
802 * resetting the phy error regs.
803 */
804 REG_WRITE(ah, AR_PHY_ERR_1, 0);
805 REG_WRITE(ah, AR_PHY_ERR_2, 0);
806 return;
807 }
808
809 /* NB: these are not reset-on-read */
810 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
811 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
812 if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) ||
813 ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) {
814
815 if (!use_new_ani(ah))
816 ath9k_hw_ani_read_counters(ah);
817
818 /* NB: always restart to insure the h/w counters are reset */
819 ath9k_ani_restart(ah);
820 }
821}
822EXPORT_SYMBOL(ath9k_hw_proc_mib_event);
823
824void ath9k_hw_ani_setup(struct ath_hw *ah) 492void ath9k_hw_ani_setup(struct ath_hw *ah)
825{ 493{
826 int i; 494 int i;
@@ -845,66 +513,37 @@ void ath9k_hw_ani_init(struct ath_hw *ah)
845 513
846 ath_dbg(common, ANI, "Initialize ANI\n"); 514 ath_dbg(common, ANI, "Initialize ANI\n");
847 515
848 if (use_new_ani(ah)) { 516 ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH;
849 ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_NEW; 517 ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW;
850 ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW_NEW;
851 518
852 ah->config.cck_trig_high = ATH9K_ANI_CCK_TRIG_HIGH_NEW; 519 ah->config.cck_trig_high = ATH9K_ANI_CCK_TRIG_HIGH;
853 ah->config.cck_trig_low = ATH9K_ANI_CCK_TRIG_LOW_NEW; 520 ah->config.cck_trig_low = ATH9K_ANI_CCK_TRIG_LOW;
854 } else {
855 ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_OLD;
856 ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW_OLD;
857
858 ah->config.cck_trig_high = ATH9K_ANI_CCK_TRIG_HIGH_OLD;
859 ah->config.cck_trig_low = ATH9K_ANI_CCK_TRIG_LOW_OLD;
860 }
861 521
862 for (i = 0; i < ARRAY_SIZE(ah->channels); i++) { 522 for (i = 0; i < ARRAY_SIZE(ah->channels); i++) {
863 struct ath9k_channel *chan = &ah->channels[i]; 523 struct ath9k_channel *chan = &ah->channels[i];
864 struct ar5416AniState *ani = &chan->ani; 524 struct ar5416AniState *ani = &chan->ani;
865 525
866 if (use_new_ani(ah)) { 526 ani->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
867 ani->spurImmunityLevel =
868 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW;
869 527
870 ani->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW; 528 ani->firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
871 529
872 if (AR_SREV_9300_20_OR_LATER(ah)) 530 ani->mrcCCK = AR_SREV_9300_20_OR_LATER(ah) ? true : false;
873 ani->mrcCCKOff = 531
874 !ATH9K_ANI_ENABLE_MRC_CCK; 532 ani->ofdmsTurn = true;
875 else
876 ani->mrcCCKOff = true;
877
878 ani->ofdmsTurn = true;
879 } else {
880 ani->spurImmunityLevel =
881 ATH9K_ANI_SPUR_IMMUNE_LVL_OLD;
882 ani->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_OLD;
883
884 ani->cckWeakSigThreshold =
885 ATH9K_ANI_CCK_WEAK_SIG_THR;
886 }
887 533
888 ani->rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH; 534 ani->rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH;
889 ani->rssiThrLow = ATH9K_ANI_RSSI_THR_LOW; 535 ani->rssiThrLow = ATH9K_ANI_RSSI_THR_LOW;
890 ani->ofdmWeakSigDetectOff = 536 ani->ofdmWeakSigDetect = ATH9K_ANI_USE_OFDM_WEAK_SIG;
891 !ATH9K_ANI_USE_OFDM_WEAK_SIG;
892 ani->cckNoiseImmunityLevel = ATH9K_ANI_CCK_DEF_LEVEL; 537 ani->cckNoiseImmunityLevel = ATH9K_ANI_CCK_DEF_LEVEL;
893 ani->ofdmNoiseImmunityLevel = ATH9K_ANI_OFDM_DEF_LEVEL; 538 ani->ofdmNoiseImmunityLevel = ATH9K_ANI_OFDM_DEF_LEVEL;
894 ani->update_ani = false;
895 } 539 }
896 540
897 /* 541 /*
898 * since we expect some ongoing maintenance on the tables, let's sanity 542 * since we expect some ongoing maintenance on the tables, let's sanity
899 * check here default level should not modify INI setting. 543 * check here default level should not modify INI setting.
900 */ 544 */
901 if (use_new_ani(ah)) { 545 ah->aniperiod = ATH9K_ANI_PERIOD;
902 ah->aniperiod = ATH9K_ANI_PERIOD_NEW; 546 ah->config.ani_poll_interval = ATH9K_ANI_POLLINTERVAL;
903 ah->config.ani_poll_interval = ATH9K_ANI_POLLINTERVAL_NEW;
904 } else {
905 ah->aniperiod = ATH9K_ANI_PERIOD_OLD;
906 ah->config.ani_poll_interval = ATH9K_ANI_POLLINTERVAL_OLD;
907 }
908 547
909 if (ah->config.enable_ani) 548 if (ah->config.enable_ani)
910 ah->proc_phyerr |= HAL_PROCESS_ANI; 549 ah->proc_phyerr |= HAL_PROCESS_ANI;
diff --git a/drivers/net/wireless/ath/ath9k/ani.h b/drivers/net/wireless/ath/ath9k/ani.h
index 72e2b874e179..1485bf5e3518 100644
--- a/drivers/net/wireless/ath/ath9k/ani.h
+++ b/drivers/net/wireless/ath/ath9k/ani.h
@@ -24,42 +24,34 @@
24#define BEACON_RSSI(ahp) (ahp->stats.avgbrssi) 24#define BEACON_RSSI(ahp) (ahp->stats.avgbrssi)
25 25
26/* units are errors per second */ 26/* units are errors per second */
27#define ATH9K_ANI_OFDM_TRIG_HIGH_OLD 500 27#define ATH9K_ANI_OFDM_TRIG_HIGH 3500
28#define ATH9K_ANI_OFDM_TRIG_HIGH_NEW 3500
29#define ATH9K_ANI_OFDM_TRIG_HIGH_BELOW_INI 1000 28#define ATH9K_ANI_OFDM_TRIG_HIGH_BELOW_INI 1000
30 29
31/* units are errors per second */ 30/* units are errors per second */
32#define ATH9K_ANI_OFDM_TRIG_LOW_OLD 200 31#define ATH9K_ANI_OFDM_TRIG_LOW 400
33#define ATH9K_ANI_OFDM_TRIG_LOW_NEW 400
34#define ATH9K_ANI_OFDM_TRIG_LOW_ABOVE_INI 900 32#define ATH9K_ANI_OFDM_TRIG_LOW_ABOVE_INI 900
35 33
36/* units are errors per second */ 34/* units are errors per second */
37#define ATH9K_ANI_CCK_TRIG_HIGH_OLD 200 35#define ATH9K_ANI_CCK_TRIG_HIGH 600
38#define ATH9K_ANI_CCK_TRIG_HIGH_NEW 600
39 36
40/* units are errors per second */ 37/* units are errors per second */
41#define ATH9K_ANI_CCK_TRIG_LOW_OLD 100 38#define ATH9K_ANI_CCK_TRIG_LOW 300
42#define ATH9K_ANI_CCK_TRIG_LOW_NEW 300
43 39
44#define ATH9K_ANI_NOISE_IMMUNE_LVL 4 40#define ATH9K_ANI_NOISE_IMMUNE_LVL 4
45#define ATH9K_ANI_USE_OFDM_WEAK_SIG true 41#define ATH9K_ANI_USE_OFDM_WEAK_SIG true
46#define ATH9K_ANI_CCK_WEAK_SIG_THR false 42#define ATH9K_ANI_CCK_WEAK_SIG_THR false
47 43
48#define ATH9K_ANI_SPUR_IMMUNE_LVL_OLD 7 44#define ATH9K_ANI_SPUR_IMMUNE_LVL 3
49#define ATH9K_ANI_SPUR_IMMUNE_LVL_NEW 3
50 45
51#define ATH9K_ANI_FIRSTEP_LVL_OLD 0 46#define ATH9K_ANI_FIRSTEP_LVL 2
52#define ATH9K_ANI_FIRSTEP_LVL_NEW 2
53 47
54#define ATH9K_ANI_RSSI_THR_HIGH 40 48#define ATH9K_ANI_RSSI_THR_HIGH 40
55#define ATH9K_ANI_RSSI_THR_LOW 7 49#define ATH9K_ANI_RSSI_THR_LOW 7
56 50
57#define ATH9K_ANI_PERIOD_OLD 100 51#define ATH9K_ANI_PERIOD 300
58#define ATH9K_ANI_PERIOD_NEW 300
59 52
60/* in ms */ 53/* in ms */
61#define ATH9K_ANI_POLLINTERVAL_OLD 100 54#define ATH9K_ANI_POLLINTERVAL 1000
62#define ATH9K_ANI_POLLINTERVAL_NEW 1000
63 55
64#define HAL_NOISE_IMMUNE_MAX 4 56#define HAL_NOISE_IMMUNE_MAX 4
65#define HAL_SPUR_IMMUNE_MAX 7 57#define HAL_SPUR_IMMUNE_MAX 7
@@ -70,8 +62,6 @@
70#define ATH9K_SIG_SPUR_IMM_SETTING_MIN 0 62#define ATH9K_SIG_SPUR_IMM_SETTING_MIN 0
71#define ATH9K_SIG_SPUR_IMM_SETTING_MAX 22 63#define ATH9K_SIG_SPUR_IMM_SETTING_MAX 22
72 64
73#define ATH9K_ANI_ENABLE_MRC_CCK true
74
75/* values here are relative to the INI */ 65/* values here are relative to the INI */
76 66
77enum ath9k_ani_cmd { 67enum ath9k_ani_cmd {
@@ -119,16 +109,14 @@ struct ar5416AniState {
119 u8 ofdmNoiseImmunityLevel; 109 u8 ofdmNoiseImmunityLevel;
120 u8 cckNoiseImmunityLevel; 110 u8 cckNoiseImmunityLevel;
121 bool ofdmsTurn; 111 bool ofdmsTurn;
122 u8 mrcCCKOff; 112 u8 mrcCCK;
123 u8 spurImmunityLevel; 113 u8 spurImmunityLevel;
124 u8 firstepLevel; 114 u8 firstepLevel;
125 u8 ofdmWeakSigDetectOff; 115 u8 ofdmWeakSigDetect;
126 u8 cckWeakSigThreshold; 116 u8 cckWeakSigThreshold;
127 bool update_ani;
128 u32 listenTime; 117 u32 listenTime;
129 int32_t rssiThrLow; 118 int32_t rssiThrLow;
130 int32_t rssiThrHigh; 119 int32_t rssiThrHigh;
131 u32 noiseFloor;
132 u32 ofdmPhyErrCount; 120 u32 ofdmPhyErrCount;
133 u32 cckPhyErrCount; 121 u32 cckPhyErrCount;
134 int16_t pktRssi[2]; 122 int16_t pktRssi[2];
diff --git a/drivers/net/wireless/ath/ath9k/antenna.c b/drivers/net/wireless/ath/ath9k/antenna.c
new file mode 100644
index 000000000000..bbcfeb3b2a60
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/antenna.c
@@ -0,0 +1,776 @@
1/*
2 * Copyright (c) 2012 Qualcomm Atheros, Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "ath9k.h"
18
19static inline bool ath_is_alt_ant_ratio_better(int alt_ratio, int maxdelta,
20 int mindelta, int main_rssi_avg,
21 int alt_rssi_avg, int pkt_count)
22{
23 return (((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
24 (alt_rssi_avg > main_rssi_avg + maxdelta)) ||
25 (alt_rssi_avg > main_rssi_avg + mindelta)) && (pkt_count > 50);
26}
27
28static inline bool ath_ant_div_comb_alt_check(u8 div_group, int alt_ratio,
29 int curr_main_set, int curr_alt_set,
30 int alt_rssi_avg, int main_rssi_avg)
31{
32 bool result = false;
33 switch (div_group) {
34 case 0:
35 if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO)
36 result = true;
37 break;
38 case 1:
39 case 2:
40 if ((((curr_main_set == ATH_ANT_DIV_COMB_LNA2) &&
41 (curr_alt_set == ATH_ANT_DIV_COMB_LNA1) &&
42 (alt_rssi_avg >= (main_rssi_avg - 5))) ||
43 ((curr_main_set == ATH_ANT_DIV_COMB_LNA1) &&
44 (curr_alt_set == ATH_ANT_DIV_COMB_LNA2) &&
45 (alt_rssi_avg >= (main_rssi_avg - 2)))) &&
46 (alt_rssi_avg >= 4))
47 result = true;
48 else
49 result = false;
50 break;
51 }
52
53 return result;
54}
55
56static void ath_lnaconf_alt_good_scan(struct ath_ant_comb *antcomb,
57 struct ath_hw_antcomb_conf ant_conf,
58 int main_rssi_avg)
59{
60 antcomb->quick_scan_cnt = 0;
61
62 if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA2)
63 antcomb->rssi_lna2 = main_rssi_avg;
64 else if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA1)
65 antcomb->rssi_lna1 = main_rssi_avg;
66
67 switch ((ant_conf.main_lna_conf << 4) | ant_conf.alt_lna_conf) {
68 case 0x10: /* LNA2 A-B */
69 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
70 antcomb->first_quick_scan_conf =
71 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
72 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1;
73 break;
74 case 0x20: /* LNA1 A-B */
75 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
76 antcomb->first_quick_scan_conf =
77 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
78 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2;
79 break;
80 case 0x21: /* LNA1 LNA2 */
81 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA2;
82 antcomb->first_quick_scan_conf =
83 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
84 antcomb->second_quick_scan_conf =
85 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
86 break;
87 case 0x12: /* LNA2 LNA1 */
88 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1;
89 antcomb->first_quick_scan_conf =
90 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
91 antcomb->second_quick_scan_conf =
92 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
93 break;
94 case 0x13: /* LNA2 A+B */
95 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
96 antcomb->first_quick_scan_conf =
97 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
98 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1;
99 break;
100 case 0x23: /* LNA1 A+B */
101 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
102 antcomb->first_quick_scan_conf =
103 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
104 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2;
105 break;
106 default:
107 break;
108 }
109}
110
111static void ath_select_ant_div_from_quick_scan(struct ath_ant_comb *antcomb,
112 struct ath_hw_antcomb_conf *div_ant_conf,
113 int main_rssi_avg, int alt_rssi_avg,
114 int alt_ratio)
115{
116 /* alt_good */
117 switch (antcomb->quick_scan_cnt) {
118 case 0:
119 /* set alt to main, and alt to first conf */
120 div_ant_conf->main_lna_conf = antcomb->main_conf;
121 div_ant_conf->alt_lna_conf = antcomb->first_quick_scan_conf;
122 break;
123 case 1:
124 /* set alt to main, and alt to first conf */
125 div_ant_conf->main_lna_conf = antcomb->main_conf;
126 div_ant_conf->alt_lna_conf = antcomb->second_quick_scan_conf;
127 antcomb->rssi_first = main_rssi_avg;
128 antcomb->rssi_second = alt_rssi_avg;
129
130 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) {
131 /* main is LNA1 */
132 if (ath_is_alt_ant_ratio_better(alt_ratio,
133 ATH_ANT_DIV_COMB_LNA1_DELTA_HI,
134 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
135 main_rssi_avg, alt_rssi_avg,
136 antcomb->total_pkt_count))
137 antcomb->first_ratio = true;
138 else
139 antcomb->first_ratio = false;
140 } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) {
141 if (ath_is_alt_ant_ratio_better(alt_ratio,
142 ATH_ANT_DIV_COMB_LNA1_DELTA_MID,
143 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
144 main_rssi_avg, alt_rssi_avg,
145 antcomb->total_pkt_count))
146 antcomb->first_ratio = true;
147 else
148 antcomb->first_ratio = false;
149 } else {
150 if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
151 (alt_rssi_avg > main_rssi_avg +
152 ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) ||
153 (alt_rssi_avg > main_rssi_avg)) &&
154 (antcomb->total_pkt_count > 50))
155 antcomb->first_ratio = true;
156 else
157 antcomb->first_ratio = false;
158 }
159 break;
160 case 2:
161 antcomb->alt_good = false;
162 antcomb->scan_not_start = false;
163 antcomb->scan = false;
164 antcomb->rssi_first = main_rssi_avg;
165 antcomb->rssi_third = alt_rssi_avg;
166
167 if (antcomb->second_quick_scan_conf == ATH_ANT_DIV_COMB_LNA1)
168 antcomb->rssi_lna1 = alt_rssi_avg;
169 else if (antcomb->second_quick_scan_conf ==
170 ATH_ANT_DIV_COMB_LNA2)
171 antcomb->rssi_lna2 = alt_rssi_avg;
172 else if (antcomb->second_quick_scan_conf ==
173 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2) {
174 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2)
175 antcomb->rssi_lna2 = main_rssi_avg;
176 else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1)
177 antcomb->rssi_lna1 = main_rssi_avg;
178 }
179
180 if (antcomb->rssi_lna2 > antcomb->rssi_lna1 +
181 ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA)
182 div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA2;
183 else
184 div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA1;
185
186 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) {
187 if (ath_is_alt_ant_ratio_better(alt_ratio,
188 ATH_ANT_DIV_COMB_LNA1_DELTA_HI,
189 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
190 main_rssi_avg, alt_rssi_avg,
191 antcomb->total_pkt_count))
192 antcomb->second_ratio = true;
193 else
194 antcomb->second_ratio = false;
195 } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) {
196 if (ath_is_alt_ant_ratio_better(alt_ratio,
197 ATH_ANT_DIV_COMB_LNA1_DELTA_MID,
198 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
199 main_rssi_avg, alt_rssi_avg,
200 antcomb->total_pkt_count))
201 antcomb->second_ratio = true;
202 else
203 antcomb->second_ratio = false;
204 } else {
205 if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
206 (alt_rssi_avg > main_rssi_avg +
207 ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) ||
208 (alt_rssi_avg > main_rssi_avg)) &&
209 (antcomb->total_pkt_count > 50))
210 antcomb->second_ratio = true;
211 else
212 antcomb->second_ratio = false;
213 }
214
215 /* set alt to the conf with maximun ratio */
216 if (antcomb->first_ratio && antcomb->second_ratio) {
217 if (antcomb->rssi_second > antcomb->rssi_third) {
218 /* first alt*/
219 if ((antcomb->first_quick_scan_conf ==
220 ATH_ANT_DIV_COMB_LNA1) ||
221 (antcomb->first_quick_scan_conf ==
222 ATH_ANT_DIV_COMB_LNA2))
223 /* Set alt LNA1 or LNA2*/
224 if (div_ant_conf->main_lna_conf ==
225 ATH_ANT_DIV_COMB_LNA2)
226 div_ant_conf->alt_lna_conf =
227 ATH_ANT_DIV_COMB_LNA1;
228 else
229 div_ant_conf->alt_lna_conf =
230 ATH_ANT_DIV_COMB_LNA2;
231 else
232 /* Set alt to A+B or A-B */
233 div_ant_conf->alt_lna_conf =
234 antcomb->first_quick_scan_conf;
235 } else if ((antcomb->second_quick_scan_conf ==
236 ATH_ANT_DIV_COMB_LNA1) ||
237 (antcomb->second_quick_scan_conf ==
238 ATH_ANT_DIV_COMB_LNA2)) {
239 /* Set alt LNA1 or LNA2 */
240 if (div_ant_conf->main_lna_conf ==
241 ATH_ANT_DIV_COMB_LNA2)
242 div_ant_conf->alt_lna_conf =
243 ATH_ANT_DIV_COMB_LNA1;
244 else
245 div_ant_conf->alt_lna_conf =
246 ATH_ANT_DIV_COMB_LNA2;
247 } else {
248 /* Set alt to A+B or A-B */
249 div_ant_conf->alt_lna_conf =
250 antcomb->second_quick_scan_conf;
251 }
252 } else if (antcomb->first_ratio) {
253 /* first alt */
254 if ((antcomb->first_quick_scan_conf ==
255 ATH_ANT_DIV_COMB_LNA1) ||
256 (antcomb->first_quick_scan_conf ==
257 ATH_ANT_DIV_COMB_LNA2))
258 /* Set alt LNA1 or LNA2 */
259 if (div_ant_conf->main_lna_conf ==
260 ATH_ANT_DIV_COMB_LNA2)
261 div_ant_conf->alt_lna_conf =
262 ATH_ANT_DIV_COMB_LNA1;
263 else
264 div_ant_conf->alt_lna_conf =
265 ATH_ANT_DIV_COMB_LNA2;
266 else
267 /* Set alt to A+B or A-B */
268 div_ant_conf->alt_lna_conf =
269 antcomb->first_quick_scan_conf;
270 } else if (antcomb->second_ratio) {
271 /* second alt */
272 if ((antcomb->second_quick_scan_conf ==
273 ATH_ANT_DIV_COMB_LNA1) ||
274 (antcomb->second_quick_scan_conf ==
275 ATH_ANT_DIV_COMB_LNA2))
276 /* Set alt LNA1 or LNA2 */
277 if (div_ant_conf->main_lna_conf ==
278 ATH_ANT_DIV_COMB_LNA2)
279 div_ant_conf->alt_lna_conf =
280 ATH_ANT_DIV_COMB_LNA1;
281 else
282 div_ant_conf->alt_lna_conf =
283 ATH_ANT_DIV_COMB_LNA2;
284 else
285 /* Set alt to A+B or A-B */
286 div_ant_conf->alt_lna_conf =
287 antcomb->second_quick_scan_conf;
288 } else {
289 /* main is largest */
290 if ((antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) ||
291 (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2))
292 /* Set alt LNA1 or LNA2 */
293 if (div_ant_conf->main_lna_conf ==
294 ATH_ANT_DIV_COMB_LNA2)
295 div_ant_conf->alt_lna_conf =
296 ATH_ANT_DIV_COMB_LNA1;
297 else
298 div_ant_conf->alt_lna_conf =
299 ATH_ANT_DIV_COMB_LNA2;
300 else
301 /* Set alt to A+B or A-B */
302 div_ant_conf->alt_lna_conf = antcomb->main_conf;
303 }
304 break;
305 default:
306 break;
307 }
308}
309
310static void ath_ant_div_conf_fast_divbias(struct ath_hw_antcomb_conf *ant_conf,
311 struct ath_ant_comb *antcomb,
312 int alt_ratio)
313{
314 if (ant_conf->div_group == 0) {
315 /* Adjust the fast_div_bias based on main and alt lna conf */
316 switch ((ant_conf->main_lna_conf << 4) |
317 ant_conf->alt_lna_conf) {
318 case 0x01: /* A-B LNA2 */
319 ant_conf->fast_div_bias = 0x3b;
320 break;
321 case 0x02: /* A-B LNA1 */
322 ant_conf->fast_div_bias = 0x3d;
323 break;
324 case 0x03: /* A-B A+B */
325 ant_conf->fast_div_bias = 0x1;
326 break;
327 case 0x10: /* LNA2 A-B */
328 ant_conf->fast_div_bias = 0x7;
329 break;
330 case 0x12: /* LNA2 LNA1 */
331 ant_conf->fast_div_bias = 0x2;
332 break;
333 case 0x13: /* LNA2 A+B */
334 ant_conf->fast_div_bias = 0x7;
335 break;
336 case 0x20: /* LNA1 A-B */
337 ant_conf->fast_div_bias = 0x6;
338 break;
339 case 0x21: /* LNA1 LNA2 */
340 ant_conf->fast_div_bias = 0x0;
341 break;
342 case 0x23: /* LNA1 A+B */
343 ant_conf->fast_div_bias = 0x6;
344 break;
345 case 0x30: /* A+B A-B */
346 ant_conf->fast_div_bias = 0x1;
347 break;
348 case 0x31: /* A+B LNA2 */
349 ant_conf->fast_div_bias = 0x3b;
350 break;
351 case 0x32: /* A+B LNA1 */
352 ant_conf->fast_div_bias = 0x3d;
353 break;
354 default:
355 break;
356 }
357 } else if (ant_conf->div_group == 1) {
358 /* Adjust the fast_div_bias based on main and alt_lna_conf */
359 switch ((ant_conf->main_lna_conf << 4) |
360 ant_conf->alt_lna_conf) {
361 case 0x01: /* A-B LNA2 */
362 ant_conf->fast_div_bias = 0x1;
363 ant_conf->main_gaintb = 0;
364 ant_conf->alt_gaintb = 0;
365 break;
366 case 0x02: /* A-B LNA1 */
367 ant_conf->fast_div_bias = 0x1;
368 ant_conf->main_gaintb = 0;
369 ant_conf->alt_gaintb = 0;
370 break;
371 case 0x03: /* A-B A+B */
372 ant_conf->fast_div_bias = 0x1;
373 ant_conf->main_gaintb = 0;
374 ant_conf->alt_gaintb = 0;
375 break;
376 case 0x10: /* LNA2 A-B */
377 if (!(antcomb->scan) &&
378 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
379 ant_conf->fast_div_bias = 0x3f;
380 else
381 ant_conf->fast_div_bias = 0x1;
382 ant_conf->main_gaintb = 0;
383 ant_conf->alt_gaintb = 0;
384 break;
385 case 0x12: /* LNA2 LNA1 */
386 ant_conf->fast_div_bias = 0x1;
387 ant_conf->main_gaintb = 0;
388 ant_conf->alt_gaintb = 0;
389 break;
390 case 0x13: /* LNA2 A+B */
391 if (!(antcomb->scan) &&
392 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
393 ant_conf->fast_div_bias = 0x3f;
394 else
395 ant_conf->fast_div_bias = 0x1;
396 ant_conf->main_gaintb = 0;
397 ant_conf->alt_gaintb = 0;
398 break;
399 case 0x20: /* LNA1 A-B */
400 if (!(antcomb->scan) &&
401 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
402 ant_conf->fast_div_bias = 0x3f;
403 else
404 ant_conf->fast_div_bias = 0x1;
405 ant_conf->main_gaintb = 0;
406 ant_conf->alt_gaintb = 0;
407 break;
408 case 0x21: /* LNA1 LNA2 */
409 ant_conf->fast_div_bias = 0x1;
410 ant_conf->main_gaintb = 0;
411 ant_conf->alt_gaintb = 0;
412 break;
413 case 0x23: /* LNA1 A+B */
414 if (!(antcomb->scan) &&
415 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
416 ant_conf->fast_div_bias = 0x3f;
417 else
418 ant_conf->fast_div_bias = 0x1;
419 ant_conf->main_gaintb = 0;
420 ant_conf->alt_gaintb = 0;
421 break;
422 case 0x30: /* A+B A-B */
423 ant_conf->fast_div_bias = 0x1;
424 ant_conf->main_gaintb = 0;
425 ant_conf->alt_gaintb = 0;
426 break;
427 case 0x31: /* A+B LNA2 */
428 ant_conf->fast_div_bias = 0x1;
429 ant_conf->main_gaintb = 0;
430 ant_conf->alt_gaintb = 0;
431 break;
432 case 0x32: /* A+B LNA1 */
433 ant_conf->fast_div_bias = 0x1;
434 ant_conf->main_gaintb = 0;
435 ant_conf->alt_gaintb = 0;
436 break;
437 default:
438 break;
439 }
440 } else if (ant_conf->div_group == 2) {
441 /* Adjust the fast_div_bias based on main and alt_lna_conf */
442 switch ((ant_conf->main_lna_conf << 4) |
443 ant_conf->alt_lna_conf) {
444 case 0x01: /* A-B LNA2 */
445 ant_conf->fast_div_bias = 0x1;
446 ant_conf->main_gaintb = 0;
447 ant_conf->alt_gaintb = 0;
448 break;
449 case 0x02: /* A-B LNA1 */
450 ant_conf->fast_div_bias = 0x1;
451 ant_conf->main_gaintb = 0;
452 ant_conf->alt_gaintb = 0;
453 break;
454 case 0x03: /* A-B A+B */
455 ant_conf->fast_div_bias = 0x1;
456 ant_conf->main_gaintb = 0;
457 ant_conf->alt_gaintb = 0;
458 break;
459 case 0x10: /* LNA2 A-B */
460 if (!(antcomb->scan) &&
461 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
462 ant_conf->fast_div_bias = 0x1;
463 else
464 ant_conf->fast_div_bias = 0x2;
465 ant_conf->main_gaintb = 0;
466 ant_conf->alt_gaintb = 0;
467 break;
468 case 0x12: /* LNA2 LNA1 */
469 ant_conf->fast_div_bias = 0x1;
470 ant_conf->main_gaintb = 0;
471 ant_conf->alt_gaintb = 0;
472 break;
473 case 0x13: /* LNA2 A+B */
474 if (!(antcomb->scan) &&
475 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
476 ant_conf->fast_div_bias = 0x1;
477 else
478 ant_conf->fast_div_bias = 0x2;
479 ant_conf->main_gaintb = 0;
480 ant_conf->alt_gaintb = 0;
481 break;
482 case 0x20: /* LNA1 A-B */
483 if (!(antcomb->scan) &&
484 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
485 ant_conf->fast_div_bias = 0x1;
486 else
487 ant_conf->fast_div_bias = 0x2;
488 ant_conf->main_gaintb = 0;
489 ant_conf->alt_gaintb = 0;
490 break;
491 case 0x21: /* LNA1 LNA2 */
492 ant_conf->fast_div_bias = 0x1;
493 ant_conf->main_gaintb = 0;
494 ant_conf->alt_gaintb = 0;
495 break;
496 case 0x23: /* LNA1 A+B */
497 if (!(antcomb->scan) &&
498 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
499 ant_conf->fast_div_bias = 0x1;
500 else
501 ant_conf->fast_div_bias = 0x2;
502 ant_conf->main_gaintb = 0;
503 ant_conf->alt_gaintb = 0;
504 break;
505 case 0x30: /* A+B A-B */
506 ant_conf->fast_div_bias = 0x1;
507 ant_conf->main_gaintb = 0;
508 ant_conf->alt_gaintb = 0;
509 break;
510 case 0x31: /* A+B LNA2 */
511 ant_conf->fast_div_bias = 0x1;
512 ant_conf->main_gaintb = 0;
513 ant_conf->alt_gaintb = 0;
514 break;
515 case 0x32: /* A+B LNA1 */
516 ant_conf->fast_div_bias = 0x1;
517 ant_conf->main_gaintb = 0;
518 ant_conf->alt_gaintb = 0;
519 break;
520 default:
521 break;
522 }
523 }
524}
525
526void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs)
527{
528 struct ath_hw_antcomb_conf div_ant_conf;
529 struct ath_ant_comb *antcomb = &sc->ant_comb;
530 int alt_ratio = 0, alt_rssi_avg = 0, main_rssi_avg = 0, curr_alt_set;
531 int curr_main_set;
532 int main_rssi = rs->rs_rssi_ctl0;
533 int alt_rssi = rs->rs_rssi_ctl1;
534 int rx_ant_conf, main_ant_conf;
535 bool short_scan = false;
536
537 rx_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_CURRENT_SHIFT) &
538 ATH_ANT_RX_MASK;
539 main_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_MAIN_SHIFT) &
540 ATH_ANT_RX_MASK;
541
542 /* Record packet only when both main_rssi and alt_rssi is positive */
543 if (main_rssi > 0 && alt_rssi > 0) {
544 antcomb->total_pkt_count++;
545 antcomb->main_total_rssi += main_rssi;
546 antcomb->alt_total_rssi += alt_rssi;
547 if (main_ant_conf == rx_ant_conf)
548 antcomb->main_recv_cnt++;
549 else
550 antcomb->alt_recv_cnt++;
551 }
552
553 /* Short scan check */
554 if (antcomb->scan && antcomb->alt_good) {
555 if (time_after(jiffies, antcomb->scan_start_time +
556 msecs_to_jiffies(ATH_ANT_DIV_COMB_SHORT_SCAN_INTR)))
557 short_scan = true;
558 else
559 if (antcomb->total_pkt_count ==
560 ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT) {
561 alt_ratio = ((antcomb->alt_recv_cnt * 100) /
562 antcomb->total_pkt_count);
563 if (alt_ratio < ATH_ANT_DIV_COMB_ALT_ANT_RATIO)
564 short_scan = true;
565 }
566 }
567
568 if (((antcomb->total_pkt_count < ATH_ANT_DIV_COMB_MAX_PKTCOUNT) ||
569 rs->rs_moreaggr) && !short_scan)
570 return;
571
572 if (antcomb->total_pkt_count) {
573 alt_ratio = ((antcomb->alt_recv_cnt * 100) /
574 antcomb->total_pkt_count);
575 main_rssi_avg = (antcomb->main_total_rssi /
576 antcomb->total_pkt_count);
577 alt_rssi_avg = (antcomb->alt_total_rssi /
578 antcomb->total_pkt_count);
579 }
580
581
582 ath9k_hw_antdiv_comb_conf_get(sc->sc_ah, &div_ant_conf);
583 curr_alt_set = div_ant_conf.alt_lna_conf;
584 curr_main_set = div_ant_conf.main_lna_conf;
585
586 antcomb->count++;
587
588 if (antcomb->count == ATH_ANT_DIV_COMB_MAX_COUNT) {
589 if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO) {
590 ath_lnaconf_alt_good_scan(antcomb, div_ant_conf,
591 main_rssi_avg);
592 antcomb->alt_good = true;
593 } else {
594 antcomb->alt_good = false;
595 }
596
597 antcomb->count = 0;
598 antcomb->scan = true;
599 antcomb->scan_not_start = true;
600 }
601
602 if (!antcomb->scan) {
603 if (ath_ant_div_comb_alt_check(div_ant_conf.div_group,
604 alt_ratio, curr_main_set, curr_alt_set,
605 alt_rssi_avg, main_rssi_avg)) {
606 if (curr_alt_set == ATH_ANT_DIV_COMB_LNA2) {
607 /* Switch main and alt LNA */
608 div_ant_conf.main_lna_conf =
609 ATH_ANT_DIV_COMB_LNA2;
610 div_ant_conf.alt_lna_conf =
611 ATH_ANT_DIV_COMB_LNA1;
612 } else if (curr_alt_set == ATH_ANT_DIV_COMB_LNA1) {
613 div_ant_conf.main_lna_conf =
614 ATH_ANT_DIV_COMB_LNA1;
615 div_ant_conf.alt_lna_conf =
616 ATH_ANT_DIV_COMB_LNA2;
617 }
618
619 goto div_comb_done;
620 } else if ((curr_alt_set != ATH_ANT_DIV_COMB_LNA1) &&
621 (curr_alt_set != ATH_ANT_DIV_COMB_LNA2)) {
622 /* Set alt to another LNA */
623 if (curr_main_set == ATH_ANT_DIV_COMB_LNA2)
624 div_ant_conf.alt_lna_conf =
625 ATH_ANT_DIV_COMB_LNA1;
626 else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1)
627 div_ant_conf.alt_lna_conf =
628 ATH_ANT_DIV_COMB_LNA2;
629
630 goto div_comb_done;
631 }
632
633 if ((alt_rssi_avg < (main_rssi_avg +
634 div_ant_conf.lna1_lna2_delta)))
635 goto div_comb_done;
636 }
637
638 if (!antcomb->scan_not_start) {
639 switch (curr_alt_set) {
640 case ATH_ANT_DIV_COMB_LNA2:
641 antcomb->rssi_lna2 = alt_rssi_avg;
642 antcomb->rssi_lna1 = main_rssi_avg;
643 antcomb->scan = true;
644 /* set to A+B */
645 div_ant_conf.main_lna_conf =
646 ATH_ANT_DIV_COMB_LNA1;
647 div_ant_conf.alt_lna_conf =
648 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
649 break;
650 case ATH_ANT_DIV_COMB_LNA1:
651 antcomb->rssi_lna1 = alt_rssi_avg;
652 antcomb->rssi_lna2 = main_rssi_avg;
653 antcomb->scan = true;
654 /* set to A+B */
655 div_ant_conf.main_lna_conf = ATH_ANT_DIV_COMB_LNA2;
656 div_ant_conf.alt_lna_conf =
657 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
658 break;
659 case ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2:
660 antcomb->rssi_add = alt_rssi_avg;
661 antcomb->scan = true;
662 /* set to A-B */
663 div_ant_conf.alt_lna_conf =
664 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
665 break;
666 case ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2:
667 antcomb->rssi_sub = alt_rssi_avg;
668 antcomb->scan = false;
669 if (antcomb->rssi_lna2 >
670 (antcomb->rssi_lna1 +
671 ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA)) {
672 /* use LNA2 as main LNA */
673 if ((antcomb->rssi_add > antcomb->rssi_lna1) &&
674 (antcomb->rssi_add > antcomb->rssi_sub)) {
675 /* set to A+B */
676 div_ant_conf.main_lna_conf =
677 ATH_ANT_DIV_COMB_LNA2;
678 div_ant_conf.alt_lna_conf =
679 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
680 } else if (antcomb->rssi_sub >
681 antcomb->rssi_lna1) {
682 /* set to A-B */
683 div_ant_conf.main_lna_conf =
684 ATH_ANT_DIV_COMB_LNA2;
685 div_ant_conf.alt_lna_conf =
686 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
687 } else {
688 /* set to LNA1 */
689 div_ant_conf.main_lna_conf =
690 ATH_ANT_DIV_COMB_LNA2;
691 div_ant_conf.alt_lna_conf =
692 ATH_ANT_DIV_COMB_LNA1;
693 }
694 } else {
695 /* use LNA1 as main LNA */
696 if ((antcomb->rssi_add > antcomb->rssi_lna2) &&
697 (antcomb->rssi_add > antcomb->rssi_sub)) {
698 /* set to A+B */
699 div_ant_conf.main_lna_conf =
700 ATH_ANT_DIV_COMB_LNA1;
701 div_ant_conf.alt_lna_conf =
702 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
703 } else if (antcomb->rssi_sub >
704 antcomb->rssi_lna1) {
705 /* set to A-B */
706 div_ant_conf.main_lna_conf =
707 ATH_ANT_DIV_COMB_LNA1;
708 div_ant_conf.alt_lna_conf =
709 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
710 } else {
711 /* set to LNA2 */
712 div_ant_conf.main_lna_conf =
713 ATH_ANT_DIV_COMB_LNA1;
714 div_ant_conf.alt_lna_conf =
715 ATH_ANT_DIV_COMB_LNA2;
716 }
717 }
718 break;
719 default:
720 break;
721 }
722 } else {
723 if (!antcomb->alt_good) {
724 antcomb->scan_not_start = false;
725 /* Set alt to another LNA */
726 if (curr_main_set == ATH_ANT_DIV_COMB_LNA2) {
727 div_ant_conf.main_lna_conf =
728 ATH_ANT_DIV_COMB_LNA2;
729 div_ant_conf.alt_lna_conf =
730 ATH_ANT_DIV_COMB_LNA1;
731 } else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1) {
732 div_ant_conf.main_lna_conf =
733 ATH_ANT_DIV_COMB_LNA1;
734 div_ant_conf.alt_lna_conf =
735 ATH_ANT_DIV_COMB_LNA2;
736 }
737 goto div_comb_done;
738 }
739 }
740
741 ath_select_ant_div_from_quick_scan(antcomb, &div_ant_conf,
742 main_rssi_avg, alt_rssi_avg,
743 alt_ratio);
744
745 antcomb->quick_scan_cnt++;
746
747div_comb_done:
748 ath_ant_div_conf_fast_divbias(&div_ant_conf, antcomb, alt_ratio);
749 ath9k_hw_antdiv_comb_conf_set(sc->sc_ah, &div_ant_conf);
750
751 antcomb->scan_start_time = jiffies;
752 antcomb->total_pkt_count = 0;
753 antcomb->main_total_rssi = 0;
754 antcomb->alt_total_rssi = 0;
755 antcomb->main_recv_cnt = 0;
756 antcomb->alt_recv_cnt = 0;
757}
758
759void ath_ant_comb_update(struct ath_softc *sc)
760{
761 struct ath_hw *ah = sc->sc_ah;
762 struct ath_hw_antcomb_conf div_ant_conf;
763 u8 lna_conf;
764
765 ath9k_hw_antdiv_comb_conf_get(ah, &div_ant_conf);
766
767 if (sc->ant_rx == 1)
768 lna_conf = ATH_ANT_DIV_COMB_LNA1;
769 else
770 lna_conf = ATH_ANT_DIV_COMB_LNA2;
771
772 div_ant_conf.main_lna_conf = lna_conf;
773 div_ant_conf.alt_lna_conf = lna_conf;
774
775 ath9k_hw_antdiv_comb_conf_set(ah, &div_ant_conf);
776}
diff --git a/drivers/net/wireless/ath/ath9k/ar5008_phy.c b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
index c7492c6a2519..874186bfda41 100644
--- a/drivers/net/wireless/ath/ath9k/ar5008_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
@@ -995,141 +995,6 @@ static u32 ar5008_hw_compute_pll_control(struct ath_hw *ah,
995 return pll; 995 return pll;
996} 996}
997 997
998static bool ar5008_hw_ani_control_old(struct ath_hw *ah,
999 enum ath9k_ani_cmd cmd,
1000 int param)
1001{
1002 struct ar5416AniState *aniState = &ah->curchan->ani;
1003 struct ath_common *common = ath9k_hw_common(ah);
1004
1005 switch (cmd & ah->ani_function) {
1006 case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
1007 u32 level = param;
1008
1009 if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
1010 ath_dbg(common, ANI, "level out of range (%u > %zu)\n",
1011 level, ARRAY_SIZE(ah->totalSizeDesired));
1012 return false;
1013 }
1014
1015 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
1016 AR_PHY_DESIRED_SZ_TOT_DES,
1017 ah->totalSizeDesired[level]);
1018 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
1019 AR_PHY_AGC_CTL1_COARSE_LOW,
1020 ah->coarse_low[level]);
1021 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
1022 AR_PHY_AGC_CTL1_COARSE_HIGH,
1023 ah->coarse_high[level]);
1024 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1025 AR_PHY_FIND_SIG_FIRPWR,
1026 ah->firpwr[level]);
1027
1028 if (level > aniState->noiseImmunityLevel)
1029 ah->stats.ast_ani_niup++;
1030 else if (level < aniState->noiseImmunityLevel)
1031 ah->stats.ast_ani_nidown++;
1032 aniState->noiseImmunityLevel = level;
1033 break;
1034 }
1035 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
1036 u32 on = param ? 1 : 0;
1037
1038 if (on)
1039 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
1040 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1041 else
1042 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
1043 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1044
1045 if (!on != aniState->ofdmWeakSigDetectOff) {
1046 if (on)
1047 ah->stats.ast_ani_ofdmon++;
1048 else
1049 ah->stats.ast_ani_ofdmoff++;
1050 aniState->ofdmWeakSigDetectOff = !on;
1051 }
1052 break;
1053 }
1054 case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
1055 static const int weakSigThrCck[] = { 8, 6 };
1056 u32 high = param ? 1 : 0;
1057
1058 REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
1059 AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
1060 weakSigThrCck[high]);
1061 if (high != aniState->cckWeakSigThreshold) {
1062 if (high)
1063 ah->stats.ast_ani_cckhigh++;
1064 else
1065 ah->stats.ast_ani_ccklow++;
1066 aniState->cckWeakSigThreshold = high;
1067 }
1068 break;
1069 }
1070 case ATH9K_ANI_FIRSTEP_LEVEL:{
1071 static const int firstep[] = { 0, 4, 8 };
1072 u32 level = param;
1073
1074 if (level >= ARRAY_SIZE(firstep)) {
1075 ath_dbg(common, ANI, "level out of range (%u > %zu)\n",
1076 level, ARRAY_SIZE(firstep));
1077 return false;
1078 }
1079 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1080 AR_PHY_FIND_SIG_FIRSTEP,
1081 firstep[level]);
1082 if (level > aniState->firstepLevel)
1083 ah->stats.ast_ani_stepup++;
1084 else if (level < aniState->firstepLevel)
1085 ah->stats.ast_ani_stepdown++;
1086 aniState->firstepLevel = level;
1087 break;
1088 }
1089 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
1090 static const int cycpwrThr1[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
1091 u32 level = param;
1092
1093 if (level >= ARRAY_SIZE(cycpwrThr1)) {
1094 ath_dbg(common, ANI, "level out of range (%u > %zu)\n",
1095 level, ARRAY_SIZE(cycpwrThr1));
1096 return false;
1097 }
1098 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1099 AR_PHY_TIMING5_CYCPWR_THR1,
1100 cycpwrThr1[level]);
1101 if (level > aniState->spurImmunityLevel)
1102 ah->stats.ast_ani_spurup++;
1103 else if (level < aniState->spurImmunityLevel)
1104 ah->stats.ast_ani_spurdown++;
1105 aniState->spurImmunityLevel = level;
1106 break;
1107 }
1108 case ATH9K_ANI_PRESENT:
1109 break;
1110 default:
1111 ath_dbg(common, ANI, "invalid cmd %u\n", cmd);
1112 return false;
1113 }
1114
1115 ath_dbg(common, ANI, "ANI parameters:\n");
1116 ath_dbg(common, ANI,
1117 "noiseImmunityLevel=%d, spurImmunityLevel=%d, ofdmWeakSigDetectOff=%d\n",
1118 aniState->noiseImmunityLevel,
1119 aniState->spurImmunityLevel,
1120 !aniState->ofdmWeakSigDetectOff);
1121 ath_dbg(common, ANI,
1122 "cckWeakSigThreshold=%d, firstepLevel=%d, listenTime=%d\n",
1123 aniState->cckWeakSigThreshold,
1124 aniState->firstepLevel,
1125 aniState->listenTime);
1126 ath_dbg(common, ANI, "ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
1127 aniState->ofdmPhyErrCount,
1128 aniState->cckPhyErrCount);
1129
1130 return true;
1131}
1132
1133static bool ar5008_hw_ani_control_new(struct ath_hw *ah, 998static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
1134 enum ath9k_ani_cmd cmd, 999 enum ath9k_ani_cmd cmd,
1135 int param) 1000 int param)
@@ -1206,18 +1071,18 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
1206 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, 1071 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
1207 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 1072 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1208 1073
1209 if (!on != aniState->ofdmWeakSigDetectOff) { 1074 if (on != aniState->ofdmWeakSigDetect) {
1210 ath_dbg(common, ANI, 1075 ath_dbg(common, ANI,
1211 "** ch %d: ofdm weak signal: %s=>%s\n", 1076 "** ch %d: ofdm weak signal: %s=>%s\n",
1212 chan->channel, 1077 chan->channel,
1213 !aniState->ofdmWeakSigDetectOff ? 1078 aniState->ofdmWeakSigDetect ?
1214 "on" : "off", 1079 "on" : "off",
1215 on ? "on" : "off"); 1080 on ? "on" : "off");
1216 if (on) 1081 if (on)
1217 ah->stats.ast_ani_ofdmon++; 1082 ah->stats.ast_ani_ofdmon++;
1218 else 1083 else
1219 ah->stats.ast_ani_ofdmoff++; 1084 ah->stats.ast_ani_ofdmoff++;
1220 aniState->ofdmWeakSigDetectOff = !on; 1085 aniState->ofdmWeakSigDetect = on;
1221 } 1086 }
1222 break; 1087 break;
1223 } 1088 }
@@ -1236,7 +1101,7 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
1236 * from INI file & cap value 1101 * from INI file & cap value
1237 */ 1102 */
1238 value = firstep_table[level] - 1103 value = firstep_table[level] -
1239 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] + 1104 firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
1240 aniState->iniDef.firstep; 1105 aniState->iniDef.firstep;
1241 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN) 1106 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1242 value = ATH9K_SIG_FIRSTEP_SETTING_MIN; 1107 value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
@@ -1251,7 +1116,7 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
1251 * from INI file & cap value 1116 * from INI file & cap value
1252 */ 1117 */
1253 value2 = firstep_table[level] - 1118 value2 = firstep_table[level] -
1254 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] + 1119 firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
1255 aniState->iniDef.firstepLow; 1120 aniState->iniDef.firstepLow;
1256 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN) 1121 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1257 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN; 1122 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
@@ -1267,7 +1132,7 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
1267 chan->channel, 1132 chan->channel,
1268 aniState->firstepLevel, 1133 aniState->firstepLevel,
1269 level, 1134 level,
1270 ATH9K_ANI_FIRSTEP_LVL_NEW, 1135 ATH9K_ANI_FIRSTEP_LVL,
1271 value, 1136 value,
1272 aniState->iniDef.firstep); 1137 aniState->iniDef.firstep);
1273 ath_dbg(common, ANI, 1138 ath_dbg(common, ANI,
@@ -1275,7 +1140,7 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
1275 chan->channel, 1140 chan->channel,
1276 aniState->firstepLevel, 1141 aniState->firstepLevel,
1277 level, 1142 level,
1278 ATH9K_ANI_FIRSTEP_LVL_NEW, 1143 ATH9K_ANI_FIRSTEP_LVL,
1279 value2, 1144 value2,
1280 aniState->iniDef.firstepLow); 1145 aniState->iniDef.firstepLow);
1281 if (level > aniState->firstepLevel) 1146 if (level > aniState->firstepLevel)
@@ -1300,7 +1165,7 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
1300 * from INI file & cap value 1165 * from INI file & cap value
1301 */ 1166 */
1302 value = cycpwrThr1_table[level] - 1167 value = cycpwrThr1_table[level] -
1303 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] + 1168 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
1304 aniState->iniDef.cycpwrThr1; 1169 aniState->iniDef.cycpwrThr1;
1305 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN) 1170 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1306 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN; 1171 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
@@ -1316,7 +1181,7 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
1316 * from INI file & cap value 1181 * from INI file & cap value
1317 */ 1182 */
1318 value2 = cycpwrThr1_table[level] - 1183 value2 = cycpwrThr1_table[level] -
1319 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] + 1184 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
1320 aniState->iniDef.cycpwrThr1Ext; 1185 aniState->iniDef.cycpwrThr1Ext;
1321 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN) 1186 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1322 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN; 1187 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
@@ -1331,7 +1196,7 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
1331 chan->channel, 1196 chan->channel,
1332 aniState->spurImmunityLevel, 1197 aniState->spurImmunityLevel,
1333 level, 1198 level,
1334 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW, 1199 ATH9K_ANI_SPUR_IMMUNE_LVL,
1335 value, 1200 value,
1336 aniState->iniDef.cycpwrThr1); 1201 aniState->iniDef.cycpwrThr1);
1337 ath_dbg(common, ANI, 1202 ath_dbg(common, ANI,
@@ -1339,7 +1204,7 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
1339 chan->channel, 1204 chan->channel,
1340 aniState->spurImmunityLevel, 1205 aniState->spurImmunityLevel,
1341 level, 1206 level,
1342 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW, 1207 ATH9K_ANI_SPUR_IMMUNE_LVL,
1343 value2, 1208 value2,
1344 aniState->iniDef.cycpwrThr1Ext); 1209 aniState->iniDef.cycpwrThr1Ext);
1345 if (level > aniState->spurImmunityLevel) 1210 if (level > aniState->spurImmunityLevel)
@@ -1367,9 +1232,9 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
1367 ath_dbg(common, ANI, 1232 ath_dbg(common, ANI,
1368 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n", 1233 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1369 aniState->spurImmunityLevel, 1234 aniState->spurImmunityLevel,
1370 !aniState->ofdmWeakSigDetectOff ? "on" : "off", 1235 aniState->ofdmWeakSigDetect ? "on" : "off",
1371 aniState->firstepLevel, 1236 aniState->firstepLevel,
1372 !aniState->mrcCCKOff ? "on" : "off", 1237 aniState->mrcCCK ? "on" : "off",
1373 aniState->listenTime, 1238 aniState->listenTime,
1374 aniState->ofdmPhyErrCount, 1239 aniState->ofdmPhyErrCount,
1375 aniState->cckPhyErrCount); 1240 aniState->cckPhyErrCount);
@@ -1454,10 +1319,10 @@ static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah)
1454 AR_PHY_EXT_TIMING5_CYCPWR_THR1); 1319 AR_PHY_EXT_TIMING5_CYCPWR_THR1);
1455 1320
1456 /* these levels just got reset to defaults by the INI */ 1321 /* these levels just got reset to defaults by the INI */
1457 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL_NEW; 1322 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
1458 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW; 1323 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
1459 aniState->ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG; 1324 aniState->ofdmWeakSigDetect = ATH9K_ANI_USE_OFDM_WEAK_SIG;
1460 aniState->mrcCCKOff = true; /* not available on pre AR9003 */ 1325 aniState->mrcCCK = false; /* not available on pre AR9003 */
1461} 1326}
1462 1327
1463static void ar5008_hw_set_nf_limits(struct ath_hw *ah) 1328static void ar5008_hw_set_nf_limits(struct ath_hw *ah)
@@ -1545,11 +1410,8 @@ void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
1545 priv_ops->do_getnf = ar5008_hw_do_getnf; 1410 priv_ops->do_getnf = ar5008_hw_do_getnf;
1546 priv_ops->set_radar_params = ar5008_hw_set_radar_params; 1411 priv_ops->set_radar_params = ar5008_hw_set_radar_params;
1547 1412
1548 if (modparam_force_new_ani) { 1413 priv_ops->ani_control = ar5008_hw_ani_control_new;
1549 priv_ops->ani_control = ar5008_hw_ani_control_new; 1414 priv_ops->ani_cache_ini_regs = ar5008_hw_ani_cache_ini_regs;
1550 priv_ops->ani_cache_ini_regs = ar5008_hw_ani_cache_ini_regs;
1551 } else
1552 priv_ops->ani_control = ar5008_hw_ani_control_old;
1553 1415
1554 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) 1416 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
1555 priv_ops->compute_pll_control = ar9160_hw_compute_pll_control; 1417 priv_ops->compute_pll_control = ar9160_hw_compute_pll_control;
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_hw.c b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
index d9a69fc470cd..edf21ea4fe93 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_hw.c
+++ b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
@@ -21,10 +21,6 @@
21#include "ar9002_initvals.h" 21#include "ar9002_initvals.h"
22#include "ar9002_phy.h" 22#include "ar9002_phy.h"
23 23
24int modparam_force_new_ani;
25module_param_named(force_new_ani, modparam_force_new_ani, int, 0444);
26MODULE_PARM_DESC(force_new_ani, "Force new ANI for AR5008, AR9001, AR9002");
27
28/* General hardware code for the A5008/AR9001/AR9002 hadware families */ 24/* General hardware code for the A5008/AR9001/AR9002 hadware families */
29 25
30static void ar9002_hw_init_mode_regs(struct ath_hw *ah) 26static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h b/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
index 952cb2b4656b..89bf94d4d8a1 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
@@ -1,5 +1,6 @@
1/* 1/*
2 * Copyright (c) 2010-2011 Atheros Communications Inc. 2 * Copyright (c) 2010-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2012 Qualcomm Atheros Inc.
3 * 4 *
4 * Permission to use, copy, modify, and/or distribute this software for any 5 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above 6 * purpose with or without fee is hereby granted, provided that the above
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_calib.c b/drivers/net/wireless/ath/ath9k/ar9003_calib.c
index 9fdd70fcaf5b..84b558d126ca 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_calib.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_calib.c
@@ -159,14 +159,11 @@ static bool ar9003_hw_calibrate(struct ath_hw *ah,
159 } 159 }
160 } 160 }
161 161
162 /* Do NF cal only at longer intervals */ 162 /*
163 if (longcal) { 163 * Do NF cal only at longer intervals. Get the value from
164 /* 164 * the previous NF cal and update history buffer.
165 * Get the value from the previous NF cal and update 165 */
166 * history buffer. 166 if (longcal && ath9k_hw_getnf(ah, chan)) {
167 */
168 ath9k_hw_getnf(ah, chan);
169
170 /* 167 /*
171 * Load the NF from history buffer of the current channel. 168 * Load the NF from history buffer of the current channel.
172 * NF is slow time-variant, so it is OK to use a historical 169 * NF is slow time-variant, so it is OK to use a historical
@@ -653,7 +650,6 @@ static void ar9003_hw_detect_outlier(int *mp_coeff, int nmeasurement,
653} 650}
654 651
655static void ar9003_hw_tx_iqcal_load_avg_2_passes(struct ath_hw *ah, 652static void ar9003_hw_tx_iqcal_load_avg_2_passes(struct ath_hw *ah,
656 u8 num_chains,
657 struct coeff *coeff, 653 struct coeff *coeff,
658 bool is_reusable) 654 bool is_reusable)
659{ 655{
@@ -677,7 +673,9 @@ static void ar9003_hw_tx_iqcal_load_avg_2_passes(struct ath_hw *ah,
677 } 673 }
678 674
679 /* Load the average of 2 passes */ 675 /* Load the average of 2 passes */
680 for (i = 0; i < num_chains; i++) { 676 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
677 if (!(ah->txchainmask & (1 << i)))
678 continue;
681 nmeasurement = REG_READ_FIELD(ah, 679 nmeasurement = REG_READ_FIELD(ah,
682 AR_PHY_TX_IQCAL_STATUS_B0, 680 AR_PHY_TX_IQCAL_STATUS_B0,
683 AR_PHY_CALIBRATED_GAINS_0); 681 AR_PHY_CALIBRATED_GAINS_0);
@@ -767,16 +765,13 @@ static void ar9003_hw_tx_iq_cal_post_proc(struct ath_hw *ah, bool is_reusable)
767 }; 765 };
768 struct coeff coeff; 766 struct coeff coeff;
769 s32 iq_res[6]; 767 s32 iq_res[6];
770 u8 num_chains = 0;
771 int i, im, j; 768 int i, im, j;
772 int nmeasurement; 769 int nmeasurement;
773 770
774 for (i = 0; i < AR9300_MAX_CHAINS; i++) { 771 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
775 if (ah->txchainmask & (1 << i)) 772 if (!(ah->txchainmask & (1 << i)))
776 num_chains++; 773 continue;
777 }
778 774
779 for (i = 0; i < num_chains; i++) {
780 nmeasurement = REG_READ_FIELD(ah, 775 nmeasurement = REG_READ_FIELD(ah,
781 AR_PHY_TX_IQCAL_STATUS_B0, 776 AR_PHY_TX_IQCAL_STATUS_B0,
782 AR_PHY_CALIBRATED_GAINS_0); 777 AR_PHY_CALIBRATED_GAINS_0);
@@ -839,8 +834,7 @@ static void ar9003_hw_tx_iq_cal_post_proc(struct ath_hw *ah, bool is_reusable)
839 coeff.phs_coeff[i][im] -= 128; 834 coeff.phs_coeff[i][im] -= 128;
840 } 835 }
841 } 836 }
842 ar9003_hw_tx_iqcal_load_avg_2_passes(ah, num_chains, 837 ar9003_hw_tx_iqcal_load_avg_2_passes(ah, &coeff, is_reusable);
843 &coeff, is_reusable);
844 838
845 return; 839 return;
846 840
@@ -901,7 +895,6 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah,
901 bool is_reusable = true, status = true; 895 bool is_reusable = true, status = true;
902 bool run_rtt_cal = false, run_agc_cal; 896 bool run_rtt_cal = false, run_agc_cal;
903 bool rtt = !!(ah->caps.hw_caps & ATH9K_HW_CAP_RTT); 897 bool rtt = !!(ah->caps.hw_caps & ATH9K_HW_CAP_RTT);
904 bool mci = !!(ah->caps.hw_caps & ATH9K_HW_CAP_MCI);
905 u32 agc_ctrl = 0, agc_supp_cals = AR_PHY_AGC_CONTROL_OFFSET_CAL | 898 u32 agc_ctrl = 0, agc_supp_cals = AR_PHY_AGC_CONTROL_OFFSET_CAL |
906 AR_PHY_AGC_CONTROL_FLTR_CAL | 899 AR_PHY_AGC_CONTROL_FLTR_CAL |
907 AR_PHY_AGC_CONTROL_PKDET_CAL; 900 AR_PHY_AGC_CONTROL_PKDET_CAL;
@@ -970,7 +963,7 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah,
970 } else if (caldata && !caldata->done_txiqcal_once) 963 } else if (caldata && !caldata->done_txiqcal_once)
971 run_agc_cal = true; 964 run_agc_cal = true;
972 965
973 if (mci && IS_CHAN_2GHZ(chan) && run_agc_cal) 966 if (ath9k_hw_mci_is_enabled(ah) && IS_CHAN_2GHZ(chan) && run_agc_cal)
974 ar9003_mci_init_cal_req(ah, &is_reusable); 967 ar9003_mci_init_cal_req(ah, &is_reusable);
975 968
976 if (!(IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan))) { 969 if (!(IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan))) {
@@ -993,7 +986,7 @@ skip_tx_iqcal:
993 0, AH_WAIT_TIMEOUT); 986 0, AH_WAIT_TIMEOUT);
994 } 987 }
995 988
996 if (mci && IS_CHAN_2GHZ(chan) && run_agc_cal) 989 if (ath9k_hw_mci_is_enabled(ah) && IS_CHAN_2GHZ(chan) && run_agc_cal)
997 ar9003_mci_init_cal_done(ah); 990 ar9003_mci_init_cal_done(ah);
998 991
999 if (rtt && !run_rtt_cal) { 992 if (rtt && !run_rtt_cal) {
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
index dfb0441f406c..ab2bfcb3bed2 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
@@ -3178,7 +3178,7 @@ static int ar9300_compress_decision(struct ath_hw *ah,
3178 mdata_size, length); 3178 mdata_size, length);
3179 return -1; 3179 return -1;
3180 } 3180 }
3181 memcpy(mptr, (u8 *) (word + COMP_HDR_LEN), length); 3181 memcpy(mptr, word + COMP_HDR_LEN, length);
3182 ath_dbg(common, EEPROM, 3182 ath_dbg(common, EEPROM,
3183 "restored eeprom %d: uncompressed, length %d\n", 3183 "restored eeprom %d: uncompressed, length %d\n",
3184 it, length); 3184 it, length);
@@ -3199,7 +3199,7 @@ static int ar9300_compress_decision(struct ath_hw *ah,
3199 "restore eeprom %d: block, reference %d, length %d\n", 3199 "restore eeprom %d: block, reference %d, length %d\n",
3200 it, reference, length); 3200 it, reference, length);
3201 ar9300_uncompress_block(ah, mptr, mdata_size, 3201 ar9300_uncompress_block(ah, mptr, mdata_size,
3202 (u8 *) (word + COMP_HDR_LEN), length); 3202 (word + COMP_HDR_LEN), length);
3203 break; 3203 break;
3204 default: 3204 default:
3205 ath_dbg(common, EEPROM, "unknown compression code %d\n", code); 3205 ath_dbg(common, EEPROM, "unknown compression code %d\n", code);
@@ -3412,11 +3412,11 @@ static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
3412 if (!dump_base_hdr) { 3412 if (!dump_base_hdr) {
3413 len += snprintf(buf + len, size - len, 3413 len += snprintf(buf + len, size - len,
3414 "%20s :\n", "2GHz modal Header"); 3414 "%20s :\n", "2GHz modal Header");
3415 len += ar9003_dump_modal_eeprom(buf, len, size, 3415 len = ar9003_dump_modal_eeprom(buf, len, size,
3416 &eep->modalHeader2G); 3416 &eep->modalHeader2G);
3417 len += snprintf(buf + len, size - len, 3417 len += snprintf(buf + len, size - len,
3418 "%20s :\n", "5GHz modal Header"); 3418 "%20s :\n", "5GHz modal Header");
3419 len += ar9003_dump_modal_eeprom(buf, len, size, 3419 len = ar9003_dump_modal_eeprom(buf, len, size,
3420 &eep->modalHeader5G); 3420 &eep->modalHeader5G);
3421 goto out; 3421 goto out;
3422 } 3422 }
@@ -3509,7 +3509,7 @@ static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
3509 3509
3510 if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah)) 3510 if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
3511 REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias); 3511 REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
3512 else if (AR_SREV_9462(ah)) 3512 else if (AR_SREV_9462(ah) || AR_SREV_9550(ah))
3513 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias); 3513 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
3514 else { 3514 else {
3515 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias); 3515 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
@@ -3591,6 +3591,9 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
3591 if (AR_SREV_9462(ah)) { 3591 if (AR_SREV_9462(ah)) {
3592 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, 3592 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
3593 AR_SWITCH_TABLE_COM_AR9462_ALL, value); 3593 AR_SWITCH_TABLE_COM_AR9462_ALL, value);
3594 } else if (AR_SREV_9550(ah)) {
3595 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
3596 AR_SWITCH_TABLE_COM_AR9550_ALL, value);
3594 } else 3597 } else
3595 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, 3598 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
3596 AR_SWITCH_TABLE_COM_ALL, value); 3599 AR_SWITCH_TABLE_COM_ALL, value);
@@ -3613,6 +3616,7 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
3613 value = ar9003_switch_com_spdt_get(ah, is2ghz); 3616 value = ar9003_switch_com_spdt_get(ah, is2ghz);
3614 REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL, 3617 REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL,
3615 AR_SWITCH_TABLE_COM_SPDT_ALL, value); 3618 AR_SWITCH_TABLE_COM_SPDT_ALL, value);
3619 REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, AR_BTCOEX_CTRL_SPDT_ENABLE);
3616 } 3620 }
3617 3621
3618 value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz); 3622 value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz);
@@ -3956,7 +3960,7 @@ static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
3956 ar9003_hw_drive_strength_apply(ah); 3960 ar9003_hw_drive_strength_apply(ah);
3957 ar9003_hw_atten_apply(ah, chan); 3961 ar9003_hw_atten_apply(ah, chan);
3958 ar9003_hw_quick_drop_apply(ah, chan->channel); 3962 ar9003_hw_quick_drop_apply(ah, chan->channel);
3959 if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah)) 3963 if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah) && !AR_SREV_9550(ah))
3960 ar9003_hw_internal_regulator_apply(ah); 3964 ar9003_hw_internal_regulator_apply(ah);
3961 if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah)) 3965 if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
3962 ar9003_hw_apply_tuning_caps(ah); 3966 ar9003_hw_apply_tuning_caps(ah);
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_hw.c b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
index a0e3394b10dc..41e88c660e48 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
@@ -21,6 +21,7 @@
21#include "ar9340_initvals.h" 21#include "ar9340_initvals.h"
22#include "ar9330_1p1_initvals.h" 22#include "ar9330_1p1_initvals.h"
23#include "ar9330_1p2_initvals.h" 23#include "ar9330_1p2_initvals.h"
24#include "ar955x_1p0_initvals.h"
24#include "ar9580_1p0_initvals.h" 25#include "ar9580_1p0_initvals.h"
25#include "ar9462_2p0_initvals.h" 26#include "ar9462_2p0_initvals.h"
26 27
@@ -327,7 +328,61 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
327 328
328 INIT_INI_ARRAY(&ah->ini_japan2484, AR9462_BBC_TXIFR_COEFFJ, 329 INIT_INI_ARRAY(&ah->ini_japan2484, AR9462_BBC_TXIFR_COEFFJ,
329 ARRAY_SIZE(AR9462_BBC_TXIFR_COEFFJ), 2); 330 ARRAY_SIZE(AR9462_BBC_TXIFR_COEFFJ), 2);
331 } else if (AR_SREV_9550(ah)) {
332 /* mac */
333 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
334 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
335 ar955x_1p0_mac_core,
336 ARRAY_SIZE(ar955x_1p0_mac_core), 2);
337 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
338 ar955x_1p0_mac_postamble,
339 ARRAY_SIZE(ar955x_1p0_mac_postamble), 5);
340
341 /* bb */
342 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
343 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
344 ar955x_1p0_baseband_core,
345 ARRAY_SIZE(ar955x_1p0_baseband_core), 2);
346 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
347 ar955x_1p0_baseband_postamble,
348 ARRAY_SIZE(ar955x_1p0_baseband_postamble), 5);
349
350 /* radio */
351 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
352 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
353 ar955x_1p0_radio_core,
354 ARRAY_SIZE(ar955x_1p0_radio_core), 2);
355 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
356 ar955x_1p0_radio_postamble,
357 ARRAY_SIZE(ar955x_1p0_radio_postamble), 5);
358
359 /* soc */
360 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
361 ar955x_1p0_soc_preamble,
362 ARRAY_SIZE(ar955x_1p0_soc_preamble), 2);
363 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
364 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
365 ar955x_1p0_soc_postamble,
366 ARRAY_SIZE(ar955x_1p0_soc_postamble), 5);
330 367
368 /* rx/tx gain */
369 INIT_INI_ARRAY(&ah->iniModesRxGain,
370 ar955x_1p0_common_wo_xlna_rx_gain_table,
371 ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_table),
372 2);
373 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
374 ar955x_1p0_common_wo_xlna_rx_gain_bounds,
375 ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_bounds),
376 5);
377 INIT_INI_ARRAY(&ah->iniModesTxGain,
378 ar955x_1p0_modes_xpa_tx_gain_table,
379 ARRAY_SIZE(ar955x_1p0_modes_xpa_tx_gain_table),
380 9);
381
382 /* Fast clock modal settings */
383 INIT_INI_ARRAY(&ah->iniModesFastClock,
384 ar955x_1p0_modes_fast_clock,
385 ARRAY_SIZE(ar955x_1p0_modes_fast_clock), 3);
331 } else if (AR_SREV_9580(ah)) { 386 } else if (AR_SREV_9580(ah)) {
332 /* mac */ 387 /* mac */
333 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0); 388 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
@@ -470,6 +525,11 @@ static void ar9003_tx_gain_table_mode0(struct ath_hw *ah)
470 ar9485_modes_lowest_ob_db_tx_gain_1_1, 525 ar9485_modes_lowest_ob_db_tx_gain_1_1,
471 ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1), 526 ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
472 5); 527 5);
528 else if (AR_SREV_9550(ah))
529 INIT_INI_ARRAY(&ah->iniModesTxGain,
530 ar955x_1p0_modes_xpa_tx_gain_table,
531 ARRAY_SIZE(ar955x_1p0_modes_xpa_tx_gain_table),
532 9);
473 else if (AR_SREV_9580(ah)) 533 else if (AR_SREV_9580(ah))
474 INIT_INI_ARRAY(&ah->iniModesTxGain, 534 INIT_INI_ARRAY(&ah->iniModesTxGain,
475 ar9580_1p0_lowest_ob_db_tx_gain_table, 535 ar9580_1p0_lowest_ob_db_tx_gain_table,
@@ -514,6 +574,11 @@ static void ar9003_tx_gain_table_mode1(struct ath_hw *ah)
514 ar9580_1p0_high_ob_db_tx_gain_table, 574 ar9580_1p0_high_ob_db_tx_gain_table,
515 ARRAY_SIZE(ar9580_1p0_high_ob_db_tx_gain_table), 575 ARRAY_SIZE(ar9580_1p0_high_ob_db_tx_gain_table),
516 5); 576 5);
577 else if (AR_SREV_9550(ah))
578 INIT_INI_ARRAY(&ah->iniModesTxGain,
579 ar955x_1p0_modes_no_xpa_tx_gain_table,
580 ARRAY_SIZE(ar955x_1p0_modes_no_xpa_tx_gain_table),
581 9);
517 else if (AR_SREV_9462_20(ah)) 582 else if (AR_SREV_9462_20(ah))
518 INIT_INI_ARRAY(&ah->iniModesTxGain, 583 INIT_INI_ARRAY(&ah->iniModesTxGain,
519 ar9462_modes_high_ob_db_tx_gain_table_2p0, 584 ar9462_modes_high_ob_db_tx_gain_table_2p0,
@@ -635,7 +700,16 @@ static void ar9003_rx_gain_table_mode0(struct ath_hw *ah)
635 ar9485Common_wo_xlna_rx_gain_1_1, 700 ar9485Common_wo_xlna_rx_gain_1_1,
636 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1), 701 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
637 2); 702 2);
638 else if (AR_SREV_9580(ah)) 703 else if (AR_SREV_9550(ah)) {
704 INIT_INI_ARRAY(&ah->iniModesRxGain,
705 ar955x_1p0_common_rx_gain_table,
706 ARRAY_SIZE(ar955x_1p0_common_rx_gain_table),
707 2);
708 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
709 ar955x_1p0_common_rx_gain_bounds,
710 ARRAY_SIZE(ar955x_1p0_common_rx_gain_bounds),
711 5);
712 } else if (AR_SREV_9580(ah))
639 INIT_INI_ARRAY(&ah->iniModesRxGain, 713 INIT_INI_ARRAY(&ah->iniModesRxGain,
640 ar9580_1p0_rx_gain_table, 714 ar9580_1p0_rx_gain_table,
641 ARRAY_SIZE(ar9580_1p0_rx_gain_table), 715 ARRAY_SIZE(ar9580_1p0_rx_gain_table),
@@ -679,7 +753,16 @@ static void ar9003_rx_gain_table_mode1(struct ath_hw *ah)
679 ar9462_common_wo_xlna_rx_gain_table_2p0, 753 ar9462_common_wo_xlna_rx_gain_table_2p0,
680 ARRAY_SIZE(ar9462_common_wo_xlna_rx_gain_table_2p0), 754 ARRAY_SIZE(ar9462_common_wo_xlna_rx_gain_table_2p0),
681 2); 755 2);
682 else if (AR_SREV_9580(ah)) 756 else if (AR_SREV_9550(ah)) {
757 INIT_INI_ARRAY(&ah->iniModesRxGain,
758 ar955x_1p0_common_wo_xlna_rx_gain_table,
759 ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_table),
760 2);
761 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
762 ar955x_1p0_common_wo_xlna_rx_gain_bounds,
763 ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_bounds),
764 5);
765 } else if (AR_SREV_9580(ah))
683 INIT_INI_ARRAY(&ah->iniModesRxGain, 766 INIT_INI_ARRAY(&ah->iniModesRxGain,
684 ar9580_1p0_wo_xlna_rx_gain_table, 767 ar9580_1p0_wo_xlna_rx_gain_table,
685 ARRAY_SIZE(ar9580_1p0_wo_xlna_rx_gain_table), 768 ARRAY_SIZE(ar9580_1p0_wo_xlna_rx_gain_table),
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_mac.c b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
index d9e0824af093..78816b8b2173 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_mac.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
@@ -181,11 +181,14 @@ static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
181 u32 mask2 = 0; 181 u32 mask2 = 0;
182 struct ath9k_hw_capabilities *pCap = &ah->caps; 182 struct ath9k_hw_capabilities *pCap = &ah->caps;
183 struct ath_common *common = ath9k_hw_common(ah); 183 struct ath_common *common = ath9k_hw_common(ah);
184 u32 sync_cause = 0, async_cause; 184 u32 sync_cause = 0, async_cause, async_mask = AR_INTR_MAC_IRQ;
185
186 if (ath9k_hw_mci_is_enabled(ah))
187 async_mask |= AR_INTR_ASYNC_MASK_MCI;
185 188
186 async_cause = REG_READ(ah, AR_INTR_ASYNC_CAUSE); 189 async_cause = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
187 190
188 if (async_cause & (AR_INTR_MAC_IRQ | AR_INTR_ASYNC_MASK_MCI)) { 191 if (async_cause & async_mask) {
189 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) 192 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
190 == AR_RTC_STATUS_ON) 193 == AR_RTC_STATUS_ON)
191 isr = REG_READ(ah, AR_ISR); 194 isr = REG_READ(ah, AR_ISR);
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_mci.c b/drivers/net/wireless/ath/ath9k/ar9003_mci.c
index ffbb180f91e1..9a34fcaae3ff 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_mci.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_mci.c
@@ -35,31 +35,30 @@ static int ar9003_mci_wait_for_interrupt(struct ath_hw *ah, u32 address,
35 struct ath_common *common = ath9k_hw_common(ah); 35 struct ath_common *common = ath9k_hw_common(ah);
36 36
37 while (time_out) { 37 while (time_out) {
38 if (REG_READ(ah, address) & bit_position) { 38 if (!(REG_READ(ah, address) & bit_position)) {
39 REG_WRITE(ah, address, bit_position); 39 udelay(10);
40 40 time_out -= 10;
41 if (address == AR_MCI_INTERRUPT_RX_MSG_RAW) {
42 if (bit_position &
43 AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE)
44 ar9003_mci_reset_req_wakeup(ah);
45
46 if (bit_position &
47 (AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING |
48 AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING))
49 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW,
50 AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE);
51
52 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW,
53 AR_MCI_INTERRUPT_RX_MSG);
54 }
55 break;
56 }
57 41
58 udelay(10); 42 if (time_out < 0)
59 time_out -= 10; 43 break;
44 else
45 continue;
46 }
47 REG_WRITE(ah, address, bit_position);
60 48
61 if (time_out < 0) 49 if (address != AR_MCI_INTERRUPT_RX_MSG_RAW)
62 break; 50 break;
51
52 if (bit_position & AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE)
53 ar9003_mci_reset_req_wakeup(ah);
54
55 if (bit_position & (AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING |
56 AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING))
57 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW,
58 AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE);
59
60 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, AR_MCI_INTERRUPT_RX_MSG);
61 break;
63 } 62 }
64 63
65 if (time_out <= 0) { 64 if (time_out <= 0) {
@@ -127,14 +126,13 @@ static void ar9003_mci_send_coex_version_query(struct ath_hw *ah,
127 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; 126 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
128 u32 payload[4] = {0, 0, 0, 0}; 127 u32 payload[4] = {0, 0, 0, 0};
129 128
130 if (!mci->bt_version_known && 129 if (mci->bt_version_known ||
131 (mci->bt_state != MCI_BT_SLEEP)) { 130 (mci->bt_state == MCI_BT_SLEEP))
132 MCI_GPM_SET_TYPE_OPCODE(payload, 131 return;
133 MCI_GPM_COEX_AGENT, 132
134 MCI_GPM_COEX_VERSION_QUERY); 133 MCI_GPM_SET_TYPE_OPCODE(payload, MCI_GPM_COEX_AGENT,
135 ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 16, 134 MCI_GPM_COEX_VERSION_QUERY);
136 wait_done, true); 135 ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 16, wait_done, true);
137 }
138} 136}
139 137
140static void ar9003_mci_send_coex_version_response(struct ath_hw *ah, 138static void ar9003_mci_send_coex_version_response(struct ath_hw *ah,
@@ -158,15 +156,14 @@ static void ar9003_mci_send_coex_wlan_channels(struct ath_hw *ah,
158 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; 156 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
159 u32 *payload = &mci->wlan_channels[0]; 157 u32 *payload = &mci->wlan_channels[0];
160 158
161 if ((mci->wlan_channels_update == true) && 159 if (!mci->wlan_channels_update ||
162 (mci->bt_state != MCI_BT_SLEEP)) { 160 (mci->bt_state == MCI_BT_SLEEP))
163 MCI_GPM_SET_TYPE_OPCODE(payload, 161 return;
164 MCI_GPM_COEX_AGENT, 162
165 MCI_GPM_COEX_WLAN_CHANNELS); 163 MCI_GPM_SET_TYPE_OPCODE(payload, MCI_GPM_COEX_AGENT,
166 ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 16, 164 MCI_GPM_COEX_WLAN_CHANNELS);
167 wait_done, true); 165 ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 16, wait_done, true);
168 MCI_GPM_SET_TYPE_OPCODE(payload, 0xff, 0xff); 166 MCI_GPM_SET_TYPE_OPCODE(payload, 0xff, 0xff);
169 }
170} 167}
171 168
172static void ar9003_mci_send_coex_bt_status_query(struct ath_hw *ah, 169static void ar9003_mci_send_coex_bt_status_query(struct ath_hw *ah,
@@ -174,29 +171,30 @@ static void ar9003_mci_send_coex_bt_status_query(struct ath_hw *ah,
174{ 171{
175 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; 172 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
176 u32 payload[4] = {0, 0, 0, 0}; 173 u32 payload[4] = {0, 0, 0, 0};
177 bool query_btinfo = !!(query_type & (MCI_GPM_COEX_QUERY_BT_ALL_INFO | 174 bool query_btinfo;
178 MCI_GPM_COEX_QUERY_BT_TOPOLOGY));
179 175
180 if (mci->bt_state != MCI_BT_SLEEP) { 176 if (mci->bt_state == MCI_BT_SLEEP)
177 return;
181 178
182 MCI_GPM_SET_TYPE_OPCODE(payload, MCI_GPM_COEX_AGENT, 179 query_btinfo = !!(query_type & (MCI_GPM_COEX_QUERY_BT_ALL_INFO |
183 MCI_GPM_COEX_STATUS_QUERY); 180 MCI_GPM_COEX_QUERY_BT_TOPOLOGY));
181 MCI_GPM_SET_TYPE_OPCODE(payload, MCI_GPM_COEX_AGENT,
182 MCI_GPM_COEX_STATUS_QUERY);
184 183
185 *(((u8 *)payload) + MCI_GPM_COEX_B_BT_BITMAP) = query_type; 184 *(((u8 *)payload) + MCI_GPM_COEX_B_BT_BITMAP) = query_type;
186
187 /*
188 * If bt_status_query message is not sent successfully,
189 * then need_flush_btinfo should be set again.
190 */
191 if (!ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 16,
192 wait_done, true)) {
193 if (query_btinfo)
194 mci->need_flush_btinfo = true;
195 }
196 185
186 /*
187 * If bt_status_query message is not sent successfully,
188 * then need_flush_btinfo should be set again.
189 */
190 if (!ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 16,
191 wait_done, true)) {
197 if (query_btinfo) 192 if (query_btinfo)
198 mci->query_bt = false; 193 mci->need_flush_btinfo = true;
199 } 194 }
195
196 if (query_btinfo)
197 mci->query_bt = false;
200} 198}
201 199
202static void ar9003_mci_send_coex_halt_bt_gpm(struct ath_hw *ah, bool halt, 200static void ar9003_mci_send_coex_halt_bt_gpm(struct ath_hw *ah, bool halt,
@@ -241,73 +239,73 @@ static void ar9003_mci_prep_interface(struct ath_hw *ah)
241 ar9003_mci_remote_reset(ah, true); 239 ar9003_mci_remote_reset(ah, true);
242 ar9003_mci_send_req_wake(ah, true); 240 ar9003_mci_send_req_wake(ah, true);
243 241
244 if (ar9003_mci_wait_for_interrupt(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, 242 if (!ar9003_mci_wait_for_interrupt(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
245 AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING, 500)) { 243 AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING, 500))
244 goto clear_redunt;
246 245
247 mci->bt_state = MCI_BT_AWAKE; 246 mci->bt_state = MCI_BT_AWAKE;
248 247
249 /* 248 /*
250 * we don't need to send more remote_reset at this moment. 249 * we don't need to send more remote_reset at this moment.
251 * If BT receive first remote_reset, then BT HW will 250 * If BT receive first remote_reset, then BT HW will
252 * be cleaned up and will be able to receive req_wake 251 * be cleaned up and will be able to receive req_wake
253 * and BT HW will respond sys_waking. 252 * and BT HW will respond sys_waking.
254 * In this case, WLAN will receive BT's HW sys_waking. 253 * In this case, WLAN will receive BT's HW sys_waking.
255 * Otherwise, if BT SW missed initial remote_reset, 254 * Otherwise, if BT SW missed initial remote_reset,
256 * that remote_reset will still clean up BT MCI RX, 255 * that remote_reset will still clean up BT MCI RX,
257 * and the req_wake will wake BT up, 256 * and the req_wake will wake BT up,
258 * and BT SW will respond this req_wake with a remote_reset and 257 * and BT SW will respond this req_wake with a remote_reset and
259 * sys_waking. In this case, WLAN will receive BT's SW 258 * sys_waking. In this case, WLAN will receive BT's SW
260 * sys_waking. In either case, BT's RX is cleaned up. So we 259 * sys_waking. In either case, BT's RX is cleaned up. So we
261 * don't need to reply BT's remote_reset now, if any. 260 * don't need to reply BT's remote_reset now, if any.
262 * Similarly, if in any case, WLAN can receive BT's sys_waking, 261 * Similarly, if in any case, WLAN can receive BT's sys_waking,
263 * that means WLAN's RX is also fine. 262 * that means WLAN's RX is also fine.
264 */ 263 */
265 ar9003_mci_send_sys_waking(ah, true); 264 ar9003_mci_send_sys_waking(ah, true);
266 udelay(10); 265 udelay(10);
267 266
268 /* 267 /*
269 * Set BT priority interrupt value to be 0xff to 268 * Set BT priority interrupt value to be 0xff to
270 * avoid having too many BT PRIORITY interrupts. 269 * avoid having too many BT PRIORITY interrupts.
271 */ 270 */
272 REG_WRITE(ah, AR_MCI_BT_PRI0, 0xFFFFFFFF); 271 REG_WRITE(ah, AR_MCI_BT_PRI0, 0xFFFFFFFF);
273 REG_WRITE(ah, AR_MCI_BT_PRI1, 0xFFFFFFFF); 272 REG_WRITE(ah, AR_MCI_BT_PRI1, 0xFFFFFFFF);
274 REG_WRITE(ah, AR_MCI_BT_PRI2, 0xFFFFFFFF); 273 REG_WRITE(ah, AR_MCI_BT_PRI2, 0xFFFFFFFF);
275 REG_WRITE(ah, AR_MCI_BT_PRI3, 0xFFFFFFFF); 274 REG_WRITE(ah, AR_MCI_BT_PRI3, 0xFFFFFFFF);
276 REG_WRITE(ah, AR_MCI_BT_PRI, 0X000000FF); 275 REG_WRITE(ah, AR_MCI_BT_PRI, 0X000000FF);
277 276
278 /* 277 /*
279 * A contention reset will be received after send out 278 * A contention reset will be received after send out
280 * sys_waking. Also BT priority interrupt bits will be set. 279 * sys_waking. Also BT priority interrupt bits will be set.
281 * Clear those bits before the next step. 280 * Clear those bits before the next step.
282 */ 281 */
283 282
284 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, 283 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
285 AR_MCI_INTERRUPT_RX_MSG_CONT_RST); 284 AR_MCI_INTERRUPT_RX_MSG_CONT_RST);
286 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, 285 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, AR_MCI_INTERRUPT_BT_PRI);
287 AR_MCI_INTERRUPT_BT_PRI);
288 286
289 if (mci->is_2g) { 287 if (mci->is_2g) {
290 ar9003_mci_send_lna_transfer(ah, true); 288 ar9003_mci_send_lna_transfer(ah, true);
291 udelay(5); 289 udelay(5);
292 } 290 }
293 291
294 if ((mci->is_2g && !mci->update_2g5g)) { 292 if ((mci->is_2g && !mci->update_2g5g)) {
295 if (ar9003_mci_wait_for_interrupt(ah, 293 if (ar9003_mci_wait_for_interrupt(ah,
296 AR_MCI_INTERRUPT_RX_MSG_RAW, 294 AR_MCI_INTERRUPT_RX_MSG_RAW,
297 AR_MCI_INTERRUPT_RX_MSG_LNA_INFO, 295 AR_MCI_INTERRUPT_RX_MSG_LNA_INFO,
298 mci_timeout)) 296 mci_timeout))
299 ath_dbg(common, MCI, 297 ath_dbg(common, MCI,
300 "MCI WLAN has control over the LNA & BT obeys it\n"); 298 "MCI WLAN has control over the LNA & BT obeys it\n");
301 else 299 else
302 ath_dbg(common, MCI, 300 ath_dbg(common, MCI,
303 "MCI BT didn't respond to LNA_TRANS\n"); 301 "MCI BT didn't respond to LNA_TRANS\n");
304 }
305 } 302 }
306 303
304clear_redunt:
307 /* Clear the extra redundant SYS_WAKING from BT */ 305 /* Clear the extra redundant SYS_WAKING from BT */
308 if ((mci->bt_state == MCI_BT_AWAKE) && 306 if ((mci->bt_state == MCI_BT_AWAKE) &&
309 (REG_READ_FIELD(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, 307 (REG_READ_FIELD(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
310 AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING)) && 308 AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING)) &&
311 (REG_READ_FIELD(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, 309 (REG_READ_FIELD(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
312 AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING) == 0)) { 310 AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING) == 0)) {
313 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, 311 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
@@ -323,14 +321,13 @@ void ar9003_mci_set_full_sleep(struct ath_hw *ah)
323{ 321{
324 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; 322 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
325 323
326 if (ar9003_mci_state(ah, MCI_STATE_ENABLE, NULL) && 324 if (ar9003_mci_state(ah, MCI_STATE_ENABLE) &&
327 (mci->bt_state != MCI_BT_SLEEP) && 325 (mci->bt_state != MCI_BT_SLEEP) &&
328 !mci->halted_bt_gpm) { 326 !mci->halted_bt_gpm) {
329 ar9003_mci_send_coex_halt_bt_gpm(ah, true, true); 327 ar9003_mci_send_coex_halt_bt_gpm(ah, true, true);
330 } 328 }
331 329
332 mci->ready = false; 330 mci->ready = false;
333 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
334} 331}
335 332
336static void ar9003_mci_disable_interrupt(struct ath_hw *ah) 333static void ar9003_mci_disable_interrupt(struct ath_hw *ah)
@@ -487,7 +484,7 @@ static void ar9003_mci_sync_bt_state(struct ath_hw *ah)
487 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; 484 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
488 u32 cur_bt_state; 485 u32 cur_bt_state;
489 486
490 cur_bt_state = ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP, NULL); 487 cur_bt_state = ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP);
491 488
492 if (mci->bt_state != cur_bt_state) 489 if (mci->bt_state != cur_bt_state)
493 mci->bt_state = cur_bt_state; 490 mci->bt_state = cur_bt_state;
@@ -596,8 +593,7 @@ static u32 ar9003_mci_wait_for_gpm(struct ath_hw *ah, u8 gpm_type,
596 if (!time_out) 593 if (!time_out)
597 break; 594 break;
598 595
599 offset = ar9003_mci_state(ah, MCI_STATE_NEXT_GPM_OFFSET, 596 offset = ar9003_mci_get_next_gpm_offset(ah, false, &more_data);
600 &more_data);
601 597
602 if (offset == MCI_GPM_INVALID) 598 if (offset == MCI_GPM_INVALID)
603 continue; 599 continue;
@@ -615,9 +611,9 @@ static u32 ar9003_mci_wait_for_gpm(struct ath_hw *ah, u8 gpm_type,
615 } 611 }
616 break; 612 break;
617 } 613 }
618 } else if ((recv_type == gpm_type) && (recv_opcode == gpm_opcode)) { 614 } else if ((recv_type == gpm_type) &&
615 (recv_opcode == gpm_opcode))
619 break; 616 break;
620 }
621 617
622 /* 618 /*
623 * check if it's cal_grant 619 * check if it's cal_grant
@@ -661,8 +657,7 @@ static u32 ar9003_mci_wait_for_gpm(struct ath_hw *ah, u8 gpm_type,
661 time_out = 0; 657 time_out = 0;
662 658
663 while (more_data == MCI_GPM_MORE) { 659 while (more_data == MCI_GPM_MORE) {
664 offset = ar9003_mci_state(ah, MCI_STATE_NEXT_GPM_OFFSET, 660 offset = ar9003_mci_get_next_gpm_offset(ah, false, &more_data);
665 &more_data);
666 if (offset == MCI_GPM_INVALID) 661 if (offset == MCI_GPM_INVALID)
667 break; 662 break;
668 663
@@ -731,38 +726,38 @@ int ar9003_mci_end_reset(struct ath_hw *ah, struct ath9k_channel *chan,
731 if (!IS_CHAN_2GHZ(chan) || (mci_hw->bt_state != MCI_BT_SLEEP)) 726 if (!IS_CHAN_2GHZ(chan) || (mci_hw->bt_state != MCI_BT_SLEEP))
732 goto exit; 727 goto exit;
733 728
734 if (ar9003_mci_check_int(ah, AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET) || 729 if (!ar9003_mci_check_int(ah, AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET) &&
735 ar9003_mci_check_int(ah, AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE)) { 730 !ar9003_mci_check_int(ah, AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE))
731 goto exit;
736 732
737 /* 733 /*
738 * BT is sleeping. Check if BT wakes up during 734 * BT is sleeping. Check if BT wakes up during
739 * WLAN calibration. If BT wakes up during 735 * WLAN calibration. If BT wakes up during
740 * WLAN calibration, need to go through all 736 * WLAN calibration, need to go through all
741 * message exchanges again and recal. 737 * message exchanges again and recal.
742 */ 738 */
743 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, 739 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
744 AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET | 740 (AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET |
745 AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE); 741 AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE));
746 742
747 ar9003_mci_remote_reset(ah, true); 743 ar9003_mci_remote_reset(ah, true);
748 ar9003_mci_send_sys_waking(ah, true); 744 ar9003_mci_send_sys_waking(ah, true);
749 udelay(1); 745 udelay(1);
750 746
751 if (IS_CHAN_2GHZ(chan)) 747 if (IS_CHAN_2GHZ(chan))
752 ar9003_mci_send_lna_transfer(ah, true); 748 ar9003_mci_send_lna_transfer(ah, true);
753 749
754 mci_hw->bt_state = MCI_BT_AWAKE; 750 mci_hw->bt_state = MCI_BT_AWAKE;
755 751
756 if (caldata) { 752 if (caldata) {
757 caldata->done_txiqcal_once = false; 753 caldata->done_txiqcal_once = false;
758 caldata->done_txclcal_once = false; 754 caldata->done_txclcal_once = false;
759 caldata->rtt_done = false; 755 caldata->rtt_done = false;
760 } 756 }
761 757
762 if (!ath9k_hw_init_cal(ah, chan)) 758 if (!ath9k_hw_init_cal(ah, chan))
763 return -EIO; 759 return -EIO;
764 760
765 }
766exit: 761exit:
767 ar9003_mci_enable_interrupt(ah); 762 ar9003_mci_enable_interrupt(ah);
768 return 0; 763 return 0;
@@ -772,10 +767,6 @@ static void ar9003_mci_mute_bt(struct ath_hw *ah)
772{ 767{
773 /* disable all MCI messages */ 768 /* disable all MCI messages */
774 REG_WRITE(ah, AR_MCI_MSG_ATTRIBUTES_TABLE, 0xffff0000); 769 REG_WRITE(ah, AR_MCI_MSG_ATTRIBUTES_TABLE, 0xffff0000);
775 REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS0, 0xffffffff);
776 REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS1, 0xffffffff);
777 REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS2, 0xffffffff);
778 REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS3, 0xffffffff);
779 REG_SET_BIT(ah, AR_MCI_TX_CTRL, AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE); 770 REG_SET_BIT(ah, AR_MCI_TX_CTRL, AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE);
780 771
781 /* wait pending HW messages to flush out */ 772 /* wait pending HW messages to flush out */
@@ -798,29 +789,27 @@ static void ar9003_mci_osla_setup(struct ath_hw *ah, bool enable)
798 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; 789 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
799 u32 thresh; 790 u32 thresh;
800 791
801 if (enable) { 792 if (!enable) {
802 REG_RMW_FIELD(ah, AR_MCI_SCHD_TABLE_2,
803 AR_MCI_SCHD_TABLE_2_HW_BASED, 1);
804 REG_RMW_FIELD(ah, AR_MCI_SCHD_TABLE_2,
805 AR_MCI_SCHD_TABLE_2_MEM_BASED, 1);
806
807 if (!(mci->config & ATH_MCI_CONFIG_DISABLE_AGGR_THRESH)) {
808 thresh = MS(mci->config, ATH_MCI_CONFIG_AGGR_THRESH);
809 REG_RMW_FIELD(ah, AR_BTCOEX_CTRL,
810 AR_BTCOEX_CTRL_AGGR_THRESH, thresh);
811 REG_RMW_FIELD(ah, AR_BTCOEX_CTRL,
812 AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN, 1);
813 } else {
814 REG_RMW_FIELD(ah, AR_BTCOEX_CTRL,
815 AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN, 0);
816 }
817
818 REG_RMW_FIELD(ah, AR_BTCOEX_CTRL,
819 AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN, 1);
820 } else {
821 REG_CLR_BIT(ah, AR_BTCOEX_CTRL, 793 REG_CLR_BIT(ah, AR_BTCOEX_CTRL,
822 AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN); 794 AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN);
795 return;
823 } 796 }
797 REG_RMW_FIELD(ah, AR_MCI_SCHD_TABLE_2, AR_MCI_SCHD_TABLE_2_HW_BASED, 1);
798 REG_RMW_FIELD(ah, AR_MCI_SCHD_TABLE_2,
799 AR_MCI_SCHD_TABLE_2_MEM_BASED, 1);
800
801 if (!(mci->config & ATH_MCI_CONFIG_DISABLE_AGGR_THRESH)) {
802 thresh = MS(mci->config, ATH_MCI_CONFIG_AGGR_THRESH);
803 REG_RMW_FIELD(ah, AR_BTCOEX_CTRL,
804 AR_BTCOEX_CTRL_AGGR_THRESH, thresh);
805 REG_RMW_FIELD(ah, AR_BTCOEX_CTRL,
806 AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN, 1);
807 } else
808 REG_RMW_FIELD(ah, AR_BTCOEX_CTRL,
809 AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN, 0);
810
811 REG_RMW_FIELD(ah, AR_BTCOEX_CTRL,
812 AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN, 1);
824} 813}
825 814
826void ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g, 815void ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g,
@@ -898,13 +887,16 @@ void ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g,
898 udelay(100); 887 udelay(100);
899 } 888 }
900 889
890 /* Check pending GPM msg before MCI Reset Rx */
891 ar9003_mci_check_gpm_offset(ah);
892
901 regval |= SM(1, AR_MCI_COMMAND2_RESET_RX); 893 regval |= SM(1, AR_MCI_COMMAND2_RESET_RX);
902 REG_WRITE(ah, AR_MCI_COMMAND2, regval); 894 REG_WRITE(ah, AR_MCI_COMMAND2, regval);
903 udelay(1); 895 udelay(1);
904 regval &= ~SM(1, AR_MCI_COMMAND2_RESET_RX); 896 regval &= ~SM(1, AR_MCI_COMMAND2_RESET_RX);
905 REG_WRITE(ah, AR_MCI_COMMAND2, regval); 897 REG_WRITE(ah, AR_MCI_COMMAND2, regval);
906 898
907 ar9003_mci_state(ah, MCI_STATE_INIT_GPM_OFFSET, NULL); 899 ar9003_mci_get_next_gpm_offset(ah, true, NULL);
908 900
909 REG_WRITE(ah, AR_MCI_MSG_ATTRIBUTES_TABLE, 901 REG_WRITE(ah, AR_MCI_MSG_ATTRIBUTES_TABLE,
910 (SM(0xe801, AR_MCI_MSG_ATTRIBUTES_TABLE_INVALID_HDR) | 902 (SM(0xe801, AR_MCI_MSG_ATTRIBUTES_TABLE_INVALID_HDR) |
@@ -943,26 +935,27 @@ static void ar9003_mci_send_2g5g_status(struct ath_hw *ah, bool wait_done)
943 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; 935 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
944 u32 new_flags, to_set, to_clear; 936 u32 new_flags, to_set, to_clear;
945 937
946 if (mci->update_2g5g && (mci->bt_state != MCI_BT_SLEEP)) { 938 if (!mci->update_2g5g || (mci->bt_state == MCI_BT_SLEEP))
947 if (mci->is_2g) { 939 return;
948 new_flags = MCI_2G_FLAGS; 940
949 to_clear = MCI_2G_FLAGS_CLEAR_MASK; 941 if (mci->is_2g) {
950 to_set = MCI_2G_FLAGS_SET_MASK; 942 new_flags = MCI_2G_FLAGS;
951 } else { 943 to_clear = MCI_2G_FLAGS_CLEAR_MASK;
952 new_flags = MCI_5G_FLAGS; 944 to_set = MCI_2G_FLAGS_SET_MASK;
953 to_clear = MCI_5G_FLAGS_CLEAR_MASK; 945 } else {
954 to_set = MCI_5G_FLAGS_SET_MASK; 946 new_flags = MCI_5G_FLAGS;
955 } 947 to_clear = MCI_5G_FLAGS_CLEAR_MASK;
948 to_set = MCI_5G_FLAGS_SET_MASK;
949 }
956 950
957 if (to_clear) 951 if (to_clear)
958 ar9003_mci_send_coex_bt_flags(ah, wait_done, 952 ar9003_mci_send_coex_bt_flags(ah, wait_done,
959 MCI_GPM_COEX_BT_FLAGS_CLEAR, 953 MCI_GPM_COEX_BT_FLAGS_CLEAR,
960 to_clear); 954 to_clear);
961 if (to_set) 955 if (to_set)
962 ar9003_mci_send_coex_bt_flags(ah, wait_done, 956 ar9003_mci_send_coex_bt_flags(ah, wait_done,
963 MCI_GPM_COEX_BT_FLAGS_SET, 957 MCI_GPM_COEX_BT_FLAGS_SET,
964 to_set); 958 to_set);
965 }
966} 959}
967 960
968static void ar9003_mci_queue_unsent_gpm(struct ath_hw *ah, u8 header, 961static void ar9003_mci_queue_unsent_gpm(struct ath_hw *ah, u8 header,
@@ -1014,38 +1007,36 @@ static void ar9003_mci_queue_unsent_gpm(struct ath_hw *ah, u8 header,
1014 } 1007 }
1015} 1008}
1016 1009
1017void ar9003_mci_2g5g_switch(struct ath_hw *ah, bool wait_done) 1010void ar9003_mci_2g5g_switch(struct ath_hw *ah, bool force)
1018{ 1011{
1019 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; 1012 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
1020 1013
1021 if (mci->update_2g5g) { 1014 if (!mci->update_2g5g && !force)
1022 if (mci->is_2g) { 1015 return;
1023 ar9003_mci_send_2g5g_status(ah, true);
1024 ar9003_mci_send_lna_transfer(ah, true);
1025 udelay(5);
1026 1016
1027 REG_CLR_BIT(ah, AR_MCI_TX_CTRL, 1017 if (mci->is_2g) {
1028 AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE); 1018 ar9003_mci_send_2g5g_status(ah, true);
1029 REG_CLR_BIT(ah, AR_PHY_GLB_CONTROL, 1019 ar9003_mci_send_lna_transfer(ah, true);
1030 AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL); 1020 udelay(5);
1031 1021
1032 if (!(mci->config & ATH_MCI_CONFIG_DISABLE_OSLA)) { 1022 REG_CLR_BIT(ah, AR_MCI_TX_CTRL,
1033 REG_SET_BIT(ah, AR_BTCOEX_CTRL, 1023 AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE);
1034 AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN); 1024 REG_CLR_BIT(ah, AR_PHY_GLB_CONTROL,
1035 } 1025 AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL);
1036 } else { 1026
1037 ar9003_mci_send_lna_take(ah, true); 1027 if (!(mci->config & ATH_MCI_CONFIG_DISABLE_OSLA))
1038 udelay(5); 1028 ar9003_mci_osla_setup(ah, true);
1029 } else {
1030 ar9003_mci_send_lna_take(ah, true);
1031 udelay(5);
1039 1032
1040 REG_SET_BIT(ah, AR_MCI_TX_CTRL, 1033 REG_SET_BIT(ah, AR_MCI_TX_CTRL,
1041 AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE); 1034 AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE);
1042 REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, 1035 REG_SET_BIT(ah, AR_PHY_GLB_CONTROL,
1043 AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL); 1036 AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL);
1044 REG_CLR_BIT(ah, AR_BTCOEX_CTRL,
1045 AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN);
1046 1037
1047 ar9003_mci_send_2g5g_status(ah, true); 1038 ar9003_mci_osla_setup(ah, false);
1048 } 1039 ar9003_mci_send_2g5g_status(ah, true);
1049 } 1040 }
1050} 1041}
1051 1042
@@ -1132,7 +1123,7 @@ void ar9003_mci_init_cal_req(struct ath_hw *ah, bool *is_reusable)
1132 if (ar9003_mci_wait_for_gpm(ah, MCI_GPM_BT_CAL_GRANT, 0, 50000)) { 1123 if (ar9003_mci_wait_for_gpm(ah, MCI_GPM_BT_CAL_GRANT, 0, 50000)) {
1133 ath_dbg(common, MCI, "MCI BT_CAL_GRANT received\n"); 1124 ath_dbg(common, MCI, "MCI BT_CAL_GRANT received\n");
1134 } else { 1125 } else {
1135 is_reusable = false; 1126 *is_reusable = false;
1136 ath_dbg(common, MCI, "MCI BT_CAL_GRANT not received\n"); 1127 ath_dbg(common, MCI, "MCI BT_CAL_GRANT not received\n");
1137 } 1128 }
1138} 1129}
@@ -1173,11 +1164,10 @@ void ar9003_mci_cleanup(struct ath_hw *ah)
1173} 1164}
1174EXPORT_SYMBOL(ar9003_mci_cleanup); 1165EXPORT_SYMBOL(ar9003_mci_cleanup);
1175 1166
1176u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type, u32 *p_data) 1167u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type)
1177{ 1168{
1178 struct ath_common *common = ath9k_hw_common(ah);
1179 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; 1169 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
1180 u32 value = 0, more_gpm = 0, gpm_ptr; 1170 u32 value = 0;
1181 u8 query_type; 1171 u8 query_type;
1182 1172
1183 switch (state_type) { 1173 switch (state_type) {
@@ -1190,81 +1180,6 @@ u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type, u32 *p_data)
1190 } 1180 }
1191 value &= AR_BTCOEX_CTRL_MCI_MODE_EN; 1181 value &= AR_BTCOEX_CTRL_MCI_MODE_EN;
1192 break; 1182 break;
1193 case MCI_STATE_INIT_GPM_OFFSET:
1194 value = MS(REG_READ(ah, AR_MCI_GPM_1), AR_MCI_GPM_WRITE_PTR);
1195 mci->gpm_idx = value;
1196 break;
1197 case MCI_STATE_NEXT_GPM_OFFSET:
1198 case MCI_STATE_LAST_GPM_OFFSET:
1199 /*
1200 * This could be useful to avoid new GPM message interrupt which
1201 * may lead to spurious interrupt after power sleep, or multiple
1202 * entry of ath_mci_intr().
1203 * Adding empty GPM check by returning HAL_MCI_GPM_INVALID can
1204 * alleviate this effect, but clearing GPM RX interrupt bit is
1205 * safe, because whether this is called from hw or driver code
1206 * there must be an interrupt bit set/triggered initially
1207 */
1208 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
1209 AR_MCI_INTERRUPT_RX_MSG_GPM);
1210
1211 gpm_ptr = MS(REG_READ(ah, AR_MCI_GPM_1), AR_MCI_GPM_WRITE_PTR);
1212 value = gpm_ptr;
1213
1214 if (value == 0)
1215 value = mci->gpm_len - 1;
1216 else if (value >= mci->gpm_len) {
1217 if (value != 0xFFFF)
1218 value = 0;
1219 } else {
1220 value--;
1221 }
1222
1223 if (value == 0xFFFF) {
1224 value = MCI_GPM_INVALID;
1225 more_gpm = MCI_GPM_NOMORE;
1226 } else if (state_type == MCI_STATE_NEXT_GPM_OFFSET) {
1227 if (gpm_ptr == mci->gpm_idx) {
1228 value = MCI_GPM_INVALID;
1229 more_gpm = MCI_GPM_NOMORE;
1230 } else {
1231 for (;;) {
1232 u32 temp_index;
1233
1234 /* skip reserved GPM if any */
1235
1236 if (value != mci->gpm_idx)
1237 more_gpm = MCI_GPM_MORE;
1238 else
1239 more_gpm = MCI_GPM_NOMORE;
1240
1241 temp_index = mci->gpm_idx;
1242 mci->gpm_idx++;
1243
1244 if (mci->gpm_idx >=
1245 mci->gpm_len)
1246 mci->gpm_idx = 0;
1247
1248 if (ar9003_mci_is_gpm_valid(ah,
1249 temp_index)) {
1250 value = temp_index;
1251 break;
1252 }
1253
1254 if (more_gpm == MCI_GPM_NOMORE) {
1255 value = MCI_GPM_INVALID;
1256 break;
1257 }
1258 }
1259 }
1260 if (p_data)
1261 *p_data = more_gpm;
1262 }
1263
1264 if (value != MCI_GPM_INVALID)
1265 value <<= 4;
1266
1267 break;
1268 case MCI_STATE_LAST_SCHD_MSG_OFFSET: 1183 case MCI_STATE_LAST_SCHD_MSG_OFFSET:
1269 value = MS(REG_READ(ah, AR_MCI_RX_STATUS), 1184 value = MS(REG_READ(ah, AR_MCI_RX_STATUS),
1270 AR_MCI_RX_LAST_SCHD_MSG_INDEX); 1185 AR_MCI_RX_LAST_SCHD_MSG_INDEX);
@@ -1276,21 +1191,6 @@ u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type, u32 *p_data)
1276 AR_MCI_RX_REMOTE_SLEEP) ? 1191 AR_MCI_RX_REMOTE_SLEEP) ?
1277 MCI_BT_SLEEP : MCI_BT_AWAKE; 1192 MCI_BT_SLEEP : MCI_BT_AWAKE;
1278 break; 1193 break;
1279 case MCI_STATE_CONT_RSSI_POWER:
1280 value = MS(mci->cont_status, AR_MCI_CONT_RSSI_POWER);
1281 break;
1282 case MCI_STATE_CONT_PRIORITY:
1283 value = MS(mci->cont_status, AR_MCI_CONT_RRIORITY);
1284 break;
1285 case MCI_STATE_CONT_TXRX:
1286 value = MS(mci->cont_status, AR_MCI_CONT_TXRX);
1287 break;
1288 case MCI_STATE_BT:
1289 value = mci->bt_state;
1290 break;
1291 case MCI_STATE_SET_BT_SLEEP:
1292 mci->bt_state = MCI_BT_SLEEP;
1293 break;
1294 case MCI_STATE_SET_BT_AWAKE: 1194 case MCI_STATE_SET_BT_AWAKE:
1295 mci->bt_state = MCI_BT_AWAKE; 1195 mci->bt_state = MCI_BT_AWAKE;
1296 ar9003_mci_send_coex_version_query(ah, true); 1196 ar9003_mci_send_coex_version_query(ah, true);
@@ -1299,7 +1199,7 @@ u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type, u32 *p_data)
1299 if (mci->unhalt_bt_gpm) 1199 if (mci->unhalt_bt_gpm)
1300 ar9003_mci_send_coex_halt_bt_gpm(ah, false, true); 1200 ar9003_mci_send_coex_halt_bt_gpm(ah, false, true);
1301 1201
1302 ar9003_mci_2g5g_switch(ah, true); 1202 ar9003_mci_2g5g_switch(ah, false);
1303 break; 1203 break;
1304 case MCI_STATE_SET_BT_CAL_START: 1204 case MCI_STATE_SET_BT_CAL_START:
1305 mci->bt_state = MCI_BT_CAL_START; 1205 mci->bt_state = MCI_BT_CAL_START;
@@ -1323,34 +1223,6 @@ u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type, u32 *p_data)
1323 case MCI_STATE_SEND_WLAN_COEX_VERSION: 1223 case MCI_STATE_SEND_WLAN_COEX_VERSION:
1324 ar9003_mci_send_coex_version_response(ah, true); 1224 ar9003_mci_send_coex_version_response(ah, true);
1325 break; 1225 break;
1326 case MCI_STATE_SET_BT_COEX_VERSION:
1327 if (!p_data)
1328 ath_dbg(common, MCI,
1329 "MCI Set BT Coex version with NULL data!!\n");
1330 else {
1331 mci->bt_ver_major = (*p_data >> 8) & 0xff;
1332 mci->bt_ver_minor = (*p_data) & 0xff;
1333 mci->bt_version_known = true;
1334 ath_dbg(common, MCI, "MCI BT version set: %d.%d\n",
1335 mci->bt_ver_major, mci->bt_ver_minor);
1336 }
1337 break;
1338 case MCI_STATE_SEND_WLAN_CHANNELS:
1339 if (p_data) {
1340 if (((mci->wlan_channels[1] & 0xffff0000) ==
1341 (*(p_data + 1) & 0xffff0000)) &&
1342 (mci->wlan_channels[2] == *(p_data + 2)) &&
1343 (mci->wlan_channels[3] == *(p_data + 3)))
1344 break;
1345
1346 mci->wlan_channels[0] = *p_data++;
1347 mci->wlan_channels[1] = *p_data++;
1348 mci->wlan_channels[2] = *p_data++;
1349 mci->wlan_channels[3] = *p_data++;
1350 }
1351 mci->wlan_channels_update = true;
1352 ar9003_mci_send_coex_wlan_channels(ah, true);
1353 break;
1354 case MCI_STATE_SEND_VERSION_QUERY: 1226 case MCI_STATE_SEND_VERSION_QUERY:
1355 ar9003_mci_send_coex_version_query(ah, true); 1227 ar9003_mci_send_coex_version_query(ah, true);
1356 break; 1228 break;
@@ -1358,38 +1230,16 @@ u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type, u32 *p_data)
1358 query_type = MCI_GPM_COEX_QUERY_BT_TOPOLOGY; 1230 query_type = MCI_GPM_COEX_QUERY_BT_TOPOLOGY;
1359 ar9003_mci_send_coex_bt_status_query(ah, true, query_type); 1231 ar9003_mci_send_coex_bt_status_query(ah, true, query_type);
1360 break; 1232 break;
1361 case MCI_STATE_NEED_FLUSH_BT_INFO:
1362 /*
1363 * btcoex_hw.mci.unhalt_bt_gpm means whether it's
1364 * needed to send UNHALT message. It's set whenever
1365 * there's a request to send HALT message.
1366 * mci_halted_bt_gpm means whether HALT message is sent
1367 * out successfully.
1368 *
1369 * Checking (mci_unhalt_bt_gpm == false) instead of
1370 * checking (ah->mci_halted_bt_gpm == false) will make
1371 * sure currently is in UNHALT-ed mode and BT can
1372 * respond to status query.
1373 */
1374 value = (!mci->unhalt_bt_gpm &&
1375 mci->need_flush_btinfo) ? 1 : 0;
1376 if (p_data)
1377 mci->need_flush_btinfo =
1378 (*p_data != 0) ? true : false;
1379 break;
1380 case MCI_STATE_RECOVER_RX: 1233 case MCI_STATE_RECOVER_RX:
1381 ar9003_mci_prep_interface(ah); 1234 ar9003_mci_prep_interface(ah);
1382 mci->query_bt = true; 1235 mci->query_bt = true;
1383 mci->need_flush_btinfo = true; 1236 mci->need_flush_btinfo = true;
1384 ar9003_mci_send_coex_wlan_channels(ah, true); 1237 ar9003_mci_send_coex_wlan_channels(ah, true);
1385 ar9003_mci_2g5g_switch(ah, true); 1238 ar9003_mci_2g5g_switch(ah, false);
1386 break; 1239 break;
1387 case MCI_STATE_NEED_FTP_STOMP: 1240 case MCI_STATE_NEED_FTP_STOMP:
1388 value = !(mci->config & ATH_MCI_CONFIG_DISABLE_FTP_STOMP); 1241 value = !(mci->config & ATH_MCI_CONFIG_DISABLE_FTP_STOMP);
1389 break; 1242 break;
1390 case MCI_STATE_NEED_TUNING:
1391 value = !(mci->config & ATH_MCI_CONFIG_DISABLE_TUNING);
1392 break;
1393 default: 1243 default:
1394 break; 1244 break;
1395 } 1245 }
@@ -1397,3 +1247,173 @@ u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type, u32 *p_data)
1397 return value; 1247 return value;
1398} 1248}
1399EXPORT_SYMBOL(ar9003_mci_state); 1249EXPORT_SYMBOL(ar9003_mci_state);
1250
1251void ar9003_mci_bt_gain_ctrl(struct ath_hw *ah)
1252{
1253 struct ath_common *common = ath9k_hw_common(ah);
1254 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
1255
1256 ath_dbg(common, MCI, "Give LNA and SPDT control to BT\n");
1257
1258 ar9003_mci_send_lna_take(ah, true);
1259 udelay(50);
1260
1261 REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL);
1262 mci->is_2g = false;
1263 mci->update_2g5g = true;
1264 ar9003_mci_send_2g5g_status(ah, true);
1265
1266 /* Force another 2g5g update at next scanning */
1267 mci->update_2g5g = true;
1268}
1269
1270void ar9003_mci_set_power_awake(struct ath_hw *ah)
1271{
1272 u32 btcoex_ctrl2, diag_sw;
1273 int i;
1274 u8 lna_ctrl, bt_sleep;
1275
1276 for (i = 0; i < AH_WAIT_TIMEOUT; i++) {
1277 btcoex_ctrl2 = REG_READ(ah, AR_BTCOEX_CTRL2);
1278 if (btcoex_ctrl2 != 0xdeadbeef)
1279 break;
1280 udelay(AH_TIME_QUANTUM);
1281 }
1282 REG_WRITE(ah, AR_BTCOEX_CTRL2, (btcoex_ctrl2 | BIT(23)));
1283
1284 for (i = 0; i < AH_WAIT_TIMEOUT; i++) {
1285 diag_sw = REG_READ(ah, AR_DIAG_SW);
1286 if (diag_sw != 0xdeadbeef)
1287 break;
1288 udelay(AH_TIME_QUANTUM);
1289 }
1290 REG_WRITE(ah, AR_DIAG_SW, (diag_sw | BIT(27) | BIT(19) | BIT(18)));
1291 lna_ctrl = REG_READ(ah, AR_OBS_BUS_CTRL) & 0x3;
1292 bt_sleep = REG_READ(ah, AR_MCI_RX_STATUS) & AR_MCI_RX_REMOTE_SLEEP;
1293
1294 REG_WRITE(ah, AR_BTCOEX_CTRL2, btcoex_ctrl2);
1295 REG_WRITE(ah, AR_DIAG_SW, diag_sw);
1296
1297 if (bt_sleep && (lna_ctrl == 2)) {
1298 REG_SET_BIT(ah, AR_BTCOEX_RC, 0x1);
1299 REG_CLR_BIT(ah, AR_BTCOEX_RC, 0x1);
1300 udelay(50);
1301 }
1302}
1303
1304void ar9003_mci_check_gpm_offset(struct ath_hw *ah)
1305{
1306 struct ath_common *common = ath9k_hw_common(ah);
1307 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
1308 u32 offset;
1309
1310 /*
1311 * This should only be called before "MAC Warm Reset" or "MCI Reset Rx".
1312 */
1313 offset = MS(REG_READ(ah, AR_MCI_GPM_1), AR_MCI_GPM_WRITE_PTR);
1314 if (mci->gpm_idx == offset)
1315 return;
1316 ath_dbg(common, MCI, "GPM cached write pointer mismatch %d %d\n",
1317 mci->gpm_idx, offset);
1318 mci->query_bt = true;
1319 mci->need_flush_btinfo = true;
1320 mci->gpm_idx = 0;
1321}
1322
1323u32 ar9003_mci_get_next_gpm_offset(struct ath_hw *ah, bool first, u32 *more)
1324{
1325 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
1326 u32 offset, more_gpm = 0, gpm_ptr;
1327
1328 if (first) {
1329 gpm_ptr = MS(REG_READ(ah, AR_MCI_GPM_1), AR_MCI_GPM_WRITE_PTR);
1330 mci->gpm_idx = gpm_ptr;
1331 return gpm_ptr;
1332 }
1333
1334 /*
1335 * This could be useful to avoid new GPM message interrupt which
1336 * may lead to spurious interrupt after power sleep, or multiple
1337 * entry of ath_mci_intr().
1338 * Adding empty GPM check by returning HAL_MCI_GPM_INVALID can
1339 * alleviate this effect, but clearing GPM RX interrupt bit is
1340 * safe, because whether this is called from hw or driver code
1341 * there must be an interrupt bit set/triggered initially
1342 */
1343 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
1344 AR_MCI_INTERRUPT_RX_MSG_GPM);
1345
1346 gpm_ptr = MS(REG_READ(ah, AR_MCI_GPM_1), AR_MCI_GPM_WRITE_PTR);
1347 offset = gpm_ptr;
1348
1349 if (!offset)
1350 offset = mci->gpm_len - 1;
1351 else if (offset >= mci->gpm_len) {
1352 if (offset != 0xFFFF)
1353 offset = 0;
1354 } else {
1355 offset--;
1356 }
1357
1358 if ((offset == 0xFFFF) || (gpm_ptr == mci->gpm_idx)) {
1359 offset = MCI_GPM_INVALID;
1360 more_gpm = MCI_GPM_NOMORE;
1361 goto out;
1362 }
1363 for (;;) {
1364 u32 temp_index;
1365
1366 /* skip reserved GPM if any */
1367
1368 if (offset != mci->gpm_idx)
1369 more_gpm = MCI_GPM_MORE;
1370 else
1371 more_gpm = MCI_GPM_NOMORE;
1372
1373 temp_index = mci->gpm_idx;
1374 mci->gpm_idx++;
1375
1376 if (mci->gpm_idx >= mci->gpm_len)
1377 mci->gpm_idx = 0;
1378
1379 if (ar9003_mci_is_gpm_valid(ah, temp_index)) {
1380 offset = temp_index;
1381 break;
1382 }
1383
1384 if (more_gpm == MCI_GPM_NOMORE) {
1385 offset = MCI_GPM_INVALID;
1386 break;
1387 }
1388 }
1389
1390 if (offset != MCI_GPM_INVALID)
1391 offset <<= 4;
1392out:
1393 if (more)
1394 *more = more_gpm;
1395
1396 return offset;
1397}
1398EXPORT_SYMBOL(ar9003_mci_get_next_gpm_offset);
1399
1400void ar9003_mci_set_bt_version(struct ath_hw *ah, u8 major, u8 minor)
1401{
1402 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
1403
1404 mci->bt_ver_major = major;
1405 mci->bt_ver_minor = minor;
1406 mci->bt_version_known = true;
1407 ath_dbg(ath9k_hw_common(ah), MCI, "MCI BT version set: %d.%d\n",
1408 mci->bt_ver_major, mci->bt_ver_minor);
1409}
1410EXPORT_SYMBOL(ar9003_mci_set_bt_version);
1411
1412void ar9003_mci_send_wlan_channels(struct ath_hw *ah)
1413{
1414 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
1415
1416 mci->wlan_channels_update = true;
1417 ar9003_mci_send_coex_wlan_channels(ah, true);
1418}
1419EXPORT_SYMBOL(ar9003_mci_send_wlan_channels);
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_mci.h b/drivers/net/wireless/ath/ath9k/ar9003_mci.h
index 4842f6c06b8c..d33b8e128855 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_mci.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_mci.h
@@ -189,30 +189,18 @@ enum mci_bt_state {
189/* Type of state query */ 189/* Type of state query */
190enum mci_state_type { 190enum mci_state_type {
191 MCI_STATE_ENABLE, 191 MCI_STATE_ENABLE,
192 MCI_STATE_INIT_GPM_OFFSET,
193 MCI_STATE_NEXT_GPM_OFFSET,
194 MCI_STATE_LAST_GPM_OFFSET,
195 MCI_STATE_BT,
196 MCI_STATE_SET_BT_SLEEP,
197 MCI_STATE_SET_BT_AWAKE, 192 MCI_STATE_SET_BT_AWAKE,
198 MCI_STATE_SET_BT_CAL_START, 193 MCI_STATE_SET_BT_CAL_START,
199 MCI_STATE_SET_BT_CAL, 194 MCI_STATE_SET_BT_CAL,
200 MCI_STATE_LAST_SCHD_MSG_OFFSET, 195 MCI_STATE_LAST_SCHD_MSG_OFFSET,
201 MCI_STATE_REMOTE_SLEEP, 196 MCI_STATE_REMOTE_SLEEP,
202 MCI_STATE_CONT_RSSI_POWER,
203 MCI_STATE_CONT_PRIORITY,
204 MCI_STATE_CONT_TXRX,
205 MCI_STATE_RESET_REQ_WAKE, 197 MCI_STATE_RESET_REQ_WAKE,
206 MCI_STATE_SEND_WLAN_COEX_VERSION, 198 MCI_STATE_SEND_WLAN_COEX_VERSION,
207 MCI_STATE_SET_BT_COEX_VERSION,
208 MCI_STATE_SEND_WLAN_CHANNELS,
209 MCI_STATE_SEND_VERSION_QUERY, 199 MCI_STATE_SEND_VERSION_QUERY,
210 MCI_STATE_SEND_STATUS_QUERY, 200 MCI_STATE_SEND_STATUS_QUERY,
211 MCI_STATE_NEED_FLUSH_BT_INFO,
212 MCI_STATE_SET_CONCUR_TX_PRI, 201 MCI_STATE_SET_CONCUR_TX_PRI,
213 MCI_STATE_RECOVER_RX, 202 MCI_STATE_RECOVER_RX,
214 MCI_STATE_NEED_FTP_STOMP, 203 MCI_STATE_NEED_FTP_STOMP,
215 MCI_STATE_NEED_TUNING,
216 MCI_STATE_DEBUG, 204 MCI_STATE_DEBUG,
217 MCI_STATE_MAX 205 MCI_STATE_MAX
218}; 206};
@@ -260,28 +248,26 @@ enum mci_gpm_coex_opcode {
260bool ar9003_mci_send_message(struct ath_hw *ah, u8 header, u32 flag, 248bool ar9003_mci_send_message(struct ath_hw *ah, u8 header, u32 flag,
261 u32 *payload, u8 len, bool wait_done, 249 u32 *payload, u8 len, bool wait_done,
262 bool check_bt); 250 bool check_bt);
263u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type, u32 *p_data); 251u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type);
264void ar9003_mci_setup(struct ath_hw *ah, u32 gpm_addr, void *gpm_buf, 252void ar9003_mci_setup(struct ath_hw *ah, u32 gpm_addr, void *gpm_buf,
265 u16 len, u32 sched_addr); 253 u16 len, u32 sched_addr);
266void ar9003_mci_cleanup(struct ath_hw *ah); 254void ar9003_mci_cleanup(struct ath_hw *ah);
267void ar9003_mci_get_interrupt(struct ath_hw *ah, u32 *raw_intr, 255void ar9003_mci_get_interrupt(struct ath_hw *ah, u32 *raw_intr,
268 u32 *rx_msg_intr); 256 u32 *rx_msg_intr);
269 257u32 ar9003_mci_get_next_gpm_offset(struct ath_hw *ah, bool first, u32 *more);
258void ar9003_mci_set_bt_version(struct ath_hw *ah, u8 major, u8 minor);
259void ar9003_mci_send_wlan_channels(struct ath_hw *ah);
270/* 260/*
271 * These functions are used by ath9k_hw. 261 * These functions are used by ath9k_hw.
272 */ 262 */
273 263
274#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 264#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
275 265
276static inline bool ar9003_mci_is_ready(struct ath_hw *ah)
277{
278 return ah->btcoex_hw.mci.ready;
279}
280void ar9003_mci_stop_bt(struct ath_hw *ah, bool save_fullsleep); 266void ar9003_mci_stop_bt(struct ath_hw *ah, bool save_fullsleep);
281void ar9003_mci_init_cal_req(struct ath_hw *ah, bool *is_reusable); 267void ar9003_mci_init_cal_req(struct ath_hw *ah, bool *is_reusable);
282void ar9003_mci_init_cal_done(struct ath_hw *ah); 268void ar9003_mci_init_cal_done(struct ath_hw *ah);
283void ar9003_mci_set_full_sleep(struct ath_hw *ah); 269void ar9003_mci_set_full_sleep(struct ath_hw *ah);
284void ar9003_mci_2g5g_switch(struct ath_hw *ah, bool wait_done); 270void ar9003_mci_2g5g_switch(struct ath_hw *ah, bool force);
285void ar9003_mci_check_bt(struct ath_hw *ah); 271void ar9003_mci_check_bt(struct ath_hw *ah);
286bool ar9003_mci_start_reset(struct ath_hw *ah, struct ath9k_channel *chan); 272bool ar9003_mci_start_reset(struct ath_hw *ah, struct ath9k_channel *chan);
287int ar9003_mci_end_reset(struct ath_hw *ah, struct ath9k_channel *chan, 273int ar9003_mci_end_reset(struct ath_hw *ah, struct ath9k_channel *chan,
@@ -289,13 +275,12 @@ int ar9003_mci_end_reset(struct ath_hw *ah, struct ath9k_channel *chan,
289void ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g, 275void ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g,
290 bool is_full_sleep); 276 bool is_full_sleep);
291void ar9003_mci_get_isr(struct ath_hw *ah, enum ath9k_int *masked); 277void ar9003_mci_get_isr(struct ath_hw *ah, enum ath9k_int *masked);
278void ar9003_mci_bt_gain_ctrl(struct ath_hw *ah);
279void ar9003_mci_set_power_awake(struct ath_hw *ah);
280void ar9003_mci_check_gpm_offset(struct ath_hw *ah);
292 281
293#else 282#else
294 283
295static inline bool ar9003_mci_is_ready(struct ath_hw *ah)
296{
297 return false;
298}
299static inline void ar9003_mci_stop_bt(struct ath_hw *ah, bool save_fullsleep) 284static inline void ar9003_mci_stop_bt(struct ath_hw *ah, bool save_fullsleep)
300{ 285{
301} 286}
@@ -330,6 +315,15 @@ static inline void ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g,
330static inline void ar9003_mci_get_isr(struct ath_hw *ah, enum ath9k_int *masked) 315static inline void ar9003_mci_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
331{ 316{
332} 317}
318static inline void ar9003_mci_bt_gain_ctrl(struct ath_hw *ah)
319{
320}
321static inline void ar9003_mci_set_power_awake(struct ath_hw *ah)
322{
323}
324static inline void ar9003_mci_check_gpm_offset(struct ath_hw *ah)
325{
326}
333#endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */ 327#endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
334 328
335#endif 329#endif
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_paprd.c b/drivers/net/wireless/ath/ath9k/ar9003_paprd.c
index 3d400e8d6535..2c9f7d7ed4cc 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_paprd.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_paprd.c
@@ -211,7 +211,7 @@ static int ar9003_paprd_setup_single_table(struct ath_hw *ah)
211 AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES, 7); 211 AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES, 7);
212 REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3, 212 REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
213 AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL, 1); 213 AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL, 1);
214 if (AR_SREV_9485(ah) || AR_SREV_9462(ah)) 214 if (AR_SREV_9485(ah) || AR_SREV_9462(ah) || AR_SREV_9550(ah))
215 REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3, 215 REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
216 AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP, 216 AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP,
217 -3); 217 -3);
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
index 11abb972be1f..d2346dbad6cd 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
@@ -99,7 +99,7 @@ static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
99 channelSel = (freq * 4) / 120; 99 channelSel = (freq * 4) / 120;
100 chan_frac = (((freq * 4) % 120) * 0x20000) / 120; 100 chan_frac = (((freq * 4) % 120) * 0x20000) / 120;
101 channelSel = (channelSel << 17) | chan_frac; 101 channelSel = (channelSel << 17) | chan_frac;
102 } else if (AR_SREV_9340(ah)) { 102 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
103 if (ah->is_clk_25mhz) { 103 if (ah->is_clk_25mhz) {
104 u32 chan_frac; 104 u32 chan_frac;
105 105
@@ -113,7 +113,8 @@ static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
113 /* Set to 2G mode */ 113 /* Set to 2G mode */
114 bMode = 1; 114 bMode = 1;
115 } else { 115 } else {
116 if (AR_SREV_9340(ah) && ah->is_clk_25mhz) { 116 if ((AR_SREV_9340(ah) || AR_SREV_9550(ah)) &&
117 ah->is_clk_25mhz) {
117 u32 chan_frac; 118 u32 chan_frac;
118 119
119 channelSel = (freq * 2) / 75; 120 channelSel = (freq * 2) / 75;
@@ -173,16 +174,15 @@ static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
173 int cur_bb_spur, negative = 0, cck_spur_freq; 174 int cur_bb_spur, negative = 0, cck_spur_freq;
174 int i; 175 int i;
175 int range, max_spur_cnts, synth_freq; 176 int range, max_spur_cnts, synth_freq;
176 u8 *spur_fbin_ptr = NULL; 177 u8 *spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, IS_CHAN_2GHZ(chan));
177 178
178 /* 179 /*
179 * Need to verify range +/- 10 MHz in control channel, otherwise spur 180 * Need to verify range +/- 10 MHz in control channel, otherwise spur
180 * is out-of-band and can be ignored. 181 * is out-of-band and can be ignored.
181 */ 182 */
182 183
183 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah)) { 184 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
184 spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, 185 AR_SREV_9550(ah)) {
185 IS_CHAN_2GHZ(chan));
186 if (spur_fbin_ptr[0] == 0) /* No spur */ 186 if (spur_fbin_ptr[0] == 0) /* No spur */
187 return; 187 return;
188 max_spur_cnts = 5; 188 max_spur_cnts = 5;
@@ -207,7 +207,8 @@ static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
207 if (AR_SREV_9462(ah) && (i == 0 || i == 3)) 207 if (AR_SREV_9462(ah) && (i == 0 || i == 3))
208 continue; 208 continue;
209 negative = 0; 209 negative = 0;
210 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah)) 210 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
211 AR_SREV_9550(ah))
211 cur_bb_spur = ath9k_hw_fbin2freq(spur_fbin_ptr[i], 212 cur_bb_spur = ath9k_hw_fbin2freq(spur_fbin_ptr[i],
212 IS_CHAN_2GHZ(chan)); 213 IS_CHAN_2GHZ(chan));
213 else 214 else
@@ -620,6 +621,50 @@ static void ar9003_hw_prog_ini(struct ath_hw *ah,
620 } 621 }
621} 622}
622 623
624static int ar9550_hw_get_modes_txgain_index(struct ath_hw *ah,
625 struct ath9k_channel *chan)
626{
627 int ret;
628
629 switch (chan->chanmode) {
630 case CHANNEL_A:
631 case CHANNEL_A_HT20:
632 if (chan->channel <= 5350)
633 ret = 1;
634 else if ((chan->channel > 5350) && (chan->channel <= 5600))
635 ret = 3;
636 else
637 ret = 5;
638 break;
639
640 case CHANNEL_A_HT40PLUS:
641 case CHANNEL_A_HT40MINUS:
642 if (chan->channel <= 5350)
643 ret = 2;
644 else if ((chan->channel > 5350) && (chan->channel <= 5600))
645 ret = 4;
646 else
647 ret = 6;
648 break;
649
650 case CHANNEL_G:
651 case CHANNEL_G_HT20:
652 case CHANNEL_B:
653 ret = 8;
654 break;
655
656 case CHANNEL_G_HT40PLUS:
657 case CHANNEL_G_HT40MINUS:
658 ret = 7;
659 break;
660
661 default:
662 ret = -EINVAL;
663 }
664
665 return ret;
666}
667
623static int ar9003_hw_process_ini(struct ath_hw *ah, 668static int ar9003_hw_process_ini(struct ath_hw *ah,
624 struct ath9k_channel *chan) 669 struct ath9k_channel *chan)
625{ 670{
@@ -661,7 +706,22 @@ static int ar9003_hw_process_ini(struct ath_hw *ah,
661 } 706 }
662 707
663 REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites); 708 REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
664 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); 709 if (AR_SREV_9550(ah))
710 REG_WRITE_ARRAY(&ah->ini_modes_rx_gain_bounds, modesIndex,
711 regWrites);
712
713 if (AR_SREV_9550(ah)) {
714 int modes_txgain_index;
715
716 modes_txgain_index = ar9550_hw_get_modes_txgain_index(ah, chan);
717 if (modes_txgain_index < 0)
718 return -EINVAL;
719
720 REG_WRITE_ARRAY(&ah->iniModesTxGain, modes_txgain_index,
721 regWrites);
722 } else {
723 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
724 }
665 725
666 /* 726 /*
667 * For 5GHz channels requiring Fast Clock, apply 727 * For 5GHz channels requiring Fast Clock, apply
@@ -676,6 +736,10 @@ static int ar9003_hw_process_ini(struct ath_hw *ah,
676 if (chan->channel == 2484) 736 if (chan->channel == 2484)
677 ar9003_hw_prog_ini(ah, &ah->ini_japan2484, 1); 737 ar9003_hw_prog_ini(ah, &ah->ini_japan2484, 1);
678 738
739 if (AR_SREV_9462(ah))
740 REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE,
741 AR_GLB_SWREG_DISCONT_EN_BT_WLAN);
742
679 ah->modes_index = modesIndex; 743 ah->modes_index = modesIndex;
680 ar9003_hw_override_ini(ah); 744 ar9003_hw_override_ini(ah);
681 ar9003_hw_set_channel_regs(ah, chan); 745 ar9003_hw_set_channel_regs(ah, chan);
@@ -821,18 +885,18 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
821 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, 885 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
822 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); 886 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
823 887
824 if (!on != aniState->ofdmWeakSigDetectOff) { 888 if (on != aniState->ofdmWeakSigDetect) {
825 ath_dbg(common, ANI, 889 ath_dbg(common, ANI,
826 "** ch %d: ofdm weak signal: %s=>%s\n", 890 "** ch %d: ofdm weak signal: %s=>%s\n",
827 chan->channel, 891 chan->channel,
828 !aniState->ofdmWeakSigDetectOff ? 892 aniState->ofdmWeakSigDetect ?
829 "on" : "off", 893 "on" : "off",
830 on ? "on" : "off"); 894 on ? "on" : "off");
831 if (on) 895 if (on)
832 ah->stats.ast_ani_ofdmon++; 896 ah->stats.ast_ani_ofdmon++;
833 else 897 else
834 ah->stats.ast_ani_ofdmoff++; 898 ah->stats.ast_ani_ofdmoff++;
835 aniState->ofdmWeakSigDetectOff = !on; 899 aniState->ofdmWeakSigDetect = on;
836 } 900 }
837 break; 901 break;
838 } 902 }
@@ -851,7 +915,7 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
851 * from INI file & cap value 915 * from INI file & cap value
852 */ 916 */
853 value = firstep_table[level] - 917 value = firstep_table[level] -
854 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] + 918 firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
855 aniState->iniDef.firstep; 919 aniState->iniDef.firstep;
856 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN) 920 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
857 value = ATH9K_SIG_FIRSTEP_SETTING_MIN; 921 value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
@@ -866,7 +930,7 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
866 * from INI file & cap value 930 * from INI file & cap value
867 */ 931 */
868 value2 = firstep_table[level] - 932 value2 = firstep_table[level] -
869 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] + 933 firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
870 aniState->iniDef.firstepLow; 934 aniState->iniDef.firstepLow;
871 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN) 935 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
872 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN; 936 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
@@ -882,7 +946,7 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
882 chan->channel, 946 chan->channel,
883 aniState->firstepLevel, 947 aniState->firstepLevel,
884 level, 948 level,
885 ATH9K_ANI_FIRSTEP_LVL_NEW, 949 ATH9K_ANI_FIRSTEP_LVL,
886 value, 950 value,
887 aniState->iniDef.firstep); 951 aniState->iniDef.firstep);
888 ath_dbg(common, ANI, 952 ath_dbg(common, ANI,
@@ -890,7 +954,7 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
890 chan->channel, 954 chan->channel,
891 aniState->firstepLevel, 955 aniState->firstepLevel,
892 level, 956 level,
893 ATH9K_ANI_FIRSTEP_LVL_NEW, 957 ATH9K_ANI_FIRSTEP_LVL,
894 value2, 958 value2,
895 aniState->iniDef.firstepLow); 959 aniState->iniDef.firstepLow);
896 if (level > aniState->firstepLevel) 960 if (level > aniState->firstepLevel)
@@ -915,7 +979,7 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
915 * from INI file & cap value 979 * from INI file & cap value
916 */ 980 */
917 value = cycpwrThr1_table[level] - 981 value = cycpwrThr1_table[level] -
918 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] + 982 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
919 aniState->iniDef.cycpwrThr1; 983 aniState->iniDef.cycpwrThr1;
920 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN) 984 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
921 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN; 985 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
@@ -931,7 +995,7 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
931 * from INI file & cap value 995 * from INI file & cap value
932 */ 996 */
933 value2 = cycpwrThr1_table[level] - 997 value2 = cycpwrThr1_table[level] -
934 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] + 998 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
935 aniState->iniDef.cycpwrThr1Ext; 999 aniState->iniDef.cycpwrThr1Ext;
936 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN) 1000 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
937 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN; 1001 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
@@ -946,7 +1010,7 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
946 chan->channel, 1010 chan->channel,
947 aniState->spurImmunityLevel, 1011 aniState->spurImmunityLevel,
948 level, 1012 level,
949 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW, 1013 ATH9K_ANI_SPUR_IMMUNE_LVL,
950 value, 1014 value,
951 aniState->iniDef.cycpwrThr1); 1015 aniState->iniDef.cycpwrThr1);
952 ath_dbg(common, ANI, 1016 ath_dbg(common, ANI,
@@ -954,7 +1018,7 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
954 chan->channel, 1018 chan->channel,
955 aniState->spurImmunityLevel, 1019 aniState->spurImmunityLevel,
956 level, 1020 level,
957 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW, 1021 ATH9K_ANI_SPUR_IMMUNE_LVL,
958 value2, 1022 value2,
959 aniState->iniDef.cycpwrThr1Ext); 1023 aniState->iniDef.cycpwrThr1Ext);
960 if (level > aniState->spurImmunityLevel) 1024 if (level > aniState->spurImmunityLevel)
@@ -975,16 +1039,16 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
975 AR_PHY_MRC_CCK_ENABLE, is_on); 1039 AR_PHY_MRC_CCK_ENABLE, is_on);
976 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL, 1040 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
977 AR_PHY_MRC_CCK_MUX_REG, is_on); 1041 AR_PHY_MRC_CCK_MUX_REG, is_on);
978 if (!is_on != aniState->mrcCCKOff) { 1042 if (is_on != aniState->mrcCCK) {
979 ath_dbg(common, ANI, "** ch %d: MRC CCK: %s=>%s\n", 1043 ath_dbg(common, ANI, "** ch %d: MRC CCK: %s=>%s\n",
980 chan->channel, 1044 chan->channel,
981 !aniState->mrcCCKOff ? "on" : "off", 1045 aniState->mrcCCK ? "on" : "off",
982 is_on ? "on" : "off"); 1046 is_on ? "on" : "off");
983 if (is_on) 1047 if (is_on)
984 ah->stats.ast_ani_ccklow++; 1048 ah->stats.ast_ani_ccklow++;
985 else 1049 else
986 ah->stats.ast_ani_cckhigh++; 1050 ah->stats.ast_ani_cckhigh++;
987 aniState->mrcCCKOff = !is_on; 1051 aniState->mrcCCK = is_on;
988 } 1052 }
989 break; 1053 break;
990 } 1054 }
@@ -998,9 +1062,9 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
998 ath_dbg(common, ANI, 1062 ath_dbg(common, ANI,
999 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n", 1063 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1000 aniState->spurImmunityLevel, 1064 aniState->spurImmunityLevel,
1001 !aniState->ofdmWeakSigDetectOff ? "on" : "off", 1065 aniState->ofdmWeakSigDetect ? "on" : "off",
1002 aniState->firstepLevel, 1066 aniState->firstepLevel,
1003 !aniState->mrcCCKOff ? "on" : "off", 1067 aniState->mrcCCK ? "on" : "off",
1004 aniState->listenTime, 1068 aniState->listenTime,
1005 aniState->ofdmPhyErrCount, 1069 aniState->ofdmPhyErrCount,
1006 aniState->cckPhyErrCount); 1070 aniState->cckPhyErrCount);
@@ -1107,10 +1171,10 @@ static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
1107 AR_PHY_EXT_CYCPWR_THR1); 1171 AR_PHY_EXT_CYCPWR_THR1);
1108 1172
1109 /* these levels just got reset to defaults by the INI */ 1173 /* these levels just got reset to defaults by the INI */
1110 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL_NEW; 1174 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
1111 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW; 1175 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
1112 aniState->ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG; 1176 aniState->ofdmWeakSigDetect = ATH9K_ANI_USE_OFDM_WEAK_SIG;
1113 aniState->mrcCCKOff = !ATH9K_ANI_ENABLE_MRC_CCK; 1177 aniState->mrcCCK = true;
1114} 1178}
1115 1179
1116static void ar9003_hw_set_radar_params(struct ath_hw *ah, 1180static void ar9003_hw_set_radar_params(struct ath_hw *ah,
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.h b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
index 7268a48a92a1..751c83b21493 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
@@ -636,8 +636,8 @@
636 636
637#define AR_CH0_TOP (AR_SREV_9300(ah) ? 0x16288 : \ 637#define AR_CH0_TOP (AR_SREV_9300(ah) ? 0x16288 : \
638 ((AR_SREV_9462(ah) ? 0x1628c : 0x16280))) 638 ((AR_SREV_9462(ah) ? 0x1628c : 0x16280)))
639#define AR_CH0_TOP_XPABIASLVL (0x300) 639#define AR_CH0_TOP_XPABIASLVL (AR_SREV_9550(ah) ? 0x3c0 : 0x300)
640#define AR_CH0_TOP_XPABIASLVL_S (8) 640#define AR_CH0_TOP_XPABIASLVL_S (AR_SREV_9550(ah) ? 6 : 8)
641 641
642#define AR_CH0_THERM (AR_SREV_9300(ah) ? 0x16290 : \ 642#define AR_CH0_THERM (AR_SREV_9300(ah) ? 0x16290 : \
643 ((AR_SREV_9485(ah) ? 0x1628c : 0x16294))) 643 ((AR_SREV_9485(ah) ? 0x1628c : 0x16294)))
@@ -650,6 +650,8 @@
650#define AR_SWITCH_TABLE_COM_ALL_S (0) 650#define AR_SWITCH_TABLE_COM_ALL_S (0)
651#define AR_SWITCH_TABLE_COM_AR9462_ALL (0xffffff) 651#define AR_SWITCH_TABLE_COM_AR9462_ALL (0xffffff)
652#define AR_SWITCH_TABLE_COM_AR9462_ALL_S (0) 652#define AR_SWITCH_TABLE_COM_AR9462_ALL_S (0)
653#define AR_SWITCH_TABLE_COM_AR9550_ALL (0xffffff)
654#define AR_SWITCH_TABLE_COM_AR9550_ALL_S (0)
653#define AR_SWITCH_TABLE_COM_SPDT (0x00f00000) 655#define AR_SWITCH_TABLE_COM_SPDT (0x00f00000)
654#define AR_SWITCH_TABLE_COM_SPDT_ALL (0x0000fff0) 656#define AR_SWITCH_TABLE_COM_SPDT_ALL (0x0000fff0)
655#define AR_SWITCH_TABLE_COM_SPDT_ALL_S (4) 657#define AR_SWITCH_TABLE_COM_SPDT_ALL_S (4)
@@ -820,18 +822,26 @@
820#define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001 822#define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001
821#define AR_PHY_RX_DELAY_DELAY 0x00003FFF 823#define AR_PHY_RX_DELAY_DELAY 0x00003FFF
822#define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010 824#define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010
823#define AR_PHY_SPECTRAL_SCAN_ENABLE 0x00000001 825
824#define AR_PHY_SPECTRAL_SCAN_ENABLE_S 0 826#define AR_PHY_SPECTRAL_SCAN_ENABLE 0x00000001
825#define AR_PHY_SPECTRAL_SCAN_ACTIVE 0x00000002 827#define AR_PHY_SPECTRAL_SCAN_ENABLE_S 0
826#define AR_PHY_SPECTRAL_SCAN_ACTIVE_S 1 828#define AR_PHY_SPECTRAL_SCAN_ACTIVE 0x00000002
827#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD 0x000000F0 829#define AR_PHY_SPECTRAL_SCAN_ACTIVE_S 1
828#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S 4 830#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD 0x000000F0
829#define AR_PHY_SPECTRAL_SCAN_PERIOD 0x0000FF00 831#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S 4
830#define AR_PHY_SPECTRAL_SCAN_PERIOD_S 8 832#define AR_PHY_SPECTRAL_SCAN_PERIOD 0x0000FF00
831#define AR_PHY_SPECTRAL_SCAN_COUNT 0x00FF0000 833#define AR_PHY_SPECTRAL_SCAN_PERIOD_S 8
832#define AR_PHY_SPECTRAL_SCAN_COUNT_S 16 834#define AR_PHY_SPECTRAL_SCAN_COUNT 0x0FFF0000
833#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x01000000 835#define AR_PHY_SPECTRAL_SCAN_COUNT_S 16
834#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 24 836#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x10000000
837#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 28
838#define AR_PHY_SPECTRAL_SCAN_PRIORITY 0x20000000
839#define AR_PHY_SPECTRAL_SCAN_PRIORITY_S 29
840#define AR_PHY_SPECTRAL_SCAN_USE_ERR5 0x40000000
841#define AR_PHY_SPECTRAL_SCAN_USE_ERR5_S 30
842#define AR_PHY_SPECTRAL_SCAN_COMPRESSED_RPT 0x80000000
843#define AR_PHY_SPECTRAL_SCAN_COMPRESSED_RPT_S 31
844
835#define AR_PHY_CHANNEL_STATUS_RX_CLEAR 0x00000004 845#define AR_PHY_CHANNEL_STATUS_RX_CLEAR 0x00000004
836#define AR_PHY_RTT_CTRL_ENA_RADIO_RETENTION 0x00000001 846#define AR_PHY_RTT_CTRL_ENA_RADIO_RETENTION 0x00000001
837#define AR_PHY_RTT_CTRL_ENA_RADIO_RETENTION_S 0 847#define AR_PHY_RTT_CTRL_ENA_RADIO_RETENTION_S 0
diff --git a/drivers/net/wireless/ath/ath9k/ar9330_1p1_initvals.h b/drivers/net/wireless/ath/ath9k/ar9330_1p1_initvals.h
index 1bd3a3d22101..6e1756bc3833 100644
--- a/drivers/net/wireless/ath/ath9k/ar9330_1p1_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9330_1p1_initvals.h
@@ -337,12 +337,7 @@ static const u32 ar9331_modes_low_ob_db_tx_gain_1p1[][5] = {
337 {0x00016284, 0x14d3f000, 0x14d3f000, 0x14d3f000, 0x14d3f000}, 337 {0x00016284, 0x14d3f000, 0x14d3f000, 0x14d3f000, 0x14d3f000},
338}; 338};
339 339
340static const u32 ar9331_1p1_baseband_core_txfir_coeff_japan_2484[][2] = { 340#define ar9331_1p1_baseband_core_txfir_coeff_japan_2484 ar9462_2p0_baseband_core_txfir_coeff_japan_2484
341 /* Addr allmodes */
342 {0x0000a398, 0x00000000},
343 {0x0000a39c, 0x6f7f0301},
344 {0x0000a3a0, 0xca9228ee},
345};
346 341
347static const u32 ar9331_1p1_xtal_25M[][2] = { 342static const u32 ar9331_1p1_xtal_25M[][2] = {
348 /* Addr allmodes */ 343 /* Addr allmodes */
@@ -783,17 +778,7 @@ static const u32 ar9331_modes_high_power_tx_gain_1p1[][5] = {
783 {0x00016284, 0x14d3f000, 0x14d3f000, 0x14d3f000, 0x14d3f000}, 778 {0x00016284, 0x14d3f000, 0x14d3f000, 0x14d3f000, 0x14d3f000},
784}; 779};
785 780
786static const u32 ar9331_1p1_mac_postamble[][5] = { 781#define ar9331_1p1_mac_postamble ar9300_2p2_mac_postamble
787 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
788 {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
789 {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
790 {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
791 {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
792 {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
793 {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
794 {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
795 {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
796};
797 782
798static const u32 ar9331_1p1_soc_preamble[][2] = { 783static const u32 ar9331_1p1_soc_preamble[][2] = {
799 /* Addr allmodes */ 784 /* Addr allmodes */
@@ -1112,38 +1097,4 @@ static const u32 ar9331_common_tx_gain_offset1_1[][1] = {
1112 {0x00000000}, 1097 {0x00000000},
1113}; 1098};
1114 1099
1115static const u32 ar9331_1p1_chansel_xtal_25M[] = {
1116 0x0101479e,
1117 0x0101d027,
1118 0x010258af,
1119 0x0102e138,
1120 0x010369c0,
1121 0x0103f249,
1122 0x01047ad1,
1123 0x0105035a,
1124 0x01058be2,
1125 0x0106146b,
1126 0x01069cf3,
1127 0x0107257c,
1128 0x0107ae04,
1129 0x0108f5b2,
1130};
1131
1132static const u32 ar9331_1p1_chansel_xtal_40M[] = {
1133 0x00a0ccbe,
1134 0x00a12213,
1135 0x00a17769,
1136 0x00a1ccbe,
1137 0x00a22213,
1138 0x00a27769,
1139 0x00a2ccbe,
1140 0x00a32213,
1141 0x00a37769,
1142 0x00a3ccbe,
1143 0x00a42213,
1144 0x00a47769,
1145 0x00a4ccbe,
1146 0x00a5998b,
1147};
1148
1149#endif /* INITVALS_9330_1P1_H */ 1100#endif /* INITVALS_9330_1P1_H */
diff --git a/drivers/net/wireless/ath/ath9k/ar9330_1p2_initvals.h b/drivers/net/wireless/ath/ath9k/ar9330_1p2_initvals.h
index 0e6ca0834b34..57ed8a112173 100644
--- a/drivers/net/wireless/ath/ath9k/ar9330_1p2_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9330_1p2_initvals.h
@@ -1,5 +1,6 @@
1/* 1/*
2 * Copyright (c) 2011 Atheros Communications Inc. 2 * Copyright (c) 2010-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2012 Qualcomm Atheros Inc.
3 * 4 *
4 * Permission to use, copy, modify, and/or distribute this software for any 5 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above 6 * purpose with or without fee is hereby granted, provided that the above
@@ -17,8 +18,8 @@
17#ifndef INITVALS_9330_1P2_H 18#ifndef INITVALS_9330_1P2_H
18#define INITVALS_9330_1P2_H 19#define INITVALS_9330_1P2_H
19 20
20static const u32 ar9331_modes_lowest_ob_db_tx_gain_1p2[][5] = { 21static const u32 ar9331_modes_high_ob_db_tx_gain_1p2[][5] = {
21 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 22 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
22 {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d7, 0x000050d7}, 23 {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d7, 0x000050d7},
23 {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000}, 24 {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
24 {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002}, 25 {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
@@ -102,8 +103,14 @@ static const u32 ar9331_modes_lowest_ob_db_tx_gain_1p2[][5] = {
102 {0x0000a63c, 0x04011004, 0x04011004, 0x04011004, 0x04011004}, 103 {0x0000a63c, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
103}; 104};
104 105
106#define ar9331_modes_high_power_tx_gain_1p2 ar9331_modes_high_ob_db_tx_gain_1p2
107
108#define ar9331_modes_low_ob_db_tx_gain_1p2 ar9331_modes_high_power_tx_gain_1p2
109
110#define ar9331_modes_lowest_ob_db_tx_gain_1p2 ar9331_modes_low_ob_db_tx_gain_1p2
111
105static const u32 ar9331_1p2_baseband_postamble[][5] = { 112static const u32 ar9331_1p2_baseband_postamble[][5] = {
106 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 113 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
107 {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005}, 114 {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005},
108 {0x00009820, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e}, 115 {0x00009820, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e},
109 {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0}, 116 {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
@@ -147,191 +154,6 @@ static const u32 ar9331_1p2_baseband_postamble[][5] = {
147 {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 154 {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
148}; 155};
149 156
150static const u32 ar9331_modes_high_ob_db_tx_gain_1p2[][5] = {
151 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
152 {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d7, 0x000050d7},
153 {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
154 {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
155 {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
156 {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
157 {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
158 {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
159 {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
160 {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
161 {0x0000a520, 0x2f001f04, 0x2f001f04, 0x23000a00, 0x23000a00},
162 {0x0000a524, 0x35001fc4, 0x35001fc4, 0x27000a02, 0x27000a02},
163 {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2b000a04, 0x2b000a04},
164 {0x0000a52c, 0x41023e85, 0x41023e85, 0x3f001620, 0x3f001620},
165 {0x0000a530, 0x48023ec6, 0x48023ec6, 0x41001621, 0x41001621},
166 {0x0000a534, 0x4d023f01, 0x4d023f01, 0x44001640, 0x44001640},
167 {0x0000a538, 0x53023f4b, 0x53023f4b, 0x46001641, 0x46001641},
168 {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x48001642, 0x48001642},
169 {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x4b001644, 0x4b001644},
170 {0x0000a544, 0x6502feca, 0x6502feca, 0x4e001a81, 0x4e001a81},
171 {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x51001a83, 0x51001a83},
172 {0x0000a54c, 0x7203feca, 0x7203feca, 0x54001c84, 0x54001c84},
173 {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x57001ce3, 0x57001ce3},
174 {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x5b001ce5, 0x5b001ce5},
175 {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x5f001ce9, 0x5f001ce9},
176 {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x66001eec, 0x66001eec},
177 {0x0000a560, 0x900fff0b, 0x900fff0b, 0x66001eec, 0x66001eec},
178 {0x0000a564, 0x960fffcb, 0x960fffcb, 0x66001eec, 0x66001eec},
179 {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
180 {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
181 {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
182 {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
183 {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
184 {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
185 {0x0000a580, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
186 {0x0000a584, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
187 {0x0000a588, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
188 {0x0000a58c, 0x11062202, 0x11062202, 0x0b000200, 0x0b000200},
189 {0x0000a590, 0x17022e00, 0x17022e00, 0x0f000202, 0x0f000202},
190 {0x0000a594, 0x1d000ec2, 0x1d000ec2, 0x11000400, 0x11000400},
191 {0x0000a598, 0x25020ec0, 0x25020ec0, 0x15000402, 0x15000402},
192 {0x0000a59c, 0x2b020ec3, 0x2b020ec3, 0x19000404, 0x19000404},
193 {0x0000a5a0, 0x2f001f04, 0x2f001f04, 0x1b000603, 0x1b000603},
194 {0x0000a5a4, 0x35001fc4, 0x35001fc4, 0x1f000a02, 0x1f000a02},
195 {0x0000a5a8, 0x3c022f04, 0x3c022f04, 0x23000a04, 0x23000a04},
196 {0x0000a5ac, 0x41023e85, 0x41023e85, 0x26000a20, 0x26000a20},
197 {0x0000a5b0, 0x48023ec6, 0x48023ec6, 0x2a000e20, 0x2a000e20},
198 {0x0000a5b4, 0x4d023f01, 0x4d023f01, 0x2e000e22, 0x2e000e22},
199 {0x0000a5b8, 0x53023f4b, 0x53023f4b, 0x31000e24, 0x31000e24},
200 {0x0000a5bc, 0x5a027f09, 0x5a027f09, 0x34001640, 0x34001640},
201 {0x0000a5c0, 0x5f027fc9, 0x5f027fc9, 0x38001660, 0x38001660},
202 {0x0000a5c4, 0x6502feca, 0x6502feca, 0x3b001861, 0x3b001861},
203 {0x0000a5c8, 0x6b02ff4a, 0x6b02ff4a, 0x3e001a81, 0x3e001a81},
204 {0x0000a5cc, 0x7203feca, 0x7203feca, 0x42001a83, 0x42001a83},
205 {0x0000a5d0, 0x7703ff0b, 0x7703ff0b, 0x44001c84, 0x44001c84},
206 {0x0000a5d4, 0x7d06ffcb, 0x7d06ffcb, 0x48001ce3, 0x48001ce3},
207 {0x0000a5d8, 0x8407ff0b, 0x8407ff0b, 0x4c001ce5, 0x4c001ce5},
208 {0x0000a5dc, 0x8907ffcb, 0x8907ffcb, 0x50001ce9, 0x50001ce9},
209 {0x0000a5e0, 0x900fff0b, 0x900fff0b, 0x54001ceb, 0x54001ceb},
210 {0x0000a5e4, 0x960fffcb, 0x960fffcb, 0x56001eec, 0x56001eec},
211 {0x0000a5e8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
212 {0x0000a5ec, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
213 {0x0000a5f0, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
214 {0x0000a5f4, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
215 {0x0000a5f8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
216 {0x0000a5fc, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
217 {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
218 {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
219 {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
220 {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
221 {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
222 {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
223 {0x0000a618, 0x02008501, 0x02008501, 0x02008501, 0x02008501},
224 {0x0000a61c, 0x02008802, 0x02008802, 0x02008802, 0x02008802},
225 {0x0000a620, 0x0300c802, 0x0300c802, 0x0300c802, 0x0300c802},
226 {0x0000a624, 0x0300cc03, 0x0300cc03, 0x0300cc03, 0x0300cc03},
227 {0x0000a628, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
228 {0x0000a62c, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
229 {0x0000a630, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
230 {0x0000a634, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
231 {0x0000a638, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
232 {0x0000a63c, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
233};
234
235static const u32 ar9331_modes_low_ob_db_tx_gain_1p2[][5] = {
236 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
237 {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d7, 0x000050d7},
238 {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
239 {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
240 {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
241 {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
242 {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
243 {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
244 {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
245 {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
246 {0x0000a520, 0x2f001f04, 0x2f001f04, 0x23000a00, 0x23000a00},
247 {0x0000a524, 0x35001fc4, 0x35001fc4, 0x27000a02, 0x27000a02},
248 {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2b000a04, 0x2b000a04},
249 {0x0000a52c, 0x41023e85, 0x41023e85, 0x3f001620, 0x3f001620},
250 {0x0000a530, 0x48023ec6, 0x48023ec6, 0x41001621, 0x41001621},
251 {0x0000a534, 0x4d023f01, 0x4d023f01, 0x44001640, 0x44001640},
252 {0x0000a538, 0x53023f4b, 0x53023f4b, 0x46001641, 0x46001641},
253 {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x48001642, 0x48001642},
254 {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x4b001644, 0x4b001644},
255 {0x0000a544, 0x6502feca, 0x6502feca, 0x4e001a81, 0x4e001a81},
256 {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x51001a83, 0x51001a83},
257 {0x0000a54c, 0x7203feca, 0x7203feca, 0x54001c84, 0x54001c84},
258 {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x57001ce3, 0x57001ce3},
259 {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x5b001ce5, 0x5b001ce5},
260 {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x5f001ce9, 0x5f001ce9},
261 {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x66001eec, 0x66001eec},
262 {0x0000a560, 0x900fff0b, 0x900fff0b, 0x66001eec, 0x66001eec},
263 {0x0000a564, 0x960fffcb, 0x960fffcb, 0x66001eec, 0x66001eec},
264 {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
265 {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
266 {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
267 {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
268 {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
269 {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
270 {0x0000a580, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
271 {0x0000a584, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
272 {0x0000a588, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
273 {0x0000a58c, 0x11062202, 0x11062202, 0x0b000200, 0x0b000200},
274 {0x0000a590, 0x17022e00, 0x17022e00, 0x0f000202, 0x0f000202},
275 {0x0000a594, 0x1d000ec2, 0x1d000ec2, 0x11000400, 0x11000400},
276 {0x0000a598, 0x25020ec0, 0x25020ec0, 0x15000402, 0x15000402},
277 {0x0000a59c, 0x2b020ec3, 0x2b020ec3, 0x19000404, 0x19000404},
278 {0x0000a5a0, 0x2f001f04, 0x2f001f04, 0x1b000603, 0x1b000603},
279 {0x0000a5a4, 0x35001fc4, 0x35001fc4, 0x1f000a02, 0x1f000a02},
280 {0x0000a5a8, 0x3c022f04, 0x3c022f04, 0x23000a04, 0x23000a04},
281 {0x0000a5ac, 0x41023e85, 0x41023e85, 0x26000a20, 0x26000a20},
282 {0x0000a5b0, 0x48023ec6, 0x48023ec6, 0x2a000e20, 0x2a000e20},
283 {0x0000a5b4, 0x4d023f01, 0x4d023f01, 0x2e000e22, 0x2e000e22},
284 {0x0000a5b8, 0x53023f4b, 0x53023f4b, 0x31000e24, 0x31000e24},
285 {0x0000a5bc, 0x5a027f09, 0x5a027f09, 0x34001640, 0x34001640},
286 {0x0000a5c0, 0x5f027fc9, 0x5f027fc9, 0x38001660, 0x38001660},
287 {0x0000a5c4, 0x6502feca, 0x6502feca, 0x3b001861, 0x3b001861},
288 {0x0000a5c8, 0x6b02ff4a, 0x6b02ff4a, 0x3e001a81, 0x3e001a81},
289 {0x0000a5cc, 0x7203feca, 0x7203feca, 0x42001a83, 0x42001a83},
290 {0x0000a5d0, 0x7703ff0b, 0x7703ff0b, 0x44001c84, 0x44001c84},
291 {0x0000a5d4, 0x7d06ffcb, 0x7d06ffcb, 0x48001ce3, 0x48001ce3},
292 {0x0000a5d8, 0x8407ff0b, 0x8407ff0b, 0x4c001ce5, 0x4c001ce5},
293 {0x0000a5dc, 0x8907ffcb, 0x8907ffcb, 0x50001ce9, 0x50001ce9},
294 {0x0000a5e0, 0x900fff0b, 0x900fff0b, 0x54001ceb, 0x54001ceb},
295 {0x0000a5e4, 0x960fffcb, 0x960fffcb, 0x56001eec, 0x56001eec},
296 {0x0000a5e8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
297 {0x0000a5ec, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
298 {0x0000a5f0, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
299 {0x0000a5f4, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
300 {0x0000a5f8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
301 {0x0000a5fc, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
302 {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
303 {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
304 {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
305 {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
306 {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
307 {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
308 {0x0000a618, 0x02008501, 0x02008501, 0x02008501, 0x02008501},
309 {0x0000a61c, 0x02008802, 0x02008802, 0x02008802, 0x02008802},
310 {0x0000a620, 0x0300c802, 0x0300c802, 0x0300c802, 0x0300c802},
311 {0x0000a624, 0x0300cc03, 0x0300cc03, 0x0300cc03, 0x0300cc03},
312 {0x0000a628, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
313 {0x0000a62c, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
314 {0x0000a630, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
315 {0x0000a634, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
316 {0x0000a638, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
317 {0x0000a63c, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
318};
319
320static const u32 ar9331_1p2_baseband_core_txfir_coeff_japan_2484[][2] = {
321 /* Addr allmodes */
322 {0x0000a398, 0x00000000},
323 {0x0000a39c, 0x6f7f0301},
324 {0x0000a3a0, 0xca9228ee},
325};
326
327static const u32 ar9331_1p2_xtal_25M[][2] = {
328 /* Addr allmodes */
329 {0x00007038, 0x000002f8},
330 {0x00008244, 0x0010f3d7},
331 {0x0000824c, 0x0001e7ae},
332 {0x0001609c, 0x0f508f29},
333};
334
335static const u32 ar9331_1p2_radio_core[][2] = { 157static const u32 ar9331_1p2_radio_core[][2] = {
336 /* Addr allmodes */ 158 /* Addr allmodes */
337 {0x00016000, 0x36db6db6}, 159 {0x00016000, 0x36db6db6},
@@ -397,684 +219,24 @@ static const u32 ar9331_1p2_radio_core[][2] = {
397 {0x000163d4, 0x00000000}, 219 {0x000163d4, 0x00000000},
398}; 220};
399 221
400static const u32 ar9331_1p2_soc_postamble[][5] = { 222#define ar9331_1p2_baseband_core_txfir_coeff_japan_2484 ar9331_1p1_baseband_core_txfir_coeff_japan_2484
401 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
402 {0x00007010, 0x00000022, 0x00000022, 0x00000022, 0x00000022},
403};
404 223
405static const u32 ar9331_common_wo_xlna_rx_gain_1p2[][2] = { 224#define ar9331_1p2_xtal_25M ar9331_1p1_xtal_25M
406 /* Addr allmodes */
407 {0x0000a000, 0x00060005},
408 {0x0000a004, 0x00810080},
409 {0x0000a008, 0x00830082},
410 {0x0000a00c, 0x00850084},
411 {0x0000a010, 0x01820181},
412 {0x0000a014, 0x01840183},
413 {0x0000a018, 0x01880185},
414 {0x0000a01c, 0x018a0189},
415 {0x0000a020, 0x02850284},
416 {0x0000a024, 0x02890288},
417 {0x0000a028, 0x028b028a},
418 {0x0000a02c, 0x03850384},
419 {0x0000a030, 0x03890388},
420 {0x0000a034, 0x038b038a},
421 {0x0000a038, 0x038d038c},
422 {0x0000a03c, 0x03910390},
423 {0x0000a040, 0x03930392},
424 {0x0000a044, 0x03950394},
425 {0x0000a048, 0x00000396},
426 {0x0000a04c, 0x00000000},
427 {0x0000a050, 0x00000000},
428 {0x0000a054, 0x00000000},
429 {0x0000a058, 0x00000000},
430 {0x0000a05c, 0x00000000},
431 {0x0000a060, 0x00000000},
432 {0x0000a064, 0x00000000},
433 {0x0000a068, 0x00000000},
434 {0x0000a06c, 0x00000000},
435 {0x0000a070, 0x00000000},
436 {0x0000a074, 0x00000000},
437 {0x0000a078, 0x00000000},
438 {0x0000a07c, 0x00000000},
439 {0x0000a080, 0x28282828},
440 {0x0000a084, 0x28282828},
441 {0x0000a088, 0x28282828},
442 {0x0000a08c, 0x28282828},
443 {0x0000a090, 0x28282828},
444 {0x0000a094, 0x24242428},
445 {0x0000a098, 0x171e1e1e},
446 {0x0000a09c, 0x02020b0b},
447 {0x0000a0a0, 0x02020202},
448 {0x0000a0a4, 0x00000000},
449 {0x0000a0a8, 0x00000000},
450 {0x0000a0ac, 0x00000000},
451 {0x0000a0b0, 0x00000000},
452 {0x0000a0b4, 0x00000000},
453 {0x0000a0b8, 0x00000000},
454 {0x0000a0bc, 0x00000000},
455 {0x0000a0c0, 0x22072208},
456 {0x0000a0c4, 0x22052206},
457 {0x0000a0c8, 0x22032204},
458 {0x0000a0cc, 0x22012202},
459 {0x0000a0d0, 0x221f2200},
460 {0x0000a0d4, 0x221d221e},
461 {0x0000a0d8, 0x33023303},
462 {0x0000a0dc, 0x33003301},
463 {0x0000a0e0, 0x331e331f},
464 {0x0000a0e4, 0x4402331d},
465 {0x0000a0e8, 0x44004401},
466 {0x0000a0ec, 0x441e441f},
467 {0x0000a0f0, 0x55025503},
468 {0x0000a0f4, 0x55005501},
469 {0x0000a0f8, 0x551e551f},
470 {0x0000a0fc, 0x6602551d},
471 {0x0000a100, 0x66006601},
472 {0x0000a104, 0x661e661f},
473 {0x0000a108, 0x7703661d},
474 {0x0000a10c, 0x77017702},
475 {0x0000a110, 0x00007700},
476 {0x0000a114, 0x00000000},
477 {0x0000a118, 0x00000000},
478 {0x0000a11c, 0x00000000},
479 {0x0000a120, 0x00000000},
480 {0x0000a124, 0x00000000},
481 {0x0000a128, 0x00000000},
482 {0x0000a12c, 0x00000000},
483 {0x0000a130, 0x00000000},
484 {0x0000a134, 0x00000000},
485 {0x0000a138, 0x00000000},
486 {0x0000a13c, 0x00000000},
487 {0x0000a140, 0x001f0000},
488 {0x0000a144, 0x111f1100},
489 {0x0000a148, 0x111d111e},
490 {0x0000a14c, 0x111b111c},
491 {0x0000a150, 0x22032204},
492 {0x0000a154, 0x22012202},
493 {0x0000a158, 0x221f2200},
494 {0x0000a15c, 0x221d221e},
495 {0x0000a160, 0x33013302},
496 {0x0000a164, 0x331f3300},
497 {0x0000a168, 0x4402331e},
498 {0x0000a16c, 0x44004401},
499 {0x0000a170, 0x441e441f},
500 {0x0000a174, 0x55015502},
501 {0x0000a178, 0x551f5500},
502 {0x0000a17c, 0x6602551e},
503 {0x0000a180, 0x66006601},
504 {0x0000a184, 0x661e661f},
505 {0x0000a188, 0x7703661d},
506 {0x0000a18c, 0x77017702},
507 {0x0000a190, 0x00007700},
508 {0x0000a194, 0x00000000},
509 {0x0000a198, 0x00000000},
510 {0x0000a19c, 0x00000000},
511 {0x0000a1a0, 0x00000000},
512 {0x0000a1a4, 0x00000000},
513 {0x0000a1a8, 0x00000000},
514 {0x0000a1ac, 0x00000000},
515 {0x0000a1b0, 0x00000000},
516 {0x0000a1b4, 0x00000000},
517 {0x0000a1b8, 0x00000000},
518 {0x0000a1bc, 0x00000000},
519 {0x0000a1c0, 0x00000000},
520 {0x0000a1c4, 0x00000000},
521 {0x0000a1c8, 0x00000000},
522 {0x0000a1cc, 0x00000000},
523 {0x0000a1d0, 0x00000000},
524 {0x0000a1d4, 0x00000000},
525 {0x0000a1d8, 0x00000000},
526 {0x0000a1dc, 0x00000000},
527 {0x0000a1e0, 0x00000000},
528 {0x0000a1e4, 0x00000000},
529 {0x0000a1e8, 0x00000000},
530 {0x0000a1ec, 0x00000000},
531 {0x0000a1f0, 0x00000396},
532 {0x0000a1f4, 0x00000396},
533 {0x0000a1f8, 0x00000396},
534 {0x0000a1fc, 0x00000296},
535};
536 225
537static const u32 ar9331_1p2_baseband_core[][2] = { 226#define ar9331_1p2_xtal_40M ar9331_1p1_xtal_40M
538 /* Addr allmodes */
539 {0x00009800, 0xafe68e30},
540 {0x00009804, 0xfd14e000},
541 {0x00009808, 0x9c0a8f6b},
542 {0x0000980c, 0x04800000},
543 {0x00009814, 0x9280c00a},
544 {0x00009818, 0x00000000},
545 {0x0000981c, 0x00020028},
546 {0x00009834, 0x5f3ca3de},
547 {0x00009838, 0x0108ecff},
548 {0x0000983c, 0x14750600},
549 {0x00009880, 0x201fff00},
550 {0x00009884, 0x00001042},
551 {0x000098a4, 0x00200400},
552 {0x000098b0, 0x32840bbe},
553 {0x000098d0, 0x004b6a8e},
554 {0x000098d4, 0x00000820},
555 {0x000098dc, 0x00000000},
556 {0x000098f0, 0x00000000},
557 {0x000098f4, 0x00000000},
558 {0x00009c04, 0x00000000},
559 {0x00009c08, 0x03200000},
560 {0x00009c0c, 0x00000000},
561 {0x00009c10, 0x00000000},
562 {0x00009c14, 0x00046384},
563 {0x00009c18, 0x05b6b440},
564 {0x00009c1c, 0x00b6b440},
565 {0x00009d00, 0xc080a333},
566 {0x00009d04, 0x40206c10},
567 {0x00009d08, 0x009c4060},
568 {0x00009d0c, 0x1883800a},
569 {0x00009d10, 0x01834061},
570 {0x00009d14, 0x00c00400},
571 {0x00009d18, 0x00000000},
572 {0x00009e08, 0x0038233c},
573 {0x00009e24, 0x9927b515},
574 {0x00009e28, 0x12ef0200},
575 {0x00009e30, 0x06336f77},
576 {0x00009e34, 0x6af6532f},
577 {0x00009e38, 0x0cc80c00},
578 {0x00009e40, 0x0d261820},
579 {0x00009e4c, 0x00001004},
580 {0x00009e50, 0x00ff03f1},
581 {0x00009fc0, 0x803e4788},
582 {0x00009fc4, 0x0001efb5},
583 {0x00009fcc, 0x40000014},
584 {0x0000a20c, 0x00000000},
585 {0x0000a220, 0x00000000},
586 {0x0000a224, 0x00000000},
587 {0x0000a228, 0x10002310},
588 {0x0000a23c, 0x00000000},
589 {0x0000a244, 0x0c000000},
590 {0x0000a2a0, 0x00000001},
591 {0x0000a2c0, 0x00000001},
592 {0x0000a2c8, 0x00000000},
593 {0x0000a2cc, 0x18c43433},
594 {0x0000a2d4, 0x00000000},
595 {0x0000a2dc, 0x00000000},
596 {0x0000a2e0, 0x00000000},
597 {0x0000a2e4, 0x00000000},
598 {0x0000a2e8, 0x00000000},
599 {0x0000a2ec, 0x00000000},
600 {0x0000a2f0, 0x00000000},
601 {0x0000a2f4, 0x00000000},
602 {0x0000a2f8, 0x00000000},
603 {0x0000a344, 0x00000000},
604 {0x0000a34c, 0x00000000},
605 {0x0000a350, 0x0000a000},
606 {0x0000a364, 0x00000000},
607 {0x0000a370, 0x00000000},
608 {0x0000a390, 0x00000001},
609 {0x0000a394, 0x00000444},
610 {0x0000a398, 0x001f0e0f},
611 {0x0000a39c, 0x0075393f},
612 {0x0000a3a0, 0xb79f6427},
613 {0x0000a3a4, 0x00000000},
614 {0x0000a3a8, 0xaaaaaaaa},
615 {0x0000a3ac, 0x3c466478},
616 {0x0000a3c0, 0x20202020},
617 {0x0000a3c4, 0x22222220},
618 {0x0000a3c8, 0x20200020},
619 {0x0000a3cc, 0x20202020},
620 {0x0000a3d0, 0x20202020},
621 {0x0000a3d4, 0x20202020},
622 {0x0000a3d8, 0x20202020},
623 {0x0000a3dc, 0x20202020},
624 {0x0000a3e0, 0x20202020},
625 {0x0000a3e4, 0x20202020},
626 {0x0000a3e8, 0x20202020},
627 {0x0000a3ec, 0x20202020},
628 {0x0000a3f0, 0x00000000},
629 {0x0000a3f4, 0x00000006},
630 {0x0000a3f8, 0x0cdbd380},
631 {0x0000a3fc, 0x000f0f01},
632 {0x0000a400, 0x8fa91f01},
633 {0x0000a404, 0x00000000},
634 {0x0000a408, 0x0e79e5c6},
635 {0x0000a40c, 0x00820820},
636 {0x0000a414, 0x1ce739ce},
637 {0x0000a418, 0x2d001dce},
638 {0x0000a41c, 0x1ce739ce},
639 {0x0000a420, 0x000001ce},
640 {0x0000a424, 0x1ce739ce},
641 {0x0000a428, 0x000001ce},
642 {0x0000a42c, 0x1ce739ce},
643 {0x0000a430, 0x1ce739ce},
644 {0x0000a434, 0x00000000},
645 {0x0000a438, 0x00001801},
646 {0x0000a43c, 0x00000000},
647 {0x0000a440, 0x00000000},
648 {0x0000a444, 0x00000000},
649 {0x0000a448, 0x04000000},
650 {0x0000a44c, 0x00000001},
651 {0x0000a450, 0x00010000},
652 {0x0000a458, 0x00000000},
653 {0x0000a640, 0x00000000},
654 {0x0000a644, 0x3fad9d74},
655 {0x0000a648, 0x0048060a},
656 {0x0000a64c, 0x00003c37},
657 {0x0000a670, 0x03020100},
658 {0x0000a674, 0x09080504},
659 {0x0000a678, 0x0d0c0b0a},
660 {0x0000a67c, 0x13121110},
661 {0x0000a680, 0x31301514},
662 {0x0000a684, 0x35343332},
663 {0x0000a688, 0x00000036},
664 {0x0000a690, 0x00000838},
665 {0x0000a7c0, 0x00000000},
666 {0x0000a7c4, 0xfffffffc},
667 {0x0000a7c8, 0x00000000},
668 {0x0000a7cc, 0x00000000},
669 {0x0000a7d0, 0x00000000},
670 {0x0000a7d4, 0x00000004},
671 {0x0000a7dc, 0x00000001},
672};
673 227
674static const u32 ar9331_modes_high_power_tx_gain_1p2[][5] = { 228#define ar9331_1p2_baseband_core ar9331_1p1_baseband_core
675 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
676 {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d7, 0x000050d7},
677 {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
678 {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
679 {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
680 {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
681 {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
682 {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
683 {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
684 {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
685 {0x0000a520, 0x2f001f04, 0x2f001f04, 0x23000a00, 0x23000a00},
686 {0x0000a524, 0x35001fc4, 0x35001fc4, 0x27000a02, 0x27000a02},
687 {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2b000a04, 0x2b000a04},
688 {0x0000a52c, 0x41023e85, 0x41023e85, 0x3f001620, 0x3f001620},
689 {0x0000a530, 0x48023ec6, 0x48023ec6, 0x41001621, 0x41001621},
690 {0x0000a534, 0x4d023f01, 0x4d023f01, 0x44001640, 0x44001640},
691 {0x0000a538, 0x53023f4b, 0x53023f4b, 0x46001641, 0x46001641},
692 {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x48001642, 0x48001642},
693 {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x4b001644, 0x4b001644},
694 {0x0000a544, 0x6502feca, 0x6502feca, 0x4e001a81, 0x4e001a81},
695 {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x51001a83, 0x51001a83},
696 {0x0000a54c, 0x7203feca, 0x7203feca, 0x54001c84, 0x54001c84},
697 {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x57001ce3, 0x57001ce3},
698 {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x5b001ce5, 0x5b001ce5},
699 {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x5f001ce9, 0x5f001ce9},
700 {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x66001eec, 0x66001eec},
701 {0x0000a560, 0x900fff0b, 0x900fff0b, 0x66001eec, 0x66001eec},
702 {0x0000a564, 0x960fffcb, 0x960fffcb, 0x66001eec, 0x66001eec},
703 {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
704 {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
705 {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
706 {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
707 {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
708 {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
709 {0x0000a580, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
710 {0x0000a584, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
711 {0x0000a588, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
712 {0x0000a58c, 0x11062202, 0x11062202, 0x0b000200, 0x0b000200},
713 {0x0000a590, 0x17022e00, 0x17022e00, 0x0f000202, 0x0f000202},
714 {0x0000a594, 0x1d000ec2, 0x1d000ec2, 0x11000400, 0x11000400},
715 {0x0000a598, 0x25020ec0, 0x25020ec0, 0x15000402, 0x15000402},
716 {0x0000a59c, 0x2b020ec3, 0x2b020ec3, 0x19000404, 0x19000404},
717 {0x0000a5a0, 0x2f001f04, 0x2f001f04, 0x1b000603, 0x1b000603},
718 {0x0000a5a4, 0x35001fc4, 0x35001fc4, 0x1f000a02, 0x1f000a02},
719 {0x0000a5a8, 0x3c022f04, 0x3c022f04, 0x23000a04, 0x23000a04},
720 {0x0000a5ac, 0x41023e85, 0x41023e85, 0x26000a20, 0x26000a20},
721 {0x0000a5b0, 0x48023ec6, 0x48023ec6, 0x2a000e20, 0x2a000e20},
722 {0x0000a5b4, 0x4d023f01, 0x4d023f01, 0x2e000e22, 0x2e000e22},
723 {0x0000a5b8, 0x53023f4b, 0x53023f4b, 0x31000e24, 0x31000e24},
724 {0x0000a5bc, 0x5a027f09, 0x5a027f09, 0x34001640, 0x34001640},
725 {0x0000a5c0, 0x5f027fc9, 0x5f027fc9, 0x38001660, 0x38001660},
726 {0x0000a5c4, 0x6502feca, 0x6502feca, 0x3b001861, 0x3b001861},
727 {0x0000a5c8, 0x6b02ff4a, 0x6b02ff4a, 0x3e001a81, 0x3e001a81},
728 {0x0000a5cc, 0x7203feca, 0x7203feca, 0x42001a83, 0x42001a83},
729 {0x0000a5d0, 0x7703ff0b, 0x7703ff0b, 0x44001c84, 0x44001c84},
730 {0x0000a5d4, 0x7d06ffcb, 0x7d06ffcb, 0x48001ce3, 0x48001ce3},
731 {0x0000a5d8, 0x8407ff0b, 0x8407ff0b, 0x4c001ce5, 0x4c001ce5},
732 {0x0000a5dc, 0x8907ffcb, 0x8907ffcb, 0x50001ce9, 0x50001ce9},
733 {0x0000a5e0, 0x900fff0b, 0x900fff0b, 0x54001ceb, 0x54001ceb},
734 {0x0000a5e4, 0x960fffcb, 0x960fffcb, 0x56001eec, 0x56001eec},
735 {0x0000a5e8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
736 {0x0000a5ec, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
737 {0x0000a5f0, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
738 {0x0000a5f4, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
739 {0x0000a5f8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
740 {0x0000a5fc, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
741 {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
742 {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
743 {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
744 {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
745 {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
746 {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
747 {0x0000a618, 0x02008501, 0x02008501, 0x02008501, 0x02008501},
748 {0x0000a61c, 0x02008802, 0x02008802, 0x02008802, 0x02008802},
749 {0x0000a620, 0x0300c802, 0x0300c802, 0x0300c802, 0x0300c802},
750 {0x0000a624, 0x0300cc03, 0x0300cc03, 0x0300cc03, 0x0300cc03},
751 {0x0000a628, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
752 {0x0000a62c, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
753 {0x0000a630, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
754 {0x0000a634, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
755 {0x0000a638, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
756 {0x0000a63c, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
757};
758 229
759static const u32 ar9331_1p2_mac_postamble[][5] = { 230#define ar9331_1p2_soc_postamble ar9331_1p1_soc_postamble
760 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
761 {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
762 {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
763 {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
764 {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
765 {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
766 {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
767 {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
768 {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
769};
770 231
771static const u32 ar9331_1p2_soc_preamble[][2] = { 232#define ar9331_1p2_mac_postamble ar9331_1p1_mac_postamble
772 /* Addr allmodes */
773 {0x00007020, 0x00000000},
774 {0x00007034, 0x00000002},
775 {0x00007038, 0x000002f8},
776};
777 233
778static const u32 ar9331_1p2_xtal_40M[][2] = { 234#define ar9331_1p2_soc_preamble ar9331_1p1_soc_preamble
779 /* Addr allmodes */
780 {0x00007038, 0x000004c2},
781 {0x00008244, 0x0010f400},
782 {0x0000824c, 0x0001e800},
783 {0x0001609c, 0x0b283f31},
784};
785 235
786static const u32 ar9331_1p2_mac_core[][2] = { 236#define ar9331_1p2_mac_core ar9331_1p1_mac_core
787 /* Addr allmodes */
788 {0x00000008, 0x00000000},
789 {0x00000030, 0x00020085},
790 {0x00000034, 0x00000005},
791 {0x00000040, 0x00000000},
792 {0x00000044, 0x00000000},
793 {0x00000048, 0x00000008},
794 {0x0000004c, 0x00000010},
795 {0x00000050, 0x00000000},
796 {0x00001040, 0x002ffc0f},
797 {0x00001044, 0x002ffc0f},
798 {0x00001048, 0x002ffc0f},
799 {0x0000104c, 0x002ffc0f},
800 {0x00001050, 0x002ffc0f},
801 {0x00001054, 0x002ffc0f},
802 {0x00001058, 0x002ffc0f},
803 {0x0000105c, 0x002ffc0f},
804 {0x00001060, 0x002ffc0f},
805 {0x00001064, 0x002ffc0f},
806 {0x000010f0, 0x00000100},
807 {0x00001270, 0x00000000},
808 {0x000012b0, 0x00000000},
809 {0x000012f0, 0x00000000},
810 {0x0000143c, 0x00000000},
811 {0x0000147c, 0x00000000},
812 {0x00008000, 0x00000000},
813 {0x00008004, 0x00000000},
814 {0x00008008, 0x00000000},
815 {0x0000800c, 0x00000000},
816 {0x00008018, 0x00000000},
817 {0x00008020, 0x00000000},
818 {0x00008038, 0x00000000},
819 {0x0000803c, 0x00000000},
820 {0x00008040, 0x00000000},
821 {0x00008044, 0x00000000},
822 {0x00008048, 0x00000000},
823 {0x0000804c, 0xffffffff},
824 {0x00008054, 0x00000000},
825 {0x00008058, 0x00000000},
826 {0x0000805c, 0x000fc78f},
827 {0x00008060, 0x0000000f},
828 {0x00008064, 0x00000000},
829 {0x00008070, 0x00000310},
830 {0x00008074, 0x00000020},
831 {0x00008078, 0x00000000},
832 {0x0000809c, 0x0000000f},
833 {0x000080a0, 0x00000000},
834 {0x000080a4, 0x02ff0000},
835 {0x000080a8, 0x0e070605},
836 {0x000080ac, 0x0000000d},
837 {0x000080b0, 0x00000000},
838 {0x000080b4, 0x00000000},
839 {0x000080b8, 0x00000000},
840 {0x000080bc, 0x00000000},
841 {0x000080c0, 0x2a800000},
842 {0x000080c4, 0x06900168},
843 {0x000080c8, 0x13881c20},
844 {0x000080cc, 0x01f40000},
845 {0x000080d0, 0x00252500},
846 {0x000080d4, 0x00a00000},
847 {0x000080d8, 0x00400000},
848 {0x000080dc, 0x00000000},
849 {0x000080e0, 0xffffffff},
850 {0x000080e4, 0x0000ffff},
851 {0x000080e8, 0x3f3f3f3f},
852 {0x000080ec, 0x00000000},
853 {0x000080f0, 0x00000000},
854 {0x000080f4, 0x00000000},
855 {0x000080fc, 0x00020000},
856 {0x00008100, 0x00000000},
857 {0x00008108, 0x00000052},
858 {0x0000810c, 0x00000000},
859 {0x00008110, 0x00000000},
860 {0x00008114, 0x000007ff},
861 {0x00008118, 0x000000aa},
862 {0x0000811c, 0x00003210},
863 {0x00008124, 0x00000000},
864 {0x00008128, 0x00000000},
865 {0x0000812c, 0x00000000},
866 {0x00008130, 0x00000000},
867 {0x00008134, 0x00000000},
868 {0x00008138, 0x00000000},
869 {0x0000813c, 0x0000ffff},
870 {0x00008144, 0xffffffff},
871 {0x00008168, 0x00000000},
872 {0x0000816c, 0x00000000},
873 {0x00008170, 0x18486200},
874 {0x00008174, 0x33332210},
875 {0x00008178, 0x00000000},
876 {0x0000817c, 0x00020000},
877 {0x000081c0, 0x00000000},
878 {0x000081c4, 0x33332210},
879 {0x000081c8, 0x00000000},
880 {0x000081cc, 0x00000000},
881 {0x000081d4, 0x00000000},
882 {0x000081ec, 0x00000000},
883 {0x000081f0, 0x00000000},
884 {0x000081f4, 0x00000000},
885 {0x000081f8, 0x00000000},
886 {0x000081fc, 0x00000000},
887 {0x00008240, 0x00100000},
888 {0x00008248, 0x00000800},
889 {0x00008250, 0x00000000},
890 {0x00008254, 0x00000000},
891 {0x00008258, 0x00000000},
892 {0x0000825c, 0x40000000},
893 {0x00008260, 0x00080922},
894 {0x00008264, 0x9d400010},
895 {0x00008268, 0xffffffff},
896 {0x0000826c, 0x0000ffff},
897 {0x00008270, 0x00000000},
898 {0x00008274, 0x40000000},
899 {0x00008278, 0x003e4180},
900 {0x0000827c, 0x00000004},
901 {0x00008284, 0x0000002c},
902 {0x00008288, 0x0000002c},
903 {0x0000828c, 0x000000ff},
904 {0x00008294, 0x00000000},
905 {0x00008298, 0x00000000},
906 {0x0000829c, 0x00000000},
907 {0x00008300, 0x00000140},
908 {0x00008314, 0x00000000},
909 {0x0000831c, 0x0000010d},
910 {0x00008328, 0x00000000},
911 {0x0000832c, 0x00000007},
912 {0x00008330, 0x00000302},
913 {0x00008334, 0x00000700},
914 {0x00008338, 0x00ff0000},
915 {0x0000833c, 0x02400000},
916 {0x00008340, 0x000107ff},
917 {0x00008344, 0xaa48105b},
918 {0x00008348, 0x008f0000},
919 {0x0000835c, 0x00000000},
920 {0x00008360, 0xffffffff},
921 {0x00008364, 0xffffffff},
922 {0x00008368, 0x00000000},
923 {0x00008370, 0x00000000},
924 {0x00008374, 0x000000ff},
925 {0x00008378, 0x00000000},
926 {0x0000837c, 0x00000000},
927 {0x00008380, 0xffffffff},
928 {0x00008384, 0xffffffff},
929 {0x00008390, 0xffffffff},
930 {0x00008394, 0xffffffff},
931 {0x00008398, 0x00000000},
932 {0x0000839c, 0x00000000},
933 {0x000083a0, 0x00000000},
934 {0x000083a4, 0x0000fa14},
935 {0x000083a8, 0x000f0c00},
936 {0x000083ac, 0x33332210},
937 {0x000083b0, 0x33332210},
938 {0x000083b4, 0x33332210},
939 {0x000083b8, 0x33332210},
940 {0x000083bc, 0x00000000},
941 {0x000083c0, 0x00000000},
942 {0x000083c4, 0x00000000},
943 {0x000083c8, 0x00000000},
944 {0x000083cc, 0x00000200},
945 {0x000083d0, 0x000301ff},
946};
947 237
948static const u32 ar9331_common_rx_gain_1p2[][2] = { 238#define ar9331_common_wo_xlna_rx_gain_1p2 ar9331_common_wo_xlna_rx_gain_1p1
949 /* Addr allmodes */ 239
950 {0x0000a000, 0x00010000}, 240#define ar9331_common_rx_gain_1p2 ar9485_common_rx_gain_1_1
951 {0x0000a004, 0x00030002},
952 {0x0000a008, 0x00050004},
953 {0x0000a00c, 0x00810080},
954 {0x0000a010, 0x01800082},
955 {0x0000a014, 0x01820181},
956 {0x0000a018, 0x01840183},
957 {0x0000a01c, 0x01880185},
958 {0x0000a020, 0x018a0189},
959 {0x0000a024, 0x02850284},
960 {0x0000a028, 0x02890288},
961 {0x0000a02c, 0x03850384},
962 {0x0000a030, 0x03890388},
963 {0x0000a034, 0x038b038a},
964 {0x0000a038, 0x038d038c},
965 {0x0000a03c, 0x03910390},
966 {0x0000a040, 0x03930392},
967 {0x0000a044, 0x03950394},
968 {0x0000a048, 0x00000396},
969 {0x0000a04c, 0x00000000},
970 {0x0000a050, 0x00000000},
971 {0x0000a054, 0x00000000},
972 {0x0000a058, 0x00000000},
973 {0x0000a05c, 0x00000000},
974 {0x0000a060, 0x00000000},
975 {0x0000a064, 0x00000000},
976 {0x0000a068, 0x00000000},
977 {0x0000a06c, 0x00000000},
978 {0x0000a070, 0x00000000},
979 {0x0000a074, 0x00000000},
980 {0x0000a078, 0x00000000},
981 {0x0000a07c, 0x00000000},
982 {0x0000a080, 0x28282828},
983 {0x0000a084, 0x28282828},
984 {0x0000a088, 0x28282828},
985 {0x0000a08c, 0x28282828},
986 {0x0000a090, 0x28282828},
987 {0x0000a094, 0x21212128},
988 {0x0000a098, 0x171c1c1c},
989 {0x0000a09c, 0x02020212},
990 {0x0000a0a0, 0x00000202},
991 {0x0000a0a4, 0x00000000},
992 {0x0000a0a8, 0x00000000},
993 {0x0000a0ac, 0x00000000},
994 {0x0000a0b0, 0x00000000},
995 {0x0000a0b4, 0x00000000},
996 {0x0000a0b8, 0x00000000},
997 {0x0000a0bc, 0x00000000},
998 {0x0000a0c0, 0x001f0000},
999 {0x0000a0c4, 0x111f1100},
1000 {0x0000a0c8, 0x111d111e},
1001 {0x0000a0cc, 0x111b111c},
1002 {0x0000a0d0, 0x22032204},
1003 {0x0000a0d4, 0x22012202},
1004 {0x0000a0d8, 0x221f2200},
1005 {0x0000a0dc, 0x221d221e},
1006 {0x0000a0e0, 0x33013302},
1007 {0x0000a0e4, 0x331f3300},
1008 {0x0000a0e8, 0x4402331e},
1009 {0x0000a0ec, 0x44004401},
1010 {0x0000a0f0, 0x441e441f},
1011 {0x0000a0f4, 0x55015502},
1012 {0x0000a0f8, 0x551f5500},
1013 {0x0000a0fc, 0x6602551e},
1014 {0x0000a100, 0x66006601},
1015 {0x0000a104, 0x661e661f},
1016 {0x0000a108, 0x7703661d},
1017 {0x0000a10c, 0x77017702},
1018 {0x0000a110, 0x00007700},
1019 {0x0000a114, 0x00000000},
1020 {0x0000a118, 0x00000000},
1021 {0x0000a11c, 0x00000000},
1022 {0x0000a120, 0x00000000},
1023 {0x0000a124, 0x00000000},
1024 {0x0000a128, 0x00000000},
1025 {0x0000a12c, 0x00000000},
1026 {0x0000a130, 0x00000000},
1027 {0x0000a134, 0x00000000},
1028 {0x0000a138, 0x00000000},
1029 {0x0000a13c, 0x00000000},
1030 {0x0000a140, 0x001f0000},
1031 {0x0000a144, 0x111f1100},
1032 {0x0000a148, 0x111d111e},
1033 {0x0000a14c, 0x111b111c},
1034 {0x0000a150, 0x22032204},
1035 {0x0000a154, 0x22012202},
1036 {0x0000a158, 0x221f2200},
1037 {0x0000a15c, 0x221d221e},
1038 {0x0000a160, 0x33013302},
1039 {0x0000a164, 0x331f3300},
1040 {0x0000a168, 0x4402331e},
1041 {0x0000a16c, 0x44004401},
1042 {0x0000a170, 0x441e441f},
1043 {0x0000a174, 0x55015502},
1044 {0x0000a178, 0x551f5500},
1045 {0x0000a17c, 0x6602551e},
1046 {0x0000a180, 0x66006601},
1047 {0x0000a184, 0x661e661f},
1048 {0x0000a188, 0x7703661d},
1049 {0x0000a18c, 0x77017702},
1050 {0x0000a190, 0x00007700},
1051 {0x0000a194, 0x00000000},
1052 {0x0000a198, 0x00000000},
1053 {0x0000a19c, 0x00000000},
1054 {0x0000a1a0, 0x00000000},
1055 {0x0000a1a4, 0x00000000},
1056 {0x0000a1a8, 0x00000000},
1057 {0x0000a1ac, 0x00000000},
1058 {0x0000a1b0, 0x00000000},
1059 {0x0000a1b4, 0x00000000},
1060 {0x0000a1b8, 0x00000000},
1061 {0x0000a1bc, 0x00000000},
1062 {0x0000a1c0, 0x00000000},
1063 {0x0000a1c4, 0x00000000},
1064 {0x0000a1c8, 0x00000000},
1065 {0x0000a1cc, 0x00000000},
1066 {0x0000a1d0, 0x00000000},
1067 {0x0000a1d4, 0x00000000},
1068 {0x0000a1d8, 0x00000000},
1069 {0x0000a1dc, 0x00000000},
1070 {0x0000a1e0, 0x00000000},
1071 {0x0000a1e4, 0x00000000},
1072 {0x0000a1e8, 0x00000000},
1073 {0x0000a1ec, 0x00000000},
1074 {0x0000a1f0, 0x00000396},
1075 {0x0000a1f4, 0x00000396},
1076 {0x0000a1f8, 0x00000396},
1077 {0x0000a1fc, 0x00000296},
1078};
1079 241
1080#endif /* INITVALS_9330_1P2_H */ 242#endif /* INITVALS_9330_1P2_H */
diff --git a/drivers/net/wireless/ath/ath9k/ar9340_initvals.h b/drivers/net/wireless/ath/ath9k/ar9340_initvals.h
index 815a8af1beef..1d8235e19f0f 100644
--- a/drivers/net/wireless/ath/ath9k/ar9340_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9340_initvals.h
@@ -1,5 +1,6 @@
1/* 1/*
2 * Copyright (c) 2011 Atheros Communications Inc. 2 * Copyright (c) 2010-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2012 Qualcomm Atheros Inc.
3 * 4 *
4 * Permission to use, copy, modify, and/or distribute this software for any 5 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above 6 * purpose with or without fee is hereby granted, provided that the above
@@ -18,16 +19,16 @@
18#define INITVALS_9340_H 19#define INITVALS_9340_H
19 20
20static const u32 ar9340_1p0_radio_postamble[][5] = { 21static const u32 ar9340_1p0_radio_postamble[][5] = {
21 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 22 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
22 {0x000160ac, 0xa4646800, 0xa4646800, 0xa4646800, 0xa4646800}, 23 {0x000160ac, 0xa4646800, 0xa4646800, 0xa4646800, 0xa4646800},
23 {0x0001610c, 0x08000000, 0x08000000, 0x00000000, 0x00000000}, 24 {0x0001610c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
24 {0x00016140, 0x10804000, 0x10804000, 0x50804000, 0x50804000}, 25 {0x00016140, 0x10804000, 0x10804000, 0x50804000, 0x50804000},
25 {0x0001650c, 0x08000000, 0x08000000, 0x00000000, 0x00000000}, 26 {0x0001650c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
26 {0x00016540, 0x10804000, 0x10804000, 0x50804000, 0x50804000}, 27 {0x00016540, 0x10804000, 0x10804000, 0x50804000, 0x50804000},
27}; 28};
28 29
29static const u32 ar9340Modes_lowest_ob_db_tx_gain_table_1p0[][5] = { 30static const u32 ar9340Modes_lowest_ob_db_tx_gain_table_1p0[][5] = {
30 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 31 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
31 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9}, 32 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
32 {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 33 {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
33 {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002}, 34 {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
@@ -99,21 +100,10 @@ static const u32 ar9340Modes_lowest_ob_db_tx_gain_table_1p0[][5] = {
99 {0x00016448, 0x24925266, 0x24925266, 0x24925266, 0x24925266}, 100 {0x00016448, 0x24925266, 0x24925266, 0x24925266, 0x24925266},
100}; 101};
101 102
102static const u32 ar9340Modes_fast_clock_1p0[][3] = { 103#define ar9340Modes_fast_clock_1p0 ar9300Modes_fast_clock_2p2
103 /* Addr 5G_HT20 5G_HT40 */
104 {0x00001030, 0x00000268, 0x000004d0},
105 {0x00001070, 0x0000018c, 0x00000318},
106 {0x000010b0, 0x00000fd0, 0x00001fa0},
107 {0x00008014, 0x044c044c, 0x08980898},
108 {0x0000801c, 0x148ec02b, 0x148ec057},
109 {0x00008318, 0x000044c0, 0x00008980},
110 {0x00009e00, 0x03721821, 0x03721821},
111 {0x0000a230, 0x0000000b, 0x00000016},
112 {0x0000a254, 0x00000898, 0x00001130},
113};
114 104
115static const u32 ar9340_1p0_radio_core[][2] = { 105static const u32 ar9340_1p0_radio_core[][2] = {
116 /* Addr allmodes */ 106 /* Addr allmodes */
117 {0x00016000, 0x36db6db6}, 107 {0x00016000, 0x36db6db6},
118 {0x00016004, 0x6db6db40}, 108 {0x00016004, 0x6db6db40},
119 {0x00016008, 0x73f00000}, 109 {0x00016008, 0x73f00000},
@@ -146,15 +136,13 @@ static const u32 ar9340_1p0_radio_core[][2] = {
146 {0x00016100, 0x04cb0001}, 136 {0x00016100, 0x04cb0001},
147 {0x00016104, 0xfff80000}, 137 {0x00016104, 0xfff80000},
148 {0x00016108, 0x00080010}, 138 {0x00016108, 0x00080010},
149 {0x0001610c, 0x00000000},
150 {0x00016140, 0x50804008}, 139 {0x00016140, 0x50804008},
151 {0x00016144, 0x01884080}, 140 {0x00016144, 0x01884080},
152 {0x00016148, 0x000080c0}, 141 {0x00016148, 0x000080c0},
153 {0x00016280, 0x01000015}, 142 {0x00016280, 0x01000015},
154 {0x00016284, 0x05530000}, 143 {0x00016284, 0x15530000},
155 {0x00016288, 0x00318000}, 144 {0x00016288, 0x00318000},
156 {0x0001628c, 0x50000000}, 145 {0x0001628c, 0x50000000},
157 {0x00016290, 0x4080294f},
158 {0x00016380, 0x00000000}, 146 {0x00016380, 0x00000000},
159 {0x00016384, 0x00000000}, 147 {0x00016384, 0x00000000},
160 {0x00016388, 0x00800700}, 148 {0x00016388, 0x00800700},
@@ -219,52 +207,43 @@ static const u32 ar9340_1p0_radio_core[][2] = {
219}; 207};
220 208
221static const u32 ar9340_1p0_radio_core_40M[][2] = { 209static const u32 ar9340_1p0_radio_core_40M[][2] = {
210 /* Addr allmodes */
222 {0x0001609c, 0x02566f3a}, 211 {0x0001609c, 0x02566f3a},
223 {0x000160ac, 0xa4647c00}, 212 {0x000160ac, 0xa4647c00},
224 {0x000160b0, 0x01885f5a}, 213 {0x000160b0, 0x01885f5a},
225}; 214};
226 215
227static const u32 ar9340_1p0_mac_postamble[][5] = { 216#define ar9340_1p0_mac_postamble ar9300_2p2_mac_postamble
228 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
229 {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
230 {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
231 {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
232 {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
233 {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
234 {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
235 {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
236 {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
237};
238 217
239static const u32 ar9340_1p0_soc_postamble[][5] = { 218#define ar9340_1p0_soc_postamble ar9300_2p2_soc_postamble
240 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
241 {0x00007010, 0x00000023, 0x00000023, 0x00000023, 0x00000023},
242};
243 219
244static const u32 ar9340_1p0_baseband_postamble[][5] = { 220static const u32 ar9340_1p0_baseband_postamble[][5] = {
245 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 221 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
246 {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011}, 222 {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011},
247 {0x00009820, 0x206a022e, 0x206a022e, 0x206a022e, 0x206a022e}, 223 {0x00009820, 0x206a022e, 0x206a022e, 0x206a022e, 0x206a022e},
248 {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0}, 224 {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
249 {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881}, 225 {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
250 {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4}, 226 {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
251 {0x00009830, 0x0000059c, 0x0000059c, 0x0000119c, 0x0000119c}, 227 {0x00009830, 0x0000059c, 0x0000059c, 0x0000119c, 0x0000119c},
252 {0x00009c00, 0x00000044, 0x000000c4, 0x000000c4, 0x00000044}, 228 {0x00009c00, 0x000000c4, 0x000000c4, 0x000000c4, 0x000000c4},
253 {0x00009e00, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0}, 229 {0x00009e00, 0x0372111a, 0x0372111a, 0x037216a0, 0x037216a0},
254 {0x00009e04, 0x00182020, 0x00182020, 0x00182020, 0x00182020}, 230 {0x00009e04, 0x001c2020, 0x001c2020, 0x001c2020, 0x001c2020},
255 {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2}, 231 {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
256 {0x00009e10, 0x7ec88d2e, 0x7ec88d2e, 0x7ec88d2e, 0x7ec88d2e}, 232 {0x00009e10, 0x7ec88d2e, 0x7ec88d2e, 0x7ec88d2e, 0x7ec88d2e},
257 {0x00009e14, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e}, 233 {0x00009e14, 0x37b95d5e, 0x37b9605e, 0x3379605e, 0x33795d5e},
258 {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 234 {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
259 {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c}, 235 {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
260 {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce}, 236 {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
261 {0x00009e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021}, 237 {0x00009e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021},
238 {0x00009e3c, 0xcf946220, 0xcf946220, 0xcf946222, 0xcf946222},
262 {0x00009e44, 0x02321e27, 0x02321e27, 0x02291e27, 0x02291e27}, 239 {0x00009e44, 0x02321e27, 0x02321e27, 0x02291e27, 0x02291e27},
263 {0x00009e48, 0x5030201a, 0x5030201a, 0x50302012, 0x50302012}, 240 {0x00009e48, 0x5030201a, 0x5030201a, 0x50302012, 0x50302012},
264 {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000}, 241 {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
265 {0x0000a204, 0x00003fc0, 0x00003fc4, 0x00003fc4, 0x00003fc0}, 242 {0x0000a204, 0x00003ec0, 0x00003ec4, 0x00003ec4, 0x00003ec0},
266 {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004}, 243 {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004},
244 {0x0000a22c, 0x07e26a2f, 0x07e26a2f, 0x01026a2f, 0x01026a2f},
267 {0x0000a230, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b}, 245 {0x0000a230, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b},
246 {0x0000a234, 0x00000fff, 0x10000fff, 0x10000fff, 0x00000fff},
268 {0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018}, 247 {0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018},
269 {0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108}, 248 {0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108},
270 {0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898}, 249 {0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898},
@@ -277,11 +256,11 @@ static const u32 ar9340_1p0_baseband_postamble[][5] = {
277 {0x0000a288, 0x00000220, 0x00000220, 0x00000110, 0x00000110}, 256 {0x0000a288, 0x00000220, 0x00000220, 0x00000110, 0x00000110},
278 {0x0000a28c, 0x00011111, 0x00011111, 0x00022222, 0x00022222}, 257 {0x0000a28c, 0x00011111, 0x00011111, 0x00022222, 0x00022222},
279 {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18}, 258 {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
280 {0x0000a2d0, 0x00071981, 0x00071981, 0x00071981, 0x00071982}, 259 {0x0000a2d0, 0x00041983, 0x00041983, 0x00041982, 0x00041982},
281 {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0xf999a83a, 0xf999a83a}, 260 {0x0000a2d8, 0x7999a83a, 0x7999a83a, 0x7999a83a, 0x7999a83a},
282 {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 261 {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
283 {0x0000a830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c}, 262 {0x0000a830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
284 {0x0000ae04, 0x00180000, 0x00180000, 0x00180000, 0x00180000}, 263 {0x0000ae04, 0x001c0000, 0x001c0000, 0x001c0000, 0x001c0000},
285 {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 264 {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
286 {0x0000ae1c, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c}, 265 {0x0000ae1c, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
287 {0x0000ae20, 0x000001b5, 0x000001b5, 0x000001ce, 0x000001ce}, 266 {0x0000ae20, 0x000001b5, 0x000001b5, 0x000001ce, 0x000001ce},
@@ -289,21 +268,21 @@ static const u32 ar9340_1p0_baseband_postamble[][5] = {
289}; 268};
290 269
291static const u32 ar9340_1p0_baseband_core[][2] = { 270static const u32 ar9340_1p0_baseband_core[][2] = {
292 /* Addr allmodes */ 271 /* Addr allmodes */
293 {0x00009800, 0xafe68e30}, 272 {0x00009800, 0xafe68e30},
294 {0x00009804, 0xfd14e000}, 273 {0x00009804, 0xfd14e000},
295 {0x00009808, 0x9c0a9f6b}, 274 {0x00009808, 0x9c0a9f6b},
296 {0x0000980c, 0x04900000}, 275 {0x0000980c, 0x04900000},
297 {0x00009814, 0xb280c00a}, 276 {0x00009814, 0x3280c00a},
298 {0x00009818, 0x00000000}, 277 {0x00009818, 0x00000000},
299 {0x0000981c, 0x00020028}, 278 {0x0000981c, 0x00020028},
300 {0x00009834, 0x5f3ca3de}, 279 {0x00009834, 0x6400a190},
301 {0x00009838, 0x0108ecff}, 280 {0x00009838, 0x0108ecff},
302 {0x0000983c, 0x14750600}, 281 {0x0000983c, 0x14000600},
303 {0x00009880, 0x201fff00}, 282 {0x00009880, 0x201fff00},
304 {0x00009884, 0x00001042}, 283 {0x00009884, 0x00001042},
305 {0x000098a4, 0x00200400}, 284 {0x000098a4, 0x00200400},
306 {0x000098b0, 0x52440bbe}, 285 {0x000098b0, 0x32840bbe},
307 {0x000098d0, 0x004b6a8e}, 286 {0x000098d0, 0x004b6a8e},
308 {0x000098d4, 0x00000820}, 287 {0x000098d4, 0x00000820},
309 {0x000098dc, 0x00000000}, 288 {0x000098dc, 0x00000000},
@@ -329,7 +308,6 @@ static const u32 ar9340_1p0_baseband_core[][2] = {
329 {0x00009e30, 0x06336f77}, 308 {0x00009e30, 0x06336f77},
330 {0x00009e34, 0x6af6532f}, 309 {0x00009e34, 0x6af6532f},
331 {0x00009e38, 0x0cc80c00}, 310 {0x00009e38, 0x0cc80c00},
332 {0x00009e3c, 0xcf946222},
333 {0x00009e40, 0x0d261820}, 311 {0x00009e40, 0x0d261820},
334 {0x00009e4c, 0x00001004}, 312 {0x00009e4c, 0x00001004},
335 {0x00009e50, 0x00ff03f1}, 313 {0x00009e50, 0x00ff03f1},
@@ -342,8 +320,6 @@ static const u32 ar9340_1p0_baseband_core[][2] = {
342 {0x0000a220, 0x00000000}, 320 {0x0000a220, 0x00000000},
343 {0x0000a224, 0x00000000}, 321 {0x0000a224, 0x00000000},
344 {0x0000a228, 0x10002310}, 322 {0x0000a228, 0x10002310},
345 {0x0000a22c, 0x01036a1e},
346 {0x0000a234, 0x10000fff},
347 {0x0000a23c, 0x00000000}, 323 {0x0000a23c, 0x00000000},
348 {0x0000a244, 0x0c000000}, 324 {0x0000a244, 0x0c000000},
349 {0x0000a2a0, 0x00000001}, 325 {0x0000a2a0, 0x00000001},
@@ -351,10 +327,6 @@ static const u32 ar9340_1p0_baseband_core[][2] = {
351 {0x0000a2c8, 0x00000000}, 327 {0x0000a2c8, 0x00000000},
352 {0x0000a2cc, 0x18c43433}, 328 {0x0000a2cc, 0x18c43433},
353 {0x0000a2d4, 0x00000000}, 329 {0x0000a2d4, 0x00000000},
354 {0x0000a2dc, 0x00000000},
355 {0x0000a2e0, 0x00000000},
356 {0x0000a2e4, 0x00000000},
357 {0x0000a2e8, 0x00000000},
358 {0x0000a2ec, 0x00000000}, 330 {0x0000a2ec, 0x00000000},
359 {0x0000a2f0, 0x00000000}, 331 {0x0000a2f0, 0x00000000},
360 {0x0000a2f4, 0x00000000}, 332 {0x0000a2f4, 0x00000000},
@@ -385,7 +357,7 @@ static const u32 ar9340_1p0_baseband_core[][2] = {
385 {0x0000a3e8, 0x20202020}, 357 {0x0000a3e8, 0x20202020},
386 {0x0000a3ec, 0x20202020}, 358 {0x0000a3ec, 0x20202020},
387 {0x0000a3f0, 0x00000000}, 359 {0x0000a3f0, 0x00000000},
388 {0x0000a3f4, 0x00000246}, 360 {0x0000a3f4, 0x00000000},
389 {0x0000a3f8, 0x0cdbd380}, 361 {0x0000a3f8, 0x0cdbd380},
390 {0x0000a3fc, 0x000f0f01}, 362 {0x0000a3fc, 0x000f0f01},
391 {0x0000a400, 0x8fa91f01}, 363 {0x0000a400, 0x8fa91f01},
@@ -402,33 +374,17 @@ static const u32 ar9340_1p0_baseband_core[][2] = {
402 {0x0000a430, 0x1ce739ce}, 374 {0x0000a430, 0x1ce739ce},
403 {0x0000a434, 0x00000000}, 375 {0x0000a434, 0x00000000},
404 {0x0000a438, 0x00001801}, 376 {0x0000a438, 0x00001801},
405 {0x0000a43c, 0x00000000}, 377 {0x0000a43c, 0x00100000},
406 {0x0000a440, 0x00000000}, 378 {0x0000a440, 0x00000000},
407 {0x0000a444, 0x00000000}, 379 {0x0000a444, 0x00000000},
408 {0x0000a448, 0x04000080}, 380 {0x0000a448, 0x05000080},
409 {0x0000a44c, 0x00000001}, 381 {0x0000a44c, 0x00000001},
410 {0x0000a450, 0x00010000}, 382 {0x0000a450, 0x00010000},
411 {0x0000a458, 0x00000000}, 383 {0x0000a458, 0x00000000},
412 {0x0000a600, 0x00000000},
413 {0x0000a604, 0x00000000},
414 {0x0000a608, 0x00000000},
415 {0x0000a60c, 0x00000000},
416 {0x0000a610, 0x00000000},
417 {0x0000a614, 0x00000000},
418 {0x0000a618, 0x00000000},
419 {0x0000a61c, 0x00000000},
420 {0x0000a620, 0x00000000},
421 {0x0000a624, 0x00000000},
422 {0x0000a628, 0x00000000},
423 {0x0000a62c, 0x00000000},
424 {0x0000a630, 0x00000000},
425 {0x0000a634, 0x00000000},
426 {0x0000a638, 0x00000000},
427 {0x0000a63c, 0x00000000},
428 {0x0000a640, 0x00000000}, 384 {0x0000a640, 0x00000000},
429 {0x0000a644, 0x3fad9d74}, 385 {0x0000a644, 0x3fad9d74},
430 {0x0000a648, 0x0048060a}, 386 {0x0000a648, 0x0048060a},
431 {0x0000a64c, 0x00000637}, 387 {0x0000a64c, 0x00003c37},
432 {0x0000a670, 0x03020100}, 388 {0x0000a670, 0x03020100},
433 {0x0000a674, 0x09080504}, 389 {0x0000a674, 0x09080504},
434 {0x0000a678, 0x0d0c0b0a}, 390 {0x0000a678, 0x0d0c0b0a},
@@ -451,10 +407,6 @@ static const u32 ar9340_1p0_baseband_core[][2] = {
451 {0x0000a8f4, 0x00000000}, 407 {0x0000a8f4, 0x00000000},
452 {0x0000b2d0, 0x00000080}, 408 {0x0000b2d0, 0x00000080},
453 {0x0000b2d4, 0x00000000}, 409 {0x0000b2d4, 0x00000000},
454 {0x0000b2dc, 0x00000000},
455 {0x0000b2e0, 0x00000000},
456 {0x0000b2e4, 0x00000000},
457 {0x0000b2e8, 0x00000000},
458 {0x0000b2ec, 0x00000000}, 410 {0x0000b2ec, 0x00000000},
459 {0x0000b2f0, 0x00000000}, 411 {0x0000b2f0, 0x00000000},
460 {0x0000b2f4, 0x00000000}, 412 {0x0000b2f4, 0x00000000},
@@ -465,80 +417,108 @@ static const u32 ar9340_1p0_baseband_core[][2] = {
465}; 417};
466 418
467static const u32 ar9340Modes_high_power_tx_gain_table_1p0[][5] = { 419static const u32 ar9340Modes_high_power_tx_gain_table_1p0[][5] = {
468 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 420 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
421 {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
422 {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
423 {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
424 {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
425 {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
426 {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
427 {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
428 {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
429 {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
430 {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
431 {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501},
432 {0x0000a61c, 0x02008802, 0x02008802, 0x02008501, 0x02008501},
433 {0x0000a620, 0x0300cc03, 0x0300cc03, 0x0280ca03, 0x0280ca03},
434 {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04},
435 {0x0000a628, 0x0300cc03, 0x0300cc03, 0x04014c04, 0x04014c04},
436 {0x0000a62c, 0x03810c03, 0x03810c03, 0x04015005, 0x04015005},
437 {0x0000a630, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
438 {0x0000a634, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
439 {0x0000a638, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
440 {0x0000a63c, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
441 {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
442 {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
443 {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
444 {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
469 {0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9}, 445 {0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9},
470 {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000}, 446 {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
471 {0x0000a504, 0x04002222, 0x04002222, 0x04000002, 0x04000002}, 447 {0x0000a504, 0x04002222, 0x04002222, 0x02000001, 0x02000001},
472 {0x0000a508, 0x09002421, 0x09002421, 0x08000004, 0x08000004}, 448 {0x0000a508, 0x09002421, 0x09002421, 0x05000003, 0x05000003},
473 {0x0000a50c, 0x0d002621, 0x0d002621, 0x0b000200, 0x0b000200}, 449 {0x0000a50c, 0x0d002621, 0x0d002621, 0x0a000005, 0x0a000005},
474 {0x0000a510, 0x13004620, 0x13004620, 0x0f000202, 0x0f000202}, 450 {0x0000a510, 0x13004620, 0x13004620, 0x0e000201, 0x0e000201},
475 {0x0000a514, 0x19004a20, 0x19004a20, 0x11000400, 0x11000400}, 451 {0x0000a514, 0x19004a20, 0x19004a20, 0x11000203, 0x11000203},
476 {0x0000a518, 0x1d004e20, 0x1d004e20, 0x15000402, 0x15000402}, 452 {0x0000a518, 0x1d004e20, 0x1d004e20, 0x14000401, 0x14000401},
477 {0x0000a51c, 0x21005420, 0x21005420, 0x19000404, 0x19000404}, 453 {0x0000a51c, 0x21005420, 0x21005420, 0x18000403, 0x18000403},
478 {0x0000a520, 0x26005e20, 0x26005e20, 0x1b000603, 0x1b000603}, 454 {0x0000a520, 0x26005e20, 0x26005e20, 0x1b000602, 0x1b000602},
479 {0x0000a524, 0x2b005e40, 0x2b005e40, 0x1f000a02, 0x1f000a02}, 455 {0x0000a524, 0x2b005e40, 0x2b005e40, 0x1f000802, 0x1f000802},
480 {0x0000a528, 0x2f005e42, 0x2f005e42, 0x23000a04, 0x23000a04}, 456 {0x0000a528, 0x2f005e42, 0x2f005e42, 0x21000620, 0x21000620},
481 {0x0000a52c, 0x33005e44, 0x33005e44, 0x26000a20, 0x26000a20}, 457 {0x0000a52c, 0x33005e44, 0x33005e44, 0x25000820, 0x25000820},
482 {0x0000a530, 0x38005e65, 0x38005e65, 0x2a000e20, 0x2a000e20}, 458 {0x0000a530, 0x38005e65, 0x38005e65, 0x29000822, 0x29000822},
483 {0x0000a534, 0x3c005e69, 0x3c005e69, 0x2e000e22, 0x2e000e22}, 459 {0x0000a534, 0x3c005e69, 0x3c005e69, 0x2d000824, 0x2d000824},
484 {0x0000a538, 0x40005e6b, 0x40005e6b, 0x31000e24, 0x31000e24}, 460 {0x0000a538, 0x40005e6b, 0x40005e6b, 0x30000828, 0x30000828},
485 {0x0000a53c, 0x44005e6d, 0x44005e6d, 0x34001640, 0x34001640}, 461 {0x0000a53c, 0x44005e6d, 0x44005e6d, 0x3400082a, 0x3400082a},
486 {0x0000a540, 0x49005e72, 0x49005e72, 0x38001660, 0x38001660}, 462 {0x0000a540, 0x49005e72, 0x49005e72, 0x38000849, 0x38000849},
487 {0x0000a544, 0x4e005eb2, 0x4e005eb2, 0x3b001861, 0x3b001861}, 463 {0x0000a544, 0x4e005eb2, 0x4e005eb2, 0x3b000a2c, 0x3b000a2c},
488 {0x0000a548, 0x53005f12, 0x53005f12, 0x3e001a81, 0x3e001a81}, 464 {0x0000a548, 0x53005f12, 0x53005f12, 0x3e000e2b, 0x3e000e2b},
489 {0x0000a54c, 0x59025eb5, 0x59025eb5, 0x42001a83, 0x42001a83}, 465 {0x0000a54c, 0x59025eb5, 0x59025eb5, 0x42000e2d, 0x42000e2d},
490 {0x0000a550, 0x5e025f12, 0x5e025f12, 0x44001c84, 0x44001c84}, 466 {0x0000a550, 0x5e025f12, 0x5e025f12, 0x4500124a, 0x4500124a},
491 {0x0000a554, 0x61027f12, 0x61027f12, 0x48001ce3, 0x48001ce3}, 467 {0x0000a554, 0x61027f12, 0x61027f12, 0x4900124c, 0x4900124c},
492 {0x0000a558, 0x6702bf12, 0x6702bf12, 0x4c001ce5, 0x4c001ce5}, 468 {0x0000a558, 0x6702bf12, 0x6702bf12, 0x4c00126c, 0x4c00126c},
493 {0x0000a55c, 0x6b02bf14, 0x6b02bf14, 0x50001ce9, 0x50001ce9}, 469 {0x0000a55c, 0x6b02bf14, 0x6b02bf14, 0x4f00128c, 0x4f00128c},
494 {0x0000a560, 0x6f02bf16, 0x6f02bf16, 0x54001ceb, 0x54001ceb}, 470 {0x0000a560, 0x6f02bf16, 0x6f02bf16, 0x52001290, 0x52001290},
495 {0x0000a564, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec}, 471 {0x0000a564, 0x6f02bf16, 0x6f02bf16, 0x56001292, 0x56001292},
496 {0x0000a568, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec}, 472 {0x0000a568, 0x6f02bf16, 0x6f02bf16, 0x56001292, 0x56001292},
497 {0x0000a56c, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec}, 473 {0x0000a56c, 0x6f02bf16, 0x6f02bf16, 0x56001292, 0x56001292},
498 {0x0000a570, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec}, 474 {0x0000a570, 0x6f02bf16, 0x6f02bf16, 0x56001292, 0x56001292},
499 {0x0000a574, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec}, 475 {0x0000a574, 0x6f02bf16, 0x6f02bf16, 0x56001292, 0x56001292},
500 {0x0000a578, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec}, 476 {0x0000a578, 0x6f02bf16, 0x6f02bf16, 0x56001292, 0x56001292},
501 {0x0000a57c, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec}, 477 {0x0000a57c, 0x6f02bf16, 0x6f02bf16, 0x56001292, 0x56001292},
502 {0x0000a580, 0x00802220, 0x00802220, 0x00800000, 0x00800000}, 478 {0x0000a580, 0x00802220, 0x00802220, 0x00800000, 0x00800000},
503 {0x0000a584, 0x04802222, 0x04802222, 0x04800002, 0x04800002}, 479 {0x0000a584, 0x04802222, 0x04802222, 0x02800001, 0x02800001},
504 {0x0000a588, 0x09802421, 0x09802421, 0x08800004, 0x08800004}, 480 {0x0000a588, 0x09802421, 0x09802421, 0x05800003, 0x05800003},
505 {0x0000a58c, 0x0d802621, 0x0d802621, 0x0b800200, 0x0b800200}, 481 {0x0000a58c, 0x0d802621, 0x0d802621, 0x0a800005, 0x0a800005},
506 {0x0000a590, 0x13804620, 0x13804620, 0x0f800202, 0x0f800202}, 482 {0x0000a590, 0x13804620, 0x13804620, 0x0e800201, 0x0e800201},
507 {0x0000a594, 0x19804a20, 0x19804a20, 0x11800400, 0x11800400}, 483 {0x0000a594, 0x19804a20, 0x19804a20, 0x11800203, 0x11800203},
508 {0x0000a598, 0x1d804e20, 0x1d804e20, 0x15800402, 0x15800402}, 484 {0x0000a598, 0x1d804e20, 0x1d804e20, 0x14800401, 0x14800401},
509 {0x0000a59c, 0x21805420, 0x21805420, 0x19800404, 0x19800404}, 485 {0x0000a59c, 0x21805420, 0x21805420, 0x18800403, 0x18800403},
510 {0x0000a5a0, 0x26805e20, 0x26805e20, 0x1b800603, 0x1b800603}, 486 {0x0000a5a0, 0x26805e20, 0x26805e20, 0x1b800602, 0x1b800602},
511 {0x0000a5a4, 0x2b805e40, 0x2b805e40, 0x1f800a02, 0x1f800a02}, 487 {0x0000a5a4, 0x2b805e40, 0x2b805e40, 0x1f800802, 0x1f800802},
512 {0x0000a5a8, 0x2f805e42, 0x2f805e42, 0x23800a04, 0x23800a04}, 488 {0x0000a5a8, 0x2f805e42, 0x2f805e42, 0x21800620, 0x21800620},
513 {0x0000a5ac, 0x33805e44, 0x33805e44, 0x26800a20, 0x26800a20}, 489 {0x0000a5ac, 0x33805e44, 0x33805e44, 0x25800820, 0x25800820},
514 {0x0000a5b0, 0x38805e65, 0x38805e65, 0x2a800e20, 0x2a800e20}, 490 {0x0000a5b0, 0x38805e65, 0x38805e65, 0x29800822, 0x29800822},
515 {0x0000a5b4, 0x3c805e69, 0x3c805e69, 0x2e800e22, 0x2e800e22}, 491 {0x0000a5b4, 0x3c805e69, 0x3c805e69, 0x2d800824, 0x2d800824},
516 {0x0000a5b8, 0x40805e6b, 0x40805e6b, 0x31800e24, 0x31800e24}, 492 {0x0000a5b8, 0x40805e6b, 0x40805e6b, 0x30800828, 0x30800828},
517 {0x0000a5bc, 0x44805e6d, 0x44805e6d, 0x34801640, 0x34801640}, 493 {0x0000a5bc, 0x44805e6d, 0x44805e6d, 0x3480082a, 0x3480082a},
518 {0x0000a5c0, 0x49805e72, 0x49805e72, 0x38801660, 0x38801660}, 494 {0x0000a5c0, 0x49805e72, 0x49805e72, 0x38800849, 0x38800849},
519 {0x0000a5c4, 0x4e805eb2, 0x4e805eb2, 0x3b801861, 0x3b801861}, 495 {0x0000a5c4, 0x4e805eb2, 0x4e805eb2, 0x3b800a2c, 0x3b800a2c},
520 {0x0000a5c8, 0x53805f12, 0x53805f12, 0x3e801a81, 0x3e801a81}, 496 {0x0000a5c8, 0x53805f12, 0x53805f12, 0x3e800e2b, 0x3e800e2b},
521 {0x0000a5cc, 0x59825eb2, 0x59825eb2, 0x42801a83, 0x42801a83}, 497 {0x0000a5cc, 0x59825eb2, 0x59825eb2, 0x42800e2d, 0x42800e2d},
522 {0x0000a5d0, 0x5e825f12, 0x5e825f12, 0x44801c84, 0x44801c84}, 498 {0x0000a5d0, 0x5e825f12, 0x5e825f12, 0x4580124a, 0x4580124a},
523 {0x0000a5d4, 0x61827f12, 0x61827f12, 0x48801ce3, 0x48801ce3}, 499 {0x0000a5d4, 0x61827f12, 0x61827f12, 0x4980124c, 0x4980124c},
524 {0x0000a5d8, 0x6782bf12, 0x6782bf12, 0x4c801ce5, 0x4c801ce5}, 500 {0x0000a5d8, 0x6782bf12, 0x6782bf12, 0x4c80126c, 0x4c80126c},
525 {0x0000a5dc, 0x6b82bf14, 0x6b82bf14, 0x50801ce9, 0x50801ce9}, 501 {0x0000a5dc, 0x6b82bf14, 0x6b82bf14, 0x4f80128c, 0x4f80128c},
526 {0x0000a5e0, 0x6f82bf16, 0x6f82bf16, 0x54801ceb, 0x54801ceb}, 502 {0x0000a5e0, 0x6f82bf16, 0x6f82bf16, 0x52801290, 0x52801290},
527 {0x0000a5e4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec}, 503 {0x0000a5e4, 0x6f82bf16, 0x6f82bf16, 0x56801292, 0x56801292},
528 {0x0000a5e8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec}, 504 {0x0000a5e8, 0x6f82bf16, 0x6f82bf16, 0x56801292, 0x56801292},
529 {0x0000a5ec, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec}, 505 {0x0000a5ec, 0x6f82bf16, 0x6f82bf16, 0x56801292, 0x56801292},
530 {0x0000a5f0, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec}, 506 {0x0000a5f0, 0x6f82bf16, 0x6f82bf16, 0x56801292, 0x56801292},
531 {0x0000a5f4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec}, 507 {0x0000a5f4, 0x6f82bf16, 0x6f82bf16, 0x56801292, 0x56801292},
532 {0x0000a5f8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec}, 508 {0x0000a5f8, 0x6f82bf16, 0x6f82bf16, 0x56801292, 0x56801292},
533 {0x0000a5fc, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec}, 509 {0x0000a5fc, 0x6f82bf16, 0x6f82bf16, 0x56801292, 0x56801292},
534 {0x00016044, 0x056db2db, 0x056db2db, 0x056db2db, 0x056db2db}, 510 {0x00016044, 0x056db2db, 0x056db2db, 0x022492db, 0x022492db},
535 {0x00016048, 0x24925266, 0x24925266, 0x24925266, 0x24925266}, 511 {0x00016048, 0x24925266, 0x24925266, 0x24925266, 0x24925266},
536 {0x00016444, 0x056db2db, 0x056db2db, 0x056db2db, 0x056db2db}, 512 {0x00016444, 0x056db2db, 0x056db2db, 0x022492db, 0x022492db},
537 {0x00016448, 0x24925266, 0x24925266, 0x24925266, 0x24925266}, 513 {0x00016448, 0x24925266, 0x24925266, 0x24925266, 0x24925266},
538}; 514};
539 515
540static const u32 ar9340Modes_high_ob_db_tx_gain_table_1p0[][5] = { 516static const u32 ar9340Modes_high_ob_db_tx_gain_table_1p0[][5] = {
541 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 517 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
518 {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
519 {0x0000a2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
520 {0x0000a2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
521 {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
542 {0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9}, 522 {0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9},
543 {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000}, 523 {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
544 {0x0000a504, 0x04002222, 0x04002222, 0x04000002, 0x04000002}, 524 {0x0000a504, 0x04002222, 0x04002222, 0x04000002, 0x04000002},
@@ -559,7 +539,7 @@ static const u32 ar9340Modes_high_ob_db_tx_gain_table_1p0[][5] = {
559 {0x0000a540, 0x49005e72, 0x49005e72, 0x38001660, 0x38001660}, 539 {0x0000a540, 0x49005e72, 0x49005e72, 0x38001660, 0x38001660},
560 {0x0000a544, 0x4e005eb2, 0x4e005eb2, 0x3b001861, 0x3b001861}, 540 {0x0000a544, 0x4e005eb2, 0x4e005eb2, 0x3b001861, 0x3b001861},
561 {0x0000a548, 0x53005f12, 0x53005f12, 0x3e001a81, 0x3e001a81}, 541 {0x0000a548, 0x53005f12, 0x53005f12, 0x3e001a81, 0x3e001a81},
562 {0x0000a54c, 0x59025eb5, 0x59025eb5, 0x42001a83, 0x42001a83}, 542 {0x0000a54c, 0x59025eb2, 0x59025eb2, 0x42001a83, 0x42001a83},
563 {0x0000a550, 0x5e025f12, 0x5e025f12, 0x44001c84, 0x44001c84}, 543 {0x0000a550, 0x5e025f12, 0x5e025f12, 0x44001c84, 0x44001c84},
564 {0x0000a554, 0x61027f12, 0x61027f12, 0x48001ce3, 0x48001ce3}, 544 {0x0000a554, 0x61027f12, 0x61027f12, 0x48001ce3, 0x48001ce3},
565 {0x0000a558, 0x6702bf12, 0x6702bf12, 0x4c001ce5, 0x4c001ce5}, 545 {0x0000a558, 0x6702bf12, 0x6702bf12, 0x4c001ce5, 0x4c001ce5},
@@ -604,13 +584,43 @@ static const u32 ar9340Modes_high_ob_db_tx_gain_table_1p0[][5] = {
604 {0x0000a5f4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec}, 584 {0x0000a5f4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
605 {0x0000a5f8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec}, 585 {0x0000a5f8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
606 {0x0000a5fc, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec}, 586 {0x0000a5fc, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
587 {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
588 {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
589 {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
590 {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
591 {0x0000a610, 0x00804000, 0x00804000, 0x00000000, 0x00000000},
592 {0x0000a614, 0x00804201, 0x00804201, 0x01404000, 0x01404000},
593 {0x0000a618, 0x0280c802, 0x0280c802, 0x01404501, 0x01404501},
594 {0x0000a61c, 0x0280ca03, 0x0280ca03, 0x02008501, 0x02008501},
595 {0x0000a620, 0x04c15104, 0x04c15104, 0x0280ca03, 0x0280ca03},
596 {0x0000a624, 0x04c15305, 0x04c15305, 0x03010c04, 0x03010c04},
597 {0x0000a628, 0x04c15305, 0x04c15305, 0x04014c04, 0x04014c04},
598 {0x0000a62c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
599 {0x0000a630, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
600 {0x0000a634, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
601 {0x0000a638, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
602 {0x0000a63c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
603 {0x0000b2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
604 {0x0000b2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
605 {0x0000b2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
606 {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
607 {0x00016044, 0x03b6d2e4, 0x03b6d2e4, 0x03b6d2e4, 0x03b6d2e4}, 607 {0x00016044, 0x03b6d2e4, 0x03b6d2e4, 0x03b6d2e4, 0x03b6d2e4},
608 {0x00016048, 0x8e481266, 0x8e481266, 0x8e481266, 0x8e481266}, 608 {0x00016048, 0x8e481666, 0x8e481666, 0x8e481266, 0x8e481266},
609 {0x00016280, 0x01000015, 0x01000015, 0x01001015, 0x01001015},
609 {0x00016444, 0x03b6d2e4, 0x03b6d2e4, 0x03b6d2e4, 0x03b6d2e4}, 610 {0x00016444, 0x03b6d2e4, 0x03b6d2e4, 0x03b6d2e4, 0x03b6d2e4},
610 {0x00016448, 0x8e481266, 0x8e481266, 0x8e481266, 0x8e481266}, 611 {0x00016448, 0x8e481666, 0x8e481666, 0x8e481266, 0x8e481266},
611}; 612};
613
612static const u32 ar9340Modes_ub124_tx_gain_table_1p0[][5] = { 614static const u32 ar9340Modes_ub124_tx_gain_table_1p0[][5] = {
613 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 615 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
616 {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005},
617 {0x00009820, 0x206a022e, 0x206a022e, 0x206a00ae, 0x206a00ae},
618 {0x00009830, 0x0000059c, 0x0000059c, 0x0000059c, 0x0000059c},
619 {0x00009e10, 0x7ec88d2e, 0x7ec88d2e, 0x7ec82d2e, 0x7ec82d2e},
620 {0x0000a2dc, 0xfef5d402, 0xfef5d402, 0xfdab5b52, 0xfdab5b52},
621 {0x0000a2e0, 0xfe896600, 0xfe896600, 0xfd339c84, 0xfd339c84},
622 {0x0000a2e4, 0xff01f800, 0xff01f800, 0xfec3e000, 0xfec3e000},
623 {0x0000a2e8, 0xfffe0000, 0xfffe0000, 0xfffc0000, 0xfffc0000},
614 {0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9}, 624 {0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9},
615 {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000}, 625 {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
616 {0x0000a504, 0x04002222, 0x04002222, 0x04000002, 0x04000002}, 626 {0x0000a504, 0x04002222, 0x04002222, 0x04000002, 0x04000002},
@@ -676,15 +686,34 @@ static const u32 ar9340Modes_ub124_tx_gain_table_1p0[][5] = {
676 {0x0000a5f4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec}, 686 {0x0000a5f4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
677 {0x0000a5f8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec}, 687 {0x0000a5f8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
678 {0x0000a5fc, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec}, 688 {0x0000a5fc, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
679 {0x00016044, 0x036db2db, 0x036db2db, 0x036db2db, 0x036db2db}, 689 {0x00016044, 0x03b6d2e4, 0x03b6d2e4, 0x03b6d2e4, 0x03b6d2e4},
680 {0x00016048, 0x69b65266, 0x69b65266, 0x69b65266, 0x69b65266}, 690 {0x00016048, 0x8e480086, 0x8e480086, 0x8e480086, 0x8e480086},
681 {0x00016444, 0x036db2db, 0x036db2db, 0x036db2db, 0x036db2db}, 691 {0x00016444, 0x03b6d2e4, 0x03b6d2e4, 0x03b6d2e4, 0x03b6d2e4},
682 {0x00016448, 0x69b65266, 0x69b65266, 0x69b65266, 0x69b65266}, 692 {0x00016448, 0x8e480086, 0x8e480086, 0x8e480086, 0x8e480086},
693 {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
694 {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
695 {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
696 {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
697 {0x0000a610, 0x00804000, 0x00804000, 0x00000000, 0x00000000},
698 {0x0000a614, 0x00804201, 0x00804201, 0x01404000, 0x01404000},
699 {0x0000a618, 0x0280c802, 0x0280c802, 0x01404501, 0x01404501},
700 {0x0000a61c, 0x0280ca03, 0x0280ca03, 0x02008501, 0x02008501},
701 {0x0000a620, 0x04c15104, 0x04c15104, 0x0280ca03, 0x0280ca03},
702 {0x0000a624, 0x04c15305, 0x04c15305, 0x03010c04, 0x03010c04},
703 {0x0000a628, 0x04c15305, 0x04c15305, 0x04014c04, 0x04014c04},
704 {0x0000a62c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
705 {0x0000a630, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
706 {0x0000a634, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
707 {0x0000a638, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
708 {0x0000a63c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
709 {0x0000b2dc, 0xfef5d402, 0xfef5d402, 0xfdab5b52, 0xfdab5b52},
710 {0x0000b2e0, 0xfe896600, 0xfe896600, 0xfd339c84, 0xfd339c84},
711 {0x0000b2e4, 0xff01f800, 0xff01f800, 0xfec3e000, 0xfec3e000},
712 {0x0000b2e8, 0xfffe0000, 0xfffe0000, 0xfffc0000, 0xfffc0000},
683}; 713};
684 714
685
686static const u32 ar9340Common_rx_gain_table_1p0[][2] = { 715static const u32 ar9340Common_rx_gain_table_1p0[][2] = {
687 /* Addr allmodes */ 716 /* Addr allmodes */
688 {0x0000a000, 0x00010000}, 717 {0x0000a000, 0x00010000},
689 {0x0000a004, 0x00030002}, 718 {0x0000a004, 0x00030002},
690 {0x0000a008, 0x00050004}, 719 {0x0000a008, 0x00050004},
@@ -845,14 +874,14 @@ static const u32 ar9340Common_rx_gain_table_1p0[][2] = {
845 {0x0000b074, 0x00000000}, 874 {0x0000b074, 0x00000000},
846 {0x0000b078, 0x00000000}, 875 {0x0000b078, 0x00000000},
847 {0x0000b07c, 0x00000000}, 876 {0x0000b07c, 0x00000000},
848 {0x0000b080, 0x32323232}, 877 {0x0000b080, 0x23232323},
849 {0x0000b084, 0x2f2f3232}, 878 {0x0000b084, 0x21232323},
850 {0x0000b088, 0x23282a2d}, 879 {0x0000b088, 0x19191c1e},
851 {0x0000b08c, 0x1c1e2123}, 880 {0x0000b08c, 0x12141417},
852 {0x0000b090, 0x14171919}, 881 {0x0000b090, 0x07070e0e},
853 {0x0000b094, 0x0e0e1214}, 882 {0x0000b094, 0x03030305},
854 {0x0000b098, 0x03050707}, 883 {0x0000b098, 0x00000003},
855 {0x0000b09c, 0x00030303}, 884 {0x0000b09c, 0x00000000},
856 {0x0000b0a0, 0x00000000}, 885 {0x0000b0a0, 0x00000000},
857 {0x0000b0a4, 0x00000000}, 886 {0x0000b0a4, 0x00000000},
858 {0x0000b0a8, 0x00000000}, 887 {0x0000b0a8, 0x00000000},
@@ -944,7 +973,11 @@ static const u32 ar9340Common_rx_gain_table_1p0[][2] = {
944}; 973};
945 974
946static const u32 ar9340Modes_low_ob_db_tx_gain_table_1p0[][5] = { 975static const u32 ar9340Modes_low_ob_db_tx_gain_table_1p0[][5] = {
947 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 976 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
977 {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
978 {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
979 {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
980 {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
948 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9}, 981 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
949 {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 982 {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
950 {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002}, 983 {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
@@ -952,8 +985,8 @@ static const u32 ar9340Modes_low_ob_db_tx_gain_table_1p0[][5] = {
952 {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200}, 985 {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
953 {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202}, 986 {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
954 {0x0000a514, 0x1c000223, 0x1c000223, 0x12000400, 0x12000400}, 987 {0x0000a514, 0x1c000223, 0x1c000223, 0x12000400, 0x12000400},
955 {0x0000a518, 0x21020220, 0x21020220, 0x16000402, 0x16000402}, 988 {0x0000a518, 0x21002220, 0x21002220, 0x16000402, 0x16000402},
956 {0x0000a51c, 0x27020223, 0x27020223, 0x19000404, 0x19000404}, 989 {0x0000a51c, 0x27002223, 0x27002223, 0x19000404, 0x19000404},
957 {0x0000a520, 0x2b022220, 0x2b022220, 0x1c000603, 0x1c000603}, 990 {0x0000a520, 0x2b022220, 0x2b022220, 0x1c000603, 0x1c000603},
958 {0x0000a524, 0x2f022222, 0x2f022222, 0x21000a02, 0x21000a02}, 991 {0x0000a524, 0x2f022222, 0x2f022222, 0x21000a02, 0x21000a02},
959 {0x0000a528, 0x34022225, 0x34022225, 0x25000a04, 0x25000a04}, 992 {0x0000a528, 0x34022225, 0x34022225, 0x25000a04, 0x25000a04},
@@ -965,19 +998,19 @@ static const u32 ar9340Modes_low_ob_db_tx_gain_table_1p0[][5] = {
965 {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660}, 998 {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660},
966 {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861}, 999 {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861},
967 {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81}, 1000 {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81},
968 {0x0000a54c, 0x5c04286b, 0x5c04286b, 0x47001a83, 0x47001a83}, 1001 {0x0000a54c, 0x5c02486b, 0x5c02486b, 0x47001a83, 0x47001a83},
969 {0x0000a550, 0x61042a6c, 0x61042a6c, 0x4a001c84, 0x4a001c84}, 1002 {0x0000a550, 0x61024a6c, 0x61024a6c, 0x4a001c84, 0x4a001c84},
970 {0x0000a554, 0x66062a6c, 0x66062a6c, 0x4e001ce3, 0x4e001ce3}, 1003 {0x0000a554, 0x66026a6c, 0x66026a6c, 0x4e001ce3, 0x4e001ce3},
971 {0x0000a558, 0x6b062e6c, 0x6b062e6c, 0x52001ce5, 0x52001ce5}, 1004 {0x0000a558, 0x6b026e6c, 0x6b026e6c, 0x52001ce5, 0x52001ce5},
972 {0x0000a55c, 0x7006308c, 0x7006308c, 0x56001ce9, 0x56001ce9}, 1005 {0x0000a55c, 0x7002708c, 0x7002708c, 0x56001ce9, 0x56001ce9},
973 {0x0000a560, 0x730a308a, 0x730a308a, 0x5a001ceb, 0x5a001ceb}, 1006 {0x0000a560, 0x7302b08a, 0x7302b08a, 0x5a001ceb, 0x5a001ceb},
974 {0x0000a564, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, 1007 {0x0000a564, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
975 {0x0000a568, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, 1008 {0x0000a568, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
976 {0x0000a56c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, 1009 {0x0000a56c, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
977 {0x0000a570, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, 1010 {0x0000a570, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
978 {0x0000a574, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, 1011 {0x0000a574, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
979 {0x0000a578, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, 1012 {0x0000a578, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
980 {0x0000a57c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec}, 1013 {0x0000a57c, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
981 {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000}, 1014 {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
982 {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002}, 1015 {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002},
983 {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004}, 1016 {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004},
@@ -1010,14 +1043,40 @@ static const u32 ar9340Modes_low_ob_db_tx_gain_table_1p0[][5] = {
1010 {0x0000a5f4, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec}, 1043 {0x0000a5f4, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
1011 {0x0000a5f8, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec}, 1044 {0x0000a5f8, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
1012 {0x0000a5fc, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec}, 1045 {0x0000a5fc, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
1046 {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1047 {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1048 {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1049 {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1050 {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1051 {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
1052 {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501},
1053 {0x0000a61c, 0x02008802, 0x02008802, 0x02008501, 0x02008501},
1054 {0x0000a620, 0x0300cc03, 0x0300cc03, 0x0280ca03, 0x0280ca03},
1055 {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04},
1056 {0x0000a628, 0x0300cc03, 0x0300cc03, 0x04014c04, 0x04014c04},
1057 {0x0000a62c, 0x03810c03, 0x03810c03, 0x04015005, 0x04015005},
1058 {0x0000a630, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
1059 {0x0000a634, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
1060 {0x0000a638, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
1061 {0x0000a63c, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
1062 {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
1063 {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
1064 {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
1065 {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
1013 {0x00016044, 0x056db2db, 0x056db2db, 0x056db2db, 0x056db2db}, 1066 {0x00016044, 0x056db2db, 0x056db2db, 0x056db2db, 0x056db2db},
1014 {0x00016048, 0x24925266, 0x24925266, 0x24925266, 0x24925266}, 1067 {0x00016048, 0x24925666, 0x24925666, 0x24925266, 0x24925266},
1068 {0x00016280, 0x01000015, 0x01000015, 0x01001015, 0x01001015},
1069 {0x00016288, 0xf0318000, 0xf0318000, 0xf0318000, 0xf0318000},
1015 {0x00016444, 0x056db2db, 0x056db2db, 0x056db2db, 0x056db2db}, 1070 {0x00016444, 0x056db2db, 0x056db2db, 0x056db2db, 0x056db2db},
1016 {0x00016448, 0x24925266, 0x24925266, 0x24925266, 0x24925266}, 1071 {0x00016448, 0x24925666, 0x24925666, 0x24925266, 0x24925266},
1017}; 1072};
1018 1073
1019static const u32 ar9340Modes_mixed_ob_db_tx_gain_table_1p0[][5] = { 1074static const u32 ar9340Modes_mixed_ob_db_tx_gain_table_1p0[][5] = {
1020 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 1075 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
1076 {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
1077 {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
1078 {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
1079 {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
1021 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9}, 1080 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
1022 {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 1081 {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1023 {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002}, 1082 {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
@@ -1025,8 +1084,8 @@ static const u32 ar9340Modes_mixed_ob_db_tx_gain_table_1p0[][5] = {
1025 {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200}, 1084 {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
1026 {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202}, 1085 {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
1027 {0x0000a514, 0x1c000223, 0x1c000223, 0x11000400, 0x11000400}, 1086 {0x0000a514, 0x1c000223, 0x1c000223, 0x11000400, 0x11000400},
1028 {0x0000a518, 0x21020220, 0x21020220, 0x15000402, 0x15000402}, 1087 {0x0000a518, 0x21002220, 0x21002220, 0x15000402, 0x15000402},
1029 {0x0000a51c, 0x27020223, 0x27020223, 0x19000404, 0x19000404}, 1088 {0x0000a51c, 0x27002223, 0x27002223, 0x19000404, 0x19000404},
1030 {0x0000a520, 0x2b022220, 0x2b022220, 0x1b000603, 0x1b000603}, 1089 {0x0000a520, 0x2b022220, 0x2b022220, 0x1b000603, 0x1b000603},
1031 {0x0000a524, 0x2f022222, 0x2f022222, 0x1f000a02, 0x1f000a02}, 1090 {0x0000a524, 0x2f022222, 0x2f022222, 0x1f000a02, 0x1f000a02},
1032 {0x0000a528, 0x34022225, 0x34022225, 0x23000a04, 0x23000a04}, 1091 {0x0000a528, 0x34022225, 0x34022225, 0x23000a04, 0x23000a04},
@@ -1038,19 +1097,19 @@ static const u32 ar9340Modes_mixed_ob_db_tx_gain_table_1p0[][5] = {
1038 {0x0000a540, 0x4e02246c, 0x4e02246c, 0x38001660, 0x38001660}, 1097 {0x0000a540, 0x4e02246c, 0x4e02246c, 0x38001660, 0x38001660},
1039 {0x0000a544, 0x5302266c, 0x5302266c, 0x3b001861, 0x3b001861}, 1098 {0x0000a544, 0x5302266c, 0x5302266c, 0x3b001861, 0x3b001861},
1040 {0x0000a548, 0x5702286c, 0x5702286c, 0x3e001a81, 0x3e001a81}, 1099 {0x0000a548, 0x5702286c, 0x5702286c, 0x3e001a81, 0x3e001a81},
1041 {0x0000a54c, 0x5c04286b, 0x5c04286b, 0x42001a83, 0x42001a83}, 1100 {0x0000a54c, 0x5c02486b, 0x5c02486b, 0x42001a83, 0x42001a83},
1042 {0x0000a550, 0x61042a6c, 0x61042a6c, 0x44001c84, 0x44001c84}, 1101 {0x0000a550, 0x61024a6c, 0x61024a6c, 0x44001c84, 0x44001c84},
1043 {0x0000a554, 0x66062a6c, 0x66062a6c, 0x48001ce3, 0x48001ce3}, 1102 {0x0000a554, 0x66026a6c, 0x66026a6c, 0x48001ce3, 0x48001ce3},
1044 {0x0000a558, 0x6b062e6c, 0x6b062e6c, 0x4c001ce5, 0x4c001ce5}, 1103 {0x0000a558, 0x6b026e6c, 0x6b026e6c, 0x4c001ce5, 0x4c001ce5},
1045 {0x0000a55c, 0x7006308c, 0x7006308c, 0x50001ce9, 0x50001ce9}, 1104 {0x0000a55c, 0x7002708c, 0x7002708c, 0x50001ce9, 0x50001ce9},
1046 {0x0000a560, 0x730a308a, 0x730a308a, 0x54001ceb, 0x54001ceb}, 1105 {0x0000a560, 0x7302b08a, 0x7302b08a, 0x54001ceb, 0x54001ceb},
1047 {0x0000a564, 0x770a308c, 0x770a308c, 0x56001eec, 0x56001eec}, 1106 {0x0000a564, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
1048 {0x0000a568, 0x770a308c, 0x770a308c, 0x56001eec, 0x56001eec}, 1107 {0x0000a568, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
1049 {0x0000a56c, 0x770a308c, 0x770a308c, 0x56001eec, 0x56001eec}, 1108 {0x0000a56c, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
1050 {0x0000a570, 0x770a308c, 0x770a308c, 0x56001eec, 0x56001eec}, 1109 {0x0000a570, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
1051 {0x0000a574, 0x770a308c, 0x770a308c, 0x56001eec, 0x56001eec}, 1110 {0x0000a574, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
1052 {0x0000a578, 0x770a308c, 0x770a308c, 0x56001eec, 0x56001eec}, 1111 {0x0000a578, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
1053 {0x0000a57c, 0x770a308c, 0x770a308c, 0x56001eec, 0x56001eec}, 1112 {0x0000a57c, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
1054 {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000}, 1113 {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
1055 {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002}, 1114 {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002},
1056 {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004}, 1115 {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004},
@@ -1083,14 +1142,36 @@ static const u32 ar9340Modes_mixed_ob_db_tx_gain_table_1p0[][5] = {
1083 {0x0000a5f4, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec}, 1142 {0x0000a5f4, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
1084 {0x0000a5f8, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec}, 1143 {0x0000a5f8, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
1085 {0x0000a5fc, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec}, 1144 {0x0000a5fc, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
1145 {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1146 {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1147 {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1148 {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1149 {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1150 {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
1151 {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501},
1152 {0x0000a61c, 0x02008802, 0x02008802, 0x02008501, 0x02008501},
1153 {0x0000a620, 0x0300cc03, 0x0300cc03, 0x0280ca03, 0x0280ca03},
1154 {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04},
1155 {0x0000a628, 0x0300cc03, 0x0300cc03, 0x04014c04, 0x04014c04},
1156 {0x0000a62c, 0x03810c03, 0x03810c03, 0x04015005, 0x04015005},
1157 {0x0000a630, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
1158 {0x0000a634, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
1159 {0x0000a638, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
1160 {0x0000a63c, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
1161 {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
1162 {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
1163 {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
1164 {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
1086 {0x00016044, 0x056db2db, 0x056db2db, 0x03b6d2e4, 0x03b6d2e4}, 1165 {0x00016044, 0x056db2db, 0x056db2db, 0x03b6d2e4, 0x03b6d2e4},
1087 {0x00016048, 0x24927266, 0x24927266, 0x8e483266, 0x8e483266}, 1166 {0x00016048, 0x24925666, 0x24925666, 0x8e481266, 0x8e481266},
1167 {0x00016280, 0x01000015, 0x01000015, 0x01001015, 0x01001015},
1168 {0x00016288, 0x30318000, 0x30318000, 0x00318000, 0x00318000},
1088 {0x00016444, 0x056db2db, 0x056db2db, 0x03b6d2e4, 0x03b6d2e4}, 1169 {0x00016444, 0x056db2db, 0x056db2db, 0x03b6d2e4, 0x03b6d2e4},
1089 {0x00016448, 0x24927266, 0x24927266, 0x8e482266, 0x8e482266}, 1170 {0x00016448, 0x24925666, 0x24925666, 0x8e481266, 0x8e481266},
1090}; 1171};
1091 1172
1092static const u32 ar9340_1p0_mac_core[][2] = { 1173static const u32 ar9340_1p0_mac_core[][2] = {
1093 /* Addr allmodes */ 1174 /* Addr allmodes */
1094 {0x00000008, 0x00000000}, 1175 {0x00000008, 0x00000000},
1095 {0x00000030, 0x00020085}, 1176 {0x00000030, 0x00020085},
1096 {0x00000034, 0x00000005}, 1177 {0x00000034, 0x00000005},
@@ -1119,6 +1200,7 @@ static const u32 ar9340_1p0_mac_core[][2] = {
1119 {0x00008004, 0x00000000}, 1200 {0x00008004, 0x00000000},
1120 {0x00008008, 0x00000000}, 1201 {0x00008008, 0x00000000},
1121 {0x0000800c, 0x00000000}, 1202 {0x0000800c, 0x00000000},
1203 {0x00008010, 0x00080800},
1122 {0x00008018, 0x00000000}, 1204 {0x00008018, 0x00000000},
1123 {0x00008020, 0x00000000}, 1205 {0x00008020, 0x00000000},
1124 {0x00008038, 0x00000000}, 1206 {0x00008038, 0x00000000},
@@ -1146,7 +1228,7 @@ static const u32 ar9340_1p0_mac_core[][2] = {
1146 {0x000080bc, 0x00000000}, 1228 {0x000080bc, 0x00000000},
1147 {0x000080c0, 0x2a800000}, 1229 {0x000080c0, 0x2a800000},
1148 {0x000080c4, 0x06900168}, 1230 {0x000080c4, 0x06900168},
1149 {0x000080c8, 0x13881c20}, 1231 {0x000080c8, 0x13881c22},
1150 {0x000080cc, 0x01f40000}, 1232 {0x000080cc, 0x01f40000},
1151 {0x000080d0, 0x00252500}, 1233 {0x000080d0, 0x00252500},
1152 {0x000080d4, 0x00a00000}, 1234 {0x000080d4, 0x00a00000},
@@ -1250,276 +1332,17 @@ static const u32 ar9340_1p0_mac_core[][2] = {
1250 {0x000083c4, 0x00000000}, 1332 {0x000083c4, 0x00000000},
1251 {0x000083c8, 0x00000000}, 1333 {0x000083c8, 0x00000000},
1252 {0x000083cc, 0x00000200}, 1334 {0x000083cc, 0x00000200},
1253 {0x000083d0, 0x000301ff}, 1335 {0x000083d0, 0x000101ff},
1254}; 1336};
1255 1337
1256static const u32 ar9340Common_wo_xlna_rx_gain_table_1p0[][2] = { 1338#define ar9340Common_wo_xlna_rx_gain_table_1p0 ar9300Common_wo_xlna_rx_gain_table_2p2
1257 /* Addr allmodes */
1258 {0x0000a000, 0x00010000},
1259 {0x0000a004, 0x00030002},
1260 {0x0000a008, 0x00050004},
1261 {0x0000a00c, 0x00810080},
1262 {0x0000a010, 0x00830082},
1263 {0x0000a014, 0x01810180},
1264 {0x0000a018, 0x01830182},
1265 {0x0000a01c, 0x01850184},
1266 {0x0000a020, 0x01890188},
1267 {0x0000a024, 0x018b018a},
1268 {0x0000a028, 0x018d018c},
1269 {0x0000a02c, 0x03820190},
1270 {0x0000a030, 0x03840383},
1271 {0x0000a034, 0x03880385},
1272 {0x0000a038, 0x038a0389},
1273 {0x0000a03c, 0x038c038b},
1274 {0x0000a040, 0x0390038d},
1275 {0x0000a044, 0x03920391},
1276 {0x0000a048, 0x03940393},
1277 {0x0000a04c, 0x03960395},
1278 {0x0000a050, 0x00000000},
1279 {0x0000a054, 0x00000000},
1280 {0x0000a058, 0x00000000},
1281 {0x0000a05c, 0x00000000},
1282 {0x0000a060, 0x00000000},
1283 {0x0000a064, 0x00000000},
1284 {0x0000a068, 0x00000000},
1285 {0x0000a06c, 0x00000000},
1286 {0x0000a070, 0x00000000},
1287 {0x0000a074, 0x00000000},
1288 {0x0000a078, 0x00000000},
1289 {0x0000a07c, 0x00000000},
1290 {0x0000a080, 0x29292929},
1291 {0x0000a084, 0x29292929},
1292 {0x0000a088, 0x29292929},
1293 {0x0000a08c, 0x29292929},
1294 {0x0000a090, 0x22292929},
1295 {0x0000a094, 0x1d1d2222},
1296 {0x0000a098, 0x0c111117},
1297 {0x0000a09c, 0x00030303},
1298 {0x0000a0a0, 0x00000000},
1299 {0x0000a0a4, 0x00000000},
1300 {0x0000a0a8, 0x00000000},
1301 {0x0000a0ac, 0x00000000},
1302 {0x0000a0b0, 0x00000000},
1303 {0x0000a0b4, 0x00000000},
1304 {0x0000a0b8, 0x00000000},
1305 {0x0000a0bc, 0x00000000},
1306 {0x0000a0c0, 0x001f0000},
1307 {0x0000a0c4, 0x01000101},
1308 {0x0000a0c8, 0x011e011f},
1309 {0x0000a0cc, 0x011c011d},
1310 {0x0000a0d0, 0x02030204},
1311 {0x0000a0d4, 0x02010202},
1312 {0x0000a0d8, 0x021f0200},
1313 {0x0000a0dc, 0x0302021e},
1314 {0x0000a0e0, 0x03000301},
1315 {0x0000a0e4, 0x031e031f},
1316 {0x0000a0e8, 0x0402031d},
1317 {0x0000a0ec, 0x04000401},
1318 {0x0000a0f0, 0x041e041f},
1319 {0x0000a0f4, 0x0502041d},
1320 {0x0000a0f8, 0x05000501},
1321 {0x0000a0fc, 0x051e051f},
1322 {0x0000a100, 0x06010602},
1323 {0x0000a104, 0x061f0600},
1324 {0x0000a108, 0x061d061e},
1325 {0x0000a10c, 0x07020703},
1326 {0x0000a110, 0x07000701},
1327 {0x0000a114, 0x00000000},
1328 {0x0000a118, 0x00000000},
1329 {0x0000a11c, 0x00000000},
1330 {0x0000a120, 0x00000000},
1331 {0x0000a124, 0x00000000},
1332 {0x0000a128, 0x00000000},
1333 {0x0000a12c, 0x00000000},
1334 {0x0000a130, 0x00000000},
1335 {0x0000a134, 0x00000000},
1336 {0x0000a138, 0x00000000},
1337 {0x0000a13c, 0x00000000},
1338 {0x0000a140, 0x001f0000},
1339 {0x0000a144, 0x01000101},
1340 {0x0000a148, 0x011e011f},
1341 {0x0000a14c, 0x011c011d},
1342 {0x0000a150, 0x02030204},
1343 {0x0000a154, 0x02010202},
1344 {0x0000a158, 0x021f0200},
1345 {0x0000a15c, 0x0302021e},
1346 {0x0000a160, 0x03000301},
1347 {0x0000a164, 0x031e031f},
1348 {0x0000a168, 0x0402031d},
1349 {0x0000a16c, 0x04000401},
1350 {0x0000a170, 0x041e041f},
1351 {0x0000a174, 0x0502041d},
1352 {0x0000a178, 0x05000501},
1353 {0x0000a17c, 0x051e051f},
1354 {0x0000a180, 0x06010602},
1355 {0x0000a184, 0x061f0600},
1356 {0x0000a188, 0x061d061e},
1357 {0x0000a18c, 0x07020703},
1358 {0x0000a190, 0x07000701},
1359 {0x0000a194, 0x00000000},
1360 {0x0000a198, 0x00000000},
1361 {0x0000a19c, 0x00000000},
1362 {0x0000a1a0, 0x00000000},
1363 {0x0000a1a4, 0x00000000},
1364 {0x0000a1a8, 0x00000000},
1365 {0x0000a1ac, 0x00000000},
1366 {0x0000a1b0, 0x00000000},
1367 {0x0000a1b4, 0x00000000},
1368 {0x0000a1b8, 0x00000000},
1369 {0x0000a1bc, 0x00000000},
1370 {0x0000a1c0, 0x00000000},
1371 {0x0000a1c4, 0x00000000},
1372 {0x0000a1c8, 0x00000000},
1373 {0x0000a1cc, 0x00000000},
1374 {0x0000a1d0, 0x00000000},
1375 {0x0000a1d4, 0x00000000},
1376 {0x0000a1d8, 0x00000000},
1377 {0x0000a1dc, 0x00000000},
1378 {0x0000a1e0, 0x00000000},
1379 {0x0000a1e4, 0x00000000},
1380 {0x0000a1e8, 0x00000000},
1381 {0x0000a1ec, 0x00000000},
1382 {0x0000a1f0, 0x00000396},
1383 {0x0000a1f4, 0x00000396},
1384 {0x0000a1f8, 0x00000396},
1385 {0x0000a1fc, 0x00000196},
1386 {0x0000b000, 0x00010000},
1387 {0x0000b004, 0x00030002},
1388 {0x0000b008, 0x00050004},
1389 {0x0000b00c, 0x00810080},
1390 {0x0000b010, 0x00830082},
1391 {0x0000b014, 0x01810180},
1392 {0x0000b018, 0x01830182},
1393 {0x0000b01c, 0x01850184},
1394 {0x0000b020, 0x02810280},
1395 {0x0000b024, 0x02830282},
1396 {0x0000b028, 0x02850284},
1397 {0x0000b02c, 0x02890288},
1398 {0x0000b030, 0x028b028a},
1399 {0x0000b034, 0x0388028c},
1400 {0x0000b038, 0x038a0389},
1401 {0x0000b03c, 0x038c038b},
1402 {0x0000b040, 0x0390038d},
1403 {0x0000b044, 0x03920391},
1404 {0x0000b048, 0x03940393},
1405 {0x0000b04c, 0x03960395},
1406 {0x0000b050, 0x00000000},
1407 {0x0000b054, 0x00000000},
1408 {0x0000b058, 0x00000000},
1409 {0x0000b05c, 0x00000000},
1410 {0x0000b060, 0x00000000},
1411 {0x0000b064, 0x00000000},
1412 {0x0000b068, 0x00000000},
1413 {0x0000b06c, 0x00000000},
1414 {0x0000b070, 0x00000000},
1415 {0x0000b074, 0x00000000},
1416 {0x0000b078, 0x00000000},
1417 {0x0000b07c, 0x00000000},
1418 {0x0000b080, 0x32323232},
1419 {0x0000b084, 0x2f2f3232},
1420 {0x0000b088, 0x23282a2d},
1421 {0x0000b08c, 0x1c1e2123},
1422 {0x0000b090, 0x14171919},
1423 {0x0000b094, 0x0e0e1214},
1424 {0x0000b098, 0x03050707},
1425 {0x0000b09c, 0x00030303},
1426 {0x0000b0a0, 0x00000000},
1427 {0x0000b0a4, 0x00000000},
1428 {0x0000b0a8, 0x00000000},
1429 {0x0000b0ac, 0x00000000},
1430 {0x0000b0b0, 0x00000000},
1431 {0x0000b0b4, 0x00000000},
1432 {0x0000b0b8, 0x00000000},
1433 {0x0000b0bc, 0x00000000},
1434 {0x0000b0c0, 0x003f0020},
1435 {0x0000b0c4, 0x00400041},
1436 {0x0000b0c8, 0x0140005f},
1437 {0x0000b0cc, 0x0160015f},
1438 {0x0000b0d0, 0x017e017f},
1439 {0x0000b0d4, 0x02410242},
1440 {0x0000b0d8, 0x025f0240},
1441 {0x0000b0dc, 0x027f0260},
1442 {0x0000b0e0, 0x0341027e},
1443 {0x0000b0e4, 0x035f0340},
1444 {0x0000b0e8, 0x037f0360},
1445 {0x0000b0ec, 0x04400441},
1446 {0x0000b0f0, 0x0460045f},
1447 {0x0000b0f4, 0x0541047f},
1448 {0x0000b0f8, 0x055f0540},
1449 {0x0000b0fc, 0x057f0560},
1450 {0x0000b100, 0x06400641},
1451 {0x0000b104, 0x0660065f},
1452 {0x0000b108, 0x067e067f},
1453 {0x0000b10c, 0x07410742},
1454 {0x0000b110, 0x075f0740},
1455 {0x0000b114, 0x077f0760},
1456 {0x0000b118, 0x07800781},
1457 {0x0000b11c, 0x07a0079f},
1458 {0x0000b120, 0x07c107bf},
1459 {0x0000b124, 0x000007c0},
1460 {0x0000b128, 0x00000000},
1461 {0x0000b12c, 0x00000000},
1462 {0x0000b130, 0x00000000},
1463 {0x0000b134, 0x00000000},
1464 {0x0000b138, 0x00000000},
1465 {0x0000b13c, 0x00000000},
1466 {0x0000b140, 0x003f0020},
1467 {0x0000b144, 0x00400041},
1468 {0x0000b148, 0x0140005f},
1469 {0x0000b14c, 0x0160015f},
1470 {0x0000b150, 0x017e017f},
1471 {0x0000b154, 0x02410242},
1472 {0x0000b158, 0x025f0240},
1473 {0x0000b15c, 0x027f0260},
1474 {0x0000b160, 0x0341027e},
1475 {0x0000b164, 0x035f0340},
1476 {0x0000b168, 0x037f0360},
1477 {0x0000b16c, 0x04400441},
1478 {0x0000b170, 0x0460045f},
1479 {0x0000b174, 0x0541047f},
1480 {0x0000b178, 0x055f0540},
1481 {0x0000b17c, 0x057f0560},
1482 {0x0000b180, 0x06400641},
1483 {0x0000b184, 0x0660065f},
1484 {0x0000b188, 0x067e067f},
1485 {0x0000b18c, 0x07410742},
1486 {0x0000b190, 0x075f0740},
1487 {0x0000b194, 0x077f0760},
1488 {0x0000b198, 0x07800781},
1489 {0x0000b19c, 0x07a0079f},
1490 {0x0000b1a0, 0x07c107bf},
1491 {0x0000b1a4, 0x000007c0},
1492 {0x0000b1a8, 0x00000000},
1493 {0x0000b1ac, 0x00000000},
1494 {0x0000b1b0, 0x00000000},
1495 {0x0000b1b4, 0x00000000},
1496 {0x0000b1b8, 0x00000000},
1497 {0x0000b1bc, 0x00000000},
1498 {0x0000b1c0, 0x00000000},
1499 {0x0000b1c4, 0x00000000},
1500 {0x0000b1c8, 0x00000000},
1501 {0x0000b1cc, 0x00000000},
1502 {0x0000b1d0, 0x00000000},
1503 {0x0000b1d4, 0x00000000},
1504 {0x0000b1d8, 0x00000000},
1505 {0x0000b1dc, 0x00000000},
1506 {0x0000b1e0, 0x00000000},
1507 {0x0000b1e4, 0x00000000},
1508 {0x0000b1e8, 0x00000000},
1509 {0x0000b1ec, 0x00000000},
1510 {0x0000b1f0, 0x00000396},
1511 {0x0000b1f4, 0x00000396},
1512 {0x0000b1f8, 0x00000396},
1513 {0x0000b1fc, 0x00000196},
1514};
1515 1339
1516static const u32 ar9340_1p0_soc_preamble[][2] = { 1340static const u32 ar9340_1p0_soc_preamble[][2] = {
1517 /* Addr allmodes */ 1341 /* Addr allmodes */
1518 {0x000040a4, 0x00a0c1c9},
1519 {0x00007008, 0x00000000}, 1342 {0x00007008, 0x00000000},
1520 {0x00007020, 0x00000000}, 1343 {0x00007020, 0x00000000},
1521 {0x00007034, 0x00000002}, 1344 {0x00007034, 0x00000002},
1522 {0x00007038, 0x000004c2}, 1345 {0x00007038, 0x000004c2},
1523}; 1346};
1524 1347
1525#endif 1348#endif /* INITVALS_9340_H */
diff --git a/drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h b/drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h
index 1d6658e139b5..4ef7dcccaa2f 100644
--- a/drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h
@@ -1,5 +1,6 @@
1/* 1/*
2 * Copyright (c) 2010 Atheros Communications Inc. 2 * Copyright (c) 2010-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2012 Qualcomm Atheros Inc.
3 * 4 *
4 * Permission to use, copy, modify, and/or distribute this software for any 5 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above 6 * purpose with or without fee is hereby granted, provided that the above
@@ -52,7 +53,7 @@ static const u32 ar9462_2p0_baseband_postamble[][5] = {
52 {0x00009e04, 0x001c2020, 0x001c2020, 0x001c2020, 0x001c2020}, 53 {0x00009e04, 0x001c2020, 0x001c2020, 0x001c2020, 0x001c2020},
53 {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000d8}, 54 {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000d8},
54 {0x00009e10, 0x92c88d2e, 0x7ec88d2e, 0x7ec84d2e, 0x7ec86d2e}, 55 {0x00009e10, 0x92c88d2e, 0x7ec88d2e, 0x7ec84d2e, 0x7ec86d2e},
55 {0x00009e14, 0x37b95d5e, 0x37b9605e, 0x3376605e, 0x33795d5e}, 56 {0x00009e14, 0x37b95d5e, 0x37b9605e, 0x3376605e, 0x32395d5e},
56 {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 57 {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
57 {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c}, 58 {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
58 {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce}, 59 {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
@@ -61,7 +62,7 @@ static const u32 ar9462_2p0_baseband_postamble[][5] = {
61 {0x00009e44, 0x62321e27, 0x62321e27, 0xfe291e27, 0xfe291e27}, 62 {0x00009e44, 0x62321e27, 0x62321e27, 0xfe291e27, 0xfe291e27},
62 {0x00009e48, 0x5030201a, 0x5030201a, 0x50302012, 0x50302012}, 63 {0x00009e48, 0x5030201a, 0x5030201a, 0x50302012, 0x50302012},
63 {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000}, 64 {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
64 {0x0000a204, 0x013187c0, 0x013187c4, 0x013187c4, 0x013187c0}, 65 {0x0000a204, 0x01318fc0, 0x01318fc4, 0x01318fc4, 0x01318fc0},
65 {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004}, 66 {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004},
66 {0x0000a22c, 0x01026a2f, 0x01026a27, 0x01026a2f, 0x01026a2f}, 67 {0x0000a22c, 0x01026a2f, 0x01026a27, 0x01026a2f, 0x01026a2f},
67 {0x0000a230, 0x0000400a, 0x00004014, 0x00004016, 0x0000400b}, 68 {0x0000a230, 0x0000400a, 0x00004014, 0x00004016, 0x0000400b},
@@ -958,7 +959,7 @@ static const u32 ar9462_2p0_radio_core[][2] = {
958 {0x0001604c, 0x2699e04f}, 959 {0x0001604c, 0x2699e04f},
959 {0x00016050, 0x6db6db6c}, 960 {0x00016050, 0x6db6db6c},
960 {0x00016058, 0x6c200000}, 961 {0x00016058, 0x6c200000},
961 {0x00016080, 0x00040000}, 962 {0x00016080, 0x000c0000},
962 {0x00016084, 0x9a68048c}, 963 {0x00016084, 0x9a68048c},
963 {0x00016088, 0x54214514}, 964 {0x00016088, 0x54214514},
964 {0x0001608c, 0x1203040b}, 965 {0x0001608c, 0x1203040b},
@@ -981,7 +982,7 @@ static const u32 ar9462_2p0_radio_core[][2] = {
981 {0x00016144, 0x02084080}, 982 {0x00016144, 0x02084080},
982 {0x00016148, 0x000080c0}, 983 {0x00016148, 0x000080c0},
983 {0x00016280, 0x050a0001}, 984 {0x00016280, 0x050a0001},
984 {0x00016284, 0x3d841400}, 985 {0x00016284, 0x3d841418},
985 {0x00016288, 0x00000000}, 986 {0x00016288, 0x00000000},
986 {0x0001628c, 0xe3000000}, 987 {0x0001628c, 0xe3000000},
987 {0x00016290, 0xa1005080}, 988 {0x00016290, 0xa1005080},
@@ -1007,6 +1008,7 @@ static const u32 ar9462_2p0_radio_core[][2] = {
1007 1008
1008static const u32 ar9462_2p0_soc_preamble[][2] = { 1009static const u32 ar9462_2p0_soc_preamble[][2] = {
1009 /* Addr allmodes */ 1010 /* Addr allmodes */
1011 {0x000040a4, 0x00a0c1c9},
1010 {0x00007020, 0x00000000}, 1012 {0x00007020, 0x00000000},
1011 {0x00007034, 0x00000002}, 1013 {0x00007034, 0x00000002},
1012 {0x00007038, 0x000004c2}, 1014 {0x00007038, 0x000004c2},
diff --git a/drivers/net/wireless/ath/ath9k/ar9485_initvals.h b/drivers/net/wireless/ath/ath9k/ar9485_initvals.h
index d16d029f81a9..fb4497fc7a3d 100644
--- a/drivers/net/wireless/ath/ath9k/ar9485_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9485_initvals.h
@@ -1,5 +1,6 @@
1/* 1/*
2 * Copyright (c) 2010-2011 Atheros Communications Inc. 2 * Copyright (c) 2010-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2012 Qualcomm Atheros Inc.
3 * 4 *
4 * Permission to use, copy, modify, and/or distribute this software for any 5 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above 6 * purpose with or without fee is hereby granted, provided that the above
@@ -17,360 +18,151 @@
17#ifndef INITVALS_9485_H 18#ifndef INITVALS_9485_H
18#define INITVALS_9485_H 19#define INITVALS_9485_H
19 20
20static const u32 ar9485_1_1_mac_core[][2] = { 21/* AR9485 1.0 */
21 /* Addr allmodes */
22 {0x00000008, 0x00000000},
23 {0x00000030, 0x00020085},
24 {0x00000034, 0x00000005},
25 {0x00000040, 0x00000000},
26 {0x00000044, 0x00000000},
27 {0x00000048, 0x00000008},
28 {0x0000004c, 0x00000010},
29 {0x00000050, 0x00000000},
30 {0x00001040, 0x002ffc0f},
31 {0x00001044, 0x002ffc0f},
32 {0x00001048, 0x002ffc0f},
33 {0x0000104c, 0x002ffc0f},
34 {0x00001050, 0x002ffc0f},
35 {0x00001054, 0x002ffc0f},
36 {0x00001058, 0x002ffc0f},
37 {0x0000105c, 0x002ffc0f},
38 {0x00001060, 0x002ffc0f},
39 {0x00001064, 0x002ffc0f},
40 {0x000010f0, 0x00000100},
41 {0x00001270, 0x00000000},
42 {0x000012b0, 0x00000000},
43 {0x000012f0, 0x00000000},
44 {0x0000143c, 0x00000000},
45 {0x0000147c, 0x00000000},
46 {0x00008000, 0x00000000},
47 {0x00008004, 0x00000000},
48 {0x00008008, 0x00000000},
49 {0x0000800c, 0x00000000},
50 {0x00008018, 0x00000000},
51 {0x00008020, 0x00000000},
52 {0x00008038, 0x00000000},
53 {0x0000803c, 0x00000000},
54 {0x00008040, 0x00000000},
55 {0x00008044, 0x00000000},
56 {0x00008048, 0x00000000},
57 {0x0000804c, 0xffffffff},
58 {0x00008054, 0x00000000},
59 {0x00008058, 0x00000000},
60 {0x0000805c, 0x000fc78f},
61 {0x00008060, 0x0000000f},
62 {0x00008064, 0x00000000},
63 {0x00008070, 0x00000310},
64 {0x00008074, 0x00000020},
65 {0x00008078, 0x00000000},
66 {0x0000809c, 0x0000000f},
67 {0x000080a0, 0x00000000},
68 {0x000080a4, 0x02ff0000},
69 {0x000080a8, 0x0e070605},
70 {0x000080ac, 0x0000000d},
71 {0x000080b0, 0x00000000},
72 {0x000080b4, 0x00000000},
73 {0x000080b8, 0x00000000},
74 {0x000080bc, 0x00000000},
75 {0x000080c0, 0x2a800000},
76 {0x000080c4, 0x06900168},
77 {0x000080c8, 0x13881c22},
78 {0x000080cc, 0x01f40000},
79 {0x000080d0, 0x00252500},
80 {0x000080d4, 0x00a00000},
81 {0x000080d8, 0x00400000},
82 {0x000080dc, 0x00000000},
83 {0x000080e0, 0xffffffff},
84 {0x000080e4, 0x0000ffff},
85 {0x000080e8, 0x3f3f3f3f},
86 {0x000080ec, 0x00000000},
87 {0x000080f0, 0x00000000},
88 {0x000080f4, 0x00000000},
89 {0x000080fc, 0x00020000},
90 {0x00008100, 0x00000000},
91 {0x00008108, 0x00000052},
92 {0x0000810c, 0x00000000},
93 {0x00008110, 0x00000000},
94 {0x00008114, 0x000007ff},
95 {0x00008118, 0x000000aa},
96 {0x0000811c, 0x00003210},
97 {0x00008124, 0x00000000},
98 {0x00008128, 0x00000000},
99 {0x0000812c, 0x00000000},
100 {0x00008130, 0x00000000},
101 {0x00008134, 0x00000000},
102 {0x00008138, 0x00000000},
103 {0x0000813c, 0x0000ffff},
104 {0x00008144, 0xffffffff},
105 {0x00008168, 0x00000000},
106 {0x0000816c, 0x00000000},
107 {0x00008170, 0x18486200},
108 {0x00008174, 0x33332210},
109 {0x00008178, 0x00000000},
110 {0x0000817c, 0x00020000},
111 {0x000081c0, 0x00000000},
112 {0x000081c4, 0x33332210},
113 {0x000081d4, 0x00000000},
114 {0x000081ec, 0x00000000},
115 {0x000081f0, 0x00000000},
116 {0x000081f4, 0x00000000},
117 {0x000081f8, 0x00000000},
118 {0x000081fc, 0x00000000},
119 {0x00008240, 0x00100000},
120 {0x00008244, 0x0010f400},
121 {0x00008248, 0x00000800},
122 {0x0000824c, 0x0001e800},
123 {0x00008250, 0x00000000},
124 {0x00008254, 0x00000000},
125 {0x00008258, 0x00000000},
126 {0x0000825c, 0x40000000},
127 {0x00008260, 0x00080922},
128 {0x00008264, 0x9ca00010},
129 {0x00008268, 0xffffffff},
130 {0x0000826c, 0x0000ffff},
131 {0x00008270, 0x00000000},
132 {0x00008274, 0x40000000},
133 {0x00008278, 0x003e4180},
134 {0x0000827c, 0x00000004},
135 {0x00008284, 0x0000002c},
136 {0x00008288, 0x0000002c},
137 {0x0000828c, 0x000000ff},
138 {0x00008294, 0x00000000},
139 {0x00008298, 0x00000000},
140 {0x0000829c, 0x00000000},
141 {0x00008300, 0x00000140},
142 {0x00008314, 0x00000000},
143 {0x0000831c, 0x0000010d},
144 {0x00008328, 0x00000000},
145 {0x0000832c, 0x00000007},
146 {0x00008330, 0x00000302},
147 {0x00008334, 0x00000700},
148 {0x00008338, 0x00ff0000},
149 {0x0000833c, 0x02400000},
150 {0x00008340, 0x000107ff},
151 {0x00008344, 0xa248105b},
152 {0x00008348, 0x008f0000},
153 {0x0000835c, 0x00000000},
154 {0x00008360, 0xffffffff},
155 {0x00008364, 0xffffffff},
156 {0x00008368, 0x00000000},
157 {0x00008370, 0x00000000},
158 {0x00008374, 0x000000ff},
159 {0x00008378, 0x00000000},
160 {0x0000837c, 0x00000000},
161 {0x00008380, 0xffffffff},
162 {0x00008384, 0xffffffff},
163 {0x00008390, 0xffffffff},
164 {0x00008394, 0xffffffff},
165 {0x00008398, 0x00000000},
166 {0x0000839c, 0x00000000},
167 {0x000083a0, 0x00000000},
168 {0x000083a4, 0x0000fa14},
169 {0x000083a8, 0x000f0c00},
170 {0x000083ac, 0x33332210},
171 {0x000083b0, 0x33332210},
172 {0x000083b4, 0x33332210},
173 {0x000083b8, 0x33332210},
174 {0x000083bc, 0x00000000},
175 {0x000083c0, 0x00000000},
176 {0x000083c4, 0x00000000},
177 {0x000083c8, 0x00000000},
178 {0x000083cc, 0x00000200},
179 {0x000083d0, 0x000301ff},
180};
181 22
182static const u32 ar9485_1_1_baseband_core[][2] = { 23#define ar9485_1_1_mac_postamble ar9300_2p2_mac_postamble
183 /* Addr allmodes */
184 {0x00009800, 0xafe68e30},
185 {0x00009804, 0xfd14e000},
186 {0x00009808, 0x9c0a8f6b},
187 {0x0000980c, 0x04800000},
188 {0x00009814, 0x9280c00a},
189 {0x00009818, 0x00000000},
190 {0x0000981c, 0x00020028},
191 {0x00009834, 0x5f3ca3de},
192 {0x00009838, 0x0108ecff},
193 {0x0000983c, 0x14750600},
194 {0x00009880, 0x201fff00},
195 {0x00009884, 0x00001042},
196 {0x000098a4, 0x00200400},
197 {0x000098b0, 0x52440bbe},
198 {0x000098d0, 0x004b6a8e},
199 {0x000098d4, 0x00000820},
200 {0x000098dc, 0x00000000},
201 {0x000098f0, 0x00000000},
202 {0x000098f4, 0x00000000},
203 {0x00009c04, 0x00000000},
204 {0x00009c08, 0x03200000},
205 {0x00009c0c, 0x00000000},
206 {0x00009c10, 0x00000000},
207 {0x00009c14, 0x00046384},
208 {0x00009c18, 0x05b6b440},
209 {0x00009c1c, 0x00b6b440},
210 {0x00009d00, 0xc080a333},
211 {0x00009d04, 0x40206c10},
212 {0x00009d08, 0x009c4060},
213 {0x00009d0c, 0x1883800a},
214 {0x00009d10, 0x01834061},
215 {0x00009d14, 0x00c00400},
216 {0x00009d18, 0x00000000},
217 {0x00009d1c, 0x00000000},
218 {0x00009e08, 0x0038233c},
219 {0x00009e24, 0x9927b515},
220 {0x00009e28, 0x12ef0200},
221 {0x00009e30, 0x06336f77},
222 {0x00009e34, 0x6af6532f},
223 {0x00009e38, 0x0cc80c00},
224 {0x00009e40, 0x0d261820},
225 {0x00009e4c, 0x00001004},
226 {0x00009e50, 0x00ff03f1},
227 {0x00009fc0, 0x80be4788},
228 {0x00009fc4, 0x0001efb5},
229 {0x00009fcc, 0x40000014},
230 {0x0000a20c, 0x00000000},
231 {0x0000a210, 0x00000000},
232 {0x0000a220, 0x00000000},
233 {0x0000a224, 0x00000000},
234 {0x0000a228, 0x10002310},
235 {0x0000a23c, 0x00000000},
236 {0x0000a244, 0x0c000000},
237 {0x0000a2a0, 0x00000001},
238 {0x0000a2c0, 0x00000001},
239 {0x0000a2c8, 0x00000000},
240 {0x0000a2cc, 0x18c43433},
241 {0x0000a2d4, 0x00000000},
242 {0x0000a2dc, 0x00000000},
243 {0x0000a2e0, 0x00000000},
244 {0x0000a2e4, 0x00000000},
245 {0x0000a2e8, 0x00000000},
246 {0x0000a2ec, 0x00000000},
247 {0x0000a2f0, 0x00000000},
248 {0x0000a2f4, 0x00000000},
249 {0x0000a2f8, 0x00000000},
250 {0x0000a344, 0x00000000},
251 {0x0000a34c, 0x00000000},
252 {0x0000a350, 0x0000a000},
253 {0x0000a364, 0x00000000},
254 {0x0000a370, 0x00000000},
255 {0x0000a390, 0x00000001},
256 {0x0000a394, 0x00000444},
257 {0x0000a398, 0x001f0e0f},
258 {0x0000a39c, 0x0075393f},
259 {0x0000a3a0, 0xb79f6427},
260 {0x0000a3a4, 0x000000ff},
261 {0x0000a3a8, 0x3b3b3b3b},
262 {0x0000a3ac, 0x2f2f2f2f},
263 {0x0000a3c0, 0x20202020},
264 {0x0000a3c4, 0x22222220},
265 {0x0000a3c8, 0x20200020},
266 {0x0000a3cc, 0x20202020},
267 {0x0000a3d0, 0x20202020},
268 {0x0000a3d4, 0x20202020},
269 {0x0000a3d8, 0x20202020},
270 {0x0000a3dc, 0x20202020},
271 {0x0000a3e0, 0x20202020},
272 {0x0000a3e4, 0x20202020},
273 {0x0000a3e8, 0x20202020},
274 {0x0000a3ec, 0x20202020},
275 {0x0000a3f0, 0x00000000},
276 {0x0000a3f4, 0x00000006},
277 {0x0000a3f8, 0x0cdbd380},
278 {0x0000a3fc, 0x000f0f01},
279 {0x0000a400, 0x8fa91f01},
280 {0x0000a404, 0x00000000},
281 {0x0000a408, 0x0e79e5c6},
282 {0x0000a40c, 0x00820820},
283 {0x0000a414, 0x1ce739cf},
284 {0x0000a418, 0x2d0019ce},
285 {0x0000a41c, 0x1ce739ce},
286 {0x0000a420, 0x000001ce},
287 {0x0000a424, 0x1ce739ce},
288 {0x0000a428, 0x000001ce},
289 {0x0000a42c, 0x1ce739ce},
290 {0x0000a430, 0x1ce739ce},
291 {0x0000a434, 0x00000000},
292 {0x0000a438, 0x00001801},
293 {0x0000a43c, 0x00000000},
294 {0x0000a440, 0x00000000},
295 {0x0000a444, 0x00000000},
296 {0x0000a448, 0x04000000},
297 {0x0000a44c, 0x00000001},
298 {0x0000a450, 0x00010000},
299 {0x0000a5c4, 0xbfad9d74},
300 {0x0000a5c8, 0x0048060a},
301 {0x0000a5cc, 0x00000637},
302 {0x0000a760, 0x03020100},
303 {0x0000a764, 0x09080504},
304 {0x0000a768, 0x0d0c0b0a},
305 {0x0000a76c, 0x13121110},
306 {0x0000a770, 0x31301514},
307 {0x0000a774, 0x35343332},
308 {0x0000a778, 0x00000036},
309 {0x0000a780, 0x00000838},
310 {0x0000a7c0, 0x00000000},
311 {0x0000a7c4, 0xfffffffc},
312 {0x0000a7c8, 0x00000000},
313 {0x0000a7cc, 0x00000000},
314 {0x0000a7d0, 0x00000000},
315 {0x0000a7d4, 0x00000004},
316 {0x0000a7dc, 0x00000000},
317};
318 24
319static const u32 ar9485Common_1_1[][2] = { 25static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_disable_L1[][2] = {
320 /* Addr allmodes */ 26 /* Addr allmodes */
321 {0x00007010, 0x00000022}, 27 {0x00018c00, 0x18012e5e},
322 {0x00007020, 0x00000000}, 28 {0x00018c04, 0x000801d8},
323 {0x00007034, 0x00000002}, 29 {0x00018c08, 0x0000080c},
324 {0x00007038, 0x000004c2},
325}; 30};
326 31
327static const u32 ar9485_1_1_baseband_postamble[][5] = { 32static const u32 ar9485Common_wo_xlna_rx_gain_1_1[][2] = {
328 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 33 /* Addr allmodes */
329 {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005}, 34 {0x0000a000, 0x00060005},
330 {0x00009820, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e}, 35 {0x0000a004, 0x00810080},
331 {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0}, 36 {0x0000a008, 0x00830082},
332 {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881}, 37 {0x0000a00c, 0x00850084},
333 {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4}, 38 {0x0000a010, 0x01820181},
334 {0x00009830, 0x0000059c, 0x0000059c, 0x0000059c, 0x0000059c}, 39 {0x0000a014, 0x01840183},
335 {0x00009c00, 0x00000044, 0x00000044, 0x00000044, 0x00000044}, 40 {0x0000a018, 0x01880185},
336 {0x00009e00, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0}, 41 {0x0000a01c, 0x018a0189},
337 {0x00009e04, 0x00182020, 0x00182020, 0x00182020, 0x00182020}, 42 {0x0000a020, 0x02850284},
338 {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2}, 43 {0x0000a024, 0x02890288},
339 {0x00009e10, 0x7ec88d2e, 0x7ec88d2e, 0x7ec80d2e, 0x7ec80d2e}, 44 {0x0000a028, 0x028b028a},
340 {0x00009e14, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e}, 45 {0x0000a02c, 0x03850384},
341 {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 46 {0x0000a030, 0x03890388},
342 {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c}, 47 {0x0000a034, 0x038b038a},
343 {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce}, 48 {0x0000a038, 0x038d038c},
344 {0x00009e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021}, 49 {0x0000a03c, 0x03910390},
345 {0x00009e3c, 0xcf946220, 0xcf946220, 0xcf946222, 0xcf946222}, 50 {0x0000a040, 0x03930392},
346 {0x00009e44, 0x02321e27, 0x02321e27, 0x02282324, 0x02282324}, 51 {0x0000a044, 0x03950394},
347 {0x00009e48, 0x5030201a, 0x5030201a, 0x50302010, 0x50302010}, 52 {0x0000a048, 0x00000396},
348 {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000}, 53 {0x0000a04c, 0x00000000},
349 {0x0000a204, 0x01303fc0, 0x01303fc4, 0x01303fc4, 0x01303fc0}, 54 {0x0000a050, 0x00000000},
350 {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004}, 55 {0x0000a054, 0x00000000},
351 {0x0000a230, 0x0000400a, 0x00004014, 0x00004016, 0x0000400b}, 56 {0x0000a058, 0x00000000},
352 {0x0000a234, 0x10000fff, 0x10000fff, 0x10000fff, 0x10000fff}, 57 {0x0000a05c, 0x00000000},
353 {0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018}, 58 {0x0000a060, 0x00000000},
354 {0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108}, 59 {0x0000a064, 0x00000000},
355 {0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898}, 60 {0x0000a068, 0x00000000},
356 {0x0000a258, 0x02020002, 0x02020002, 0x02020002, 0x02020002}, 61 {0x0000a06c, 0x00000000},
357 {0x0000a25c, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e}, 62 {0x0000a070, 0x00000000},
358 {0x0000a260, 0x3a021501, 0x3a021501, 0x3a021501, 0x3a021501}, 63 {0x0000a074, 0x00000000},
359 {0x0000a264, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e}, 64 {0x0000a078, 0x00000000},
360 {0x0000a280, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b}, 65 {0x0000a07c, 0x00000000},
361 {0x0000a284, 0x00000000, 0x00000000, 0x000002a0, 0x000002a0}, 66 {0x0000a080, 0x28282828},
362 {0x0000a288, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 67 {0x0000a084, 0x28282828},
363 {0x0000a28c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 68 {0x0000a088, 0x28282828},
364 {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18}, 69 {0x0000a08c, 0x28282828},
365 {0x0000a2d0, 0x00071981, 0x00071981, 0x00071982, 0x00071982}, 70 {0x0000a090, 0x28282828},
366 {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0xf999a83a, 0xf999a83a}, 71 {0x0000a094, 0x24242428},
367 {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 72 {0x0000a098, 0x171e1e1e},
368 {0x0000be04, 0x00802020, 0x00802020, 0x00802020, 0x00802020}, 73 {0x0000a09c, 0x02020b0b},
369 {0x0000be18, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 74 {0x0000a0a0, 0x02020202},
75 {0x0000a0a4, 0x00000000},
76 {0x0000a0a8, 0x00000000},
77 {0x0000a0ac, 0x00000000},
78 {0x0000a0b0, 0x00000000},
79 {0x0000a0b4, 0x00000000},
80 {0x0000a0b8, 0x00000000},
81 {0x0000a0bc, 0x00000000},
82 {0x0000a0c0, 0x22072208},
83 {0x0000a0c4, 0x22052206},
84 {0x0000a0c8, 0x22032204},
85 {0x0000a0cc, 0x22012202},
86 {0x0000a0d0, 0x221f2200},
87 {0x0000a0d4, 0x221d221e},
88 {0x0000a0d8, 0x33023303},
89 {0x0000a0dc, 0x33003301},
90 {0x0000a0e0, 0x331e331f},
91 {0x0000a0e4, 0x4402331d},
92 {0x0000a0e8, 0x44004401},
93 {0x0000a0ec, 0x441e441f},
94 {0x0000a0f0, 0x55025503},
95 {0x0000a0f4, 0x55005501},
96 {0x0000a0f8, 0x551e551f},
97 {0x0000a0fc, 0x6602551d},
98 {0x0000a100, 0x66006601},
99 {0x0000a104, 0x661e661f},
100 {0x0000a108, 0x7703661d},
101 {0x0000a10c, 0x77017702},
102 {0x0000a110, 0x00007700},
103 {0x0000a114, 0x00000000},
104 {0x0000a118, 0x00000000},
105 {0x0000a11c, 0x00000000},
106 {0x0000a120, 0x00000000},
107 {0x0000a124, 0x00000000},
108 {0x0000a128, 0x00000000},
109 {0x0000a12c, 0x00000000},
110 {0x0000a130, 0x00000000},
111 {0x0000a134, 0x00000000},
112 {0x0000a138, 0x00000000},
113 {0x0000a13c, 0x00000000},
114 {0x0000a140, 0x001f0000},
115 {0x0000a144, 0x111f1100},
116 {0x0000a148, 0x111d111e},
117 {0x0000a14c, 0x111b111c},
118 {0x0000a150, 0x22032204},
119 {0x0000a154, 0x22012202},
120 {0x0000a158, 0x221f2200},
121 {0x0000a15c, 0x221d221e},
122 {0x0000a160, 0x33013302},
123 {0x0000a164, 0x331f3300},
124 {0x0000a168, 0x4402331e},
125 {0x0000a16c, 0x44004401},
126 {0x0000a170, 0x441e441f},
127 {0x0000a174, 0x55015502},
128 {0x0000a178, 0x551f5500},
129 {0x0000a17c, 0x6602551e},
130 {0x0000a180, 0x66006601},
131 {0x0000a184, 0x661e661f},
132 {0x0000a188, 0x7703661d},
133 {0x0000a18c, 0x77017702},
134 {0x0000a190, 0x00007700},
135 {0x0000a194, 0x00000000},
136 {0x0000a198, 0x00000000},
137 {0x0000a19c, 0x00000000},
138 {0x0000a1a0, 0x00000000},
139 {0x0000a1a4, 0x00000000},
140 {0x0000a1a8, 0x00000000},
141 {0x0000a1ac, 0x00000000},
142 {0x0000a1b0, 0x00000000},
143 {0x0000a1b4, 0x00000000},
144 {0x0000a1b8, 0x00000000},
145 {0x0000a1bc, 0x00000000},
146 {0x0000a1c0, 0x00000000},
147 {0x0000a1c4, 0x00000000},
148 {0x0000a1c8, 0x00000000},
149 {0x0000a1cc, 0x00000000},
150 {0x0000a1d0, 0x00000000},
151 {0x0000a1d4, 0x00000000},
152 {0x0000a1d8, 0x00000000},
153 {0x0000a1dc, 0x00000000},
154 {0x0000a1e0, 0x00000000},
155 {0x0000a1e4, 0x00000000},
156 {0x0000a1e8, 0x00000000},
157 {0x0000a1ec, 0x00000000},
158 {0x0000a1f0, 0x00000396},
159 {0x0000a1f4, 0x00000396},
160 {0x0000a1f8, 0x00000396},
161 {0x0000a1fc, 0x00000296},
370}; 162};
371 163
372static const u32 ar9485Modes_high_ob_db_tx_gain_1_1[][5] = { 164static const u32 ar9485Modes_high_power_tx_gain_1_1[][5] = {
373 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 165 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
374 {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002}, 166 {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
375 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8}, 167 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
376 {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 168 {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
@@ -442,102 +234,34 @@ static const u32 ar9485Modes_high_ob_db_tx_gain_1_1[][5] = {
442 {0x00016048, 0x6c924260, 0x6c924260, 0x6c924260, 0x6c924260}, 234 {0x00016048, 0x6c924260, 0x6c924260, 0x6c924260, 0x6c924260},
443}; 235};
444 236
445static const u32 ar9485_modes_lowest_ob_db_tx_gain_1_1[][5] = { 237#define ar9485Modes_high_ob_db_tx_gain_1_1 ar9485Modes_high_power_tx_gain_1_1
446 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
447 {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
448 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
449 {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
450 {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
451 {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
452 {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
453 {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
454 {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
455 {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
456 {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
457 {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
458 {0x0000a520, 0x2f001f04, 0x2f001f04, 0x21000603, 0x21000603},
459 {0x0000a524, 0x35001fc4, 0x35001fc4, 0x25000605, 0x25000605},
460 {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2a000a03, 0x2a000a03},
461 {0x0000a52c, 0x41023e85, 0x41023e85, 0x2c000a04, 0x2c000a04},
462 {0x0000a530, 0x48023ec6, 0x48023ec6, 0x34000e20, 0x34000e20},
463 {0x0000a534, 0x4d023f01, 0x4d023f01, 0x35000e21, 0x35000e21},
464 {0x0000a538, 0x53023f4b, 0x53023f4b, 0x43000e62, 0x43000e62},
465 {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x45000e63, 0x45000e63},
466 {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x49000e65, 0x49000e65},
467 {0x0000a544, 0x6502feca, 0x6502feca, 0x4b000e66, 0x4b000e66},
468 {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x4d001645, 0x4d001645},
469 {0x0000a54c, 0x7203feca, 0x7203feca, 0x51001865, 0x51001865},
470 {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x55001a86, 0x55001a86},
471 {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x57001ce9, 0x57001ce9},
472 {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x5a001ceb, 0x5a001ceb},
473 {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x5e001eeb, 0x5e001eeb},
474 {0x0000a560, 0x900fff0b, 0x900fff0b, 0x5e001eeb, 0x5e001eeb},
475 {0x0000a564, 0x960fffcb, 0x960fffcb, 0x5e001eeb, 0x5e001eeb},
476 {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
477 {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
478 {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
479 {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
480 {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
481 {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
482 {0x0000b500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
483 {0x0000b504, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
484 {0x0000b508, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
485 {0x0000b50c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
486 {0x0000b510, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
487 {0x0000b514, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
488 {0x0000b518, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
489 {0x0000b51c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
490 {0x0000b520, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
491 {0x0000b524, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
492 {0x0000b528, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
493 {0x0000b52c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
494 {0x0000b530, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
495 {0x0000b534, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
496 {0x0000b538, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
497 {0x0000b53c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
498 {0x0000b540, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
499 {0x0000b544, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
500 {0x0000b548, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
501 {0x0000b54c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
502 {0x0000b550, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
503 {0x0000b554, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
504 {0x0000b558, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
505 {0x0000b55c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
506 {0x0000b560, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
507 {0x0000b564, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
508 {0x0000b568, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
509 {0x0000b56c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
510 {0x0000b570, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
511 {0x0000b574, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
512 {0x0000b578, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
513 {0x0000b57c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
514 {0x00016044, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db},
515 {0x00016048, 0x6c924260, 0x6c924260, 0x6c924260, 0x6c924260},
516};
517 238
518static const u32 ar9485_1_1_radio_postamble[][2] = { 239#define ar9485Modes_low_ob_db_tx_gain_1_1 ar9485Modes_high_ob_db_tx_gain_1_1
519 /* Addr allmodes */
520 {0x0001609c, 0x0b283f31},
521 {0x000160ac, 0x24611800},
522 {0x000160b0, 0x03284f3e},
523 {0x0001610c, 0x00170000},
524 {0x00016140, 0x50804008},
525};
526 240
527static const u32 ar9485_1_1_mac_postamble[][5] = { 241#define ar9485_modes_lowest_ob_db_tx_gain_1_1 ar9485Modes_low_ob_db_tx_gain_1_1
528 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 242
529 {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160}, 243static const u32 ar9485_1_1[][2] = {
530 {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c}, 244 /* Addr allmodes */
531 {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38}, 245 {0x0000a580, 0x00000000},
532 {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00}, 246 {0x0000a584, 0x00000000},
533 {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b}, 247 {0x0000a588, 0x00000000},
534 {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810}, 248 {0x0000a58c, 0x00000000},
535 {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a}, 249 {0x0000a590, 0x00000000},
536 {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440}, 250 {0x0000a594, 0x00000000},
251 {0x0000a598, 0x00000000},
252 {0x0000a59c, 0x00000000},
253 {0x0000a5a0, 0x00000000},
254 {0x0000a5a4, 0x00000000},
255 {0x0000a5a8, 0x00000000},
256 {0x0000a5ac, 0x00000000},
257 {0x0000a5b0, 0x00000000},
258 {0x0000a5b4, 0x00000000},
259 {0x0000a5b8, 0x00000000},
260 {0x0000a5bc, 0x00000000},
537}; 261};
538 262
539static const u32 ar9485_1_1_radio_core[][2] = { 263static const u32 ar9485_1_1_radio_core[][2] = {
540 /* Addr allmodes */ 264 /* Addr allmodes */
541 {0x00016000, 0x36db6db6}, 265 {0x00016000, 0x36db6db6},
542 {0x00016004, 0x6db6db40}, 266 {0x00016004, 0x6db6db40},
543 {0x00016008, 0x73800000}, 267 {0x00016008, 0x73800000},
@@ -601,294 +325,145 @@ static const u32 ar9485_1_1_radio_core[][2] = {
601 {0x00016c44, 0x12000000}, 325 {0x00016c44, 0x12000000},
602}; 326};
603 327
604static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_enable_L1[][2] = { 328static const u32 ar9485_1_1_baseband_core[][2] = {
605 /* Addr allmodes */ 329 /* Addr allmodes */
606 {0x00018c00, 0x18052e5e}, 330 {0x00009800, 0xafe68e30},
607 {0x00018c04, 0x000801d8}, 331 {0x00009804, 0xfd14e000},
608 {0x00018c08, 0x0000080c}, 332 {0x00009808, 0x9c0a8f6b},
609}; 333 {0x0000980c, 0x04800000},
610 334 {0x00009814, 0x9280c00a},
611static const u32 ar9485Modes_high_power_tx_gain_1_1[][5] = { 335 {0x00009818, 0x00000000},
612 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 336 {0x0000981c, 0x00020028},
613 {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002}, 337 {0x00009834, 0x5f3ca3de},
614 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8}, 338 {0x00009838, 0x0108ecff},
615 {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 339 {0x0000983c, 0x14750600},
616 {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000}, 340 {0x00009880, 0x201fff00},
617 {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002}, 341 {0x00009884, 0x00001042},
618 {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004}, 342 {0x000098a4, 0x00200400},
619 {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200}, 343 {0x000098b0, 0x52440bbe},
620 {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202}, 344 {0x000098d0, 0x004b6a8e},
621 {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400}, 345 {0x000098d4, 0x00000820},
622 {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402}, 346 {0x000098dc, 0x00000000},
623 {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404}, 347 {0x000098f0, 0x00000000},
624 {0x0000a520, 0x2f001f04, 0x2f001f04, 0x21000603, 0x21000603}, 348 {0x000098f4, 0x00000000},
625 {0x0000a524, 0x35001fc4, 0x35001fc4, 0x25000605, 0x25000605}, 349 {0x00009c04, 0x00000000},
626 {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2a000a03, 0x2a000a03}, 350 {0x00009c08, 0x03200000},
627 {0x0000a52c, 0x41023e85, 0x41023e85, 0x2c000a04, 0x2c000a04}, 351 {0x00009c0c, 0x00000000},
628 {0x0000a530, 0x48023ec6, 0x48023ec6, 0x34000e20, 0x34000e20}, 352 {0x00009c10, 0x00000000},
629 {0x0000a534, 0x4d023f01, 0x4d023f01, 0x35000e21, 0x35000e21}, 353 {0x00009c14, 0x00046384},
630 {0x0000a538, 0x53023f4b, 0x53023f4b, 0x43000e62, 0x43000e62}, 354 {0x00009c18, 0x05b6b440},
631 {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x45000e63, 0x45000e63}, 355 {0x00009c1c, 0x00b6b440},
632 {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x49000e65, 0x49000e65}, 356 {0x00009d00, 0xc080a333},
633 {0x0000a544, 0x6502feca, 0x6502feca, 0x4b000e66, 0x4b000e66}, 357 {0x00009d04, 0x40206c10},
634 {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x4d001645, 0x4d001645}, 358 {0x00009d08, 0x009c4060},
635 {0x0000a54c, 0x7203feca, 0x7203feca, 0x51001865, 0x51001865}, 359 {0x00009d0c, 0x1883800a},
636 {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x55001a86, 0x55001a86}, 360 {0x00009d10, 0x01834061},
637 {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x57001ce9, 0x57001ce9}, 361 {0x00009d14, 0x00c00400},
638 {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x5a001ceb, 0x5a001ceb}, 362 {0x00009d18, 0x00000000},
639 {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x5e001eeb, 0x5e001eeb}, 363 {0x00009d1c, 0x00000000},
640 {0x0000a560, 0x900fff0b, 0x900fff0b, 0x5e001eeb, 0x5e001eeb}, 364 {0x00009e08, 0x0038233c},
641 {0x0000a564, 0x960fffcb, 0x960fffcb, 0x5e001eeb, 0x5e001eeb}, 365 {0x00009e24, 0x9927b515},
642 {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb}, 366 {0x00009e28, 0x12ef0200},
643 {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb}, 367 {0x00009e30, 0x06336f77},
644 {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb}, 368 {0x00009e34, 0x6af6532f},
645 {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb}, 369 {0x00009e38, 0x0cc80c00},
646 {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb}, 370 {0x00009e40, 0x0d261820},
647 {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb}, 371 {0x00009e4c, 0x00001004},
648 {0x0000b500, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 372 {0x00009e50, 0x00ff03f1},
649 {0x0000b504, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 373 {0x00009fc0, 0x80be4788},
650 {0x0000b508, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 374 {0x00009fc4, 0x0001efb5},
651 {0x0000b50c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 375 {0x00009fcc, 0x40000014},
652 {0x0000b510, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 376 {0x0000a20c, 0x00000000},
653 {0x0000b514, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 377 {0x0000a210, 0x00000000},
654 {0x0000b518, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 378 {0x0000a220, 0x00000000},
655 {0x0000b51c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 379 {0x0000a224, 0x00000000},
656 {0x0000b520, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 380 {0x0000a228, 0x10002310},
657 {0x0000b524, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 381 {0x0000a23c, 0x00000000},
658 {0x0000b528, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 382 {0x0000a244, 0x0c000000},
659 {0x0000b52c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 383 {0x0000a2a0, 0x00000001},
660 {0x0000b530, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 384 {0x0000a2c0, 0x00000001},
661 {0x0000b534, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 385 {0x0000a2c8, 0x00000000},
662 {0x0000b538, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 386 {0x0000a2cc, 0x18c43433},
663 {0x0000b53c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 387 {0x0000a2d4, 0x00000000},
664 {0x0000b540, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 388 {0x0000a2dc, 0x00000000},
665 {0x0000b544, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 389 {0x0000a2e0, 0x00000000},
666 {0x0000b548, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 390 {0x0000a2e4, 0x00000000},
667 {0x0000b54c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 391 {0x0000a2e8, 0x00000000},
668 {0x0000b550, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 392 {0x0000a2ec, 0x00000000},
669 {0x0000b554, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 393 {0x0000a2f0, 0x00000000},
670 {0x0000b558, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 394 {0x0000a2f4, 0x00000000},
671 {0x0000b55c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 395 {0x0000a2f8, 0x00000000},
672 {0x0000b560, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 396 {0x0000a344, 0x00000000},
673 {0x0000b564, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 397 {0x0000a34c, 0x00000000},
674 {0x0000b568, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 398 {0x0000a350, 0x0000a000},
675 {0x0000b56c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 399 {0x0000a364, 0x00000000},
676 {0x0000b570, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 400 {0x0000a370, 0x00000000},
677 {0x0000b574, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 401 {0x0000a390, 0x00000001},
678 {0x0000b578, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 402 {0x0000a394, 0x00000444},
679 {0x0000b57c, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 403 {0x0000a398, 0x001f0e0f},
680 {0x00016044, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db}, 404 {0x0000a39c, 0x0075393f},
681 {0x00016048, 0x6c924260, 0x6c924260, 0x6c924260, 0x6c924260}, 405 {0x0000a3a0, 0xb79f6427},
682}; 406 {0x0000a3a4, 0x000000ff},
683 407 {0x0000a3a8, 0x3b3b3b3b},
684static const u32 ar9485_1_1[][2] = { 408 {0x0000a3ac, 0x2f2f2f2f},
685 /* Addr allmodes */ 409 {0x0000a3c0, 0x20202020},
686 {0x0000a580, 0x00000000}, 410 {0x0000a3c4, 0x22222220},
687 {0x0000a584, 0x00000000}, 411 {0x0000a3c8, 0x20200020},
688 {0x0000a588, 0x00000000}, 412 {0x0000a3cc, 0x20202020},
689 {0x0000a58c, 0x00000000}, 413 {0x0000a3d0, 0x20202020},
690 {0x0000a590, 0x00000000}, 414 {0x0000a3d4, 0x20202020},
691 {0x0000a594, 0x00000000}, 415 {0x0000a3d8, 0x20202020},
692 {0x0000a598, 0x00000000}, 416 {0x0000a3dc, 0x20202020},
693 {0x0000a59c, 0x00000000}, 417 {0x0000a3e0, 0x20202020},
694 {0x0000a5a0, 0x00000000}, 418 {0x0000a3e4, 0x20202020},
695 {0x0000a5a4, 0x00000000}, 419 {0x0000a3e8, 0x20202020},
696 {0x0000a5a8, 0x00000000}, 420 {0x0000a3ec, 0x20202020},
697 {0x0000a5ac, 0x00000000}, 421 {0x0000a3f0, 0x00000000},
698 {0x0000a5b0, 0x00000000}, 422 {0x0000a3f4, 0x00000006},
699 {0x0000a5b4, 0x00000000}, 423 {0x0000a3f8, 0x0cdbd380},
700 {0x0000a5b8, 0x00000000}, 424 {0x0000a3fc, 0x000f0f01},
701 {0x0000a5bc, 0x00000000}, 425 {0x0000a400, 0x8fa91f01},
702}; 426 {0x0000a404, 0x00000000},
703 427 {0x0000a408, 0x0e79e5c6},
704static const u32 ar9485_modes_green_ob_db_tx_gain_1_1[][5] = { 428 {0x0000a40c, 0x00820820},
705 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 429 {0x0000a414, 0x1ce739cf},
706 {0x000098bc, 0x00000003, 0x00000003, 0x00000003, 0x00000003}, 430 {0x0000a418, 0x2d0019ce},
707 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8}, 431 {0x0000a41c, 0x1ce739ce},
708 {0x0000a458, 0x80000000, 0x80000000, 0x80000000, 0x80000000}, 432 {0x0000a420, 0x000001ce},
709 {0x0000a500, 0x00022200, 0x00022200, 0x00000006, 0x00000006}, 433 {0x0000a424, 0x1ce739ce},
710 {0x0000a504, 0x05062002, 0x05062002, 0x03000201, 0x03000201}, 434 {0x0000a428, 0x000001ce},
711 {0x0000a508, 0x0c002e00, 0x0c002e00, 0x06000203, 0x06000203}, 435 {0x0000a42c, 0x1ce739ce},
712 {0x0000a50c, 0x11062202, 0x11062202, 0x0a000401, 0x0a000401}, 436 {0x0000a430, 0x1ce739ce},
713 {0x0000a510, 0x17022e00, 0x17022e00, 0x0e000403, 0x0e000403}, 437 {0x0000a434, 0x00000000},
714 {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x12000405, 0x12000405}, 438 {0x0000a438, 0x00001801},
715 {0x0000a518, 0x25020ec0, 0x25020ec0, 0x15000604, 0x15000604}, 439 {0x0000a43c, 0x00000000},
716 {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x18000605, 0x18000605}, 440 {0x0000a440, 0x00000000},
717 {0x0000a520, 0x2f001f04, 0x2f001f04, 0x1c000a04, 0x1c000a04}, 441 {0x0000a444, 0x00000000},
718 {0x0000a524, 0x35001fc4, 0x35001fc4, 0x21000a06, 0x21000a06}, 442 {0x0000a448, 0x04000000},
719 {0x0000a528, 0x3c022f04, 0x3c022f04, 0x29000a24, 0x29000a24}, 443 {0x0000a44c, 0x00000001},
720 {0x0000a52c, 0x41023e85, 0x41023e85, 0x2f000e21, 0x2f000e21}, 444 {0x0000a450, 0x00010000},
721 {0x0000a530, 0x48023ec6, 0x48023ec6, 0x31000e20, 0x31000e20}, 445 {0x0000a5c4, 0xbfad9d74},
722 {0x0000a534, 0x4d023f01, 0x4d023f01, 0x33000e20, 0x33000e20}, 446 {0x0000a5c8, 0x0048060a},
723 {0x0000a538, 0x53023f4b, 0x53023f4b, 0x43000e62, 0x43000e62}, 447 {0x0000a5cc, 0x00000637},
724 {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x45000e63, 0x45000e63}, 448 {0x0000a760, 0x03020100},
725 {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x49000e65, 0x49000e65}, 449 {0x0000a764, 0x09080504},
726 {0x0000a544, 0x6502feca, 0x6502feca, 0x4b000e66, 0x4b000e66}, 450 {0x0000a768, 0x0d0c0b0a},
727 {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x4d001645, 0x4d001645}, 451 {0x0000a76c, 0x13121110},
728 {0x0000a54c, 0x7203feca, 0x7203feca, 0x51001865, 0x51001865}, 452 {0x0000a770, 0x31301514},
729 {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x55001a86, 0x55001a86}, 453 {0x0000a774, 0x35343332},
730 {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x57001ce9, 0x57001ce9}, 454 {0x0000a778, 0x00000036},
731 {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x5a001ceb, 0x5a001ceb}, 455 {0x0000a780, 0x00000838},
732 {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x5e001eeb, 0x5e001eeb}, 456 {0x0000a7c0, 0x00000000},
733 {0x0000a560, 0x900fff0b, 0x900fff0b, 0x5e001eeb, 0x5e001eeb}, 457 {0x0000a7c4, 0xfffffffc},
734 {0x0000a564, 0x960fffcb, 0x960fffcb, 0x5e001eeb, 0x5e001eeb}, 458 {0x0000a7c8, 0x00000000},
735 {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb}, 459 {0x0000a7cc, 0x00000000},
736 {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb}, 460 {0x0000a7d0, 0x00000000},
737 {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb}, 461 {0x0000a7d4, 0x00000004},
738 {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb}, 462 {0x0000a7dc, 0x00000000},
739 {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
740 {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
741 {0x0000b500, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
742 {0x0000b504, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
743 {0x0000b508, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
744 {0x0000b50c, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
745 {0x0000b510, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
746 {0x0000b514, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
747 {0x0000b518, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
748 {0x0000b51c, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
749 {0x0000b520, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
750 {0x0000b524, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
751 {0x0000b528, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a},
752 {0x0000b52c, 0x0000002a, 0x0000002a, 0x0000002a, 0x0000002a},
753 {0x0000b530, 0x0000003a, 0x0000003a, 0x0000003a, 0x0000003a},
754 {0x0000b534, 0x0000004a, 0x0000004a, 0x0000004a, 0x0000004a},
755 {0x0000b538, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
756 {0x0000b53c, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
757 {0x0000b540, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
758 {0x0000b544, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
759 {0x0000b548, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
760 {0x0000b54c, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
761 {0x0000b550, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
762 {0x0000b554, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
763 {0x0000b558, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
764 {0x0000b55c, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
765 {0x0000b560, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
766 {0x0000b564, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
767 {0x0000b568, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
768 {0x0000b56c, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
769 {0x0000b570, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
770 {0x0000b574, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
771 {0x0000b578, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
772 {0x0000b57c, 0x0000005b, 0x0000005b, 0x0000005b, 0x0000005b},
773 {0x00016044, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db},
774 {0x00016048, 0x6c924260, 0x6c924260, 0x6c924260, 0x6c924260},
775};
776
777static const u32 ar9485_1_1_pcie_phy_clkreq_disable_L1[][2] = {
778 /* Addr allmodes */
779 {0x00018c00, 0x18013e5e},
780 {0x00018c04, 0x000801d8},
781 {0x00018c08, 0x0000080c},
782};
783
784static const u32 ar9485_1_1_soc_preamble[][2] = {
785 /* Addr allmodes */
786 {0x00004014, 0xba280400},
787 {0x00004090, 0x00aa10aa},
788 {0x000040a4, 0x00a0c9c9},
789 {0x00007010, 0x00000022},
790 {0x00007020, 0x00000000},
791 {0x00007034, 0x00000002},
792 {0x00007038, 0x000004c2},
793 {0x00007048, 0x00000002},
794};
795
796static const u32 ar9485_1_1_baseband_core_txfir_coeff_japan_2484[][2] = {
797 /* Addr allmodes */
798 {0x0000a398, 0x00000000},
799 {0x0000a39c, 0x6f7f0301},
800 {0x0000a3a0, 0xca9228ee},
801};
802
803static const u32 ar9485Modes_low_ob_db_tx_gain_1_1[][5] = {
804 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
805 {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
806 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
807 {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
808 {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
809 {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
810 {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
811 {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
812 {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
813 {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
814 {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
815 {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
816 {0x0000a520, 0x2f001f04, 0x2f001f04, 0x21000603, 0x21000603},
817 {0x0000a524, 0x35001fc4, 0x35001fc4, 0x25000605, 0x25000605},
818 {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2a000a03, 0x2a000a03},
819 {0x0000a52c, 0x41023e85, 0x41023e85, 0x2c000a04, 0x2c000a04},
820 {0x0000a530, 0x48023ec6, 0x48023ec6, 0x34000e20, 0x34000e20},
821 {0x0000a534, 0x4d023f01, 0x4d023f01, 0x35000e21, 0x35000e21},
822 {0x0000a538, 0x53023f4b, 0x53023f4b, 0x43000e62, 0x43000e62},
823 {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x45000e63, 0x45000e63},
824 {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x49000e65, 0x49000e65},
825 {0x0000a544, 0x6502feca, 0x6502feca, 0x4b000e66, 0x4b000e66},
826 {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x4d001645, 0x4d001645},
827 {0x0000a54c, 0x7203feca, 0x7203feca, 0x51001865, 0x51001865},
828 {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x55001a86, 0x55001a86},
829 {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x57001ce9, 0x57001ce9},
830 {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x5a001ceb, 0x5a001ceb},
831 {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x5e001eeb, 0x5e001eeb},
832 {0x0000a560, 0x900fff0b, 0x900fff0b, 0x5e001eeb, 0x5e001eeb},
833 {0x0000a564, 0x960fffcb, 0x960fffcb, 0x5e001eeb, 0x5e001eeb},
834 {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
835 {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
836 {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
837 {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
838 {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
839 {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x5e001eeb, 0x5e001eeb},
840 {0x0000b500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
841 {0x0000b504, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
842 {0x0000b508, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
843 {0x0000b50c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
844 {0x0000b510, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
845 {0x0000b514, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
846 {0x0000b518, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
847 {0x0000b51c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
848 {0x0000b520, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
849 {0x0000b524, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
850 {0x0000b528, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
851 {0x0000b52c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
852 {0x0000b530, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
853 {0x0000b534, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
854 {0x0000b538, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
855 {0x0000b53c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
856 {0x0000b540, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
857 {0x0000b544, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
858 {0x0000b548, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
859 {0x0000b54c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
860 {0x0000b550, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
861 {0x0000b554, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
862 {0x0000b558, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
863 {0x0000b55c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
864 {0x0000b560, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
865 {0x0000b564, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
866 {0x0000b568, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
867 {0x0000b56c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
868 {0x0000b570, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
869 {0x0000b574, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
870 {0x0000b578, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
871 {0x0000b57c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
872 {0x00016044, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db, 0x05d6b2db},
873 {0x00016048, 0x6c924260, 0x6c924260, 0x6c924260, 0x6c924260},
874};
875
876static const u32 ar9485_fast_clock_1_1_baseband_postamble[][3] = {
877 /* Addr 5G_HT2 5G_HT40 */
878 {0x00009e00, 0x03721821, 0x03721821},
879 {0x0000a230, 0x0000400b, 0x00004016},
880 {0x0000a254, 0x00000898, 0x00001130},
881};
882
883static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_disable_L1[][2] = {
884 /* Addr allmodes */
885 {0x00018c00, 0x18012e5e},
886 {0x00018c04, 0x000801d8},
887 {0x00018c08, 0x0000080c},
888}; 463};
889 464
890static const u32 ar9485_common_rx_gain_1_1[][2] = { 465static const u32 ar9485_common_rx_gain_1_1[][2] = {
891 /* Addr allmodes */ 466 /* Addr allmodes */
892 {0x0000a000, 0x00010000}, 467 {0x0000a000, 0x00010000},
893 {0x0000a004, 0x00030002}, 468 {0x0000a004, 0x00030002},
894 {0x0000a008, 0x00050004}, 469 {0x0000a008, 0x00050004},
@@ -1019,143 +594,260 @@ static const u32 ar9485_common_rx_gain_1_1[][2] = {
1019 {0x0000a1fc, 0x00000296}, 594 {0x0000a1fc, 0x00000296},
1020}; 595};
1021 596
597static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_enable_L1[][2] = {
598 /* Addr allmodes */
599 {0x00018c00, 0x18052e5e},
600 {0x00018c04, 0x000801d8},
601 {0x00018c08, 0x0000080c},
602};
603
1022static const u32 ar9485_1_1_pcie_phy_clkreq_enable_L1[][2] = { 604static const u32 ar9485_1_1_pcie_phy_clkreq_enable_L1[][2] = {
1023 /* Addr allmodes */ 605 /* Addr allmodes */
1024 {0x00018c00, 0x18053e5e}, 606 {0x00018c00, 0x18053e5e},
1025 {0x00018c04, 0x000801d8}, 607 {0x00018c04, 0x000801d8},
1026 {0x00018c08, 0x0000080c}, 608 {0x00018c08, 0x0000080c},
1027}; 609};
1028 610
1029static const u32 ar9485Common_wo_xlna_rx_gain_1_1[][2] = { 611static const u32 ar9485_1_1_soc_preamble[][2] = {
1030 /* Addr allmodes */ 612 /* Addr allmodes */
1031 {0x0000a000, 0x00060005}, 613 {0x00004014, 0xba280400},
1032 {0x0000a004, 0x00810080}, 614 {0x00004090, 0x00aa10aa},
1033 {0x0000a008, 0x00830082}, 615 {0x000040a4, 0x00a0c9c9},
1034 {0x0000a00c, 0x00850084}, 616 {0x00007010, 0x00000022},
1035 {0x0000a010, 0x01820181}, 617 {0x00007020, 0x00000000},
1036 {0x0000a014, 0x01840183}, 618 {0x00007034, 0x00000002},
1037 {0x0000a018, 0x01880185}, 619 {0x00007038, 0x000004c2},
1038 {0x0000a01c, 0x018a0189}, 620 {0x00007048, 0x00000002},
1039 {0x0000a020, 0x02850284}, 621};
1040 {0x0000a024, 0x02890288}, 622
1041 {0x0000a028, 0x028b028a}, 623static const u32 ar9485_fast_clock_1_1_baseband_postamble[][3] = {
1042 {0x0000a02c, 0x03850384}, 624 /* Addr 5G_HT20 5G_HT40 */
1043 {0x0000a030, 0x03890388}, 625 {0x00009e00, 0x03721821, 0x03721821},
1044 {0x0000a034, 0x038b038a}, 626 {0x0000a230, 0x0000400b, 0x00004016},
1045 {0x0000a038, 0x038d038c}, 627 {0x0000a254, 0x00000898, 0x00001130},
1046 {0x0000a03c, 0x03910390}, 628};
1047 {0x0000a040, 0x03930392}, 629
1048 {0x0000a044, 0x03950394}, 630static const u32 ar9485_1_1_baseband_postamble[][5] = {
1049 {0x0000a048, 0x00000396}, 631 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
1050 {0x0000a04c, 0x00000000}, 632 {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005},
1051 {0x0000a050, 0x00000000}, 633 {0x00009820, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e},
1052 {0x0000a054, 0x00000000}, 634 {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
1053 {0x0000a058, 0x00000000}, 635 {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
1054 {0x0000a05c, 0x00000000}, 636 {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
1055 {0x0000a060, 0x00000000}, 637 {0x00009830, 0x0000059c, 0x0000059c, 0x0000059c, 0x0000059c},
1056 {0x0000a064, 0x00000000}, 638 {0x00009c00, 0x00000044, 0x00000044, 0x00000044, 0x00000044},
1057 {0x0000a068, 0x00000000}, 639 {0x00009e00, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0},
1058 {0x0000a06c, 0x00000000}, 640 {0x00009e04, 0x00182020, 0x00182020, 0x00182020, 0x00182020},
1059 {0x0000a070, 0x00000000}, 641 {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
1060 {0x0000a074, 0x00000000}, 642 {0x00009e10, 0x7ec88d2e, 0x7ec88d2e, 0x7ec80d2e, 0x7ec80d2e},
1061 {0x0000a078, 0x00000000}, 643 {0x00009e14, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e},
1062 {0x0000a07c, 0x00000000}, 644 {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1063 {0x0000a080, 0x28282828}, 645 {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
1064 {0x0000a084, 0x28282828}, 646 {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
1065 {0x0000a088, 0x28282828}, 647 {0x00009e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021},
1066 {0x0000a08c, 0x28282828}, 648 {0x00009e3c, 0xcf946220, 0xcf946220, 0xcf946222, 0xcf946222},
1067 {0x0000a090, 0x28282828}, 649 {0x00009e44, 0x02321e27, 0x02321e27, 0x02282324, 0x02282324},
1068 {0x0000a094, 0x24242428}, 650 {0x00009e48, 0x5030201a, 0x5030201a, 0x50302010, 0x50302010},
1069 {0x0000a098, 0x171e1e1e}, 651 {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
1070 {0x0000a09c, 0x02020b0b}, 652 {0x0000a204, 0x01303fc0, 0x01303fc4, 0x01303fc4, 0x01303fc0},
1071 {0x0000a0a0, 0x02020202}, 653 {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004},
1072 {0x0000a0a4, 0x00000000}, 654 {0x0000a230, 0x0000400a, 0x00004014, 0x00004016, 0x0000400b},
1073 {0x0000a0a8, 0x00000000}, 655 {0x0000a234, 0x10000fff, 0x10000fff, 0x10000fff, 0x10000fff},
1074 {0x0000a0ac, 0x00000000}, 656 {0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018},
1075 {0x0000a0b0, 0x00000000}, 657 {0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108},
1076 {0x0000a0b4, 0x00000000}, 658 {0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898},
1077 {0x0000a0b8, 0x00000000}, 659 {0x0000a258, 0x02020002, 0x02020002, 0x02020002, 0x02020002},
1078 {0x0000a0bc, 0x00000000}, 660 {0x0000a25c, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e},
1079 {0x0000a0c0, 0x22072208}, 661 {0x0000a260, 0x3a021501, 0x3a021501, 0x3a021501, 0x3a021501},
1080 {0x0000a0c4, 0x22052206}, 662 {0x0000a264, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e},
1081 {0x0000a0c8, 0x22032204}, 663 {0x0000a280, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b},
1082 {0x0000a0cc, 0x22012202}, 664 {0x0000a284, 0x00000000, 0x00000000, 0x000002a0, 0x000002a0},
1083 {0x0000a0d0, 0x221f2200}, 665 {0x0000a288, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1084 {0x0000a0d4, 0x221d221e}, 666 {0x0000a28c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1085 {0x0000a0d8, 0x33023303}, 667 {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
1086 {0x0000a0dc, 0x33003301}, 668 {0x0000a2d0, 0x00071981, 0x00071981, 0x00071982, 0x00071982},
1087 {0x0000a0e0, 0x331e331f}, 669 {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0xf999a83a, 0xf999a83a},
1088 {0x0000a0e4, 0x4402331d}, 670 {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1089 {0x0000a0e8, 0x44004401}, 671 {0x0000be04, 0x00802020, 0x00802020, 0x00802020, 0x00802020},
1090 {0x0000a0ec, 0x441e441f}, 672 {0x0000be18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1091 {0x0000a0f0, 0x55025503}, 673};
1092 {0x0000a0f4, 0x55005501}, 674
1093 {0x0000a0f8, 0x551e551f}, 675static const u32 ar9485_1_1_pcie_phy_clkreq_disable_L1[][2] = {
1094 {0x0000a0fc, 0x6602551d}, 676 /* Addr allmodes */
1095 {0x0000a100, 0x66006601}, 677 {0x00018c00, 0x18013e5e},
1096 {0x0000a104, 0x661e661f}, 678 {0x00018c04, 0x000801d8},
1097 {0x0000a108, 0x7703661d}, 679 {0x00018c08, 0x0000080c},
1098 {0x0000a10c, 0x77017702}, 680};
1099 {0x0000a110, 0x00007700}, 681
1100 {0x0000a114, 0x00000000}, 682static const u32 ar9485_1_1_radio_postamble[][2] = {
1101 {0x0000a118, 0x00000000}, 683 /* Addr allmodes */
1102 {0x0000a11c, 0x00000000}, 684 {0x0001609c, 0x0b283f31},
1103 {0x0000a120, 0x00000000}, 685 {0x000160ac, 0x24611800},
1104 {0x0000a124, 0x00000000}, 686 {0x000160b0, 0x03284f3e},
1105 {0x0000a128, 0x00000000}, 687 {0x0001610c, 0x00170000},
1106 {0x0000a12c, 0x00000000}, 688 {0x00016140, 0x50804008},
1107 {0x0000a130, 0x00000000}, 689};
1108 {0x0000a134, 0x00000000}, 690
1109 {0x0000a138, 0x00000000}, 691static const u32 ar9485_1_1_mac_core[][2] = {
1110 {0x0000a13c, 0x00000000}, 692 /* Addr allmodes */
1111 {0x0000a140, 0x001f0000}, 693 {0x00000008, 0x00000000},
1112 {0x0000a144, 0x111f1100}, 694 {0x00000030, 0x00020085},
1113 {0x0000a148, 0x111d111e}, 695 {0x00000034, 0x00000005},
1114 {0x0000a14c, 0x111b111c}, 696 {0x00000040, 0x00000000},
1115 {0x0000a150, 0x22032204}, 697 {0x00000044, 0x00000000},
1116 {0x0000a154, 0x22012202}, 698 {0x00000048, 0x00000008},
1117 {0x0000a158, 0x221f2200}, 699 {0x0000004c, 0x00000010},
1118 {0x0000a15c, 0x221d221e}, 700 {0x00000050, 0x00000000},
1119 {0x0000a160, 0x33013302}, 701 {0x00001040, 0x002ffc0f},
1120 {0x0000a164, 0x331f3300}, 702 {0x00001044, 0x002ffc0f},
1121 {0x0000a168, 0x4402331e}, 703 {0x00001048, 0x002ffc0f},
1122 {0x0000a16c, 0x44004401}, 704 {0x0000104c, 0x002ffc0f},
1123 {0x0000a170, 0x441e441f}, 705 {0x00001050, 0x002ffc0f},
1124 {0x0000a174, 0x55015502}, 706 {0x00001054, 0x002ffc0f},
1125 {0x0000a178, 0x551f5500}, 707 {0x00001058, 0x002ffc0f},
1126 {0x0000a17c, 0x6602551e}, 708 {0x0000105c, 0x002ffc0f},
1127 {0x0000a180, 0x66006601}, 709 {0x00001060, 0x002ffc0f},
1128 {0x0000a184, 0x661e661f}, 710 {0x00001064, 0x002ffc0f},
1129 {0x0000a188, 0x7703661d}, 711 {0x000010f0, 0x00000100},
1130 {0x0000a18c, 0x77017702}, 712 {0x00001270, 0x00000000},
1131 {0x0000a190, 0x00007700}, 713 {0x000012b0, 0x00000000},
1132 {0x0000a194, 0x00000000}, 714 {0x000012f0, 0x00000000},
1133 {0x0000a198, 0x00000000}, 715 {0x0000143c, 0x00000000},
1134 {0x0000a19c, 0x00000000}, 716 {0x0000147c, 0x00000000},
1135 {0x0000a1a0, 0x00000000}, 717 {0x00008000, 0x00000000},
1136 {0x0000a1a4, 0x00000000}, 718 {0x00008004, 0x00000000},
1137 {0x0000a1a8, 0x00000000}, 719 {0x00008008, 0x00000000},
1138 {0x0000a1ac, 0x00000000}, 720 {0x0000800c, 0x00000000},
1139 {0x0000a1b0, 0x00000000}, 721 {0x00008018, 0x00000000},
1140 {0x0000a1b4, 0x00000000}, 722 {0x00008020, 0x00000000},
1141 {0x0000a1b8, 0x00000000}, 723 {0x00008038, 0x00000000},
1142 {0x0000a1bc, 0x00000000}, 724 {0x0000803c, 0x00000000},
1143 {0x0000a1c0, 0x00000000}, 725 {0x00008040, 0x00000000},
1144 {0x0000a1c4, 0x00000000}, 726 {0x00008044, 0x00000000},
1145 {0x0000a1c8, 0x00000000}, 727 {0x00008048, 0x00000000},
1146 {0x0000a1cc, 0x00000000}, 728 {0x0000804c, 0xffffffff},
1147 {0x0000a1d0, 0x00000000}, 729 {0x00008054, 0x00000000},
1148 {0x0000a1d4, 0x00000000}, 730 {0x00008058, 0x00000000},
1149 {0x0000a1d8, 0x00000000}, 731 {0x0000805c, 0x000fc78f},
1150 {0x0000a1dc, 0x00000000}, 732 {0x00008060, 0x0000000f},
1151 {0x0000a1e0, 0x00000000}, 733 {0x00008064, 0x00000000},
1152 {0x0000a1e4, 0x00000000}, 734 {0x00008070, 0x00000310},
1153 {0x0000a1e8, 0x00000000}, 735 {0x00008074, 0x00000020},
1154 {0x0000a1ec, 0x00000000}, 736 {0x00008078, 0x00000000},
1155 {0x0000a1f0, 0x00000396}, 737 {0x0000809c, 0x0000000f},
1156 {0x0000a1f4, 0x00000396}, 738 {0x000080a0, 0x00000000},
1157 {0x0000a1f8, 0x00000396}, 739 {0x000080a4, 0x02ff0000},
1158 {0x0000a1fc, 0x00000296}, 740 {0x000080a8, 0x0e070605},
741 {0x000080ac, 0x0000000d},
742 {0x000080b0, 0x00000000},
743 {0x000080b4, 0x00000000},
744 {0x000080b8, 0x00000000},
745 {0x000080bc, 0x00000000},
746 {0x000080c0, 0x2a800000},
747 {0x000080c4, 0x06900168},
748 {0x000080c8, 0x13881c22},
749 {0x000080cc, 0x01f40000},
750 {0x000080d0, 0x00252500},
751 {0x000080d4, 0x00a00000},
752 {0x000080d8, 0x00400000},
753 {0x000080dc, 0x00000000},
754 {0x000080e0, 0xffffffff},
755 {0x000080e4, 0x0000ffff},
756 {0x000080e8, 0x3f3f3f3f},
757 {0x000080ec, 0x00000000},
758 {0x000080f0, 0x00000000},
759 {0x000080f4, 0x00000000},
760 {0x000080fc, 0x00020000},
761 {0x00008100, 0x00000000},
762 {0x00008108, 0x00000052},
763 {0x0000810c, 0x00000000},
764 {0x00008110, 0x00000000},
765 {0x00008114, 0x000007ff},
766 {0x00008118, 0x000000aa},
767 {0x0000811c, 0x00003210},
768 {0x00008124, 0x00000000},
769 {0x00008128, 0x00000000},
770 {0x0000812c, 0x00000000},
771 {0x00008130, 0x00000000},
772 {0x00008134, 0x00000000},
773 {0x00008138, 0x00000000},
774 {0x0000813c, 0x0000ffff},
775 {0x00008144, 0xffffffff},
776 {0x00008168, 0x00000000},
777 {0x0000816c, 0x00000000},
778 {0x00008170, 0x18486200},
779 {0x00008174, 0x33332210},
780 {0x00008178, 0x00000000},
781 {0x0000817c, 0x00020000},
782 {0x000081c0, 0x00000000},
783 {0x000081c4, 0x33332210},
784 {0x000081d4, 0x00000000},
785 {0x000081ec, 0x00000000},
786 {0x000081f0, 0x00000000},
787 {0x000081f4, 0x00000000},
788 {0x000081f8, 0x00000000},
789 {0x000081fc, 0x00000000},
790 {0x00008240, 0x00100000},
791 {0x00008244, 0x0010f400},
792 {0x00008248, 0x00000800},
793 {0x0000824c, 0x0001e800},
794 {0x00008250, 0x00000000},
795 {0x00008254, 0x00000000},
796 {0x00008258, 0x00000000},
797 {0x0000825c, 0x40000000},
798 {0x00008260, 0x00080922},
799 {0x00008264, 0x9ca00010},
800 {0x00008268, 0xffffffff},
801 {0x0000826c, 0x0000ffff},
802 {0x00008270, 0x00000000},
803 {0x00008274, 0x40000000},
804 {0x00008278, 0x003e4180},
805 {0x0000827c, 0x00000004},
806 {0x00008284, 0x0000002c},
807 {0x00008288, 0x0000002c},
808 {0x0000828c, 0x000000ff},
809 {0x00008294, 0x00000000},
810 {0x00008298, 0x00000000},
811 {0x0000829c, 0x00000000},
812 {0x00008300, 0x00000140},
813 {0x00008314, 0x00000000},
814 {0x0000831c, 0x0000010d},
815 {0x00008328, 0x00000000},
816 {0x0000832c, 0x00000007},
817 {0x00008330, 0x00000302},
818 {0x00008334, 0x00000700},
819 {0x00008338, 0x00ff0000},
820 {0x0000833c, 0x02400000},
821 {0x00008340, 0x000107ff},
822 {0x00008344, 0xa248105b},
823 {0x00008348, 0x008f0000},
824 {0x0000835c, 0x00000000},
825 {0x00008360, 0xffffffff},
826 {0x00008364, 0xffffffff},
827 {0x00008368, 0x00000000},
828 {0x00008370, 0x00000000},
829 {0x00008374, 0x000000ff},
830 {0x00008378, 0x00000000},
831 {0x0000837c, 0x00000000},
832 {0x00008380, 0xffffffff},
833 {0x00008384, 0xffffffff},
834 {0x00008390, 0xffffffff},
835 {0x00008394, 0xffffffff},
836 {0x00008398, 0x00000000},
837 {0x0000839c, 0x00000000},
838 {0x000083a0, 0x00000000},
839 {0x000083a4, 0x0000fa14},
840 {0x000083a8, 0x000f0c00},
841 {0x000083ac, 0x33332210},
842 {0x000083b0, 0x33332210},
843 {0x000083b4, 0x33332210},
844 {0x000083b8, 0x33332210},
845 {0x000083bc, 0x00000000},
846 {0x000083c0, 0x00000000},
847 {0x000083c4, 0x00000000},
848 {0x000083c8, 0x00000000},
849 {0x000083cc, 0x00000200},
850 {0x000083d0, 0x000301ff},
1159}; 851};
1160 852
1161#endif 853#endif /* INITVALS_9485_H */
diff --git a/drivers/net/wireless/ath/ath9k/ar955x_1p0_initvals.h b/drivers/net/wireless/ath/ath9k/ar955x_1p0_initvals.h
new file mode 100644
index 000000000000..df97f21c52dc
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/ar955x_1p0_initvals.h
@@ -0,0 +1,1284 @@
1/*
2 * Copyright (c) 2010-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2012 Qualcomm Atheros Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18#ifndef INITVALS_955X_1P0_H
19#define INITVALS_955X_1P0_H
20
21/* AR955X 1.0 */
22
23static const u32 ar955x_1p0_radio_postamble[][5] = {
24 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
25 {0x00016098, 0xd2dd5554, 0xd2dd5554, 0xd28b3330, 0xd28b3330},
26 {0x0001609c, 0x0a566f3a, 0x0a566f3a, 0x06345f2a, 0x06345f2a},
27 {0x000160ac, 0xa4647c00, 0xa4647c00, 0xa4646800, 0xa4646800},
28 {0x000160b0, 0x01885f52, 0x01885f52, 0x04accf3a, 0x04accf3a},
29 {0x00016104, 0xb7a00001, 0xb7a00001, 0xb7a00001, 0xb7a00001},
30 {0x0001610c, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000},
31 {0x00016140, 0x10804008, 0x10804008, 0x10804008, 0x10804008},
32 {0x00016504, 0xb7a00001, 0xb7a00001, 0xb7a00001, 0xb7a00001},
33 {0x0001650c, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000},
34 {0x00016540, 0x10804008, 0x10804008, 0x10804008, 0x10804008},
35 {0x00016904, 0xb7a00001, 0xb7a00001, 0xb7a00001, 0xb7a00001},
36 {0x0001690c, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000},
37 {0x00016940, 0x10804008, 0x10804008, 0x10804008, 0x10804008},
38};
39
40static const u32 ar955x_1p0_baseband_core_txfir_coeff_japan_2484[][2] = {
41 /* Addr allmodes */
42 {0x0000a398, 0x00000000},
43 {0x0000a39c, 0x6f7f0301},
44 {0x0000a3a0, 0xca9228ee},
45};
46
47static const u32 ar955x_1p0_baseband_postamble[][5] = {
48 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
49 {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011},
50 {0x00009820, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e},
51 {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
52 {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
53 {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
54 {0x00009830, 0x0000059c, 0x0000059c, 0x0000119c, 0x0000119c},
55 {0x00009c00, 0x000000c4, 0x000000c4, 0x000000c4, 0x000000c4},
56 {0x00009e00, 0x0372111a, 0x0372111a, 0x037216a0, 0x037216a0},
57 {0x00009e04, 0x001c2020, 0x001c2020, 0x001c2020, 0x001c2020},
58 {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
59 {0x00009e10, 0x7ec88d2e, 0x7ec88d2e, 0x7ec84d2e, 0x7ec84d2e},
60 {0x00009e14, 0x37b95d5e, 0x37b9605e, 0x3379605e, 0x33795d5e},
61 {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
62 {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
63 {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
64 {0x00009e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021},
65 {0x00009e3c, 0xcfa10820, 0xcfa10820, 0xcfa10822, 0xcfa10822},
66 {0x00009e44, 0xfe321e27, 0xfe321e27, 0xfe291e27, 0xfe291e27},
67 {0x00009e48, 0x5030201a, 0x5030201a, 0x50302012, 0x50302012},
68 {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
69 {0x0000a204, 0x005c0ec0, 0x005c0ec4, 0x005c0ec4, 0x005c0ec0},
70 {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004},
71 {0x0000a22c, 0x07e26a2f, 0x07e26a2f, 0x01026a2f, 0x01026a2f},
72 {0x0000a230, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b},
73 {0x0000a234, 0x00000fff, 0x10000fff, 0x10000fff, 0x00000fff},
74 {0x0000a238, 0xffb01018, 0xffb01018, 0xffb01018, 0xffb01018},
75 {0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108},
76 {0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898},
77 {0x0000a258, 0x02020002, 0x02020002, 0x02020002, 0x02020002},
78 {0x0000a25c, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e},
79 {0x0000a260, 0x0a021501, 0x0a021501, 0x3a021501, 0x3a021501},
80 {0x0000a264, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e},
81 {0x0000a280, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b},
82 {0x0000a284, 0x00000000, 0x00000000, 0x00000010, 0x00000010},
83 {0x0000a288, 0x00000110, 0x00000110, 0x00000110, 0x00000110},
84 {0x0000a28c, 0x00022222, 0x00022222, 0x00022222, 0x00022222},
85 {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
86 {0x0000a2cc, 0x18c50033, 0x18c43433, 0x18c41033, 0x18c44c33},
87 {0x0000a2d0, 0x00041982, 0x00041982, 0x00041982, 0x00041982},
88 {0x0000a2d8, 0x7999a83b, 0x7999a83b, 0x7999a83b, 0x7999a83b},
89 {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
90 {0x0000a830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
91 {0x0000ae04, 0x001c0000, 0x001c0000, 0x001c0000, 0x001c0000},
92 {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
93 {0x0000ae1c, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
94 {0x0000ae20, 0x000001b5, 0x000001b5, 0x000001ce, 0x000001ce},
95 {0x0000b284, 0x00000000, 0x00000000, 0x00000010, 0x00000010},
96 {0x0000b830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
97 {0x0000be04, 0x001c0000, 0x001c0000, 0x001c0000, 0x001c0000},
98 {0x0000be18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
99 {0x0000be1c, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
100 {0x0000be20, 0x000001b5, 0x000001b5, 0x000001ce, 0x000001ce},
101 {0x0000c284, 0x00000000, 0x00000000, 0x00000010, 0x00000010},
102};
103
104static const u32 ar955x_1p0_radio_core[][2] = {
105 /* Addr allmodes */
106 {0x00016000, 0x36db6db6},
107 {0x00016004, 0x6db6db40},
108 {0x00016008, 0x73f00000},
109 {0x0001600c, 0x00000000},
110 {0x00016040, 0x7f80fff8},
111 {0x0001604c, 0x76d005b5},
112 {0x00016050, 0x557cf031},
113 {0x00016054, 0x13449440},
114 {0x00016058, 0x0c51c92c},
115 {0x0001605c, 0x3db7fffc},
116 {0x00016060, 0xfffffffc},
117 {0x00016064, 0x000f0278},
118 {0x00016068, 0x6db6db6c},
119 {0x0001606c, 0x6db60000},
120 {0x00016080, 0x00080000},
121 {0x00016084, 0x0e48048c},
122 {0x00016088, 0x14214514},
123 {0x0001608c, 0x119f101e},
124 {0x00016090, 0x24926490},
125 {0x00016094, 0x00000000},
126 {0x000160a0, 0x0a108ffe},
127 {0x000160a4, 0x812fc370},
128 {0x000160a8, 0x423c8000},
129 {0x000160b4, 0x92480080},
130 {0x000160c0, 0x006db6d0},
131 {0x000160c4, 0x6db6db60},
132 {0x000160c8, 0x6db6db6c},
133 {0x000160cc, 0x01e6c000},
134 {0x00016100, 0x11999601},
135 {0x00016108, 0x00080010},
136 {0x00016144, 0x02084080},
137 {0x00016148, 0x000080c0},
138 {0x00016280, 0x01800804},
139 {0x00016284, 0x00038dc5},
140 {0x00016288, 0x00000000},
141 {0x0001628c, 0x00000040},
142 {0x00016380, 0x00000000},
143 {0x00016384, 0x00000000},
144 {0x00016388, 0x00400705},
145 {0x0001638c, 0x00800700},
146 {0x00016390, 0x00800700},
147 {0x00016394, 0x00000000},
148 {0x00016398, 0x00000000},
149 {0x0001639c, 0x00000000},
150 {0x000163a0, 0x00000001},
151 {0x000163a4, 0x00000001},
152 {0x000163a8, 0x00000000},
153 {0x000163ac, 0x00000000},
154 {0x000163b0, 0x00000000},
155 {0x000163b4, 0x00000000},
156 {0x000163b8, 0x00000000},
157 {0x000163bc, 0x00000000},
158 {0x000163c0, 0x000000a0},
159 {0x000163c4, 0x000c0000},
160 {0x000163c8, 0x14021402},
161 {0x000163cc, 0x00001402},
162 {0x000163d0, 0x00000000},
163 {0x000163d4, 0x00000000},
164 {0x00016400, 0x36db6db6},
165 {0x00016404, 0x6db6db40},
166 {0x00016408, 0x73f00000},
167 {0x0001640c, 0x00000000},
168 {0x00016440, 0x7f80fff8},
169 {0x0001644c, 0x76d005b5},
170 {0x00016450, 0x557cf031},
171 {0x00016454, 0x13449440},
172 {0x00016458, 0x0c51c92c},
173 {0x0001645c, 0x3db7fffc},
174 {0x00016460, 0xfffffffc},
175 {0x00016464, 0x000f0278},
176 {0x00016468, 0x6db6db6c},
177 {0x0001646c, 0x6db60000},
178 {0x00016500, 0x11999601},
179 {0x00016508, 0x00080010},
180 {0x00016544, 0x02084080},
181 {0x00016548, 0x000080c0},
182 {0x00016780, 0x00000000},
183 {0x00016784, 0x00000000},
184 {0x00016788, 0x00400705},
185 {0x0001678c, 0x00800700},
186 {0x00016790, 0x00800700},
187 {0x00016794, 0x00000000},
188 {0x00016798, 0x00000000},
189 {0x0001679c, 0x00000000},
190 {0x000167a0, 0x00000001},
191 {0x000167a4, 0x00000001},
192 {0x000167a8, 0x00000000},
193 {0x000167ac, 0x00000000},
194 {0x000167b0, 0x00000000},
195 {0x000167b4, 0x00000000},
196 {0x000167b8, 0x00000000},
197 {0x000167bc, 0x00000000},
198 {0x000167c0, 0x000000a0},
199 {0x000167c4, 0x000c0000},
200 {0x000167c8, 0x14021402},
201 {0x000167cc, 0x00001402},
202 {0x000167d0, 0x00000000},
203 {0x000167d4, 0x00000000},
204 {0x00016800, 0x36db6db6},
205 {0x00016804, 0x6db6db40},
206 {0x00016808, 0x73f00000},
207 {0x0001680c, 0x00000000},
208 {0x00016840, 0x7f80fff8},
209 {0x0001684c, 0x76d005b5},
210 {0x00016850, 0x557cf031},
211 {0x00016854, 0x13449440},
212 {0x00016858, 0x0c51c92c},
213 {0x0001685c, 0x3db7fffc},
214 {0x00016860, 0xfffffffc},
215 {0x00016864, 0x000f0278},
216 {0x00016868, 0x6db6db6c},
217 {0x0001686c, 0x6db60000},
218 {0x00016900, 0x11999601},
219 {0x00016908, 0x00080010},
220 {0x00016944, 0x02084080},
221 {0x00016948, 0x000080c0},
222 {0x00016b80, 0x00000000},
223 {0x00016b84, 0x00000000},
224 {0x00016b88, 0x00400705},
225 {0x00016b8c, 0x00800700},
226 {0x00016b90, 0x00800700},
227 {0x00016b94, 0x00000000},
228 {0x00016b98, 0x00000000},
229 {0x00016b9c, 0x00000000},
230 {0x00016ba0, 0x00000001},
231 {0x00016ba4, 0x00000001},
232 {0x00016ba8, 0x00000000},
233 {0x00016bac, 0x00000000},
234 {0x00016bb0, 0x00000000},
235 {0x00016bb4, 0x00000000},
236 {0x00016bb8, 0x00000000},
237 {0x00016bbc, 0x00000000},
238 {0x00016bc0, 0x000000a0},
239 {0x00016bc4, 0x000c0000},
240 {0x00016bc8, 0x14021402},
241 {0x00016bcc, 0x00001402},
242 {0x00016bd0, 0x00000000},
243 {0x00016bd4, 0x00000000},
244};
245
246static const u32 ar955x_1p0_modes_xpa_tx_gain_table[][9] = {
247 /* Addr 5G_HT20_L 5G_HT40_L 5G_HT20_M 5G_HT40_M 5G_HT20_H 5G_HT40_H 2G_HT40 2G_HT20 */
248 {0x0000a2dc, 0xffffaaaa, 0xffffaaaa, 0xffffaaaa, 0xffffaaaa, 0xffffaaaa, 0xffffaaaa, 0xfffd5aaa, 0xfffd5aaa},
249 {0x0000a2e0, 0xffffcccc, 0xffffcccc, 0xffffcccc, 0xffffcccc, 0xffffcccc, 0xffffcccc, 0xfffe9ccc, 0xfffe9ccc},
250 {0x0000a2e4, 0xfffff0f0, 0xfffff0f0, 0xfffff0f0, 0xfffff0f0, 0xfffff0f0, 0xfffff0f0, 0xffffe0f0, 0xffffe0f0},
251 {0x0000a2e8, 0xffffff00, 0xffffff00, 0xffffff00, 0xffffff00, 0xffffff00, 0xffffff00, 0xfffcff00, 0xfffcff00},
252 {0x0000a410, 0x000050de, 0x000050de, 0x000050de, 0x000050de, 0x000050de, 0x000050de, 0x000050da, 0x000050da},
253 {0x0000a500, 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000000, 0x00000000},
254 {0x0000a504, 0x04000005, 0x04000005, 0x04000005, 0x04000005, 0x04000005, 0x04000005, 0x04000002, 0x04000002},
255 {0x0000a508, 0x08000009, 0x08000009, 0x08000009, 0x08000009, 0x08000009, 0x08000009, 0x08000004, 0x08000004},
256 {0x0000a50c, 0x0c00000b, 0x0c00000b, 0x0c00000b, 0x0c00000b, 0x0c00000b, 0x0c00000b, 0x0c000006, 0x0c000006},
257 {0x0000a510, 0x1000000d, 0x1000000d, 0x1000000d, 0x1000000d, 0x1000000d, 0x1000000d, 0x0f00000a, 0x0f00000a},
258 {0x0000a514, 0x14000011, 0x14000011, 0x14000011, 0x14000011, 0x14000011, 0x14000011, 0x1300000c, 0x1300000c},
259 {0x0000a518, 0x19004008, 0x19004008, 0x19004008, 0x19004008, 0x18004008, 0x18004008, 0x1700000e, 0x1700000e},
260 {0x0000a51c, 0x1d00400a, 0x1d00400a, 0x1d00400a, 0x1d00400a, 0x1c00400a, 0x1c00400a, 0x1b000064, 0x1b000064},
261 {0x0000a520, 0x230020a2, 0x230020a2, 0x210020a2, 0x210020a2, 0x200020a2, 0x200020a2, 0x1f000242, 0x1f000242},
262 {0x0000a524, 0x2500006e, 0x2500006e, 0x2500006e, 0x2500006e, 0x2400006e, 0x2400006e, 0x23000229, 0x23000229},
263 {0x0000a528, 0x29022221, 0x29022221, 0x28022221, 0x28022221, 0x27022221, 0x27022221, 0x270002a2, 0x270002a2},
264 {0x0000a52c, 0x2d00062a, 0x2d00062a, 0x2c00062a, 0x2c00062a, 0x2a00062a, 0x2a00062a, 0x2c001203, 0x2c001203},
265 {0x0000a530, 0x340220a5, 0x340220a5, 0x320220a5, 0x320220a5, 0x2f0220a5, 0x2f0220a5, 0x30001803, 0x30001803},
266 {0x0000a534, 0x380022c5, 0x380022c5, 0x350022c5, 0x350022c5, 0x320022c5, 0x320022c5, 0x33000881, 0x33000881},
267 {0x0000a538, 0x3b002486, 0x3b002486, 0x39002486, 0x39002486, 0x36002486, 0x36002486, 0x38001809, 0x38001809},
268 {0x0000a53c, 0x3f00248a, 0x3f00248a, 0x3d00248a, 0x3d00248a, 0x3a00248a, 0x3a00248a, 0x3a000814, 0x3a000814},
269 {0x0000a540, 0x4202242c, 0x4202242c, 0x4102242c, 0x4102242c, 0x3f02242c, 0x3f02242c, 0x3f001a0c, 0x3f001a0c},
270 {0x0000a544, 0x490044c6, 0x490044c6, 0x460044c6, 0x460044c6, 0x420044c6, 0x420044c6, 0x43001a0e, 0x43001a0e},
271 {0x0000a548, 0x4d024485, 0x4d024485, 0x4a024485, 0x4a024485, 0x46024485, 0x46024485, 0x46001812, 0x46001812},
272 {0x0000a54c, 0x51044483, 0x51044483, 0x4e044483, 0x4e044483, 0x4a044483, 0x4a044483, 0x49001884, 0x49001884},
273 {0x0000a550, 0x5404a40c, 0x5404a40c, 0x5204a40c, 0x5204a40c, 0x4d04a40c, 0x4d04a40c, 0x4d001e84, 0x4d001e84},
274 {0x0000a554, 0x57024632, 0x57024632, 0x55024632, 0x55024632, 0x52024632, 0x52024632, 0x50001e69, 0x50001e69},
275 {0x0000a558, 0x5c00a634, 0x5c00a634, 0x5900a634, 0x5900a634, 0x5600a634, 0x5600a634, 0x550006f4, 0x550006f4},
276 {0x0000a55c, 0x5f026832, 0x5f026832, 0x5d026832, 0x5d026832, 0x5a026832, 0x5a026832, 0x59000ad3, 0x59000ad3},
277 {0x0000a560, 0x6602b012, 0x6602b012, 0x6202b012, 0x6202b012, 0x5d02b012, 0x5d02b012, 0x5e000ad5, 0x5e000ad5},
278 {0x0000a564, 0x6e02d0e1, 0x6e02d0e1, 0x6802d0e1, 0x6802d0e1, 0x6002d0e1, 0x6002d0e1, 0x61001ced, 0x61001ced},
279 {0x0000a568, 0x7202b4c4, 0x7202b4c4, 0x6c02b4c4, 0x6c02b4c4, 0x6502b4c4, 0x6502b4c4, 0x660018d4, 0x660018d4},
280 {0x0000a56c, 0x75007894, 0x75007894, 0x70007894, 0x70007894, 0x6b007894, 0x6b007894, 0x660018d4, 0x660018d4},
281 {0x0000a570, 0x7b025c74, 0x7b025c74, 0x75025c74, 0x75025c74, 0x70025c74, 0x70025c74, 0x660018d4, 0x660018d4},
282 {0x0000a574, 0x8300bcb5, 0x8300bcb5, 0x7a00bcb5, 0x7a00bcb5, 0x7600bcb5, 0x7600bcb5, 0x660018d4, 0x660018d4},
283 {0x0000a578, 0x8a04dc74, 0x8a04dc74, 0x7f04dc74, 0x7f04dc74, 0x7c04dc74, 0x7c04dc74, 0x660018d4, 0x660018d4},
284 {0x0000a57c, 0x8a04dc74, 0x8a04dc74, 0x7f04dc74, 0x7f04dc74, 0x7c04dc74, 0x7c04dc74, 0x660018d4, 0x660018d4},
285 {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
286 {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
287 {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
288 {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03804000, 0x03804000},
289 {0x0000a610, 0x04c08c01, 0x04c08c01, 0x04808b01, 0x04808b01, 0x04808a01, 0x04808a01, 0x0300ca02, 0x0300ca02},
290 {0x0000a614, 0x00c0c303, 0x00c0c303, 0x00c0c303, 0x00c0c303, 0x00c0c303, 0x00c0c303, 0x00000e04, 0x00000e04},
291 {0x0000a618, 0x04010c01, 0x04010c01, 0x03c10b01, 0x03c10b01, 0x03810a01, 0x03810a01, 0x03014000, 0x03014000},
292 {0x0000a61c, 0x03814e05, 0x03814e05, 0x03414d05, 0x03414d05, 0x03414d05, 0x03414d05, 0x00000000, 0x00000000},
293 {0x0000a620, 0x04010303, 0x04010303, 0x03c10303, 0x03c10303, 0x03810303, 0x03810303, 0x00000000, 0x00000000},
294 {0x0000a624, 0x03814e05, 0x03814e05, 0x03414d05, 0x03414d05, 0x03414d05, 0x03414d05, 0x03014000, 0x03014000},
295 {0x0000a628, 0x00c0c000, 0x00c0c000, 0x00c0c000, 0x00c0c000, 0x00c0c000, 0x00c0c000, 0x03804c05, 0x03804c05},
296 {0x0000a62c, 0x00c0c303, 0x00c0c303, 0x00c0c303, 0x00c0c303, 0x00c0c303, 0x00c0c303, 0x0701de06, 0x0701de06},
297 {0x0000a630, 0x03418000, 0x03418000, 0x03018000, 0x03018000, 0x02c18000, 0x02c18000, 0x07819c07, 0x07819c07},
298 {0x0000a634, 0x03815004, 0x03815004, 0x03414f04, 0x03414f04, 0x03414e04, 0x03414e04, 0x0701dc07, 0x0701dc07},
299 {0x0000a638, 0x03005302, 0x03005302, 0x02c05202, 0x02c05202, 0x02805202, 0x02805202, 0x0701dc07, 0x0701dc07},
300 {0x0000a63c, 0x04c09302, 0x04c09302, 0x04809202, 0x04809202, 0x04809202, 0x04809202, 0x0701dc07, 0x0701dc07},
301 {0x0000b2dc, 0xffffaaaa, 0xffffaaaa, 0xffffaaaa, 0xffffaaaa, 0xffffaaaa, 0xffffaaaa, 0xfffd5aaa, 0xfffd5aaa},
302 {0x0000b2e0, 0xffffcccc, 0xffffcccc, 0xffffcccc, 0xffffcccc, 0xffffcccc, 0xffffcccc, 0xfffe9ccc, 0xfffe9ccc},
303 {0x0000b2e4, 0xfffff0f0, 0xfffff0f0, 0xfffff0f0, 0xfffff0f0, 0xfffff0f0, 0xfffff0f0, 0xffffe0f0, 0xffffe0f0},
304 {0x0000b2e8, 0xffffff00, 0xffffff00, 0xffffff00, 0xffffff00, 0xffffff00, 0xffffff00, 0xfffcff00, 0xfffcff00},
305 {0x0000c2dc, 0xffffaaaa, 0xffffaaaa, 0xffffaaaa, 0xffffaaaa, 0xffffaaaa, 0xffffaaaa, 0xfffd5aaa, 0xfffd5aaa},
306 {0x0000c2e0, 0xffffcccc, 0xffffcccc, 0xffffcccc, 0xffffcccc, 0xffffcccc, 0xffffcccc, 0xfffe9ccc, 0xfffe9ccc},
307 {0x0000c2e4, 0xfffff0f0, 0xfffff0f0, 0xfffff0f0, 0xfffff0f0, 0xfffff0f0, 0xfffff0f0, 0xffffe0f0, 0xffffe0f0},
308 {0x0000c2e8, 0xffffff00, 0xffffff00, 0xffffff00, 0xffffff00, 0xffffff00, 0xffffff00, 0xfffcff00, 0xfffcff00},
309 {0x00016044, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x010002d4, 0x010002d4},
310 {0x00016048, 0x62482401, 0x62482401, 0x62482401, 0x62482401, 0x62482401, 0x62482401, 0x66482401, 0x66482401},
311 {0x00016280, 0x01801e84, 0x01801e84, 0x01801e84, 0x01801e84, 0x01801e84, 0x01801e84, 0x01808e84, 0x01808e84},
312 {0x00016444, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x010002d4, 0x010002d4},
313 {0x00016448, 0x62482401, 0x62482401, 0x62482401, 0x62482401, 0x62482401, 0x62482401, 0x66482401, 0x66482401},
314 {0x00016844, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x010002d4, 0x010002d4},
315 {0x00016848, 0x62482401, 0x62482401, 0x62482401, 0x62482401, 0x62482401, 0x62482401, 0x66482401, 0x66482401},
316};
317
318static const u32 ar955x_1p0_mac_core[][2] = {
319 /* Addr allmodes */
320 {0x00000008, 0x00000000},
321 {0x00000030, 0x00020085},
322 {0x00000034, 0x00000005},
323 {0x00000040, 0x00000000},
324 {0x00000044, 0x00000000},
325 {0x00000048, 0x00000008},
326 {0x0000004c, 0x00000010},
327 {0x00000050, 0x00000000},
328 {0x00001040, 0x002ffc0f},
329 {0x00001044, 0x002ffc0f},
330 {0x00001048, 0x002ffc0f},
331 {0x0000104c, 0x002ffc0f},
332 {0x00001050, 0x002ffc0f},
333 {0x00001054, 0x002ffc0f},
334 {0x00001058, 0x002ffc0f},
335 {0x0000105c, 0x002ffc0f},
336 {0x00001060, 0x002ffc0f},
337 {0x00001064, 0x002ffc0f},
338 {0x000010f0, 0x00000100},
339 {0x00001270, 0x00000000},
340 {0x000012b0, 0x00000000},
341 {0x000012f0, 0x00000000},
342 {0x0000143c, 0x00000000},
343 {0x0000147c, 0x00000000},
344 {0x00008000, 0x00000000},
345 {0x00008004, 0x00000000},
346 {0x00008008, 0x00000000},
347 {0x0000800c, 0x00000000},
348 {0x00008018, 0x00000000},
349 {0x00008020, 0x00000000},
350 {0x00008038, 0x00000000},
351 {0x0000803c, 0x00000000},
352 {0x00008040, 0x00000000},
353 {0x00008044, 0x00000000},
354 {0x00008048, 0x00000000},
355 {0x0000804c, 0xffffffff},
356 {0x00008054, 0x00000000},
357 {0x00008058, 0x00000000},
358 {0x0000805c, 0x000fc78f},
359 {0x00008060, 0x0000000f},
360 {0x00008064, 0x00000000},
361 {0x00008070, 0x00000310},
362 {0x00008074, 0x00000020},
363 {0x00008078, 0x00000000},
364 {0x0000809c, 0x0000000f},
365 {0x000080a0, 0x00000000},
366 {0x000080a4, 0x02ff0000},
367 {0x000080a8, 0x0e070605},
368 {0x000080ac, 0x0000000d},
369 {0x000080b0, 0x00000000},
370 {0x000080b4, 0x00000000},
371 {0x000080b8, 0x00000000},
372 {0x000080bc, 0x00000000},
373 {0x000080c0, 0x2a800000},
374 {0x000080c4, 0x06900168},
375 {0x000080c8, 0x13881c22},
376 {0x000080cc, 0x01f40000},
377 {0x000080d0, 0x00252500},
378 {0x000080d4, 0x00a00000},
379 {0x000080d8, 0x00400000},
380 {0x000080dc, 0x00000000},
381 {0x000080e0, 0xffffffff},
382 {0x000080e4, 0x0000ffff},
383 {0x000080e8, 0x3f3f3f3f},
384 {0x000080ec, 0x00000000},
385 {0x000080f0, 0x00000000},
386 {0x000080f4, 0x00000000},
387 {0x000080fc, 0x00020000},
388 {0x00008100, 0x00000000},
389 {0x00008108, 0x00000052},
390 {0x0000810c, 0x00000000},
391 {0x00008110, 0x00000000},
392 {0x00008114, 0x000007ff},
393 {0x00008118, 0x000000aa},
394 {0x0000811c, 0x00003210},
395 {0x00008124, 0x00000000},
396 {0x00008128, 0x00000000},
397 {0x0000812c, 0x00000000},
398 {0x00008130, 0x00000000},
399 {0x00008134, 0x00000000},
400 {0x00008138, 0x00000000},
401 {0x0000813c, 0x0000ffff},
402 {0x00008140, 0x000000fe},
403 {0x00008144, 0xffffffff},
404 {0x00008168, 0x00000000},
405 {0x0000816c, 0x00000000},
406 {0x000081c0, 0x00000000},
407 {0x000081c4, 0x33332210},
408 {0x000081ec, 0x00000000},
409 {0x000081f0, 0x00000000},
410 {0x000081f4, 0x00000000},
411 {0x000081f8, 0x00000000},
412 {0x000081fc, 0x00000000},
413 {0x00008240, 0x00100000},
414 {0x00008244, 0x0010f400},
415 {0x00008248, 0x00000800},
416 {0x0000824c, 0x0001e800},
417 {0x00008250, 0x00000000},
418 {0x00008254, 0x00000000},
419 {0x00008258, 0x00000000},
420 {0x0000825c, 0x40000000},
421 {0x00008260, 0x00080922},
422 {0x00008264, 0x9d400010},
423 {0x00008268, 0xffffffff},
424 {0x0000826c, 0x0000ffff},
425 {0x00008270, 0x00000000},
426 {0x00008274, 0x40000000},
427 {0x00008278, 0x003e4180},
428 {0x0000827c, 0x00000004},
429 {0x00008284, 0x0000002c},
430 {0x00008288, 0x0000002c},
431 {0x0000828c, 0x000000ff},
432 {0x00008294, 0x00000000},
433 {0x00008298, 0x00000000},
434 {0x0000829c, 0x00000000},
435 {0x00008300, 0x00001d40},
436 {0x00008314, 0x00000000},
437 {0x0000831c, 0x0000010d},
438 {0x00008328, 0x00000000},
439 {0x0000832c, 0x0000001f},
440 {0x00008330, 0x00000302},
441 {0x00008334, 0x00000700},
442 {0x00008338, 0xffff0000},
443 {0x0000833c, 0x02400000},
444 {0x00008340, 0x000107ff},
445 {0x00008344, 0xaa48107b},
446 {0x00008348, 0x008f0000},
447 {0x0000835c, 0x00000000},
448 {0x00008360, 0xffffffff},
449 {0x00008364, 0xffffffff},
450 {0x00008368, 0x00000000},
451 {0x00008370, 0x00000000},
452 {0x00008374, 0x000000ff},
453 {0x00008378, 0x00000000},
454 {0x0000837c, 0x00000000},
455 {0x00008380, 0xffffffff},
456 {0x00008384, 0xffffffff},
457 {0x00008390, 0xffffffff},
458 {0x00008394, 0xffffffff},
459 {0x00008398, 0x00000000},
460 {0x0000839c, 0x00000000},
461 {0x000083a0, 0x00000000},
462 {0x000083a4, 0x0000fa14},
463 {0x000083a8, 0x000f0c00},
464 {0x000083ac, 0x33332210},
465 {0x000083b0, 0x33332210},
466 {0x000083b4, 0x33332210},
467 {0x000083b8, 0x33332210},
468 {0x000083bc, 0x00000000},
469 {0x000083c0, 0x00000000},
470 {0x000083c4, 0x00000000},
471 {0x000083c8, 0x00000000},
472 {0x000083cc, 0x00000200},
473 {0x000083d0, 0x8c7901ff},
474};
475
476static const u32 ar955x_1p0_common_rx_gain_table[][2] = {
477 /* Addr allmodes */
478 {0x0000a000, 0x00010000},
479 {0x0000a004, 0x00030002},
480 {0x0000a008, 0x00050004},
481 {0x0000a00c, 0x00810080},
482 {0x0000a010, 0x00830082},
483 {0x0000a014, 0x01810180},
484 {0x0000a018, 0x01830182},
485 {0x0000a01c, 0x01850184},
486 {0x0000a020, 0x01890188},
487 {0x0000a024, 0x018b018a},
488 {0x0000a028, 0x018d018c},
489 {0x0000a02c, 0x01910190},
490 {0x0000a030, 0x01930192},
491 {0x0000a034, 0x01950194},
492 {0x0000a038, 0x038a0196},
493 {0x0000a03c, 0x038c038b},
494 {0x0000a040, 0x0390038d},
495 {0x0000a044, 0x03920391},
496 {0x0000a048, 0x03940393},
497 {0x0000a04c, 0x03960395},
498 {0x0000a050, 0x00000000},
499 {0x0000a054, 0x00000000},
500 {0x0000a058, 0x00000000},
501 {0x0000a05c, 0x00000000},
502 {0x0000a060, 0x00000000},
503 {0x0000a064, 0x00000000},
504 {0x0000a068, 0x00000000},
505 {0x0000a06c, 0x00000000},
506 {0x0000a070, 0x00000000},
507 {0x0000a074, 0x00000000},
508 {0x0000a078, 0x00000000},
509 {0x0000a07c, 0x00000000},
510 {0x0000a080, 0x22222229},
511 {0x0000a084, 0x1d1d1d1d},
512 {0x0000a088, 0x1d1d1d1d},
513 {0x0000a08c, 0x1d1d1d1d},
514 {0x0000a090, 0x171d1d1d},
515 {0x0000a094, 0x11111717},
516 {0x0000a098, 0x00030311},
517 {0x0000a09c, 0x00000000},
518 {0x0000a0a0, 0x00000000},
519 {0x0000a0a4, 0x00000000},
520 {0x0000a0a8, 0x00000000},
521 {0x0000a0ac, 0x00000000},
522 {0x0000a0b0, 0x00000000},
523 {0x0000a0b4, 0x00000000},
524 {0x0000a0b8, 0x00000000},
525 {0x0000a0bc, 0x00000000},
526 {0x0000a0c0, 0x001f0000},
527 {0x0000a0c4, 0x01000101},
528 {0x0000a0c8, 0x011e011f},
529 {0x0000a0cc, 0x011c011d},
530 {0x0000a0d0, 0x02030204},
531 {0x0000a0d4, 0x02010202},
532 {0x0000a0d8, 0x021f0200},
533 {0x0000a0dc, 0x0302021e},
534 {0x0000a0e0, 0x03000301},
535 {0x0000a0e4, 0x031e031f},
536 {0x0000a0e8, 0x0402031d},
537 {0x0000a0ec, 0x04000401},
538 {0x0000a0f0, 0x041e041f},
539 {0x0000a0f4, 0x0502041d},
540 {0x0000a0f8, 0x05000501},
541 {0x0000a0fc, 0x051e051f},
542 {0x0000a100, 0x06010602},
543 {0x0000a104, 0x061f0600},
544 {0x0000a108, 0x061d061e},
545 {0x0000a10c, 0x07020703},
546 {0x0000a110, 0x07000701},
547 {0x0000a114, 0x00000000},
548 {0x0000a118, 0x00000000},
549 {0x0000a11c, 0x00000000},
550 {0x0000a120, 0x00000000},
551 {0x0000a124, 0x00000000},
552 {0x0000a128, 0x00000000},
553 {0x0000a12c, 0x00000000},
554 {0x0000a130, 0x00000000},
555 {0x0000a134, 0x00000000},
556 {0x0000a138, 0x00000000},
557 {0x0000a13c, 0x00000000},
558 {0x0000a140, 0x001f0000},
559 {0x0000a144, 0x01000101},
560 {0x0000a148, 0x011e011f},
561 {0x0000a14c, 0x011c011d},
562 {0x0000a150, 0x02030204},
563 {0x0000a154, 0x02010202},
564 {0x0000a158, 0x021f0200},
565 {0x0000a15c, 0x0302021e},
566 {0x0000a160, 0x03000301},
567 {0x0000a164, 0x031e031f},
568 {0x0000a168, 0x0402031d},
569 {0x0000a16c, 0x04000401},
570 {0x0000a170, 0x041e041f},
571 {0x0000a174, 0x0502041d},
572 {0x0000a178, 0x05000501},
573 {0x0000a17c, 0x051e051f},
574 {0x0000a180, 0x06010602},
575 {0x0000a184, 0x061f0600},
576 {0x0000a188, 0x061d061e},
577 {0x0000a18c, 0x07020703},
578 {0x0000a190, 0x07000701},
579 {0x0000a194, 0x00000000},
580 {0x0000a198, 0x00000000},
581 {0x0000a19c, 0x00000000},
582 {0x0000a1a0, 0x00000000},
583 {0x0000a1a4, 0x00000000},
584 {0x0000a1a8, 0x00000000},
585 {0x0000a1ac, 0x00000000},
586 {0x0000a1b0, 0x00000000},
587 {0x0000a1b4, 0x00000000},
588 {0x0000a1b8, 0x00000000},
589 {0x0000a1bc, 0x00000000},
590 {0x0000a1c0, 0x00000000},
591 {0x0000a1c4, 0x00000000},
592 {0x0000a1c8, 0x00000000},
593 {0x0000a1cc, 0x00000000},
594 {0x0000a1d0, 0x00000000},
595 {0x0000a1d4, 0x00000000},
596 {0x0000a1d8, 0x00000000},
597 {0x0000a1dc, 0x00000000},
598 {0x0000a1e0, 0x00000000},
599 {0x0000a1e4, 0x00000000},
600 {0x0000a1e8, 0x00000000},
601 {0x0000a1ec, 0x00000000},
602 {0x0000a1f0, 0x00000396},
603 {0x0000a1f4, 0x00000396},
604 {0x0000a1f8, 0x00000396},
605 {0x0000a1fc, 0x00000196},
606 {0x0000b000, 0x00010000},
607 {0x0000b004, 0x00030002},
608 {0x0000b008, 0x00050004},
609 {0x0000b00c, 0x00810080},
610 {0x0000b010, 0x00830082},
611 {0x0000b014, 0x01810180},
612 {0x0000b018, 0x01830182},
613 {0x0000b01c, 0x01850184},
614 {0x0000b020, 0x02810280},
615 {0x0000b024, 0x02830282},
616 {0x0000b028, 0x02850284},
617 {0x0000b02c, 0x02890288},
618 {0x0000b030, 0x028b028a},
619 {0x0000b034, 0x0388028c},
620 {0x0000b038, 0x038a0389},
621 {0x0000b03c, 0x038c038b},
622 {0x0000b040, 0x0390038d},
623 {0x0000b044, 0x03920391},
624 {0x0000b048, 0x03940393},
625 {0x0000b04c, 0x03960395},
626 {0x0000b050, 0x00000000},
627 {0x0000b054, 0x00000000},
628 {0x0000b058, 0x00000000},
629 {0x0000b05c, 0x00000000},
630 {0x0000b060, 0x00000000},
631 {0x0000b064, 0x00000000},
632 {0x0000b068, 0x00000000},
633 {0x0000b06c, 0x00000000},
634 {0x0000b070, 0x00000000},
635 {0x0000b074, 0x00000000},
636 {0x0000b078, 0x00000000},
637 {0x0000b07c, 0x00000000},
638 {0x0000b080, 0x23232323},
639 {0x0000b084, 0x21232323},
640 {0x0000b088, 0x19191c1e},
641 {0x0000b08c, 0x12141417},
642 {0x0000b090, 0x07070e0e},
643 {0x0000b094, 0x03030305},
644 {0x0000b098, 0x00000003},
645 {0x0000b09c, 0x00000000},
646 {0x0000b0a0, 0x00000000},
647 {0x0000b0a4, 0x00000000},
648 {0x0000b0a8, 0x00000000},
649 {0x0000b0ac, 0x00000000},
650 {0x0000b0b0, 0x00000000},
651 {0x0000b0b4, 0x00000000},
652 {0x0000b0b8, 0x00000000},
653 {0x0000b0bc, 0x00000000},
654 {0x0000b0c0, 0x003f0020},
655 {0x0000b0c4, 0x00400041},
656 {0x0000b0c8, 0x0140005f},
657 {0x0000b0cc, 0x0160015f},
658 {0x0000b0d0, 0x017e017f},
659 {0x0000b0d4, 0x02410242},
660 {0x0000b0d8, 0x025f0240},
661 {0x0000b0dc, 0x027f0260},
662 {0x0000b0e0, 0x0341027e},
663 {0x0000b0e4, 0x035f0340},
664 {0x0000b0e8, 0x037f0360},
665 {0x0000b0ec, 0x04400441},
666 {0x0000b0f0, 0x0460045f},
667 {0x0000b0f4, 0x0541047f},
668 {0x0000b0f8, 0x055f0540},
669 {0x0000b0fc, 0x057f0560},
670 {0x0000b100, 0x06400641},
671 {0x0000b104, 0x0660065f},
672 {0x0000b108, 0x067e067f},
673 {0x0000b10c, 0x07410742},
674 {0x0000b110, 0x075f0740},
675 {0x0000b114, 0x077f0760},
676 {0x0000b118, 0x07800781},
677 {0x0000b11c, 0x07a0079f},
678 {0x0000b120, 0x07c107bf},
679 {0x0000b124, 0x000007c0},
680 {0x0000b128, 0x00000000},
681 {0x0000b12c, 0x00000000},
682 {0x0000b130, 0x00000000},
683 {0x0000b134, 0x00000000},
684 {0x0000b138, 0x00000000},
685 {0x0000b13c, 0x00000000},
686 {0x0000b140, 0x003f0020},
687 {0x0000b144, 0x00400041},
688 {0x0000b148, 0x0140005f},
689 {0x0000b14c, 0x0160015f},
690 {0x0000b150, 0x017e017f},
691 {0x0000b154, 0x02410242},
692 {0x0000b158, 0x025f0240},
693 {0x0000b15c, 0x027f0260},
694 {0x0000b160, 0x0341027e},
695 {0x0000b164, 0x035f0340},
696 {0x0000b168, 0x037f0360},
697 {0x0000b16c, 0x04400441},
698 {0x0000b170, 0x0460045f},
699 {0x0000b174, 0x0541047f},
700 {0x0000b178, 0x055f0540},
701 {0x0000b17c, 0x057f0560},
702 {0x0000b180, 0x06400641},
703 {0x0000b184, 0x0660065f},
704 {0x0000b188, 0x067e067f},
705 {0x0000b18c, 0x07410742},
706 {0x0000b190, 0x075f0740},
707 {0x0000b194, 0x077f0760},
708 {0x0000b198, 0x07800781},
709 {0x0000b19c, 0x07a0079f},
710 {0x0000b1a0, 0x07c107bf},
711 {0x0000b1a4, 0x000007c0},
712 {0x0000b1a8, 0x00000000},
713 {0x0000b1ac, 0x00000000},
714 {0x0000b1b0, 0x00000000},
715 {0x0000b1b4, 0x00000000},
716 {0x0000b1b8, 0x00000000},
717 {0x0000b1bc, 0x00000000},
718 {0x0000b1c0, 0x00000000},
719 {0x0000b1c4, 0x00000000},
720 {0x0000b1c8, 0x00000000},
721 {0x0000b1cc, 0x00000000},
722 {0x0000b1d0, 0x00000000},
723 {0x0000b1d4, 0x00000000},
724 {0x0000b1d8, 0x00000000},
725 {0x0000b1dc, 0x00000000},
726 {0x0000b1e0, 0x00000000},
727 {0x0000b1e4, 0x00000000},
728 {0x0000b1e8, 0x00000000},
729 {0x0000b1ec, 0x00000000},
730 {0x0000b1f0, 0x00000396},
731 {0x0000b1f4, 0x00000396},
732 {0x0000b1f8, 0x00000396},
733 {0x0000b1fc, 0x00000196},
734};
735
736static const u32 ar955x_1p0_baseband_core[][2] = {
737 /* Addr allmodes */
738 {0x00009800, 0xafe68e30},
739 {0x00009804, 0xfd14e000},
740 {0x00009808, 0x9c0a9f6b},
741 {0x0000980c, 0x04900000},
742 {0x00009814, 0x0280c00a},
743 {0x00009818, 0x00000000},
744 {0x0000981c, 0x00020028},
745 {0x00009834, 0x6400a190},
746 {0x00009838, 0x0108ecff},
747 {0x0000983c, 0x14000600},
748 {0x00009880, 0x201fff00},
749 {0x00009884, 0x00001042},
750 {0x000098a4, 0x00200400},
751 {0x000098b0, 0x32840bbe},
752 {0x000098bc, 0x00000002},
753 {0x000098d0, 0x004b6a8e},
754 {0x000098d4, 0x00000820},
755 {0x000098dc, 0x00000000},
756 {0x000098f0, 0x00000000},
757 {0x000098f4, 0x00000000},
758 {0x00009c04, 0xff55ff55},
759 {0x00009c08, 0x0320ff55},
760 {0x00009c0c, 0x00000000},
761 {0x00009c10, 0x00000000},
762 {0x00009c14, 0x00046384},
763 {0x00009c18, 0x05b6b440},
764 {0x00009c1c, 0x00b6b440},
765 {0x00009d00, 0xc080a333},
766 {0x00009d04, 0x40206c10},
767 {0x00009d08, 0x009c4060},
768 {0x00009d0c, 0x9883800a},
769 {0x00009d10, 0x01834061},
770 {0x00009d14, 0x00c0040b},
771 {0x00009d18, 0x00000000},
772 {0x00009e08, 0x0038230c},
773 {0x00009e24, 0x990bb515},
774 {0x00009e28, 0x0c6f0000},
775 {0x00009e30, 0x06336f77},
776 {0x00009e34, 0x6af6532f},
777 {0x00009e38, 0x0cc80c00},
778 {0x00009e40, 0x0d261820},
779 {0x00009e4c, 0x00001004},
780 {0x00009e50, 0x00ff03f1},
781 {0x00009fc0, 0x813e4788},
782 {0x00009fc4, 0x0001efb5},
783 {0x00009fcc, 0x40000014},
784 {0x00009fd0, 0x01193b93},
785 {0x0000a20c, 0x00000000},
786 {0x0000a220, 0x00000000},
787 {0x0000a224, 0x00000000},
788 {0x0000a228, 0x10002310},
789 {0x0000a23c, 0x00000000},
790 {0x0000a244, 0x0c000000},
791 {0x0000a248, 0x00000140},
792 {0x0000a2a0, 0x00000007},
793 {0x0000a2c0, 0x00000007},
794 {0x0000a2c8, 0x00000000},
795 {0x0000a2d4, 0x00000000},
796 {0x0000a2ec, 0x00000000},
797 {0x0000a2f0, 0x00000000},
798 {0x0000a2f4, 0x00000000},
799 {0x0000a2f8, 0x00000000},
800 {0x0000a344, 0x00000000},
801 {0x0000a34c, 0x00000000},
802 {0x0000a350, 0x0000a000},
803 {0x0000a364, 0x00000000},
804 {0x0000a370, 0x00000000},
805 {0x0000a390, 0x00000001},
806 {0x0000a394, 0x00000444},
807 {0x0000a398, 0x1f020503},
808 {0x0000a39c, 0x29180c03},
809 {0x0000a3a0, 0x9a8b6844},
810 {0x0000a3a4, 0x00000000},
811 {0x0000a3a8, 0xaaaaaaaa},
812 {0x0000a3ac, 0x3c466478},
813 {0x0000a3c0, 0x20202020},
814 {0x0000a3c4, 0x22222220},
815 {0x0000a3c8, 0x20200020},
816 {0x0000a3cc, 0x20202020},
817 {0x0000a3d0, 0x20202020},
818 {0x0000a3d4, 0x20202020},
819 {0x0000a3d8, 0x20202020},
820 {0x0000a3dc, 0x20202020},
821 {0x0000a3e0, 0x20202020},
822 {0x0000a3e4, 0x20202020},
823 {0x0000a3e8, 0x20202020},
824 {0x0000a3ec, 0x20202020},
825 {0x0000a3f0, 0x00000000},
826 {0x0000a3f4, 0x00000000},
827 {0x0000a3f8, 0x0c9bd380},
828 {0x0000a3fc, 0x000f0f01},
829 {0x0000a400, 0x8fa91f01},
830 {0x0000a404, 0x00000000},
831 {0x0000a408, 0x0e79e5c6},
832 {0x0000a40c, 0x00820820},
833 {0x0000a414, 0x1ce739ce},
834 {0x0000a418, 0x2d001dce},
835 {0x0000a41c, 0x1ce739ce},
836 {0x0000a420, 0x000001ce},
837 {0x0000a424, 0x1ce739ce},
838 {0x0000a428, 0x000001ce},
839 {0x0000a42c, 0x1ce739ce},
840 {0x0000a430, 0x1ce739ce},
841 {0x0000a434, 0x00000000},
842 {0x0000a438, 0x00001801},
843 {0x0000a43c, 0x00100000},
844 {0x0000a444, 0x00000000},
845 {0x0000a448, 0x05000080},
846 {0x0000a44c, 0x00000001},
847 {0x0000a450, 0x00010000},
848 {0x0000a458, 0x00000000},
849 {0x0000a644, 0x3fad9d74},
850 {0x0000a648, 0x0048060a},
851 {0x0000a64c, 0x00003c37},
852 {0x0000a670, 0x03020100},
853 {0x0000a674, 0x09080504},
854 {0x0000a678, 0x0d0c0b0a},
855 {0x0000a67c, 0x13121110},
856 {0x0000a680, 0x31301514},
857 {0x0000a684, 0x35343332},
858 {0x0000a688, 0x00000036},
859 {0x0000a690, 0x00000838},
860 {0x0000a7cc, 0x00000000},
861 {0x0000a7d0, 0x00000000},
862 {0x0000a7d4, 0x00000004},
863 {0x0000a7dc, 0x00000000},
864 {0x0000a8d0, 0x004b6a8e},
865 {0x0000a8d4, 0x00000820},
866 {0x0000a8dc, 0x00000000},
867 {0x0000a8f0, 0x00000000},
868 {0x0000a8f4, 0x00000000},
869 {0x0000b2d0, 0x00000080},
870 {0x0000b2d4, 0x00000000},
871 {0x0000b2ec, 0x00000000},
872 {0x0000b2f0, 0x00000000},
873 {0x0000b2f4, 0x00000000},
874 {0x0000b2f8, 0x00000000},
875 {0x0000b408, 0x0e79e5c0},
876 {0x0000b40c, 0x00820820},
877 {0x0000b420, 0x00000000},
878 {0x0000b8d0, 0x004b6a8e},
879 {0x0000b8d4, 0x00000820},
880 {0x0000b8dc, 0x00000000},
881 {0x0000b8f0, 0x00000000},
882 {0x0000b8f4, 0x00000000},
883 {0x0000c2d0, 0x00000080},
884 {0x0000c2d4, 0x00000000},
885 {0x0000c2ec, 0x00000000},
886 {0x0000c2f0, 0x00000000},
887 {0x0000c2f4, 0x00000000},
888 {0x0000c2f8, 0x00000000},
889 {0x0000c408, 0x0e79e5c0},
890 {0x0000c40c, 0x00820820},
891 {0x0000c420, 0x00000000},
892};
893
894static const u32 ar955x_1p0_common_wo_xlna_rx_gain_table[][2] = {
895 /* Addr allmodes */
896 {0x0000a000, 0x00010000},
897 {0x0000a004, 0x00030002},
898 {0x0000a008, 0x00050004},
899 {0x0000a00c, 0x00810080},
900 {0x0000a010, 0x00830082},
901 {0x0000a014, 0x01810180},
902 {0x0000a018, 0x01830182},
903 {0x0000a01c, 0x01850184},
904 {0x0000a020, 0x01890188},
905 {0x0000a024, 0x018b018a},
906 {0x0000a028, 0x018d018c},
907 {0x0000a02c, 0x03820190},
908 {0x0000a030, 0x03840383},
909 {0x0000a034, 0x03880385},
910 {0x0000a038, 0x038a0389},
911 {0x0000a03c, 0x038c038b},
912 {0x0000a040, 0x0390038d},
913 {0x0000a044, 0x03920391},
914 {0x0000a048, 0x03940393},
915 {0x0000a04c, 0x03960395},
916 {0x0000a050, 0x00000000},
917 {0x0000a054, 0x00000000},
918 {0x0000a058, 0x00000000},
919 {0x0000a05c, 0x00000000},
920 {0x0000a060, 0x00000000},
921 {0x0000a064, 0x00000000},
922 {0x0000a068, 0x00000000},
923 {0x0000a06c, 0x00000000},
924 {0x0000a070, 0x00000000},
925 {0x0000a074, 0x00000000},
926 {0x0000a078, 0x00000000},
927 {0x0000a07c, 0x00000000},
928 {0x0000a080, 0x29292929},
929 {0x0000a084, 0x29292929},
930 {0x0000a088, 0x29292929},
931 {0x0000a08c, 0x29292929},
932 {0x0000a090, 0x22292929},
933 {0x0000a094, 0x1d1d2222},
934 {0x0000a098, 0x0c111117},
935 {0x0000a09c, 0x00030303},
936 {0x0000a0a0, 0x00000000},
937 {0x0000a0a4, 0x00000000},
938 {0x0000a0a8, 0x00000000},
939 {0x0000a0ac, 0x00000000},
940 {0x0000a0b0, 0x00000000},
941 {0x0000a0b4, 0x00000000},
942 {0x0000a0b8, 0x00000000},
943 {0x0000a0bc, 0x00000000},
944 {0x0000a0c0, 0x001f0000},
945 {0x0000a0c4, 0x01000101},
946 {0x0000a0c8, 0x011e011f},
947 {0x0000a0cc, 0x011c011d},
948 {0x0000a0d0, 0x02030204},
949 {0x0000a0d4, 0x02010202},
950 {0x0000a0d8, 0x021f0200},
951 {0x0000a0dc, 0x0302021e},
952 {0x0000a0e0, 0x03000301},
953 {0x0000a0e4, 0x031e031f},
954 {0x0000a0e8, 0x0402031d},
955 {0x0000a0ec, 0x04000401},
956 {0x0000a0f0, 0x041e041f},
957 {0x0000a0f4, 0x0502041d},
958 {0x0000a0f8, 0x05000501},
959 {0x0000a0fc, 0x051e051f},
960 {0x0000a100, 0x06010602},
961 {0x0000a104, 0x061f0600},
962 {0x0000a108, 0x061d061e},
963 {0x0000a10c, 0x07020703},
964 {0x0000a110, 0x07000701},
965 {0x0000a114, 0x00000000},
966 {0x0000a118, 0x00000000},
967 {0x0000a11c, 0x00000000},
968 {0x0000a120, 0x00000000},
969 {0x0000a124, 0x00000000},
970 {0x0000a128, 0x00000000},
971 {0x0000a12c, 0x00000000},
972 {0x0000a130, 0x00000000},
973 {0x0000a134, 0x00000000},
974 {0x0000a138, 0x00000000},
975 {0x0000a13c, 0x00000000},
976 {0x0000a140, 0x001f0000},
977 {0x0000a144, 0x01000101},
978 {0x0000a148, 0x011e011f},
979 {0x0000a14c, 0x011c011d},
980 {0x0000a150, 0x02030204},
981 {0x0000a154, 0x02010202},
982 {0x0000a158, 0x021f0200},
983 {0x0000a15c, 0x0302021e},
984 {0x0000a160, 0x03000301},
985 {0x0000a164, 0x031e031f},
986 {0x0000a168, 0x0402031d},
987 {0x0000a16c, 0x04000401},
988 {0x0000a170, 0x041e041f},
989 {0x0000a174, 0x0502041d},
990 {0x0000a178, 0x05000501},
991 {0x0000a17c, 0x051e051f},
992 {0x0000a180, 0x06010602},
993 {0x0000a184, 0x061f0600},
994 {0x0000a188, 0x061d061e},
995 {0x0000a18c, 0x07020703},
996 {0x0000a190, 0x07000701},
997 {0x0000a194, 0x00000000},
998 {0x0000a198, 0x00000000},
999 {0x0000a19c, 0x00000000},
1000 {0x0000a1a0, 0x00000000},
1001 {0x0000a1a4, 0x00000000},
1002 {0x0000a1a8, 0x00000000},
1003 {0x0000a1ac, 0x00000000},
1004 {0x0000a1b0, 0x00000000},
1005 {0x0000a1b4, 0x00000000},
1006 {0x0000a1b8, 0x00000000},
1007 {0x0000a1bc, 0x00000000},
1008 {0x0000a1c0, 0x00000000},
1009 {0x0000a1c4, 0x00000000},
1010 {0x0000a1c8, 0x00000000},
1011 {0x0000a1cc, 0x00000000},
1012 {0x0000a1d0, 0x00000000},
1013 {0x0000a1d4, 0x00000000},
1014 {0x0000a1d8, 0x00000000},
1015 {0x0000a1dc, 0x00000000},
1016 {0x0000a1e0, 0x00000000},
1017 {0x0000a1e4, 0x00000000},
1018 {0x0000a1e8, 0x00000000},
1019 {0x0000a1ec, 0x00000000},
1020 {0x0000a1f0, 0x00000396},
1021 {0x0000a1f4, 0x00000396},
1022 {0x0000a1f8, 0x00000396},
1023 {0x0000a1fc, 0x00000196},
1024 {0x0000b000, 0x00010000},
1025 {0x0000b004, 0x00030002},
1026 {0x0000b008, 0x00050004},
1027 {0x0000b00c, 0x00810080},
1028 {0x0000b010, 0x00830082},
1029 {0x0000b014, 0x01810180},
1030 {0x0000b018, 0x01830182},
1031 {0x0000b01c, 0x01850184},
1032 {0x0000b020, 0x02810280},
1033 {0x0000b024, 0x02830282},
1034 {0x0000b028, 0x02850284},
1035 {0x0000b02c, 0x02890288},
1036 {0x0000b030, 0x028b028a},
1037 {0x0000b034, 0x0388028c},
1038 {0x0000b038, 0x038a0389},
1039 {0x0000b03c, 0x038c038b},
1040 {0x0000b040, 0x0390038d},
1041 {0x0000b044, 0x03920391},
1042 {0x0000b048, 0x03940393},
1043 {0x0000b04c, 0x03960395},
1044 {0x0000b050, 0x00000000},
1045 {0x0000b054, 0x00000000},
1046 {0x0000b058, 0x00000000},
1047 {0x0000b05c, 0x00000000},
1048 {0x0000b060, 0x00000000},
1049 {0x0000b064, 0x00000000},
1050 {0x0000b068, 0x00000000},
1051 {0x0000b06c, 0x00000000},
1052 {0x0000b070, 0x00000000},
1053 {0x0000b074, 0x00000000},
1054 {0x0000b078, 0x00000000},
1055 {0x0000b07c, 0x00000000},
1056 {0x0000b080, 0x32323232},
1057 {0x0000b084, 0x2f2f3232},
1058 {0x0000b088, 0x23282a2d},
1059 {0x0000b08c, 0x1c1e2123},
1060 {0x0000b090, 0x14171919},
1061 {0x0000b094, 0x0e0e1214},
1062 {0x0000b098, 0x03050707},
1063 {0x0000b09c, 0x00030303},
1064 {0x0000b0a0, 0x00000000},
1065 {0x0000b0a4, 0x00000000},
1066 {0x0000b0a8, 0x00000000},
1067 {0x0000b0ac, 0x00000000},
1068 {0x0000b0b0, 0x00000000},
1069 {0x0000b0b4, 0x00000000},
1070 {0x0000b0b8, 0x00000000},
1071 {0x0000b0bc, 0x00000000},
1072 {0x0000b0c0, 0x003f0020},
1073 {0x0000b0c4, 0x00400041},
1074 {0x0000b0c8, 0x0140005f},
1075 {0x0000b0cc, 0x0160015f},
1076 {0x0000b0d0, 0x017e017f},
1077 {0x0000b0d4, 0x02410242},
1078 {0x0000b0d8, 0x025f0240},
1079 {0x0000b0dc, 0x027f0260},
1080 {0x0000b0e0, 0x0341027e},
1081 {0x0000b0e4, 0x035f0340},
1082 {0x0000b0e8, 0x037f0360},
1083 {0x0000b0ec, 0x04400441},
1084 {0x0000b0f0, 0x0460045f},
1085 {0x0000b0f4, 0x0541047f},
1086 {0x0000b0f8, 0x055f0540},
1087 {0x0000b0fc, 0x057f0560},
1088 {0x0000b100, 0x06400641},
1089 {0x0000b104, 0x0660065f},
1090 {0x0000b108, 0x067e067f},
1091 {0x0000b10c, 0x07410742},
1092 {0x0000b110, 0x075f0740},
1093 {0x0000b114, 0x077f0760},
1094 {0x0000b118, 0x07800781},
1095 {0x0000b11c, 0x07a0079f},
1096 {0x0000b120, 0x07c107bf},
1097 {0x0000b124, 0x000007c0},
1098 {0x0000b128, 0x00000000},
1099 {0x0000b12c, 0x00000000},
1100 {0x0000b130, 0x00000000},
1101 {0x0000b134, 0x00000000},
1102 {0x0000b138, 0x00000000},
1103 {0x0000b13c, 0x00000000},
1104 {0x0000b140, 0x003f0020},
1105 {0x0000b144, 0x00400041},
1106 {0x0000b148, 0x0140005f},
1107 {0x0000b14c, 0x0160015f},
1108 {0x0000b150, 0x017e017f},
1109 {0x0000b154, 0x02410242},
1110 {0x0000b158, 0x025f0240},
1111 {0x0000b15c, 0x027f0260},
1112 {0x0000b160, 0x0341027e},
1113 {0x0000b164, 0x035f0340},
1114 {0x0000b168, 0x037f0360},
1115 {0x0000b16c, 0x04400441},
1116 {0x0000b170, 0x0460045f},
1117 {0x0000b174, 0x0541047f},
1118 {0x0000b178, 0x055f0540},
1119 {0x0000b17c, 0x057f0560},
1120 {0x0000b180, 0x06400641},
1121 {0x0000b184, 0x0660065f},
1122 {0x0000b188, 0x067e067f},
1123 {0x0000b18c, 0x07410742},
1124 {0x0000b190, 0x075f0740},
1125 {0x0000b194, 0x077f0760},
1126 {0x0000b198, 0x07800781},
1127 {0x0000b19c, 0x07a0079f},
1128 {0x0000b1a0, 0x07c107bf},
1129 {0x0000b1a4, 0x000007c0},
1130 {0x0000b1a8, 0x00000000},
1131 {0x0000b1ac, 0x00000000},
1132 {0x0000b1b0, 0x00000000},
1133 {0x0000b1b4, 0x00000000},
1134 {0x0000b1b8, 0x00000000},
1135 {0x0000b1bc, 0x00000000},
1136 {0x0000b1c0, 0x00000000},
1137 {0x0000b1c4, 0x00000000},
1138 {0x0000b1c8, 0x00000000},
1139 {0x0000b1cc, 0x00000000},
1140 {0x0000b1d0, 0x00000000},
1141 {0x0000b1d4, 0x00000000},
1142 {0x0000b1d8, 0x00000000},
1143 {0x0000b1dc, 0x00000000},
1144 {0x0000b1e0, 0x00000000},
1145 {0x0000b1e4, 0x00000000},
1146 {0x0000b1e8, 0x00000000},
1147 {0x0000b1ec, 0x00000000},
1148 {0x0000b1f0, 0x00000396},
1149 {0x0000b1f4, 0x00000396},
1150 {0x0000b1f8, 0x00000396},
1151 {0x0000b1fc, 0x00000196},
1152};
1153
1154static const u32 ar955x_1p0_soc_preamble[][2] = {
1155 /* Addr allmodes */
1156 {0x00007000, 0x00000000},
1157 {0x00007004, 0x00000000},
1158 {0x00007008, 0x00000000},
1159 {0x0000700c, 0x00000000},
1160 {0x0000701c, 0x00000000},
1161 {0x00007020, 0x00000000},
1162 {0x00007024, 0x00000000},
1163 {0x00007028, 0x00000000},
1164 {0x0000702c, 0x00000000},
1165 {0x00007030, 0x00000000},
1166 {0x00007034, 0x00000002},
1167 {0x00007038, 0x000004c2},
1168 {0x00007048, 0x00000000},
1169};
1170
1171static const u32 ar955x_1p0_common_wo_xlna_rx_gain_bounds[][5] = {
1172 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
1173 {0x00009e44, 0xfe321e27, 0xfe321e27, 0xfe291e27, 0xfe291e27},
1174 {0x00009e48, 0x5030201a, 0x5030201a, 0x50302012, 0x50302012},
1175};
1176
1177static const u32 ar955x_1p0_mac_postamble[][5] = {
1178 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
1179 {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
1180 {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
1181 {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
1182 {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
1183 {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
1184 {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
1185 {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
1186 {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
1187};
1188
1189static const u32 ar955x_1p0_common_rx_gain_bounds[][5] = {
1190 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
1191 {0x00009e44, 0xfe321e27, 0xfe321e27, 0xfe291e27, 0xfe291e27},
1192 {0x00009e48, 0x5030201a, 0x5030201a, 0x50302018, 0x50302018},
1193};
1194
1195static const u32 ar955x_1p0_modes_no_xpa_tx_gain_table[][9] = {
1196 /* Addr 5G_HT20_L 5G_HT40_L 5G_HT20_M 5G_HT40_M 5G_HT20_H 5G_HT40_H 2G_HT40 2G_HT20 */
1197 {0x0000a2dc, 0x01feee00, 0x01feee00, 0x01feee00, 0x01feee00, 0x01feee00, 0x01feee00, 0xfffe5aaa, 0xfffe5aaa},
1198 {0x0000a2e0, 0x0000f000, 0x0000f000, 0x0000f000, 0x0000f000, 0x0000f000, 0x0000f000, 0xfffe9ccc, 0xfffe9ccc},
1199 {0x0000a2e4, 0x01ff0000, 0x01ff0000, 0x01ff0000, 0x01ff0000, 0x01ff0000, 0x01ff0000, 0xffffe0f0, 0xffffe0f0},
1200 {0x0000a2e8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffffef00, 0xffffef00},
1201 {0x0000a410, 0x000050d8, 0x000050d8, 0x000050d8, 0x000050d8, 0x000050d8, 0x000050d8, 0x000050d7, 0x000050d7},
1202 {0x0000a500, 0x00002220, 0x00002220, 0x00002220, 0x00002220, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
1203 {0x0000a504, 0x04002222, 0x04002222, 0x04002222, 0x04002222, 0x04002222, 0x04002222, 0x04000002, 0x04000002},
1204 {0x0000a508, 0x09002421, 0x09002421, 0x09002421, 0x09002421, 0x09002421, 0x09002421, 0x08000004, 0x08000004},
1205 {0x0000a50c, 0x0d002621, 0x0d002621, 0x0d002621, 0x0d002621, 0x0d002621, 0x0d002621, 0x0b000006, 0x0b000006},
1206 {0x0000a510, 0x13004620, 0x13004620, 0x13004620, 0x13004620, 0x13004620, 0x13004620, 0x0f00000a, 0x0f00000a},
1207 {0x0000a514, 0x19004a20, 0x19004a20, 0x19004a20, 0x19004a20, 0x19004a20, 0x19004a20, 0x1300000c, 0x1300000c},
1208 {0x0000a518, 0x1d004e20, 0x1d004e20, 0x1d004e20, 0x1d004e20, 0x1d004e20, 0x1d004e20, 0x1700000e, 0x1700000e},
1209 {0x0000a51c, 0x21005420, 0x21005420, 0x21005420, 0x21005420, 0x21005420, 0x21005420, 0x1b000012, 0x1b000012},
1210 {0x0000a520, 0x26005e20, 0x26005e20, 0x26005e20, 0x26005e20, 0x26005e20, 0x26005e20, 0x1f00004a, 0x1f00004a},
1211 {0x0000a524, 0x2b005e40, 0x2b005e40, 0x2b005e40, 0x2b005e40, 0x2b005e40, 0x2b005e40, 0x23000244, 0x23000244},
1212 {0x0000a528, 0x2f005e42, 0x2f005e42, 0x2f005e42, 0x2f005e42, 0x2f005e42, 0x2f005e42, 0x2700022b, 0x2700022b},
1213 {0x0000a52c, 0x33005e44, 0x33005e44, 0x33005e44, 0x33005e44, 0x33005e44, 0x33005e44, 0x2b000625, 0x2b000625},
1214 {0x0000a530, 0x38005e65, 0x38005e65, 0x38005e65, 0x38005e65, 0x38005e65, 0x38005e65, 0x2f001006, 0x2f001006},
1215 {0x0000a534, 0x3c005e69, 0x3c005e69, 0x3c005e69, 0x3c005e69, 0x3c005e69, 0x3c005e69, 0x330008a0, 0x330008a0},
1216 {0x0000a538, 0x40005e6b, 0x40005e6b, 0x40005e6b, 0x40005e6b, 0x40005e6b, 0x40005e6b, 0x37000a2a, 0x37000a2a},
1217 {0x0000a53c, 0x44005e6d, 0x44005e6d, 0x44005e6d, 0x44005e6d, 0x44005e6d, 0x44005e6d, 0x3b001c23, 0x3b001c23},
1218 {0x0000a540, 0x49005e72, 0x49005e72, 0x49005e72, 0x49005e72, 0x49005e72, 0x49005e72, 0x3f0014a0, 0x3f0014a0},
1219 {0x0000a544, 0x4e005eb2, 0x4e005eb2, 0x4e005eb2, 0x4e005eb2, 0x4e005eb2, 0x4e005eb2, 0x43001882, 0x43001882},
1220 {0x0000a548, 0x53005f12, 0x53005f12, 0x53005f12, 0x53005f12, 0x53005f12, 0x53005f12, 0x47001ca2, 0x47001ca2},
1221 {0x0000a54c, 0x59025eb2, 0x59025eb2, 0x59025eb2, 0x59025eb2, 0x59025eb2, 0x59025eb2, 0x4b001ec3, 0x4b001ec3},
1222 {0x0000a550, 0x5e025f12, 0x5e025f12, 0x5e025f12, 0x5e025f12, 0x5e025f12, 0x5e025f12, 0x4f00148c, 0x4f00148c},
1223 {0x0000a554, 0x61027f12, 0x61027f12, 0x61027f12, 0x61027f12, 0x61027f12, 0x61027f12, 0x53001c6e, 0x53001c6e},
1224 {0x0000a558, 0x6702bf12, 0x6702bf12, 0x6702bf12, 0x6702bf12, 0x6702bf12, 0x6702bf12, 0x57001c92, 0x57001c92},
1225 {0x0000a55c, 0x6b02bf14, 0x6b02bf14, 0x6b02bf14, 0x6b02bf14, 0x6b02bf14, 0x6b02bf14, 0x5c001af6, 0x5c001af6},
1226 {0x0000a560, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x5c001af6, 0x5c001af6},
1227 {0x0000a564, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x5c001af6, 0x5c001af6},
1228 {0x0000a568, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x5c001af6, 0x5c001af6},
1229 {0x0000a56c, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x5c001af6, 0x5c001af6},
1230 {0x0000a570, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x5c001af6, 0x5c001af6},
1231 {0x0000a574, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x5c001af6, 0x5c001af6},
1232 {0x0000a578, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x5c001af6, 0x5c001af6},
1233 {0x0000a57c, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x6f02bf16, 0x5c001af6, 0x5c001af6},
1234 {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1235 {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1236 {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1237 {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1238 {0x0000a610, 0x00804000, 0x00804000, 0x00804000, 0x00804000, 0x00804000, 0x00804000, 0x04005001, 0x04005001},
1239 {0x0000a614, 0x00804201, 0x00804201, 0x00804201, 0x00804201, 0x00804201, 0x00804201, 0x03808e02, 0x03808e02},
1240 {0x0000a618, 0x0280c802, 0x0280c802, 0x0280c802, 0x0280c802, 0x0280c802, 0x0280c802, 0x0300c000, 0x0300c000},
1241 {0x0000a61c, 0x0280ca03, 0x0280ca03, 0x0280ca03, 0x0280ca03, 0x0280ca03, 0x0280ca03, 0x03808e02, 0x03808e02},
1242 {0x0000a620, 0x04c15104, 0x04c15104, 0x04c15104, 0x04c15104, 0x04c15104, 0x04c15104, 0x03410c03, 0x03410c03},
1243 {0x0000a624, 0x04c15305, 0x04c15305, 0x04c15305, 0x04c15305, 0x04c15305, 0x04c15305, 0x04014c03, 0x04014c03},
1244 {0x0000a628, 0x04c15305, 0x04c15305, 0x04c15305, 0x04c15305, 0x04c15305, 0x04c15305, 0x05818d04, 0x05818d04},
1245 {0x0000a62c, 0x04c15305, 0x04c15305, 0x04c15305, 0x04c15305, 0x04c15305, 0x04c15305, 0x0801cd04, 0x0801cd04},
1246 {0x0000a630, 0x04c15305, 0x04c15305, 0x04c15305, 0x04c15305, 0x04c15305, 0x04c15305, 0x0801e007, 0x0801e007},
1247 {0x0000a634, 0x04c15305, 0x04c15305, 0x04c15305, 0x04c15305, 0x04c15305, 0x04c15305, 0x0801e007, 0x0801e007},
1248 {0x0000a638, 0x04c15305, 0x04c15305, 0x04c15305, 0x04c15305, 0x04c15305, 0x04c15305, 0x0801e007, 0x0801e007},
1249 {0x0000a63c, 0x04c15305, 0x04c15305, 0x04c15305, 0x04c15305, 0x04c15305, 0x04c15305, 0x0801e007, 0x0801e007},
1250 {0x0000b2dc, 0x01feee00, 0x01feee00, 0x01feee00, 0x01feee00, 0x01feee00, 0x01feee00, 0xfffe5aaa, 0xfffe5aaa},
1251 {0x0000b2e0, 0x0000f000, 0x0000f000, 0x0000f000, 0x0000f000, 0x0000f000, 0x0000f000, 0xfffe9ccc, 0xfffe9ccc},
1252 {0x0000b2e4, 0x01ff0000, 0x01ff0000, 0x01ff0000, 0x01ff0000, 0x01ff0000, 0x01ff0000, 0xffffe0f0, 0xffffe0f0},
1253 {0x0000b2e8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffffef00, 0xffffef00},
1254 {0x0000c2dc, 0x01feee00, 0x01feee00, 0x01feee00, 0x01feee00, 0x01feee00, 0x01feee00, 0xfffe5aaa, 0xfffe5aaa},
1255 {0x0000c2e0, 0x0000f000, 0x0000f000, 0x0000f000, 0x0000f000, 0x0000f000, 0x0000f000, 0xfffe9ccc, 0xfffe9ccc},
1256 {0x0000c2e4, 0x01ff0000, 0x01ff0000, 0x01ff0000, 0x01ff0000, 0x01ff0000, 0x01ff0000, 0xffffe0f0, 0xffffe0f0},
1257 {0x0000c2e8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffffef00, 0xffffef00},
1258 {0x00016044, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x054922d4, 0x054922d4},
1259 {0x00016048, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401},
1260 {0x00016444, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x054922d4, 0x054922d4},
1261 {0x00016448, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401},
1262 {0x00016844, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x056db2d4, 0x054922d4, 0x054922d4},
1263 {0x00016848, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401, 0x66482401},
1264};
1265
1266static const u32 ar955x_1p0_soc_postamble[][5] = {
1267 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
1268 {0x00007010, 0x00000023, 0x00000023, 0x00000023, 0x00000023},
1269};
1270
1271static const u32 ar955x_1p0_modes_fast_clock[][3] = {
1272 /* Addr 5G_HT20 5G_HT40 */
1273 {0x00001030, 0x00000268, 0x000004d0},
1274 {0x00001070, 0x0000018c, 0x00000318},
1275 {0x000010b0, 0x00000fd0, 0x00001fa0},
1276 {0x00008014, 0x044c044c, 0x08980898},
1277 {0x0000801c, 0x148ec02b, 0x148ec057},
1278 {0x00008318, 0x000044c0, 0x00008980},
1279 {0x00009e00, 0x0372131c, 0x0372131c},
1280 {0x0000a230, 0x0000000b, 0x00000016},
1281 {0x0000a254, 0x00000898, 0x00001130},
1282};
1283
1284#endif /* INITVALS_955X_1P0_H */
diff --git a/drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h b/drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h
index 06b3f0df9fad..6e1915aee712 100644
--- a/drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h
@@ -1,5 +1,6 @@
1/* 1/*
2 * Copyright (c) 2010 Atheros Communications Inc. 2 * Copyright (c) 2010-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2012 Qualcomm Atheros Inc.
3 * 4 *
4 * Permission to use, copy, modify, and/or distribute this software for any 5 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above 6 * purpose with or without fee is hereby granted, provided that the above
@@ -19,18 +20,7 @@
19 20
20/* AR9580 1.0 */ 21/* AR9580 1.0 */
21 22
22static const u32 ar9580_1p0_modes_fast_clock[][3] = { 23#define ar9580_1p0_modes_fast_clock ar9300Modes_fast_clock_2p2
23 /* Addr 5G_HT20 5G_HT40 */
24 {0x00001030, 0x00000268, 0x000004d0},
25 {0x00001070, 0x0000018c, 0x00000318},
26 {0x000010b0, 0x00000fd0, 0x00001fa0},
27 {0x00008014, 0x044c044c, 0x08980898},
28 {0x0000801c, 0x148ec02b, 0x148ec057},
29 {0x00008318, 0x000044c0, 0x00008980},
30 {0x00009e00, 0x0372131c, 0x0372131c},
31 {0x0000a230, 0x0000000b, 0x00000016},
32 {0x0000a254, 0x00000898, 0x00001130},
33};
34 24
35static const u32 ar9580_1p0_radio_postamble[][5] = { 25static const u32 ar9580_1p0_radio_postamble[][5] = {
36 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 26 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
@@ -208,17 +198,7 @@ static const u32 ar9580_1p0_baseband_core[][2] = {
208 {0x0000c420, 0x00000000}, 198 {0x0000c420, 0x00000000},
209}; 199};
210 200
211static const u32 ar9580_1p0_mac_postamble[][5] = { 201#define ar9580_1p0_mac_postamble ar9300_2p2_mac_postamble
212 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
213 {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
214 {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
215 {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
216 {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
217 {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
218 {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
219 {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
220 {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
221};
222 202
223static const u32 ar9580_1p0_low_ob_db_tx_gain_table[][5] = { 203static const u32 ar9580_1p0_low_ob_db_tx_gain_table[][5] = {
224 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 204 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
@@ -326,111 +306,7 @@ static const u32 ar9580_1p0_low_ob_db_tx_gain_table[][5] = {
326 {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c}, 306 {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
327}; 307};
328 308
329static const u32 ar9580_1p0_high_power_tx_gain_table[][5] = { 309#define ar9580_1p0_high_power_tx_gain_table ar9580_1p0_low_ob_db_tx_gain_table
330 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
331 {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
332 {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
333 {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
334 {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
335 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
336 {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
337 {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
338 {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
339 {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
340 {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
341 {0x0000a514, 0x1c000223, 0x1c000223, 0x12000400, 0x12000400},
342 {0x0000a518, 0x21002220, 0x21002220, 0x16000402, 0x16000402},
343 {0x0000a51c, 0x27002223, 0x27002223, 0x19000404, 0x19000404},
344 {0x0000a520, 0x2b022220, 0x2b022220, 0x1c000603, 0x1c000603},
345 {0x0000a524, 0x2f022222, 0x2f022222, 0x21000a02, 0x21000a02},
346 {0x0000a528, 0x34022225, 0x34022225, 0x25000a04, 0x25000a04},
347 {0x0000a52c, 0x3a02222a, 0x3a02222a, 0x28000a20, 0x28000a20},
348 {0x0000a530, 0x3e02222c, 0x3e02222c, 0x2c000e20, 0x2c000e20},
349 {0x0000a534, 0x4202242a, 0x4202242a, 0x30000e22, 0x30000e22},
350 {0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24},
351 {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640},
352 {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660},
353 {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861},
354 {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81},
355 {0x0000a54c, 0x5c02486b, 0x5c02486b, 0x47001a83, 0x47001a83},
356 {0x0000a550, 0x61024a6c, 0x61024a6c, 0x4a001c84, 0x4a001c84},
357 {0x0000a554, 0x66026a6c, 0x66026a6c, 0x4e001ce3, 0x4e001ce3},
358 {0x0000a558, 0x6b026e6c, 0x6b026e6c, 0x52001ce5, 0x52001ce5},
359 {0x0000a55c, 0x7002708c, 0x7002708c, 0x56001ce9, 0x56001ce9},
360 {0x0000a560, 0x7302b08a, 0x7302b08a, 0x5a001ceb, 0x5a001ceb},
361 {0x0000a564, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
362 {0x0000a568, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
363 {0x0000a56c, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
364 {0x0000a570, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
365 {0x0000a574, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
366 {0x0000a578, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
367 {0x0000a57c, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
368 {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
369 {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002},
370 {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004},
371 {0x0000a58c, 0x10800023, 0x10800023, 0x0b800200, 0x0b800200},
372 {0x0000a590, 0x16800220, 0x16800220, 0x0f800202, 0x0f800202},
373 {0x0000a594, 0x1c800223, 0x1c800223, 0x12800400, 0x12800400},
374 {0x0000a598, 0x21802220, 0x21802220, 0x16800402, 0x16800402},
375 {0x0000a59c, 0x27802223, 0x27802223, 0x19800404, 0x19800404},
376 {0x0000a5a0, 0x2b822220, 0x2b822220, 0x1c800603, 0x1c800603},
377 {0x0000a5a4, 0x2f822222, 0x2f822222, 0x21800a02, 0x21800a02},
378 {0x0000a5a8, 0x34822225, 0x34822225, 0x25800a04, 0x25800a04},
379 {0x0000a5ac, 0x3a82222a, 0x3a82222a, 0x28800a20, 0x28800a20},
380 {0x0000a5b0, 0x3e82222c, 0x3e82222c, 0x2c800e20, 0x2c800e20},
381 {0x0000a5b4, 0x4282242a, 0x4282242a, 0x30800e22, 0x30800e22},
382 {0x0000a5b8, 0x4782244a, 0x4782244a, 0x34800e24, 0x34800e24},
383 {0x0000a5bc, 0x4b82244c, 0x4b82244c, 0x38801640, 0x38801640},
384 {0x0000a5c0, 0x4e82246c, 0x4e82246c, 0x3c801660, 0x3c801660},
385 {0x0000a5c4, 0x5382266c, 0x5382266c, 0x3f801861, 0x3f801861},
386 {0x0000a5c8, 0x5782286c, 0x5782286c, 0x43801a81, 0x43801a81},
387 {0x0000a5cc, 0x5c82486b, 0x5c82486b, 0x47801a83, 0x47801a83},
388 {0x0000a5d0, 0x61824a6c, 0x61824a6c, 0x4a801c84, 0x4a801c84},
389 {0x0000a5d4, 0x66826a6c, 0x66826a6c, 0x4e801ce3, 0x4e801ce3},
390 {0x0000a5d8, 0x6b826e6c, 0x6b826e6c, 0x52801ce5, 0x52801ce5},
391 {0x0000a5dc, 0x7082708c, 0x7082708c, 0x56801ce9, 0x56801ce9},
392 {0x0000a5e0, 0x7382b08a, 0x7382b08a, 0x5a801ceb, 0x5a801ceb},
393 {0x0000a5e4, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
394 {0x0000a5e8, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
395 {0x0000a5ec, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
396 {0x0000a5f0, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
397 {0x0000a5f4, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
398 {0x0000a5f8, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
399 {0x0000a5fc, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
400 {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
401 {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
402 {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
403 {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
404 {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
405 {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
406 {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501},
407 {0x0000a61c, 0x02008802, 0x02008802, 0x02008501, 0x02008501},
408 {0x0000a620, 0x0300cc03, 0x0300cc03, 0x0280ca03, 0x0280ca03},
409 {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04},
410 {0x0000a628, 0x0300cc03, 0x0300cc03, 0x04014c04, 0x04014c04},
411 {0x0000a62c, 0x03810c03, 0x03810c03, 0x04015005, 0x04015005},
412 {0x0000a630, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
413 {0x0000a634, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
414 {0x0000a638, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
415 {0x0000a63c, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
416 {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
417 {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
418 {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
419 {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
420 {0x0000c2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
421 {0x0000c2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
422 {0x0000c2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
423 {0x0000c2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
424 {0x00016044, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
425 {0x00016048, 0x66480001, 0x66480001, 0x66480001, 0x66480001},
426 {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
427 {0x00016444, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
428 {0x00016448, 0x66480001, 0x66480001, 0x66480001, 0x66480001},
429 {0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
430 {0x00016844, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
431 {0x00016848, 0x66480001, 0x66480001, 0x66480001, 0x66480001},
432 {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
433};
434 310
435static const u32 ar9580_1p0_lowest_ob_db_tx_gain_table[][5] = { 311static const u32 ar9580_1p0_lowest_ob_db_tx_gain_table[][5] = {
436 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 312 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
@@ -538,12 +414,7 @@ static const u32 ar9580_1p0_lowest_ob_db_tx_gain_table[][5] = {
538 {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c}, 414 {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
539}; 415};
540 416
541static const u32 ar9580_1p0_baseband_core_txfir_coeff_japan_2484[][2] = { 417#define ar9580_1p0_baseband_core_txfir_coeff_japan_2484 ar9462_2p0_baseband_core_txfir_coeff_japan_2484
542 /* Addr allmodes */
543 {0x0000a398, 0x00000000},
544 {0x0000a39c, 0x6f7f0301},
545 {0x0000a3a0, 0xca9228ee},
546};
547 418
548static const u32 ar9580_1p0_mac_core[][2] = { 419static const u32 ar9580_1p0_mac_core[][2] = {
549 /* Addr allmodes */ 420 /* Addr allmodes */
@@ -808,376 +679,11 @@ static const u32 ar9580_1p0_mixed_ob_db_tx_gain_table[][5] = {
808 {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c}, 679 {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
809}; 680};
810 681
811static const u32 ar9580_1p0_wo_xlna_rx_gain_table[][2] = { 682#define ar9580_1p0_wo_xlna_rx_gain_table ar9300Common_wo_xlna_rx_gain_table_2p2
812 /* Addr allmodes */
813 {0x0000a000, 0x00010000},
814 {0x0000a004, 0x00030002},
815 {0x0000a008, 0x00050004},
816 {0x0000a00c, 0x00810080},
817 {0x0000a010, 0x00830082},
818 {0x0000a014, 0x01810180},
819 {0x0000a018, 0x01830182},
820 {0x0000a01c, 0x01850184},
821 {0x0000a020, 0x01890188},
822 {0x0000a024, 0x018b018a},
823 {0x0000a028, 0x018d018c},
824 {0x0000a02c, 0x03820190},
825 {0x0000a030, 0x03840383},
826 {0x0000a034, 0x03880385},
827 {0x0000a038, 0x038a0389},
828 {0x0000a03c, 0x038c038b},
829 {0x0000a040, 0x0390038d},
830 {0x0000a044, 0x03920391},
831 {0x0000a048, 0x03940393},
832 {0x0000a04c, 0x03960395},
833 {0x0000a050, 0x00000000},
834 {0x0000a054, 0x00000000},
835 {0x0000a058, 0x00000000},
836 {0x0000a05c, 0x00000000},
837 {0x0000a060, 0x00000000},
838 {0x0000a064, 0x00000000},
839 {0x0000a068, 0x00000000},
840 {0x0000a06c, 0x00000000},
841 {0x0000a070, 0x00000000},
842 {0x0000a074, 0x00000000},
843 {0x0000a078, 0x00000000},
844 {0x0000a07c, 0x00000000},
845 {0x0000a080, 0x29292929},
846 {0x0000a084, 0x29292929},
847 {0x0000a088, 0x29292929},
848 {0x0000a08c, 0x29292929},
849 {0x0000a090, 0x22292929},
850 {0x0000a094, 0x1d1d2222},
851 {0x0000a098, 0x0c111117},
852 {0x0000a09c, 0x00030303},
853 {0x0000a0a0, 0x00000000},
854 {0x0000a0a4, 0x00000000},
855 {0x0000a0a8, 0x00000000},
856 {0x0000a0ac, 0x00000000},
857 {0x0000a0b0, 0x00000000},
858 {0x0000a0b4, 0x00000000},
859 {0x0000a0b8, 0x00000000},
860 {0x0000a0bc, 0x00000000},
861 {0x0000a0c0, 0x001f0000},
862 {0x0000a0c4, 0x01000101},
863 {0x0000a0c8, 0x011e011f},
864 {0x0000a0cc, 0x011c011d},
865 {0x0000a0d0, 0x02030204},
866 {0x0000a0d4, 0x02010202},
867 {0x0000a0d8, 0x021f0200},
868 {0x0000a0dc, 0x0302021e},
869 {0x0000a0e0, 0x03000301},
870 {0x0000a0e4, 0x031e031f},
871 {0x0000a0e8, 0x0402031d},
872 {0x0000a0ec, 0x04000401},
873 {0x0000a0f0, 0x041e041f},
874 {0x0000a0f4, 0x0502041d},
875 {0x0000a0f8, 0x05000501},
876 {0x0000a0fc, 0x051e051f},
877 {0x0000a100, 0x06010602},
878 {0x0000a104, 0x061f0600},
879 {0x0000a108, 0x061d061e},
880 {0x0000a10c, 0x07020703},
881 {0x0000a110, 0x07000701},
882 {0x0000a114, 0x00000000},
883 {0x0000a118, 0x00000000},
884 {0x0000a11c, 0x00000000},
885 {0x0000a120, 0x00000000},
886 {0x0000a124, 0x00000000},
887 {0x0000a128, 0x00000000},
888 {0x0000a12c, 0x00000000},
889 {0x0000a130, 0x00000000},
890 {0x0000a134, 0x00000000},
891 {0x0000a138, 0x00000000},
892 {0x0000a13c, 0x00000000},
893 {0x0000a140, 0x001f0000},
894 {0x0000a144, 0x01000101},
895 {0x0000a148, 0x011e011f},
896 {0x0000a14c, 0x011c011d},
897 {0x0000a150, 0x02030204},
898 {0x0000a154, 0x02010202},
899 {0x0000a158, 0x021f0200},
900 {0x0000a15c, 0x0302021e},
901 {0x0000a160, 0x03000301},
902 {0x0000a164, 0x031e031f},
903 {0x0000a168, 0x0402031d},
904 {0x0000a16c, 0x04000401},
905 {0x0000a170, 0x041e041f},
906 {0x0000a174, 0x0502041d},
907 {0x0000a178, 0x05000501},
908 {0x0000a17c, 0x051e051f},
909 {0x0000a180, 0x06010602},
910 {0x0000a184, 0x061f0600},
911 {0x0000a188, 0x061d061e},
912 {0x0000a18c, 0x07020703},
913 {0x0000a190, 0x07000701},
914 {0x0000a194, 0x00000000},
915 {0x0000a198, 0x00000000},
916 {0x0000a19c, 0x00000000},
917 {0x0000a1a0, 0x00000000},
918 {0x0000a1a4, 0x00000000},
919 {0x0000a1a8, 0x00000000},
920 {0x0000a1ac, 0x00000000},
921 {0x0000a1b0, 0x00000000},
922 {0x0000a1b4, 0x00000000},
923 {0x0000a1b8, 0x00000000},
924 {0x0000a1bc, 0x00000000},
925 {0x0000a1c0, 0x00000000},
926 {0x0000a1c4, 0x00000000},
927 {0x0000a1c8, 0x00000000},
928 {0x0000a1cc, 0x00000000},
929 {0x0000a1d0, 0x00000000},
930 {0x0000a1d4, 0x00000000},
931 {0x0000a1d8, 0x00000000},
932 {0x0000a1dc, 0x00000000},
933 {0x0000a1e0, 0x00000000},
934 {0x0000a1e4, 0x00000000},
935 {0x0000a1e8, 0x00000000},
936 {0x0000a1ec, 0x00000000},
937 {0x0000a1f0, 0x00000396},
938 {0x0000a1f4, 0x00000396},
939 {0x0000a1f8, 0x00000396},
940 {0x0000a1fc, 0x00000196},
941 {0x0000b000, 0x00010000},
942 {0x0000b004, 0x00030002},
943 {0x0000b008, 0x00050004},
944 {0x0000b00c, 0x00810080},
945 {0x0000b010, 0x00830082},
946 {0x0000b014, 0x01810180},
947 {0x0000b018, 0x01830182},
948 {0x0000b01c, 0x01850184},
949 {0x0000b020, 0x02810280},
950 {0x0000b024, 0x02830282},
951 {0x0000b028, 0x02850284},
952 {0x0000b02c, 0x02890288},
953 {0x0000b030, 0x028b028a},
954 {0x0000b034, 0x0388028c},
955 {0x0000b038, 0x038a0389},
956 {0x0000b03c, 0x038c038b},
957 {0x0000b040, 0x0390038d},
958 {0x0000b044, 0x03920391},
959 {0x0000b048, 0x03940393},
960 {0x0000b04c, 0x03960395},
961 {0x0000b050, 0x00000000},
962 {0x0000b054, 0x00000000},
963 {0x0000b058, 0x00000000},
964 {0x0000b05c, 0x00000000},
965 {0x0000b060, 0x00000000},
966 {0x0000b064, 0x00000000},
967 {0x0000b068, 0x00000000},
968 {0x0000b06c, 0x00000000},
969 {0x0000b070, 0x00000000},
970 {0x0000b074, 0x00000000},
971 {0x0000b078, 0x00000000},
972 {0x0000b07c, 0x00000000},
973 {0x0000b080, 0x32323232},
974 {0x0000b084, 0x2f2f3232},
975 {0x0000b088, 0x23282a2d},
976 {0x0000b08c, 0x1c1e2123},
977 {0x0000b090, 0x14171919},
978 {0x0000b094, 0x0e0e1214},
979 {0x0000b098, 0x03050707},
980 {0x0000b09c, 0x00030303},
981 {0x0000b0a0, 0x00000000},
982 {0x0000b0a4, 0x00000000},
983 {0x0000b0a8, 0x00000000},
984 {0x0000b0ac, 0x00000000},
985 {0x0000b0b0, 0x00000000},
986 {0x0000b0b4, 0x00000000},
987 {0x0000b0b8, 0x00000000},
988 {0x0000b0bc, 0x00000000},
989 {0x0000b0c0, 0x003f0020},
990 {0x0000b0c4, 0x00400041},
991 {0x0000b0c8, 0x0140005f},
992 {0x0000b0cc, 0x0160015f},
993 {0x0000b0d0, 0x017e017f},
994 {0x0000b0d4, 0x02410242},
995 {0x0000b0d8, 0x025f0240},
996 {0x0000b0dc, 0x027f0260},
997 {0x0000b0e0, 0x0341027e},
998 {0x0000b0e4, 0x035f0340},
999 {0x0000b0e8, 0x037f0360},
1000 {0x0000b0ec, 0x04400441},
1001 {0x0000b0f0, 0x0460045f},
1002 {0x0000b0f4, 0x0541047f},
1003 {0x0000b0f8, 0x055f0540},
1004 {0x0000b0fc, 0x057f0560},
1005 {0x0000b100, 0x06400641},
1006 {0x0000b104, 0x0660065f},
1007 {0x0000b108, 0x067e067f},
1008 {0x0000b10c, 0x07410742},
1009 {0x0000b110, 0x075f0740},
1010 {0x0000b114, 0x077f0760},
1011 {0x0000b118, 0x07800781},
1012 {0x0000b11c, 0x07a0079f},
1013 {0x0000b120, 0x07c107bf},
1014 {0x0000b124, 0x000007c0},
1015 {0x0000b128, 0x00000000},
1016 {0x0000b12c, 0x00000000},
1017 {0x0000b130, 0x00000000},
1018 {0x0000b134, 0x00000000},
1019 {0x0000b138, 0x00000000},
1020 {0x0000b13c, 0x00000000},
1021 {0x0000b140, 0x003f0020},
1022 {0x0000b144, 0x00400041},
1023 {0x0000b148, 0x0140005f},
1024 {0x0000b14c, 0x0160015f},
1025 {0x0000b150, 0x017e017f},
1026 {0x0000b154, 0x02410242},
1027 {0x0000b158, 0x025f0240},
1028 {0x0000b15c, 0x027f0260},
1029 {0x0000b160, 0x0341027e},
1030 {0x0000b164, 0x035f0340},
1031 {0x0000b168, 0x037f0360},
1032 {0x0000b16c, 0x04400441},
1033 {0x0000b170, 0x0460045f},
1034 {0x0000b174, 0x0541047f},
1035 {0x0000b178, 0x055f0540},
1036 {0x0000b17c, 0x057f0560},
1037 {0x0000b180, 0x06400641},
1038 {0x0000b184, 0x0660065f},
1039 {0x0000b188, 0x067e067f},
1040 {0x0000b18c, 0x07410742},
1041 {0x0000b190, 0x075f0740},
1042 {0x0000b194, 0x077f0760},
1043 {0x0000b198, 0x07800781},
1044 {0x0000b19c, 0x07a0079f},
1045 {0x0000b1a0, 0x07c107bf},
1046 {0x0000b1a4, 0x000007c0},
1047 {0x0000b1a8, 0x00000000},
1048 {0x0000b1ac, 0x00000000},
1049 {0x0000b1b0, 0x00000000},
1050 {0x0000b1b4, 0x00000000},
1051 {0x0000b1b8, 0x00000000},
1052 {0x0000b1bc, 0x00000000},
1053 {0x0000b1c0, 0x00000000},
1054 {0x0000b1c4, 0x00000000},
1055 {0x0000b1c8, 0x00000000},
1056 {0x0000b1cc, 0x00000000},
1057 {0x0000b1d0, 0x00000000},
1058 {0x0000b1d4, 0x00000000},
1059 {0x0000b1d8, 0x00000000},
1060 {0x0000b1dc, 0x00000000},
1061 {0x0000b1e0, 0x00000000},
1062 {0x0000b1e4, 0x00000000},
1063 {0x0000b1e8, 0x00000000},
1064 {0x0000b1ec, 0x00000000},
1065 {0x0000b1f0, 0x00000396},
1066 {0x0000b1f4, 0x00000396},
1067 {0x0000b1f8, 0x00000396},
1068 {0x0000b1fc, 0x00000196},
1069};
1070 683
1071static const u32 ar9580_1p0_soc_postamble[][5] = { 684#define ar9580_1p0_soc_postamble ar9300_2p2_soc_postamble
1072 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
1073 {0x00007010, 0x00000023, 0x00000023, 0x00000023, 0x00000023},
1074};
1075 685
1076static const u32 ar9580_1p0_high_ob_db_tx_gain_table[][5] = { 686#define ar9580_1p0_high_ob_db_tx_gain_table ar9300Modes_high_ob_db_tx_gain_table_2p2
1077 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
1078 {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
1079 {0x0000a2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
1080 {0x0000a2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
1081 {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
1082 {0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9},
1083 {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
1084 {0x0000a504, 0x04002222, 0x04002222, 0x04000002, 0x04000002},
1085 {0x0000a508, 0x09002421, 0x09002421, 0x08000004, 0x08000004},
1086 {0x0000a50c, 0x0d002621, 0x0d002621, 0x0b000200, 0x0b000200},
1087 {0x0000a510, 0x13004620, 0x13004620, 0x0f000202, 0x0f000202},
1088 {0x0000a514, 0x19004a20, 0x19004a20, 0x11000400, 0x11000400},
1089 {0x0000a518, 0x1d004e20, 0x1d004e20, 0x15000402, 0x15000402},
1090 {0x0000a51c, 0x21005420, 0x21005420, 0x19000404, 0x19000404},
1091 {0x0000a520, 0x26005e20, 0x26005e20, 0x1b000603, 0x1b000603},
1092 {0x0000a524, 0x2b005e40, 0x2b005e40, 0x1f000a02, 0x1f000a02},
1093 {0x0000a528, 0x2f005e42, 0x2f005e42, 0x23000a04, 0x23000a04},
1094 {0x0000a52c, 0x33005e44, 0x33005e44, 0x26000a20, 0x26000a20},
1095 {0x0000a530, 0x38005e65, 0x38005e65, 0x2a000e20, 0x2a000e20},
1096 {0x0000a534, 0x3c005e69, 0x3c005e69, 0x2e000e22, 0x2e000e22},
1097 {0x0000a538, 0x40005e6b, 0x40005e6b, 0x31000e24, 0x31000e24},
1098 {0x0000a53c, 0x44005e6d, 0x44005e6d, 0x34001640, 0x34001640},
1099 {0x0000a540, 0x49005e72, 0x49005e72, 0x38001660, 0x38001660},
1100 {0x0000a544, 0x4e005eb2, 0x4e005eb2, 0x3b001861, 0x3b001861},
1101 {0x0000a548, 0x53005f12, 0x53005f12, 0x3e001a81, 0x3e001a81},
1102 {0x0000a54c, 0x59025eb2, 0x59025eb2, 0x42001a83, 0x42001a83},
1103 {0x0000a550, 0x5e025f12, 0x5e025f12, 0x44001c84, 0x44001c84},
1104 {0x0000a554, 0x61027f12, 0x61027f12, 0x48001ce3, 0x48001ce3},
1105 {0x0000a558, 0x6702bf12, 0x6702bf12, 0x4c001ce5, 0x4c001ce5},
1106 {0x0000a55c, 0x6b02bf14, 0x6b02bf14, 0x50001ce9, 0x50001ce9},
1107 {0x0000a560, 0x6f02bf16, 0x6f02bf16, 0x54001ceb, 0x54001ceb},
1108 {0x0000a564, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
1109 {0x0000a568, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
1110 {0x0000a56c, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
1111 {0x0000a570, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
1112 {0x0000a574, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
1113 {0x0000a578, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
1114 {0x0000a57c, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
1115 {0x0000a580, 0x00802220, 0x00802220, 0x00800000, 0x00800000},
1116 {0x0000a584, 0x04802222, 0x04802222, 0x04800002, 0x04800002},
1117 {0x0000a588, 0x09802421, 0x09802421, 0x08800004, 0x08800004},
1118 {0x0000a58c, 0x0d802621, 0x0d802621, 0x0b800200, 0x0b800200},
1119 {0x0000a590, 0x13804620, 0x13804620, 0x0f800202, 0x0f800202},
1120 {0x0000a594, 0x19804a20, 0x19804a20, 0x11800400, 0x11800400},
1121 {0x0000a598, 0x1d804e20, 0x1d804e20, 0x15800402, 0x15800402},
1122 {0x0000a59c, 0x21805420, 0x21805420, 0x19800404, 0x19800404},
1123 {0x0000a5a0, 0x26805e20, 0x26805e20, 0x1b800603, 0x1b800603},
1124 {0x0000a5a4, 0x2b805e40, 0x2b805e40, 0x1f800a02, 0x1f800a02},
1125 {0x0000a5a8, 0x2f805e42, 0x2f805e42, 0x23800a04, 0x23800a04},
1126 {0x0000a5ac, 0x33805e44, 0x33805e44, 0x26800a20, 0x26800a20},
1127 {0x0000a5b0, 0x38805e65, 0x38805e65, 0x2a800e20, 0x2a800e20},
1128 {0x0000a5b4, 0x3c805e69, 0x3c805e69, 0x2e800e22, 0x2e800e22},
1129 {0x0000a5b8, 0x40805e6b, 0x40805e6b, 0x31800e24, 0x31800e24},
1130 {0x0000a5bc, 0x44805e6d, 0x44805e6d, 0x34801640, 0x34801640},
1131 {0x0000a5c0, 0x49805e72, 0x49805e72, 0x38801660, 0x38801660},
1132 {0x0000a5c4, 0x4e805eb2, 0x4e805eb2, 0x3b801861, 0x3b801861},
1133 {0x0000a5c8, 0x53805f12, 0x53805f12, 0x3e801a81, 0x3e801a81},
1134 {0x0000a5cc, 0x59825eb2, 0x59825eb2, 0x42801a83, 0x42801a83},
1135 {0x0000a5d0, 0x5e825f12, 0x5e825f12, 0x44801c84, 0x44801c84},
1136 {0x0000a5d4, 0x61827f12, 0x61827f12, 0x48801ce3, 0x48801ce3},
1137 {0x0000a5d8, 0x6782bf12, 0x6782bf12, 0x4c801ce5, 0x4c801ce5},
1138 {0x0000a5dc, 0x6b82bf14, 0x6b82bf14, 0x50801ce9, 0x50801ce9},
1139 {0x0000a5e0, 0x6f82bf16, 0x6f82bf16, 0x54801ceb, 0x54801ceb},
1140 {0x0000a5e4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
1141 {0x0000a5e8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
1142 {0x0000a5ec, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
1143 {0x0000a5f0, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
1144 {0x0000a5f4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
1145 {0x0000a5f8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
1146 {0x0000a5fc, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
1147 {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1148 {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1149 {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1150 {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1151 {0x0000a610, 0x00804000, 0x00804000, 0x00000000, 0x00000000},
1152 {0x0000a614, 0x00804201, 0x00804201, 0x01404000, 0x01404000},
1153 {0x0000a618, 0x0280c802, 0x0280c802, 0x01404501, 0x01404501},
1154 {0x0000a61c, 0x0280ca03, 0x0280ca03, 0x02008501, 0x02008501},
1155 {0x0000a620, 0x04c15104, 0x04c15104, 0x0280ca03, 0x0280ca03},
1156 {0x0000a624, 0x04c15305, 0x04c15305, 0x03010c04, 0x03010c04},
1157 {0x0000a628, 0x04c15305, 0x04c15305, 0x04014c04, 0x04014c04},
1158 {0x0000a62c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
1159 {0x0000a630, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
1160 {0x0000a634, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
1161 {0x0000a638, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
1162 {0x0000a63c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
1163 {0x0000b2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
1164 {0x0000b2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
1165 {0x0000b2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
1166 {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
1167 {0x0000c2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
1168 {0x0000c2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
1169 {0x0000c2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
1170 {0x0000c2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
1171 {0x00016044, 0x056db2e4, 0x056db2e4, 0x056db2e4, 0x056db2e4},
1172 {0x00016048, 0x8e480001, 0x8e480001, 0x8e480001, 0x8e480001},
1173 {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
1174 {0x00016444, 0x056db2e4, 0x056db2e4, 0x056db2e4, 0x056db2e4},
1175 {0x00016448, 0x8e480001, 0x8e480001, 0x8e480001, 0x8e480001},
1176 {0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
1177 {0x00016844, 0x056db2e4, 0x056db2e4, 0x056db2e4, 0x056db2e4},
1178 {0x00016848, 0x8e480001, 0x8e480001, 0x8e480001, 0x8e480001},
1179 {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
1180};
1181 687
1182static const u32 ar9580_1p0_soc_preamble[][2] = { 688static const u32 ar9580_1p0_soc_preamble[][2] = {
1183 /* Addr allmodes */ 689 /* Addr allmodes */
@@ -1189,265 +695,7 @@ static const u32 ar9580_1p0_soc_preamble[][2] = {
1189 {0x00007048, 0x00000008}, 695 {0x00007048, 0x00000008},
1190}; 696};
1191 697
1192static const u32 ar9580_1p0_rx_gain_table[][2] = { 698#define ar9580_1p0_rx_gain_table ar9462_common_rx_gain_table_2p0
1193 /* Addr allmodes */
1194 {0x0000a000, 0x00010000},
1195 {0x0000a004, 0x00030002},
1196 {0x0000a008, 0x00050004},
1197 {0x0000a00c, 0x00810080},
1198 {0x0000a010, 0x00830082},
1199 {0x0000a014, 0x01810180},
1200 {0x0000a018, 0x01830182},
1201 {0x0000a01c, 0x01850184},
1202 {0x0000a020, 0x01890188},
1203 {0x0000a024, 0x018b018a},
1204 {0x0000a028, 0x018d018c},
1205 {0x0000a02c, 0x01910190},
1206 {0x0000a030, 0x01930192},
1207 {0x0000a034, 0x01950194},
1208 {0x0000a038, 0x038a0196},
1209 {0x0000a03c, 0x038c038b},
1210 {0x0000a040, 0x0390038d},
1211 {0x0000a044, 0x03920391},
1212 {0x0000a048, 0x03940393},
1213 {0x0000a04c, 0x03960395},
1214 {0x0000a050, 0x00000000},
1215 {0x0000a054, 0x00000000},
1216 {0x0000a058, 0x00000000},
1217 {0x0000a05c, 0x00000000},
1218 {0x0000a060, 0x00000000},
1219 {0x0000a064, 0x00000000},
1220 {0x0000a068, 0x00000000},
1221 {0x0000a06c, 0x00000000},
1222 {0x0000a070, 0x00000000},
1223 {0x0000a074, 0x00000000},
1224 {0x0000a078, 0x00000000},
1225 {0x0000a07c, 0x00000000},
1226 {0x0000a080, 0x22222229},
1227 {0x0000a084, 0x1d1d1d1d},
1228 {0x0000a088, 0x1d1d1d1d},
1229 {0x0000a08c, 0x1d1d1d1d},
1230 {0x0000a090, 0x171d1d1d},
1231 {0x0000a094, 0x11111717},
1232 {0x0000a098, 0x00030311},
1233 {0x0000a09c, 0x00000000},
1234 {0x0000a0a0, 0x00000000},
1235 {0x0000a0a4, 0x00000000},
1236 {0x0000a0a8, 0x00000000},
1237 {0x0000a0ac, 0x00000000},
1238 {0x0000a0b0, 0x00000000},
1239 {0x0000a0b4, 0x00000000},
1240 {0x0000a0b8, 0x00000000},
1241 {0x0000a0bc, 0x00000000},
1242 {0x0000a0c0, 0x001f0000},
1243 {0x0000a0c4, 0x01000101},
1244 {0x0000a0c8, 0x011e011f},
1245 {0x0000a0cc, 0x011c011d},
1246 {0x0000a0d0, 0x02030204},
1247 {0x0000a0d4, 0x02010202},
1248 {0x0000a0d8, 0x021f0200},
1249 {0x0000a0dc, 0x0302021e},
1250 {0x0000a0e0, 0x03000301},
1251 {0x0000a0e4, 0x031e031f},
1252 {0x0000a0e8, 0x0402031d},
1253 {0x0000a0ec, 0x04000401},
1254 {0x0000a0f0, 0x041e041f},
1255 {0x0000a0f4, 0x0502041d},
1256 {0x0000a0f8, 0x05000501},
1257 {0x0000a0fc, 0x051e051f},
1258 {0x0000a100, 0x06010602},
1259 {0x0000a104, 0x061f0600},
1260 {0x0000a108, 0x061d061e},
1261 {0x0000a10c, 0x07020703},
1262 {0x0000a110, 0x07000701},
1263 {0x0000a114, 0x00000000},
1264 {0x0000a118, 0x00000000},
1265 {0x0000a11c, 0x00000000},
1266 {0x0000a120, 0x00000000},
1267 {0x0000a124, 0x00000000},
1268 {0x0000a128, 0x00000000},
1269 {0x0000a12c, 0x00000000},
1270 {0x0000a130, 0x00000000},
1271 {0x0000a134, 0x00000000},
1272 {0x0000a138, 0x00000000},
1273 {0x0000a13c, 0x00000000},
1274 {0x0000a140, 0x001f0000},
1275 {0x0000a144, 0x01000101},
1276 {0x0000a148, 0x011e011f},
1277 {0x0000a14c, 0x011c011d},
1278 {0x0000a150, 0x02030204},
1279 {0x0000a154, 0x02010202},
1280 {0x0000a158, 0x021f0200},
1281 {0x0000a15c, 0x0302021e},
1282 {0x0000a160, 0x03000301},
1283 {0x0000a164, 0x031e031f},
1284 {0x0000a168, 0x0402031d},
1285 {0x0000a16c, 0x04000401},
1286 {0x0000a170, 0x041e041f},
1287 {0x0000a174, 0x0502041d},
1288 {0x0000a178, 0x05000501},
1289 {0x0000a17c, 0x051e051f},
1290 {0x0000a180, 0x06010602},
1291 {0x0000a184, 0x061f0600},
1292 {0x0000a188, 0x061d061e},
1293 {0x0000a18c, 0x07020703},
1294 {0x0000a190, 0x07000701},
1295 {0x0000a194, 0x00000000},
1296 {0x0000a198, 0x00000000},
1297 {0x0000a19c, 0x00000000},
1298 {0x0000a1a0, 0x00000000},
1299 {0x0000a1a4, 0x00000000},
1300 {0x0000a1a8, 0x00000000},
1301 {0x0000a1ac, 0x00000000},
1302 {0x0000a1b0, 0x00000000},
1303 {0x0000a1b4, 0x00000000},
1304 {0x0000a1b8, 0x00000000},
1305 {0x0000a1bc, 0x00000000},
1306 {0x0000a1c0, 0x00000000},
1307 {0x0000a1c4, 0x00000000},
1308 {0x0000a1c8, 0x00000000},
1309 {0x0000a1cc, 0x00000000},
1310 {0x0000a1d0, 0x00000000},
1311 {0x0000a1d4, 0x00000000},
1312 {0x0000a1d8, 0x00000000},
1313 {0x0000a1dc, 0x00000000},
1314 {0x0000a1e0, 0x00000000},
1315 {0x0000a1e4, 0x00000000},
1316 {0x0000a1e8, 0x00000000},
1317 {0x0000a1ec, 0x00000000},
1318 {0x0000a1f0, 0x00000396},
1319 {0x0000a1f4, 0x00000396},
1320 {0x0000a1f8, 0x00000396},
1321 {0x0000a1fc, 0x00000196},
1322 {0x0000b000, 0x00010000},
1323 {0x0000b004, 0x00030002},
1324 {0x0000b008, 0x00050004},
1325 {0x0000b00c, 0x00810080},
1326 {0x0000b010, 0x00830082},
1327 {0x0000b014, 0x01810180},
1328 {0x0000b018, 0x01830182},
1329 {0x0000b01c, 0x01850184},
1330 {0x0000b020, 0x02810280},
1331 {0x0000b024, 0x02830282},
1332 {0x0000b028, 0x02850284},
1333 {0x0000b02c, 0x02890288},
1334 {0x0000b030, 0x028b028a},
1335 {0x0000b034, 0x0388028c},
1336 {0x0000b038, 0x038a0389},
1337 {0x0000b03c, 0x038c038b},
1338 {0x0000b040, 0x0390038d},
1339 {0x0000b044, 0x03920391},
1340 {0x0000b048, 0x03940393},
1341 {0x0000b04c, 0x03960395},
1342 {0x0000b050, 0x00000000},
1343 {0x0000b054, 0x00000000},
1344 {0x0000b058, 0x00000000},
1345 {0x0000b05c, 0x00000000},
1346 {0x0000b060, 0x00000000},
1347 {0x0000b064, 0x00000000},
1348 {0x0000b068, 0x00000000},
1349 {0x0000b06c, 0x00000000},
1350 {0x0000b070, 0x00000000},
1351 {0x0000b074, 0x00000000},
1352 {0x0000b078, 0x00000000},
1353 {0x0000b07c, 0x00000000},
1354 {0x0000b080, 0x2a2d2f32},
1355 {0x0000b084, 0x21232328},
1356 {0x0000b088, 0x19191c1e},
1357 {0x0000b08c, 0x12141417},
1358 {0x0000b090, 0x07070e0e},
1359 {0x0000b094, 0x03030305},
1360 {0x0000b098, 0x00000003},
1361 {0x0000b09c, 0x00000000},
1362 {0x0000b0a0, 0x00000000},
1363 {0x0000b0a4, 0x00000000},
1364 {0x0000b0a8, 0x00000000},
1365 {0x0000b0ac, 0x00000000},
1366 {0x0000b0b0, 0x00000000},
1367 {0x0000b0b4, 0x00000000},
1368 {0x0000b0b8, 0x00000000},
1369 {0x0000b0bc, 0x00000000},
1370 {0x0000b0c0, 0x003f0020},
1371 {0x0000b0c4, 0x00400041},
1372 {0x0000b0c8, 0x0140005f},
1373 {0x0000b0cc, 0x0160015f},
1374 {0x0000b0d0, 0x017e017f},
1375 {0x0000b0d4, 0x02410242},
1376 {0x0000b0d8, 0x025f0240},
1377 {0x0000b0dc, 0x027f0260},
1378 {0x0000b0e0, 0x0341027e},
1379 {0x0000b0e4, 0x035f0340},
1380 {0x0000b0e8, 0x037f0360},
1381 {0x0000b0ec, 0x04400441},
1382 {0x0000b0f0, 0x0460045f},
1383 {0x0000b0f4, 0x0541047f},
1384 {0x0000b0f8, 0x055f0540},
1385 {0x0000b0fc, 0x057f0560},
1386 {0x0000b100, 0x06400641},
1387 {0x0000b104, 0x0660065f},
1388 {0x0000b108, 0x067e067f},
1389 {0x0000b10c, 0x07410742},
1390 {0x0000b110, 0x075f0740},
1391 {0x0000b114, 0x077f0760},
1392 {0x0000b118, 0x07800781},
1393 {0x0000b11c, 0x07a0079f},
1394 {0x0000b120, 0x07c107bf},
1395 {0x0000b124, 0x000007c0},
1396 {0x0000b128, 0x00000000},
1397 {0x0000b12c, 0x00000000},
1398 {0x0000b130, 0x00000000},
1399 {0x0000b134, 0x00000000},
1400 {0x0000b138, 0x00000000},
1401 {0x0000b13c, 0x00000000},
1402 {0x0000b140, 0x003f0020},
1403 {0x0000b144, 0x00400041},
1404 {0x0000b148, 0x0140005f},
1405 {0x0000b14c, 0x0160015f},
1406 {0x0000b150, 0x017e017f},
1407 {0x0000b154, 0x02410242},
1408 {0x0000b158, 0x025f0240},
1409 {0x0000b15c, 0x027f0260},
1410 {0x0000b160, 0x0341027e},
1411 {0x0000b164, 0x035f0340},
1412 {0x0000b168, 0x037f0360},
1413 {0x0000b16c, 0x04400441},
1414 {0x0000b170, 0x0460045f},
1415 {0x0000b174, 0x0541047f},
1416 {0x0000b178, 0x055f0540},
1417 {0x0000b17c, 0x057f0560},
1418 {0x0000b180, 0x06400641},
1419 {0x0000b184, 0x0660065f},
1420 {0x0000b188, 0x067e067f},
1421 {0x0000b18c, 0x07410742},
1422 {0x0000b190, 0x075f0740},
1423 {0x0000b194, 0x077f0760},
1424 {0x0000b198, 0x07800781},
1425 {0x0000b19c, 0x07a0079f},
1426 {0x0000b1a0, 0x07c107bf},
1427 {0x0000b1a4, 0x000007c0},
1428 {0x0000b1a8, 0x00000000},
1429 {0x0000b1ac, 0x00000000},
1430 {0x0000b1b0, 0x00000000},
1431 {0x0000b1b4, 0x00000000},
1432 {0x0000b1b8, 0x00000000},
1433 {0x0000b1bc, 0x00000000},
1434 {0x0000b1c0, 0x00000000},
1435 {0x0000b1c4, 0x00000000},
1436 {0x0000b1c8, 0x00000000},
1437 {0x0000b1cc, 0x00000000},
1438 {0x0000b1d0, 0x00000000},
1439 {0x0000b1d4, 0x00000000},
1440 {0x0000b1d8, 0x00000000},
1441 {0x0000b1dc, 0x00000000},
1442 {0x0000b1e0, 0x00000000},
1443 {0x0000b1e4, 0x00000000},
1444 {0x0000b1e8, 0x00000000},
1445 {0x0000b1ec, 0x00000000},
1446 {0x0000b1f0, 0x00000396},
1447 {0x0000b1f4, 0x00000396},
1448 {0x0000b1f8, 0x00000396},
1449 {0x0000b1fc, 0x00000196},
1450};
1451 699
1452static const u32 ar9580_1p0_radio_core[][2] = { 700static const u32 ar9580_1p0_radio_core[][2] = {
1453 /* Addr allmodes */ 701 /* Addr allmodes */
diff --git a/drivers/net/wireless/ath/ath9k/ath9k.h b/drivers/net/wireless/ath/ath9k/ath9k.h
index 4866550ddd96..79840d6deef2 100644
--- a/drivers/net/wireless/ath/ath9k/ath9k.h
+++ b/drivers/net/wireless/ath/ath9k/ath9k.h
@@ -308,6 +308,7 @@ struct ath_rx {
308 u8 defant; 308 u8 defant;
309 u8 rxotherant; 309 u8 rxotherant;
310 u32 *rxlink; 310 u32 *rxlink;
311 u32 num_pkts;
311 unsigned int rxfilter; 312 unsigned int rxfilter;
312 spinlock_t rxbuflock; 313 spinlock_t rxbuflock;
313 struct list_head rxbuf; 314 struct list_head rxbuf;
@@ -326,6 +327,9 @@ int ath_rx_init(struct ath_softc *sc, int nbufs);
326void ath_rx_cleanup(struct ath_softc *sc); 327void ath_rx_cleanup(struct ath_softc *sc);
327int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp); 328int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp);
328struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype); 329struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
330void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq);
331void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq);
332void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq);
329void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq); 333void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
330bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx); 334bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx);
331void ath_draintxq(struct ath_softc *sc, 335void ath_draintxq(struct ath_softc *sc,
@@ -415,9 +419,9 @@ int ath_beaconq_config(struct ath_softc *sc);
415void ath_set_beacon(struct ath_softc *sc); 419void ath_set_beacon(struct ath_softc *sc);
416void ath9k_set_beaconing_status(struct ath_softc *sc, bool status); 420void ath9k_set_beaconing_status(struct ath_softc *sc, bool status);
417 421
418/*******/ 422/*******************/
419/* ANI */ 423/* Link Monitoring */
420/*******/ 424/*******************/
421 425
422#define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */ 426#define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */
423#define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */ 427#define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */
@@ -428,7 +432,9 @@ void ath9k_set_beaconing_status(struct ath_softc *sc, bool status);
428#define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */ 432#define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */
429 433
430#define ATH_PAPRD_TIMEOUT 100 /* msecs */ 434#define ATH_PAPRD_TIMEOUT 100 /* msecs */
435#define ATH_PLL_WORK_INTERVAL 100
431 436
437void ath_tx_complete_poll_work(struct work_struct *work);
432void ath_reset_work(struct work_struct *work); 438void ath_reset_work(struct work_struct *work);
433void ath_hw_check(struct work_struct *work); 439void ath_hw_check(struct work_struct *work);
434void ath_hw_pll_work(struct work_struct *work); 440void ath_hw_pll_work(struct work_struct *work);
@@ -437,22 +443,31 @@ void ath_start_rx_poll(struct ath_softc *sc, u8 nbeacon);
437void ath_paprd_calibrate(struct work_struct *work); 443void ath_paprd_calibrate(struct work_struct *work);
438void ath_ani_calibrate(unsigned long data); 444void ath_ani_calibrate(unsigned long data);
439void ath_start_ani(struct ath_common *common); 445void ath_start_ani(struct ath_common *common);
446int ath_update_survey_stats(struct ath_softc *sc);
447void ath_update_survey_nf(struct ath_softc *sc, int channel);
440 448
441/**********/ 449/**********/
442/* BTCOEX */ 450/* BTCOEX */
443/**********/ 451/**********/
444 452
453enum bt_op_flags {
454 BT_OP_PRIORITY_DETECTED,
455 BT_OP_SCAN,
456};
457
445struct ath_btcoex { 458struct ath_btcoex {
446 bool hw_timer_enabled; 459 bool hw_timer_enabled;
447 spinlock_t btcoex_lock; 460 spinlock_t btcoex_lock;
448 struct timer_list period_timer; /* Timer for BT period */ 461 struct timer_list period_timer; /* Timer for BT period */
449 u32 bt_priority_cnt; 462 u32 bt_priority_cnt;
450 unsigned long bt_priority_time; 463 unsigned long bt_priority_time;
464 unsigned long op_flags;
451 int bt_stomp_type; /* Types of BT stomping */ 465 int bt_stomp_type; /* Types of BT stomping */
452 u32 btcoex_no_stomp; /* in usec */ 466 u32 btcoex_no_stomp; /* in usec */
453 u32 btcoex_period; /* in usec */ 467 u32 btcoex_period; /* in usec */
454 u32 btscan_no_stomp; /* in usec */ 468 u32 btscan_no_stomp; /* in usec */
455 u32 duty_cycle; 469 u32 duty_cycle;
470 u32 bt_wait_time;
456 struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */ 471 struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */
457 struct ath_mci_profile mci; 472 struct ath_mci_profile mci;
458}; 473};
@@ -466,6 +481,7 @@ void ath9k_btcoex_timer_resume(struct ath_softc *sc);
466void ath9k_btcoex_timer_pause(struct ath_softc *sc); 481void ath9k_btcoex_timer_pause(struct ath_softc *sc);
467void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, u32 status); 482void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, u32 status);
468u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, u32 max_4ms_framelen); 483u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, u32 max_4ms_framelen);
484void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc);
469#else 485#else
470static inline int ath9k_init_btcoex(struct ath_softc *sc) 486static inline int ath9k_init_btcoex(struct ath_softc *sc)
471{ 487{
@@ -489,6 +505,9 @@ static inline u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc,
489{ 505{
490 return 0; 506 return 0;
491} 507}
508static inline void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc)
509{
510}
492#endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */ 511#endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
493 512
494/********************/ 513/********************/
@@ -514,8 +533,10 @@ static inline void ath_deinit_leds(struct ath_softc *sc)
514} 533}
515#endif 534#endif
516 535
517 536/*******************************/
518/* Antenna diversity/combining */ 537/* Antenna diversity/combining */
538/*******************************/
539
519#define ATH_ANT_RX_CURRENT_SHIFT 4 540#define ATH_ANT_RX_CURRENT_SHIFT 4
520#define ATH_ANT_RX_MAIN_SHIFT 2 541#define ATH_ANT_RX_MAIN_SHIFT 2
521#define ATH_ANT_RX_MASK 0x3 542#define ATH_ANT_RX_MASK 0x3
@@ -568,6 +589,9 @@ struct ath_ant_comb {
568 unsigned long scan_start_time; 589 unsigned long scan_start_time;
569}; 590};
570 591
592void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs);
593void ath_ant_comb_update(struct ath_softc *sc);
594
571/********************/ 595/********************/
572/* Main driver core */ 596/* Main driver core */
573/********************/ 597/********************/
@@ -585,15 +609,15 @@ struct ath_ant_comb {
585#define ATH_TXPOWER_MAX 100 /* .5 dBm units */ 609#define ATH_TXPOWER_MAX 100 /* .5 dBm units */
586#define ATH_RATE_DUMMY_MARKER 0 610#define ATH_RATE_DUMMY_MARKER 0
587 611
588#define SC_OP_INVALID BIT(0) 612enum sc_op_flags {
589#define SC_OP_BEACONS BIT(1) 613 SC_OP_INVALID,
590#define SC_OP_OFFCHANNEL BIT(2) 614 SC_OP_BEACONS,
591#define SC_OP_RXFLUSH BIT(3) 615 SC_OP_RXFLUSH,
592#define SC_OP_TSF_RESET BIT(4) 616 SC_OP_TSF_RESET,
593#define SC_OP_BT_PRIORITY_DETECTED BIT(5) 617 SC_OP_ANI_RUN,
594#define SC_OP_BT_SCAN BIT(6) 618 SC_OP_PRIM_STA_VIF,
595#define SC_OP_ANI_RUN BIT(7) 619 SC_OP_HW_RESET,
596#define SC_OP_PRIM_STA_VIF BIT(8) 620};
597 621
598/* Powersave flags */ 622/* Powersave flags */
599#define PS_WAIT_FOR_BEACON BIT(0) 623#define PS_WAIT_FOR_BEACON BIT(0)
@@ -639,9 +663,9 @@ struct ath_softc {
639 struct completion paprd_complete; 663 struct completion paprd_complete;
640 664
641 unsigned int hw_busy_count; 665 unsigned int hw_busy_count;
666 unsigned long sc_flags;
642 667
643 u32 intrstatus; 668 u32 intrstatus;
644 u32 sc_flags; /* SC_OP_* */
645 u16 ps_flags; /* PS_* */ 669 u16 ps_flags; /* PS_* */
646 u16 curtxpow; 670 u16 curtxpow;
647 bool ps_enabled; 671 bool ps_enabled;
@@ -679,6 +703,7 @@ struct ath_softc {
679#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 703#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
680 struct ath_btcoex btcoex; 704 struct ath_btcoex btcoex;
681 struct ath_mci_coex mci_coex; 705 struct ath_mci_coex mci_coex;
706 struct work_struct mci_work;
682#endif 707#endif
683 708
684 struct ath_descdma txsdma; 709 struct ath_descdma txsdma;
@@ -701,6 +726,7 @@ extern int ath9k_modparam_nohwcrypt;
701extern int led_blink; 726extern int led_blink;
702extern bool is_ath9k_unloaded; 727extern bool is_ath9k_unloaded;
703 728
729u8 ath9k_parse_mpdudensity(u8 mpdudensity);
704irqreturn_t ath_isr(int irq, void *dev); 730irqreturn_t ath_isr(int irq, void *dev);
705int ath9k_init_device(u16 devid, struct ath_softc *sc, 731int ath9k_init_device(u16 devid, struct ath_softc *sc,
706 const struct ath_bus_ops *bus_ops); 732 const struct ath_bus_ops *bus_ops);
@@ -737,5 +763,4 @@ void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
737 struct ieee80211_vif *vif, 763 struct ieee80211_vif *vif,
738 struct ath9k_vif_iter_data *iter_data); 764 struct ath9k_vif_iter_data *iter_data);
739 765
740
741#endif /* ATH9K_H */ 766#endif /* ATH9K_H */
diff --git a/drivers/net/wireless/ath/ath9k/beacon.c b/drivers/net/wireless/ath/ath9k/beacon.c
index 11bc55e3d697..40775da8941e 100644
--- a/drivers/net/wireless/ath/ath9k/beacon.c
+++ b/drivers/net/wireless/ath/ath9k/beacon.c
@@ -48,7 +48,10 @@ int ath_beaconq_config(struct ath_softc *sc)
48 txq = sc->tx.txq_map[WME_AC_BE]; 48 txq = sc->tx.txq_map[WME_AC_BE];
49 ath9k_hw_get_txq_props(ah, txq->axq_qnum, &qi_be); 49 ath9k_hw_get_txq_props(ah, txq->axq_qnum, &qi_be);
50 qi.tqi_aifs = qi_be.tqi_aifs; 50 qi.tqi_aifs = qi_be.tqi_aifs;
51 qi.tqi_cwmin = 4*qi_be.tqi_cwmin; 51 if (ah->slottime == ATH9K_SLOT_TIME_20)
52 qi.tqi_cwmin = 2*qi_be.tqi_cwmin;
53 else
54 qi.tqi_cwmin = 4*qi_be.tqi_cwmin;
52 qi.tqi_cwmax = qi_be.tqi_cwmax; 55 qi.tqi_cwmax = qi_be.tqi_cwmax;
53 } 56 }
54 57
@@ -387,7 +390,7 @@ void ath_beacon_tasklet(unsigned long data)
387 } else if (sc->beacon.bmisscnt >= BSTUCK_THRESH) { 390 } else if (sc->beacon.bmisscnt >= BSTUCK_THRESH) {
388 ath_dbg(common, BSTUCK, "beacon is officially stuck\n"); 391 ath_dbg(common, BSTUCK, "beacon is officially stuck\n");
389 sc->beacon.bmisscnt = 0; 392 sc->beacon.bmisscnt = 0;
390 sc->sc_flags |= SC_OP_TSF_RESET; 393 set_bit(SC_OP_TSF_RESET, &sc->sc_flags);
391 ieee80211_queue_work(sc->hw, &sc->hw_reset_work); 394 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
392 } 395 }
393 396
@@ -477,16 +480,16 @@ static void ath9k_beacon_init(struct ath_softc *sc,
477 u32 next_beacon, 480 u32 next_beacon,
478 u32 beacon_period) 481 u32 beacon_period)
479{ 482{
480 if (sc->sc_flags & SC_OP_TSF_RESET) { 483 if (test_bit(SC_OP_TSF_RESET, &sc->sc_flags)) {
481 ath9k_ps_wakeup(sc); 484 ath9k_ps_wakeup(sc);
482 ath9k_hw_reset_tsf(sc->sc_ah); 485 ath9k_hw_reset_tsf(sc->sc_ah);
483 } 486 }
484 487
485 ath9k_hw_beaconinit(sc->sc_ah, next_beacon, beacon_period); 488 ath9k_hw_beaconinit(sc->sc_ah, next_beacon, beacon_period);
486 489
487 if (sc->sc_flags & SC_OP_TSF_RESET) { 490 if (test_bit(SC_OP_TSF_RESET, &sc->sc_flags)) {
488 ath9k_ps_restore(sc); 491 ath9k_ps_restore(sc);
489 sc->sc_flags &= ~SC_OP_TSF_RESET; 492 clear_bit(SC_OP_TSF_RESET, &sc->sc_flags);
490 } 493 }
491} 494}
492 495
@@ -516,7 +519,7 @@ static void ath_beacon_config_ap(struct ath_softc *sc,
516 /* Set the computed AP beacon timers */ 519 /* Set the computed AP beacon timers */
517 520
518 ath9k_hw_disable_interrupts(ah); 521 ath9k_hw_disable_interrupts(ah);
519 sc->sc_flags |= SC_OP_TSF_RESET; 522 set_bit(SC_OP_TSF_RESET, &sc->sc_flags);
520 ath9k_beacon_init(sc, nexttbtt, intval); 523 ath9k_beacon_init(sc, nexttbtt, intval);
521 sc->beacon.bmisscnt = 0; 524 sc->beacon.bmisscnt = 0;
522 ath9k_hw_set_interrupts(ah); 525 ath9k_hw_set_interrupts(ah);
@@ -659,7 +662,7 @@ static void ath_beacon_config_adhoc(struct ath_softc *sc,
659 u32 tsf, intval, nexttbtt; 662 u32 tsf, intval, nexttbtt;
660 663
661 ath9k_reset_beacon_status(sc); 664 ath9k_reset_beacon_status(sc);
662 if (!(sc->sc_flags & SC_OP_BEACONS)) 665 if (!test_bit(SC_OP_BEACONS, &sc->sc_flags))
663 ath9k_hw_settsf64(ah, sc->beacon.bc_tstamp); 666 ath9k_hw_settsf64(ah, sc->beacon.bc_tstamp);
664 667
665 intval = TU_TO_USEC(conf->beacon_interval); 668 intval = TU_TO_USEC(conf->beacon_interval);
@@ -724,7 +727,7 @@ static bool ath9k_allow_beacon_config(struct ath_softc *sc,
724 */ 727 */
725 if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) && 728 if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) &&
726 (vif->type == NL80211_IFTYPE_STATION) && 729 (vif->type == NL80211_IFTYPE_STATION) &&
727 (sc->sc_flags & SC_OP_BEACONS) && 730 test_bit(SC_OP_BEACONS, &sc->sc_flags) &&
728 !avp->primary_sta_vif) { 731 !avp->primary_sta_vif) {
729 ath_dbg(common, CONFIG, 732 ath_dbg(common, CONFIG,
730 "Beacon already configured for a station interface\n"); 733 "Beacon already configured for a station interface\n");
@@ -810,7 +813,7 @@ void ath_set_beacon(struct ath_softc *sc)
810 return; 813 return;
811 } 814 }
812 815
813 sc->sc_flags |= SC_OP_BEACONS; 816 set_bit(SC_OP_BEACONS, &sc->sc_flags);
814} 817}
815 818
816void ath9k_set_beaconing_status(struct ath_softc *sc, bool status) 819void ath9k_set_beaconing_status(struct ath_softc *sc, bool status)
@@ -818,7 +821,7 @@ void ath9k_set_beaconing_status(struct ath_softc *sc, bool status)
818 struct ath_hw *ah = sc->sc_ah; 821 struct ath_hw *ah = sc->sc_ah;
819 822
820 if (!ath_has_valid_bslot(sc)) { 823 if (!ath_has_valid_bslot(sc)) {
821 sc->sc_flags &= ~SC_OP_BEACONS; 824 clear_bit(SC_OP_BEACONS, &sc->sc_flags);
822 return; 825 return;
823 } 826 }
824 827
diff --git a/drivers/net/wireless/ath/ath9k/btcoex.c b/drivers/net/wireless/ath/ath9k/btcoex.c
index 1ca6da80d4ad..acd437384fe4 100644
--- a/drivers/net/wireless/ath/ath9k/btcoex.c
+++ b/drivers/net/wireless/ath/ath9k/btcoex.c
@@ -336,10 +336,16 @@ static void ar9003_btcoex_bt_stomp(struct ath_hw *ah,
336 enum ath_stomp_type stomp_type) 336 enum ath_stomp_type stomp_type)
337{ 337{
338 struct ath_btcoex_hw *btcoex = &ah->btcoex_hw; 338 struct ath_btcoex_hw *btcoex = &ah->btcoex_hw;
339 const u32 *weight = AR_SREV_9462(ah) ? ar9003_wlan_weights[stomp_type] : 339 const u32 *weight = ar9003_wlan_weights[stomp_type];
340 ar9462_wlan_weights[stomp_type];
341 int i; 340 int i;
342 341
342 if (AR_SREV_9462(ah)) {
343 if ((stomp_type == ATH_BTCOEX_STOMP_LOW) &&
344 btcoex->mci.stomp_ftp)
345 stomp_type = ATH_BTCOEX_STOMP_LOW_FTP;
346 weight = ar9462_wlan_weights[stomp_type];
347 }
348
343 for (i = 0; i < AR9300_NUM_WLAN_WEIGHTS; i++) { 349 for (i = 0; i < AR9300_NUM_WLAN_WEIGHTS; i++) {
344 btcoex->bt_weight[i] = AR9300_BT_WGHT; 350 btcoex->bt_weight[i] = AR9300_BT_WGHT;
345 btcoex->wlan_weight[i] = weight[i]; 351 btcoex->wlan_weight[i] = weight[i];
diff --git a/drivers/net/wireless/ath/ath9k/btcoex.h b/drivers/net/wireless/ath/ath9k/btcoex.h
index 3a1e1cfabd5e..20092f98658f 100644
--- a/drivers/net/wireless/ath/ath9k/btcoex.h
+++ b/drivers/net/wireless/ath/ath9k/btcoex.h
@@ -36,6 +36,9 @@
36#define ATH_BT_CNT_THRESHOLD 3 36#define ATH_BT_CNT_THRESHOLD 3
37#define ATH_BT_CNT_SCAN_THRESHOLD 15 37#define ATH_BT_CNT_SCAN_THRESHOLD 15
38 38
39#define ATH_BTCOEX_RX_WAIT_TIME 100
40#define ATH_BTCOEX_STOMP_FTP_THRESH 5
41
39#define AR9300_NUM_BT_WEIGHTS 4 42#define AR9300_NUM_BT_WEIGHTS 4
40#define AR9300_NUM_WLAN_WEIGHTS 4 43#define AR9300_NUM_WLAN_WEIGHTS 4
41/* Defines the BT AR_BT_COEX_WGHT used */ 44/* Defines the BT AR_BT_COEX_WGHT used */
@@ -80,6 +83,7 @@ struct ath9k_hw_mci {
80 u8 bt_ver_major; 83 u8 bt_ver_major;
81 u8 bt_ver_minor; 84 u8 bt_ver_minor;
82 u8 bt_state; 85 u8 bt_state;
86 u8 stomp_ftp;
83}; 87};
84 88
85struct ath_btcoex_hw { 89struct ath_btcoex_hw {
diff --git a/drivers/net/wireless/ath/ath9k/debug.c b/drivers/net/wireless/ath/ath9k/debug.c
index fde700c4e490..5c3192ffc196 100644
--- a/drivers/net/wireless/ath/ath9k/debug.c
+++ b/drivers/net/wireless/ath/ath9k/debug.c
@@ -205,10 +205,10 @@ static ssize_t write_file_disable_ani(struct file *file,
205 common->disable_ani = !!disable_ani; 205 common->disable_ani = !!disable_ani;
206 206
207 if (disable_ani) { 207 if (disable_ani) {
208 sc->sc_flags &= ~SC_OP_ANI_RUN; 208 clear_bit(SC_OP_ANI_RUN, &sc->sc_flags);
209 del_timer_sync(&common->ani.timer); 209 del_timer_sync(&common->ani.timer);
210 } else { 210 } else {
211 sc->sc_flags |= SC_OP_ANI_RUN; 211 set_bit(SC_OP_ANI_RUN, &sc->sc_flags);
212 ath_start_ani(common); 212 ath_start_ani(common);
213 } 213 }
214 214
@@ -348,8 +348,6 @@ void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status)
348 sc->debug.stats.istats.txok++; 348 sc->debug.stats.istats.txok++;
349 if (status & ATH9K_INT_TXURN) 349 if (status & ATH9K_INT_TXURN)
350 sc->debug.stats.istats.txurn++; 350 sc->debug.stats.istats.txurn++;
351 if (status & ATH9K_INT_MIB)
352 sc->debug.stats.istats.mib++;
353 if (status & ATH9K_INT_RXPHY) 351 if (status & ATH9K_INT_RXPHY)
354 sc->debug.stats.istats.rxphyerr++; 352 sc->debug.stats.istats.rxphyerr++;
355 if (status & ATH9K_INT_RXKCM) 353 if (status & ATH9K_INT_RXKCM)
@@ -374,6 +372,8 @@ void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status)
374 sc->debug.stats.istats.dtim++; 372 sc->debug.stats.istats.dtim++;
375 if (status & ATH9K_INT_TSFOOR) 373 if (status & ATH9K_INT_TSFOOR)
376 sc->debug.stats.istats.tsfoor++; 374 sc->debug.stats.istats.tsfoor++;
375 if (status & ATH9K_INT_MCI)
376 sc->debug.stats.istats.mci++;
377} 377}
378 378
379static ssize_t read_file_interrupt(struct file *file, char __user *user_buf, 379static ssize_t read_file_interrupt(struct file *file, char __user *user_buf,
@@ -418,6 +418,7 @@ static ssize_t read_file_interrupt(struct file *file, char __user *user_buf,
418 PR_IS("DTIMSYNC", dtimsync); 418 PR_IS("DTIMSYNC", dtimsync);
419 PR_IS("DTIM", dtim); 419 PR_IS("DTIM", dtim);
420 PR_IS("TSFOOR", tsfoor); 420 PR_IS("TSFOOR", tsfoor);
421 PR_IS("MCI", mci);
421 PR_IS("TOTAL", total); 422 PR_IS("TOTAL", total);
422 423
423 len += snprintf(buf + len, mxlen - len, 424 len += snprintf(buf + len, mxlen - len,
@@ -1318,7 +1319,7 @@ static int open_file_bb_mac_samps(struct inode *inode, struct file *file)
1318 u8 chainmask = (ah->rxchainmask << 3) | ah->rxchainmask; 1319 u8 chainmask = (ah->rxchainmask << 3) | ah->rxchainmask;
1319 u8 nread; 1320 u8 nread;
1320 1321
1321 if (sc->sc_flags & SC_OP_INVALID) 1322 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
1322 return -EAGAIN; 1323 return -EAGAIN;
1323 1324
1324 buf = vmalloc(size); 1325 buf = vmalloc(size);
diff --git a/drivers/net/wireless/ath/ath9k/debug.h b/drivers/net/wireless/ath/ath9k/debug.h
index c34da09d9103..d0f851cea43a 100644
--- a/drivers/net/wireless/ath/ath9k/debug.h
+++ b/drivers/net/wireless/ath/ath9k/debug.h
@@ -86,6 +86,7 @@ struct ath_interrupt_stats {
86 u32 dtim; 86 u32 dtim;
87 u32 bb_watchdog; 87 u32 bb_watchdog;
88 u32 tsfoor; 88 u32 tsfoor;
89 u32 mci;
89 90
90 /* Sync-cause stats */ 91 /* Sync-cause stats */
91 u32 sync_cause_all; 92 u32 sync_cause_all;
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_4k.c b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
index 4322ac80c203..7d075105a85d 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_4k.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
@@ -135,7 +135,7 @@ static u32 ath9k_hw_4k_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
135 if (!dump_base_hdr) { 135 if (!dump_base_hdr) {
136 len += snprintf(buf + len, size - len, 136 len += snprintf(buf + len, size - len,
137 "%20s :\n", "2GHz modal Header"); 137 "%20s :\n", "2GHz modal Header");
138 len += ath9k_dump_4k_modal_eeprom(buf, len, size, 138 len = ath9k_dump_4k_modal_eeprom(buf, len, size,
139 &eep->modalHeader); 139 &eep->modalHeader);
140 goto out; 140 goto out;
141 } 141 }
@@ -188,8 +188,7 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
188{ 188{
189#define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16)) 189#define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
190 struct ath_common *common = ath9k_hw_common(ah); 190 struct ath_common *common = ath9k_hw_common(ah);
191 struct ar5416_eeprom_4k *eep = 191 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
192 (struct ar5416_eeprom_4k *) &ah->eeprom.map4k;
193 u16 *eepdata, temp, magic, magic2; 192 u16 *eepdata, temp, magic, magic2;
194 u32 sum = 0, el; 193 u32 sum = 0, el;
195 bool need_swap = false; 194 bool need_swap = false;
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_9287.c b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
index aa614767adff..cd742fb944c2 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_9287.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
@@ -132,7 +132,7 @@ static u32 ath9k_hw_ar9287_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
132 if (!dump_base_hdr) { 132 if (!dump_base_hdr) {
133 len += snprintf(buf + len, size - len, 133 len += snprintf(buf + len, size - len,
134 "%20s :\n", "2GHz modal Header"); 134 "%20s :\n", "2GHz modal Header");
135 len += ar9287_dump_modal_eeprom(buf, len, size, 135 len = ar9287_dump_modal_eeprom(buf, len, size,
136 &eep->modalHeader); 136 &eep->modalHeader);
137 goto out; 137 goto out;
138 } 138 }
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_def.c b/drivers/net/wireless/ath/ath9k/eeprom_def.c
index b5fba8b18b8b..a8ac30a00720 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_def.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_def.c
@@ -211,11 +211,11 @@ static u32 ath9k_hw_def_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
211 if (!dump_base_hdr) { 211 if (!dump_base_hdr) {
212 len += snprintf(buf + len, size - len, 212 len += snprintf(buf + len, size - len,
213 "%20s :\n", "2GHz modal Header"); 213 "%20s :\n", "2GHz modal Header");
214 len += ath9k_def_dump_modal_eeprom(buf, len, size, 214 len = ath9k_def_dump_modal_eeprom(buf, len, size,
215 &eep->modalHeader[0]); 215 &eep->modalHeader[0]);
216 len += snprintf(buf + len, size - len, 216 len += snprintf(buf + len, size - len,
217 "%20s :\n", "5GHz modal Header"); 217 "%20s :\n", "5GHz modal Header");
218 len += ath9k_def_dump_modal_eeprom(buf, len, size, 218 len = ath9k_def_dump_modal_eeprom(buf, len, size,
219 &eep->modalHeader[1]); 219 &eep->modalHeader[1]);
220 goto out; 220 goto out;
221 } 221 }
@@ -264,8 +264,7 @@ static u32 ath9k_hw_def_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
264 264
265static int ath9k_hw_def_check_eeprom(struct ath_hw *ah) 265static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
266{ 266{
267 struct ar5416_eeprom_def *eep = 267 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
268 (struct ar5416_eeprom_def *) &ah->eeprom.def;
269 struct ath_common *common = ath9k_hw_common(ah); 268 struct ath_common *common = ath9k_hw_common(ah);
270 u16 *eepdata, temp, magic, magic2; 269 u16 *eepdata, temp, magic, magic2;
271 u32 sum = 0, el; 270 u32 sum = 0, el;
diff --git a/drivers/net/wireless/ath/ath9k/gpio.c b/drivers/net/wireless/ath/ath9k/gpio.c
index 281a9af0f1b6..bacdb8fb4ef4 100644
--- a/drivers/net/wireless/ath/ath9k/gpio.c
+++ b/drivers/net/wireless/ath/ath9k/gpio.c
@@ -132,17 +132,18 @@ static void ath_detect_bt_priority(struct ath_softc *sc)
132 132
133 if (time_after(jiffies, btcoex->bt_priority_time + 133 if (time_after(jiffies, btcoex->bt_priority_time +
134 msecs_to_jiffies(ATH_BT_PRIORITY_TIME_THRESHOLD))) { 134 msecs_to_jiffies(ATH_BT_PRIORITY_TIME_THRESHOLD))) {
135 sc->sc_flags &= ~(SC_OP_BT_PRIORITY_DETECTED | SC_OP_BT_SCAN); 135 clear_bit(BT_OP_PRIORITY_DETECTED, &btcoex->op_flags);
136 clear_bit(BT_OP_SCAN, &btcoex->op_flags);
136 /* Detect if colocated bt started scanning */ 137 /* Detect if colocated bt started scanning */
137 if (btcoex->bt_priority_cnt >= ATH_BT_CNT_SCAN_THRESHOLD) { 138 if (btcoex->bt_priority_cnt >= ATH_BT_CNT_SCAN_THRESHOLD) {
138 ath_dbg(ath9k_hw_common(sc->sc_ah), BTCOEX, 139 ath_dbg(ath9k_hw_common(sc->sc_ah), BTCOEX,
139 "BT scan detected\n"); 140 "BT scan detected\n");
140 sc->sc_flags |= (SC_OP_BT_SCAN | 141 set_bit(BT_OP_PRIORITY_DETECTED, &btcoex->op_flags);
141 SC_OP_BT_PRIORITY_DETECTED); 142 set_bit(BT_OP_SCAN, &btcoex->op_flags);
142 } else if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) { 143 } else if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) {
143 ath_dbg(ath9k_hw_common(sc->sc_ah), BTCOEX, 144 ath_dbg(ath9k_hw_common(sc->sc_ah), BTCOEX,
144 "BT priority traffic detected\n"); 145 "BT priority traffic detected\n");
145 sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED; 146 set_bit(BT_OP_PRIORITY_DETECTED, &btcoex->op_flags);
146 } 147 }
147 148
148 btcoex->bt_priority_cnt = 0; 149 btcoex->bt_priority_cnt = 0;
@@ -190,13 +191,34 @@ static void ath_btcoex_period_timer(unsigned long data)
190 struct ath_softc *sc = (struct ath_softc *) data; 191 struct ath_softc *sc = (struct ath_softc *) data;
191 struct ath_hw *ah = sc->sc_ah; 192 struct ath_hw *ah = sc->sc_ah;
192 struct ath_btcoex *btcoex = &sc->btcoex; 193 struct ath_btcoex *btcoex = &sc->btcoex;
194 struct ath_mci_profile *mci = &btcoex->mci;
193 u32 timer_period; 195 u32 timer_period;
194 bool is_btscan; 196 bool is_btscan;
197 unsigned long flags;
198
199 spin_lock_irqsave(&sc->sc_pm_lock, flags);
200 if (sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP) {
201 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
202 goto skip_hw_wakeup;
203 }
204 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
195 205
196 ath9k_ps_wakeup(sc); 206 ath9k_ps_wakeup(sc);
197 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_MCI)) 207 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_MCI))
198 ath_detect_bt_priority(sc); 208 ath_detect_bt_priority(sc);
199 is_btscan = sc->sc_flags & SC_OP_BT_SCAN; 209 is_btscan = test_bit(BT_OP_SCAN, &btcoex->op_flags);
210
211 btcoex->bt_wait_time += btcoex->btcoex_period;
212 if (btcoex->bt_wait_time > ATH_BTCOEX_RX_WAIT_TIME) {
213 if (ar9003_mci_state(ah, MCI_STATE_NEED_FTP_STOMP) &&
214 (mci->num_pan || mci->num_other_acl))
215 ah->btcoex_hw.mci.stomp_ftp =
216 (sc->rx.num_pkts < ATH_BTCOEX_STOMP_FTP_THRESH);
217 else
218 ah->btcoex_hw.mci.stomp_ftp = false;
219 btcoex->bt_wait_time = 0;
220 sc->rx.num_pkts = 0;
221 }
200 222
201 spin_lock_bh(&btcoex->btcoex_lock); 223 spin_lock_bh(&btcoex->btcoex_lock);
202 224
@@ -218,9 +240,9 @@ static void ath_btcoex_period_timer(unsigned long data)
218 } 240 }
219 241
220 ath9k_ps_restore(sc); 242 ath9k_ps_restore(sc);
221 timer_period = btcoex->btcoex_period / 1000; 243skip_hw_wakeup:
222 mod_timer(&btcoex->period_timer, jiffies + 244 timer_period = btcoex->btcoex_period;
223 msecs_to_jiffies(timer_period)); 245 mod_timer(&btcoex->period_timer, jiffies + msecs_to_jiffies(timer_period));
224} 246}
225 247
226/* 248/*
@@ -233,14 +255,14 @@ static void ath_btcoex_no_stomp_timer(void *arg)
233 struct ath_hw *ah = sc->sc_ah; 255 struct ath_hw *ah = sc->sc_ah;
234 struct ath_btcoex *btcoex = &sc->btcoex; 256 struct ath_btcoex *btcoex = &sc->btcoex;
235 struct ath_common *common = ath9k_hw_common(ah); 257 struct ath_common *common = ath9k_hw_common(ah);
236 bool is_btscan = sc->sc_flags & SC_OP_BT_SCAN;
237 258
238 ath_dbg(common, BTCOEX, "no stomp timer running\n"); 259 ath_dbg(common, BTCOEX, "no stomp timer running\n");
239 260
240 ath9k_ps_wakeup(sc); 261 ath9k_ps_wakeup(sc);
241 spin_lock_bh(&btcoex->btcoex_lock); 262 spin_lock_bh(&btcoex->btcoex_lock);
242 263
243 if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_LOW || is_btscan) 264 if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_LOW ||
265 test_bit(BT_OP_SCAN, &btcoex->op_flags))
244 ath9k_hw_btcoex_bt_stomp(ah, ATH_BTCOEX_STOMP_NONE); 266 ath9k_hw_btcoex_bt_stomp(ah, ATH_BTCOEX_STOMP_NONE);
245 else if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_ALL) 267 else if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_ALL)
246 ath9k_hw_btcoex_bt_stomp(ah, ATH_BTCOEX_STOMP_LOW); 268 ath9k_hw_btcoex_bt_stomp(ah, ATH_BTCOEX_STOMP_LOW);
@@ -254,10 +276,10 @@ static int ath_init_btcoex_timer(struct ath_softc *sc)
254{ 276{
255 struct ath_btcoex *btcoex = &sc->btcoex; 277 struct ath_btcoex *btcoex = &sc->btcoex;
256 278
257 btcoex->btcoex_period = ATH_BTCOEX_DEF_BT_PERIOD * 1000; 279 btcoex->btcoex_period = ATH_BTCOEX_DEF_BT_PERIOD;
258 btcoex->btcoex_no_stomp = (100 - ATH_BTCOEX_DEF_DUTY_CYCLE) * 280 btcoex->btcoex_no_stomp = (100 - ATH_BTCOEX_DEF_DUTY_CYCLE) * 1000 *
259 btcoex->btcoex_period / 100; 281 btcoex->btcoex_period / 100;
260 btcoex->btscan_no_stomp = (100 - ATH_BTCOEX_BTSCAN_DUTY_CYCLE) * 282 btcoex->btscan_no_stomp = (100 - ATH_BTCOEX_BTSCAN_DUTY_CYCLE) * 1000 *
261 btcoex->btcoex_period / 100; 283 btcoex->btcoex_period / 100;
262 284
263 setup_timer(&btcoex->period_timer, ath_btcoex_period_timer, 285 setup_timer(&btcoex->period_timer, ath_btcoex_period_timer,
@@ -292,7 +314,8 @@ void ath9k_btcoex_timer_resume(struct ath_softc *sc)
292 314
293 btcoex->bt_priority_cnt = 0; 315 btcoex->bt_priority_cnt = 0;
294 btcoex->bt_priority_time = jiffies; 316 btcoex->bt_priority_time = jiffies;
295 sc->sc_flags &= ~(SC_OP_BT_PRIORITY_DETECTED | SC_OP_BT_SCAN); 317 clear_bit(BT_OP_PRIORITY_DETECTED, &btcoex->op_flags);
318 clear_bit(BT_OP_SCAN, &btcoex->op_flags);
296 319
297 mod_timer(&btcoex->period_timer, jiffies); 320 mod_timer(&btcoex->period_timer, jiffies);
298} 321}
@@ -314,14 +337,22 @@ void ath9k_btcoex_timer_pause(struct ath_softc *sc)
314 btcoex->hw_timer_enabled = false; 337 btcoex->hw_timer_enabled = false;
315} 338}
316 339
340void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc)
341{
342 struct ath_btcoex *btcoex = &sc->btcoex;
343
344 ath9k_gen_timer_stop(sc->sc_ah, btcoex->no_stomp_timer);
345}
346
317u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, u32 max_4ms_framelen) 347u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, u32 max_4ms_framelen)
318{ 348{
349 struct ath_btcoex *btcoex = &sc->btcoex;
319 struct ath_mci_profile *mci = &sc->btcoex.mci; 350 struct ath_mci_profile *mci = &sc->btcoex.mci;
320 u16 aggr_limit = 0; 351 u16 aggr_limit = 0;
321 352
322 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_MCI) && mci->aggr_limit) 353 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_MCI) && mci->aggr_limit)
323 aggr_limit = (max_4ms_framelen * mci->aggr_limit) >> 4; 354 aggr_limit = (max_4ms_framelen * mci->aggr_limit) >> 4;
324 else if (sc->sc_flags & SC_OP_BT_PRIORITY_DETECTED) 355 else if (test_bit(BT_OP_PRIORITY_DETECTED, &btcoex->op_flags))
325 aggr_limit = min((max_4ms_framelen * 3) / 8, 356 aggr_limit = min((max_4ms_framelen * 3) / 8,
326 (u32)ATH_AMPDU_LIMIT_MAX); 357 (u32)ATH_AMPDU_LIMIT_MAX);
327 358
@@ -362,9 +393,9 @@ void ath9k_stop_btcoex(struct ath_softc *sc)
362 393
363 if (ah->btcoex_hw.enabled && 394 if (ah->btcoex_hw.enabled &&
364 ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) { 395 ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) {
365 ath9k_hw_btcoex_disable(ah);
366 if (ath9k_hw_get_btcoex_scheme(ah) == ATH_BTCOEX_CFG_3WIRE) 396 if (ath9k_hw_get_btcoex_scheme(ah) == ATH_BTCOEX_CFG_3WIRE)
367 ath9k_btcoex_timer_pause(sc); 397 ath9k_btcoex_timer_pause(sc);
398 ath9k_hw_btcoex_disable(ah);
368 if (AR_SREV_9462(ah)) 399 if (AR_SREV_9462(ah))
369 ath_mci_flush_profile(&sc->btcoex.mci); 400 ath_mci_flush_profile(&sc->btcoex.mci);
370 } 401 }
@@ -372,11 +403,13 @@ void ath9k_stop_btcoex(struct ath_softc *sc)
372 403
373void ath9k_deinit_btcoex(struct ath_softc *sc) 404void ath9k_deinit_btcoex(struct ath_softc *sc)
374{ 405{
406 struct ath_hw *ah = sc->sc_ah;
407
375 if ((sc->btcoex.no_stomp_timer) && 408 if ((sc->btcoex.no_stomp_timer) &&
376 ath9k_hw_get_btcoex_scheme(sc->sc_ah) == ATH_BTCOEX_CFG_3WIRE) 409 ath9k_hw_get_btcoex_scheme(sc->sc_ah) == ATH_BTCOEX_CFG_3WIRE)
377 ath_gen_timer_free(sc->sc_ah, sc->btcoex.no_stomp_timer); 410 ath_gen_timer_free(sc->sc_ah, sc->btcoex.no_stomp_timer);
378 411
379 if (AR_SREV_9462(sc->sc_ah)) 412 if (ath9k_hw_mci_is_enabled(ah))
380 ath_mci_cleanup(sc); 413 ath_mci_cleanup(sc);
381} 414}
382 415
@@ -402,7 +435,7 @@ int ath9k_init_btcoex(struct ath_softc *sc)
402 txq = sc->tx.txq_map[WME_AC_BE]; 435 txq = sc->tx.txq_map[WME_AC_BE];
403 ath9k_hw_init_btcoex_hw(sc->sc_ah, txq->axq_qnum); 436 ath9k_hw_init_btcoex_hw(sc->sc_ah, txq->axq_qnum);
404 sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW; 437 sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
405 if (AR_SREV_9462(ah)) { 438 if (ath9k_hw_mci_is_enabled(ah)) {
406 sc->btcoex.duty_cycle = ATH_BTCOEX_DEF_DUTY_CYCLE; 439 sc->btcoex.duty_cycle = ATH_BTCOEX_DEF_DUTY_CYCLE;
407 INIT_LIST_HEAD(&sc->btcoex.mci.info); 440 INIT_LIST_HEAD(&sc->btcoex.mci.info);
408 441
diff --git a/drivers/net/wireless/ath/ath9k/htc.h b/drivers/net/wireless/ath/ath9k/htc.h
index 135795257d95..936e920fb88e 100644
--- a/drivers/net/wireless/ath/ath9k/htc.h
+++ b/drivers/net/wireless/ath/ath9k/htc.h
@@ -453,7 +453,6 @@ struct ath9k_htc_priv {
453 u8 num_sta_assoc_vif; 453 u8 num_sta_assoc_vif;
454 u8 num_ap_vif; 454 u8 num_ap_vif;
455 455
456 u16 op_flags;
457 u16 curtxpow; 456 u16 curtxpow;
458 u16 txpowlimit; 457 u16 txpowlimit;
459 u16 nvifs; 458 u16 nvifs;
@@ -461,6 +460,7 @@ struct ath9k_htc_priv {
461 bool rearm_ani; 460 bool rearm_ani;
462 bool reconfig_beacon; 461 bool reconfig_beacon;
463 unsigned int rxfilter; 462 unsigned int rxfilter;
463 unsigned long op_flags;
464 464
465 struct ath9k_hw_cal_data caldata; 465 struct ath9k_hw_cal_data caldata;
466 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS]; 466 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
@@ -572,8 +572,6 @@ bool ath9k_htc_setpower(struct ath9k_htc_priv *priv,
572 572
573void ath9k_start_rfkill_poll(struct ath9k_htc_priv *priv); 573void ath9k_start_rfkill_poll(struct ath9k_htc_priv *priv);
574void ath9k_htc_rfkill_poll_state(struct ieee80211_hw *hw); 574void ath9k_htc_rfkill_poll_state(struct ieee80211_hw *hw);
575void ath9k_htc_radio_enable(struct ieee80211_hw *hw);
576void ath9k_htc_radio_disable(struct ieee80211_hw *hw);
577 575
578#ifdef CONFIG_MAC80211_LEDS 576#ifdef CONFIG_MAC80211_LEDS
579void ath9k_init_leds(struct ath9k_htc_priv *priv); 577void ath9k_init_leds(struct ath9k_htc_priv *priv);
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c b/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c
index 2eadffb7971c..77d541feb910 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c
@@ -207,9 +207,9 @@ static void ath9k_htc_beacon_config_ap(struct ath9k_htc_priv *priv,
207 else 207 else
208 priv->ah->config.sw_beacon_response_time = MIN_SWBA_RESPONSE; 208 priv->ah->config.sw_beacon_response_time = MIN_SWBA_RESPONSE;
209 209
210 if (priv->op_flags & OP_TSF_RESET) { 210 if (test_bit(OP_TSF_RESET, &priv->op_flags)) {
211 ath9k_hw_reset_tsf(priv->ah); 211 ath9k_hw_reset_tsf(priv->ah);
212 priv->op_flags &= ~OP_TSF_RESET; 212 clear_bit(OP_TSF_RESET, &priv->op_flags);
213 } else { 213 } else {
214 /* 214 /*
215 * Pull nexttbtt forward to reflect the current TSF. 215 * Pull nexttbtt forward to reflect the current TSF.
@@ -221,7 +221,7 @@ static void ath9k_htc_beacon_config_ap(struct ath9k_htc_priv *priv,
221 } while (nexttbtt < tsftu); 221 } while (nexttbtt < tsftu);
222 } 222 }
223 223
224 if (priv->op_flags & OP_ENABLE_BEACON) 224 if (test_bit(OP_ENABLE_BEACON, &priv->op_flags))
225 imask |= ATH9K_INT_SWBA; 225 imask |= ATH9K_INT_SWBA;
226 226
227 ath_dbg(common, CONFIG, 227 ath_dbg(common, CONFIG,
@@ -269,7 +269,7 @@ static void ath9k_htc_beacon_config_adhoc(struct ath9k_htc_priv *priv,
269 else 269 else
270 priv->ah->config.sw_beacon_response_time = MIN_SWBA_RESPONSE; 270 priv->ah->config.sw_beacon_response_time = MIN_SWBA_RESPONSE;
271 271
272 if (priv->op_flags & OP_ENABLE_BEACON) 272 if (test_bit(OP_ENABLE_BEACON, &priv->op_flags))
273 imask |= ATH9K_INT_SWBA; 273 imask |= ATH9K_INT_SWBA;
274 274
275 ath_dbg(common, CONFIG, 275 ath_dbg(common, CONFIG,
@@ -365,7 +365,7 @@ static void ath9k_htc_send_beacon(struct ath9k_htc_priv *priv,
365 vif = priv->cur_beacon_conf.bslot[slot]; 365 vif = priv->cur_beacon_conf.bslot[slot];
366 avp = (struct ath9k_htc_vif *)vif->drv_priv; 366 avp = (struct ath9k_htc_vif *)vif->drv_priv;
367 367
368 if (unlikely(priv->op_flags & OP_SCANNING)) { 368 if (unlikely(test_bit(OP_SCANNING, &priv->op_flags))) {
369 spin_unlock_bh(&priv->beacon_lock); 369 spin_unlock_bh(&priv->beacon_lock);
370 return; 370 return;
371 } 371 }
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_gpio.c b/drivers/net/wireless/ath/ath9k/htc_drv_gpio.c
index 1c10e2e5c237..07df279c8d46 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_gpio.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_gpio.c
@@ -37,17 +37,18 @@ static void ath_detect_bt_priority(struct ath9k_htc_priv *priv)
37 37
38 if (time_after(jiffies, btcoex->bt_priority_time + 38 if (time_after(jiffies, btcoex->bt_priority_time +
39 msecs_to_jiffies(ATH_BT_PRIORITY_TIME_THRESHOLD))) { 39 msecs_to_jiffies(ATH_BT_PRIORITY_TIME_THRESHOLD))) {
40 priv->op_flags &= ~(OP_BT_PRIORITY_DETECTED | OP_BT_SCAN); 40 clear_bit(OP_BT_PRIORITY_DETECTED, &priv->op_flags);
41 clear_bit(OP_BT_SCAN, &priv->op_flags);
41 /* Detect if colocated bt started scanning */ 42 /* Detect if colocated bt started scanning */
42 if (btcoex->bt_priority_cnt >= ATH_BT_CNT_SCAN_THRESHOLD) { 43 if (btcoex->bt_priority_cnt >= ATH_BT_CNT_SCAN_THRESHOLD) {
43 ath_dbg(ath9k_hw_common(ah), BTCOEX, 44 ath_dbg(ath9k_hw_common(ah), BTCOEX,
44 "BT scan detected\n"); 45 "BT scan detected\n");
45 priv->op_flags |= (OP_BT_SCAN | 46 set_bit(OP_BT_PRIORITY_DETECTED, &priv->op_flags);
46 OP_BT_PRIORITY_DETECTED); 47 set_bit(OP_BT_SCAN, &priv->op_flags);
47 } else if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) { 48 } else if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) {
48 ath_dbg(ath9k_hw_common(ah), BTCOEX, 49 ath_dbg(ath9k_hw_common(ah), BTCOEX,
49 "BT priority traffic detected\n"); 50 "BT priority traffic detected\n");
50 priv->op_flags |= OP_BT_PRIORITY_DETECTED; 51 set_bit(OP_BT_PRIORITY_DETECTED, &priv->op_flags);
51 } 52 }
52 53
53 btcoex->bt_priority_cnt = 0; 54 btcoex->bt_priority_cnt = 0;
@@ -67,26 +68,23 @@ static void ath_btcoex_period_work(struct work_struct *work)
67 struct ath_btcoex *btcoex = &priv->btcoex; 68 struct ath_btcoex *btcoex = &priv->btcoex;
68 struct ath_common *common = ath9k_hw_common(priv->ah); 69 struct ath_common *common = ath9k_hw_common(priv->ah);
69 u32 timer_period; 70 u32 timer_period;
70 bool is_btscan;
71 int ret; 71 int ret;
72 72
73 ath_detect_bt_priority(priv); 73 ath_detect_bt_priority(priv);
74 74
75 is_btscan = !!(priv->op_flags & OP_BT_SCAN);
76
77 ret = ath9k_htc_update_cap_target(priv, 75 ret = ath9k_htc_update_cap_target(priv,
78 !!(priv->op_flags & OP_BT_PRIORITY_DETECTED)); 76 test_bit(OP_BT_PRIORITY_DETECTED, &priv->op_flags));
79 if (ret) { 77 if (ret) {
80 ath_err(common, "Unable to set BTCOEX parameters\n"); 78 ath_err(common, "Unable to set BTCOEX parameters\n");
81 return; 79 return;
82 } 80 }
83 81
84 ath9k_hw_btcoex_bt_stomp(priv->ah, is_btscan ? ATH_BTCOEX_STOMP_ALL : 82 ath9k_hw_btcoex_bt_stomp(priv->ah, test_bit(OP_BT_SCAN, &priv->op_flags) ?
85 btcoex->bt_stomp_type); 83 ATH_BTCOEX_STOMP_ALL : btcoex->bt_stomp_type);
86 84
87 ath9k_hw_btcoex_enable(priv->ah); 85 ath9k_hw_btcoex_enable(priv->ah);
88 timer_period = is_btscan ? btcoex->btscan_no_stomp : 86 timer_period = test_bit(OP_BT_SCAN, &priv->op_flags) ?
89 btcoex->btcoex_no_stomp; 87 btcoex->btscan_no_stomp : btcoex->btcoex_no_stomp;
90 ieee80211_queue_delayed_work(priv->hw, &priv->duty_cycle_work, 88 ieee80211_queue_delayed_work(priv->hw, &priv->duty_cycle_work,
91 msecs_to_jiffies(timer_period)); 89 msecs_to_jiffies(timer_period));
92 ieee80211_queue_delayed_work(priv->hw, &priv->coex_period_work, 90 ieee80211_queue_delayed_work(priv->hw, &priv->coex_period_work,
@@ -104,14 +102,15 @@ static void ath_btcoex_duty_cycle_work(struct work_struct *work)
104 struct ath_hw *ah = priv->ah; 102 struct ath_hw *ah = priv->ah;
105 struct ath_btcoex *btcoex = &priv->btcoex; 103 struct ath_btcoex *btcoex = &priv->btcoex;
106 struct ath_common *common = ath9k_hw_common(ah); 104 struct ath_common *common = ath9k_hw_common(ah);
107 bool is_btscan = priv->op_flags & OP_BT_SCAN;
108 105
109 ath_dbg(common, BTCOEX, "time slice work for bt and wlan\n"); 106 ath_dbg(common, BTCOEX, "time slice work for bt and wlan\n");
110 107
111 if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_LOW || is_btscan) 108 if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_LOW ||
109 test_bit(OP_BT_SCAN, &priv->op_flags))
112 ath9k_hw_btcoex_bt_stomp(ah, ATH_BTCOEX_STOMP_NONE); 110 ath9k_hw_btcoex_bt_stomp(ah, ATH_BTCOEX_STOMP_NONE);
113 else if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_ALL) 111 else if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_ALL)
114 ath9k_hw_btcoex_bt_stomp(ah, ATH_BTCOEX_STOMP_LOW); 112 ath9k_hw_btcoex_bt_stomp(ah, ATH_BTCOEX_STOMP_LOW);
113
115 ath9k_hw_btcoex_enable(priv->ah); 114 ath9k_hw_btcoex_enable(priv->ah);
116} 115}
117 116
@@ -141,7 +140,8 @@ static void ath_htc_resume_btcoex_work(struct ath9k_htc_priv *priv)
141 140
142 btcoex->bt_priority_cnt = 0; 141 btcoex->bt_priority_cnt = 0;
143 btcoex->bt_priority_time = jiffies; 142 btcoex->bt_priority_time = jiffies;
144 priv->op_flags &= ~(OP_BT_PRIORITY_DETECTED | OP_BT_SCAN); 143 clear_bit(OP_BT_PRIORITY_DETECTED, &priv->op_flags);
144 clear_bit(OP_BT_SCAN, &priv->op_flags);
145 ieee80211_queue_delayed_work(priv->hw, &priv->coex_period_work, 0); 145 ieee80211_queue_delayed_work(priv->hw, &priv->coex_period_work, 0);
146} 146}
147 147
@@ -310,95 +310,3 @@ void ath9k_start_rfkill_poll(struct ath9k_htc_priv *priv)
310 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 310 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
311 wiphy_rfkill_start_polling(priv->hw->wiphy); 311 wiphy_rfkill_start_polling(priv->hw->wiphy);
312} 312}
313
314void ath9k_htc_radio_enable(struct ieee80211_hw *hw)
315{
316 struct ath9k_htc_priv *priv = hw->priv;
317 struct ath_hw *ah = priv->ah;
318 struct ath_common *common = ath9k_hw_common(ah);
319 int ret;
320 u8 cmd_rsp;
321
322 if (!ah->curchan)
323 ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
324
325 /* Reset the HW */
326 ret = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
327 if (ret) {
328 ath_err(common,
329 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
330 ret, ah->curchan->channel);
331 }
332
333 ath9k_cmn_update_txpow(ah, priv->curtxpow, priv->txpowlimit,
334 &priv->curtxpow);
335
336 /* Start RX */
337 WMI_CMD(WMI_START_RECV_CMDID);
338 ath9k_host_rx_init(priv);
339
340 /* Start TX */
341 htc_start(priv->htc);
342 spin_lock_bh(&priv->tx.tx_lock);
343 priv->tx.flags &= ~ATH9K_HTC_OP_TX_QUEUES_STOP;
344 spin_unlock_bh(&priv->tx.tx_lock);
345 ieee80211_wake_queues(hw);
346
347 WMI_CMD(WMI_ENABLE_INTR_CMDID);
348
349 /* Enable LED */
350 ath9k_hw_cfg_output(ah, ah->led_pin,
351 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
352 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
353}
354
355void ath9k_htc_radio_disable(struct ieee80211_hw *hw)
356{
357 struct ath9k_htc_priv *priv = hw->priv;
358 struct ath_hw *ah = priv->ah;
359 struct ath_common *common = ath9k_hw_common(ah);
360 int ret;
361 u8 cmd_rsp;
362
363 ath9k_htc_ps_wakeup(priv);
364
365 /* Disable LED */
366 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
367 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
368
369 WMI_CMD(WMI_DISABLE_INTR_CMDID);
370
371 /* Stop TX */
372 ieee80211_stop_queues(hw);
373 ath9k_htc_tx_drain(priv);
374 WMI_CMD(WMI_DRAIN_TXQ_ALL_CMDID);
375
376 /* Stop RX */
377 WMI_CMD(WMI_STOP_RECV_CMDID);
378
379 /* Clear the WMI event queue */
380 ath9k_wmi_event_drain(priv);
381
382 /*
383 * The MIB counters have to be disabled here,
384 * since the target doesn't do it.
385 */
386 ath9k_hw_disable_mib_counters(ah);
387
388 if (!ah->curchan)
389 ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
390
391 /* Reset the HW */
392 ret = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
393 if (ret) {
394 ath_err(common,
395 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
396 ret, ah->curchan->channel);
397 }
398
399 /* Disable the PHY */
400 ath9k_hw_phy_disable(ah);
401
402 ath9k_htc_ps_restore(priv);
403 ath9k_htc_setpower(priv, ATH9K_PM_FULL_SLEEP);
404}
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_init.c b/drivers/net/wireless/ath/ath9k/htc_drv_init.c
index 25213d521bc2..a035a380d669 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_init.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_init.c
@@ -611,7 +611,7 @@ static int ath9k_init_priv(struct ath9k_htc_priv *priv,
611 struct ath_common *common; 611 struct ath_common *common;
612 int i, ret = 0, csz = 0; 612 int i, ret = 0, csz = 0;
613 613
614 priv->op_flags |= OP_INVALID; 614 set_bit(OP_INVALID, &priv->op_flags);
615 615
616 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL); 616 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
617 if (!ah) 617 if (!ah)
@@ -718,7 +718,7 @@ static void ath9k_set_hw_capab(struct ath9k_htc_priv *priv,
718 718
719 hw->queues = 4; 719 hw->queues = 4;
720 hw->channel_change_time = 5000; 720 hw->channel_change_time = 5000;
721 hw->max_listen_interval = 10; 721 hw->max_listen_interval = 1;
722 722
723 hw->vif_data_size = sizeof(struct ath9k_htc_vif); 723 hw->vif_data_size = sizeof(struct ath9k_htc_vif);
724 hw->sta_data_size = sizeof(struct ath9k_htc_sta); 724 hw->sta_data_size = sizeof(struct ath9k_htc_sta);
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_main.c b/drivers/net/wireless/ath/ath9k/htc_drv_main.c
index abbd6effd60d..374c32ed905a 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_main.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_main.c
@@ -75,14 +75,19 @@ unlock:
75 75
76void ath9k_htc_ps_restore(struct ath9k_htc_priv *priv) 76void ath9k_htc_ps_restore(struct ath9k_htc_priv *priv)
77{ 77{
78 bool reset;
79
78 mutex_lock(&priv->htc_pm_lock); 80 mutex_lock(&priv->htc_pm_lock);
79 if (--priv->ps_usecount != 0) 81 if (--priv->ps_usecount != 0)
80 goto unlock; 82 goto unlock;
81 83
82 if (priv->ps_idle) 84 if (priv->ps_idle) {
85 ath9k_hw_setrxabort(priv->ah, true);
86 ath9k_hw_stopdmarecv(priv->ah, &reset);
83 ath9k_hw_setpower(priv->ah, ATH9K_PM_FULL_SLEEP); 87 ath9k_hw_setpower(priv->ah, ATH9K_PM_FULL_SLEEP);
84 else if (priv->ps_enabled) 88 } else if (priv->ps_enabled) {
85 ath9k_hw_setpower(priv->ah, ATH9K_PM_NETWORK_SLEEP); 89 ath9k_hw_setpower(priv->ah, ATH9K_PM_NETWORK_SLEEP);
90 }
86 91
87unlock: 92unlock:
88 mutex_unlock(&priv->htc_pm_lock); 93 mutex_unlock(&priv->htc_pm_lock);
@@ -250,7 +255,7 @@ static int ath9k_htc_set_channel(struct ath9k_htc_priv *priv,
250 u8 cmd_rsp; 255 u8 cmd_rsp;
251 int ret; 256 int ret;
252 257
253 if (priv->op_flags & OP_INVALID) 258 if (test_bit(OP_INVALID, &priv->op_flags))
254 return -EIO; 259 return -EIO;
255 260
256 fastcc = !!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL); 261 fastcc = !!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL);
@@ -304,7 +309,7 @@ static int ath9k_htc_set_channel(struct ath9k_htc_priv *priv,
304 309
305 htc_start(priv->htc); 310 htc_start(priv->htc);
306 311
307 if (!(priv->op_flags & OP_SCANNING) && 312 if (!test_bit(OP_SCANNING, &priv->op_flags) &&
308 !(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) 313 !(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
309 ath9k_htc_vif_reconfig(priv); 314 ath9k_htc_vif_reconfig(priv);
310 315
@@ -750,7 +755,7 @@ void ath9k_htc_start_ani(struct ath9k_htc_priv *priv)
750 common->ani.shortcal_timer = timestamp; 755 common->ani.shortcal_timer = timestamp;
751 common->ani.checkani_timer = timestamp; 756 common->ani.checkani_timer = timestamp;
752 757
753 priv->op_flags |= OP_ANI_RUNNING; 758 set_bit(OP_ANI_RUNNING, &priv->op_flags);
754 759
755 ieee80211_queue_delayed_work(common->hw, &priv->ani_work, 760 ieee80211_queue_delayed_work(common->hw, &priv->ani_work,
756 msecs_to_jiffies(ATH_ANI_POLLINTERVAL)); 761 msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
@@ -759,7 +764,7 @@ void ath9k_htc_start_ani(struct ath9k_htc_priv *priv)
759void ath9k_htc_stop_ani(struct ath9k_htc_priv *priv) 764void ath9k_htc_stop_ani(struct ath9k_htc_priv *priv)
760{ 765{
761 cancel_delayed_work_sync(&priv->ani_work); 766 cancel_delayed_work_sync(&priv->ani_work);
762 priv->op_flags &= ~OP_ANI_RUNNING; 767 clear_bit(OP_ANI_RUNNING, &priv->op_flags);
763} 768}
764 769
765void ath9k_htc_ani_work(struct work_struct *work) 770void ath9k_htc_ani_work(struct work_struct *work)
@@ -944,7 +949,7 @@ static int ath9k_htc_start(struct ieee80211_hw *hw)
944 ath_dbg(common, CONFIG, 949 ath_dbg(common, CONFIG,
945 "Failed to update capability in target\n"); 950 "Failed to update capability in target\n");
946 951
947 priv->op_flags &= ~OP_INVALID; 952 clear_bit(OP_INVALID, &priv->op_flags);
948 htc_start(priv->htc); 953 htc_start(priv->htc);
949 954
950 spin_lock_bh(&priv->tx.tx_lock); 955 spin_lock_bh(&priv->tx.tx_lock);
@@ -973,7 +978,7 @@ static void ath9k_htc_stop(struct ieee80211_hw *hw)
973 978
974 mutex_lock(&priv->mutex); 979 mutex_lock(&priv->mutex);
975 980
976 if (priv->op_flags & OP_INVALID) { 981 if (test_bit(OP_INVALID, &priv->op_flags)) {
977 ath_dbg(common, ANY, "Device not present\n"); 982 ath_dbg(common, ANY, "Device not present\n");
978 mutex_unlock(&priv->mutex); 983 mutex_unlock(&priv->mutex);
979 return; 984 return;
@@ -1015,7 +1020,7 @@ static void ath9k_htc_stop(struct ieee80211_hw *hw)
1015 ath9k_htc_ps_restore(priv); 1020 ath9k_htc_ps_restore(priv);
1016 ath9k_htc_setpower(priv, ATH9K_PM_FULL_SLEEP); 1021 ath9k_htc_setpower(priv, ATH9K_PM_FULL_SLEEP);
1017 1022
1018 priv->op_flags |= OP_INVALID; 1023 set_bit(OP_INVALID, &priv->op_flags);
1019 1024
1020 ath_dbg(common, CONFIG, "Driver halt\n"); 1025 ath_dbg(common, CONFIG, "Driver halt\n");
1021 mutex_unlock(&priv->mutex); 1026 mutex_unlock(&priv->mutex);
@@ -1105,7 +1110,7 @@ static int ath9k_htc_add_interface(struct ieee80211_hw *hw,
1105 ath9k_htc_set_opmode(priv); 1110 ath9k_htc_set_opmode(priv);
1106 1111
1107 if ((priv->ah->opmode == NL80211_IFTYPE_AP) && 1112 if ((priv->ah->opmode == NL80211_IFTYPE_AP) &&
1108 !(priv->op_flags & OP_ANI_RUNNING)) { 1113 !test_bit(OP_ANI_RUNNING, &priv->op_flags)) {
1109 ath9k_hw_set_tsfadjust(priv->ah, 1); 1114 ath9k_hw_set_tsfadjust(priv->ah, 1);
1110 ath9k_htc_start_ani(priv); 1115 ath9k_htc_start_ani(priv);
1111 } 1116 }
@@ -1178,24 +1183,20 @@ static int ath9k_htc_config(struct ieee80211_hw *hw, u32 changed)
1178 struct ath9k_htc_priv *priv = hw->priv; 1183 struct ath9k_htc_priv *priv = hw->priv;
1179 struct ath_common *common = ath9k_hw_common(priv->ah); 1184 struct ath_common *common = ath9k_hw_common(priv->ah);
1180 struct ieee80211_conf *conf = &hw->conf; 1185 struct ieee80211_conf *conf = &hw->conf;
1186 bool chip_reset = false;
1187 int ret = 0;
1181 1188
1182 mutex_lock(&priv->mutex); 1189 mutex_lock(&priv->mutex);
1190 ath9k_htc_ps_wakeup(priv);
1183 1191
1184 if (changed & IEEE80211_CONF_CHANGE_IDLE) { 1192 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
1185 bool enable_radio = false;
1186 bool idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1187
1188 mutex_lock(&priv->htc_pm_lock); 1193 mutex_lock(&priv->htc_pm_lock);
1189 if (!idle && priv->ps_idle)
1190 enable_radio = true;
1191 priv->ps_idle = idle;
1192 mutex_unlock(&priv->htc_pm_lock);
1193 1194
1194 if (enable_radio) { 1195 priv->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1195 ath_dbg(common, CONFIG, "not-idle: enabling radio\n"); 1196 if (priv->ps_idle)
1196 ath9k_htc_setpower(priv, ATH9K_PM_AWAKE); 1197 chip_reset = true;
1197 ath9k_htc_radio_enable(hw); 1198
1198 } 1199 mutex_unlock(&priv->htc_pm_lock);
1199 } 1200 }
1200 1201
1201 /* 1202 /*
@@ -1210,7 +1211,7 @@ static int ath9k_htc_config(struct ieee80211_hw *hw, u32 changed)
1210 ath9k_htc_remove_monitor_interface(priv); 1211 ath9k_htc_remove_monitor_interface(priv);
1211 } 1212 }
1212 1213
1213 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { 1214 if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || chip_reset) {
1214 struct ieee80211_channel *curchan = hw->conf.channel; 1215 struct ieee80211_channel *curchan = hw->conf.channel;
1215 int pos = curchan->hw_value; 1216 int pos = curchan->hw_value;
1216 1217
@@ -1223,8 +1224,8 @@ static int ath9k_htc_config(struct ieee80211_hw *hw, u32 changed)
1223 1224
1224 if (ath9k_htc_set_channel(priv, hw, &priv->ah->channels[pos]) < 0) { 1225 if (ath9k_htc_set_channel(priv, hw, &priv->ah->channels[pos]) < 0) {
1225 ath_err(common, "Unable to set channel\n"); 1226 ath_err(common, "Unable to set channel\n");
1226 mutex_unlock(&priv->mutex); 1227 ret = -EINVAL;
1227 return -EINVAL; 1228 goto out;
1228 } 1229 }
1229 1230
1230 } 1231 }
@@ -1246,21 +1247,10 @@ static int ath9k_htc_config(struct ieee80211_hw *hw, u32 changed)
1246 priv->txpowlimit, &priv->curtxpow); 1247 priv->txpowlimit, &priv->curtxpow);
1247 } 1248 }
1248 1249
1249 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
1250 mutex_lock(&priv->htc_pm_lock);
1251 if (!priv->ps_idle) {
1252 mutex_unlock(&priv->htc_pm_lock);
1253 goto out;
1254 }
1255 mutex_unlock(&priv->htc_pm_lock);
1256
1257 ath_dbg(common, CONFIG, "idle: disabling radio\n");
1258 ath9k_htc_radio_disable(hw);
1259 }
1260
1261out: 1250out:
1251 ath9k_htc_ps_restore(priv);
1262 mutex_unlock(&priv->mutex); 1252 mutex_unlock(&priv->mutex);
1263 return 0; 1253 return ret;
1264} 1254}
1265 1255
1266#define SUPPORTED_FILTERS \ 1256#define SUPPORTED_FILTERS \
@@ -1285,7 +1275,7 @@ static void ath9k_htc_configure_filter(struct ieee80211_hw *hw,
1285 changed_flags &= SUPPORTED_FILTERS; 1275 changed_flags &= SUPPORTED_FILTERS;
1286 *total_flags &= SUPPORTED_FILTERS; 1276 *total_flags &= SUPPORTED_FILTERS;
1287 1277
1288 if (priv->op_flags & OP_INVALID) { 1278 if (test_bit(OP_INVALID, &priv->op_flags)) {
1289 ath_dbg(ath9k_hw_common(priv->ah), ANY, 1279 ath_dbg(ath9k_hw_common(priv->ah), ANY,
1290 "Unable to configure filter on invalid state\n"); 1280 "Unable to configure filter on invalid state\n");
1291 mutex_unlock(&priv->mutex); 1281 mutex_unlock(&priv->mutex);
@@ -1516,7 +1506,7 @@ static void ath9k_htc_bss_info_changed(struct ieee80211_hw *hw,
1516 ath_dbg(common, CONFIG, "Beacon enabled for BSS: %pM\n", 1506 ath_dbg(common, CONFIG, "Beacon enabled for BSS: %pM\n",
1517 bss_conf->bssid); 1507 bss_conf->bssid);
1518 ath9k_htc_set_tsfadjust(priv, vif); 1508 ath9k_htc_set_tsfadjust(priv, vif);
1519 priv->op_flags |= OP_ENABLE_BEACON; 1509 set_bit(OP_ENABLE_BEACON, &priv->op_flags);
1520 ath9k_htc_beacon_config(priv, vif); 1510 ath9k_htc_beacon_config(priv, vif);
1521 } 1511 }
1522 1512
@@ -1529,7 +1519,7 @@ static void ath9k_htc_bss_info_changed(struct ieee80211_hw *hw,
1529 ath_dbg(common, CONFIG, 1519 ath_dbg(common, CONFIG,
1530 "Beacon disabled for BSS: %pM\n", 1520 "Beacon disabled for BSS: %pM\n",
1531 bss_conf->bssid); 1521 bss_conf->bssid);
1532 priv->op_flags &= ~OP_ENABLE_BEACON; 1522 clear_bit(OP_ENABLE_BEACON, &priv->op_flags);
1533 ath9k_htc_beacon_config(priv, vif); 1523 ath9k_htc_beacon_config(priv, vif);
1534 } 1524 }
1535 } 1525 }
@@ -1542,7 +1532,7 @@ static void ath9k_htc_bss_info_changed(struct ieee80211_hw *hw,
1542 (priv->nvifs == 1) && 1532 (priv->nvifs == 1) &&
1543 (priv->num_ap_vif == 1) && 1533 (priv->num_ap_vif == 1) &&
1544 (vif->type == NL80211_IFTYPE_AP)) { 1534 (vif->type == NL80211_IFTYPE_AP)) {
1545 priv->op_flags |= OP_TSF_RESET; 1535 set_bit(OP_TSF_RESET, &priv->op_flags);
1546 } 1536 }
1547 ath_dbg(common, CONFIG, 1537 ath_dbg(common, CONFIG,
1548 "Beacon interval changed for BSS: %pM\n", 1538 "Beacon interval changed for BSS: %pM\n",
@@ -1654,7 +1644,7 @@ static void ath9k_htc_sw_scan_start(struct ieee80211_hw *hw)
1654 1644
1655 mutex_lock(&priv->mutex); 1645 mutex_lock(&priv->mutex);
1656 spin_lock_bh(&priv->beacon_lock); 1646 spin_lock_bh(&priv->beacon_lock);
1657 priv->op_flags |= OP_SCANNING; 1647 set_bit(OP_SCANNING, &priv->op_flags);
1658 spin_unlock_bh(&priv->beacon_lock); 1648 spin_unlock_bh(&priv->beacon_lock);
1659 cancel_work_sync(&priv->ps_work); 1649 cancel_work_sync(&priv->ps_work);
1660 ath9k_htc_stop_ani(priv); 1650 ath9k_htc_stop_ani(priv);
@@ -1667,7 +1657,7 @@ static void ath9k_htc_sw_scan_complete(struct ieee80211_hw *hw)
1667 1657
1668 mutex_lock(&priv->mutex); 1658 mutex_lock(&priv->mutex);
1669 spin_lock_bh(&priv->beacon_lock); 1659 spin_lock_bh(&priv->beacon_lock);
1670 priv->op_flags &= ~OP_SCANNING; 1660 clear_bit(OP_SCANNING, &priv->op_flags);
1671 spin_unlock_bh(&priv->beacon_lock); 1661 spin_unlock_bh(&priv->beacon_lock);
1672 ath9k_htc_ps_wakeup(priv); 1662 ath9k_htc_ps_wakeup(priv);
1673 ath9k_htc_vif_reconfig(priv); 1663 ath9k_htc_vif_reconfig(priv);
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c b/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c
index 3e40a6461512..47e61d0da33b 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c
@@ -916,7 +916,7 @@ void ath9k_host_rx_init(struct ath9k_htc_priv *priv)
916{ 916{
917 ath9k_hw_rxena(priv->ah); 917 ath9k_hw_rxena(priv->ah);
918 ath9k_htc_opmode_init(priv); 918 ath9k_htc_opmode_init(priv);
919 ath9k_hw_startpcureceive(priv->ah, (priv->op_flags & OP_SCANNING)); 919 ath9k_hw_startpcureceive(priv->ah, test_bit(OP_SCANNING, &priv->op_flags));
920 priv->rx.last_rssi = ATH_RSSI_DUMMY_MARKER; 920 priv->rx.last_rssi = ATH_RSSI_DUMMY_MARKER;
921} 921}
922 922
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index 995ca8e1302e..c1659d079513 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -342,6 +342,9 @@ static void ath9k_hw_read_revisions(struct ath_hw *ah)
342 val = REG_READ(ah, AR_SREV); 342 val = REG_READ(ah, AR_SREV);
343 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 343 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
344 return; 344 return;
345 case AR9300_DEVID_QCA955X:
346 ah->hw_version.macVersion = AR_SREV_VERSION_9550;
347 return;
345 } 348 }
346 349
347 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; 350 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
@@ -390,14 +393,6 @@ static void ath9k_hw_disablepcie(struct ath_hw *ah)
390 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 393 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
391} 394}
392 395
393static void ath9k_hw_aspm_init(struct ath_hw *ah)
394{
395 struct ath_common *common = ath9k_hw_common(ah);
396
397 if (common->bus_ops->aspm_init)
398 common->bus_ops->aspm_init(common);
399}
400
401/* This should work for all families including legacy */ 396/* This should work for all families including legacy */
402static bool ath9k_hw_chip_test(struct ath_hw *ah) 397static bool ath9k_hw_chip_test(struct ath_hw *ah)
403{ 398{
@@ -654,6 +649,7 @@ static int __ath9k_hw_init(struct ath_hw *ah)
654 case AR_SREV_VERSION_9485: 649 case AR_SREV_VERSION_9485:
655 case AR_SREV_VERSION_9340: 650 case AR_SREV_VERSION_9340:
656 case AR_SREV_VERSION_9462: 651 case AR_SREV_VERSION_9462:
652 case AR_SREV_VERSION_9550:
657 break; 653 break;
658 default: 654 default:
659 ath_err(common, 655 ath_err(common,
@@ -663,7 +659,7 @@ static int __ath9k_hw_init(struct ath_hw *ah)
663 } 659 }
664 660
665 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) || 661 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
666 AR_SREV_9330(ah)) 662 AR_SREV_9330(ah) || AR_SREV_9550(ah))
667 ah->is_pciexpress = false; 663 ah->is_pciexpress = false;
668 664
669 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 665 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
@@ -693,9 +689,6 @@ static int __ath9k_hw_init(struct ath_hw *ah)
693 if (r) 689 if (r)
694 return r; 690 return r;
695 691
696 if (ah->is_pciexpress)
697 ath9k_hw_aspm_init(ah);
698
699 r = ath9k_hw_init_macaddr(ah); 692 r = ath9k_hw_init_macaddr(ah);
700 if (r) { 693 if (r) {
701 ath_err(common, "Failed to initialize MAC address\n"); 694 ath_err(common, "Failed to initialize MAC address\n");
@@ -738,6 +731,7 @@ int ath9k_hw_init(struct ath_hw *ah)
738 case AR9300_DEVID_AR9485_PCIE: 731 case AR9300_DEVID_AR9485_PCIE:
739 case AR9300_DEVID_AR9330: 732 case AR9300_DEVID_AR9330:
740 case AR9300_DEVID_AR9340: 733 case AR9300_DEVID_AR9340:
734 case AR9300_DEVID_QCA955X:
741 case AR9300_DEVID_AR9580: 735 case AR9300_DEVID_AR9580:
742 case AR9300_DEVID_AR9462: 736 case AR9300_DEVID_AR9462:
743 break; 737 break;
@@ -876,7 +870,7 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
876 /* program BB PLL phase_shift */ 870 /* program BB PLL phase_shift */
877 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 871 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
878 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1); 872 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
879 } else if (AR_SREV_9340(ah)) { 873 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
880 u32 regval, pll2_divint, pll2_divfrac, refdiv; 874 u32 regval, pll2_divint, pll2_divfrac, refdiv;
881 875
882 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); 876 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
@@ -890,9 +884,15 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
890 pll2_divfrac = 0x1eb85; 884 pll2_divfrac = 0x1eb85;
891 refdiv = 3; 885 refdiv = 3;
892 } else { 886 } else {
893 pll2_divint = 88; 887 if (AR_SREV_9340(ah)) {
894 pll2_divfrac = 0; 888 pll2_divint = 88;
895 refdiv = 5; 889 pll2_divfrac = 0;
890 refdiv = 5;
891 } else {
892 pll2_divint = 0x11;
893 pll2_divfrac = 0x26666;
894 refdiv = 1;
895 }
896 } 896 }
897 897
898 regval = REG_READ(ah, AR_PHY_PLL_MODE); 898 regval = REG_READ(ah, AR_PHY_PLL_MODE);
@@ -905,8 +905,12 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
905 udelay(100); 905 udelay(100);
906 906
907 regval = REG_READ(ah, AR_PHY_PLL_MODE); 907 regval = REG_READ(ah, AR_PHY_PLL_MODE);
908 regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) | 908 if (AR_SREV_9340(ah))
909 (0x4 << 26) | (0x18 << 19); 909 regval = (regval & 0x80071fff) | (0x1 << 30) |
910 (0x1 << 13) | (0x4 << 26) | (0x18 << 19);
911 else
912 regval = (regval & 0x80071fff) | (0x3 << 30) |
913 (0x1 << 13) | (0x4 << 26) | (0x60 << 19);
910 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 914 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
911 REG_WRITE(ah, AR_PHY_PLL_MODE, 915 REG_WRITE(ah, AR_PHY_PLL_MODE,
912 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff); 916 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
@@ -917,7 +921,8 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
917 921
918 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 922 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
919 923
920 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah)) 924 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
925 AR_SREV_9550(ah))
921 udelay(1000); 926 udelay(1000);
922 927
923 /* Switch the core clock for ar9271 to 117Mhz */ 928 /* Switch the core clock for ar9271 to 117Mhz */
@@ -930,7 +935,7 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
930 935
931 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 936 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
932 937
933 if (AR_SREV_9340(ah)) { 938 if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
934 if (ah->is_clk_25mhz) { 939 if (ah->is_clk_25mhz) {
935 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1); 940 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
936 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7); 941 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
@@ -954,7 +959,7 @@ static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
954 AR_IMR_RXORN | 959 AR_IMR_RXORN |
955 AR_IMR_BCNMISC; 960 AR_IMR_BCNMISC;
956 961
957 if (AR_SREV_9340(ah)) 962 if (AR_SREV_9340(ah) || AR_SREV_9550(ah))
958 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL; 963 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
959 964
960 if (AR_SREV_9300_20_OR_LATER(ah)) { 965 if (AR_SREV_9300_20_OR_LATER(ah)) {
@@ -1371,6 +1376,9 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1371 } 1376 }
1372 } 1377 }
1373 1378
1379 if (ath9k_hw_mci_is_enabled(ah))
1380 ar9003_mci_check_gpm_offset(ah);
1381
1374 REG_WRITE(ah, AR_RTC_RC, rst_flags); 1382 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1375 1383
1376 REGWRITE_BUFFER_FLUSH(ah); 1384 REGWRITE_BUFFER_FLUSH(ah);
@@ -1455,9 +1463,6 @@ static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1455 break; 1463 break;
1456 } 1464 }
1457 1465
1458 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
1459 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
1460
1461 return ret; 1466 return ret;
1462} 1467}
1463 1468
@@ -1733,8 +1738,8 @@ static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
1733 ath9k_hw_loadnf(ah, ah->curchan); 1738 ath9k_hw_loadnf(ah, ah->curchan);
1734 ath9k_hw_start_nfcal(ah, true); 1739 ath9k_hw_start_nfcal(ah, true);
1735 1740
1736 if ((ah->caps.hw_caps & ATH9K_HW_CAP_MCI) && ar9003_mci_is_ready(ah)) 1741 if (ath9k_hw_mci_is_enabled(ah))
1737 ar9003_mci_2g5g_switch(ah, true); 1742 ar9003_mci_2g5g_switch(ah, false);
1738 1743
1739 if (AR_SREV_9271(ah)) 1744 if (AR_SREV_9271(ah))
1740 ar9002_hw_load_ani_reg(ah, chan); 1745 ar9002_hw_load_ani_reg(ah, chan);
@@ -1754,10 +1759,9 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1754 u64 tsf = 0; 1759 u64 tsf = 0;
1755 int i, r; 1760 int i, r;
1756 bool start_mci_reset = false; 1761 bool start_mci_reset = false;
1757 bool mci = !!(ah->caps.hw_caps & ATH9K_HW_CAP_MCI);
1758 bool save_fullsleep = ah->chip_fullsleep; 1762 bool save_fullsleep = ah->chip_fullsleep;
1759 1763
1760 if (mci) { 1764 if (ath9k_hw_mci_is_enabled(ah)) {
1761 start_mci_reset = ar9003_mci_start_reset(ah, chan); 1765 start_mci_reset = ar9003_mci_start_reset(ah, chan);
1762 if (start_mci_reset) 1766 if (start_mci_reset)
1763 return 0; 1767 return 0;
@@ -1786,7 +1790,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1786 return r; 1790 return r;
1787 } 1791 }
1788 1792
1789 if (mci) 1793 if (ath9k_hw_mci_is_enabled(ah))
1790 ar9003_mci_stop_bt(ah, save_fullsleep); 1794 ar9003_mci_stop_bt(ah, save_fullsleep);
1791 1795
1792 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); 1796 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
@@ -1844,7 +1848,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1844 if (r) 1848 if (r)
1845 return r; 1849 return r;
1846 1850
1847 if (mci) 1851 if (ath9k_hw_mci_is_enabled(ah))
1848 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep); 1852 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1849 1853
1850 /* 1854 /*
@@ -1939,7 +1943,8 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1939 1943
1940 ath9k_hw_set_dma(ah); 1944 ath9k_hw_set_dma(ah);
1941 1945
1942 REG_WRITE(ah, AR_OBS, 8); 1946 if (!ath9k_hw_mci_is_enabled(ah))
1947 REG_WRITE(ah, AR_OBS, 8);
1943 1948
1944 if (ah->config.rx_intr_mitigation) { 1949 if (ah->config.rx_intr_mitigation) {
1945 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); 1950 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
@@ -1960,10 +1965,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1960 if (!ath9k_hw_init_cal(ah, chan)) 1965 if (!ath9k_hw_init_cal(ah, chan))
1961 return -EIO; 1966 return -EIO;
1962 1967
1963 ath9k_hw_loadnf(ah, chan); 1968 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata))
1964 ath9k_hw_start_nfcal(ah, true);
1965
1966 if (mci && ar9003_mci_end_reset(ah, chan, caldata))
1967 return -EIO; 1969 return -EIO;
1968 1970
1969 ENABLE_REGWRITE_BUFFER(ah); 1971 ENABLE_REGWRITE_BUFFER(ah);
@@ -1998,7 +2000,8 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1998 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 2000 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1999 } 2001 }
2000#ifdef __BIG_ENDIAN 2002#ifdef __BIG_ENDIAN
2001 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah)) 2003 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) ||
2004 AR_SREV_9550(ah))
2002 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0); 2005 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
2003 else 2006 else
2004 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 2007 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
@@ -2008,9 +2011,12 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2008 if (ath9k_hw_btcoex_is_enabled(ah)) 2011 if (ath9k_hw_btcoex_is_enabled(ah))
2009 ath9k_hw_btcoex_enable(ah); 2012 ath9k_hw_btcoex_enable(ah);
2010 2013
2011 if (mci) 2014 if (ath9k_hw_mci_is_enabled(ah))
2012 ar9003_mci_check_bt(ah); 2015 ar9003_mci_check_bt(ah);
2013 2016
2017 ath9k_hw_loadnf(ah, chan);
2018 ath9k_hw_start_nfcal(ah, true);
2019
2014 if (AR_SREV_9300_20_OR_LATER(ah)) { 2020 if (AR_SREV_9300_20_OR_LATER(ah)) {
2015 ar9003_hw_bb_watchdog_config(ah); 2021 ar9003_hw_bb_watchdog_config(ah);
2016 2022
@@ -2031,39 +2037,35 @@ EXPORT_SYMBOL(ath9k_hw_reset);
2031 * Notify Power Mgt is disabled in self-generated frames. 2037 * Notify Power Mgt is disabled in self-generated frames.
2032 * If requested, force chip to sleep. 2038 * If requested, force chip to sleep.
2033 */ 2039 */
2034static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip) 2040static void ath9k_set_power_sleep(struct ath_hw *ah)
2035{ 2041{
2036 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2042 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2037 if (setChip) {
2038 if (AR_SREV_9462(ah)) {
2039 REG_WRITE(ah, AR_TIMER_MODE,
2040 REG_READ(ah, AR_TIMER_MODE) & 0xFFFFFF00);
2041 REG_WRITE(ah, AR_NDP2_TIMER_MODE, REG_READ(ah,
2042 AR_NDP2_TIMER_MODE) & 0xFFFFFF00);
2043 REG_WRITE(ah, AR_SLP32_INC,
2044 REG_READ(ah, AR_SLP32_INC) & 0xFFF00000);
2045 /* xxx Required for WLAN only case ? */
2046 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
2047 udelay(100);
2048 }
2049 2043
2050 /* 2044 if (AR_SREV_9462(ah)) {
2051 * Clear the RTC force wake bit to allow the 2045 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff);
2052 * mac to go to sleep. 2046 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff);
2053 */ 2047 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff);
2054 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 2048 /* xxx Required for WLAN only case ? */
2049 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
2050 udelay(100);
2051 }
2055 2052
2056 if (AR_SREV_9462(ah)) 2053 /*
2057 udelay(100); 2054 * Clear the RTC force wake bit to allow the
2055 * mac to go to sleep.
2056 */
2057 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
2058 2058
2059 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 2059 if (ath9k_hw_mci_is_enabled(ah))
2060 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 2060 udelay(100);
2061 2061
2062 /* Shutdown chip. Active low */ 2062 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
2063 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) { 2063 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2064 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN); 2064
2065 udelay(2); 2065 /* Shutdown chip. Active low */
2066 } 2066 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
2067 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
2068 udelay(2);
2067 } 2069 }
2068 2070
2069 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */ 2071 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
@@ -2076,44 +2078,38 @@ static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2076 * frames. If request, set power mode of chip to 2078 * frames. If request, set power mode of chip to
2077 * auto/normal. Duration in units of 128us (1/8 TU). 2079 * auto/normal. Duration in units of 128us (1/8 TU).
2078 */ 2080 */
2079static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip) 2081static void ath9k_set_power_network_sleep(struct ath_hw *ah)
2080{ 2082{
2081 u32 val; 2083 struct ath9k_hw_capabilities *pCap = &ah->caps;
2082 2084
2083 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2085 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2084 if (setChip) {
2085 struct ath9k_hw_capabilities *pCap = &ah->caps;
2086 2086
2087 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 2087 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2088 /* Set WakeOnInterrupt bit; clear ForceWake bit */ 2088 /* Set WakeOnInterrupt bit; clear ForceWake bit */
2089 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 2089 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2090 AR_RTC_FORCE_WAKE_ON_INT); 2090 AR_RTC_FORCE_WAKE_ON_INT);
2091 } else { 2091 } else {
2092 2092
2093 /* When chip goes into network sleep, it could be waken 2093 /* When chip goes into network sleep, it could be waken
2094 * up by MCI_INT interrupt caused by BT's HW messages 2094 * up by MCI_INT interrupt caused by BT's HW messages
2095 * (LNA_xxx, CONT_xxx) which chould be in a very fast 2095 * (LNA_xxx, CONT_xxx) which chould be in a very fast
2096 * rate (~100us). This will cause chip to leave and 2096 * rate (~100us). This will cause chip to leave and
2097 * re-enter network sleep mode frequently, which in 2097 * re-enter network sleep mode frequently, which in
2098 * consequence will have WLAN MCI HW to generate lots of 2098 * consequence will have WLAN MCI HW to generate lots of
2099 * SYS_WAKING and SYS_SLEEPING messages which will make 2099 * SYS_WAKING and SYS_SLEEPING messages which will make
2100 * BT CPU to busy to process. 2100 * BT CPU to busy to process.
2101 */ 2101 */
2102 if (AR_SREV_9462(ah)) { 2102 if (ath9k_hw_mci_is_enabled(ah))
2103 val = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_EN) & 2103 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
2104 ~AR_MCI_INTERRUPT_RX_HW_MSG_MASK; 2104 AR_MCI_INTERRUPT_RX_HW_MSG_MASK);
2105 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, val); 2105 /*
2106 } 2106 * Clear the RTC force wake bit to allow the
2107 /* 2107 * mac to go to sleep.
2108 * Clear the RTC force wake bit to allow the 2108 */
2109 * mac to go to sleep. 2109 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
2110 */ 2110
2111 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, 2111 if (ath9k_hw_mci_is_enabled(ah))
2112 AR_RTC_FORCE_WAKE_EN); 2112 udelay(30);
2113
2114 if (AR_SREV_9462(ah))
2115 udelay(30);
2116 }
2117 } 2113 }
2118 2114
2119 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */ 2115 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
@@ -2121,7 +2117,7 @@ static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2121 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 2117 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
2122} 2118}
2123 2119
2124static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip) 2120static bool ath9k_hw_set_power_awake(struct ath_hw *ah)
2125{ 2121{
2126 u32 val; 2122 u32 val;
2127 int i; 2123 int i;
@@ -2132,37 +2128,38 @@ static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2132 udelay(10); 2128 udelay(10);
2133 } 2129 }
2134 2130
2135 if (setChip) { 2131 if ((REG_READ(ah, AR_RTC_STATUS) &
2136 if ((REG_READ(ah, AR_RTC_STATUS) & 2132 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2137 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { 2133 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
2138 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 2134 return false;
2139 return false;
2140 }
2141 if (!AR_SREV_9300_20_OR_LATER(ah))
2142 ath9k_hw_init_pll(ah, NULL);
2143 } 2135 }
2144 if (AR_SREV_9100(ah)) 2136 if (!AR_SREV_9300_20_OR_LATER(ah))
2145 REG_SET_BIT(ah, AR_RTC_RESET, 2137 ath9k_hw_init_pll(ah, NULL);
2146 AR_RTC_RESET_EN); 2138 }
2139 if (AR_SREV_9100(ah))
2140 REG_SET_BIT(ah, AR_RTC_RESET,
2141 AR_RTC_RESET_EN);
2142
2143 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2144 AR_RTC_FORCE_WAKE_EN);
2145 udelay(50);
2146
2147 if (ath9k_hw_mci_is_enabled(ah))
2148 ar9003_mci_set_power_awake(ah);
2147 2149
2150 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2151 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2152 if (val == AR_RTC_STATUS_ON)
2153 break;
2154 udelay(50);
2148 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2155 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2149 AR_RTC_FORCE_WAKE_EN); 2156 AR_RTC_FORCE_WAKE_EN);
2150 udelay(50); 2157 }
2151 2158 if (i == 0) {
2152 for (i = POWER_UP_TIME / 50; i > 0; i--) { 2159 ath_err(ath9k_hw_common(ah),
2153 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; 2160 "Failed to wakeup in %uus\n",
2154 if (val == AR_RTC_STATUS_ON) 2161 POWER_UP_TIME / 20);
2155 break; 2162 return false;
2156 udelay(50);
2157 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2158 AR_RTC_FORCE_WAKE_EN);
2159 }
2160 if (i == 0) {
2161 ath_err(ath9k_hw_common(ah),
2162 "Failed to wakeup in %uus\n",
2163 POWER_UP_TIME / 20);
2164 return false;
2165 }
2166 } 2163 }
2167 2164
2168 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2165 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
@@ -2173,7 +2170,7 @@ static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2173bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) 2170bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2174{ 2171{
2175 struct ath_common *common = ath9k_hw_common(ah); 2172 struct ath_common *common = ath9k_hw_common(ah);
2176 int status = true, setChip = true; 2173 int status = true;
2177 static const char *modes[] = { 2174 static const char *modes[] = {
2178 "AWAKE", 2175 "AWAKE",
2179 "FULL-SLEEP", 2176 "FULL-SLEEP",
@@ -2189,25 +2186,17 @@ bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2189 2186
2190 switch (mode) { 2187 switch (mode) {
2191 case ATH9K_PM_AWAKE: 2188 case ATH9K_PM_AWAKE:
2192 status = ath9k_hw_set_power_awake(ah, setChip); 2189 status = ath9k_hw_set_power_awake(ah);
2193
2194 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
2195 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
2196
2197 break; 2190 break;
2198 case ATH9K_PM_FULL_SLEEP: 2191 case ATH9K_PM_FULL_SLEEP:
2199 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI) 2192 if (ath9k_hw_mci_is_enabled(ah))
2200 ar9003_mci_set_full_sleep(ah); 2193 ar9003_mci_set_full_sleep(ah);
2201 2194
2202 ath9k_set_power_sleep(ah, setChip); 2195 ath9k_set_power_sleep(ah);
2203 ah->chip_fullsleep = true; 2196 ah->chip_fullsleep = true;
2204 break; 2197 break;
2205 case ATH9K_PM_NETWORK_SLEEP: 2198 case ATH9K_PM_NETWORK_SLEEP:
2206 2199 ath9k_set_power_network_sleep(ah);
2207 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
2208 REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
2209
2210 ath9k_set_power_network_sleep(ah, setChip);
2211 break; 2200 break;
2212 default: 2201 default:
2213 ath_err(common, "Unknown power mode %u\n", mode); 2202 ath_err(common, "Unknown power mode %u\n", mode);
@@ -2777,6 +2766,9 @@ EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2777 2766
2778bool ath9k_hw_phy_disable(struct ath_hw *ah) 2767bool ath9k_hw_phy_disable(struct ath_hw *ah)
2779{ 2768{
2769 if (ath9k_hw_mci_is_enabled(ah))
2770 ar9003_mci_bt_gain_ctrl(ah);
2771
2780 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 2772 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2781 return false; 2773 return false;
2782 2774
@@ -3162,6 +3154,7 @@ static struct {
3162 { AR_SREV_VERSION_9340, "9340" }, 3154 { AR_SREV_VERSION_9340, "9340" },
3163 { AR_SREV_VERSION_9485, "9485" }, 3155 { AR_SREV_VERSION_9485, "9485" },
3164 { AR_SREV_VERSION_9462, "9462" }, 3156 { AR_SREV_VERSION_9462, "9462" },
3157 { AR_SREV_VERSION_9550, "9550" },
3165}; 3158};
3166 3159
3167/* For devices with external radios */ 3160/* For devices with external radios */
diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
index b620c557c2a6..26da1732978d 100644
--- a/drivers/net/wireless/ath/ath9k/hw.h
+++ b/drivers/net/wireless/ath/ath9k/hw.h
@@ -48,6 +48,7 @@
48#define AR9300_DEVID_AR9580 0x0033 48#define AR9300_DEVID_AR9580 0x0033
49#define AR9300_DEVID_AR9462 0x0034 49#define AR9300_DEVID_AR9462 0x0034
50#define AR9300_DEVID_AR9330 0x0035 50#define AR9300_DEVID_AR9330 0x0035
51#define AR9300_DEVID_QCA955X 0x0038
51 52
52#define AR5416_AR9100_DEVID 0x000b 53#define AR5416_AR9100_DEVID 0x000b
53 54
@@ -818,13 +819,13 @@ struct ath_hw {
818 struct ar5416IniArray iniModesFastClock; 819 struct ar5416IniArray iniModesFastClock;
819 struct ar5416IniArray iniAdditional; 820 struct ar5416IniArray iniAdditional;
820 struct ar5416IniArray iniModesRxGain; 821 struct ar5416IniArray iniModesRxGain;
822 struct ar5416IniArray ini_modes_rx_gain_bounds;
821 struct ar5416IniArray iniModesTxGain; 823 struct ar5416IniArray iniModesTxGain;
822 struct ar5416IniArray iniCckfirNormal; 824 struct ar5416IniArray iniCckfirNormal;
823 struct ar5416IniArray iniCckfirJapan2484; 825 struct ar5416IniArray iniCckfirJapan2484;
824 struct ar5416IniArray ini_japan2484; 826 struct ar5416IniArray ini_japan2484;
825 struct ar5416IniArray iniModes_9271_ANI_reg; 827 struct ar5416IniArray iniModes_9271_ANI_reg;
826 struct ar5416IniArray ini_radio_post_sys2ant; 828 struct ar5416IniArray ini_radio_post_sys2ant;
827 struct ar5416IniArray ini_BTCOEX_MAX_TXPWR;
828 829
829 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT]; 830 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
830 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT]; 831 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
@@ -1020,16 +1021,8 @@ void ar9002_hw_attach_ops(struct ath_hw *ah);
1020void ar9003_hw_attach_ops(struct ath_hw *ah); 1021void ar9003_hw_attach_ops(struct ath_hw *ah);
1021 1022
1022void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan); 1023void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan);
1023/* 1024
1024 * ANI work can be shared between all families but a next
1025 * generation implementation of ANI will be used only for AR9003 only
1026 * for now as the other families still need to be tested with the same
1027 * next generation ANI. Feel free to start testing it though for the
1028 * older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani.
1029 */
1030extern int modparam_force_new_ani;
1031void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning); 1025void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning);
1032void ath9k_hw_proc_mib_event(struct ath_hw *ah);
1033void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan); 1026void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan);
1034 1027
1035#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 1028#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
@@ -1037,6 +1030,12 @@ static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah)
1037{ 1030{
1038 return ah->btcoex_hw.enabled; 1031 return ah->btcoex_hw.enabled;
1039} 1032}
1033static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah)
1034{
1035 return ah->common.btcoex_enabled &&
1036 (ah->caps.hw_caps & ATH9K_HW_CAP_MCI);
1037
1038}
1040void ath9k_hw_btcoex_enable(struct ath_hw *ah); 1039void ath9k_hw_btcoex_enable(struct ath_hw *ah);
1041static inline enum ath_btcoex_scheme 1040static inline enum ath_btcoex_scheme
1042ath9k_hw_get_btcoex_scheme(struct ath_hw *ah) 1041ath9k_hw_get_btcoex_scheme(struct ath_hw *ah)
@@ -1048,6 +1047,10 @@ static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah)
1048{ 1047{
1049 return false; 1048 return false;
1050} 1049}
1050static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah)
1051{
1052 return false;
1053}
1051static inline void ath9k_hw_btcoex_enable(struct ath_hw *ah) 1054static inline void ath9k_hw_btcoex_enable(struct ath_hw *ah)
1052{ 1055{
1053} 1056}
diff --git a/drivers/net/wireless/ath/ath9k/init.c b/drivers/net/wireless/ath/ath9k/init.c
index dee9e092449a..9dfce1a69c73 100644
--- a/drivers/net/wireless/ath/ath9k/init.c
+++ b/drivers/net/wireless/ath/ath9k/init.c
@@ -489,6 +489,7 @@ static void ath9k_init_misc(struct ath_softc *sc)
489 489
490 setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc); 490 setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc);
491 491
492 sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
492 sc->config.txpowlimit = ATH_TXPOWER_MAX; 493 sc->config.txpowlimit = ATH_TXPOWER_MAX;
493 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN); 494 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
494 sc->beacon.slottime = ATH9K_SLOT_TIME_9; 495 sc->beacon.slottime = ATH9K_SLOT_TIME_9;
@@ -560,6 +561,12 @@ static int ath9k_init_softc(u16 devid, struct ath_softc *sc,
560 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet, 561 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
561 (unsigned long)sc); 562 (unsigned long)sc);
562 563
564 INIT_WORK(&sc->hw_reset_work, ath_reset_work);
565 INIT_WORK(&sc->hw_check_work, ath_hw_check);
566 INIT_WORK(&sc->paprd_work, ath_paprd_calibrate);
567 INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work);
568 setup_timer(&sc->rx_poll_timer, ath_rx_poll, (unsigned long)sc);
569
563 /* 570 /*
564 * Cache line size is used to size and align various 571 * Cache line size is used to size and align various
565 * structures used to communicate with the hardware. 572 * structures used to communicate with the hardware.
@@ -590,6 +597,9 @@ static int ath9k_init_softc(u16 devid, struct ath_softc *sc,
590 ath9k_cmn_init_crypto(sc->sc_ah); 597 ath9k_cmn_init_crypto(sc->sc_ah);
591 ath9k_init_misc(sc); 598 ath9k_init_misc(sc);
592 599
600 if (common->bus_ops->aspm_init)
601 common->bus_ops->aspm_init(common);
602
593 return 0; 603 return 0;
594 604
595err_btcoex: 605err_btcoex:
@@ -782,11 +792,6 @@ int ath9k_init_device(u16 devid, struct ath_softc *sc,
782 ARRAY_SIZE(ath9k_tpt_blink)); 792 ARRAY_SIZE(ath9k_tpt_blink));
783#endif 793#endif
784 794
785 INIT_WORK(&sc->hw_reset_work, ath_reset_work);
786 INIT_WORK(&sc->hw_check_work, ath_hw_check);
787 INIT_WORK(&sc->paprd_work, ath_paprd_calibrate);
788 INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work);
789
790 /* Register with mac80211 */ 795 /* Register with mac80211 */
791 error = ieee80211_register_hw(hw); 796 error = ieee80211_register_hw(hw);
792 if (error) 797 if (error)
@@ -805,9 +810,6 @@ int ath9k_init_device(u16 devid, struct ath_softc *sc,
805 goto error_world; 810 goto error_world;
806 } 811 }
807 812
808 setup_timer(&sc->rx_poll_timer, ath_rx_poll, (unsigned long)sc);
809 sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
810
811 ath_init_leds(sc); 813 ath_init_leds(sc);
812 ath_start_rfkill_poll(sc); 814 ath_start_rfkill_poll(sc);
813 815
diff --git a/drivers/net/wireless/ath/ath9k/link.c b/drivers/net/wireless/ath/ath9k/link.c
new file mode 100644
index 000000000000..91650fe50461
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/link.c
@@ -0,0 +1,510 @@
1/*
2 * Copyright (c) 2012 Qualcomm Atheros, Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "ath9k.h"
18
19/*
20 * TX polling - checks if the TX engine is stuck somewhere
21 * and issues a chip reset if so.
22 */
23void ath_tx_complete_poll_work(struct work_struct *work)
24{
25 struct ath_softc *sc = container_of(work, struct ath_softc,
26 tx_complete_work.work);
27 struct ath_txq *txq;
28 int i;
29 bool needreset = false;
30#ifdef CONFIG_ATH9K_DEBUGFS
31 sc->tx_complete_poll_work_seen++;
32#endif
33
34 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
35 if (ATH_TXQ_SETUP(sc, i)) {
36 txq = &sc->tx.txq[i];
37 ath_txq_lock(sc, txq);
38 if (txq->axq_depth) {
39 if (txq->axq_tx_inprogress) {
40 needreset = true;
41 ath_txq_unlock(sc, txq);
42 break;
43 } else {
44 txq->axq_tx_inprogress = true;
45 }
46 }
47 ath_txq_unlock_complete(sc, txq);
48 }
49
50 if (needreset) {
51 ath_dbg(ath9k_hw_common(sc->sc_ah), RESET,
52 "tx hung, resetting the chip\n");
53 RESET_STAT_INC(sc, RESET_TYPE_TX_HANG);
54 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
55 return;
56 }
57
58 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
59 msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT));
60}
61
62/*
63 * Checks if the BB/MAC is hung.
64 */
65void ath_hw_check(struct work_struct *work)
66{
67 struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work);
68 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
69 unsigned long flags;
70 int busy;
71 u8 is_alive, nbeacon = 1;
72
73 ath9k_ps_wakeup(sc);
74 is_alive = ath9k_hw_check_alive(sc->sc_ah);
75
76 if (is_alive && !AR_SREV_9300(sc->sc_ah))
77 goto out;
78 else if (!is_alive && AR_SREV_9300(sc->sc_ah)) {
79 ath_dbg(common, RESET,
80 "DCU stuck is detected. Schedule chip reset\n");
81 RESET_STAT_INC(sc, RESET_TYPE_MAC_HANG);
82 goto sched_reset;
83 }
84
85 spin_lock_irqsave(&common->cc_lock, flags);
86 busy = ath_update_survey_stats(sc);
87 spin_unlock_irqrestore(&common->cc_lock, flags);
88
89 ath_dbg(common, RESET, "Possible baseband hang, busy=%d (try %d)\n",
90 busy, sc->hw_busy_count + 1);
91 if (busy >= 99) {
92 if (++sc->hw_busy_count >= 3) {
93 RESET_STAT_INC(sc, RESET_TYPE_BB_HANG);
94 goto sched_reset;
95 }
96 } else if (busy >= 0) {
97 sc->hw_busy_count = 0;
98 nbeacon = 3;
99 }
100
101 ath_start_rx_poll(sc, nbeacon);
102 goto out;
103
104sched_reset:
105 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
106out:
107 ath9k_ps_restore(sc);
108}
109
110/*
111 * PLL-WAR for AR9485/AR9340
112 */
113static bool ath_hw_pll_rx_hang_check(struct ath_softc *sc, u32 pll_sqsum)
114{
115 static int count;
116 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
117
118 if (pll_sqsum >= 0x40000) {
119 count++;
120 if (count == 3) {
121 ath_dbg(common, RESET, "PLL WAR, resetting the chip\n");
122 RESET_STAT_INC(sc, RESET_TYPE_PLL_HANG);
123 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
124 count = 0;
125 return true;
126 }
127 } else {
128 count = 0;
129 }
130
131 return false;
132}
133
134void ath_hw_pll_work(struct work_struct *work)
135{
136 u32 pll_sqsum;
137 struct ath_softc *sc = container_of(work, struct ath_softc,
138 hw_pll_work.work);
139 /*
140 * ensure that the PLL WAR is executed only
141 * after the STA is associated (or) if the
142 * beaconing had started in interfaces that
143 * uses beacons.
144 */
145 if (!test_bit(SC_OP_BEACONS, &sc->sc_flags))
146 return;
147
148 ath9k_ps_wakeup(sc);
149 pll_sqsum = ar9003_get_pll_sqsum_dvc(sc->sc_ah);
150 ath9k_ps_restore(sc);
151 if (ath_hw_pll_rx_hang_check(sc, pll_sqsum))
152 return;
153
154 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
155 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
156}
157
158/*
159 * RX Polling - monitors baseband hangs.
160 */
161void ath_start_rx_poll(struct ath_softc *sc, u8 nbeacon)
162{
163 if (!AR_SREV_9300(sc->sc_ah))
164 return;
165
166 if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags))
167 return;
168
169 mod_timer(&sc->rx_poll_timer, jiffies + msecs_to_jiffies
170 (nbeacon * sc->cur_beacon_conf.beacon_interval));
171}
172
173void ath_rx_poll(unsigned long data)
174{
175 struct ath_softc *sc = (struct ath_softc *)data;
176
177 ieee80211_queue_work(sc->hw, &sc->hw_check_work);
178}
179
180/*
181 * PA Pre-distortion.
182 */
183static void ath_paprd_activate(struct ath_softc *sc)
184{
185 struct ath_hw *ah = sc->sc_ah;
186 struct ath9k_hw_cal_data *caldata = ah->caldata;
187 int chain;
188
189 if (!caldata || !caldata->paprd_done)
190 return;
191
192 ath9k_ps_wakeup(sc);
193 ar9003_paprd_enable(ah, false);
194 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
195 if (!(ah->txchainmask & BIT(chain)))
196 continue;
197
198 ar9003_paprd_populate_single_table(ah, caldata, chain);
199 }
200
201 ar9003_paprd_enable(ah, true);
202 ath9k_ps_restore(sc);
203}
204
205static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int chain)
206{
207 struct ieee80211_hw *hw = sc->hw;
208 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
209 struct ath_hw *ah = sc->sc_ah;
210 struct ath_common *common = ath9k_hw_common(ah);
211 struct ath_tx_control txctl;
212 int time_left;
213
214 memset(&txctl, 0, sizeof(txctl));
215 txctl.txq = sc->tx.txq_map[WME_AC_BE];
216
217 memset(tx_info, 0, sizeof(*tx_info));
218 tx_info->band = hw->conf.channel->band;
219 tx_info->flags |= IEEE80211_TX_CTL_NO_ACK;
220 tx_info->control.rates[0].idx = 0;
221 tx_info->control.rates[0].count = 1;
222 tx_info->control.rates[0].flags = IEEE80211_TX_RC_MCS;
223 tx_info->control.rates[1].idx = -1;
224
225 init_completion(&sc->paprd_complete);
226 txctl.paprd = BIT(chain);
227
228 if (ath_tx_start(hw, skb, &txctl) != 0) {
229 ath_dbg(common, CALIBRATE, "PAPRD TX failed\n");
230 dev_kfree_skb_any(skb);
231 return false;
232 }
233
234 time_left = wait_for_completion_timeout(&sc->paprd_complete,
235 msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
236
237 if (!time_left)
238 ath_dbg(common, CALIBRATE,
239 "Timeout waiting for paprd training on TX chain %d\n",
240 chain);
241
242 return !!time_left;
243}
244
245void ath_paprd_calibrate(struct work_struct *work)
246{
247 struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);
248 struct ieee80211_hw *hw = sc->hw;
249 struct ath_hw *ah = sc->sc_ah;
250 struct ieee80211_hdr *hdr;
251 struct sk_buff *skb = NULL;
252 struct ath9k_hw_cal_data *caldata = ah->caldata;
253 struct ath_common *common = ath9k_hw_common(ah);
254 int ftype;
255 int chain_ok = 0;
256 int chain;
257 int len = 1800;
258
259 if (!caldata)
260 return;
261
262 ath9k_ps_wakeup(sc);
263
264 if (ar9003_paprd_init_table(ah) < 0)
265 goto fail_paprd;
266
267 skb = alloc_skb(len, GFP_KERNEL);
268 if (!skb)
269 goto fail_paprd;
270
271 skb_put(skb, len);
272 memset(skb->data, 0, len);
273 hdr = (struct ieee80211_hdr *)skb->data;
274 ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC;
275 hdr->frame_control = cpu_to_le16(ftype);
276 hdr->duration_id = cpu_to_le16(10);
277 memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
278 memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
279 memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
280
281 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
282 if (!(ah->txchainmask & BIT(chain)))
283 continue;
284
285 chain_ok = 0;
286
287 ath_dbg(common, CALIBRATE,
288 "Sending PAPRD frame for thermal measurement on chain %d\n",
289 chain);
290 if (!ath_paprd_send_frame(sc, skb, chain))
291 goto fail_paprd;
292
293 ar9003_paprd_setup_gain_table(ah, chain);
294
295 ath_dbg(common, CALIBRATE,
296 "Sending PAPRD training frame on chain %d\n", chain);
297 if (!ath_paprd_send_frame(sc, skb, chain))
298 goto fail_paprd;
299
300 if (!ar9003_paprd_is_done(ah)) {
301 ath_dbg(common, CALIBRATE,
302 "PAPRD not yet done on chain %d\n", chain);
303 break;
304 }
305
306 if (ar9003_paprd_create_curve(ah, caldata, chain)) {
307 ath_dbg(common, CALIBRATE,
308 "PAPRD create curve failed on chain %d\n",
309 chain);
310 break;
311 }
312
313 chain_ok = 1;
314 }
315 kfree_skb(skb);
316
317 if (chain_ok) {
318 caldata->paprd_done = true;
319 ath_paprd_activate(sc);
320 }
321
322fail_paprd:
323 ath9k_ps_restore(sc);
324}
325
326/*
327 * ANI performs periodic noise floor calibration
328 * that is used to adjust and optimize the chip performance. This
329 * takes environmental changes (location, temperature) into account.
330 * When the task is complete, it reschedules itself depending on the
331 * appropriate interval that was calculated.
332 */
333void ath_ani_calibrate(unsigned long data)
334{
335 struct ath_softc *sc = (struct ath_softc *)data;
336 struct ath_hw *ah = sc->sc_ah;
337 struct ath_common *common = ath9k_hw_common(ah);
338 bool longcal = false;
339 bool shortcal = false;
340 bool aniflag = false;
341 unsigned int timestamp = jiffies_to_msecs(jiffies);
342 u32 cal_interval, short_cal_interval, long_cal_interval;
343 unsigned long flags;
344
345 if (ah->caldata && ah->caldata->nfcal_interference)
346 long_cal_interval = ATH_LONG_CALINTERVAL_INT;
347 else
348 long_cal_interval = ATH_LONG_CALINTERVAL;
349
350 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
351 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
352
353 /* Only calibrate if awake */
354 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
355 goto set_timer;
356
357 ath9k_ps_wakeup(sc);
358
359 /* Long calibration runs independently of short calibration. */
360 if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) {
361 longcal = true;
362 common->ani.longcal_timer = timestamp;
363 }
364
365 /* Short calibration applies only while caldone is false */
366 if (!common->ani.caldone) {
367 if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
368 shortcal = true;
369 common->ani.shortcal_timer = timestamp;
370 common->ani.resetcal_timer = timestamp;
371 }
372 } else {
373 if ((timestamp - common->ani.resetcal_timer) >=
374 ATH_RESTART_CALINTERVAL) {
375 common->ani.caldone = ath9k_hw_reset_calvalid(ah);
376 if (common->ani.caldone)
377 common->ani.resetcal_timer = timestamp;
378 }
379 }
380
381 /* Verify whether we must check ANI */
382 if (sc->sc_ah->config.enable_ani
383 && (timestamp - common->ani.checkani_timer) >=
384 ah->config.ani_poll_interval) {
385 aniflag = true;
386 common->ani.checkani_timer = timestamp;
387 }
388
389 /* Call ANI routine if necessary */
390 if (aniflag) {
391 spin_lock_irqsave(&common->cc_lock, flags);
392 ath9k_hw_ani_monitor(ah, ah->curchan);
393 ath_update_survey_stats(sc);
394 spin_unlock_irqrestore(&common->cc_lock, flags);
395 }
396
397 /* Perform calibration if necessary */
398 if (longcal || shortcal) {
399 common->ani.caldone =
400 ath9k_hw_calibrate(ah, ah->curchan,
401 ah->rxchainmask, longcal);
402 }
403
404 ath_dbg(common, ANI,
405 "Calibration @%lu finished: %s %s %s, caldone: %s\n",
406 jiffies,
407 longcal ? "long" : "", shortcal ? "short" : "",
408 aniflag ? "ani" : "", common->ani.caldone ? "true" : "false");
409
410 ath9k_debug_samp_bb_mac(sc);
411 ath9k_ps_restore(sc);
412
413set_timer:
414 /*
415 * Set timer interval based on previous results.
416 * The interval must be the shortest necessary to satisfy ANI,
417 * short calibration and long calibration.
418 */
419 cal_interval = ATH_LONG_CALINTERVAL;
420 if (sc->sc_ah->config.enable_ani)
421 cal_interval = min(cal_interval,
422 (u32)ah->config.ani_poll_interval);
423 if (!common->ani.caldone)
424 cal_interval = min(cal_interval, (u32)short_cal_interval);
425
426 mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
427 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) {
428 if (!ah->caldata->paprd_done)
429 ieee80211_queue_work(sc->hw, &sc->paprd_work);
430 else if (!ah->paprd_table_write_done)
431 ath_paprd_activate(sc);
432 }
433}
434
435void ath_start_ani(struct ath_common *common)
436{
437 struct ath_hw *ah = common->ah;
438 unsigned long timestamp = jiffies_to_msecs(jiffies);
439 struct ath_softc *sc = (struct ath_softc *) common->priv;
440
441 if (!test_bit(SC_OP_ANI_RUN, &sc->sc_flags))
442 return;
443
444 if (sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)
445 return;
446
447 common->ani.longcal_timer = timestamp;
448 common->ani.shortcal_timer = timestamp;
449 common->ani.checkani_timer = timestamp;
450
451 mod_timer(&common->ani.timer,
452 jiffies + msecs_to_jiffies((u32)ah->config.ani_poll_interval));
453}
454
455void ath_update_survey_nf(struct ath_softc *sc, int channel)
456{
457 struct ath_hw *ah = sc->sc_ah;
458 struct ath9k_channel *chan = &ah->channels[channel];
459 struct survey_info *survey = &sc->survey[channel];
460
461 if (chan->noisefloor) {
462 survey->filled |= SURVEY_INFO_NOISE_DBM;
463 survey->noise = ath9k_hw_getchan_noise(ah, chan);
464 }
465}
466
467/*
468 * Updates the survey statistics and returns the busy time since last
469 * update in %, if the measurement duration was long enough for the
470 * result to be useful, -1 otherwise.
471 */
472int ath_update_survey_stats(struct ath_softc *sc)
473{
474 struct ath_hw *ah = sc->sc_ah;
475 struct ath_common *common = ath9k_hw_common(ah);
476 int pos = ah->curchan - &ah->channels[0];
477 struct survey_info *survey = &sc->survey[pos];
478 struct ath_cycle_counters *cc = &common->cc_survey;
479 unsigned int div = common->clockrate * 1000;
480 int ret = 0;
481
482 if (!ah->curchan)
483 return -1;
484
485 if (ah->power_mode == ATH9K_PM_AWAKE)
486 ath_hw_cycle_counters_update(common);
487
488 if (cc->cycles > 0) {
489 survey->filled |= SURVEY_INFO_CHANNEL_TIME |
490 SURVEY_INFO_CHANNEL_TIME_BUSY |
491 SURVEY_INFO_CHANNEL_TIME_RX |
492 SURVEY_INFO_CHANNEL_TIME_TX;
493 survey->channel_time += cc->cycles / div;
494 survey->channel_time_busy += cc->rx_busy / div;
495 survey->channel_time_rx += cc->rx_frame / div;
496 survey->channel_time_tx += cc->tx_frame / div;
497 }
498
499 if (cc->cycles < div)
500 return -1;
501
502 if (cc->cycles > 0)
503 ret = cc->rx_busy * 100 / cc->cycles;
504
505 memset(cc, 0, sizeof(*cc));
506
507 ath_update_survey_nf(sc, pos);
508
509 return ret;
510}
diff --git a/drivers/net/wireless/ath/ath9k/mac.c b/drivers/net/wireless/ath/ath9k/mac.c
index 04ef775ccee1..7990cd55599c 100644
--- a/drivers/net/wireless/ath/ath9k/mac.c
+++ b/drivers/net/wireless/ath/ath9k/mac.c
@@ -810,7 +810,7 @@ void ath9k_hw_enable_interrupts(struct ath_hw *ah)
810 return; 810 return;
811 } 811 }
812 812
813 if (AR_SREV_9340(ah)) 813 if (AR_SREV_9340(ah) || AR_SREV_9550(ah))
814 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL; 814 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
815 815
816 async_mask = AR_INTR_MAC_IRQ; 816 async_mask = AR_INTR_MAC_IRQ;
diff --git a/drivers/net/wireless/ath/ath9k/mac.h b/drivers/net/wireless/ath/ath9k/mac.h
index 21c955609e6c..0eba36dca6f8 100644
--- a/drivers/net/wireless/ath/ath9k/mac.h
+++ b/drivers/net/wireless/ath/ath9k/mac.h
@@ -646,6 +646,7 @@ enum ath9k_rx_filter {
646 ATH9K_RX_FILTER_PHYRADAR = 0x00002000, 646 ATH9K_RX_FILTER_PHYRADAR = 0x00002000,
647 ATH9K_RX_FILTER_MCAST_BCAST_ALL = 0x00008000, 647 ATH9K_RX_FILTER_MCAST_BCAST_ALL = 0x00008000,
648 ATH9K_RX_FILTER_CONTROL_WRAPPER = 0x00080000, 648 ATH9K_RX_FILTER_CONTROL_WRAPPER = 0x00080000,
649 ATH9K_RX_FILTER_4ADDRESS = 0x00100000,
649}; 650};
650 651
651#define ATH9K_RATESERIES_RTS_CTS 0x0001 652#define ATH9K_RATESERIES_RTS_CTS 0x0001
diff --git a/drivers/net/wireless/ath/ath9k/main.c b/drivers/net/wireless/ath/ath9k/main.c
index dac1a2709e3c..248e5b24acfa 100644
--- a/drivers/net/wireless/ath/ath9k/main.c
+++ b/drivers/net/wireless/ath/ath9k/main.c
@@ -19,7 +19,7 @@
19#include "ath9k.h" 19#include "ath9k.h"
20#include "btcoex.h" 20#include "btcoex.h"
21 21
22static u8 parse_mpdudensity(u8 mpdudensity) 22u8 ath9k_parse_mpdudensity(u8 mpdudensity)
23{ 23{
24 /* 24 /*
25 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": 25 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
@@ -101,6 +101,7 @@ void ath9k_ps_wakeup(struct ath_softc *sc)
101 spin_lock(&common->cc_lock); 101 spin_lock(&common->cc_lock);
102 ath_hw_cycle_counters_update(common); 102 ath_hw_cycle_counters_update(common);
103 memset(&common->cc_survey, 0, sizeof(common->cc_survey)); 103 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
104 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
104 spin_unlock(&common->cc_lock); 105 spin_unlock(&common->cc_lock);
105 } 106 }
106 107
@@ -129,6 +130,8 @@ void ath9k_ps_restore(struct ath_softc *sc)
129 PS_WAIT_FOR_PSPOLL_DATA | 130 PS_WAIT_FOR_PSPOLL_DATA |
130 PS_WAIT_FOR_TX_ACK))) { 131 PS_WAIT_FOR_TX_ACK))) {
131 mode = ATH9K_PM_NETWORK_SLEEP; 132 mode = ATH9K_PM_NETWORK_SLEEP;
133 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
134 ath9k_btcoex_stop_gen_timer(sc);
132 } else { 135 } else {
133 goto unlock; 136 goto unlock;
134 } 137 }
@@ -143,90 +146,17 @@ void ath9k_ps_restore(struct ath_softc *sc)
143 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 146 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
144} 147}
145 148
146void ath_start_ani(struct ath_common *common)
147{
148 struct ath_hw *ah = common->ah;
149 unsigned long timestamp = jiffies_to_msecs(jiffies);
150 struct ath_softc *sc = (struct ath_softc *) common->priv;
151
152 if (!(sc->sc_flags & SC_OP_ANI_RUN))
153 return;
154
155 if (sc->sc_flags & SC_OP_OFFCHANNEL)
156 return;
157
158 common->ani.longcal_timer = timestamp;
159 common->ani.shortcal_timer = timestamp;
160 common->ani.checkani_timer = timestamp;
161
162 mod_timer(&common->ani.timer,
163 jiffies +
164 msecs_to_jiffies((u32)ah->config.ani_poll_interval));
165}
166
167static void ath_update_survey_nf(struct ath_softc *sc, int channel)
168{
169 struct ath_hw *ah = sc->sc_ah;
170 struct ath9k_channel *chan = &ah->channels[channel];
171 struct survey_info *survey = &sc->survey[channel];
172
173 if (chan->noisefloor) {
174 survey->filled |= SURVEY_INFO_NOISE_DBM;
175 survey->noise = ath9k_hw_getchan_noise(ah, chan);
176 }
177}
178
179/*
180 * Updates the survey statistics and returns the busy time since last
181 * update in %, if the measurement duration was long enough for the
182 * result to be useful, -1 otherwise.
183 */
184static int ath_update_survey_stats(struct ath_softc *sc)
185{
186 struct ath_hw *ah = sc->sc_ah;
187 struct ath_common *common = ath9k_hw_common(ah);
188 int pos = ah->curchan - &ah->channels[0];
189 struct survey_info *survey = &sc->survey[pos];
190 struct ath_cycle_counters *cc = &common->cc_survey;
191 unsigned int div = common->clockrate * 1000;
192 int ret = 0;
193
194 if (!ah->curchan)
195 return -1;
196
197 if (ah->power_mode == ATH9K_PM_AWAKE)
198 ath_hw_cycle_counters_update(common);
199
200 if (cc->cycles > 0) {
201 survey->filled |= SURVEY_INFO_CHANNEL_TIME |
202 SURVEY_INFO_CHANNEL_TIME_BUSY |
203 SURVEY_INFO_CHANNEL_TIME_RX |
204 SURVEY_INFO_CHANNEL_TIME_TX;
205 survey->channel_time += cc->cycles / div;
206 survey->channel_time_busy += cc->rx_busy / div;
207 survey->channel_time_rx += cc->rx_frame / div;
208 survey->channel_time_tx += cc->tx_frame / div;
209 }
210
211 if (cc->cycles < div)
212 return -1;
213
214 if (cc->cycles > 0)
215 ret = cc->rx_busy * 100 / cc->cycles;
216
217 memset(cc, 0, sizeof(*cc));
218
219 ath_update_survey_nf(sc, pos);
220
221 return ret;
222}
223
224static void __ath_cancel_work(struct ath_softc *sc) 149static void __ath_cancel_work(struct ath_softc *sc)
225{ 150{
226 cancel_work_sync(&sc->paprd_work); 151 cancel_work_sync(&sc->paprd_work);
227 cancel_work_sync(&sc->hw_check_work); 152 cancel_work_sync(&sc->hw_check_work);
228 cancel_delayed_work_sync(&sc->tx_complete_work); 153 cancel_delayed_work_sync(&sc->tx_complete_work);
229 cancel_delayed_work_sync(&sc->hw_pll_work); 154 cancel_delayed_work_sync(&sc->hw_pll_work);
155
156#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
157 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
158 cancel_work_sync(&sc->mci_work);
159#endif
230} 160}
231 161
232static void ath_cancel_work(struct ath_softc *sc) 162static void ath_cancel_work(struct ath_softc *sc)
@@ -235,6 +165,23 @@ static void ath_cancel_work(struct ath_softc *sc)
235 cancel_work_sync(&sc->hw_reset_work); 165 cancel_work_sync(&sc->hw_reset_work);
236} 166}
237 167
168static void ath_restart_work(struct ath_softc *sc)
169{
170 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
171
172 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
173
174 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9485(sc->sc_ah) ||
175 AR_SREV_9550(sc->sc_ah))
176 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
177 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
178
179 ath_start_rx_poll(sc, 3);
180
181 if (!common->disable_ani)
182 ath_start_ani(common);
183}
184
238static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush) 185static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush)
239{ 186{
240 struct ath_hw *ah = sc->sc_ah; 187 struct ath_hw *ah = sc->sc_ah;
@@ -271,6 +218,7 @@ static bool ath_complete_reset(struct ath_softc *sc, bool start)
271{ 218{
272 struct ath_hw *ah = sc->sc_ah; 219 struct ath_hw *ah = sc->sc_ah;
273 struct ath_common *common = ath9k_hw_common(ah); 220 struct ath_common *common = ath9k_hw_common(ah);
221 unsigned long flags;
274 222
275 if (ath_startrecv(sc) != 0) { 223 if (ath_startrecv(sc) != 0) {
276 ath_err(common, "Unable to restart recv logic\n"); 224 ath_err(common, "Unable to restart recv logic\n");
@@ -279,36 +227,30 @@ static bool ath_complete_reset(struct ath_softc *sc, bool start)
279 227
280 ath9k_cmn_update_txpow(ah, sc->curtxpow, 228 ath9k_cmn_update_txpow(ah, sc->curtxpow,
281 sc->config.txpowlimit, &sc->curtxpow); 229 sc->config.txpowlimit, &sc->curtxpow);
230
231 clear_bit(SC_OP_HW_RESET, &sc->sc_flags);
282 ath9k_hw_set_interrupts(ah); 232 ath9k_hw_set_interrupts(ah);
283 ath9k_hw_enable_interrupts(ah); 233 ath9k_hw_enable_interrupts(ah);
284 234
285 if (!(sc->sc_flags & (SC_OP_OFFCHANNEL)) && start) { 235 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) {
286 if (sc->sc_flags & SC_OP_BEACONS) 236 if (!test_bit(SC_OP_BEACONS, &sc->sc_flags))
287 ath_set_beacon(sc); 237 goto work;
288
289 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
290 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/2);
291 ath_start_rx_poll(sc, 3);
292 if (!common->disable_ani)
293 ath_start_ani(common);
294 }
295
296 if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3) {
297 struct ath_hw_antcomb_conf div_ant_conf;
298 u8 lna_conf;
299
300 ath9k_hw_antdiv_comb_conf_get(ah, &div_ant_conf);
301 238
302 if (sc->ant_rx == 1) 239 ath_set_beacon(sc);
303 lna_conf = ATH_ANT_DIV_COMB_LNA1;
304 else
305 lna_conf = ATH_ANT_DIV_COMB_LNA2;
306 div_ant_conf.main_lna_conf = lna_conf;
307 div_ant_conf.alt_lna_conf = lna_conf;
308 240
309 ath9k_hw_antdiv_comb_conf_set(ah, &div_ant_conf); 241 if (ah->opmode == NL80211_IFTYPE_STATION &&
242 test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
243 spin_lock_irqsave(&sc->sc_pm_lock, flags);
244 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
245 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
246 }
247 work:
248 ath_restart_work(sc);
310 } 249 }
311 250
251 if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3)
252 ath_ant_comb_update(sc);
253
312 ieee80211_wake_queues(sc->hw); 254 ieee80211_wake_queues(sc->hw);
313 255
314 return true; 256 return true;
@@ -328,7 +270,7 @@ static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan,
328 270
329 spin_lock_bh(&sc->sc_pcu_lock); 271 spin_lock_bh(&sc->sc_pcu_lock);
330 272
331 if (!(sc->sc_flags & SC_OP_OFFCHANNEL)) { 273 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) {
332 fastcc = false; 274 fastcc = false;
333 caldata = &sc->caldata; 275 caldata = &sc->caldata;
334 } 276 }
@@ -371,7 +313,7 @@ static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
371{ 313{
372 int r; 314 int r;
373 315
374 if (sc->sc_flags & SC_OP_INVALID) 316 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
375 return -EIO; 317 return -EIO;
376 318
377 r = ath_reset_internal(sc, hchan, false); 319 r = ath_reset_internal(sc, hchan, false);
@@ -379,262 +321,11 @@ static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
379 return r; 321 return r;
380} 322}
381 323
382static void ath_paprd_activate(struct ath_softc *sc)
383{
384 struct ath_hw *ah = sc->sc_ah;
385 struct ath9k_hw_cal_data *caldata = ah->caldata;
386 int chain;
387
388 if (!caldata || !caldata->paprd_done)
389 return;
390
391 ath9k_ps_wakeup(sc);
392 ar9003_paprd_enable(ah, false);
393 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
394 if (!(ah->txchainmask & BIT(chain)))
395 continue;
396
397 ar9003_paprd_populate_single_table(ah, caldata, chain);
398 }
399
400 ar9003_paprd_enable(ah, true);
401 ath9k_ps_restore(sc);
402}
403
404static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int chain)
405{
406 struct ieee80211_hw *hw = sc->hw;
407 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
408 struct ath_hw *ah = sc->sc_ah;
409 struct ath_common *common = ath9k_hw_common(ah);
410 struct ath_tx_control txctl;
411 int time_left;
412
413 memset(&txctl, 0, sizeof(txctl));
414 txctl.txq = sc->tx.txq_map[WME_AC_BE];
415
416 memset(tx_info, 0, sizeof(*tx_info));
417 tx_info->band = hw->conf.channel->band;
418 tx_info->flags |= IEEE80211_TX_CTL_NO_ACK;
419 tx_info->control.rates[0].idx = 0;
420 tx_info->control.rates[0].count = 1;
421 tx_info->control.rates[0].flags = IEEE80211_TX_RC_MCS;
422 tx_info->control.rates[1].idx = -1;
423
424 init_completion(&sc->paprd_complete);
425 txctl.paprd = BIT(chain);
426
427 if (ath_tx_start(hw, skb, &txctl) != 0) {
428 ath_dbg(common, CALIBRATE, "PAPRD TX failed\n");
429 dev_kfree_skb_any(skb);
430 return false;
431 }
432
433 time_left = wait_for_completion_timeout(&sc->paprd_complete,
434 msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
435
436 if (!time_left)
437 ath_dbg(common, CALIBRATE,
438 "Timeout waiting for paprd training on TX chain %d\n",
439 chain);
440
441 return !!time_left;
442}
443
444void ath_paprd_calibrate(struct work_struct *work)
445{
446 struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);
447 struct ieee80211_hw *hw = sc->hw;
448 struct ath_hw *ah = sc->sc_ah;
449 struct ieee80211_hdr *hdr;
450 struct sk_buff *skb = NULL;
451 struct ath9k_hw_cal_data *caldata = ah->caldata;
452 struct ath_common *common = ath9k_hw_common(ah);
453 int ftype;
454 int chain_ok = 0;
455 int chain;
456 int len = 1800;
457
458 if (!caldata)
459 return;
460
461 ath9k_ps_wakeup(sc);
462
463 if (ar9003_paprd_init_table(ah) < 0)
464 goto fail_paprd;
465
466 skb = alloc_skb(len, GFP_KERNEL);
467 if (!skb)
468 goto fail_paprd;
469
470 skb_put(skb, len);
471 memset(skb->data, 0, len);
472 hdr = (struct ieee80211_hdr *)skb->data;
473 ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC;
474 hdr->frame_control = cpu_to_le16(ftype);
475 hdr->duration_id = cpu_to_le16(10);
476 memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
477 memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
478 memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
479
480 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
481 if (!(ah->txchainmask & BIT(chain)))
482 continue;
483
484 chain_ok = 0;
485
486 ath_dbg(common, CALIBRATE,
487 "Sending PAPRD frame for thermal measurement on chain %d\n",
488 chain);
489 if (!ath_paprd_send_frame(sc, skb, chain))
490 goto fail_paprd;
491
492 ar9003_paprd_setup_gain_table(ah, chain);
493
494 ath_dbg(common, CALIBRATE,
495 "Sending PAPRD training frame on chain %d\n", chain);
496 if (!ath_paprd_send_frame(sc, skb, chain))
497 goto fail_paprd;
498
499 if (!ar9003_paprd_is_done(ah)) {
500 ath_dbg(common, CALIBRATE,
501 "PAPRD not yet done on chain %d\n", chain);
502 break;
503 }
504
505 if (ar9003_paprd_create_curve(ah, caldata, chain)) {
506 ath_dbg(common, CALIBRATE,
507 "PAPRD create curve failed on chain %d\n",
508 chain);
509 break;
510 }
511
512 chain_ok = 1;
513 }
514 kfree_skb(skb);
515
516 if (chain_ok) {
517 caldata->paprd_done = true;
518 ath_paprd_activate(sc);
519 }
520
521fail_paprd:
522 ath9k_ps_restore(sc);
523}
524
525/*
526 * This routine performs the periodic noise floor calibration function
527 * that is used to adjust and optimize the chip performance. This
528 * takes environmental changes (location, temperature) into account.
529 * When the task is complete, it reschedules itself depending on the
530 * appropriate interval that was calculated.
531 */
532void ath_ani_calibrate(unsigned long data)
533{
534 struct ath_softc *sc = (struct ath_softc *)data;
535 struct ath_hw *ah = sc->sc_ah;
536 struct ath_common *common = ath9k_hw_common(ah);
537 bool longcal = false;
538 bool shortcal = false;
539 bool aniflag = false;
540 unsigned int timestamp = jiffies_to_msecs(jiffies);
541 u32 cal_interval, short_cal_interval, long_cal_interval;
542 unsigned long flags;
543
544 if (ah->caldata && ah->caldata->nfcal_interference)
545 long_cal_interval = ATH_LONG_CALINTERVAL_INT;
546 else
547 long_cal_interval = ATH_LONG_CALINTERVAL;
548
549 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
550 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
551
552 /* Only calibrate if awake */
553 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
554 goto set_timer;
555
556 ath9k_ps_wakeup(sc);
557
558 /* Long calibration runs independently of short calibration. */
559 if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) {
560 longcal = true;
561 common->ani.longcal_timer = timestamp;
562 }
563
564 /* Short calibration applies only while caldone is false */
565 if (!common->ani.caldone) {
566 if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
567 shortcal = true;
568 common->ani.shortcal_timer = timestamp;
569 common->ani.resetcal_timer = timestamp;
570 }
571 } else {
572 if ((timestamp - common->ani.resetcal_timer) >=
573 ATH_RESTART_CALINTERVAL) {
574 common->ani.caldone = ath9k_hw_reset_calvalid(ah);
575 if (common->ani.caldone)
576 common->ani.resetcal_timer = timestamp;
577 }
578 }
579
580 /* Verify whether we must check ANI */
581 if (sc->sc_ah->config.enable_ani
582 && (timestamp - common->ani.checkani_timer) >=
583 ah->config.ani_poll_interval) {
584 aniflag = true;
585 common->ani.checkani_timer = timestamp;
586 }
587
588 /* Call ANI routine if necessary */
589 if (aniflag) {
590 spin_lock_irqsave(&common->cc_lock, flags);
591 ath9k_hw_ani_monitor(ah, ah->curchan);
592 ath_update_survey_stats(sc);
593 spin_unlock_irqrestore(&common->cc_lock, flags);
594 }
595
596 /* Perform calibration if necessary */
597 if (longcal || shortcal) {
598 common->ani.caldone =
599 ath9k_hw_calibrate(ah, ah->curchan,
600 ah->rxchainmask, longcal);
601 }
602
603 ath_dbg(common, ANI,
604 "Calibration @%lu finished: %s %s %s, caldone: %s\n",
605 jiffies,
606 longcal ? "long" : "", shortcal ? "short" : "",
607 aniflag ? "ani" : "", common->ani.caldone ? "true" : "false");
608
609 ath9k_ps_restore(sc);
610
611set_timer:
612 /*
613 * Set timer interval based on previous results.
614 * The interval must be the shortest necessary to satisfy ANI,
615 * short calibration and long calibration.
616 */
617 ath9k_debug_samp_bb_mac(sc);
618 cal_interval = ATH_LONG_CALINTERVAL;
619 if (sc->sc_ah->config.enable_ani)
620 cal_interval = min(cal_interval,
621 (u32)ah->config.ani_poll_interval);
622 if (!common->ani.caldone)
623 cal_interval = min(cal_interval, (u32)short_cal_interval);
624
625 mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
626 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) {
627 if (!ah->caldata->paprd_done)
628 ieee80211_queue_work(sc->hw, &sc->paprd_work);
629 else if (!ah->paprd_table_write_done)
630 ath_paprd_activate(sc);
631 }
632}
633
634static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta, 324static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
635 struct ieee80211_vif *vif) 325 struct ieee80211_vif *vif)
636{ 326{
637 struct ath_node *an; 327 struct ath_node *an;
328 u8 density;
638 an = (struct ath_node *)sta->drv_priv; 329 an = (struct ath_node *)sta->drv_priv;
639 330
640#ifdef CONFIG_ATH9K_DEBUGFS 331#ifdef CONFIG_ATH9K_DEBUGFS
@@ -649,7 +340,8 @@ static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
649 ath_tx_node_init(sc, an); 340 ath_tx_node_init(sc, an);
650 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + 341 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
651 sta->ht_cap.ampdu_factor); 342 sta->ht_cap.ampdu_factor);
652 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density); 343 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
344 an->mpdudensity = density;
653 } 345 }
654} 346}
655 347
@@ -668,13 +360,12 @@ static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
668 ath_tx_node_cleanup(sc, an); 360 ath_tx_node_cleanup(sc, an);
669} 361}
670 362
671
672void ath9k_tasklet(unsigned long data) 363void ath9k_tasklet(unsigned long data)
673{ 364{
674 struct ath_softc *sc = (struct ath_softc *)data; 365 struct ath_softc *sc = (struct ath_softc *)data;
675 struct ath_hw *ah = sc->sc_ah; 366 struct ath_hw *ah = sc->sc_ah;
676 struct ath_common *common = ath9k_hw_common(ah); 367 struct ath_common *common = ath9k_hw_common(ah);
677 368 unsigned long flags;
678 u32 status = sc->intrstatus; 369 u32 status = sc->intrstatus;
679 u32 rxmask; 370 u32 rxmask;
680 371
@@ -693,10 +384,12 @@ void ath9k_tasklet(unsigned long data)
693 384
694 RESET_STAT_INC(sc, type); 385 RESET_STAT_INC(sc, type);
695#endif 386#endif
387 set_bit(SC_OP_HW_RESET, &sc->sc_flags);
696 ieee80211_queue_work(sc->hw, &sc->hw_reset_work); 388 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
697 goto out; 389 goto out;
698 } 390 }
699 391
392 spin_lock_irqsave(&sc->sc_pm_lock, flags);
700 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { 393 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
701 /* 394 /*
702 * TSF sync does not look correct; remain awake to sync with 395 * TSF sync does not look correct; remain awake to sync with
@@ -705,6 +398,7 @@ void ath9k_tasklet(unsigned long data)
705 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n"); 398 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
706 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; 399 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
707 } 400 }
401 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
708 402
709 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 403 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
710 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL | 404 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
@@ -766,15 +460,17 @@ irqreturn_t ath_isr(int irq, void *dev)
766 * touch anything. Note this can happen early 460 * touch anything. Note this can happen early
767 * on if the IRQ is shared. 461 * on if the IRQ is shared.
768 */ 462 */
769 if (sc->sc_flags & SC_OP_INVALID) 463 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
770 return IRQ_NONE; 464 return IRQ_NONE;
771 465
772
773 /* shared irq, not for us */ 466 /* shared irq, not for us */
774 467
775 if (!ath9k_hw_intrpend(ah)) 468 if (!ath9k_hw_intrpend(ah))
776 return IRQ_NONE; 469 return IRQ_NONE;
777 470
471 if(test_bit(SC_OP_HW_RESET, &sc->sc_flags))
472 return IRQ_HANDLED;
473
778 /* 474 /*
779 * Figure out the reason(s) for the interrupt. Note 475 * Figure out the reason(s) for the interrupt. Note
780 * that the hal returns a pseudo-ISR that may include 476 * that the hal returns a pseudo-ISR that may include
@@ -827,24 +523,6 @@ irqreturn_t ath_isr(int irq, void *dev)
827 ath9k_hw_set_interrupts(ah); 523 ath9k_hw_set_interrupts(ah);
828 } 524 }
829 525
830 if (status & ATH9K_INT_MIB) {
831 /*
832 * Disable interrupts until we service the MIB
833 * interrupt; otherwise it will continue to
834 * fire.
835 */
836 ath9k_hw_disable_interrupts(ah);
837 /*
838 * Let the hal handle the event. We assume
839 * it will clear whatever condition caused
840 * the interrupt.
841 */
842 spin_lock(&common->cc_lock);
843 ath9k_hw_proc_mib_event(ah);
844 spin_unlock(&common->cc_lock);
845 ath9k_hw_enable_interrupts(ah);
846 }
847
848 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 526 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
849 if (status & ATH9K_INT_TIM_TIMER) { 527 if (status & ATH9K_INT_TIM_TIMER) {
850 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle)) 528 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
@@ -852,8 +530,10 @@ irqreturn_t ath_isr(int irq, void *dev)
852 /* Clear RxAbort bit so that we can 530 /* Clear RxAbort bit so that we can
853 * receive frames */ 531 * receive frames */
854 ath9k_setpower(sc, ATH9K_PM_AWAKE); 532 ath9k_setpower(sc, ATH9K_PM_AWAKE);
533 spin_lock(&sc->sc_pm_lock);
855 ath9k_hw_setrxabort(sc->sc_ah, 0); 534 ath9k_hw_setrxabort(sc->sc_ah, 0);
856 sc->ps_flags |= PS_WAIT_FOR_BEACON; 535 sc->ps_flags |= PS_WAIT_FOR_BEACON;
536 spin_unlock(&sc->sc_pm_lock);
857 } 537 }
858 538
859chip_reset: 539chip_reset:
@@ -902,96 +582,6 @@ void ath_reset_work(struct work_struct *work)
902 ath_reset(sc, true); 582 ath_reset(sc, true);
903} 583}
904 584
905void ath_hw_check(struct work_struct *work)
906{
907 struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work);
908 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
909 unsigned long flags;
910 int busy;
911 u8 is_alive, nbeacon = 1;
912
913 ath9k_ps_wakeup(sc);
914 is_alive = ath9k_hw_check_alive(sc->sc_ah);
915
916 if (is_alive && !AR_SREV_9300(sc->sc_ah))
917 goto out;
918 else if (!is_alive && AR_SREV_9300(sc->sc_ah)) {
919 ath_dbg(common, RESET,
920 "DCU stuck is detected. Schedule chip reset\n");
921 RESET_STAT_INC(sc, RESET_TYPE_MAC_HANG);
922 goto sched_reset;
923 }
924
925 spin_lock_irqsave(&common->cc_lock, flags);
926 busy = ath_update_survey_stats(sc);
927 spin_unlock_irqrestore(&common->cc_lock, flags);
928
929 ath_dbg(common, RESET, "Possible baseband hang, busy=%d (try %d)\n",
930 busy, sc->hw_busy_count + 1);
931 if (busy >= 99) {
932 if (++sc->hw_busy_count >= 3) {
933 RESET_STAT_INC(sc, RESET_TYPE_BB_HANG);
934 goto sched_reset;
935 }
936 } else if (busy >= 0) {
937 sc->hw_busy_count = 0;
938 nbeacon = 3;
939 }
940
941 ath_start_rx_poll(sc, nbeacon);
942 goto out;
943
944sched_reset:
945 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
946out:
947 ath9k_ps_restore(sc);
948}
949
950static void ath_hw_pll_rx_hang_check(struct ath_softc *sc, u32 pll_sqsum)
951{
952 static int count;
953 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
954
955 if (pll_sqsum >= 0x40000) {
956 count++;
957 if (count == 3) {
958 /* Rx is hung for more than 500ms. Reset it */
959 ath_dbg(common, RESET, "Possible RX hang, resetting\n");
960 RESET_STAT_INC(sc, RESET_TYPE_PLL_HANG);
961 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
962 count = 0;
963 }
964 } else
965 count = 0;
966}
967
968void ath_hw_pll_work(struct work_struct *work)
969{
970 struct ath_softc *sc = container_of(work, struct ath_softc,
971 hw_pll_work.work);
972 u32 pll_sqsum;
973
974 /*
975 * ensure that the PLL WAR is executed only
976 * after the STA is associated (or) if the
977 * beaconing had started in interfaces that
978 * uses beacons.
979 */
980 if (!(sc->sc_flags & SC_OP_BEACONS))
981 return;
982
983 if (AR_SREV_9485(sc->sc_ah)) {
984
985 ath9k_ps_wakeup(sc);
986 pll_sqsum = ar9003_get_pll_sqsum_dvc(sc->sc_ah);
987 ath9k_ps_restore(sc);
988
989 ath_hw_pll_rx_hang_check(sc, pll_sqsum);
990
991 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/5);
992 }
993}
994
995/**********************/ 585/**********************/
996/* mac80211 callbacks */ 586/* mac80211 callbacks */
997/**********************/ 587/**********************/
@@ -1054,10 +644,9 @@ static int ath9k_start(struct ieee80211_hw *hw)
1054 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) 644 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
1055 ah->imask |= ATH9K_INT_CST; 645 ah->imask |= ATH9K_INT_CST;
1056 646
1057 if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI) 647 ath_mci_enable(sc);
1058 ah->imask |= ATH9K_INT_MCI;
1059 648
1060 sc->sc_flags &= ~SC_OP_INVALID; 649 clear_bit(SC_OP_INVALID, &sc->sc_flags);
1061 sc->sc_ah->is_monitoring = false; 650 sc->sc_ah->is_monitoring = false;
1062 651
1063 if (!ath_complete_reset(sc, false)) { 652 if (!ath_complete_reset(sc, false)) {
@@ -1080,8 +669,6 @@ static int ath9k_start(struct ieee80211_hw *hw)
1080 669
1081 spin_unlock_bh(&sc->sc_pcu_lock); 670 spin_unlock_bh(&sc->sc_pcu_lock);
1082 671
1083 ath9k_start_btcoex(sc);
1084
1085 if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en) 672 if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
1086 common->bus_ops->extn_synch_en(common); 673 common->bus_ops->extn_synch_en(common);
1087 674
@@ -1099,6 +686,7 @@ static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
1099 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 686 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1100 struct ath_tx_control txctl; 687 struct ath_tx_control txctl;
1101 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 688 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
689 unsigned long flags;
1102 690
1103 if (sc->ps_enabled) { 691 if (sc->ps_enabled) {
1104 /* 692 /*
@@ -1121,6 +709,7 @@ static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
1121 * completed and if needed, also for RX of buffered frames. 709 * completed and if needed, also for RX of buffered frames.
1122 */ 710 */
1123 ath9k_ps_wakeup(sc); 711 ath9k_ps_wakeup(sc);
712 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1124 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 713 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
1125 ath9k_hw_setrxabort(sc->sc_ah, 0); 714 ath9k_hw_setrxabort(sc->sc_ah, 0);
1126 if (ieee80211_is_pspoll(hdr->frame_control)) { 715 if (ieee80211_is_pspoll(hdr->frame_control)) {
@@ -1136,6 +725,7 @@ static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
1136 * the ps_flags bit is cleared. We are just dropping 725 * the ps_flags bit is cleared. We are just dropping
1137 * the ps_usecount here. 726 * the ps_usecount here.
1138 */ 727 */
728 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1139 ath9k_ps_restore(sc); 729 ath9k_ps_restore(sc);
1140 } 730 }
1141 731
@@ -1176,7 +766,7 @@ static void ath9k_stop(struct ieee80211_hw *hw)
1176 ath_cancel_work(sc); 766 ath_cancel_work(sc);
1177 del_timer_sync(&sc->rx_poll_timer); 767 del_timer_sync(&sc->rx_poll_timer);
1178 768
1179 if (sc->sc_flags & SC_OP_INVALID) { 769 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
1180 ath_dbg(common, ANY, "Device not present\n"); 770 ath_dbg(common, ANY, "Device not present\n");
1181 mutex_unlock(&sc->mutex); 771 mutex_unlock(&sc->mutex);
1182 return; 772 return;
@@ -1185,8 +775,6 @@ static void ath9k_stop(struct ieee80211_hw *hw)
1185 /* Ensure HW is awake when we try to shut it down. */ 775 /* Ensure HW is awake when we try to shut it down. */
1186 ath9k_ps_wakeup(sc); 776 ath9k_ps_wakeup(sc);
1187 777
1188 ath9k_stop_btcoex(sc);
1189
1190 spin_lock_bh(&sc->sc_pcu_lock); 778 spin_lock_bh(&sc->sc_pcu_lock);
1191 779
1192 /* prevent tasklets to enable interrupts once we disable them */ 780 /* prevent tasklets to enable interrupts once we disable them */
@@ -1233,7 +821,7 @@ static void ath9k_stop(struct ieee80211_hw *hw)
1233 821
1234 ath9k_ps_restore(sc); 822 ath9k_ps_restore(sc);
1235 823
1236 sc->sc_flags |= SC_OP_INVALID; 824 set_bit(SC_OP_INVALID, &sc->sc_flags);
1237 sc->ps_idle = prev_idle; 825 sc->ps_idle = prev_idle;
1238 826
1239 mutex_unlock(&sc->mutex); 827 mutex_unlock(&sc->mutex);
@@ -1337,11 +925,11 @@ static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
1337 /* Set op-mode & TSF */ 925 /* Set op-mode & TSF */
1338 if (iter_data.naps > 0) { 926 if (iter_data.naps > 0) {
1339 ath9k_hw_set_tsfadjust(ah, 1); 927 ath9k_hw_set_tsfadjust(ah, 1);
1340 sc->sc_flags |= SC_OP_TSF_RESET; 928 set_bit(SC_OP_TSF_RESET, &sc->sc_flags);
1341 ah->opmode = NL80211_IFTYPE_AP; 929 ah->opmode = NL80211_IFTYPE_AP;
1342 } else { 930 } else {
1343 ath9k_hw_set_tsfadjust(ah, 0); 931 ath9k_hw_set_tsfadjust(ah, 0);
1344 sc->sc_flags &= ~SC_OP_TSF_RESET; 932 clear_bit(SC_OP_TSF_RESET, &sc->sc_flags);
1345 933
1346 if (iter_data.nmeshes) 934 if (iter_data.nmeshes)
1347 ah->opmode = NL80211_IFTYPE_MESH_POINT; 935 ah->opmode = NL80211_IFTYPE_MESH_POINT;
@@ -1356,14 +944,10 @@ static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
1356 /* 944 /*
1357 * Enable MIB interrupts when there are hardware phy counters. 945 * Enable MIB interrupts when there are hardware phy counters.
1358 */ 946 */
1359 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) { 947 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
1360 if (ah->config.enable_ani)
1361 ah->imask |= ATH9K_INT_MIB;
1362 ah->imask |= ATH9K_INT_TSFOOR; 948 ah->imask |= ATH9K_INT_TSFOOR;
1363 } else { 949 else
1364 ah->imask &= ~ATH9K_INT_MIB;
1365 ah->imask &= ~ATH9K_INT_TSFOOR; 950 ah->imask &= ~ATH9K_INT_TSFOOR;
1366 }
1367 951
1368 ath9k_hw_set_interrupts(ah); 952 ath9k_hw_set_interrupts(ah);
1369 953
@@ -1372,12 +956,12 @@ static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
1372 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; 956 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1373 957
1374 if (!common->disable_ani) { 958 if (!common->disable_ani) {
1375 sc->sc_flags |= SC_OP_ANI_RUN; 959 set_bit(SC_OP_ANI_RUN, &sc->sc_flags);
1376 ath_start_ani(common); 960 ath_start_ani(common);
1377 } 961 }
1378 962
1379 } else { 963 } else {
1380 sc->sc_flags &= ~SC_OP_ANI_RUN; 964 clear_bit(SC_OP_ANI_RUN, &sc->sc_flags);
1381 del_timer_sync(&common->ani.timer); 965 del_timer_sync(&common->ani.timer);
1382 } 966 }
1383} 967}
@@ -1398,25 +982,6 @@ static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw,
1398 } 982 }
1399} 983}
1400 984
1401void ath_start_rx_poll(struct ath_softc *sc, u8 nbeacon)
1402{
1403 if (!AR_SREV_9300(sc->sc_ah))
1404 return;
1405
1406 if (!(sc->sc_flags & SC_OP_PRIM_STA_VIF))
1407 return;
1408
1409 mod_timer(&sc->rx_poll_timer, jiffies + msecs_to_jiffies
1410 (nbeacon * sc->cur_beacon_conf.beacon_interval));
1411}
1412
1413void ath_rx_poll(unsigned long data)
1414{
1415 struct ath_softc *sc = (struct ath_softc *)data;
1416
1417 ieee80211_queue_work(sc->hw, &sc->hw_check_work);
1418}
1419
1420static int ath9k_add_interface(struct ieee80211_hw *hw, 985static int ath9k_add_interface(struct ieee80211_hw *hw,
1421 struct ieee80211_vif *vif) 986 struct ieee80211_vif *vif)
1422{ 987{
@@ -1573,14 +1138,17 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
1573 1138
1574 if (changed & IEEE80211_CONF_CHANGE_IDLE) { 1139 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
1575 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE); 1140 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1576 if (sc->ps_idle) 1141 if (sc->ps_idle) {
1577 ath_cancel_work(sc); 1142 ath_cancel_work(sc);
1578 else 1143 ath9k_stop_btcoex(sc);
1144 } else {
1145 ath9k_start_btcoex(sc);
1579 /* 1146 /*
1580 * The chip needs a reset to properly wake up from 1147 * The chip needs a reset to properly wake up from
1581 * full sleep 1148 * full sleep
1582 */ 1149 */
1583 reset_channel = ah->chip_fullsleep; 1150 reset_channel = ah->chip_fullsleep;
1151 }
1584 } 1152 }
1585 1153
1586 /* 1154 /*
@@ -1618,11 +1186,6 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
1618 if (ah->curchan) 1186 if (ah->curchan)
1619 old_pos = ah->curchan - &ah->channels[0]; 1187 old_pos = ah->curchan - &ah->channels[0];
1620 1188
1621 if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)
1622 sc->sc_flags |= SC_OP_OFFCHANNEL;
1623 else
1624 sc->sc_flags &= ~SC_OP_OFFCHANNEL;
1625
1626 ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n", 1189 ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n",
1627 curchan->center_freq, conf->channel_type); 1190 curchan->center_freq, conf->channel_type);
1628 1191
@@ -1664,6 +1227,7 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
1664 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) { 1227 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
1665 ath_err(common, "Unable to set channel\n"); 1228 ath_err(common, "Unable to set channel\n");
1666 mutex_unlock(&sc->mutex); 1229 mutex_unlock(&sc->mutex);
1230 ath9k_ps_restore(sc);
1667 return -EINVAL; 1231 return -EINVAL;
1668 } 1232 }
1669 1233
@@ -1902,16 +1466,16 @@ static void ath9k_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1902 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1466 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1903 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; 1467 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
1904 struct ath_vif *avp = (void *)vif->drv_priv; 1468 struct ath_vif *avp = (void *)vif->drv_priv;
1905 1469 unsigned long flags;
1906 /* 1470 /*
1907 * Skip iteration if primary station vif's bss info 1471 * Skip iteration if primary station vif's bss info
1908 * was not changed 1472 * was not changed
1909 */ 1473 */
1910 if (sc->sc_flags & SC_OP_PRIM_STA_VIF) 1474 if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags))
1911 return; 1475 return;
1912 1476
1913 if (bss_conf->assoc) { 1477 if (bss_conf->assoc) {
1914 sc->sc_flags |= SC_OP_PRIM_STA_VIF; 1478 set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
1915 avp->primary_sta_vif = true; 1479 avp->primary_sta_vif = true;
1916 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); 1480 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1917 common->curaid = bss_conf->aid; 1481 common->curaid = bss_conf->aid;
@@ -1924,7 +1488,10 @@ static void ath9k_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1924 * on the receipt of the first Beacon frame (i.e., 1488 * on the receipt of the first Beacon frame (i.e.,
1925 * after time sync with the AP). 1489 * after time sync with the AP).
1926 */ 1490 */
1491 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1927 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; 1492 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1493 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1494
1928 /* Reset rssi stats */ 1495 /* Reset rssi stats */
1929 sc->last_rssi = ATH_RSSI_DUMMY_MARKER; 1496 sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
1930 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; 1497 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
@@ -1932,7 +1499,7 @@ static void ath9k_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1932 ath_start_rx_poll(sc, 3); 1499 ath_start_rx_poll(sc, 3);
1933 1500
1934 if (!common->disable_ani) { 1501 if (!common->disable_ani) {
1935 sc->sc_flags |= SC_OP_ANI_RUN; 1502 set_bit(SC_OP_ANI_RUN, &sc->sc_flags);
1936 ath_start_ani(common); 1503 ath_start_ani(common);
1937 } 1504 }
1938 1505
@@ -1952,7 +1519,8 @@ static void ath9k_config_bss(struct ath_softc *sc, struct ieee80211_vif *vif)
1952 if (avp->primary_sta_vif && !bss_conf->assoc) { 1519 if (avp->primary_sta_vif && !bss_conf->assoc) {
1953 ath_dbg(common, CONFIG, "Bss Info DISASSOC %d, bssid %pM\n", 1520 ath_dbg(common, CONFIG, "Bss Info DISASSOC %d, bssid %pM\n",
1954 common->curaid, common->curbssid); 1521 common->curaid, common->curbssid);
1955 sc->sc_flags &= ~(SC_OP_PRIM_STA_VIF | SC_OP_BEACONS); 1522 clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
1523 clear_bit(SC_OP_BEACONS, &sc->sc_flags);
1956 avp->primary_sta_vif = false; 1524 avp->primary_sta_vif = false;
1957 memset(common->curbssid, 0, ETH_ALEN); 1525 memset(common->curbssid, 0, ETH_ALEN);
1958 common->curaid = 0; 1526 common->curaid = 0;
@@ -1965,10 +1533,9 @@ static void ath9k_config_bss(struct ath_softc *sc, struct ieee80211_vif *vif)
1965 * None of station vifs are associated. 1533 * None of station vifs are associated.
1966 * Clear bssid & aid 1534 * Clear bssid & aid
1967 */ 1535 */
1968 if (!(sc->sc_flags & SC_OP_PRIM_STA_VIF)) { 1536 if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
1969 ath9k_hw_write_associd(sc->sc_ah); 1537 ath9k_hw_write_associd(sc->sc_ah);
1970 /* Stop ANI */ 1538 clear_bit(SC_OP_ANI_RUN, &sc->sc_flags);
1971 sc->sc_flags &= ~SC_OP_ANI_RUN;
1972 del_timer_sync(&common->ani.timer); 1539 del_timer_sync(&common->ani.timer);
1973 del_timer_sync(&sc->rx_poll_timer); 1540 del_timer_sync(&sc->rx_poll_timer);
1974 memset(&sc->caldata, 0, sizeof(sc->caldata)); 1541 memset(&sc->caldata, 0, sizeof(sc->caldata));
@@ -2006,12 +1573,12 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2006 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; 1573 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
2007 1574
2008 if (!common->disable_ani) { 1575 if (!common->disable_ani) {
2009 sc->sc_flags |= SC_OP_ANI_RUN; 1576 set_bit(SC_OP_ANI_RUN, &sc->sc_flags);
2010 ath_start_ani(common); 1577 ath_start_ani(common);
2011 } 1578 }
2012 1579
2013 } else { 1580 } else {
2014 sc->sc_flags &= ~SC_OP_ANI_RUN; 1581 clear_bit(SC_OP_ANI_RUN, &sc->sc_flags);
2015 del_timer_sync(&common->ani.timer); 1582 del_timer_sync(&common->ani.timer);
2016 del_timer_sync(&sc->rx_poll_timer); 1583 del_timer_sync(&sc->rx_poll_timer);
2017 } 1584 }
@@ -2023,7 +1590,7 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2023 */ 1590 */
2024 if ((changed & BSS_CHANGED_BEACON_INT) && 1591 if ((changed & BSS_CHANGED_BEACON_INT) &&
2025 (vif->type == NL80211_IFTYPE_AP)) 1592 (vif->type == NL80211_IFTYPE_AP))
2026 sc->sc_flags |= SC_OP_TSF_RESET; 1593 set_bit(SC_OP_TSF_RESET, &sc->sc_flags);
2027 1594
2028 /* Configure beaconing (AP, IBSS, MESH) */ 1595 /* Configure beaconing (AP, IBSS, MESH) */
2029 if (ath9k_uses_beacons(vif->type) && 1596 if (ath9k_uses_beacons(vif->type) &&
@@ -2215,7 +1782,7 @@ static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
2215 return; 1782 return;
2216 } 1783 }
2217 1784
2218 if (sc->sc_flags & SC_OP_INVALID) { 1785 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
2219 ath_dbg(common, ANY, "Device not present\n"); 1786 ath_dbg(common, ANY, "Device not present\n");
2220 mutex_unlock(&sc->mutex); 1787 mutex_unlock(&sc->mutex);
2221 return; 1788 return;
@@ -2380,6 +1947,134 @@ static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
2380 return 0; 1947 return 0;
2381} 1948}
2382 1949
1950#ifdef CONFIG_ATH9K_DEBUGFS
1951
1952/* Ethtool support for get-stats */
1953
1954#define AMKSTR(nm) #nm "_BE", #nm "_BK", #nm "_VI", #nm "_VO"
1955static const char ath9k_gstrings_stats[][ETH_GSTRING_LEN] = {
1956 "tx_pkts_nic",
1957 "tx_bytes_nic",
1958 "rx_pkts_nic",
1959 "rx_bytes_nic",
1960 AMKSTR(d_tx_pkts),
1961 AMKSTR(d_tx_bytes),
1962 AMKSTR(d_tx_mpdus_queued),
1963 AMKSTR(d_tx_mpdus_completed),
1964 AMKSTR(d_tx_mpdu_xretries),
1965 AMKSTR(d_tx_aggregates),
1966 AMKSTR(d_tx_ampdus_queued_hw),
1967 AMKSTR(d_tx_ampdus_queued_sw),
1968 AMKSTR(d_tx_ampdus_completed),
1969 AMKSTR(d_tx_ampdu_retries),
1970 AMKSTR(d_tx_ampdu_xretries),
1971 AMKSTR(d_tx_fifo_underrun),
1972 AMKSTR(d_tx_op_exceeded),
1973 AMKSTR(d_tx_timer_expiry),
1974 AMKSTR(d_tx_desc_cfg_err),
1975 AMKSTR(d_tx_data_underrun),
1976 AMKSTR(d_tx_delim_underrun),
1977
1978 "d_rx_decrypt_crc_err",
1979 "d_rx_phy_err",
1980 "d_rx_mic_err",
1981 "d_rx_pre_delim_crc_err",
1982 "d_rx_post_delim_crc_err",
1983 "d_rx_decrypt_busy_err",
1984
1985 "d_rx_phyerr_radar",
1986 "d_rx_phyerr_ofdm_timing",
1987 "d_rx_phyerr_cck_timing",
1988
1989};
1990#define ATH9K_SSTATS_LEN ARRAY_SIZE(ath9k_gstrings_stats)
1991
1992static void ath9k_get_et_strings(struct ieee80211_hw *hw,
1993 struct ieee80211_vif *vif,
1994 u32 sset, u8 *data)
1995{
1996 if (sset == ETH_SS_STATS)
1997 memcpy(data, *ath9k_gstrings_stats,
1998 sizeof(ath9k_gstrings_stats));
1999}
2000
2001static int ath9k_get_et_sset_count(struct ieee80211_hw *hw,
2002 struct ieee80211_vif *vif, int sset)
2003{
2004 if (sset == ETH_SS_STATS)
2005 return ATH9K_SSTATS_LEN;
2006 return 0;
2007}
2008
2009#define PR_QNUM(_n) (sc->tx.txq_map[_n]->axq_qnum)
2010#define AWDATA(elem) \
2011 do { \
2012 data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].elem; \
2013 data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].elem; \
2014 data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].elem; \
2015 data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].elem; \
2016 } while (0)
2017
2018#define AWDATA_RX(elem) \
2019 do { \
2020 data[i++] = sc->debug.stats.rxstats.elem; \
2021 } while (0)
2022
2023static void ath9k_get_et_stats(struct ieee80211_hw *hw,
2024 struct ieee80211_vif *vif,
2025 struct ethtool_stats *stats, u64 *data)
2026{
2027 struct ath_softc *sc = hw->priv;
2028 int i = 0;
2029
2030 data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_pkts_all +
2031 sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_pkts_all +
2032 sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_pkts_all +
2033 sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_pkts_all);
2034 data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_bytes_all +
2035 sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_bytes_all +
2036 sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_bytes_all +
2037 sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_bytes_all);
2038 AWDATA_RX(rx_pkts_all);
2039 AWDATA_RX(rx_bytes_all);
2040
2041 AWDATA(tx_pkts_all);
2042 AWDATA(tx_bytes_all);
2043 AWDATA(queued);
2044 AWDATA(completed);
2045 AWDATA(xretries);
2046 AWDATA(a_aggr);
2047 AWDATA(a_queued_hw);
2048 AWDATA(a_queued_sw);
2049 AWDATA(a_completed);
2050 AWDATA(a_retries);
2051 AWDATA(a_xretries);
2052 AWDATA(fifo_underrun);
2053 AWDATA(xtxop);
2054 AWDATA(timer_exp);
2055 AWDATA(desc_cfg_err);
2056 AWDATA(data_underrun);
2057 AWDATA(delim_underrun);
2058
2059 AWDATA_RX(decrypt_crc_err);
2060 AWDATA_RX(phy_err);
2061 AWDATA_RX(mic_err);
2062 AWDATA_RX(pre_delim_crc_err);
2063 AWDATA_RX(post_delim_crc_err);
2064 AWDATA_RX(decrypt_busy_err);
2065
2066 AWDATA_RX(phy_err_stats[ATH9K_PHYERR_RADAR]);
2067 AWDATA_RX(phy_err_stats[ATH9K_PHYERR_OFDM_TIMING]);
2068 AWDATA_RX(phy_err_stats[ATH9K_PHYERR_CCK_TIMING]);
2069
2070 WARN_ON(i != ATH9K_SSTATS_LEN);
2071}
2072
2073/* End of ethtool get-stats functions */
2074
2075#endif
2076
2077
2383struct ieee80211_ops ath9k_ops = { 2078struct ieee80211_ops ath9k_ops = {
2384 .tx = ath9k_tx, 2079 .tx = ath9k_tx,
2385 .start = ath9k_start, 2080 .start = ath9k_start,
@@ -2408,4 +2103,10 @@ struct ieee80211_ops ath9k_ops = {
2408 .get_stats = ath9k_get_stats, 2103 .get_stats = ath9k_get_stats,
2409 .set_antenna = ath9k_set_antenna, 2104 .set_antenna = ath9k_set_antenna,
2410 .get_antenna = ath9k_get_antenna, 2105 .get_antenna = ath9k_get_antenna,
2106
2107#ifdef CONFIG_ATH9K_DEBUGFS
2108 .get_et_sset_count = ath9k_get_et_sset_count,
2109 .get_et_stats = ath9k_get_et_stats,
2110 .get_et_strings = ath9k_get_et_strings,
2111#endif
2411}; 2112};
diff --git a/drivers/net/wireless/ath/ath9k/mci.c b/drivers/net/wireless/ath/ath9k/mci.c
index 29fe52d69973..87acff7fdaae 100644
--- a/drivers/net/wireless/ath/ath9k/mci.c
+++ b/drivers/net/wireless/ath/ath9k/mci.c
@@ -20,7 +20,7 @@
20#include "ath9k.h" 20#include "ath9k.h"
21#include "mci.h" 21#include "mci.h"
22 22
23static const u8 ath_mci_duty_cycle[] = { 0, 50, 60, 70, 80, 85, 90, 95, 98 }; 23static const u8 ath_mci_duty_cycle[] = { 55, 50, 60, 70, 80, 85, 90, 95, 98 };
24 24
25static struct ath_mci_profile_info* 25static struct ath_mci_profile_info*
26ath_mci_find_profile(struct ath_mci_profile *mci, 26ath_mci_find_profile(struct ath_mci_profile *mci,
@@ -28,11 +28,14 @@ ath_mci_find_profile(struct ath_mci_profile *mci,
28{ 28{
29 struct ath_mci_profile_info *entry; 29 struct ath_mci_profile_info *entry;
30 30
31 if (list_empty(&mci->info))
32 return NULL;
33
31 list_for_each_entry(entry, &mci->info, list) { 34 list_for_each_entry(entry, &mci->info, list) {
32 if (entry->conn_handle == info->conn_handle) 35 if (entry->conn_handle == info->conn_handle)
33 break; 36 return entry;
34 } 37 }
35 return entry; 38 return NULL;
36} 39}
37 40
38static bool ath_mci_add_profile(struct ath_common *common, 41static bool ath_mci_add_profile(struct ath_common *common,
@@ -49,31 +52,21 @@ static bool ath_mci_add_profile(struct ath_common *common,
49 (info->type != MCI_GPM_COEX_PROFILE_VOICE)) 52 (info->type != MCI_GPM_COEX_PROFILE_VOICE))
50 return false; 53 return false;
51 54
52 entry = ath_mci_find_profile(mci, info); 55 entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
56 if (!entry)
57 return false;
53 58
54 if (entry) { 59 memcpy(entry, info, 10);
55 memcpy(entry, info, 10); 60 INC_PROF(mci, info);
56 } else { 61 list_add_tail(&entry->list, &mci->info);
57 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
58 if (!entry)
59 return false;
60
61 memcpy(entry, info, 10);
62 INC_PROF(mci, info);
63 list_add_tail(&info->list, &mci->info);
64 }
65 62
66 return true; 63 return true;
67} 64}
68 65
69static void ath_mci_del_profile(struct ath_common *common, 66static void ath_mci_del_profile(struct ath_common *common,
70 struct ath_mci_profile *mci, 67 struct ath_mci_profile *mci,
71 struct ath_mci_profile_info *info) 68 struct ath_mci_profile_info *entry)
72{ 69{
73 struct ath_mci_profile_info *entry;
74
75 entry = ath_mci_find_profile(mci, info);
76
77 if (!entry) 70 if (!entry)
78 return; 71 return;
79 72
@@ -86,12 +79,16 @@ void ath_mci_flush_profile(struct ath_mci_profile *mci)
86{ 79{
87 struct ath_mci_profile_info *info, *tinfo; 80 struct ath_mci_profile_info *info, *tinfo;
88 81
82 mci->aggr_limit = 0;
83
84 if (list_empty(&mci->info))
85 return;
86
89 list_for_each_entry_safe(info, tinfo, &mci->info, list) { 87 list_for_each_entry_safe(info, tinfo, &mci->info, list) {
90 list_del(&info->list); 88 list_del(&info->list);
91 DEC_PROF(mci, info); 89 DEC_PROF(mci, info);
92 kfree(info); 90 kfree(info);
93 } 91 }
94 mci->aggr_limit = 0;
95} 92}
96 93
97static void ath_mci_adjust_aggr_limit(struct ath_btcoex *btcoex) 94static void ath_mci_adjust_aggr_limit(struct ath_btcoex *btcoex)
@@ -116,42 +113,60 @@ static void ath_mci_update_scheme(struct ath_softc *sc)
116 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 113 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
117 struct ath_btcoex *btcoex = &sc->btcoex; 114 struct ath_btcoex *btcoex = &sc->btcoex;
118 struct ath_mci_profile *mci = &btcoex->mci; 115 struct ath_mci_profile *mci = &btcoex->mci;
116 struct ath9k_hw_mci *mci_hw = &sc->sc_ah->btcoex_hw.mci;
119 struct ath_mci_profile_info *info; 117 struct ath_mci_profile_info *info;
120 u32 num_profile = NUM_PROF(mci); 118 u32 num_profile = NUM_PROF(mci);
121 119
120 if (mci_hw->config & ATH_MCI_CONFIG_DISABLE_TUNING)
121 goto skip_tuning;
122
123 btcoex->duty_cycle = ath_mci_duty_cycle[num_profile];
124
122 if (num_profile == 1) { 125 if (num_profile == 1) {
123 info = list_first_entry(&mci->info, 126 info = list_first_entry(&mci->info,
124 struct ath_mci_profile_info, 127 struct ath_mci_profile_info,
125 list); 128 list);
126 if (mci->num_sco && info->T == 12) { 129 if (mci->num_sco) {
127 mci->aggr_limit = 8; 130 if (info->T == 12)
131 mci->aggr_limit = 8;
132 else if (info->T == 6) {
133 mci->aggr_limit = 6;
134 btcoex->duty_cycle = 30;
135 }
128 ath_dbg(common, MCI, 136 ath_dbg(common, MCI,
129 "Single SCO, aggregation limit 2 ms\n"); 137 "Single SCO, aggregation limit %d 1/4 ms\n",
130 } else if ((info->type == MCI_GPM_COEX_PROFILE_BNEP) && 138 mci->aggr_limit);
131 !info->master) { 139 } else if (mci->num_pan || mci->num_other_acl) {
132 btcoex->btcoex_period = 60; 140 /*
141 * For single PAN/FTP profile, allocate 35% for BT
142 * to improve WLAN throughput.
143 */
144 btcoex->duty_cycle = 35;
145 btcoex->btcoex_period = 53;
133 ath_dbg(common, MCI, 146 ath_dbg(common, MCI,
134 "Single slave PAN/FTP, bt period 60 ms\n"); 147 "Single PAN/FTP bt period %d ms dutycycle %d\n",
135 } else if ((info->type == MCI_GPM_COEX_PROFILE_HID) && 148 btcoex->duty_cycle, btcoex->btcoex_period);
136 (info->T > 0 && info->T < 50) && 149 } else if (mci->num_hid) {
137 (info->A > 1 || info->W > 1)) {
138 btcoex->duty_cycle = 30; 150 btcoex->duty_cycle = 30;
139 mci->aggr_limit = 8; 151 mci->aggr_limit = 6;
140 ath_dbg(common, MCI, 152 ath_dbg(common, MCI,
141 "Multiple attempt/timeout single HID " 153 "Multiple attempt/timeout single HID "
142 "aggregation limit 2 ms dutycycle 30%%\n"); 154 "aggregation limit 1.5 ms dutycycle 30%%\n");
143 } 155 }
144 } else if ((num_profile == 2) && (mci->num_hid == 2)) { 156 } else if (num_profile == 2) {
145 btcoex->duty_cycle = 30; 157 if (mci->num_hid == 2)
146 mci->aggr_limit = 8; 158 btcoex->duty_cycle = 30;
147 ath_dbg(common, MCI,
148 "Two HIDs aggregation limit 2 ms dutycycle 30%%\n");
149 } else if (num_profile > 3) {
150 mci->aggr_limit = 6; 159 mci->aggr_limit = 6;
151 ath_dbg(common, MCI, 160 ath_dbg(common, MCI,
152 "Three or more profiles aggregation limit 1.5 ms\n"); 161 "Two BT profiles aggr limit 1.5 ms dutycycle %d%%\n",
162 btcoex->duty_cycle);
163 } else if (num_profile >= 3) {
164 mci->aggr_limit = 4;
165 ath_dbg(common, MCI,
166 "Three or more profiles aggregation limit 1 ms\n");
153 } 167 }
154 168
169skip_tuning:
155 if (IS_CHAN_2GHZ(sc->sc_ah->curchan)) { 170 if (IS_CHAN_2GHZ(sc->sc_ah->curchan)) {
156 if (IS_CHAN_HT(sc->sc_ah->curchan)) 171 if (IS_CHAN_HT(sc->sc_ah->curchan))
157 ath_mci_adjust_aggr_limit(btcoex); 172 ath_mci_adjust_aggr_limit(btcoex);
@@ -159,18 +174,17 @@ static void ath_mci_update_scheme(struct ath_softc *sc)
159 btcoex->btcoex_period >>= 1; 174 btcoex->btcoex_period >>= 1;
160 } 175 }
161 176
162 ath9k_hw_btcoex_disable(sc->sc_ah);
163 ath9k_btcoex_timer_pause(sc); 177 ath9k_btcoex_timer_pause(sc);
178 ath9k_hw_btcoex_disable(sc->sc_ah);
164 179
165 if (IS_CHAN_5GHZ(sc->sc_ah->curchan)) 180 if (IS_CHAN_5GHZ(sc->sc_ah->curchan))
166 return; 181 return;
167 182
168 btcoex->duty_cycle += (mci->num_bdr ? ATH_MCI_MAX_DUTY_CYCLE : 0); 183 btcoex->duty_cycle += (mci->num_bdr ? ATH_MCI_BDR_DUTY_CYCLE : 0);
169 if (btcoex->duty_cycle > ATH_MCI_MAX_DUTY_CYCLE) 184 if (btcoex->duty_cycle > ATH_MCI_MAX_DUTY_CYCLE)
170 btcoex->duty_cycle = ATH_MCI_MAX_DUTY_CYCLE; 185 btcoex->duty_cycle = ATH_MCI_MAX_DUTY_CYCLE;
171 186
172 btcoex->btcoex_period *= 1000; 187 btcoex->btcoex_no_stomp = btcoex->btcoex_period * 1000 *
173 btcoex->btcoex_no_stomp = btcoex->btcoex_period *
174 (100 - btcoex->duty_cycle) / 100; 188 (100 - btcoex->duty_cycle) / 100;
175 189
176 ath9k_hw_btcoex_enable(sc->sc_ah); 190 ath9k_hw_btcoex_enable(sc->sc_ah);
@@ -181,20 +195,16 @@ static void ath_mci_cal_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload)
181{ 195{
182 struct ath_hw *ah = sc->sc_ah; 196 struct ath_hw *ah = sc->sc_ah;
183 struct ath_common *common = ath9k_hw_common(ah); 197 struct ath_common *common = ath9k_hw_common(ah);
198 struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
184 u32 payload[4] = {0, 0, 0, 0}; 199 u32 payload[4] = {0, 0, 0, 0};
185 200
186 switch (opcode) { 201 switch (opcode) {
187 case MCI_GPM_BT_CAL_REQ: 202 case MCI_GPM_BT_CAL_REQ:
188 if (ar9003_mci_state(ah, MCI_STATE_BT, NULL) == MCI_BT_AWAKE) { 203 if (mci_hw->bt_state == MCI_BT_AWAKE) {
189 ar9003_mci_state(ah, MCI_STATE_SET_BT_CAL_START, NULL); 204 ar9003_mci_state(ah, MCI_STATE_SET_BT_CAL_START);
190 ieee80211_queue_work(sc->hw, &sc->hw_reset_work); 205 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
191 } else {
192 ath_dbg(common, MCI, "MCI State mismatch: %d\n",
193 ar9003_mci_state(ah, MCI_STATE_BT, NULL));
194 } 206 }
195 break; 207 ath_dbg(common, MCI, "MCI State : %d\n", mci_hw->bt_state);
196 case MCI_GPM_BT_CAL_DONE:
197 ar9003_mci_state(ah, MCI_STATE_BT, NULL);
198 break; 208 break;
199 case MCI_GPM_BT_CAL_GRANT: 209 case MCI_GPM_BT_CAL_GRANT:
200 MCI_GPM_SET_CAL_TYPE(payload, MCI_GPM_WLAN_CAL_DONE); 210 MCI_GPM_SET_CAL_TYPE(payload, MCI_GPM_WLAN_CAL_DONE);
@@ -207,32 +217,55 @@ static void ath_mci_cal_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload)
207 } 217 }
208} 218}
209 219
220static void ath9k_mci_work(struct work_struct *work)
221{
222 struct ath_softc *sc = container_of(work, struct ath_softc, mci_work);
223
224 ath_mci_update_scheme(sc);
225}
226
210static void ath_mci_process_profile(struct ath_softc *sc, 227static void ath_mci_process_profile(struct ath_softc *sc,
211 struct ath_mci_profile_info *info) 228 struct ath_mci_profile_info *info)
212{ 229{
213 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 230 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
214 struct ath_btcoex *btcoex = &sc->btcoex; 231 struct ath_btcoex *btcoex = &sc->btcoex;
215 struct ath_mci_profile *mci = &btcoex->mci; 232 struct ath_mci_profile *mci = &btcoex->mci;
233 struct ath_mci_profile_info *entry = NULL;
234
235 entry = ath_mci_find_profile(mci, info);
236 if (entry) {
237 /*
238 * Two MCI interrupts are generated while connecting to
239 * headset and A2DP profile, but only one MCI interrupt
240 * is generated with last added profile type while disconnecting
241 * both profiles.
242 * So while adding second profile type decrement
243 * the first one.
244 */
245 if (entry->type != info->type) {
246 DEC_PROF(mci, entry);
247 INC_PROF(mci, info);
248 }
249 memcpy(entry, info, 10);
250 }
216 251
217 if (info->start) { 252 if (info->start) {
218 if (!ath_mci_add_profile(common, mci, info)) 253 if (!entry && !ath_mci_add_profile(common, mci, info))
219 return; 254 return;
220 } else 255 } else
221 ath_mci_del_profile(common, mci, info); 256 ath_mci_del_profile(common, mci, entry);
222 257
223 btcoex->btcoex_period = ATH_MCI_DEF_BT_PERIOD; 258 btcoex->btcoex_period = ATH_MCI_DEF_BT_PERIOD;
224 mci->aggr_limit = mci->num_sco ? 6 : 0; 259 mci->aggr_limit = mci->num_sco ? 6 : 0;
225 260
226 if (NUM_PROF(mci)) { 261 btcoex->duty_cycle = ath_mci_duty_cycle[NUM_PROF(mci)];
262 if (NUM_PROF(mci))
227 btcoex->bt_stomp_type = ATH_BTCOEX_STOMP_LOW; 263 btcoex->bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
228 btcoex->duty_cycle = ath_mci_duty_cycle[NUM_PROF(mci)]; 264 else
229 } else {
230 btcoex->bt_stomp_type = mci->num_mgmt ? ATH_BTCOEX_STOMP_ALL : 265 btcoex->bt_stomp_type = mci->num_mgmt ? ATH_BTCOEX_STOMP_ALL :
231 ATH_BTCOEX_STOMP_LOW; 266 ATH_BTCOEX_STOMP_LOW;
232 btcoex->duty_cycle = ATH_BTCOEX_DEF_DUTY_CYCLE;
233 }
234 267
235 ath_mci_update_scheme(sc); 268 ieee80211_queue_work(sc->hw, &sc->mci_work);
236} 269}
237 270
238static void ath_mci_process_status(struct ath_softc *sc, 271static void ath_mci_process_status(struct ath_softc *sc,
@@ -247,8 +280,6 @@ static void ath_mci_process_status(struct ath_softc *sc,
247 if (status->is_link) 280 if (status->is_link)
248 return; 281 return;
249 282
250 memset(&info, 0, sizeof(struct ath_mci_profile_info));
251
252 info.conn_handle = status->conn_handle; 283 info.conn_handle = status->conn_handle;
253 if (ath_mci_find_profile(mci, &info)) 284 if (ath_mci_find_profile(mci, &info))
254 return; 285 return;
@@ -268,7 +299,7 @@ static void ath_mci_process_status(struct ath_softc *sc,
268 } while (++i < ATH_MCI_MAX_PROFILE); 299 } while (++i < ATH_MCI_MAX_PROFILE);
269 300
270 if (old_num_mgmt != mci->num_mgmt) 301 if (old_num_mgmt != mci->num_mgmt)
271 ath_mci_update_scheme(sc); 302 ieee80211_queue_work(sc->hw, &sc->mci_work);
272} 303}
273 304
274static void ath_mci_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload) 305static void ath_mci_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload)
@@ -277,25 +308,20 @@ static void ath_mci_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload)
277 struct ath_mci_profile_info profile_info; 308 struct ath_mci_profile_info profile_info;
278 struct ath_mci_profile_status profile_status; 309 struct ath_mci_profile_status profile_status;
279 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 310 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
280 u32 version; 311 u8 major, minor;
281 u8 major;
282 u8 minor;
283 u32 seq_num; 312 u32 seq_num;
284 313
285 switch (opcode) { 314 switch (opcode) {
286 case MCI_GPM_COEX_VERSION_QUERY: 315 case MCI_GPM_COEX_VERSION_QUERY:
287 version = ar9003_mci_state(ah, MCI_STATE_SEND_WLAN_COEX_VERSION, 316 ar9003_mci_state(ah, MCI_STATE_SEND_WLAN_COEX_VERSION);
288 NULL);
289 break; 317 break;
290 case MCI_GPM_COEX_VERSION_RESPONSE: 318 case MCI_GPM_COEX_VERSION_RESPONSE:
291 major = *(rx_payload + MCI_GPM_COEX_B_MAJOR_VERSION); 319 major = *(rx_payload + MCI_GPM_COEX_B_MAJOR_VERSION);
292 minor = *(rx_payload + MCI_GPM_COEX_B_MINOR_VERSION); 320 minor = *(rx_payload + MCI_GPM_COEX_B_MINOR_VERSION);
293 version = (major << 8) + minor; 321 ar9003_mci_set_bt_version(ah, major, minor);
294 version = ar9003_mci_state(ah, MCI_STATE_SET_BT_COEX_VERSION,
295 &version);
296 break; 322 break;
297 case MCI_GPM_COEX_STATUS_QUERY: 323 case MCI_GPM_COEX_STATUS_QUERY:
298 ar9003_mci_state(ah, MCI_STATE_SEND_WLAN_CHANNELS, NULL); 324 ar9003_mci_send_wlan_channels(ah);
299 break; 325 break;
300 case MCI_GPM_COEX_BT_PROFILE_INFO: 326 case MCI_GPM_COEX_BT_PROFILE_INFO:
301 memcpy(&profile_info, 327 memcpy(&profile_info,
@@ -322,7 +348,7 @@ static void ath_mci_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload)
322 348
323 seq_num = *((u32 *)(rx_payload + 12)); 349 seq_num = *((u32 *)(rx_payload + 12));
324 ath_dbg(common, MCI, 350 ath_dbg(common, MCI,
325 "BT_Status_Update: is_link=%d, linkId=%d, state=%d, SEQ=%d\n", 351 "BT_Status_Update: is_link=%d, linkId=%d, state=%d, SEQ=%u\n",
326 profile_status.is_link, profile_status.conn_handle, 352 profile_status.is_link, profile_status.conn_handle,
327 profile_status.is_critical, seq_num); 353 profile_status.is_critical, seq_num);
328 354
@@ -362,6 +388,7 @@ int ath_mci_setup(struct ath_softc *sc)
362 mci->gpm_buf.bf_addr, (mci->gpm_buf.bf_len >> 4), 388 mci->gpm_buf.bf_addr, (mci->gpm_buf.bf_len >> 4),
363 mci->sched_buf.bf_paddr); 389 mci->sched_buf.bf_paddr);
364 390
391 INIT_WORK(&sc->mci_work, ath9k_mci_work);
365 ath_dbg(common, MCI, "MCI Initialized\n"); 392 ath_dbg(common, MCI, "MCI Initialized\n");
366 393
367 return 0; 394 return 0;
@@ -389,6 +416,7 @@ void ath_mci_intr(struct ath_softc *sc)
389 struct ath_mci_coex *mci = &sc->mci_coex; 416 struct ath_mci_coex *mci = &sc->mci_coex;
390 struct ath_hw *ah = sc->sc_ah; 417 struct ath_hw *ah = sc->sc_ah;
391 struct ath_common *common = ath9k_hw_common(ah); 418 struct ath_common *common = ath9k_hw_common(ah);
419 struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
392 u32 mci_int, mci_int_rxmsg; 420 u32 mci_int, mci_int_rxmsg;
393 u32 offset, subtype, opcode; 421 u32 offset, subtype, opcode;
394 u32 *pgpm; 422 u32 *pgpm;
@@ -397,8 +425,8 @@ void ath_mci_intr(struct ath_softc *sc)
397 425
398 ar9003_mci_get_interrupt(sc->sc_ah, &mci_int, &mci_int_rxmsg); 426 ar9003_mci_get_interrupt(sc->sc_ah, &mci_int, &mci_int_rxmsg);
399 427
400 if (ar9003_mci_state(ah, MCI_STATE_ENABLE, NULL) == 0) { 428 if (ar9003_mci_state(ah, MCI_STATE_ENABLE) == 0) {
401 ar9003_mci_state(ah, MCI_STATE_INIT_GPM_OFFSET, NULL); 429 ar9003_mci_get_next_gpm_offset(ah, true, NULL);
402 return; 430 return;
403 } 431 }
404 432
@@ -417,46 +445,41 @@ void ath_mci_intr(struct ath_softc *sc)
417 NULL, 0, true, false); 445 NULL, 0, true, false);
418 446
419 mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE; 447 mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE;
420 ar9003_mci_state(ah, MCI_STATE_RESET_REQ_WAKE, NULL); 448 ar9003_mci_state(ah, MCI_STATE_RESET_REQ_WAKE);
421 449
422 /* 450 /*
423 * always do this for recovery and 2G/5G toggling and LNA_TRANS 451 * always do this for recovery and 2G/5G toggling and LNA_TRANS
424 */ 452 */
425 ar9003_mci_state(ah, MCI_STATE_SET_BT_AWAKE, NULL); 453 ar9003_mci_state(ah, MCI_STATE_SET_BT_AWAKE);
426 } 454 }
427 455
428 if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING) { 456 if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING) {
429 mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING; 457 mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING;
430 458
431 if (ar9003_mci_state(ah, MCI_STATE_BT, NULL) == MCI_BT_SLEEP) { 459 if ((mci_hw->bt_state == MCI_BT_SLEEP) &&
432 if (ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP, NULL) != 460 (ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP) !=
433 MCI_BT_SLEEP) 461 MCI_BT_SLEEP))
434 ar9003_mci_state(ah, MCI_STATE_SET_BT_AWAKE, 462 ar9003_mci_state(ah, MCI_STATE_SET_BT_AWAKE);
435 NULL);
436 }
437 } 463 }
438 464
439 if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING) { 465 if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING) {
440 mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING; 466 mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING;
441 467
442 if (ar9003_mci_state(ah, MCI_STATE_BT, NULL) == MCI_BT_AWAKE) { 468 if ((mci_hw->bt_state == MCI_BT_AWAKE) &&
443 if (ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP, NULL) != 469 (ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP) !=
444 MCI_BT_AWAKE) 470 MCI_BT_AWAKE))
445 ar9003_mci_state(ah, MCI_STATE_SET_BT_SLEEP, 471 mci_hw->bt_state = MCI_BT_SLEEP;
446 NULL);
447 }
448 } 472 }
449 473
450 if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) || 474 if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) ||
451 (mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT)) { 475 (mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT)) {
452 ar9003_mci_state(ah, MCI_STATE_RECOVER_RX, NULL); 476 ar9003_mci_state(ah, MCI_STATE_RECOVER_RX);
453 skip_gpm = true; 477 skip_gpm = true;
454 } 478 }
455 479
456 if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO) { 480 if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO) {
457 mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO; 481 mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO;
458 offset = ar9003_mci_state(ah, MCI_STATE_LAST_SCHD_MSG_OFFSET, 482 offset = ar9003_mci_state(ah, MCI_STATE_LAST_SCHD_MSG_OFFSET);
459 NULL);
460 } 483 }
461 484
462 if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_GPM) { 485 if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_GPM) {
@@ -465,8 +488,8 @@ void ath_mci_intr(struct ath_softc *sc)
465 while (more_data == MCI_GPM_MORE) { 488 while (more_data == MCI_GPM_MORE) {
466 489
467 pgpm = mci->gpm_buf.bf_addr; 490 pgpm = mci->gpm_buf.bf_addr;
468 offset = ar9003_mci_state(ah, MCI_STATE_NEXT_GPM_OFFSET, 491 offset = ar9003_mci_get_next_gpm_offset(ah, false,
469 &more_data); 492 &more_data);
470 493
471 if (offset == MCI_GPM_INVALID) 494 if (offset == MCI_GPM_INVALID)
472 break; 495 break;
@@ -507,23 +530,17 @@ void ath_mci_intr(struct ath_softc *sc)
507 mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_LNA_INFO; 530 mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_LNA_INFO;
508 531
509 if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_INFO) { 532 if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_INFO) {
510 int value_dbm = ar9003_mci_state(ah, 533 int value_dbm = MS(mci_hw->cont_status,
511 MCI_STATE_CONT_RSSI_POWER, NULL); 534 AR_MCI_CONT_RSSI_POWER);
512 535
513 mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_INFO; 536 mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_INFO;
514 537
515 if (ar9003_mci_state(ah, MCI_STATE_CONT_TXRX, NULL)) 538 ath_dbg(common, MCI,
516 ath_dbg(common, MCI, 539 "MCI CONT_INFO: (%s) pri = %d pwr = %d dBm\n",
517 "MCI CONT_INFO: (tx) pri = %d, pwr = %d dBm\n", 540 MS(mci_hw->cont_status, AR_MCI_CONT_TXRX) ?
518 ar9003_mci_state(ah, 541 "tx" : "rx",
519 MCI_STATE_CONT_PRIORITY, NULL), 542 MS(mci_hw->cont_status, AR_MCI_CONT_PRIORITY),
520 value_dbm); 543 value_dbm);
521 else
522 ath_dbg(common, MCI,
523 "MCI CONT_INFO: (rx) pri = %d,pwr = %d dBm\n",
524 ar9003_mci_state(ah,
525 MCI_STATE_CONT_PRIORITY, NULL),
526 value_dbm);
527 } 544 }
528 545
529 if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_NACK) 546 if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_NACK)
@@ -538,3 +555,14 @@ void ath_mci_intr(struct ath_softc *sc)
538 mci_int &= ~(AR_MCI_INTERRUPT_RX_INVALID_HDR | 555 mci_int &= ~(AR_MCI_INTERRUPT_RX_INVALID_HDR |
539 AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT); 556 AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT);
540} 557}
558
559void ath_mci_enable(struct ath_softc *sc)
560{
561 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
562
563 if (!common->btcoex_enabled)
564 return;
565
566 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
567 sc->sc_ah->imask |= ATH9K_INT_MCI;
568}
diff --git a/drivers/net/wireless/ath/ath9k/mci.h b/drivers/net/wireless/ath/ath9k/mci.h
index c841444f53c2..fc14eea034eb 100644
--- a/drivers/net/wireless/ath/ath9k/mci.h
+++ b/drivers/net/wireless/ath/ath9k/mci.h
@@ -130,4 +130,13 @@ void ath_mci_flush_profile(struct ath_mci_profile *mci);
130int ath_mci_setup(struct ath_softc *sc); 130int ath_mci_setup(struct ath_softc *sc);
131void ath_mci_cleanup(struct ath_softc *sc); 131void ath_mci_cleanup(struct ath_softc *sc);
132void ath_mci_intr(struct ath_softc *sc); 132void ath_mci_intr(struct ath_softc *sc);
133#endif 133
134#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
135void ath_mci_enable(struct ath_softc *sc);
136#else
137static inline void ath_mci_enable(struct ath_softc *sc)
138{
139}
140#endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
141
142#endif /* MCI_H*/
diff --git a/drivers/net/wireless/ath/ath9k/pci.c b/drivers/net/wireless/ath/ath9k/pci.c
index a856b51255f4..aa0e83ac51f4 100644
--- a/drivers/net/wireless/ath/ath9k/pci.c
+++ b/drivers/net/wireless/ath/ath9k/pci.c
@@ -115,6 +115,9 @@ static void ath_pci_aspm_init(struct ath_common *common)
115 int pos; 115 int pos;
116 u8 aspm; 116 u8 aspm;
117 117
118 if (!ah->is_pciexpress)
119 return;
120
118 pos = pci_pcie_cap(pdev); 121 pos = pci_pcie_cap(pdev);
119 if (!pos) 122 if (!pos)
120 return; 123 return;
@@ -138,6 +141,7 @@ static void ath_pci_aspm_init(struct ath_common *common)
138 aspm &= ~(PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1); 141 aspm &= ~(PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
139 pci_write_config_byte(parent, pos + PCI_EXP_LNKCTL, aspm); 142 pci_write_config_byte(parent, pos + PCI_EXP_LNKCTL, aspm);
140 143
144 ath_info(common, "Disabling ASPM since BTCOEX is enabled\n");
141 return; 145 return;
142 } 146 }
143 147
@@ -147,6 +151,7 @@ static void ath_pci_aspm_init(struct ath_common *common)
147 ah->aspm_enabled = true; 151 ah->aspm_enabled = true;
148 /* Initialize PCIe PM and SERDES registers. */ 152 /* Initialize PCIe PM and SERDES registers. */
149 ath9k_hw_configpcipowersave(ah, false); 153 ath9k_hw_configpcipowersave(ah, false);
154 ath_info(common, "ASPM enabled: 0x%x\n", aspm);
150 } 155 }
151} 156}
152 157
@@ -246,7 +251,7 @@ static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
246 sc->mem = mem; 251 sc->mem = mem;
247 252
248 /* Will be cleared in ath9k_start() */ 253 /* Will be cleared in ath9k_start() */
249 sc->sc_flags |= SC_OP_INVALID; 254 set_bit(SC_OP_INVALID, &sc->sc_flags);
250 255
251 ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc); 256 ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc);
252 if (ret) { 257 if (ret) {
diff --git a/drivers/net/wireless/ath/ath9k/rc.c b/drivers/net/wireless/ath/ath9k/rc.c
index 92a6c0a87f89..e034add9cd5a 100644
--- a/drivers/net/wireless/ath/ath9k/rc.c
+++ b/drivers/net/wireless/ath/ath9k/rc.c
@@ -770,7 +770,7 @@ static void ath_get_rate(void *priv, struct ieee80211_sta *sta, void *priv_sta,
770 struct ieee80211_tx_rate *rates = tx_info->control.rates; 770 struct ieee80211_tx_rate *rates = tx_info->control.rates;
771 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 771 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
772 __le16 fc = hdr->frame_control; 772 __le16 fc = hdr->frame_control;
773 u8 try_per_rate, i = 0, rix, high_rix; 773 u8 try_per_rate, i = 0, rix;
774 int is_probe = 0; 774 int is_probe = 0;
775 775
776 if (rate_control_send_low(sta, priv_sta, txrc)) 776 if (rate_control_send_low(sta, priv_sta, txrc))
@@ -791,7 +791,6 @@ static void ath_get_rate(void *priv, struct ieee80211_sta *sta, void *priv_sta,
791 rate_table = ath_rc_priv->rate_table; 791 rate_table = ath_rc_priv->rate_table;
792 rix = ath_rc_get_highest_rix(sc, ath_rc_priv, rate_table, 792 rix = ath_rc_get_highest_rix(sc, ath_rc_priv, rate_table,
793 &is_probe, false); 793 &is_probe, false);
794 high_rix = rix;
795 794
796 /* 795 /*
797 * If we're in HT mode and both us and our peer supports LDPC. 796 * If we're in HT mode and both us and our peer supports LDPC.
@@ -839,16 +838,16 @@ static void ath_get_rate(void *priv, struct ieee80211_sta *sta, void *priv_sta,
839 try_per_rate = 8; 838 try_per_rate = 8;
840 839
841 /* 840 /*
842 * Use a legacy rate as last retry to ensure that the frame 841 * If the last rate in the rate series is MCS and has
843 * is tried in both MCS and legacy rates. 842 * more than 80% of per thresh, then use a legacy rate
843 * as last retry to ensure that the frame is tried in both
844 * MCS and legacy rate.
844 */ 845 */
845 if ((rates[2].flags & IEEE80211_TX_RC_MCS) && 846 ath_rc_get_lower_rix(rate_table, ath_rc_priv, rix, &rix);
846 (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU) || 847 if (WLAN_RC_PHY_HT(rate_table->info[rix].phy) &&
847 (ath_rc_priv->per[high_rix] > 45))) 848 (ath_rc_priv->per[rix] > 45))
848 rix = ath_rc_get_highest_rix(sc, ath_rc_priv, rate_table, 849 rix = ath_rc_get_highest_rix(sc, ath_rc_priv, rate_table,
849 &is_probe, true); 850 &is_probe, true);
850 else
851 ath_rc_get_lower_rix(rate_table, ath_rc_priv, rix, &rix);
852 851
853 /* All other rates in the series have RTS enabled */ 852 /* All other rates in the series have RTS enabled */
854 ath_rc_rate_set_series(rate_table, &rates[i], txrc, 853 ath_rc_rate_set_series(rate_table, &rates[i], txrc,
diff --git a/drivers/net/wireless/ath/ath9k/recv.c b/drivers/net/wireless/ath/ath9k/recv.c
index 0735aeb3b26c..11f3703a420a 100644
--- a/drivers/net/wireless/ath/ath9k/recv.c
+++ b/drivers/net/wireless/ath/ath9k/recv.c
@@ -20,43 +20,6 @@
20 20
21#define SKB_CB_ATHBUF(__skb) (*((struct ath_buf **)__skb->cb)) 21#define SKB_CB_ATHBUF(__skb) (*((struct ath_buf **)__skb->cb))
22 22
23static inline bool ath_is_alt_ant_ratio_better(int alt_ratio, int maxdelta,
24 int mindelta, int main_rssi_avg,
25 int alt_rssi_avg, int pkt_count)
26{
27 return (((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
28 (alt_rssi_avg > main_rssi_avg + maxdelta)) ||
29 (alt_rssi_avg > main_rssi_avg + mindelta)) && (pkt_count > 50);
30}
31
32static inline bool ath_ant_div_comb_alt_check(u8 div_group, int alt_ratio,
33 int curr_main_set, int curr_alt_set,
34 int alt_rssi_avg, int main_rssi_avg)
35{
36 bool result = false;
37 switch (div_group) {
38 case 0:
39 if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO)
40 result = true;
41 break;
42 case 1:
43 case 2:
44 if ((((curr_main_set == ATH_ANT_DIV_COMB_LNA2) &&
45 (curr_alt_set == ATH_ANT_DIV_COMB_LNA1) &&
46 (alt_rssi_avg >= (main_rssi_avg - 5))) ||
47 ((curr_main_set == ATH_ANT_DIV_COMB_LNA1) &&
48 (curr_alt_set == ATH_ANT_DIV_COMB_LNA2) &&
49 (alt_rssi_avg >= (main_rssi_avg - 2)))) &&
50 (alt_rssi_avg >= 4))
51 result = true;
52 else
53 result = false;
54 break;
55 }
56
57 return result;
58}
59
60static inline bool ath9k_check_auto_sleep(struct ath_softc *sc) 23static inline bool ath9k_check_auto_sleep(struct ath_softc *sc)
61{ 24{
62 return sc->ps_enabled && 25 return sc->ps_enabled &&
@@ -303,7 +266,7 @@ static void ath_edma_start_recv(struct ath_softc *sc)
303 266
304 ath_opmode_init(sc); 267 ath_opmode_init(sc);
305 268
306 ath9k_hw_startpcureceive(sc->sc_ah, (sc->sc_flags & SC_OP_OFFCHANNEL)); 269 ath9k_hw_startpcureceive(sc->sc_ah, !!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL));
307 270
308 spin_unlock_bh(&sc->rx.rxbuflock); 271 spin_unlock_bh(&sc->rx.rxbuflock);
309} 272}
@@ -322,8 +285,8 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
322 int error = 0; 285 int error = 0;
323 286
324 spin_lock_init(&sc->sc_pcu_lock); 287 spin_lock_init(&sc->sc_pcu_lock);
325 sc->sc_flags &= ~SC_OP_RXFLUSH;
326 spin_lock_init(&sc->rx.rxbuflock); 288 spin_lock_init(&sc->rx.rxbuflock);
289 clear_bit(SC_OP_RXFLUSH, &sc->sc_flags);
327 290
328 common->rx_bufsize = IEEE80211_MAX_MPDU_LEN / 2 + 291 common->rx_bufsize = IEEE80211_MAX_MPDU_LEN / 2 +
329 sc->sc_ah->caps.rx_status_len; 292 sc->sc_ah->caps.rx_status_len;
@@ -467,6 +430,9 @@ u32 ath_calcrxfilter(struct ath_softc *sc)
467 rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL; 430 rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL;
468 } 431 }
469 432
433 if (AR_SREV_9550(sc->sc_ah))
434 rfilt |= ATH9K_RX_FILTER_4ADDRESS;
435
470 return rfilt; 436 return rfilt;
471 437
472} 438}
@@ -500,7 +466,7 @@ int ath_startrecv(struct ath_softc *sc)
500 466
501start_recv: 467start_recv:
502 ath_opmode_init(sc); 468 ath_opmode_init(sc);
503 ath9k_hw_startpcureceive(ah, (sc->sc_flags & SC_OP_OFFCHANNEL)); 469 ath9k_hw_startpcureceive(ah, !!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL));
504 470
505 spin_unlock_bh(&sc->rx.rxbuflock); 471 spin_unlock_bh(&sc->rx.rxbuflock);
506 472
@@ -535,11 +501,11 @@ bool ath_stoprecv(struct ath_softc *sc)
535 501
536void ath_flushrecv(struct ath_softc *sc) 502void ath_flushrecv(struct ath_softc *sc)
537{ 503{
538 sc->sc_flags |= SC_OP_RXFLUSH; 504 set_bit(SC_OP_RXFLUSH, &sc->sc_flags);
539 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 505 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
540 ath_rx_tasklet(sc, 1, true); 506 ath_rx_tasklet(sc, 1, true);
541 ath_rx_tasklet(sc, 1, false); 507 ath_rx_tasklet(sc, 1, false);
542 sc->sc_flags &= ~SC_OP_RXFLUSH; 508 clear_bit(SC_OP_RXFLUSH, &sc->sc_flags);
543} 509}
544 510
545static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb) 511static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb)
@@ -624,13 +590,13 @@ static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb, bool mybeacon)
624 590
625 /* Process Beacon and CAB receive in PS state */ 591 /* Process Beacon and CAB receive in PS state */
626 if (((sc->ps_flags & PS_WAIT_FOR_BEACON) || ath9k_check_auto_sleep(sc)) 592 if (((sc->ps_flags & PS_WAIT_FOR_BEACON) || ath9k_check_auto_sleep(sc))
627 && mybeacon) 593 && mybeacon) {
628 ath_rx_ps_beacon(sc, skb); 594 ath_rx_ps_beacon(sc, skb);
629 else if ((sc->ps_flags & PS_WAIT_FOR_CAB) && 595 } else if ((sc->ps_flags & PS_WAIT_FOR_CAB) &&
630 (ieee80211_is_data(hdr->frame_control) || 596 (ieee80211_is_data(hdr->frame_control) ||
631 ieee80211_is_action(hdr->frame_control)) && 597 ieee80211_is_action(hdr->frame_control)) &&
632 is_multicast_ether_addr(hdr->addr1) && 598 is_multicast_ether_addr(hdr->addr1) &&
633 !ieee80211_has_moredata(hdr->frame_control)) { 599 !ieee80211_has_moredata(hdr->frame_control)) {
634 /* 600 /*
635 * No more broadcast/multicast frames to be received at this 601 * No more broadcast/multicast frames to be received at this
636 * point. 602 * point.
@@ -1068,709 +1034,6 @@ static void ath9k_rx_skb_postprocess(struct ath_common *common,
1068 rxs->flag &= ~RX_FLAG_DECRYPTED; 1034 rxs->flag &= ~RX_FLAG_DECRYPTED;
1069} 1035}
1070 1036
1071static void ath_lnaconf_alt_good_scan(struct ath_ant_comb *antcomb,
1072 struct ath_hw_antcomb_conf ant_conf,
1073 int main_rssi_avg)
1074{
1075 antcomb->quick_scan_cnt = 0;
1076
1077 if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA2)
1078 antcomb->rssi_lna2 = main_rssi_avg;
1079 else if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA1)
1080 antcomb->rssi_lna1 = main_rssi_avg;
1081
1082 switch ((ant_conf.main_lna_conf << 4) | ant_conf.alt_lna_conf) {
1083 case 0x10: /* LNA2 A-B */
1084 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1085 antcomb->first_quick_scan_conf =
1086 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1087 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1;
1088 break;
1089 case 0x20: /* LNA1 A-B */
1090 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1091 antcomb->first_quick_scan_conf =
1092 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1093 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2;
1094 break;
1095 case 0x21: /* LNA1 LNA2 */
1096 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA2;
1097 antcomb->first_quick_scan_conf =
1098 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1099 antcomb->second_quick_scan_conf =
1100 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1101 break;
1102 case 0x12: /* LNA2 LNA1 */
1103 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1;
1104 antcomb->first_quick_scan_conf =
1105 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1106 antcomb->second_quick_scan_conf =
1107 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1108 break;
1109 case 0x13: /* LNA2 A+B */
1110 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1111 antcomb->first_quick_scan_conf =
1112 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1113 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1;
1114 break;
1115 case 0x23: /* LNA1 A+B */
1116 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1117 antcomb->first_quick_scan_conf =
1118 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1119 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2;
1120 break;
1121 default:
1122 break;
1123 }
1124}
1125
1126static void ath_select_ant_div_from_quick_scan(struct ath_ant_comb *antcomb,
1127 struct ath_hw_antcomb_conf *div_ant_conf,
1128 int main_rssi_avg, int alt_rssi_avg,
1129 int alt_ratio)
1130{
1131 /* alt_good */
1132 switch (antcomb->quick_scan_cnt) {
1133 case 0:
1134 /* set alt to main, and alt to first conf */
1135 div_ant_conf->main_lna_conf = antcomb->main_conf;
1136 div_ant_conf->alt_lna_conf = antcomb->first_quick_scan_conf;
1137 break;
1138 case 1:
1139 /* set alt to main, and alt to first conf */
1140 div_ant_conf->main_lna_conf = antcomb->main_conf;
1141 div_ant_conf->alt_lna_conf = antcomb->second_quick_scan_conf;
1142 antcomb->rssi_first = main_rssi_avg;
1143 antcomb->rssi_second = alt_rssi_avg;
1144
1145 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) {
1146 /* main is LNA1 */
1147 if (ath_is_alt_ant_ratio_better(alt_ratio,
1148 ATH_ANT_DIV_COMB_LNA1_DELTA_HI,
1149 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1150 main_rssi_avg, alt_rssi_avg,
1151 antcomb->total_pkt_count))
1152 antcomb->first_ratio = true;
1153 else
1154 antcomb->first_ratio = false;
1155 } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) {
1156 if (ath_is_alt_ant_ratio_better(alt_ratio,
1157 ATH_ANT_DIV_COMB_LNA1_DELTA_MID,
1158 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1159 main_rssi_avg, alt_rssi_avg,
1160 antcomb->total_pkt_count))
1161 antcomb->first_ratio = true;
1162 else
1163 antcomb->first_ratio = false;
1164 } else {
1165 if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
1166 (alt_rssi_avg > main_rssi_avg +
1167 ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) ||
1168 (alt_rssi_avg > main_rssi_avg)) &&
1169 (antcomb->total_pkt_count > 50))
1170 antcomb->first_ratio = true;
1171 else
1172 antcomb->first_ratio = false;
1173 }
1174 break;
1175 case 2:
1176 antcomb->alt_good = false;
1177 antcomb->scan_not_start = false;
1178 antcomb->scan = false;
1179 antcomb->rssi_first = main_rssi_avg;
1180 antcomb->rssi_third = alt_rssi_avg;
1181
1182 if (antcomb->second_quick_scan_conf == ATH_ANT_DIV_COMB_LNA1)
1183 antcomb->rssi_lna1 = alt_rssi_avg;
1184 else if (antcomb->second_quick_scan_conf ==
1185 ATH_ANT_DIV_COMB_LNA2)
1186 antcomb->rssi_lna2 = alt_rssi_avg;
1187 else if (antcomb->second_quick_scan_conf ==
1188 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2) {
1189 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2)
1190 antcomb->rssi_lna2 = main_rssi_avg;
1191 else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1)
1192 antcomb->rssi_lna1 = main_rssi_avg;
1193 }
1194
1195 if (antcomb->rssi_lna2 > antcomb->rssi_lna1 +
1196 ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA)
1197 div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA2;
1198 else
1199 div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA1;
1200
1201 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) {
1202 if (ath_is_alt_ant_ratio_better(alt_ratio,
1203 ATH_ANT_DIV_COMB_LNA1_DELTA_HI,
1204 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1205 main_rssi_avg, alt_rssi_avg,
1206 antcomb->total_pkt_count))
1207 antcomb->second_ratio = true;
1208 else
1209 antcomb->second_ratio = false;
1210 } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) {
1211 if (ath_is_alt_ant_ratio_better(alt_ratio,
1212 ATH_ANT_DIV_COMB_LNA1_DELTA_MID,
1213 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1214 main_rssi_avg, alt_rssi_avg,
1215 antcomb->total_pkt_count))
1216 antcomb->second_ratio = true;
1217 else
1218 antcomb->second_ratio = false;
1219 } else {
1220 if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
1221 (alt_rssi_avg > main_rssi_avg +
1222 ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) ||
1223 (alt_rssi_avg > main_rssi_avg)) &&
1224 (antcomb->total_pkt_count > 50))
1225 antcomb->second_ratio = true;
1226 else
1227 antcomb->second_ratio = false;
1228 }
1229
1230 /* set alt to the conf with maximun ratio */
1231 if (antcomb->first_ratio && antcomb->second_ratio) {
1232 if (antcomb->rssi_second > antcomb->rssi_third) {
1233 /* first alt*/
1234 if ((antcomb->first_quick_scan_conf ==
1235 ATH_ANT_DIV_COMB_LNA1) ||
1236 (antcomb->first_quick_scan_conf ==
1237 ATH_ANT_DIV_COMB_LNA2))
1238 /* Set alt LNA1 or LNA2*/
1239 if (div_ant_conf->main_lna_conf ==
1240 ATH_ANT_DIV_COMB_LNA2)
1241 div_ant_conf->alt_lna_conf =
1242 ATH_ANT_DIV_COMB_LNA1;
1243 else
1244 div_ant_conf->alt_lna_conf =
1245 ATH_ANT_DIV_COMB_LNA2;
1246 else
1247 /* Set alt to A+B or A-B */
1248 div_ant_conf->alt_lna_conf =
1249 antcomb->first_quick_scan_conf;
1250 } else if ((antcomb->second_quick_scan_conf ==
1251 ATH_ANT_DIV_COMB_LNA1) ||
1252 (antcomb->second_quick_scan_conf ==
1253 ATH_ANT_DIV_COMB_LNA2)) {
1254 /* Set alt LNA1 or LNA2 */
1255 if (div_ant_conf->main_lna_conf ==
1256 ATH_ANT_DIV_COMB_LNA2)
1257 div_ant_conf->alt_lna_conf =
1258 ATH_ANT_DIV_COMB_LNA1;
1259 else
1260 div_ant_conf->alt_lna_conf =
1261 ATH_ANT_DIV_COMB_LNA2;
1262 } else {
1263 /* Set alt to A+B or A-B */
1264 div_ant_conf->alt_lna_conf =
1265 antcomb->second_quick_scan_conf;
1266 }
1267 } else if (antcomb->first_ratio) {
1268 /* first alt */
1269 if ((antcomb->first_quick_scan_conf ==
1270 ATH_ANT_DIV_COMB_LNA1) ||
1271 (antcomb->first_quick_scan_conf ==
1272 ATH_ANT_DIV_COMB_LNA2))
1273 /* Set alt LNA1 or LNA2 */
1274 if (div_ant_conf->main_lna_conf ==
1275 ATH_ANT_DIV_COMB_LNA2)
1276 div_ant_conf->alt_lna_conf =
1277 ATH_ANT_DIV_COMB_LNA1;
1278 else
1279 div_ant_conf->alt_lna_conf =
1280 ATH_ANT_DIV_COMB_LNA2;
1281 else
1282 /* Set alt to A+B or A-B */
1283 div_ant_conf->alt_lna_conf =
1284 antcomb->first_quick_scan_conf;
1285 } else if (antcomb->second_ratio) {
1286 /* second alt */
1287 if ((antcomb->second_quick_scan_conf ==
1288 ATH_ANT_DIV_COMB_LNA1) ||
1289 (antcomb->second_quick_scan_conf ==
1290 ATH_ANT_DIV_COMB_LNA2))
1291 /* Set alt LNA1 or LNA2 */
1292 if (div_ant_conf->main_lna_conf ==
1293 ATH_ANT_DIV_COMB_LNA2)
1294 div_ant_conf->alt_lna_conf =
1295 ATH_ANT_DIV_COMB_LNA1;
1296 else
1297 div_ant_conf->alt_lna_conf =
1298 ATH_ANT_DIV_COMB_LNA2;
1299 else
1300 /* Set alt to A+B or A-B */
1301 div_ant_conf->alt_lna_conf =
1302 antcomb->second_quick_scan_conf;
1303 } else {
1304 /* main is largest */
1305 if ((antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) ||
1306 (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2))
1307 /* Set alt LNA1 or LNA2 */
1308 if (div_ant_conf->main_lna_conf ==
1309 ATH_ANT_DIV_COMB_LNA2)
1310 div_ant_conf->alt_lna_conf =
1311 ATH_ANT_DIV_COMB_LNA1;
1312 else
1313 div_ant_conf->alt_lna_conf =
1314 ATH_ANT_DIV_COMB_LNA2;
1315 else
1316 /* Set alt to A+B or A-B */
1317 div_ant_conf->alt_lna_conf = antcomb->main_conf;
1318 }
1319 break;
1320 default:
1321 break;
1322 }
1323}
1324
1325static void ath_ant_div_conf_fast_divbias(struct ath_hw_antcomb_conf *ant_conf,
1326 struct ath_ant_comb *antcomb, int alt_ratio)
1327{
1328 if (ant_conf->div_group == 0) {
1329 /* Adjust the fast_div_bias based on main and alt lna conf */
1330 switch ((ant_conf->main_lna_conf << 4) |
1331 ant_conf->alt_lna_conf) {
1332 case 0x01: /* A-B LNA2 */
1333 ant_conf->fast_div_bias = 0x3b;
1334 break;
1335 case 0x02: /* A-B LNA1 */
1336 ant_conf->fast_div_bias = 0x3d;
1337 break;
1338 case 0x03: /* A-B A+B */
1339 ant_conf->fast_div_bias = 0x1;
1340 break;
1341 case 0x10: /* LNA2 A-B */
1342 ant_conf->fast_div_bias = 0x7;
1343 break;
1344 case 0x12: /* LNA2 LNA1 */
1345 ant_conf->fast_div_bias = 0x2;
1346 break;
1347 case 0x13: /* LNA2 A+B */
1348 ant_conf->fast_div_bias = 0x7;
1349 break;
1350 case 0x20: /* LNA1 A-B */
1351 ant_conf->fast_div_bias = 0x6;
1352 break;
1353 case 0x21: /* LNA1 LNA2 */
1354 ant_conf->fast_div_bias = 0x0;
1355 break;
1356 case 0x23: /* LNA1 A+B */
1357 ant_conf->fast_div_bias = 0x6;
1358 break;
1359 case 0x30: /* A+B A-B */
1360 ant_conf->fast_div_bias = 0x1;
1361 break;
1362 case 0x31: /* A+B LNA2 */
1363 ant_conf->fast_div_bias = 0x3b;
1364 break;
1365 case 0x32: /* A+B LNA1 */
1366 ant_conf->fast_div_bias = 0x3d;
1367 break;
1368 default:
1369 break;
1370 }
1371 } else if (ant_conf->div_group == 1) {
1372 /* Adjust the fast_div_bias based on main and alt_lna_conf */
1373 switch ((ant_conf->main_lna_conf << 4) |
1374 ant_conf->alt_lna_conf) {
1375 case 0x01: /* A-B LNA2 */
1376 ant_conf->fast_div_bias = 0x1;
1377 ant_conf->main_gaintb = 0;
1378 ant_conf->alt_gaintb = 0;
1379 break;
1380 case 0x02: /* A-B LNA1 */
1381 ant_conf->fast_div_bias = 0x1;
1382 ant_conf->main_gaintb = 0;
1383 ant_conf->alt_gaintb = 0;
1384 break;
1385 case 0x03: /* A-B A+B */
1386 ant_conf->fast_div_bias = 0x1;
1387 ant_conf->main_gaintb = 0;
1388 ant_conf->alt_gaintb = 0;
1389 break;
1390 case 0x10: /* LNA2 A-B */
1391 if (!(antcomb->scan) &&
1392 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1393 ant_conf->fast_div_bias = 0x3f;
1394 else
1395 ant_conf->fast_div_bias = 0x1;
1396 ant_conf->main_gaintb = 0;
1397 ant_conf->alt_gaintb = 0;
1398 break;
1399 case 0x12: /* LNA2 LNA1 */
1400 ant_conf->fast_div_bias = 0x1;
1401 ant_conf->main_gaintb = 0;
1402 ant_conf->alt_gaintb = 0;
1403 break;
1404 case 0x13: /* LNA2 A+B */
1405 if (!(antcomb->scan) &&
1406 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1407 ant_conf->fast_div_bias = 0x3f;
1408 else
1409 ant_conf->fast_div_bias = 0x1;
1410 ant_conf->main_gaintb = 0;
1411 ant_conf->alt_gaintb = 0;
1412 break;
1413 case 0x20: /* LNA1 A-B */
1414 if (!(antcomb->scan) &&
1415 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1416 ant_conf->fast_div_bias = 0x3f;
1417 else
1418 ant_conf->fast_div_bias = 0x1;
1419 ant_conf->main_gaintb = 0;
1420 ant_conf->alt_gaintb = 0;
1421 break;
1422 case 0x21: /* LNA1 LNA2 */
1423 ant_conf->fast_div_bias = 0x1;
1424 ant_conf->main_gaintb = 0;
1425 ant_conf->alt_gaintb = 0;
1426 break;
1427 case 0x23: /* LNA1 A+B */
1428 if (!(antcomb->scan) &&
1429 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1430 ant_conf->fast_div_bias = 0x3f;
1431 else
1432 ant_conf->fast_div_bias = 0x1;
1433 ant_conf->main_gaintb = 0;
1434 ant_conf->alt_gaintb = 0;
1435 break;
1436 case 0x30: /* A+B A-B */
1437 ant_conf->fast_div_bias = 0x1;
1438 ant_conf->main_gaintb = 0;
1439 ant_conf->alt_gaintb = 0;
1440 break;
1441 case 0x31: /* A+B LNA2 */
1442 ant_conf->fast_div_bias = 0x1;
1443 ant_conf->main_gaintb = 0;
1444 ant_conf->alt_gaintb = 0;
1445 break;
1446 case 0x32: /* A+B LNA1 */
1447 ant_conf->fast_div_bias = 0x1;
1448 ant_conf->main_gaintb = 0;
1449 ant_conf->alt_gaintb = 0;
1450 break;
1451 default:
1452 break;
1453 }
1454 } else if (ant_conf->div_group == 2) {
1455 /* Adjust the fast_div_bias based on main and alt_lna_conf */
1456 switch ((ant_conf->main_lna_conf << 4) |
1457 ant_conf->alt_lna_conf) {
1458 case 0x01: /* A-B LNA2 */
1459 ant_conf->fast_div_bias = 0x1;
1460 ant_conf->main_gaintb = 0;
1461 ant_conf->alt_gaintb = 0;
1462 break;
1463 case 0x02: /* A-B LNA1 */
1464 ant_conf->fast_div_bias = 0x1;
1465 ant_conf->main_gaintb = 0;
1466 ant_conf->alt_gaintb = 0;
1467 break;
1468 case 0x03: /* A-B A+B */
1469 ant_conf->fast_div_bias = 0x1;
1470 ant_conf->main_gaintb = 0;
1471 ant_conf->alt_gaintb = 0;
1472 break;
1473 case 0x10: /* LNA2 A-B */
1474 if (!(antcomb->scan) &&
1475 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1476 ant_conf->fast_div_bias = 0x1;
1477 else
1478 ant_conf->fast_div_bias = 0x2;
1479 ant_conf->main_gaintb = 0;
1480 ant_conf->alt_gaintb = 0;
1481 break;
1482 case 0x12: /* LNA2 LNA1 */
1483 ant_conf->fast_div_bias = 0x1;
1484 ant_conf->main_gaintb = 0;
1485 ant_conf->alt_gaintb = 0;
1486 break;
1487 case 0x13: /* LNA2 A+B */
1488 if (!(antcomb->scan) &&
1489 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1490 ant_conf->fast_div_bias = 0x1;
1491 else
1492 ant_conf->fast_div_bias = 0x2;
1493 ant_conf->main_gaintb = 0;
1494 ant_conf->alt_gaintb = 0;
1495 break;
1496 case 0x20: /* LNA1 A-B */
1497 if (!(antcomb->scan) &&
1498 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1499 ant_conf->fast_div_bias = 0x1;
1500 else
1501 ant_conf->fast_div_bias = 0x2;
1502 ant_conf->main_gaintb = 0;
1503 ant_conf->alt_gaintb = 0;
1504 break;
1505 case 0x21: /* LNA1 LNA2 */
1506 ant_conf->fast_div_bias = 0x1;
1507 ant_conf->main_gaintb = 0;
1508 ant_conf->alt_gaintb = 0;
1509 break;
1510 case 0x23: /* LNA1 A+B */
1511 if (!(antcomb->scan) &&
1512 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1513 ant_conf->fast_div_bias = 0x1;
1514 else
1515 ant_conf->fast_div_bias = 0x2;
1516 ant_conf->main_gaintb = 0;
1517 ant_conf->alt_gaintb = 0;
1518 break;
1519 case 0x30: /* A+B A-B */
1520 ant_conf->fast_div_bias = 0x1;
1521 ant_conf->main_gaintb = 0;
1522 ant_conf->alt_gaintb = 0;
1523 break;
1524 case 0x31: /* A+B LNA2 */
1525 ant_conf->fast_div_bias = 0x1;
1526 ant_conf->main_gaintb = 0;
1527 ant_conf->alt_gaintb = 0;
1528 break;
1529 case 0x32: /* A+B LNA1 */
1530 ant_conf->fast_div_bias = 0x1;
1531 ant_conf->main_gaintb = 0;
1532 ant_conf->alt_gaintb = 0;
1533 break;
1534 default:
1535 break;
1536 }
1537 }
1538}
1539
1540/* Antenna diversity and combining */
1541static void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs)
1542{
1543 struct ath_hw_antcomb_conf div_ant_conf;
1544 struct ath_ant_comb *antcomb = &sc->ant_comb;
1545 int alt_ratio = 0, alt_rssi_avg = 0, main_rssi_avg = 0, curr_alt_set;
1546 int curr_main_set;
1547 int main_rssi = rs->rs_rssi_ctl0;
1548 int alt_rssi = rs->rs_rssi_ctl1;
1549 int rx_ant_conf, main_ant_conf;
1550 bool short_scan = false;
1551
1552 rx_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_CURRENT_SHIFT) &
1553 ATH_ANT_RX_MASK;
1554 main_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_MAIN_SHIFT) &
1555 ATH_ANT_RX_MASK;
1556
1557 /* Record packet only when both main_rssi and alt_rssi is positive */
1558 if (main_rssi > 0 && alt_rssi > 0) {
1559 antcomb->total_pkt_count++;
1560 antcomb->main_total_rssi += main_rssi;
1561 antcomb->alt_total_rssi += alt_rssi;
1562 if (main_ant_conf == rx_ant_conf)
1563 antcomb->main_recv_cnt++;
1564 else
1565 antcomb->alt_recv_cnt++;
1566 }
1567
1568 /* Short scan check */
1569 if (antcomb->scan && antcomb->alt_good) {
1570 if (time_after(jiffies, antcomb->scan_start_time +
1571 msecs_to_jiffies(ATH_ANT_DIV_COMB_SHORT_SCAN_INTR)))
1572 short_scan = true;
1573 else
1574 if (antcomb->total_pkt_count ==
1575 ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT) {
1576 alt_ratio = ((antcomb->alt_recv_cnt * 100) /
1577 antcomb->total_pkt_count);
1578 if (alt_ratio < ATH_ANT_DIV_COMB_ALT_ANT_RATIO)
1579 short_scan = true;
1580 }
1581 }
1582
1583 if (((antcomb->total_pkt_count < ATH_ANT_DIV_COMB_MAX_PKTCOUNT) ||
1584 rs->rs_moreaggr) && !short_scan)
1585 return;
1586
1587 if (antcomb->total_pkt_count) {
1588 alt_ratio = ((antcomb->alt_recv_cnt * 100) /
1589 antcomb->total_pkt_count);
1590 main_rssi_avg = (antcomb->main_total_rssi /
1591 antcomb->total_pkt_count);
1592 alt_rssi_avg = (antcomb->alt_total_rssi /
1593 antcomb->total_pkt_count);
1594 }
1595
1596
1597 ath9k_hw_antdiv_comb_conf_get(sc->sc_ah, &div_ant_conf);
1598 curr_alt_set = div_ant_conf.alt_lna_conf;
1599 curr_main_set = div_ant_conf.main_lna_conf;
1600
1601 antcomb->count++;
1602
1603 if (antcomb->count == ATH_ANT_DIV_COMB_MAX_COUNT) {
1604 if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO) {
1605 ath_lnaconf_alt_good_scan(antcomb, div_ant_conf,
1606 main_rssi_avg);
1607 antcomb->alt_good = true;
1608 } else {
1609 antcomb->alt_good = false;
1610 }
1611
1612 antcomb->count = 0;
1613 antcomb->scan = true;
1614 antcomb->scan_not_start = true;
1615 }
1616
1617 if (!antcomb->scan) {
1618 if (ath_ant_div_comb_alt_check(div_ant_conf.div_group,
1619 alt_ratio, curr_main_set, curr_alt_set,
1620 alt_rssi_avg, main_rssi_avg)) {
1621 if (curr_alt_set == ATH_ANT_DIV_COMB_LNA2) {
1622 /* Switch main and alt LNA */
1623 div_ant_conf.main_lna_conf =
1624 ATH_ANT_DIV_COMB_LNA2;
1625 div_ant_conf.alt_lna_conf =
1626 ATH_ANT_DIV_COMB_LNA1;
1627 } else if (curr_alt_set == ATH_ANT_DIV_COMB_LNA1) {
1628 div_ant_conf.main_lna_conf =
1629 ATH_ANT_DIV_COMB_LNA1;
1630 div_ant_conf.alt_lna_conf =
1631 ATH_ANT_DIV_COMB_LNA2;
1632 }
1633
1634 goto div_comb_done;
1635 } else if ((curr_alt_set != ATH_ANT_DIV_COMB_LNA1) &&
1636 (curr_alt_set != ATH_ANT_DIV_COMB_LNA2)) {
1637 /* Set alt to another LNA */
1638 if (curr_main_set == ATH_ANT_DIV_COMB_LNA2)
1639 div_ant_conf.alt_lna_conf =
1640 ATH_ANT_DIV_COMB_LNA1;
1641 else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1)
1642 div_ant_conf.alt_lna_conf =
1643 ATH_ANT_DIV_COMB_LNA2;
1644
1645 goto div_comb_done;
1646 }
1647
1648 if ((alt_rssi_avg < (main_rssi_avg +
1649 div_ant_conf.lna1_lna2_delta)))
1650 goto div_comb_done;
1651 }
1652
1653 if (!antcomb->scan_not_start) {
1654 switch (curr_alt_set) {
1655 case ATH_ANT_DIV_COMB_LNA2:
1656 antcomb->rssi_lna2 = alt_rssi_avg;
1657 antcomb->rssi_lna1 = main_rssi_avg;
1658 antcomb->scan = true;
1659 /* set to A+B */
1660 div_ant_conf.main_lna_conf =
1661 ATH_ANT_DIV_COMB_LNA1;
1662 div_ant_conf.alt_lna_conf =
1663 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1664 break;
1665 case ATH_ANT_DIV_COMB_LNA1:
1666 antcomb->rssi_lna1 = alt_rssi_avg;
1667 antcomb->rssi_lna2 = main_rssi_avg;
1668 antcomb->scan = true;
1669 /* set to A+B */
1670 div_ant_conf.main_lna_conf = ATH_ANT_DIV_COMB_LNA2;
1671 div_ant_conf.alt_lna_conf =
1672 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1673 break;
1674 case ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2:
1675 antcomb->rssi_add = alt_rssi_avg;
1676 antcomb->scan = true;
1677 /* set to A-B */
1678 div_ant_conf.alt_lna_conf =
1679 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1680 break;
1681 case ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2:
1682 antcomb->rssi_sub = alt_rssi_avg;
1683 antcomb->scan = false;
1684 if (antcomb->rssi_lna2 >
1685 (antcomb->rssi_lna1 +
1686 ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA)) {
1687 /* use LNA2 as main LNA */
1688 if ((antcomb->rssi_add > antcomb->rssi_lna1) &&
1689 (antcomb->rssi_add > antcomb->rssi_sub)) {
1690 /* set to A+B */
1691 div_ant_conf.main_lna_conf =
1692 ATH_ANT_DIV_COMB_LNA2;
1693 div_ant_conf.alt_lna_conf =
1694 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1695 } else if (antcomb->rssi_sub >
1696 antcomb->rssi_lna1) {
1697 /* set to A-B */
1698 div_ant_conf.main_lna_conf =
1699 ATH_ANT_DIV_COMB_LNA2;
1700 div_ant_conf.alt_lna_conf =
1701 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1702 } else {
1703 /* set to LNA1 */
1704 div_ant_conf.main_lna_conf =
1705 ATH_ANT_DIV_COMB_LNA2;
1706 div_ant_conf.alt_lna_conf =
1707 ATH_ANT_DIV_COMB_LNA1;
1708 }
1709 } else {
1710 /* use LNA1 as main LNA */
1711 if ((antcomb->rssi_add > antcomb->rssi_lna2) &&
1712 (antcomb->rssi_add > antcomb->rssi_sub)) {
1713 /* set to A+B */
1714 div_ant_conf.main_lna_conf =
1715 ATH_ANT_DIV_COMB_LNA1;
1716 div_ant_conf.alt_lna_conf =
1717 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1718 } else if (antcomb->rssi_sub >
1719 antcomb->rssi_lna1) {
1720 /* set to A-B */
1721 div_ant_conf.main_lna_conf =
1722 ATH_ANT_DIV_COMB_LNA1;
1723 div_ant_conf.alt_lna_conf =
1724 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1725 } else {
1726 /* set to LNA2 */
1727 div_ant_conf.main_lna_conf =
1728 ATH_ANT_DIV_COMB_LNA1;
1729 div_ant_conf.alt_lna_conf =
1730 ATH_ANT_DIV_COMB_LNA2;
1731 }
1732 }
1733 break;
1734 default:
1735 break;
1736 }
1737 } else {
1738 if (!antcomb->alt_good) {
1739 antcomb->scan_not_start = false;
1740 /* Set alt to another LNA */
1741 if (curr_main_set == ATH_ANT_DIV_COMB_LNA2) {
1742 div_ant_conf.main_lna_conf =
1743 ATH_ANT_DIV_COMB_LNA2;
1744 div_ant_conf.alt_lna_conf =
1745 ATH_ANT_DIV_COMB_LNA1;
1746 } else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1) {
1747 div_ant_conf.main_lna_conf =
1748 ATH_ANT_DIV_COMB_LNA1;
1749 div_ant_conf.alt_lna_conf =
1750 ATH_ANT_DIV_COMB_LNA2;
1751 }
1752 goto div_comb_done;
1753 }
1754 }
1755
1756 ath_select_ant_div_from_quick_scan(antcomb, &div_ant_conf,
1757 main_rssi_avg, alt_rssi_avg,
1758 alt_ratio);
1759
1760 antcomb->quick_scan_cnt++;
1761
1762div_comb_done:
1763 ath_ant_div_conf_fast_divbias(&div_ant_conf, antcomb, alt_ratio);
1764 ath9k_hw_antdiv_comb_conf_set(sc->sc_ah, &div_ant_conf);
1765
1766 antcomb->scan_start_time = jiffies;
1767 antcomb->total_pkt_count = 0;
1768 antcomb->main_total_rssi = 0;
1769 antcomb->alt_total_rssi = 0;
1770 antcomb->main_recv_cnt = 0;
1771 antcomb->alt_recv_cnt = 0;
1772}
1773
1774int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp) 1037int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
1775{ 1038{
1776 struct ath_buf *bf; 1039 struct ath_buf *bf;
@@ -1804,7 +1067,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
1804 1067
1805 do { 1068 do {
1806 /* If handling rx interrupt and flush is in progress => exit */ 1069 /* If handling rx interrupt and flush is in progress => exit */
1807 if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0)) 1070 if (test_bit(SC_OP_RXFLUSH, &sc->sc_flags) && (flush == 0))
1808 break; 1071 break;
1809 1072
1810 memset(&rs, 0, sizeof(rs)); 1073 memset(&rs, 0, sizeof(rs));
@@ -1842,13 +1105,14 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
1842 else 1105 else
1843 rs.is_mybeacon = false; 1106 rs.is_mybeacon = false;
1844 1107
1108 sc->rx.num_pkts++;
1845 ath_debug_stat_rx(sc, &rs); 1109 ath_debug_stat_rx(sc, &rs);
1846 1110
1847 /* 1111 /*
1848 * If we're asked to flush receive queue, directly 1112 * If we're asked to flush receive queue, directly
1849 * chain it back at the queue without processing it. 1113 * chain it back at the queue without processing it.
1850 */ 1114 */
1851 if (sc->sc_flags & SC_OP_RXFLUSH) { 1115 if (test_bit(SC_OP_RXFLUSH, &sc->sc_flags)) {
1852 RX_STAT_INC(rx_drop_rxflush); 1116 RX_STAT_INC(rx_drop_rxflush);
1853 goto requeue_drop_frag; 1117 goto requeue_drop_frag;
1854 } 1118 }
@@ -1969,7 +1233,6 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
1969 skb_trim(skb, skb->len - 8); 1233 skb_trim(skb, skb->len - 8);
1970 1234
1971 spin_lock_irqsave(&sc->sc_pm_lock, flags); 1235 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1972
1973 if ((sc->ps_flags & (PS_WAIT_FOR_BEACON | 1236 if ((sc->ps_flags & (PS_WAIT_FOR_BEACON |
1974 PS_WAIT_FOR_CAB | 1237 PS_WAIT_FOR_CAB |
1975 PS_WAIT_FOR_PSPOLL_DATA)) || 1238 PS_WAIT_FOR_PSPOLL_DATA)) ||
diff --git a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h
index 458f81b4a7cb..6592c07ac646 100644
--- a/drivers/net/wireless/ath/ath9k/reg.h
+++ b/drivers/net/wireless/ath/ath9k/reg.h
@@ -798,6 +798,7 @@
798#define AR_SREV_REVISION_9580_10 4 /* AR9580 1.0 */ 798#define AR_SREV_REVISION_9580_10 4 /* AR9580 1.0 */
799#define AR_SREV_VERSION_9462 0x280 799#define AR_SREV_VERSION_9462 0x280
800#define AR_SREV_REVISION_9462_20 2 800#define AR_SREV_REVISION_9462_20 2
801#define AR_SREV_VERSION_9550 0x400
801 802
802#define AR_SREV_5416(_ah) \ 803#define AR_SREV_5416(_ah) \
803 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \ 804 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \
@@ -905,6 +906,9 @@
905 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9462) && \ 906 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9462) && \
906 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9462_20)) 907 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9462_20))
907 908
909#define AR_SREV_9550(_ah) \
910 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9550))
911
908#define AR_SREV_9580(_ah) \ 912#define AR_SREV_9580(_ah) \
909 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9580) && \ 913 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9580) && \
910 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9580_10)) 914 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9580_10))
@@ -1643,11 +1647,11 @@ enum {
1643 1647
1644#define AR_TPC 0x80e8 1648#define AR_TPC 0x80e8
1645#define AR_TPC_ACK 0x0000003f 1649#define AR_TPC_ACK 0x0000003f
1646#define AR_TPC_ACK_S 0x00 1650#define AR_TPC_ACK_S 0
1647#define AR_TPC_CTS 0x00003f00 1651#define AR_TPC_CTS 0x00003f00
1648#define AR_TPC_CTS_S 0x08 1652#define AR_TPC_CTS_S 8
1649#define AR_TPC_CHIRP 0x003f0000 1653#define AR_TPC_CHIRP 0x003f0000
1650#define AR_TPC_CHIRP_S 0x16 1654#define AR_TPC_CHIRP_S 16
1651 1655
1652#define AR_QUIET1 0x80fc 1656#define AR_QUIET1 0x80fc
1653#define AR_QUIET1_NEXT_QUIET_S 0 1657#define AR_QUIET1_NEXT_QUIET_S 0
@@ -2077,12 +2081,6 @@ enum {
2077 AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET| \ 2081 AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET| \
2078 AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING | \ 2082 AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING | \
2079 AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING| \ 2083 AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING| \
2080 AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO | \
2081 AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL | \
2082 AR_MCI_INTERRUPT_RX_MSG_LNA_INFO | \
2083 AR_MCI_INTERRUPT_RX_MSG_CONT_NACK | \
2084 AR_MCI_INTERRUPT_RX_MSG_CONT_INFO | \
2085 AR_MCI_INTERRUPT_RX_MSG_CONT_RST | \
2086 AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE) 2084 AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE)
2087 2085
2088#define AR_MCI_CPU_INT 0x1840 2086#define AR_MCI_CPU_INT 0x1840
@@ -2098,8 +2096,8 @@ enum {
2098#define AR_MCI_CONT_STATUS 0x1848 2096#define AR_MCI_CONT_STATUS 0x1848
2099#define AR_MCI_CONT_RSSI_POWER 0x000000FF 2097#define AR_MCI_CONT_RSSI_POWER 0x000000FF
2100#define AR_MCI_CONT_RSSI_POWER_S 0 2098#define AR_MCI_CONT_RSSI_POWER_S 0
2101#define AR_MCI_CONT_RRIORITY 0x0000FF00 2099#define AR_MCI_CONT_PRIORITY 0x0000FF00
2102#define AR_MCI_CONT_RRIORITY_S 8 2100#define AR_MCI_CONT_PRIORITY_S 8
2103#define AR_MCI_CONT_TXRX 0x00010000 2101#define AR_MCI_CONT_TXRX 0x00010000
2104#define AR_MCI_CONT_TXRX_S 16 2102#define AR_MCI_CONT_TXRX_S 16
2105 2103
@@ -2162,10 +2160,6 @@ enum {
2162#define AR_BTCOEX_CTRL_SPDT_POLARITY 0x80000000 2160#define AR_BTCOEX_CTRL_SPDT_POLARITY 0x80000000
2163#define AR_BTCOEX_CTRL_SPDT_POLARITY_S 31 2161#define AR_BTCOEX_CTRL_SPDT_POLARITY_S 31
2164 2162
2165#define AR_BTCOEX_WL_WEIGHTS0 0x18b0
2166#define AR_BTCOEX_WL_WEIGHTS1 0x18b4
2167#define AR_BTCOEX_WL_WEIGHTS2 0x18b8
2168#define AR_BTCOEX_WL_WEIGHTS3 0x18bc
2169#define AR_BTCOEX_MAX_TXPWR(_x) (0x18c0 + ((_x) << 2)) 2163#define AR_BTCOEX_MAX_TXPWR(_x) (0x18c0 + ((_x) << 2))
2170#define AR_BTCOEX_WL_LNA 0x1940 2164#define AR_BTCOEX_WL_LNA 0x1940
2171#define AR_BTCOEX_RFGAIN_CTRL 0x1944 2165#define AR_BTCOEX_RFGAIN_CTRL 0x1944
@@ -2211,5 +2205,7 @@ enum {
2211#define AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT 0x00000fff 2205#define AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT 0x00000fff
2212#define AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT_S 0 2206#define AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT_S 0
2213 2207
2208#define AR_GLB_SWREG_DISCONT_MODE 0x2002c
2209#define AR_GLB_SWREG_DISCONT_EN_BT_WLAN 0x3
2214 2210
2215#endif 2211#endif
diff --git a/drivers/net/wireless/ath/ath9k/xmit.c b/drivers/net/wireless/ath/ath9k/xmit.c
index 4d571394c7a8..cafb4a09729a 100644
--- a/drivers/net/wireless/ath/ath9k/xmit.c
+++ b/drivers/net/wireless/ath/ath9k/xmit.c
@@ -105,19 +105,19 @@ static int ath_max_4ms_framelen[4][32] = {
105/* Aggregation logic */ 105/* Aggregation logic */
106/*********************/ 106/*********************/
107 107
108static void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq) 108void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq)
109 __acquires(&txq->axq_lock) 109 __acquires(&txq->axq_lock)
110{ 110{
111 spin_lock_bh(&txq->axq_lock); 111 spin_lock_bh(&txq->axq_lock);
112} 112}
113 113
114static void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq) 114void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq)
115 __releases(&txq->axq_lock) 115 __releases(&txq->axq_lock)
116{ 116{
117 spin_unlock_bh(&txq->axq_lock); 117 spin_unlock_bh(&txq->axq_lock);
118} 118}
119 119
120static void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq) 120void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq)
121 __releases(&txq->axq_lock) 121 __releases(&txq->axq_lock)
122{ 122{
123 struct sk_buff_head q; 123 struct sk_buff_head q;
@@ -1165,6 +1165,7 @@ int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1165{ 1165{
1166 struct ath_atx_tid *txtid; 1166 struct ath_atx_tid *txtid;
1167 struct ath_node *an; 1167 struct ath_node *an;
1168 u8 density;
1168 1169
1169 an = (struct ath_node *)sta->drv_priv; 1170 an = (struct ath_node *)sta->drv_priv;
1170 txtid = ATH_AN_2_TID(an, tid); 1171 txtid = ATH_AN_2_TID(an, tid);
@@ -1172,6 +1173,17 @@ int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1172 if (txtid->state & (AGGR_CLEANUP | AGGR_ADDBA_COMPLETE)) 1173 if (txtid->state & (AGGR_CLEANUP | AGGR_ADDBA_COMPLETE))
1173 return -EAGAIN; 1174 return -EAGAIN;
1174 1175
1176 /* update ampdu factor/density, they may have changed. This may happen
1177 * in HT IBSS when a beacon with HT-info is received after the station
1178 * has already been added.
1179 */
1180 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1181 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
1182 sta->ht_cap.ampdu_factor);
1183 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
1184 an->mpdudensity = density;
1185 }
1186
1175 txtid->state |= AGGR_ADDBA_PROGRESS; 1187 txtid->state |= AGGR_ADDBA_PROGRESS;
1176 txtid->paused = true; 1188 txtid->paused = true;
1177 *ssn = txtid->seq_start = txtid->seq_next; 1189 *ssn = txtid->seq_start = txtid->seq_next;
@@ -1526,7 +1538,7 @@ bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1526 int i; 1538 int i;
1527 u32 npend = 0; 1539 u32 npend = 0;
1528 1540
1529 if (sc->sc_flags & SC_OP_INVALID) 1541 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
1530 return true; 1542 return true;
1531 1543
1532 ath9k_hw_abort_tx_dma(ah); 1544 ath9k_hw_abort_tx_dma(ah);
@@ -1999,6 +2011,7 @@ static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1999 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2011 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2000 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data; 2012 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
2001 int q, padpos, padsize; 2013 int q, padpos, padsize;
2014 unsigned long flags;
2002 2015
2003 ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb); 2016 ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb);
2004 2017
@@ -2017,6 +2030,7 @@ static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
2017 skb_pull(skb, padsize); 2030 skb_pull(skb, padsize);
2018 } 2031 }
2019 2032
2033 spin_lock_irqsave(&sc->sc_pm_lock, flags);
2020 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) { 2034 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) {
2021 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK; 2035 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
2022 ath_dbg(common, PS, 2036 ath_dbg(common, PS,
@@ -2026,6 +2040,7 @@ static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
2026 PS_WAIT_FOR_PSPOLL_DATA | 2040 PS_WAIT_FOR_PSPOLL_DATA |
2027 PS_WAIT_FOR_TX_ACK)); 2041 PS_WAIT_FOR_TX_ACK));
2028 } 2042 }
2043 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2029 2044
2030 q = skb_get_queue_mapping(skb); 2045 q = skb_get_queue_mapping(skb);
2031 if (txq == sc->tx.txq_map[q]) { 2046 if (txq == sc->tx.txq_map[q]) {
@@ -2236,46 +2251,6 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2236 ath_txq_unlock_complete(sc, txq); 2251 ath_txq_unlock_complete(sc, txq);
2237} 2252}
2238 2253
2239static void ath_tx_complete_poll_work(struct work_struct *work)
2240{
2241 struct ath_softc *sc = container_of(work, struct ath_softc,
2242 tx_complete_work.work);
2243 struct ath_txq *txq;
2244 int i;
2245 bool needreset = false;
2246#ifdef CONFIG_ATH9K_DEBUGFS
2247 sc->tx_complete_poll_work_seen++;
2248#endif
2249
2250 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
2251 if (ATH_TXQ_SETUP(sc, i)) {
2252 txq = &sc->tx.txq[i];
2253 ath_txq_lock(sc, txq);
2254 if (txq->axq_depth) {
2255 if (txq->axq_tx_inprogress) {
2256 needreset = true;
2257 ath_txq_unlock(sc, txq);
2258 break;
2259 } else {
2260 txq->axq_tx_inprogress = true;
2261 }
2262 }
2263 ath_txq_unlock_complete(sc, txq);
2264 }
2265
2266 if (needreset) {
2267 ath_dbg(ath9k_hw_common(sc->sc_ah), RESET,
2268 "tx hung, resetting the chip\n");
2269 RESET_STAT_INC(sc, RESET_TYPE_TX_HANG);
2270 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
2271 }
2272
2273 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2274 msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT));
2275}
2276
2277
2278
2279void ath_tx_tasklet(struct ath_softc *sc) 2254void ath_tx_tasklet(struct ath_softc *sc)
2280{ 2255{
2281 struct ath_hw *ah = sc->sc_ah; 2256 struct ath_hw *ah = sc->sc_ah;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-24 11:43:09 -0500