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-rw-r--r--drivers/net/wireless/ath/ath9k/Kconfig13
-rw-r--r--drivers/net/wireless/ath/ath9k/Makefile30
-rw-r--r--drivers/net/wireless/ath/ath9k/ahb.c29
-rw-r--r--drivers/net/wireless/ath/ath9k/ani.c141
-rw-r--r--drivers/net/wireless/ath/ath9k/ath9k.h205
-rw-r--r--drivers/net/wireless/ath/ath9k/beacon.c112
-rw-r--r--drivers/net/wireless/ath/ath9k/btcoex.c383
-rw-r--r--drivers/net/wireless/ath/ath9k/btcoex.h64
-rw-r--r--drivers/net/wireless/ath/ath9k/calib.c421
-rw-r--r--drivers/net/wireless/ath/ath9k/calib.h2
-rw-r--r--drivers/net/wireless/ath/ath9k/common.c295
-rw-r--r--drivers/net/wireless/ath/ath9k/common.h124
-rw-r--r--drivers/net/wireless/ath/ath9k/debug.c66
-rw-r--r--drivers/net/wireless/ath/ath9k/debug.h36
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom.c8
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom.h9
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_4k.c94
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_9287.c97
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_def.c183
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.c1310
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.h93
-rw-r--r--drivers/net/wireless/ath/ath9k/initvals.h101
-rw-r--r--drivers/net/wireless/ath/ath9k/mac.c162
-rw-r--r--drivers/net/wireless/ath/ath9k/mac.h11
-rw-r--r--drivers/net/wireless/ath/ath9k/main.c1247
-rw-r--r--drivers/net/wireless/ath/ath9k/pci.c47
-rw-r--r--drivers/net/wireless/ath/ath9k/phy.c1034
-rw-r--r--drivers/net/wireless/ath/ath9k/phy.h42
-rw-r--r--drivers/net/wireless/ath/ath9k/rc.c106
-rw-r--r--drivers/net/wireless/ath/ath9k/rc.h20
-rw-r--r--drivers/net/wireless/ath/ath9k/recv.c366
-rw-r--r--drivers/net/wireless/ath/ath9k/reg.h12
-rw-r--r--drivers/net/wireless/ath/ath9k/virtual.c110
-rw-r--r--drivers/net/wireless/ath/ath9k/xmit.c214
34 files changed, 4017 insertions, 3170 deletions
diff --git a/drivers/net/wireless/ath/ath9k/Kconfig b/drivers/net/wireless/ath/ath9k/Kconfig
index ef5f59c4dd80..006364f76bb4 100644
--- a/drivers/net/wireless/ath/ath9k/Kconfig
+++ b/drivers/net/wireless/ath/ath9k/Kconfig
@@ -1,9 +1,16 @@
1config ATH9K_HW
2 tristate
3config ATH9K_COMMON
4 tristate
5
1config ATH9K 6config ATH9K
2 tristate "Atheros 802.11n wireless cards support" 7 tristate "Atheros 802.11n wireless cards support"
3 depends on PCI && MAC80211 && WLAN_80211 8 depends on PCI && MAC80211
9 select ATH9K_HW
4 select MAC80211_LEDS 10 select MAC80211_LEDS
5 select LEDS_CLASS 11 select LEDS_CLASS
6 select NEW_LEDS 12 select NEW_LEDS
13 select ATH9K_COMMON
7 ---help--- 14 ---help---
8 This module adds support for wireless adapters based on 15 This module adds support for wireless adapters based on
9 Atheros IEEE 802.11n AR5008, AR9001 and AR9002 family 16 Atheros IEEE 802.11n AR5008, AR9001 and AR9002 family
@@ -16,6 +23,8 @@ config ATH9K
16 23
17 If you choose to build a module, it'll be called ath9k. 24 If you choose to build a module, it'll be called ath9k.
18 25
26if ATH_DEBUG
27
19config ATH9K_DEBUG 28config ATH9K_DEBUG
20 bool "Atheros ath9k debugging" 29 bool "Atheros ath9k debugging"
21 depends on ATH9K 30 depends on ATH9K
@@ -26,3 +35,5 @@ config ATH9K_DEBUG
26 modprobe ath9k debug=0x00000200 35 modprobe ath9k debug=0x00000200
27 36
28 Look in ath9k/debug.h for possible debug masks 37 Look in ath9k/debug.h for possible debug masks
38
39endif # ATH_DEBUG
diff --git a/drivers/net/wireless/ath/ath9k/Makefile b/drivers/net/wireless/ath/ath9k/Makefile
index ff2c9a26c10c..e53f9680a385 100644
--- a/drivers/net/wireless/ath/ath9k/Makefile
+++ b/drivers/net/wireless/ath/ath9k/Makefile
@@ -1,22 +1,28 @@
1ath9k-y += hw.o \ 1ath9k-y += beacon.o \
2 eeprom.o \
3 eeprom_def.o \
4 eeprom_4k.o \
5 eeprom_9287.o \
6 mac.o \
7 calib.o \
8 ani.o \
9 phy.o \
10 beacon.o \
11 main.o \ 2 main.o \
12 recv.o \ 3 recv.o \
13 xmit.o \ 4 xmit.o \
14 virtual.o \ 5 virtual.o \
15 rc.o \ 6 rc.o
16 btcoex.o
17 7
18ath9k-$(CONFIG_PCI) += pci.o 8ath9k-$(CONFIG_PCI) += pci.o
19ath9k-$(CONFIG_ATHEROS_AR71XX) += ahb.o 9ath9k-$(CONFIG_ATHEROS_AR71XX) += ahb.o
20ath9k-$(CONFIG_ATH9K_DEBUG) += debug.o 10ath9k-$(CONFIG_ATH9K_DEBUG) += debug.o
21 11
22obj-$(CONFIG_ATH9K) += ath9k.o 12obj-$(CONFIG_ATH9K) += ath9k.o
13
14ath9k_hw-y:= hw.o \
15 eeprom.o \
16 eeprom_def.o \
17 eeprom_4k.o \
18 eeprom_9287.o \
19 calib.o \
20 ani.o \
21 phy.o \
22 btcoex.o \
23 mac.o \
24
25obj-$(CONFIG_ATH9K_HW) += ath9k_hw.o
26
27obj-$(CONFIG_ATH9K_COMMON) += ath9k_common.o
28ath9k_common-y:= common.o
diff --git a/drivers/net/wireless/ath/ath9k/ahb.c b/drivers/net/wireless/ath/ath9k/ahb.c
index 2ad7d0280f7a..329e6bc137ab 100644
--- a/drivers/net/wireless/ath/ath9k/ahb.c
+++ b/drivers/net/wireless/ath/ath9k/ahb.c
@@ -22,27 +22,29 @@
22#include "ath9k.h" 22#include "ath9k.h"
23 23
24/* return bus cachesize in 4B word units */ 24/* return bus cachesize in 4B word units */
25static void ath_ahb_read_cachesize(struct ath_softc *sc, int *csz) 25static void ath_ahb_read_cachesize(struct ath_common *common, int *csz)
26{ 26{
27 *csz = L1_CACHE_BYTES >> 2; 27 *csz = L1_CACHE_BYTES >> 2;
28} 28}
29 29
30static void ath_ahb_cleanup(struct ath_softc *sc) 30static void ath_ahb_cleanup(struct ath_common *common)
31{ 31{
32 struct ath_softc *sc = (struct ath_softc *)common->priv;
32 iounmap(sc->mem); 33 iounmap(sc->mem);
33} 34}
34 35
35static bool ath_ahb_eeprom_read(struct ath_hw *ah, u32 off, u16 *data) 36static bool ath_ahb_eeprom_read(struct ath_common *common, u32 off, u16 *data)
36{ 37{
37 struct ath_softc *sc = ah->ah_sc; 38 struct ath_softc *sc = (struct ath_softc *)common->priv;
38 struct platform_device *pdev = to_platform_device(sc->dev); 39 struct platform_device *pdev = to_platform_device(sc->dev);
39 struct ath9k_platform_data *pdata; 40 struct ath9k_platform_data *pdata;
40 41
41 pdata = (struct ath9k_platform_data *) pdev->dev.platform_data; 42 pdata = (struct ath9k_platform_data *) pdev->dev.platform_data;
42 if (off >= (ARRAY_SIZE(pdata->eeprom_data))) { 43 if (off >= (ARRAY_SIZE(pdata->eeprom_data))) {
43 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 44 ath_print(common, ATH_DBG_FATAL,
44 "%s: flash read failed, offset %08x is out of range\n", 45 "%s: flash read failed, offset %08x "
45 __func__, off); 46 "is out of range\n",
47 __func__, off);
46 return false; 48 return false;
47 } 49 }
48 50
@@ -67,6 +69,7 @@ static int ath_ahb_probe(struct platform_device *pdev)
67 int irq; 69 int irq;
68 int ret = 0; 70 int ret = 0;
69 struct ath_hw *ah; 71 struct ath_hw *ah;
72 char hw_name[64];
70 73
71 if (!pdev->dev.platform_data) { 74 if (!pdev->dev.platform_data) {
72 dev_err(&pdev->dev, "no platform data specified\n"); 75 dev_err(&pdev->dev, "no platform data specified\n");
@@ -116,10 +119,9 @@ static int ath_ahb_probe(struct platform_device *pdev)
116 sc->hw = hw; 119 sc->hw = hw;
117 sc->dev = &pdev->dev; 120 sc->dev = &pdev->dev;
118 sc->mem = mem; 121 sc->mem = mem;
119 sc->bus_ops = &ath_ahb_bus_ops;
120 sc->irq = irq; 122 sc->irq = irq;
121 123
122 ret = ath_init_device(AR5416_AR9100_DEVID, sc, 0x0); 124 ret = ath_init_device(AR5416_AR9100_DEVID, sc, 0x0, &ath_ahb_bus_ops);
123 if (ret) { 125 if (ret) {
124 dev_err(&pdev->dev, "failed to initialize device\n"); 126 dev_err(&pdev->dev, "failed to initialize device\n");
125 goto err_free_hw; 127 goto err_free_hw;
@@ -132,14 +134,11 @@ static int ath_ahb_probe(struct platform_device *pdev)
132 } 134 }
133 135
134 ah = sc->sc_ah; 136 ah = sc->sc_ah;
137 ath9k_hw_name(ah, hw_name, sizeof(hw_name));
135 printk(KERN_INFO 138 printk(KERN_INFO
136 "%s: Atheros AR%s MAC/BB Rev:%x, " 139 "%s: %s mem=0x%lx, irq=%d\n",
137 "AR%s RF Rev:%x, mem=0x%lx, irq=%d\n",
138 wiphy_name(hw->wiphy), 140 wiphy_name(hw->wiphy),
139 ath_mac_bb_name(ah->hw_version.macVersion), 141 hw_name,
140 ah->hw_version.macRev,
141 ath_rf_name((ah->hw_version.analog5GhzRev & AR_RADIO_SREV_MAJOR)),
142 ah->hw_version.phyRev,
143 (unsigned long)mem, irq); 142 (unsigned long)mem, irq);
144 143
145 return 0; 144 return 0;
diff --git a/drivers/net/wireless/ath/ath9k/ani.c b/drivers/net/wireless/ath/ath9k/ani.c
index 2b493742ef10..2a0cd64c2bfb 100644
--- a/drivers/net/wireless/ath/ath9k/ani.c
+++ b/drivers/net/wireless/ath/ath9k/ani.c
@@ -14,7 +14,7 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17#include "ath9k.h" 17#include "hw.h"
18 18
19static int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah, 19static int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah,
20 struct ath9k_channel *chan) 20 struct ath9k_channel *chan)
@@ -31,8 +31,8 @@ static int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah,
31 } 31 }
32 } 32 }
33 33
34 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 34 ath_print(ath9k_hw_common(ah), ATH_DBG_ANI,
35 "No more channel states left. Using channel 0\n"); 35 "No more channel states left. Using channel 0\n");
36 36
37 return 0; 37 return 0;
38} 38}
@@ -41,16 +41,17 @@ static bool ath9k_hw_ani_control(struct ath_hw *ah,
41 enum ath9k_ani_cmd cmd, int param) 41 enum ath9k_ani_cmd cmd, int param)
42{ 42{
43 struct ar5416AniState *aniState = ah->curani; 43 struct ar5416AniState *aniState = ah->curani;
44 struct ath_common *common = ath9k_hw_common(ah);
44 45
45 switch (cmd & ah->ani_function) { 46 switch (cmd & ah->ani_function) {
46 case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{ 47 case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
47 u32 level = param; 48 u32 level = param;
48 49
49 if (level >= ARRAY_SIZE(ah->totalSizeDesired)) { 50 if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
50 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 51 ath_print(common, ATH_DBG_ANI,
51 "level out of range (%u > %u)\n", 52 "level out of range (%u > %u)\n",
52 level, 53 level,
53 (unsigned)ARRAY_SIZE(ah->totalSizeDesired)); 54 (unsigned)ARRAY_SIZE(ah->totalSizeDesired));
54 return false; 55 return false;
55 } 56 }
56 57
@@ -152,10 +153,10 @@ static bool ath9k_hw_ani_control(struct ath_hw *ah,
152 u32 level = param; 153 u32 level = param;
153 154
154 if (level >= ARRAY_SIZE(firstep)) { 155 if (level >= ARRAY_SIZE(firstep)) {
155 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 156 ath_print(common, ATH_DBG_ANI,
156 "level out of range (%u > %u)\n", 157 "level out of range (%u > %u)\n",
157 level, 158 level,
158 (unsigned) ARRAY_SIZE(firstep)); 159 (unsigned) ARRAY_SIZE(firstep));
159 return false; 160 return false;
160 } 161 }
161 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, 162 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
@@ -174,11 +175,10 @@ static bool ath9k_hw_ani_control(struct ath_hw *ah,
174 u32 level = param; 175 u32 level = param;
175 176
176 if (level >= ARRAY_SIZE(cycpwrThr1)) { 177 if (level >= ARRAY_SIZE(cycpwrThr1)) {
177 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 178 ath_print(common, ATH_DBG_ANI,
178 "level out of range (%u > %u)\n", 179 "level out of range (%u > %u)\n",
179 level, 180 level,
180 (unsigned) 181 (unsigned) ARRAY_SIZE(cycpwrThr1));
181 ARRAY_SIZE(cycpwrThr1));
182 return false; 182 return false;
183 } 183 }
184 REG_RMW_FIELD(ah, AR_PHY_TIMING5, 184 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
@@ -194,25 +194,28 @@ static bool ath9k_hw_ani_control(struct ath_hw *ah,
194 case ATH9K_ANI_PRESENT: 194 case ATH9K_ANI_PRESENT:
195 break; 195 break;
196 default: 196 default:
197 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 197 ath_print(common, ATH_DBG_ANI,
198 "invalid cmd %u\n", cmd); 198 "invalid cmd %u\n", cmd);
199 return false; 199 return false;
200 } 200 }
201 201
202 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "ANI parameters:\n"); 202 ath_print(common, ATH_DBG_ANI, "ANI parameters:\n");
203 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 203 ath_print(common, ATH_DBG_ANI,
204 "noiseImmunityLevel=%d, spurImmunityLevel=%d, " 204 "noiseImmunityLevel=%d, spurImmunityLevel=%d, "
205 "ofdmWeakSigDetectOff=%d\n", 205 "ofdmWeakSigDetectOff=%d\n",
206 aniState->noiseImmunityLevel, aniState->spurImmunityLevel, 206 aniState->noiseImmunityLevel,
207 !aniState->ofdmWeakSigDetectOff); 207 aniState->spurImmunityLevel,
208 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 208 !aniState->ofdmWeakSigDetectOff);
209 "cckWeakSigThreshold=%d, " 209 ath_print(common, ATH_DBG_ANI,
210 "firstepLevel=%d, listenTime=%d\n", 210 "cckWeakSigThreshold=%d, "
211 aniState->cckWeakSigThreshold, aniState->firstepLevel, 211 "firstepLevel=%d, listenTime=%d\n",
212 aniState->listenTime); 212 aniState->cckWeakSigThreshold,
213 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 213 aniState->firstepLevel,
214 aniState->listenTime);
215 ath_print(common, ATH_DBG_ANI,
214 "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n", 216 "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
215 aniState->cycleCount, aniState->ofdmPhyErrCount, 217 aniState->cycleCount,
218 aniState->ofdmPhyErrCount,
216 aniState->cckPhyErrCount); 219 aniState->cckPhyErrCount);
217 220
218 return true; 221 return true;
@@ -231,6 +234,7 @@ static void ath9k_hw_update_mibstats(struct ath_hw *ah,
231static void ath9k_ani_restart(struct ath_hw *ah) 234static void ath9k_ani_restart(struct ath_hw *ah)
232{ 235{
233 struct ar5416AniState *aniState; 236 struct ar5416AniState *aniState;
237 struct ath_common *common = ath9k_hw_common(ah);
234 238
235 if (!DO_ANI(ah)) 239 if (!DO_ANI(ah))
236 return; 240 return;
@@ -240,24 +244,24 @@ static void ath9k_ani_restart(struct ath_hw *ah)
240 244
241 if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) { 245 if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) {
242 aniState->ofdmPhyErrBase = 0; 246 aniState->ofdmPhyErrBase = 0;
243 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 247 ath_print(common, ATH_DBG_ANI,
244 "OFDM Trigger is too high for hw counters\n"); 248 "OFDM Trigger is too high for hw counters\n");
245 } else { 249 } else {
246 aniState->ofdmPhyErrBase = 250 aniState->ofdmPhyErrBase =
247 AR_PHY_COUNTMAX - aniState->ofdmTrigHigh; 251 AR_PHY_COUNTMAX - aniState->ofdmTrigHigh;
248 } 252 }
249 if (aniState->cckTrigHigh > AR_PHY_COUNTMAX) { 253 if (aniState->cckTrigHigh > AR_PHY_COUNTMAX) {
250 aniState->cckPhyErrBase = 0; 254 aniState->cckPhyErrBase = 0;
251 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 255 ath_print(common, ATH_DBG_ANI,
252 "CCK Trigger is too high for hw counters\n"); 256 "CCK Trigger is too high for hw counters\n");
253 } else { 257 } else {
254 aniState->cckPhyErrBase = 258 aniState->cckPhyErrBase =
255 AR_PHY_COUNTMAX - aniState->cckTrigHigh; 259 AR_PHY_COUNTMAX - aniState->cckTrigHigh;
256 } 260 }
257 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 261 ath_print(common, ATH_DBG_ANI,
258 "Writing ofdmbase=%u cckbase=%u\n", 262 "Writing ofdmbase=%u cckbase=%u\n",
259 aniState->ofdmPhyErrBase, 263 aniState->ofdmPhyErrBase,
260 aniState->cckPhyErrBase); 264 aniState->cckPhyErrBase);
261 REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase); 265 REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase);
262 REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase); 266 REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase);
263 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 267 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
@@ -271,7 +275,7 @@ static void ath9k_ani_restart(struct ath_hw *ah)
271 275
272static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hw *ah) 276static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hw *ah)
273{ 277{
274 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; 278 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
275 struct ar5416AniState *aniState; 279 struct ar5416AniState *aniState;
276 int32_t rssi; 280 int32_t rssi;
277 281
@@ -343,7 +347,7 @@ static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hw *ah)
343 347
344static void ath9k_hw_ani_cck_err_trigger(struct ath_hw *ah) 348static void ath9k_hw_ani_cck_err_trigger(struct ath_hw *ah)
345{ 349{
346 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; 350 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
347 struct ar5416AniState *aniState; 351 struct ar5416AniState *aniState;
348 int32_t rssi; 352 int32_t rssi;
349 353
@@ -464,6 +468,7 @@ void ath9k_ani_reset(struct ath_hw *ah)
464{ 468{
465 struct ar5416AniState *aniState; 469 struct ar5416AniState *aniState;
466 struct ath9k_channel *chan = ah->curchan; 470 struct ath9k_channel *chan = ah->curchan;
471 struct ath_common *common = ath9k_hw_common(ah);
467 int index; 472 int index;
468 473
469 if (!DO_ANI(ah)) 474 if (!DO_ANI(ah))
@@ -475,8 +480,8 @@ void ath9k_ani_reset(struct ath_hw *ah)
475 480
476 if (DO_ANI(ah) && ah->opmode != NL80211_IFTYPE_STATION 481 if (DO_ANI(ah) && ah->opmode != NL80211_IFTYPE_STATION
477 && ah->opmode != NL80211_IFTYPE_ADHOC) { 482 && ah->opmode != NL80211_IFTYPE_ADHOC) {
478 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 483 ath_print(common, ATH_DBG_ANI,
479 "Reset ANI state opmode %u\n", ah->opmode); 484 "Reset ANI state opmode %u\n", ah->opmode);
480 ah->stats.ast_ani_reset++; 485 ah->stats.ast_ani_reset++;
481 486
482 if (ah->opmode == NL80211_IFTYPE_AP) { 487 if (ah->opmode == NL80211_IFTYPE_AP) {
@@ -543,6 +548,7 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah,
543 struct ath9k_channel *chan) 548 struct ath9k_channel *chan)
544{ 549{
545 struct ar5416AniState *aniState; 550 struct ar5416AniState *aniState;
551 struct ath_common *common = ath9k_hw_common(ah);
546 int32_t listenTime; 552 int32_t listenTime;
547 u32 phyCnt1, phyCnt2; 553 u32 phyCnt1, phyCnt2;
548 u32 ofdmPhyErrCnt, cckPhyErrCnt; 554 u32 ofdmPhyErrCnt, cckPhyErrCnt;
@@ -569,20 +575,22 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah,
569 if (phyCnt1 < aniState->ofdmPhyErrBase || 575 if (phyCnt1 < aniState->ofdmPhyErrBase ||
570 phyCnt2 < aniState->cckPhyErrBase) { 576 phyCnt2 < aniState->cckPhyErrBase) {
571 if (phyCnt1 < aniState->ofdmPhyErrBase) { 577 if (phyCnt1 < aniState->ofdmPhyErrBase) {
572 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 578 ath_print(common, ATH_DBG_ANI,
573 "phyCnt1 0x%x, resetting " 579 "phyCnt1 0x%x, resetting "
574 "counter value to 0x%x\n", 580 "counter value to 0x%x\n",
575 phyCnt1, aniState->ofdmPhyErrBase); 581 phyCnt1,
582 aniState->ofdmPhyErrBase);
576 REG_WRITE(ah, AR_PHY_ERR_1, 583 REG_WRITE(ah, AR_PHY_ERR_1,
577 aniState->ofdmPhyErrBase); 584 aniState->ofdmPhyErrBase);
578 REG_WRITE(ah, AR_PHY_ERR_MASK_1, 585 REG_WRITE(ah, AR_PHY_ERR_MASK_1,
579 AR_PHY_ERR_OFDM_TIMING); 586 AR_PHY_ERR_OFDM_TIMING);
580 } 587 }
581 if (phyCnt2 < aniState->cckPhyErrBase) { 588 if (phyCnt2 < aniState->cckPhyErrBase) {
582 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 589 ath_print(common, ATH_DBG_ANI,
583 "phyCnt2 0x%x, resetting " 590 "phyCnt2 0x%x, resetting "
584 "counter value to 0x%x\n", 591 "counter value to 0x%x\n",
585 phyCnt2, aniState->cckPhyErrBase); 592 phyCnt2,
593 aniState->cckPhyErrBase);
586 REG_WRITE(ah, AR_PHY_ERR_2, 594 REG_WRITE(ah, AR_PHY_ERR_2,
587 aniState->cckPhyErrBase); 595 aniState->cckPhyErrBase);
588 REG_WRITE(ah, AR_PHY_ERR_MASK_2, 596 REG_WRITE(ah, AR_PHY_ERR_MASK_2,
@@ -621,10 +629,13 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah,
621 } 629 }
622 } 630 }
623} 631}
632EXPORT_SYMBOL(ath9k_hw_ani_monitor);
624 633
625void ath9k_enable_mib_counters(struct ath_hw *ah) 634void ath9k_enable_mib_counters(struct ath_hw *ah)
626{ 635{
627 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Enable MIB counters\n"); 636 struct ath_common *common = ath9k_hw_common(ah);
637
638 ath_print(common, ATH_DBG_ANI, "Enable MIB counters\n");
628 639
629 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); 640 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
630 641
@@ -640,7 +651,10 @@ void ath9k_enable_mib_counters(struct ath_hw *ah)
640/* Freeze the MIB counters, get the stats and then clear them */ 651/* Freeze the MIB counters, get the stats and then clear them */
641void ath9k_hw_disable_mib_counters(struct ath_hw *ah) 652void ath9k_hw_disable_mib_counters(struct ath_hw *ah)
642{ 653{
643 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Disable MIB counters\n"); 654 struct ath_common *common = ath9k_hw_common(ah);
655
656 ath_print(common, ATH_DBG_ANI, "Disable MIB counters\n");
657
644 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC); 658 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC);
645 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); 659 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
646 REG_WRITE(ah, AR_MIBC, AR_MIBC_CMC); 660 REG_WRITE(ah, AR_MIBC, AR_MIBC_CMC);
@@ -653,6 +667,7 @@ u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hw *ah,
653 u32 *rxf_pcnt, 667 u32 *rxf_pcnt,
654 u32 *txf_pcnt) 668 u32 *txf_pcnt)
655{ 669{
670 struct ath_common *common = ath9k_hw_common(ah);
656 static u32 cycles, rx_clear, rx_frame, tx_frame; 671 static u32 cycles, rx_clear, rx_frame, tx_frame;
657 u32 good = 1; 672 u32 good = 1;
658 673
@@ -662,8 +677,8 @@ u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hw *ah,
662 u32 cc = REG_READ(ah, AR_CCCNT); 677 u32 cc = REG_READ(ah, AR_CCCNT);
663 678
664 if (cycles == 0 || cycles > cc) { 679 if (cycles == 0 || cycles > cc) {
665 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 680 ath_print(common, ATH_DBG_ANI,
666 "cycle counter wrap. ExtBusy = 0\n"); 681 "cycle counter wrap. ExtBusy = 0\n");
667 good = 0; 682 good = 0;
668 } else { 683 } else {
669 u32 cc_d = cc - cycles; 684 u32 cc_d = cc - cycles;
@@ -742,6 +757,7 @@ void ath9k_hw_procmibevent(struct ath_hw *ah)
742 ath9k_ani_restart(ah); 757 ath9k_ani_restart(ah);
743 } 758 }
744} 759}
760EXPORT_SYMBOL(ath9k_hw_procmibevent);
745 761
746void ath9k_hw_ani_setup(struct ath_hw *ah) 762void ath9k_hw_ani_setup(struct ath_hw *ah)
747{ 763{
@@ -762,9 +778,10 @@ void ath9k_hw_ani_setup(struct ath_hw *ah)
762 778
763void ath9k_hw_ani_init(struct ath_hw *ah) 779void ath9k_hw_ani_init(struct ath_hw *ah)
764{ 780{
781 struct ath_common *common = ath9k_hw_common(ah);
765 int i; 782 int i;
766 783
767 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Initialize ANI\n"); 784 ath_print(common, ATH_DBG_ANI, "Initialize ANI\n");
768 785
769 memset(ah->ani, 0, sizeof(ah->ani)); 786 memset(ah->ani, 0, sizeof(ah->ani));
770 for (i = 0; i < ARRAY_SIZE(ah->ani); i++) { 787 for (i = 0; i < ARRAY_SIZE(ah->ani); i++) {
@@ -786,11 +803,11 @@ void ath9k_hw_ani_init(struct ath_hw *ah)
786 AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH; 803 AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH;
787 } 804 }
788 805
789 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 806 ath_print(common, ATH_DBG_ANI,
790 "Setting OfdmErrBase = 0x%08x\n", 807 "Setting OfdmErrBase = 0x%08x\n",
791 ah->ani[0].ofdmPhyErrBase); 808 ah->ani[0].ofdmPhyErrBase);
792 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n", 809 ath_print(common, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n",
793 ah->ani[0].cckPhyErrBase); 810 ah->ani[0].cckPhyErrBase);
794 811
795 REG_WRITE(ah, AR_PHY_ERR_1, ah->ani[0].ofdmPhyErrBase); 812 REG_WRITE(ah, AR_PHY_ERR_1, ah->ani[0].ofdmPhyErrBase);
796 REG_WRITE(ah, AR_PHY_ERR_2, ah->ani[0].cckPhyErrBase); 813 REG_WRITE(ah, AR_PHY_ERR_2, ah->ani[0].cckPhyErrBase);
@@ -803,7 +820,7 @@ void ath9k_hw_ani_init(struct ath_hw *ah)
803 820
804void ath9k_hw_ani_disable(struct ath_hw *ah) 821void ath9k_hw_ani_disable(struct ath_hw *ah)
805{ 822{
806 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Disabling ANI\n"); 823 ath_print(ath9k_hw_common(ah), ATH_DBG_ANI, "Disabling ANI\n");
807 824
808 ath9k_hw_disable_mib_counters(ah); 825 ath9k_hw_disable_mib_counters(ah);
809 REG_WRITE(ah, AR_PHY_ERR_1, 0); 826 REG_WRITE(ah, AR_PHY_ERR_1, 0);
diff --git a/drivers/net/wireless/ath/ath9k/ath9k.h b/drivers/net/wireless/ath/ath9k/ath9k.h
index 1d59f10f68da..2a40fa2cd914 100644
--- a/drivers/net/wireless/ath/ath9k/ath9k.h
+++ b/drivers/net/wireless/ath/ath9k/ath9k.h
@@ -19,14 +19,16 @@
19 19
20#include <linux/etherdevice.h> 20#include <linux/etherdevice.h>
21#include <linux/device.h> 21#include <linux/device.h>
22#include <net/mac80211.h>
23#include <linux/leds.h> 22#include <linux/leds.h>
24 23
25#include "hw.h"
26#include "rc.h" 24#include "rc.h"
27#include "debug.h" 25#include "debug.h"
28#include "../ath.h" 26#include "common.h"
29#include "btcoex.h" 27
28/*
29 * Header for the ath9k.ko driver core *only* -- hw code nor any other driver
30 * should rely on this file or its contents.
31 */
30 32
31struct ath_node; 33struct ath_node;
32 34
@@ -54,15 +56,11 @@ struct ath_node;
54 56
55#define A_MAX(a, b) ((a) > (b) ? (a) : (b)) 57#define A_MAX(a, b) ((a) > (b) ? (a) : (b))
56 58
57#define ASSERT(exp) BUG_ON(!(exp))
58
59#define TSF_TO_TU(_h,_l) \ 59#define TSF_TO_TU(_h,_l) \
60 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10)) 60 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
61 61
62#define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i)) 62#define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i))
63 63
64static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
65
66struct ath_config { 64struct ath_config {
67 u32 ath_aggr_prot; 65 u32 ath_aggr_prot;
68 u16 txpowlimit; 66 u16 txpowlimit;
@@ -103,18 +101,6 @@ enum buffer_type {
103 BUF_XRETRY = BIT(5), 101 BUF_XRETRY = BIT(5),
104}; 102};
105 103
106struct ath_buf_state {
107 int bfs_nframes;
108 u16 bfs_al;
109 u16 bfs_frmlen;
110 int bfs_seqno;
111 int bfs_tidno;
112 int bfs_retries;
113 u8 bf_type;
114 u32 bfs_keyix;
115 enum ath9k_key_type bfs_keytype;
116};
117
118#define bf_nframes bf_state.bfs_nframes 104#define bf_nframes bf_state.bfs_nframes
119#define bf_al bf_state.bfs_al 105#define bf_al bf_state.bfs_al
120#define bf_frmlen bf_state.bfs_frmlen 106#define bf_frmlen bf_state.bfs_frmlen
@@ -129,21 +115,6 @@ struct ath_buf_state {
129#define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY) 115#define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY)
130#define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY) 116#define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY)
131 117
132struct ath_buf {
133 struct list_head list;
134 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
135 an aggregate) */
136 struct ath_buf *bf_next; /* next subframe in the aggregate */
137 struct sk_buff *bf_mpdu; /* enclosing frame structure */
138 struct ath_desc *bf_desc; /* virtual addr of desc */
139 dma_addr_t bf_daddr; /* physical addr of desc */
140 dma_addr_t bf_buf_addr; /* physical addr of data buffer */
141 bool bf_stale;
142 u16 bf_flags;
143 struct ath_buf_state bf_state;
144 dma_addr_t bf_dmacontext;
145};
146
147struct ath_descdma { 118struct ath_descdma {
148 struct ath_desc *dd_desc; 119 struct ath_desc *dd_desc;
149 dma_addr_t dd_desc_paddr; 120 dma_addr_t dd_desc_paddr;
@@ -163,13 +134,9 @@ void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
163 134
164#define ATH_MAX_ANTENNA 3 135#define ATH_MAX_ANTENNA 3
165#define ATH_RXBUF 512 136#define ATH_RXBUF 512
166#define WME_NUM_TID 16
167#define ATH_TXBUF 512 137#define ATH_TXBUF 512
168#define ATH_TXMAXTRY 13 138#define ATH_TXMAXTRY 13
169#define ATH_MGT_TXMAXTRY 4 139#define ATH_MGT_TXMAXTRY 4
170#define WME_BA_BMP_SIZE 64
171#define WME_MAX_BA WME_BA_BMP_SIZE
172#define ATH_TID_MAX_BUFS (2 * WME_MAX_BA)
173 140
174#define TID_TO_WME_AC(_tid) \ 141#define TID_TO_WME_AC(_tid) \
175 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \ 142 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
@@ -177,12 +144,6 @@ void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
177 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \ 144 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
178 WME_AC_VO) 145 WME_AC_VO)
179 146
180#define WME_AC_BE 0
181#define WME_AC_BK 1
182#define WME_AC_VI 2
183#define WME_AC_VO 3
184#define WME_NUM_AC 4
185
186#define ADDBA_EXCHANGE_ATTEMPTS 10 147#define ADDBA_EXCHANGE_ATTEMPTS 10
187#define ATH_AGGR_DELIM_SZ 4 148#define ATH_AGGR_DELIM_SZ 4
188#define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */ 149#define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
@@ -191,7 +152,6 @@ void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
191/* minimum h/w qdepth to be sustained to maximize aggregation */ 152/* minimum h/w qdepth to be sustained to maximize aggregation */
192#define ATH_AGGR_MIN_QDEPTH 2 153#define ATH_AGGR_MIN_QDEPTH 2
193#define ATH_AMPDU_SUBFRAME_DEFAULT 32 154#define ATH_AMPDU_SUBFRAME_DEFAULT 32
194#define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
195 155
196#define IEEE80211_SEQ_SEQ_SHIFT 4 156#define IEEE80211_SEQ_SEQ_SHIFT 4
197#define IEEE80211_SEQ_MAX 4096 157#define IEEE80211_SEQ_MAX 4096
@@ -238,18 +198,8 @@ struct ath_txq {
238 struct list_head axq_q; 198 struct list_head axq_q;
239 spinlock_t axq_lock; 199 spinlock_t axq_lock;
240 u32 axq_depth; 200 u32 axq_depth;
241 u8 axq_aggr_depth;
242 bool stopped; 201 bool stopped;
243 bool axq_tx_inprogress; 202 bool axq_tx_inprogress;
244 struct ath_buf *axq_linkbuf;
245
246 /* first desc of the last descriptor that contains CTS */
247 struct ath_desc *axq_lastdsWithCTS;
248
249 /* final desc of the gating desc that determines whether
250 lastdsWithCTS has been DMA'ed or not */
251 struct ath_desc *axq_gatingds;
252
253 struct list_head axq_acq; 203 struct list_head axq_acq;
254}; 204};
255 205
@@ -257,30 +207,6 @@ struct ath_txq {
257#define AGGR_ADDBA_COMPLETE BIT(2) 207#define AGGR_ADDBA_COMPLETE BIT(2)
258#define AGGR_ADDBA_PROGRESS BIT(3) 208#define AGGR_ADDBA_PROGRESS BIT(3)
259 209
260struct ath_atx_tid {
261 struct list_head list;
262 struct list_head buf_q;
263 struct ath_node *an;
264 struct ath_atx_ac *ac;
265 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS];
266 u16 seq_start;
267 u16 seq_next;
268 u16 baw_size;
269 int tidno;
270 int baw_head; /* first un-acked tx buffer */
271 int baw_tail; /* next unused tx buffer slot */
272 int sched;
273 int paused;
274 u8 state;
275};
276
277struct ath_atx_ac {
278 int sched;
279 int qnum;
280 struct list_head list;
281 struct list_head tid_q;
282};
283
284struct ath_tx_control { 210struct ath_tx_control {
285 struct ath_txq *txq; 211 struct ath_txq *txq;
286 int if_id; 212 int if_id;
@@ -291,30 +217,6 @@ struct ath_tx_control {
291#define ATH_TX_XRETRY 0x02 217#define ATH_TX_XRETRY 0x02
292#define ATH_TX_BAR 0x04 218#define ATH_TX_BAR 0x04
293 219
294#define ATH_RSSI_LPF_LEN 10
295#define RSSI_LPF_THRESHOLD -20
296#define ATH9K_RSSI_BAD 0x80
297#define ATH_RSSI_EP_MULTIPLIER (1<<7)
298#define ATH_EP_MUL(x, mul) ((x) * (mul))
299#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), ATH_RSSI_EP_MULTIPLIER))
300#define ATH_LPF_RSSI(x, y, len) \
301 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y))
302#define ATH_RSSI_LPF(x, y) do { \
303 if ((y) >= RSSI_LPF_THRESHOLD) \
304 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \
305} while (0)
306#define ATH_EP_RND(x, mul) \
307 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
308
309struct ath_node {
310 struct ath_softc *an_sc;
311 struct ath_atx_tid tid[WME_NUM_TID];
312 struct ath_atx_ac ac[WME_NUM_AC];
313 u16 maxampdu;
314 u8 mpdudensity;
315 int last_rssi;
316};
317
318struct ath_tx { 220struct ath_tx {
319 u16 seq_no; 221 u16 seq_no;
320 u32 txqsetup; 222 u32 txqsetup;
@@ -329,7 +231,6 @@ struct ath_rx {
329 u8 defant; 231 u8 defant;
330 u8 rxotherant; 232 u8 rxotherant;
331 u32 *rxlink; 233 u32 *rxlink;
332 int bufsize;
333 unsigned int rxfilter; 234 unsigned int rxfilter;
334 spinlock_t rxflushlock; 235 spinlock_t rxflushlock;
335 spinlock_t rxbuflock; 236 spinlock_t rxbuflock;
@@ -427,7 +328,6 @@ struct ath_beacon {
427 328
428void ath_beacon_tasklet(unsigned long data); 329void ath_beacon_tasklet(unsigned long data);
429void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif); 330void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif);
430int ath_beaconq_setup(struct ath_hw *ah);
431int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif); 331int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif);
432void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp); 332void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp);
433 333
@@ -441,14 +341,24 @@ void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp);
441#define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */ 341#define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */
442#define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */ 342#define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */
443 343
444struct ath_ani { 344/* Defines the BT AR_BT_COEX_WGHT used */
445 bool caldone; 345enum ath_stomp_type {
446 int16_t noise_floor; 346 ATH_BTCOEX_NO_STOMP,
447 unsigned int longcal_timer; 347 ATH_BTCOEX_STOMP_ALL,
448 unsigned int shortcal_timer; 348 ATH_BTCOEX_STOMP_LOW,
449 unsigned int resetcal_timer; 349 ATH_BTCOEX_STOMP_NONE
450 unsigned int checkani_timer; 350};
451 struct timer_list timer; 351
352struct ath_btcoex {
353 bool hw_timer_enabled;
354 spinlock_t btcoex_lock;
355 struct timer_list period_timer; /* Timer for BT period */
356 u32 bt_priority_cnt;
357 unsigned long bt_priority_time;
358 int bt_stomp_type; /* Types of BT stomping */
359 u32 btcoex_no_stomp; /* in usec */
360 u32 btcoex_period; /* in usec */
361 struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */
452}; 362};
453 363
454/********************/ 364/********************/
@@ -484,25 +394,13 @@ struct ath_led {
484 * Used when PCI device not fully initialized by bootrom/BIOS 394 * Used when PCI device not fully initialized by bootrom/BIOS
485*/ 395*/
486#define DEFAULT_CACHELINE 32 396#define DEFAULT_CACHELINE 32
487#define ATH_DEFAULT_NOISE_FLOOR -95
488#define ATH_REGCLASSIDS_MAX 10 397#define ATH_REGCLASSIDS_MAX 10
489#define ATH_CABQ_READY_TIME 80 /* % of beacon interval */ 398#define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
490#define ATH_MAX_SW_RETRIES 10 399#define ATH_MAX_SW_RETRIES 10
491#define ATH_CHAN_MAX 255 400#define ATH_CHAN_MAX 255
492#define IEEE80211_WEP_NKID 4 /* number of key ids */ 401#define IEEE80211_WEP_NKID 4 /* number of key ids */
493 402
494/*
495 * The key cache is used for h/w cipher state and also for
496 * tracking station state such as the current tx antenna.
497 * We also setup a mapping table between key cache slot indices
498 * and station state to short-circuit node lookups on rx.
499 * Different parts have different size key caches. We handle
500 * up to ATH_KEYMAX entries (could dynamically allocate state).
501 */
502#define ATH_KEYMAX 128 /* max key cache size we handle */
503
504#define ATH_TXPOWER_MAX 100 /* .5 dBm units */ 403#define ATH_TXPOWER_MAX 100 /* .5 dBm units */
505#define ATH_RSSI_DUMMY_MARKER 0x127
506#define ATH_RATE_DUMMY_MARKER 0 404#define ATH_RATE_DUMMY_MARKER 0
507 405
508#define SC_OP_INVALID BIT(0) 406#define SC_OP_INVALID BIT(0)
@@ -522,23 +420,14 @@ struct ath_led {
522#define SC_OP_WAIT_FOR_PSPOLL_DATA BIT(17) 420#define SC_OP_WAIT_FOR_PSPOLL_DATA BIT(17)
523#define SC_OP_WAIT_FOR_TX_ACK BIT(18) 421#define SC_OP_WAIT_FOR_TX_ACK BIT(18)
524#define SC_OP_BEACON_SYNC BIT(19) 422#define SC_OP_BEACON_SYNC BIT(19)
525#define SC_OP_BTCOEX_ENABLED BIT(20)
526#define SC_OP_BT_PRIORITY_DETECTED BIT(21) 423#define SC_OP_BT_PRIORITY_DETECTED BIT(21)
527 424
528struct ath_bus_ops {
529 void (*read_cachesize)(struct ath_softc *sc, int *csz);
530 void (*cleanup)(struct ath_softc *sc);
531 bool (*eeprom_read)(struct ath_hw *ah, u32 off, u16 *data);
532};
533
534struct ath_wiphy; 425struct ath_wiphy;
535 426
536struct ath_softc { 427struct ath_softc {
537 struct ieee80211_hw *hw; 428 struct ieee80211_hw *hw;
538 struct device *dev; 429 struct device *dev;
539 430
540 struct ath_common common;
541
542 spinlock_t wiphy_lock; /* spinlock to protect ath_wiphy data */ 431 spinlock_t wiphy_lock; /* spinlock to protect ath_wiphy data */
543 struct ath_wiphy *pri_wiphy; 432 struct ath_wiphy *pri_wiphy;
544 struct ath_wiphy **sec_wiphy; /* secondary wiphys (virtual radios); may 433 struct ath_wiphy **sec_wiphy; /* secondary wiphys (virtual radios); may
@@ -565,24 +454,14 @@ struct ath_softc {
565 spinlock_t sc_pm_lock; 454 spinlock_t sc_pm_lock;
566 struct mutex mutex; 455 struct mutex mutex;
567 456
568 u8 curbssid[ETH_ALEN];
569 u8 bssidmask[ETH_ALEN];
570 u32 intrstatus; 457 u32 intrstatus;
571 u32 sc_flags; /* SC_OP_* */ 458 u32 sc_flags; /* SC_OP_* */
572 u16 curtxpow; 459 u16 curtxpow;
573 u16 curaid;
574 u8 nbcnvifs; 460 u8 nbcnvifs;
575 u16 nvifs; 461 u16 nvifs;
576 u8 tx_chainmask;
577 u8 rx_chainmask;
578 u32 keymax;
579 DECLARE_BITMAP(keymap, ATH_KEYMAX);
580 u8 splitmic;
581 bool ps_enabled; 462 bool ps_enabled;
582 unsigned long ps_usecount; 463 unsigned long ps_usecount;
583 enum ath9k_int imask; 464 enum ath9k_int imask;
584 enum ath9k_ht_extprotspacing ht_extprotspacing;
585 enum ath9k_ht_macmode tx_chan_width;
586 465
587 struct ath_config config; 466 struct ath_config config;
588 struct ath_rx rx; 467 struct ath_rx rx;
@@ -605,14 +484,12 @@ struct ath_softc {
605 484
606 int beacon_interval; 485 int beacon_interval;
607 486
608 struct ath_ani ani;
609#ifdef CONFIG_ATH9K_DEBUG 487#ifdef CONFIG_ATH9K_DEBUG
610 struct ath9k_debug debug; 488 struct ath9k_debug debug;
611#endif 489#endif
612 struct ath_bus_ops *bus_ops;
613 struct ath_beacon_config cur_beacon_conf; 490 struct ath_beacon_config cur_beacon_conf;
614 struct delayed_work tx_complete_work; 491 struct delayed_work tx_complete_work;
615 struct ath_btcoex_info btcoex_info; 492 struct ath_btcoex btcoex;
616}; 493};
617 494
618struct ath_wiphy { 495struct ath_wiphy {
@@ -625,6 +502,7 @@ struct ath_wiphy {
625 ATH_WIPHY_PAUSED, 502 ATH_WIPHY_PAUSED,
626 ATH_WIPHY_SCAN, 503 ATH_WIPHY_SCAN,
627 } state; 504 } state;
505 bool idle;
628 int chan_idx; 506 int chan_idx;
629 int chan_is_ht; 507 int chan_is_ht;
630}; 508};
@@ -634,31 +512,22 @@ int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
634int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc); 512int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
635int ath_cabq_update(struct ath_softc *); 513int ath_cabq_update(struct ath_softc *);
636 514
637static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah) 515static inline void ath_read_cachesize(struct ath_common *common, int *csz)
638{
639 return &ah->ah_sc->common;
640}
641
642static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
643{ 516{
644 return &(ath9k_hw_common(ah)->regulatory); 517 common->bus_ops->read_cachesize(common, csz);
645} 518}
646 519
647static inline void ath_read_cachesize(struct ath_softc *sc, int *csz) 520static inline void ath_bus_cleanup(struct ath_common *common)
648{ 521{
649 sc->bus_ops->read_cachesize(sc, csz); 522 common->bus_ops->cleanup(common);
650}
651
652static inline void ath_bus_cleanup(struct ath_softc *sc)
653{
654 sc->bus_ops->cleanup(sc);
655} 523}
656 524
657extern struct ieee80211_ops ath9k_ops; 525extern struct ieee80211_ops ath9k_ops;
658 526
659irqreturn_t ath_isr(int irq, void *dev); 527irqreturn_t ath_isr(int irq, void *dev);
660void ath_cleanup(struct ath_softc *sc); 528void ath_cleanup(struct ath_softc *sc);
661int ath_init_device(u16 devid, struct ath_softc *sc, u16 subsysid); 529int ath_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
530 const struct ath_bus_ops *bus_ops);
662void ath_detach(struct ath_softc *sc); 531void ath_detach(struct ath_softc *sc);
663const char *ath_mac_bb_name(u32 mac_bb_version); 532const char *ath_mac_bb_name(u32 mac_bb_version);
664const char *ath_rf_name(u16 rf_version); 533const char *ath_rf_name(u16 rf_version);
@@ -668,8 +537,9 @@ void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
668void ath_update_chainmask(struct ath_softc *sc, int is_ht); 537void ath_update_chainmask(struct ath_softc *sc, int is_ht);
669int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, 538int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
670 struct ath9k_channel *hchan); 539 struct ath9k_channel *hchan);
671void ath_radio_enable(struct ath_softc *sc); 540
672void ath_radio_disable(struct ath_softc *sc); 541void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw);
542void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw);
673 543
674#ifdef CONFIG_PCI 544#ifdef CONFIG_PCI
675int ath_pci_init(void); 545int ath_pci_init(void);
@@ -705,9 +575,10 @@ void ath9k_wiphy_pause_all_forced(struct ath_softc *sc,
705bool ath9k_wiphy_scanning(struct ath_softc *sc); 575bool ath9k_wiphy_scanning(struct ath_softc *sc);
706void ath9k_wiphy_work(struct work_struct *work); 576void ath9k_wiphy_work(struct work_struct *work);
707bool ath9k_all_wiphys_idle(struct ath_softc *sc); 577bool ath9k_all_wiphys_idle(struct ath_softc *sc);
578void ath9k_set_wiphy_idle(struct ath_wiphy *aphy, bool idle);
708 579
709void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val); 580void ath_mac80211_stop_queue(struct ath_softc *sc, u16 skb_queue);
710unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset); 581void ath_mac80211_start_queue(struct ath_softc *sc, u16 skb_queue);
711 582
712int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype); 583int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype);
713#endif /* ATH9K_H */ 584#endif /* ATH9K_H */
diff --git a/drivers/net/wireless/ath/ath9k/beacon.c b/drivers/net/wireless/ath/ath9k/beacon.c
index 45c4ea57616b..b10c884f2933 100644
--- a/drivers/net/wireless/ath/ath9k/beacon.c
+++ b/drivers/net/wireless/ath/ath9k/beacon.c
@@ -26,6 +26,7 @@
26static int ath_beaconq_config(struct ath_softc *sc) 26static int ath_beaconq_config(struct ath_softc *sc)
27{ 27{
28 struct ath_hw *ah = sc->sc_ah; 28 struct ath_hw *ah = sc->sc_ah;
29 struct ath_common *common = ath9k_hw_common(ah);
29 struct ath9k_tx_queue_info qi; 30 struct ath9k_tx_queue_info qi;
30 31
31 ath9k_hw_get_txq_props(ah, sc->beacon.beaconq, &qi); 32 ath9k_hw_get_txq_props(ah, sc->beacon.beaconq, &qi);
@@ -42,8 +43,8 @@ static int ath_beaconq_config(struct ath_softc *sc)
42 } 43 }
43 44
44 if (!ath9k_hw_set_txq_props(ah, sc->beacon.beaconq, &qi)) { 45 if (!ath9k_hw_set_txq_props(ah, sc->beacon.beaconq, &qi)) {
45 DPRINTF(sc, ATH_DBG_FATAL, 46 ath_print(common, ATH_DBG_FATAL,
46 "Unable to update h/w beacon queue parameters\n"); 47 "Unable to update h/w beacon queue parameters\n");
47 return 0; 48 return 0;
48 } else { 49 } else {
49 ath9k_hw_resettxqueue(ah, sc->beacon.beaconq); 50 ath9k_hw_resettxqueue(ah, sc->beacon.beaconq);
@@ -61,6 +62,7 @@ static void ath_beacon_setup(struct ath_softc *sc, struct ath_vif *avp,
61{ 62{
62 struct sk_buff *skb = bf->bf_mpdu; 63 struct sk_buff *skb = bf->bf_mpdu;
63 struct ath_hw *ah = sc->sc_ah; 64 struct ath_hw *ah = sc->sc_ah;
65 struct ath_common *common = ath9k_hw_common(ah);
64 struct ath_desc *ds; 66 struct ath_desc *ds;
65 struct ath9k_11n_rate_series series[4]; 67 struct ath9k_11n_rate_series series[4];
66 const struct ath_rate_table *rt; 68 const struct ath_rate_table *rt;
@@ -108,7 +110,7 @@ static void ath_beacon_setup(struct ath_softc *sc, struct ath_vif *avp,
108 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4); 110 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
109 series[0].Tries = 1; 111 series[0].Tries = 1;
110 series[0].Rate = rate; 112 series[0].Rate = rate;
111 series[0].ChSel = sc->tx_chainmask; 113 series[0].ChSel = common->tx_chainmask;
112 series[0].RateFlags = (ctsrate) ? ATH9K_RATESERIES_RTS_CTS : 0; 114 series[0].RateFlags = (ctsrate) ? ATH9K_RATESERIES_RTS_CTS : 0;
113 ath9k_hw_set11n_ratescenario(ah, ds, ds, 0, ctsrate, ctsduration, 115 ath9k_hw_set11n_ratescenario(ah, ds, ds, 0, ctsrate, ctsduration,
114 series, 4, 0); 116 series, 4, 0);
@@ -119,6 +121,7 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw,
119{ 121{
120 struct ath_wiphy *aphy = hw->priv; 122 struct ath_wiphy *aphy = hw->priv;
121 struct ath_softc *sc = aphy->sc; 123 struct ath_softc *sc = aphy->sc;
124 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
122 struct ath_buf *bf; 125 struct ath_buf *bf;
123 struct ath_vif *avp; 126 struct ath_vif *avp;
124 struct sk_buff *skb; 127 struct sk_buff *skb;
@@ -172,7 +175,8 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw,
172 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) { 175 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
173 dev_kfree_skb_any(skb); 176 dev_kfree_skb_any(skb);
174 bf->bf_mpdu = NULL; 177 bf->bf_mpdu = NULL;
175 DPRINTF(sc, ATH_DBG_FATAL, "dma_mapping_error on beaconing\n"); 178 ath_print(common, ATH_DBG_FATAL,
179 "dma_mapping_error on beaconing\n");
176 return NULL; 180 return NULL;
177 } 181 }
178 182
@@ -192,8 +196,8 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw,
192 196
193 if (skb && cabq_depth) { 197 if (skb && cabq_depth) {
194 if (sc->nvifs > 1) { 198 if (sc->nvifs > 1) {
195 DPRINTF(sc, ATH_DBG_BEACON, 199 ath_print(common, ATH_DBG_BEACON,
196 "Flushing previous cabq traffic\n"); 200 "Flushing previous cabq traffic\n");
197 ath_draintxq(sc, cabq, false); 201 ath_draintxq(sc, cabq, false);
198 } 202 }
199 } 203 }
@@ -216,6 +220,7 @@ static void ath_beacon_start_adhoc(struct ath_softc *sc,
216 struct ieee80211_vif *vif) 220 struct ieee80211_vif *vif)
217{ 221{
218 struct ath_hw *ah = sc->sc_ah; 222 struct ath_hw *ah = sc->sc_ah;
223 struct ath_common *common = ath9k_hw_common(ah);
219 struct ath_buf *bf; 224 struct ath_buf *bf;
220 struct ath_vif *avp; 225 struct ath_vif *avp;
221 struct sk_buff *skb; 226 struct sk_buff *skb;
@@ -233,25 +238,14 @@ static void ath_beacon_start_adhoc(struct ath_softc *sc,
233 /* NB: caller is known to have already stopped tx dma */ 238 /* NB: caller is known to have already stopped tx dma */
234 ath9k_hw_puttxbuf(ah, sc->beacon.beaconq, bf->bf_daddr); 239 ath9k_hw_puttxbuf(ah, sc->beacon.beaconq, bf->bf_daddr);
235 ath9k_hw_txstart(ah, sc->beacon.beaconq); 240 ath9k_hw_txstart(ah, sc->beacon.beaconq);
236 DPRINTF(sc, ATH_DBG_BEACON, "TXDP%u = %llx (%p)\n", 241 ath_print(common, ATH_DBG_BEACON, "TXDP%u = %llx (%p)\n",
237 sc->beacon.beaconq, ito64(bf->bf_daddr), bf->bf_desc); 242 sc->beacon.beaconq, ito64(bf->bf_daddr), bf->bf_desc);
238}
239
240int ath_beaconq_setup(struct ath_hw *ah)
241{
242 struct ath9k_tx_queue_info qi;
243
244 memset(&qi, 0, sizeof(qi));
245 qi.tqi_aifs = 1;
246 qi.tqi_cwmin = 0;
247 qi.tqi_cwmax = 0;
248 /* NB: don't enable any interrupts */
249 return ath9k_hw_setuptxqueue(ah, ATH9K_TX_QUEUE_BEACON, &qi);
250} 243}
251 244
252int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif) 245int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
253{ 246{
254 struct ath_softc *sc = aphy->sc; 247 struct ath_softc *sc = aphy->sc;
248 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
255 struct ath_vif *avp; 249 struct ath_vif *avp;
256 struct ath_buf *bf; 250 struct ath_buf *bf;
257 struct sk_buff *skb; 251 struct sk_buff *skb;
@@ -309,7 +303,7 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
309 /* NB: the beacon data buffer must be 32-bit aligned. */ 303 /* NB: the beacon data buffer must be 32-bit aligned. */
310 skb = ieee80211_beacon_get(sc->hw, vif); 304 skb = ieee80211_beacon_get(sc->hw, vif);
311 if (skb == NULL) { 305 if (skb == NULL) {
312 DPRINTF(sc, ATH_DBG_BEACON, "cannot get skb\n"); 306 ath_print(common, ATH_DBG_BEACON, "cannot get skb\n");
313 return -ENOMEM; 307 return -ENOMEM;
314 } 308 }
315 309
@@ -333,9 +327,10 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
333 tsfadjust = intval * avp->av_bslot / ATH_BCBUF; 327 tsfadjust = intval * avp->av_bslot / ATH_BCBUF;
334 avp->tsf_adjust = cpu_to_le64(TU_TO_USEC(tsfadjust)); 328 avp->tsf_adjust = cpu_to_le64(TU_TO_USEC(tsfadjust));
335 329
336 DPRINTF(sc, ATH_DBG_BEACON, 330 ath_print(common, ATH_DBG_BEACON,
337 "stagger beacons, bslot %d intval %u tsfadjust %llu\n", 331 "stagger beacons, bslot %d intval "
338 avp->av_bslot, intval, (unsigned long long)tsfadjust); 332 "%u tsfadjust %llu\n",
333 avp->av_bslot, intval, (unsigned long long)tsfadjust);
339 334
340 ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp = 335 ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp =
341 avp->tsf_adjust; 336 avp->tsf_adjust;
@@ -349,8 +344,8 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
349 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) { 344 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
350 dev_kfree_skb_any(skb); 345 dev_kfree_skb_any(skb);
351 bf->bf_mpdu = NULL; 346 bf->bf_mpdu = NULL;
352 DPRINTF(sc, ATH_DBG_FATAL, 347 ath_print(common, ATH_DBG_FATAL,
353 "dma_mapping_error on beacon alloc\n"); 348 "dma_mapping_error on beacon alloc\n");
354 return -ENOMEM; 349 return -ENOMEM;
355 } 350 }
356 351
@@ -386,6 +381,7 @@ void ath_beacon_tasklet(unsigned long data)
386{ 381{
387 struct ath_softc *sc = (struct ath_softc *)data; 382 struct ath_softc *sc = (struct ath_softc *)data;
388 struct ath_hw *ah = sc->sc_ah; 383 struct ath_hw *ah = sc->sc_ah;
384 struct ath_common *common = ath9k_hw_common(ah);
389 struct ath_buf *bf = NULL; 385 struct ath_buf *bf = NULL;
390 struct ieee80211_vif *vif; 386 struct ieee80211_vif *vif;
391 struct ath_wiphy *aphy; 387 struct ath_wiphy *aphy;
@@ -405,12 +401,12 @@ void ath_beacon_tasklet(unsigned long data)
405 sc->beacon.bmisscnt++; 401 sc->beacon.bmisscnt++;
406 402
407 if (sc->beacon.bmisscnt < BSTUCK_THRESH) { 403 if (sc->beacon.bmisscnt < BSTUCK_THRESH) {
408 DPRINTF(sc, ATH_DBG_BEACON, 404 ath_print(common, ATH_DBG_BEACON,
409 "missed %u consecutive beacons\n", 405 "missed %u consecutive beacons\n",
410 sc->beacon.bmisscnt); 406 sc->beacon.bmisscnt);
411 } else if (sc->beacon.bmisscnt >= BSTUCK_THRESH) { 407 } else if (sc->beacon.bmisscnt >= BSTUCK_THRESH) {
412 DPRINTF(sc, ATH_DBG_BEACON, 408 ath_print(common, ATH_DBG_BEACON,
413 "beacon is officially stuck\n"); 409 "beacon is officially stuck\n");
414 sc->sc_flags |= SC_OP_TSF_RESET; 410 sc->sc_flags |= SC_OP_TSF_RESET;
415 ath_reset(sc, false); 411 ath_reset(sc, false);
416 } 412 }
@@ -419,9 +415,9 @@ void ath_beacon_tasklet(unsigned long data)
419 } 415 }
420 416
421 if (sc->beacon.bmisscnt != 0) { 417 if (sc->beacon.bmisscnt != 0) {
422 DPRINTF(sc, ATH_DBG_BEACON, 418 ath_print(common, ATH_DBG_BEACON,
423 "resume beacon xmit after %u misses\n", 419 "resume beacon xmit after %u misses\n",
424 sc->beacon.bmisscnt); 420 sc->beacon.bmisscnt);
425 sc->beacon.bmisscnt = 0; 421 sc->beacon.bmisscnt = 0;
426 } 422 }
427 423
@@ -447,9 +443,9 @@ void ath_beacon_tasklet(unsigned long data)
447 vif = sc->beacon.bslot[slot]; 443 vif = sc->beacon.bslot[slot];
448 aphy = sc->beacon.bslot_aphy[slot]; 444 aphy = sc->beacon.bslot_aphy[slot];
449 445
450 DPRINTF(sc, ATH_DBG_BEACON, 446 ath_print(common, ATH_DBG_BEACON,
451 "slot %d [tsf %llu tsftu %u intval %u] vif %p\n", 447 "slot %d [tsf %llu tsftu %u intval %u] vif %p\n",
452 slot, tsf, tsftu, intval, vif); 448 slot, tsf, tsftu, intval, vif);
453 449
454 bfaddr = 0; 450 bfaddr = 0;
455 if (vif) { 451 if (vif) {
@@ -490,7 +486,7 @@ void ath_beacon_tasklet(unsigned long data)
490 * are still pending on the queue. 486 * are still pending on the queue.
491 */ 487 */
492 if (!ath9k_hw_stoptxdma(ah, sc->beacon.beaconq)) { 488 if (!ath9k_hw_stoptxdma(ah, sc->beacon.beaconq)) {
493 DPRINTF(sc, ATH_DBG_FATAL, 489 ath_print(common, ATH_DBG_FATAL,
494 "beacon queue %u did not stop?\n", sc->beacon.beaconq); 490 "beacon queue %u did not stop?\n", sc->beacon.beaconq);
495 } 491 }
496 492
@@ -502,6 +498,19 @@ void ath_beacon_tasklet(unsigned long data)
502 } 498 }
503} 499}
504 500
501static void ath9k_beacon_init(struct ath_softc *sc,
502 u32 next_beacon,
503 u32 beacon_period)
504{
505 if (beacon_period & ATH9K_BEACON_RESET_TSF)
506 ath9k_ps_wakeup(sc);
507
508 ath9k_hw_beaconinit(sc->sc_ah, next_beacon, beacon_period);
509
510 if (beacon_period & ATH9K_BEACON_RESET_TSF)
511 ath9k_ps_restore(sc);
512}
513
505/* 514/*
506 * For multi-bss ap support beacons are either staggered evenly over N slots or 515 * For multi-bss ap support beacons are either staggered evenly over N slots or
507 * burst together. For the former arrange for the SWBA to be delivered for each 516 * burst together. For the former arrange for the SWBA to be delivered for each
@@ -534,7 +543,7 @@ static void ath_beacon_config_ap(struct ath_softc *sc,
534 /* Set the computed AP beacon timers */ 543 /* Set the computed AP beacon timers */
535 544
536 ath9k_hw_set_interrupts(sc->sc_ah, 0); 545 ath9k_hw_set_interrupts(sc->sc_ah, 0);
537 ath9k_hw_beaconinit(sc->sc_ah, nexttbtt, intval); 546 ath9k_beacon_init(sc, nexttbtt, intval);
538 sc->beacon.bmisscnt = 0; 547 sc->beacon.bmisscnt = 0;
539 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask); 548 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
540 549
@@ -555,6 +564,7 @@ static void ath_beacon_config_ap(struct ath_softc *sc,
555static void ath_beacon_config_sta(struct ath_softc *sc, 564static void ath_beacon_config_sta(struct ath_softc *sc,
556 struct ath_beacon_config *conf) 565 struct ath_beacon_config *conf)
557{ 566{
567 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
558 struct ath9k_beacon_state bs; 568 struct ath9k_beacon_state bs;
559 int dtimperiod, dtimcount, sleepduration; 569 int dtimperiod, dtimcount, sleepduration;
560 int cfpperiod, cfpcount; 570 int cfpperiod, cfpcount;
@@ -651,11 +661,11 @@ static void ath_beacon_config_sta(struct ath_softc *sc,
651 /* TSF out of range threshold fixed at 1 second */ 661 /* TSF out of range threshold fixed at 1 second */
652 bs.bs_tsfoor_threshold = ATH9K_TSFOOR_THRESHOLD; 662 bs.bs_tsfoor_threshold = ATH9K_TSFOOR_THRESHOLD;
653 663
654 DPRINTF(sc, ATH_DBG_BEACON, "tsf: %llu tsftu: %u\n", tsf, tsftu); 664 ath_print(common, ATH_DBG_BEACON, "tsf: %llu tsftu: %u\n", tsf, tsftu);
655 DPRINTF(sc, ATH_DBG_BEACON, 665 ath_print(common, ATH_DBG_BEACON,
656 "bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n", 666 "bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n",
657 bs.bs_bmissthreshold, bs.bs_sleepduration, 667 bs.bs_bmissthreshold, bs.bs_sleepduration,
658 bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext); 668 bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext);
659 669
660 /* Set the computed STA beacon timers */ 670 /* Set the computed STA beacon timers */
661 671
@@ -669,6 +679,7 @@ static void ath_beacon_config_adhoc(struct ath_softc *sc,
669 struct ath_beacon_config *conf, 679 struct ath_beacon_config *conf,
670 struct ieee80211_vif *vif) 680 struct ieee80211_vif *vif)
671{ 681{
682 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
672 u64 tsf; 683 u64 tsf;
673 u32 tsftu, intval, nexttbtt; 684 u32 tsftu, intval, nexttbtt;
674 685
@@ -689,9 +700,9 @@ static void ath_beacon_config_adhoc(struct ath_softc *sc,
689 nexttbtt += intval; 700 nexttbtt += intval;
690 } while (nexttbtt < tsftu); 701 } while (nexttbtt < tsftu);
691 702
692 DPRINTF(sc, ATH_DBG_BEACON, 703 ath_print(common, ATH_DBG_BEACON,
693 "IBSS nexttbtt %u intval %u (%u)\n", 704 "IBSS nexttbtt %u intval %u (%u)\n",
694 nexttbtt, intval, conf->beacon_interval); 705 nexttbtt, intval, conf->beacon_interval);
695 706
696 /* 707 /*
697 * In IBSS mode enable the beacon timers but only enable SWBA interrupts 708 * In IBSS mode enable the beacon timers but only enable SWBA interrupts
@@ -707,7 +718,7 @@ static void ath_beacon_config_adhoc(struct ath_softc *sc,
707 /* Set the computed ADHOC beacon timers */ 718 /* Set the computed ADHOC beacon timers */
708 719
709 ath9k_hw_set_interrupts(sc->sc_ah, 0); 720 ath9k_hw_set_interrupts(sc->sc_ah, 0);
710 ath9k_hw_beaconinit(sc->sc_ah, nexttbtt, intval); 721 ath9k_beacon_init(sc, nexttbtt, intval);
711 sc->beacon.bmisscnt = 0; 722 sc->beacon.bmisscnt = 0;
712 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask); 723 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
713 724
@@ -719,6 +730,7 @@ static void ath_beacon_config_adhoc(struct ath_softc *sc,
719void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif) 730void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif)
720{ 731{
721 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf; 732 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
733 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
722 enum nl80211_iftype iftype; 734 enum nl80211_iftype iftype;
723 735
724 /* Setup the beacon configuration parameters */ 736 /* Setup the beacon configuration parameters */
@@ -759,8 +771,8 @@ void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif)
759 ath_beacon_config_sta(sc, cur_conf); 771 ath_beacon_config_sta(sc, cur_conf);
760 break; 772 break;
761 default: 773 default:
762 DPRINTF(sc, ATH_DBG_CONFIG, 774 ath_print(common, ATH_DBG_CONFIG,
763 "Unsupported beaconing mode\n"); 775 "Unsupported beaconing mode\n");
764 return; 776 return;
765 } 777 }
766 778
diff --git a/drivers/net/wireless/ath/ath9k/btcoex.c b/drivers/net/wireless/ath/ath9k/btcoex.c
index 55f607b7699e..fb4ac15f3b93 100644
--- a/drivers/net/wireless/ath/ath9k/btcoex.c
+++ b/drivers/net/wireless/ath/ath9k/btcoex.c
@@ -14,10 +14,26 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17#include "ath9k.h" 17#include "hw.h"
18 18
19static const struct ath_btcoex_config ath_bt_config = { 0, true, true, 19enum ath_bt_mode {
20 ATH_BT_COEX_MODE_SLOTTED, true, true, 2, 5, true }; 20 ATH_BT_COEX_MODE_LEGACY, /* legacy rx_clear mode */
21 ATH_BT_COEX_MODE_UNSLOTTED, /* untimed/unslotted mode */
22 ATH_BT_COEX_MODE_SLOTTED, /* slotted mode */
23 ATH_BT_COEX_MODE_DISALBED, /* coexistence disabled */
24};
25
26struct ath_btcoex_config {
27 u8 bt_time_extend;
28 bool bt_txstate_extend;
29 bool bt_txframe_extend;
30 enum ath_bt_mode bt_mode; /* coexistence mode */
31 bool bt_quiet_collision;
32 bool bt_rxclear_polarity; /* invert rx_clear as WLAN_ACTIVE*/
33 u8 bt_priority_time;
34 u8 bt_first_slot_time;
35 bool bt_hold_rx_clear;
36};
21 37
22static const u16 ath_subsysid_tbl[] = { 38static const u16 ath_subsysid_tbl[] = {
23 AR9280_COEX2WIRE_SUBSYSID, 39 AR9280_COEX2WIRE_SUBSYSID,
@@ -29,141 +45,38 @@ static const u16 ath_subsysid_tbl[] = {
29 * Checks the subsystem id of the device to see if it 45 * Checks the subsystem id of the device to see if it
30 * supports btcoex 46 * supports btcoex
31 */ 47 */
32bool ath_btcoex_supported(u16 subsysid) 48bool ath9k_hw_btcoex_supported(struct ath_hw *ah)
33{ 49{
34 int i; 50 int i;
35 51
36 if (!subsysid) 52 if (!ah->hw_version.subsysid)
37 return false; 53 return false;
38 54
39 for (i = 0; i < ARRAY_SIZE(ath_subsysid_tbl); i++) 55 for (i = 0; i < ARRAY_SIZE(ath_subsysid_tbl); i++)
40 if (subsysid == ath_subsysid_tbl[i]) 56 if (ah->hw_version.subsysid == ath_subsysid_tbl[i])
41 return true; 57 return true;
42 58
43 return false; 59 return false;
44} 60}
45 61
46/* 62void ath9k_hw_init_btcoex_hw(struct ath_hw *ah, int qnum)
47 * Detects if there is any priority bt traffic
48 */
49static void ath_detect_bt_priority(struct ath_softc *sc)
50{
51 struct ath_btcoex_info *btinfo = &sc->btcoex_info;
52
53 if (ath9k_hw_gpio_get(sc->sc_ah, btinfo->btpriority_gpio))
54 btinfo->bt_priority_cnt++;
55
56 if (time_after(jiffies, btinfo->bt_priority_time +
57 msecs_to_jiffies(ATH_BT_PRIORITY_TIME_THRESHOLD))) {
58 if (btinfo->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) {
59 DPRINTF(sc, ATH_DBG_BTCOEX,
60 "BT priority traffic detected");
61 sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED;
62 } else {
63 sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
64 }
65
66 btinfo->bt_priority_cnt = 0;
67 btinfo->bt_priority_time = jiffies;
68 }
69}
70
71/*
72 * Configures appropriate weight based on stomp type.
73 */
74static void ath_btcoex_bt_stomp(struct ath_softc *sc,
75 struct ath_btcoex_info *btinfo,
76 int stomp_type)
77{
78
79 switch (stomp_type) {
80 case ATH_BTCOEX_STOMP_ALL:
81 ath_btcoex_set_weight(btinfo, AR_BT_COEX_WGHT,
82 AR_STOMP_ALL_WLAN_WGHT);
83 break;
84 case ATH_BTCOEX_STOMP_LOW:
85 ath_btcoex_set_weight(btinfo, AR_BT_COEX_WGHT,
86 AR_STOMP_LOW_WLAN_WGHT);
87 break;
88 case ATH_BTCOEX_STOMP_NONE:
89 ath_btcoex_set_weight(btinfo, AR_BT_COEX_WGHT,
90 AR_STOMP_NONE_WLAN_WGHT);
91 break;
92 default:
93 DPRINTF(sc, ATH_DBG_BTCOEX, "Invalid Stomptype\n");
94 break;
95 }
96
97 ath9k_hw_btcoex_enable(sc->sc_ah);
98}
99
100/*
101 * This is the master bt coex timer which runs for every
102 * 45ms, bt traffic will be given priority during 55% of this
103 * period while wlan gets remaining 45%
104 */
105
106static void ath_btcoex_period_timer(unsigned long data)
107{
108 struct ath_softc *sc = (struct ath_softc *) data;
109 struct ath_btcoex_info *btinfo = &sc->btcoex_info;
110
111 ath_detect_bt_priority(sc);
112
113 spin_lock_bh(&btinfo->btcoex_lock);
114
115 ath_btcoex_bt_stomp(sc, btinfo, btinfo->bt_stomp_type);
116
117 spin_unlock_bh(&btinfo->btcoex_lock);
118
119 if (btinfo->btcoex_period != btinfo->btcoex_no_stomp) {
120 if (btinfo->hw_timer_enabled)
121 ath_gen_timer_stop(sc->sc_ah, btinfo->no_stomp_timer);
122
123 ath_gen_timer_start(sc->sc_ah,
124 btinfo->no_stomp_timer,
125 (ath9k_hw_gettsf32(sc->sc_ah) +
126 btinfo->btcoex_no_stomp),
127 btinfo->btcoex_no_stomp * 10);
128 btinfo->hw_timer_enabled = true;
129 }
130
131 mod_timer(&btinfo->period_timer, jiffies +
132 msecs_to_jiffies(ATH_BTCOEX_DEF_BT_PERIOD));
133}
134
135/*
136 * Generic tsf based hw timer which configures weight
137 * registers to time slice between wlan and bt traffic
138 */
139
140static void ath_btcoex_no_stomp_timer(void *arg)
141{
142 struct ath_softc *sc = (struct ath_softc *)arg;
143 struct ath_btcoex_info *btinfo = &sc->btcoex_info;
144
145 DPRINTF(sc, ATH_DBG_BTCOEX, "no stomp timer running \n");
146
147 spin_lock_bh(&btinfo->btcoex_lock);
148
149 if (btinfo->bt_stomp_type == ATH_BTCOEX_STOMP_LOW)
150 ath_btcoex_bt_stomp(sc, btinfo, ATH_BTCOEX_STOMP_NONE);
151 else if (btinfo->bt_stomp_type == ATH_BTCOEX_STOMP_ALL)
152 ath_btcoex_bt_stomp(sc, btinfo, ATH_BTCOEX_STOMP_LOW);
153
154 spin_unlock_bh(&btinfo->btcoex_lock);
155}
156
157static int ath_init_btcoex_info(struct ath_hw *hw,
158 struct ath_btcoex_info *btcoex_info)
159{ 63{
64 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
65 const struct ath_btcoex_config ath_bt_config = {
66 .bt_time_extend = 0,
67 .bt_txstate_extend = true,
68 .bt_txframe_extend = true,
69 .bt_mode = ATH_BT_COEX_MODE_SLOTTED,
70 .bt_quiet_collision = true,
71 .bt_rxclear_polarity = true,
72 .bt_priority_time = 2,
73 .bt_first_slot_time = 5,
74 .bt_hold_rx_clear = true,
75 };
160 u32 i; 76 u32 i;
161 int qnum;
162 77
163 qnum = ath_tx_get_qnum(hw->ah_sc, ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE); 78 btcoex_hw->bt_coex_mode =
164 79 (btcoex_hw->bt_coex_mode & AR_BT_QCU_THRESH) |
165 btcoex_info->bt_coex_mode =
166 (btcoex_info->bt_coex_mode & AR_BT_QCU_THRESH) |
167 SM(ath_bt_config.bt_time_extend, AR_BT_TIME_EXTEND) | 80 SM(ath_bt_config.bt_time_extend, AR_BT_TIME_EXTEND) |
168 SM(ath_bt_config.bt_txstate_extend, AR_BT_TXSTATE_EXTEND) | 81 SM(ath_bt_config.bt_txstate_extend, AR_BT_TXSTATE_EXTEND) |
169 SM(ath_bt_config.bt_txframe_extend, AR_BT_TX_FRAME_EXTEND) | 82 SM(ath_bt_config.bt_txframe_extend, AR_BT_TX_FRAME_EXTEND) |
@@ -174,167 +87,141 @@ static int ath_init_btcoex_info(struct ath_hw *hw,
174 SM(ath_bt_config.bt_first_slot_time, AR_BT_FIRST_SLOT_TIME) | 87 SM(ath_bt_config.bt_first_slot_time, AR_BT_FIRST_SLOT_TIME) |
175 SM(qnum, AR_BT_QCU_THRESH); 88 SM(qnum, AR_BT_QCU_THRESH);
176 89
177 btcoex_info->bt_coex_mode2 = 90 btcoex_hw->bt_coex_mode2 =
178 SM(ath_bt_config.bt_hold_rx_clear, AR_BT_HOLD_RX_CLEAR) | 91 SM(ath_bt_config.bt_hold_rx_clear, AR_BT_HOLD_RX_CLEAR) |
179 SM(ATH_BTCOEX_BMISS_THRESH, AR_BT_BCN_MISS_THRESH) | 92 SM(ATH_BTCOEX_BMISS_THRESH, AR_BT_BCN_MISS_THRESH) |
180 AR_BT_DISABLE_BT_ANT; 93 AR_BT_DISABLE_BT_ANT;
181 94
182 btcoex_info->bt_stomp_type = ATH_BTCOEX_STOMP_LOW; 95 for (i = 0; i < 32; i++)
96 ah->hw_gen_timers.gen_timer_index[(debruijn32 << i) >> 27] = i;
97}
98EXPORT_SYMBOL(ath9k_hw_init_btcoex_hw);
183 99
184 btcoex_info->btcoex_period = ATH_BTCOEX_DEF_BT_PERIOD * 1000; 100void ath9k_hw_btcoex_init_2wire(struct ath_hw *ah)
101{
102 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
185 103
186 btcoex_info->btcoex_no_stomp = (100 - ATH_BTCOEX_DEF_DUTY_CYCLE) * 104 /* connect bt_active to baseband */
187 btcoex_info->btcoex_period / 100; 105 REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
106 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
107 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
188 108
189 for (i = 0; i < 32; i++) 109 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
190 hw->hw_gen_timers.gen_timer_index[(debruijn32 << i) >> 27] = i; 110 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
191 111
192 setup_timer(&btcoex_info->period_timer, ath_btcoex_period_timer, 112 /* Set input mux for bt_active to gpio pin */
193 (unsigned long) hw->ah_sc); 113 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
114 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
115 btcoex_hw->btactive_gpio);
194 116
195 btcoex_info->no_stomp_timer = ath_gen_timer_alloc(hw, 117 /* Configure the desired gpio port for input */
196 ath_btcoex_no_stomp_timer, 118 ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btactive_gpio);
197 ath_btcoex_no_stomp_timer, 119}
198 (void *)hw->ah_sc, AR_FIRST_NDP_TIMER); 120EXPORT_SYMBOL(ath9k_hw_btcoex_init_2wire);
121
122void ath9k_hw_btcoex_init_3wire(struct ath_hw *ah)
123{
124 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
199 125
200 if (btcoex_info->no_stomp_timer == NULL) 126 /* btcoex 3-wire */
201 return -ENOMEM; 127 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
128 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB |
129 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB));
202 130
203 spin_lock_init(&btcoex_info->btcoex_lock); 131 /* Set input mux for bt_prority_async and
132 * bt_active_async to GPIO pins */
133 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
134 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
135 btcoex_hw->btactive_gpio);
204 136
205 return 0; 137 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
138 AR_GPIO_INPUT_MUX1_BT_PRIORITY,
139 btcoex_hw->btpriority_gpio);
140
141 /* Configure the desired GPIO ports for input */
142
143 ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btactive_gpio);
144 ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btpriority_gpio);
206} 145}
146EXPORT_SYMBOL(ath9k_hw_btcoex_init_3wire);
207 147
208int ath9k_hw_btcoex_init(struct ath_hw *ah) 148static void ath9k_hw_btcoex_enable_2wire(struct ath_hw *ah)
209{ 149{
210 struct ath_btcoex_info *btcoex_info = &ah->ah_sc->btcoex_info; 150 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
211 int ret = 0;
212
213 if (btcoex_info->btcoex_scheme == ATH_BTCOEX_CFG_2WIRE) {
214 /* connect bt_active to baseband */
215 REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
216 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
217 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
218
219 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
220 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
221
222 /* Set input mux for bt_active to gpio pin */
223 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
224 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
225 btcoex_info->btactive_gpio);
226
227 /* Configure the desired gpio port for input */
228 ath9k_hw_cfg_gpio_input(ah, btcoex_info->btactive_gpio);
229 } else {
230 /* btcoex 3-wire */
231 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
232 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB |
233 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB));
234
235 /* Set input mux for bt_prority_async and
236 * bt_active_async to GPIO pins */
237 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
238 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
239 btcoex_info->btactive_gpio);
240
241 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
242 AR_GPIO_INPUT_MUX1_BT_PRIORITY,
243 btcoex_info->btpriority_gpio);
244
245 /* Configure the desired GPIO ports for input */
246
247 ath9k_hw_cfg_gpio_input(ah, btcoex_info->btactive_gpio);
248 ath9k_hw_cfg_gpio_input(ah, btcoex_info->btpriority_gpio);
249
250 ret = ath_init_btcoex_info(ah, btcoex_info);
251 }
252 151
253 return ret; 152 /* Configure the desired GPIO port for TX_FRAME output */
153 ath9k_hw_cfg_output(ah, btcoex_hw->wlanactive_gpio,
154 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
254} 155}
255 156
256void ath9k_hw_btcoex_enable(struct ath_hw *ah) 157void ath9k_hw_btcoex_set_weight(struct ath_hw *ah,
158 u32 bt_weight,
159 u32 wlan_weight)
257{ 160{
258 struct ath_btcoex_info *btcoex_info = &ah->ah_sc->btcoex_info; 161 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
259
260 if (btcoex_info->btcoex_scheme == ATH_BTCOEX_CFG_2WIRE) {
261 /* Configure the desired GPIO port for TX_FRAME output */
262 ath9k_hw_cfg_output(ah, btcoex_info->wlanactive_gpio,
263 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
264 } else {
265 /*
266 * Program coex mode and weight registers to
267 * enable coex 3-wire
268 */
269 REG_WRITE(ah, AR_BT_COEX_MODE, btcoex_info->bt_coex_mode);
270 REG_WRITE(ah, AR_BT_COEX_WEIGHT, btcoex_info->bt_coex_weights);
271 REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex_info->bt_coex_mode2);
272
273 REG_RMW_FIELD(ah, AR_QUIET1,
274 AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
275 REG_RMW_FIELD(ah, AR_PCU_MISC,
276 AR_PCU_BT_ANT_PREVENT_RX, 0);
277
278 ath9k_hw_cfg_output(ah, btcoex_info->wlanactive_gpio,
279 AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL);
280 }
281 162
282 REG_RMW(ah, AR_GPIO_PDPU, 163 btcoex_hw->bt_coex_weights = SM(bt_weight, AR_BTCOEX_BT_WGHT) |
283 (0x2 << (btcoex_info->btactive_gpio * 2)), 164 SM(wlan_weight, AR_BTCOEX_WL_WGHT);
284 (0x3 << (btcoex_info->btactive_gpio * 2)));
285
286 ah->ah_sc->sc_flags |= SC_OP_BTCOEX_ENABLED;
287} 165}
166EXPORT_SYMBOL(ath9k_hw_btcoex_set_weight);
288 167
289void ath9k_hw_btcoex_disable(struct ath_hw *ah) 168static void ath9k_hw_btcoex_enable_3wire(struct ath_hw *ah)
290{ 169{
291 struct ath_btcoex_info *btcoex_info = &ah->ah_sc->btcoex_info; 170 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
292 171
293 ath9k_hw_set_gpio(ah, btcoex_info->wlanactive_gpio, 0); 172 /*
173 * Program coex mode and weight registers to
174 * enable coex 3-wire
175 */
176 REG_WRITE(ah, AR_BT_COEX_MODE, btcoex_hw->bt_coex_mode);
177 REG_WRITE(ah, AR_BT_COEX_WEIGHT, btcoex_hw->bt_coex_weights);
178 REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex_hw->bt_coex_mode2);
294 179
295 ath9k_hw_cfg_output(ah, btcoex_info->wlanactive_gpio, 180 REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
296 AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 181 REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
297 182
298 if (btcoex_info->btcoex_scheme == ATH_BTCOEX_CFG_3WIRE) { 183 ath9k_hw_cfg_output(ah, btcoex_hw->wlanactive_gpio,
299 REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE); 184 AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL);
300 REG_WRITE(ah, AR_BT_COEX_WEIGHT, 0);
301 REG_WRITE(ah, AR_BT_COEX_MODE2, 0);
302 }
303
304 ah->ah_sc->sc_flags &= ~SC_OP_BTCOEX_ENABLED;
305} 185}
306 186
307/* 187void ath9k_hw_btcoex_enable(struct ath_hw *ah)
308 * Pause btcoex timer and bt duty cycle timer
309 */
310void ath_btcoex_timer_pause(struct ath_softc *sc,
311 struct ath_btcoex_info *btinfo)
312{ 188{
189 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
313 190
314 del_timer_sync(&btinfo->period_timer); 191 switch (btcoex_hw->scheme) {
192 case ATH_BTCOEX_CFG_NONE:
193 break;
194 case ATH_BTCOEX_CFG_2WIRE:
195 ath9k_hw_btcoex_enable_2wire(ah);
196 break;
197 case ATH_BTCOEX_CFG_3WIRE:
198 ath9k_hw_btcoex_enable_3wire(ah);
199 break;
200 }
315 201
316 if (btinfo->hw_timer_enabled) 202 REG_RMW(ah, AR_GPIO_PDPU,
317 ath_gen_timer_stop(sc->sc_ah, btinfo->no_stomp_timer); 203 (0x2 << (btcoex_hw->btactive_gpio * 2)),
204 (0x3 << (btcoex_hw->btactive_gpio * 2)));
318 205
319 btinfo->hw_timer_enabled = false; 206 ah->btcoex_hw.enabled = true;
320} 207}
208EXPORT_SYMBOL(ath9k_hw_btcoex_enable);
321 209
322/* 210void ath9k_hw_btcoex_disable(struct ath_hw *ah)
323 * (Re)start btcoex timers
324 */
325void ath_btcoex_timer_resume(struct ath_softc *sc,
326 struct ath_btcoex_info *btinfo)
327{ 211{
212 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
328 213
329 DPRINTF(sc, ATH_DBG_BTCOEX, "Starting btcoex timers"); 214 ath9k_hw_set_gpio(ah, btcoex_hw->wlanactive_gpio, 0);
330 215
331 /* make sure duty cycle timer is also stopped when resuming */ 216 ath9k_hw_cfg_output(ah, btcoex_hw->wlanactive_gpio,
332 if (btinfo->hw_timer_enabled) 217 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
333 ath_gen_timer_stop(sc->sc_ah, btinfo->no_stomp_timer);
334 218
335 btinfo->bt_priority_cnt = 0; 219 if (btcoex_hw->scheme == ATH_BTCOEX_CFG_3WIRE) {
336 btinfo->bt_priority_time = jiffies; 220 REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE);
337 sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED; 221 REG_WRITE(ah, AR_BT_COEX_WEIGHT, 0);
222 REG_WRITE(ah, AR_BT_COEX_MODE2, 0);
223 }
338 224
339 mod_timer(&btinfo->period_timer, jiffies); 225 ah->btcoex_hw.enabled = false;
340} 226}
227EXPORT_SYMBOL(ath9k_hw_btcoex_disable);
diff --git a/drivers/net/wireless/ath/ath9k/btcoex.h b/drivers/net/wireless/ath/ath9k/btcoex.h
index 297b027fd3c3..1ba31a73317c 100644
--- a/drivers/net/wireless/ath/ath9k/btcoex.h
+++ b/drivers/net/wireless/ath/ath9k/btcoex.h
@@ -17,6 +17,8 @@
17#ifndef BTCOEX_H 17#ifndef BTCOEX_H
18#define BTCOEX_H 18#define BTCOEX_H
19 19
20#include "hw.h"
21
20#define ATH_WLANACTIVE_GPIO 5 22#define ATH_WLANACTIVE_GPIO 5
21#define ATH_BTACTIVE_GPIO 6 23#define ATH_BTACTIVE_GPIO 6
22#define ATH_BTPRIORITY_GPIO 7 24#define ATH_BTPRIORITY_GPIO 7
@@ -34,67 +36,25 @@ enum ath_btcoex_scheme {
34 ATH_BTCOEX_CFG_3WIRE, 36 ATH_BTCOEX_CFG_3WIRE,
35}; 37};
36 38
37enum ath_stomp_type { 39struct ath_btcoex_hw {
38 ATH_BTCOEX_NO_STOMP, 40 enum ath_btcoex_scheme scheme;
39 ATH_BTCOEX_STOMP_ALL, 41 bool enabled;
40 ATH_BTCOEX_STOMP_LOW,
41 ATH_BTCOEX_STOMP_NONE
42};
43
44enum ath_bt_mode {
45 ATH_BT_COEX_MODE_LEGACY, /* legacy rx_clear mode */
46 ATH_BT_COEX_MODE_UNSLOTTED, /* untimed/unslotted mode */
47 ATH_BT_COEX_MODE_SLOTTED, /* slotted mode */
48 ATH_BT_COEX_MODE_DISALBED, /* coexistence disabled */
49};
50
51struct ath_btcoex_config {
52 u8 bt_time_extend;
53 bool bt_txstate_extend;
54 bool bt_txframe_extend;
55 enum ath_bt_mode bt_mode; /* coexistence mode */
56 bool bt_quiet_collision;
57 bool bt_rxclear_polarity; /* invert rx_clear as WLAN_ACTIVE*/
58 u8 bt_priority_time;
59 u8 bt_first_slot_time;
60 bool bt_hold_rx_clear;
61};
62
63struct ath_btcoex_info {
64 enum ath_btcoex_scheme btcoex_scheme;
65 u8 wlanactive_gpio; 42 u8 wlanactive_gpio;
66 u8 btactive_gpio; 43 u8 btactive_gpio;
67 u8 btpriority_gpio; 44 u8 btpriority_gpio;
68 u8 bt_duty_cycle; /* BT duty cycle in percentage */
69 int bt_stomp_type; /* Types of BT stomping */
70 u32 bt_coex_mode; /* Register setting for AR_BT_COEX_MODE */ 45 u32 bt_coex_mode; /* Register setting for AR_BT_COEX_MODE */
71 u32 bt_coex_weights; /* Register setting for AR_BT_COEX_WEIGHT */ 46 u32 bt_coex_weights; /* Register setting for AR_BT_COEX_WEIGHT */
72 u32 bt_coex_mode2; /* Register setting for AR_BT_COEX_MODE2 */ 47 u32 bt_coex_mode2; /* Register setting for AR_BT_COEX_MODE2 */
73 u32 btcoex_no_stomp; /* in usec */
74 u32 btcoex_period; /* in usec */
75 u32 bt_priority_cnt;
76 unsigned long bt_priority_time;
77 bool hw_timer_enabled;
78 spinlock_t btcoex_lock;
79 struct timer_list period_timer; /* Timer for BT period */
80 struct ath_gen_timer *no_stomp_timer; /*Timer for no BT stomping*/
81}; 48};
82 49
83bool ath_btcoex_supported(u16 subsysid); 50bool ath9k_hw_btcoex_supported(struct ath_hw *ah);
84int ath9k_hw_btcoex_init(struct ath_hw *ah); 51void ath9k_hw_btcoex_init_2wire(struct ath_hw *ah);
52void ath9k_hw_btcoex_init_3wire(struct ath_hw *ah);
53void ath9k_hw_init_btcoex_hw(struct ath_hw *ah, int qnum);
54void ath9k_hw_btcoex_set_weight(struct ath_hw *ah,
55 u32 bt_weight,
56 u32 wlan_weight);
85void ath9k_hw_btcoex_enable(struct ath_hw *ah); 57void ath9k_hw_btcoex_enable(struct ath_hw *ah);
86void ath9k_hw_btcoex_disable(struct ath_hw *ah); 58void ath9k_hw_btcoex_disable(struct ath_hw *ah);
87void ath_btcoex_timer_resume(struct ath_softc *sc,
88 struct ath_btcoex_info *btinfo);
89void ath_btcoex_timer_pause(struct ath_softc *sc,
90 struct ath_btcoex_info *btinfo);
91
92static inline void ath_btcoex_set_weight(struct ath_btcoex_info *btcoex_info,
93 u32 bt_weight,
94 u32 wlan_weight)
95{
96 btcoex_info->bt_coex_weights = SM(bt_weight, AR_BTCOEX_BT_WGHT) |
97 SM(wlan_weight, AR_BTCOEX_WL_WGHT);
98}
99 59
100#endif 60#endif
diff --git a/drivers/net/wireless/ath/ath9k/calib.c b/drivers/net/wireless/ath/ath9k/calib.c
index 0ad6d0b76e9e..238a5744d8e9 100644
--- a/drivers/net/wireless/ath/ath9k/calib.c
+++ b/drivers/net/wireless/ath/ath9k/calib.c
@@ -14,7 +14,7 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17#include "ath9k.h" 17#include "hw.h"
18 18
19/* We can tune this as we go by monitoring really low values */ 19/* We can tune this as we go by monitoring really low values */
20#define ATH9K_NF_TOO_LOW -60 20#define ATH9K_NF_TOO_LOW -60
@@ -26,11 +26,11 @@
26static bool ath9k_hw_nf_in_range(struct ath_hw *ah, s16 nf) 26static bool ath9k_hw_nf_in_range(struct ath_hw *ah, s16 nf)
27{ 27{
28 if (nf > ATH9K_NF_TOO_LOW) { 28 if (nf > ATH9K_NF_TOO_LOW) {
29 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 29 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
30 "noise floor value detected (%d) is " 30 "noise floor value detected (%d) is "
31 "lower than what we think is a " 31 "lower than what we think is a "
32 "reasonable value (%d)\n", 32 "reasonable value (%d)\n",
33 nf, ATH9K_NF_TOO_LOW); 33 nf, ATH9K_NF_TOO_LOW);
34 return false; 34 return false;
35 } 35 }
36 return true; 36 return true;
@@ -89,6 +89,7 @@ static void ath9k_hw_update_nfcal_hist_buffer(struct ath9k_nfcal_hist *h,
89static void ath9k_hw_do_getnf(struct ath_hw *ah, 89static void ath9k_hw_do_getnf(struct ath_hw *ah,
90 int16_t nfarray[NUM_NF_READINGS]) 90 int16_t nfarray[NUM_NF_READINGS])
91{ 91{
92 struct ath_common *common = ath9k_hw_common(ah);
92 int16_t nf; 93 int16_t nf;
93 94
94 if (AR_SREV_9280_10_OR_LATER(ah)) 95 if (AR_SREV_9280_10_OR_LATER(ah))
@@ -98,8 +99,8 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah,
98 99
99 if (nf & 0x100) 100 if (nf & 0x100)
100 nf = 0 - ((nf ^ 0x1ff) + 1); 101 nf = 0 - ((nf ^ 0x1ff) + 1);
101 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 102 ath_print(common, ATH_DBG_CALIBRATE,
102 "NF calibrated [ctl] [chain 0] is %d\n", nf); 103 "NF calibrated [ctl] [chain 0] is %d\n", nf);
103 nfarray[0] = nf; 104 nfarray[0] = nf;
104 105
105 if (!AR_SREV_9285(ah)) { 106 if (!AR_SREV_9285(ah)) {
@@ -112,8 +113,8 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah,
112 113
113 if (nf & 0x100) 114 if (nf & 0x100)
114 nf = 0 - ((nf ^ 0x1ff) + 1); 115 nf = 0 - ((nf ^ 0x1ff) + 1);
115 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 116 ath_print(common, ATH_DBG_CALIBRATE,
116 "NF calibrated [ctl] [chain 1] is %d\n", nf); 117 "NF calibrated [ctl] [chain 1] is %d\n", nf);
117 nfarray[1] = nf; 118 nfarray[1] = nf;
118 119
119 if (!AR_SREV_9280(ah) && !AR_SREV_9287(ah)) { 120 if (!AR_SREV_9280(ah) && !AR_SREV_9287(ah)) {
@@ -121,8 +122,8 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah,
121 AR_PHY_CH2_MINCCA_PWR); 122 AR_PHY_CH2_MINCCA_PWR);
122 if (nf & 0x100) 123 if (nf & 0x100)
123 nf = 0 - ((nf ^ 0x1ff) + 1); 124 nf = 0 - ((nf ^ 0x1ff) + 1);
124 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 125 ath_print(common, ATH_DBG_CALIBRATE,
125 "NF calibrated [ctl] [chain 2] is %d\n", nf); 126 "NF calibrated [ctl] [chain 2] is %d\n", nf);
126 nfarray[2] = nf; 127 nfarray[2] = nf;
127 } 128 }
128 } 129 }
@@ -136,8 +137,8 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah,
136 137
137 if (nf & 0x100) 138 if (nf & 0x100)
138 nf = 0 - ((nf ^ 0x1ff) + 1); 139 nf = 0 - ((nf ^ 0x1ff) + 1);
139 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 140 ath_print(common, ATH_DBG_CALIBRATE,
140 "NF calibrated [ext] [chain 0] is %d\n", nf); 141 "NF calibrated [ext] [chain 0] is %d\n", nf);
141 nfarray[3] = nf; 142 nfarray[3] = nf;
142 143
143 if (!AR_SREV_9285(ah)) { 144 if (!AR_SREV_9285(ah)) {
@@ -150,8 +151,8 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah,
150 151
151 if (nf & 0x100) 152 if (nf & 0x100)
152 nf = 0 - ((nf ^ 0x1ff) + 1); 153 nf = 0 - ((nf ^ 0x1ff) + 1);
153 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 154 ath_print(common, ATH_DBG_CALIBRATE,
154 "NF calibrated [ext] [chain 1] is %d\n", nf); 155 "NF calibrated [ext] [chain 1] is %d\n", nf);
155 nfarray[4] = nf; 156 nfarray[4] = nf;
156 157
157 if (!AR_SREV_9280(ah) && !AR_SREV_9287(ah)) { 158 if (!AR_SREV_9280(ah) && !AR_SREV_9287(ah)) {
@@ -159,8 +160,8 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah,
159 AR_PHY_CH2_EXT_MINCCA_PWR); 160 AR_PHY_CH2_EXT_MINCCA_PWR);
160 if (nf & 0x100) 161 if (nf & 0x100)
161 nf = 0 - ((nf ^ 0x1ff) + 1); 162 nf = 0 - ((nf ^ 0x1ff) + 1);
162 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 163 ath_print(common, ATH_DBG_CALIBRATE,
163 "NF calibrated [ext] [chain 2] is %d\n", nf); 164 "NF calibrated [ext] [chain 2] is %d\n", nf);
164 nfarray[5] = nf; 165 nfarray[5] = nf;
165 } 166 }
166 } 167 }
@@ -188,6 +189,8 @@ static bool getNoiseFloorThresh(struct ath_hw *ah,
188static void ath9k_hw_setup_calibration(struct ath_hw *ah, 189static void ath9k_hw_setup_calibration(struct ath_hw *ah,
189 struct ath9k_cal_list *currCal) 190 struct ath9k_cal_list *currCal)
190{ 191{
192 struct ath_common *common = ath9k_hw_common(ah);
193
191 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0), 194 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
192 AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX, 195 AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
193 currCal->calData->calCountMax); 196 currCal->calData->calCountMax);
@@ -195,23 +198,23 @@ static void ath9k_hw_setup_calibration(struct ath_hw *ah,
195 switch (currCal->calData->calType) { 198 switch (currCal->calData->calType) {
196 case IQ_MISMATCH_CAL: 199 case IQ_MISMATCH_CAL:
197 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); 200 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
198 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 201 ath_print(common, ATH_DBG_CALIBRATE,
199 "starting IQ Mismatch Calibration\n"); 202 "starting IQ Mismatch Calibration\n");
200 break; 203 break;
201 case ADC_GAIN_CAL: 204 case ADC_GAIN_CAL:
202 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN); 205 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
203 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 206 ath_print(common, ATH_DBG_CALIBRATE,
204 "starting ADC Gain Calibration\n"); 207 "starting ADC Gain Calibration\n");
205 break; 208 break;
206 case ADC_DC_CAL: 209 case ADC_DC_CAL:
207 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER); 210 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
208 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 211 ath_print(common, ATH_DBG_CALIBRATE,
209 "starting ADC DC Calibration\n"); 212 "starting ADC DC Calibration\n");
210 break; 213 break;
211 case ADC_DC_INIT_CAL: 214 case ADC_DC_INIT_CAL:
212 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT); 215 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
213 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 216 ath_print(common, ATH_DBG_CALIBRATE,
214 "starting Init ADC DC Calibration\n"); 217 "starting Init ADC DC Calibration\n");
215 break; 218 break;
216 } 219 }
217 220
@@ -278,7 +281,7 @@ static bool ath9k_hw_per_calibration(struct ath_hw *ah,
278static bool ath9k_hw_iscal_supported(struct ath_hw *ah, 281static bool ath9k_hw_iscal_supported(struct ath_hw *ah,
279 enum ath9k_cal_types calType) 282 enum ath9k_cal_types calType)
280{ 283{
281 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; 284 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
282 285
283 switch (calType & ah->supp_cals) { 286 switch (calType & ah->supp_cals) {
284 case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */ 287 case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */
@@ -304,11 +307,11 @@ static void ath9k_hw_iqcal_collect(struct ath_hw *ah)
304 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); 307 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
305 ah->totalIqCorrMeas[i] += 308 ah->totalIqCorrMeas[i] +=
306 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); 309 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
307 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 310 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
308 "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n", 311 "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
309 ah->cal_samples, i, ah->totalPowerMeasI[i], 312 ah->cal_samples, i, ah->totalPowerMeasI[i],
310 ah->totalPowerMeasQ[i], 313 ah->totalPowerMeasQ[i],
311 ah->totalIqCorrMeas[i]); 314 ah->totalIqCorrMeas[i]);
312 } 315 }
313} 316}
314 317
@@ -326,14 +329,14 @@ static void ath9k_hw_adc_gaincal_collect(struct ath_hw *ah)
326 ah->totalAdcQEvenPhase[i] += 329 ah->totalAdcQEvenPhase[i] +=
327 REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); 330 REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
328 331
329 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 332 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
330 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; " 333 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
331 "oddq=0x%08x; evenq=0x%08x;\n", 334 "oddq=0x%08x; evenq=0x%08x;\n",
332 ah->cal_samples, i, 335 ah->cal_samples, i,
333 ah->totalAdcIOddPhase[i], 336 ah->totalAdcIOddPhase[i],
334 ah->totalAdcIEvenPhase[i], 337 ah->totalAdcIEvenPhase[i],
335 ah->totalAdcQOddPhase[i], 338 ah->totalAdcQOddPhase[i],
336 ah->totalAdcQEvenPhase[i]); 339 ah->totalAdcQEvenPhase[i]);
337 } 340 }
338} 341}
339 342
@@ -351,19 +354,20 @@ static void ath9k_hw_adc_dccal_collect(struct ath_hw *ah)
351 ah->totalAdcDcOffsetQEvenPhase[i] += 354 ah->totalAdcDcOffsetQEvenPhase[i] +=
352 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); 355 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
353 356
354 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 357 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
355 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; " 358 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
356 "oddq=0x%08x; evenq=0x%08x;\n", 359 "oddq=0x%08x; evenq=0x%08x;\n",
357 ah->cal_samples, i, 360 ah->cal_samples, i,
358 ah->totalAdcDcOffsetIOddPhase[i], 361 ah->totalAdcDcOffsetIOddPhase[i],
359 ah->totalAdcDcOffsetIEvenPhase[i], 362 ah->totalAdcDcOffsetIEvenPhase[i],
360 ah->totalAdcDcOffsetQOddPhase[i], 363 ah->totalAdcDcOffsetQOddPhase[i],
361 ah->totalAdcDcOffsetQEvenPhase[i]); 364 ah->totalAdcDcOffsetQEvenPhase[i]);
362 } 365 }
363} 366}
364 367
365static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) 368static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
366{ 369{
370 struct ath_common *common = ath9k_hw_common(ah);
367 u32 powerMeasQ, powerMeasI, iqCorrMeas; 371 u32 powerMeasQ, powerMeasI, iqCorrMeas;
368 u32 qCoffDenom, iCoffDenom; 372 u32 qCoffDenom, iCoffDenom;
369 int32_t qCoff, iCoff; 373 int32_t qCoff, iCoff;
@@ -374,13 +378,13 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
374 powerMeasQ = ah->totalPowerMeasQ[i]; 378 powerMeasQ = ah->totalPowerMeasQ[i];
375 iqCorrMeas = ah->totalIqCorrMeas[i]; 379 iqCorrMeas = ah->totalIqCorrMeas[i];
376 380
377 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 381 ath_print(common, ATH_DBG_CALIBRATE,
378 "Starting IQ Cal and Correction for Chain %d\n", 382 "Starting IQ Cal and Correction for Chain %d\n",
379 i); 383 i);
380 384
381 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 385 ath_print(common, ATH_DBG_CALIBRATE,
382 "Orignal: Chn %diq_corr_meas = 0x%08x\n", 386 "Orignal: Chn %diq_corr_meas = 0x%08x\n",
383 i, ah->totalIqCorrMeas[i]); 387 i, ah->totalIqCorrMeas[i]);
384 388
385 iqCorrNeg = 0; 389 iqCorrNeg = 0;
386 390
@@ -389,27 +393,28 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
389 iqCorrNeg = 1; 393 iqCorrNeg = 1;
390 } 394 }
391 395
392 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 396 ath_print(common, ATH_DBG_CALIBRATE,
393 "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI); 397 "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
394 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 398 ath_print(common, ATH_DBG_CALIBRATE,
395 "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ); 399 "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
396 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n", 400 ath_print(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
397 iqCorrNeg); 401 iqCorrNeg);
398 402
399 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128; 403 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
400 qCoffDenom = powerMeasQ / 64; 404 qCoffDenom = powerMeasQ / 64;
401 405
402 if (powerMeasQ != 0) { 406 if ((powerMeasQ != 0) && (iCoffDenom != 0) &&
407 (qCoffDenom != 0)) {
403 iCoff = iqCorrMeas / iCoffDenom; 408 iCoff = iqCorrMeas / iCoffDenom;
404 qCoff = powerMeasI / qCoffDenom - 64; 409 qCoff = powerMeasI / qCoffDenom - 64;
405 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 410 ath_print(common, ATH_DBG_CALIBRATE,
406 "Chn %d iCoff = 0x%08x\n", i, iCoff); 411 "Chn %d iCoff = 0x%08x\n", i, iCoff);
407 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 412 ath_print(common, ATH_DBG_CALIBRATE,
408 "Chn %d qCoff = 0x%08x\n", i, qCoff); 413 "Chn %d qCoff = 0x%08x\n", i, qCoff);
409 414
410 iCoff = iCoff & 0x3f; 415 iCoff = iCoff & 0x3f;
411 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 416 ath_print(common, ATH_DBG_CALIBRATE,
412 "New: Chn %d iCoff = 0x%08x\n", i, iCoff); 417 "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
413 if (iqCorrNeg == 0x0) 418 if (iqCorrNeg == 0x0)
414 iCoff = 0x40 - iCoff; 419 iCoff = 0x40 - iCoff;
415 420
@@ -418,9 +423,9 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
418 else if (qCoff <= -16) 423 else if (qCoff <= -16)
419 qCoff = 16; 424 qCoff = 16;
420 425
421 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 426 ath_print(common, ATH_DBG_CALIBRATE,
422 "Chn %d : iCoff = 0x%x qCoff = 0x%x\n", 427 "Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
423 i, iCoff, qCoff); 428 i, iCoff, qCoff);
424 429
425 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i), 430 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
426 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, 431 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
@@ -428,9 +433,9 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
428 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i), 433 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
429 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, 434 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
430 qCoff); 435 qCoff);
431 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 436 ath_print(common, ATH_DBG_CALIBRATE,
432 "IQ Cal and Correction done for Chain %d\n", 437 "IQ Cal and Correction done for Chain %d\n",
433 i); 438 i);
434 } 439 }
435 } 440 }
436 441
@@ -440,6 +445,7 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
440 445
441static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains) 446static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
442{ 447{
448 struct ath_common *common = ath9k_hw_common(ah);
443 u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset, qEvenMeasOffset; 449 u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset, qEvenMeasOffset;
444 u32 qGainMismatch, iGainMismatch, val, i; 450 u32 qGainMismatch, iGainMismatch, val, i;
445 451
@@ -449,21 +455,21 @@ static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
449 qOddMeasOffset = ah->totalAdcQOddPhase[i]; 455 qOddMeasOffset = ah->totalAdcQOddPhase[i];
450 qEvenMeasOffset = ah->totalAdcQEvenPhase[i]; 456 qEvenMeasOffset = ah->totalAdcQEvenPhase[i];
451 457
452 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 458 ath_print(common, ATH_DBG_CALIBRATE,
453 "Starting ADC Gain Cal for Chain %d\n", i); 459 "Starting ADC Gain Cal for Chain %d\n", i);
454 460
455 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 461 ath_print(common, ATH_DBG_CALIBRATE,
456 "Chn %d pwr_meas_odd_i = 0x%08x\n", i, 462 "Chn %d pwr_meas_odd_i = 0x%08x\n", i,
457 iOddMeasOffset); 463 iOddMeasOffset);
458 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 464 ath_print(common, ATH_DBG_CALIBRATE,
459 "Chn %d pwr_meas_even_i = 0x%08x\n", i, 465 "Chn %d pwr_meas_even_i = 0x%08x\n", i,
460 iEvenMeasOffset); 466 iEvenMeasOffset);
461 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 467 ath_print(common, ATH_DBG_CALIBRATE,
462 "Chn %d pwr_meas_odd_q = 0x%08x\n", i, 468 "Chn %d pwr_meas_odd_q = 0x%08x\n", i,
463 qOddMeasOffset); 469 qOddMeasOffset);
464 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 470 ath_print(common, ATH_DBG_CALIBRATE,
465 "Chn %d pwr_meas_even_q = 0x%08x\n", i, 471 "Chn %d pwr_meas_even_q = 0x%08x\n", i,
466 qEvenMeasOffset); 472 qEvenMeasOffset);
467 473
468 if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) { 474 if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) {
469 iGainMismatch = 475 iGainMismatch =
@@ -473,20 +479,20 @@ static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
473 ((qOddMeasOffset * 32) / 479 ((qOddMeasOffset * 32) /
474 qEvenMeasOffset) & 0x3f; 480 qEvenMeasOffset) & 0x3f;
475 481
476 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 482 ath_print(common, ATH_DBG_CALIBRATE,
477 "Chn %d gain_mismatch_i = 0x%08x\n", i, 483 "Chn %d gain_mismatch_i = 0x%08x\n", i,
478 iGainMismatch); 484 iGainMismatch);
479 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 485 ath_print(common, ATH_DBG_CALIBRATE,
480 "Chn %d gain_mismatch_q = 0x%08x\n", i, 486 "Chn %d gain_mismatch_q = 0x%08x\n", i,
481 qGainMismatch); 487 qGainMismatch);
482 488
483 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i)); 489 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
484 val &= 0xfffff000; 490 val &= 0xfffff000;
485 val |= (qGainMismatch) | (iGainMismatch << 6); 491 val |= (qGainMismatch) | (iGainMismatch << 6);
486 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); 492 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
487 493
488 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 494 ath_print(common, ATH_DBG_CALIBRATE,
489 "ADC Gain Cal done for Chain %d\n", i); 495 "ADC Gain Cal done for Chain %d\n", i);
490 } 496 }
491 } 497 }
492 498
@@ -497,6 +503,7 @@ static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
497 503
498static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains) 504static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
499{ 505{
506 struct ath_common *common = ath9k_hw_common(ah);
500 u32 iOddMeasOffset, iEvenMeasOffset, val, i; 507 u32 iOddMeasOffset, iEvenMeasOffset, val, i;
501 int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch; 508 int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch;
502 const struct ath9k_percal_data *calData = 509 const struct ath9k_percal_data *calData =
@@ -510,41 +517,41 @@ static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
510 qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i]; 517 qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i];
511 qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i]; 518 qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i];
512 519
513 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 520 ath_print(common, ATH_DBG_CALIBRATE,
514 "Starting ADC DC Offset Cal for Chain %d\n", i); 521 "Starting ADC DC Offset Cal for Chain %d\n", i);
515 522
516 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 523 ath_print(common, ATH_DBG_CALIBRATE,
517 "Chn %d pwr_meas_odd_i = %d\n", i, 524 "Chn %d pwr_meas_odd_i = %d\n", i,
518 iOddMeasOffset); 525 iOddMeasOffset);
519 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 526 ath_print(common, ATH_DBG_CALIBRATE,
520 "Chn %d pwr_meas_even_i = %d\n", i, 527 "Chn %d pwr_meas_even_i = %d\n", i,
521 iEvenMeasOffset); 528 iEvenMeasOffset);
522 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 529 ath_print(common, ATH_DBG_CALIBRATE,
523 "Chn %d pwr_meas_odd_q = %d\n", i, 530 "Chn %d pwr_meas_odd_q = %d\n", i,
524 qOddMeasOffset); 531 qOddMeasOffset);
525 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 532 ath_print(common, ATH_DBG_CALIBRATE,
526 "Chn %d pwr_meas_even_q = %d\n", i, 533 "Chn %d pwr_meas_even_q = %d\n", i,
527 qEvenMeasOffset); 534 qEvenMeasOffset);
528 535
529 iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) / 536 iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
530 numSamples) & 0x1ff; 537 numSamples) & 0x1ff;
531 qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) / 538 qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
532 numSamples) & 0x1ff; 539 numSamples) & 0x1ff;
533 540
534 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 541 ath_print(common, ATH_DBG_CALIBRATE,
535 "Chn %d dc_offset_mismatch_i = 0x%08x\n", i, 542 "Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
536 iDcMismatch); 543 iDcMismatch);
537 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 544 ath_print(common, ATH_DBG_CALIBRATE,
538 "Chn %d dc_offset_mismatch_q = 0x%08x\n", i, 545 "Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
539 qDcMismatch); 546 qDcMismatch);
540 547
541 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i)); 548 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
542 val &= 0xc0000fff; 549 val &= 0xc0000fff;
543 val |= (qDcMismatch << 12) | (iDcMismatch << 21); 550 val |= (qDcMismatch << 12) | (iDcMismatch << 21);
544 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); 551 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
545 552
546 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 553 ath_print(common, ATH_DBG_CALIBRATE,
547 "ADC DC Offset Cal done for Chain %d\n", i); 554 "ADC DC Offset Cal done for Chain %d\n", i);
548 } 555 }
549 556
550 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0), 557 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
@@ -555,7 +562,8 @@ static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
555/* This is done for the currently configured channel */ 562/* This is done for the currently configured channel */
556bool ath9k_hw_reset_calvalid(struct ath_hw *ah) 563bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
557{ 564{
558 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; 565 struct ath_common *common = ath9k_hw_common(ah);
566 struct ieee80211_conf *conf = &common->hw->conf;
559 struct ath9k_cal_list *currCal = ah->cal_list_curr; 567 struct ath9k_cal_list *currCal = ah->cal_list_curr;
560 568
561 if (!ah->curchan) 569 if (!ah->curchan)
@@ -568,24 +576,25 @@ bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
568 return true; 576 return true;
569 577
570 if (currCal->calState != CAL_DONE) { 578 if (currCal->calState != CAL_DONE) {
571 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 579 ath_print(common, ATH_DBG_CALIBRATE,
572 "Calibration state incorrect, %d\n", 580 "Calibration state incorrect, %d\n",
573 currCal->calState); 581 currCal->calState);
574 return true; 582 return true;
575 } 583 }
576 584
577 if (!ath9k_hw_iscal_supported(ah, currCal->calData->calType)) 585 if (!ath9k_hw_iscal_supported(ah, currCal->calData->calType))
578 return true; 586 return true;
579 587
580 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 588 ath_print(common, ATH_DBG_CALIBRATE,
581 "Resetting Cal %d state for channel %u\n", 589 "Resetting Cal %d state for channel %u\n",
582 currCal->calData->calType, conf->channel->center_freq); 590 currCal->calData->calType, conf->channel->center_freq);
583 591
584 ah->curchan->CalValid &= ~currCal->calData->calType; 592 ah->curchan->CalValid &= ~currCal->calData->calType;
585 currCal->calState = CAL_WAITING; 593 currCal->calState = CAL_WAITING;
586 594
587 return false; 595 return false;
588} 596}
597EXPORT_SYMBOL(ath9k_hw_reset_calvalid);
589 598
590void ath9k_hw_start_nfcal(struct ath_hw *ah) 599void ath9k_hw_start_nfcal(struct ath_hw *ah)
591{ 600{
@@ -645,11 +654,11 @@ void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
645 AR_PHY_AGC_CONTROL_NO_UPDATE_NF); 654 AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
646 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); 655 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
647 656
648 for (j = 0; j < 1000; j++) { 657 for (j = 0; j < 5; j++) {
649 if ((REG_READ(ah, AR_PHY_AGC_CONTROL) & 658 if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
650 AR_PHY_AGC_CONTROL_NF) == 0) 659 AR_PHY_AGC_CONTROL_NF) == 0)
651 break; 660 break;
652 udelay(10); 661 udelay(50);
653 } 662 }
654 663
655 for (i = 0; i < NUM_NF_READINGS; i++) { 664 for (i = 0; i < NUM_NF_READINGS; i++) {
@@ -665,6 +674,7 @@ void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
665int16_t ath9k_hw_getnf(struct ath_hw *ah, 674int16_t ath9k_hw_getnf(struct ath_hw *ah,
666 struct ath9k_channel *chan) 675 struct ath9k_channel *chan)
667{ 676{
677 struct ath_common *common = ath9k_hw_common(ah);
668 int16_t nf, nfThresh; 678 int16_t nf, nfThresh;
669 int16_t nfarray[NUM_NF_READINGS] = { 0 }; 679 int16_t nfarray[NUM_NF_READINGS] = { 0 };
670 struct ath9k_nfcal_hist *h; 680 struct ath9k_nfcal_hist *h;
@@ -672,8 +682,8 @@ int16_t ath9k_hw_getnf(struct ath_hw *ah,
672 682
673 chan->channelFlags &= (~CHANNEL_CW_INT); 683 chan->channelFlags &= (~CHANNEL_CW_INT);
674 if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) { 684 if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
675 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 685 ath_print(common, ATH_DBG_CALIBRATE,
676 "NF did not complete in calibration window\n"); 686 "NF did not complete in calibration window\n");
677 nf = 0; 687 nf = 0;
678 chan->rawNoiseFloor = nf; 688 chan->rawNoiseFloor = nf;
679 return chan->rawNoiseFloor; 689 return chan->rawNoiseFloor;
@@ -682,10 +692,10 @@ int16_t ath9k_hw_getnf(struct ath_hw *ah,
682 nf = nfarray[0]; 692 nf = nfarray[0];
683 if (getNoiseFloorThresh(ah, c->band, &nfThresh) 693 if (getNoiseFloorThresh(ah, c->band, &nfThresh)
684 && nf > nfThresh) { 694 && nf > nfThresh) {
685 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 695 ath_print(common, ATH_DBG_CALIBRATE,
686 "noise floor failed detected; " 696 "noise floor failed detected; "
687 "detected %d, threshold %d\n", 697 "detected %d, threshold %d\n",
688 nf, nfThresh); 698 nf, nfThresh);
689 chan->channelFlags |= CHANNEL_CW_INT; 699 chan->channelFlags |= CHANNEL_CW_INT;
690 } 700 }
691 } 701 }
@@ -737,51 +747,73 @@ s16 ath9k_hw_getchan_noise(struct ath_hw *ah, struct ath9k_channel *chan)
737 747
738 return nf; 748 return nf;
739} 749}
750EXPORT_SYMBOL(ath9k_hw_getchan_noise);
740 751
741static void ath9k_olc_temp_compensation(struct ath_hw *ah) 752static void ath9k_olc_temp_compensation_9287(struct ath_hw *ah)
742{ 753{
743 u32 rddata, i; 754 u32 rddata;
744 int delta, currPDADC, regval, slope; 755 int32_t delta, currPDADC, slope;
745 756
746 rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4); 757 rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
747 currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT); 758 currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
748 759
760 if (ah->initPDADC == 0 || currPDADC == 0) {
761 /*
762 * Zero value indicates that no frames have been transmitted yet,
763 * can't do temperature compensation until frames are transmitted.
764 */
765 return;
766 } else {
767 slope = ah->eep_ops->get_eeprom(ah, EEP_TEMPSENSE_SLOPE);
768
769 if (slope == 0) { /* to avoid divide by zero case */
770 delta = 0;
771 } else {
772 delta = ((currPDADC - ah->initPDADC)*4) / slope;
773 }
774 REG_RMW_FIELD(ah, AR_PHY_CH0_TX_PWRCTRL11,
775 AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
776 REG_RMW_FIELD(ah, AR_PHY_CH1_TX_PWRCTRL11,
777 AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
778 }
779}
780
781static void ath9k_olc_temp_compensation(struct ath_hw *ah)
782{
783 u32 rddata, i;
784 int delta, currPDADC, regval;
749 785
750 if (OLC_FOR_AR9287_10_LATER) { 786 if (OLC_FOR_AR9287_10_LATER) {
787 ath9k_olc_temp_compensation_9287(ah);
788 } else {
789 rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
790 currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
791
751 if (ah->initPDADC == 0 || currPDADC == 0) { 792 if (ah->initPDADC == 0 || currPDADC == 0) {
752 return; 793 return;
753 } else { 794 } else {
754 slope = ah->eep_ops->get_eeprom(ah, EEP_TEMPSENSE_SLOPE); 795 if (ah->eep_ops->get_eeprom(ah, EEP_DAC_HPWR_5G))
755 if (slope == 0) 796 delta = (currPDADC - ah->initPDADC + 4) / 8;
756 delta = 0;
757 else 797 else
758 delta = ((currPDADC - ah->initPDADC)*4) / slope; 798 delta = (currPDADC - ah->initPDADC + 5) / 10;
759 REG_RMW_FIELD(ah, AR_PHY_CH0_TX_PWRCTRL11, 799
760 AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta); 800 if (delta != ah->PDADCdelta) {
761 REG_RMW_FIELD(ah, AR_PHY_CH1_TX_PWRCTRL11, 801 ah->PDADCdelta = delta;
762 AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta); 802 for (i = 1; i < AR9280_TX_GAIN_TABLE_SIZE; i++) {
763 } 803 regval = ah->originalGain[i] - delta;
764 } else { 804 if (regval < 0)
765 if (ah->eep_ops->get_eeprom(ah, EEP_DAC_HPWR_5G)) 805 regval = 0;
766 delta = (currPDADC - ah->initPDADC + 4) / 8; 806
767 else 807 REG_RMW_FIELD(ah,
768 delta = (currPDADC - ah->initPDADC + 5) / 10; 808 AR_PHY_TX_GAIN_TBL1 + i * 4,
769 809 AR_PHY_TX_GAIN, regval);
770 if (delta != ah->PDADCdelta) { 810 }
771 ah->PDADCdelta = delta;
772 for (i = 1; i < AR9280_TX_GAIN_TABLE_SIZE; i++) {
773 regval = ah->originalGain[i] - delta;
774 if (regval < 0)
775 regval = 0;
776
777 REG_RMW_FIELD(ah, AR_PHY_TX_GAIN_TBL1 + i * 4,
778 AR_PHY_TX_GAIN, regval);
779 } 811 }
780 } 812 }
781 } 813 }
782} 814}
783 815
784static void ath9k_hw_9271_pa_cal(struct ath_hw *ah) 816static void ath9k_hw_9271_pa_cal(struct ath_hw *ah, bool is_reset)
785{ 817{
786 u32 regVal; 818 u32 regVal;
787 unsigned int i; 819 unsigned int i;
@@ -845,7 +877,7 @@ static void ath9k_hw_9271_pa_cal(struct ath_hw *ah)
845 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9271_AN_RF2G6_OFFS, 0); 877 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9271_AN_RF2G6_OFFS, 0);
846 878
847 /* find off_6_1; */ 879 /* find off_6_1; */
848 for (i = 6; i >= 0; i--) { 880 for (i = 6; i > 0; i--) {
849 regVal = REG_READ(ah, 0x7834); 881 regVal = REG_READ(ah, 0x7834);
850 regVal |= (1 << (20 + i)); 882 regVal |= (1 << (20 + i));
851 REG_WRITE(ah, 0x7834, regVal); 883 REG_WRITE(ah, 0x7834, regVal);
@@ -857,10 +889,19 @@ static void ath9k_hw_9271_pa_cal(struct ath_hw *ah)
857 REG_WRITE(ah, 0x7834, regVal); 889 REG_WRITE(ah, 0x7834, regVal);
858 } 890 }
859 891
860 /* Empirical offset correction */ 892 regVal = (regVal >>20) & 0x7f;
861#if 0 893
862 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9271_AN_RF2G6_OFFS, 0x20); 894 /* Update PA cal info */
863#endif 895 if ((!is_reset) && (ah->pacal_info.prev_offset == regVal)) {
896 if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
897 ah->pacal_info.max_skipcount =
898 2 * ah->pacal_info.max_skipcount;
899 ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
900 } else {
901 ah->pacal_info.max_skipcount = 1;
902 ah->pacal_info.skipcount = 0;
903 ah->pacal_info.prev_offset = regVal;
904 }
864 905
865 regVal = REG_READ(ah, 0x7834); 906 regVal = REG_READ(ah, 0x7834);
866 regVal |= 0x1; 907 regVal |= 0x1;
@@ -875,7 +916,7 @@ static void ath9k_hw_9271_pa_cal(struct ath_hw *ah)
875 916
876static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah, bool is_reset) 917static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah, bool is_reset)
877{ 918{
878 919 struct ath_common *common = ath9k_hw_common(ah);
879 u32 regVal; 920 u32 regVal;
880 int i, offset, offs_6_1, offs_0; 921 int i, offset, offs_6_1, offs_0;
881 u32 ccomp_org, reg_field; 922 u32 ccomp_org, reg_field;
@@ -889,7 +930,7 @@ static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah, bool is_reset)
889 { 0x7838, 0 }, 930 { 0x7838, 0 },
890 }; 931 };
891 932
892 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "Running PA Calibration\n"); 933 ath_print(common, ATH_DBG_CALIBRATE, "Running PA Calibration\n");
893 934
894 /* PA CAL is not needed for high power solution */ 935 /* PA CAL is not needed for high power solution */
895 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 936 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) ==
@@ -1011,7 +1052,7 @@ bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
1011 if (longcal) { 1052 if (longcal) {
1012 /* Do periodic PAOffset Cal */ 1053 /* Do periodic PAOffset Cal */
1013 if (AR_SREV_9271(ah)) 1054 if (AR_SREV_9271(ah))
1014 ath9k_hw_9271_pa_cal(ah); 1055 ath9k_hw_9271_pa_cal(ah, false);
1015 else if (AR_SREV_9285_11_OR_LATER(ah)) { 1056 else if (AR_SREV_9285_11_OR_LATER(ah)) {
1016 if (!ah->pacal_info.skipcount) 1057 if (!ah->pacal_info.skipcount)
1017 ath9k_hw_9285_pa_cal(ah, false); 1058 ath9k_hw_9285_pa_cal(ah, false);
@@ -1036,9 +1077,13 @@ bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
1036 1077
1037 return iscaldone; 1078 return iscaldone;
1038} 1079}
1080EXPORT_SYMBOL(ath9k_hw_calibrate);
1039 1081
1082/* Carrier leakage Calibration fix */
1040static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan) 1083static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan)
1041{ 1084{
1085 struct ath_common *common = ath9k_hw_common(ah);
1086
1042 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); 1087 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
1043 if (IS_CHAN_HT20(chan)) { 1088 if (IS_CHAN_HT20(chan)) {
1044 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE); 1089 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
@@ -1049,9 +1094,9 @@ static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan)
1049 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); 1094 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
1050 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, 1095 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
1051 AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) { 1096 AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) {
1052 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "offset " 1097 ath_print(common, ATH_DBG_CALIBRATE, "offset "
1053 "calibration failed to complete in " 1098 "calibration failed to complete in "
1054 "1ms; noisy ??\n"); 1099 "1ms; noisy ??\n");
1055 return false; 1100 return false;
1056 } 1101 }
1057 REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN); 1102 REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
@@ -1064,8 +1109,8 @@ static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan)
1064 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); 1109 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
1065 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 1110 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
1066 0, AH_WAIT_TIMEOUT)) { 1111 0, AH_WAIT_TIMEOUT)) {
1067 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "offset calibration " 1112 ath_print(common, ATH_DBG_CALIBRATE, "offset calibration "
1068 "failed to complete in 1ms; noisy ??\n"); 1113 "failed to complete in 1ms; noisy ??\n");
1069 return false; 1114 return false;
1070 } 1115 }
1071 1116
@@ -1078,7 +1123,9 @@ static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan)
1078 1123
1079bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan) 1124bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
1080{ 1125{
1081 if (AR_SREV_9285_12_OR_LATER(ah)) { 1126 struct ath_common *common = ath9k_hw_common(ah);
1127
1128 if (AR_SREV_9271(ah) || AR_SREV_9285_12_OR_LATER(ah)) {
1082 if (!ar9285_clc(ah, chan)) 1129 if (!ar9285_clc(ah, chan))
1083 return false; 1130 return false;
1084 } else { 1131 } else {
@@ -1098,9 +1145,9 @@ bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
1098 /* Poll for offset calibration complete */ 1145 /* Poll for offset calibration complete */
1099 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 1146 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
1100 0, AH_WAIT_TIMEOUT)) { 1147 0, AH_WAIT_TIMEOUT)) {
1101 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 1148 ath_print(common, ATH_DBG_CALIBRATE,
1102 "offset calibration failed to complete in 1ms; " 1149 "offset calibration failed to "
1103 "noisy environment?\n"); 1150 "complete in 1ms; noisy environment?\n");
1104 return false; 1151 return false;
1105 } 1152 }
1106 1153
@@ -1114,7 +1161,9 @@ bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
1114 } 1161 }
1115 1162
1116 /* Do PA Calibration */ 1163 /* Do PA Calibration */
1117 if (AR_SREV_9285_11_OR_LATER(ah)) 1164 if (AR_SREV_9271(ah))
1165 ath9k_hw_9271_pa_cal(ah, true);
1166 else if (AR_SREV_9285_11_OR_LATER(ah))
1118 ath9k_hw_9285_pa_cal(ah, true); 1167 ath9k_hw_9285_pa_cal(ah, true);
1119 1168
1120 /* Do NF Calibration after DC offset and other calibrations */ 1169 /* Do NF Calibration after DC offset and other calibrations */
@@ -1128,20 +1177,20 @@ bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
1128 if (ath9k_hw_iscal_supported(ah, ADC_GAIN_CAL)) { 1177 if (ath9k_hw_iscal_supported(ah, ADC_GAIN_CAL)) {
1129 INIT_CAL(&ah->adcgain_caldata); 1178 INIT_CAL(&ah->adcgain_caldata);
1130 INSERT_CAL(ah, &ah->adcgain_caldata); 1179 INSERT_CAL(ah, &ah->adcgain_caldata);
1131 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 1180 ath_print(common, ATH_DBG_CALIBRATE,
1132 "enabling ADC Gain Calibration.\n"); 1181 "enabling ADC Gain Calibration.\n");
1133 } 1182 }
1134 if (ath9k_hw_iscal_supported(ah, ADC_DC_CAL)) { 1183 if (ath9k_hw_iscal_supported(ah, ADC_DC_CAL)) {
1135 INIT_CAL(&ah->adcdc_caldata); 1184 INIT_CAL(&ah->adcdc_caldata);
1136 INSERT_CAL(ah, &ah->adcdc_caldata); 1185 INSERT_CAL(ah, &ah->adcdc_caldata);
1137 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 1186 ath_print(common, ATH_DBG_CALIBRATE,
1138 "enabling ADC DC Calibration.\n"); 1187 "enabling ADC DC Calibration.\n");
1139 } 1188 }
1140 if (ath9k_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) { 1189 if (ath9k_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {
1141 INIT_CAL(&ah->iq_caldata); 1190 INIT_CAL(&ah->iq_caldata);
1142 INSERT_CAL(ah, &ah->iq_caldata); 1191 INSERT_CAL(ah, &ah->iq_caldata);
1143 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 1192 ath_print(common, ATH_DBG_CALIBRATE,
1144 "enabling IQ Calibration.\n"); 1193 "enabling IQ Calibration.\n");
1145 } 1194 }
1146 1195
1147 ah->cal_list_curr = ah->cal_list; 1196 ah->cal_list_curr = ah->cal_list;
diff --git a/drivers/net/wireless/ath/ath9k/calib.h b/drivers/net/wireless/ath/ath9k/calib.h
index 9028ab193e42..b2c873e97485 100644
--- a/drivers/net/wireless/ath/ath9k/calib.h
+++ b/drivers/net/wireless/ath/ath9k/calib.h
@@ -17,6 +17,8 @@
17#ifndef CALIB_H 17#ifndef CALIB_H
18#define CALIB_H 18#define CALIB_H
19 19
20#include "hw.h"
21
20extern const struct ath9k_percal_data iq_cal_multi_sample; 22extern const struct ath9k_percal_data iq_cal_multi_sample;
21extern const struct ath9k_percal_data iq_cal_single_sample; 23extern const struct ath9k_percal_data iq_cal_single_sample;
22extern const struct ath9k_percal_data adc_gain_cal_multi_sample; 24extern const struct ath9k_percal_data adc_gain_cal_multi_sample;
diff --git a/drivers/net/wireless/ath/ath9k/common.c b/drivers/net/wireless/ath/ath9k/common.c
new file mode 100644
index 000000000000..4a13632e3e4d
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/common.c
@@ -0,0 +1,295 @@
1/*
2 * Copyright (c) 2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17/*
18 * Module for common driver code between ath9k and ath9k_htc
19 */
20
21#include <linux/kernel.h>
22#include <linux/module.h>
23
24#include "common.h"
25
26MODULE_AUTHOR("Atheros Communications");
27MODULE_DESCRIPTION("Shared library for Atheros wireless 802.11n LAN cards.");
28MODULE_LICENSE("Dual BSD/GPL");
29
30/* Common RX processing */
31
32/* Assumes you've already done the endian to CPU conversion */
33static bool ath9k_rx_accept(struct ath_common *common,
34 struct sk_buff *skb,
35 struct ieee80211_rx_status *rxs,
36 struct ath_rx_status *rx_stats,
37 bool *decrypt_error)
38{
39 struct ath_hw *ah = common->ah;
40 struct ieee80211_hdr *hdr;
41 __le16 fc;
42
43 hdr = (struct ieee80211_hdr *) skb->data;
44 fc = hdr->frame_control;
45
46 if (!rx_stats->rs_datalen)
47 return false;
48 /*
49 * rs_status follows rs_datalen so if rs_datalen is too large
50 * we can take a hint that hardware corrupted it, so ignore
51 * those frames.
52 */
53 if (rx_stats->rs_datalen > common->rx_bufsize)
54 return false;
55
56 /*
57 * rs_more indicates chained descriptors which can be used
58 * to link buffers together for a sort of scatter-gather
59 * operation.
60 *
61 * The rx_stats->rs_status will not be set until the end of the
62 * chained descriptors so it can be ignored if rs_more is set. The
63 * rs_more will be false at the last element of the chained
64 * descriptors.
65 */
66 if (!rx_stats->rs_more && rx_stats->rs_status != 0) {
67 if (rx_stats->rs_status & ATH9K_RXERR_CRC)
68 rxs->flag |= RX_FLAG_FAILED_FCS_CRC;
69 if (rx_stats->rs_status & ATH9K_RXERR_PHY)
70 return false;
71
72 if (rx_stats->rs_status & ATH9K_RXERR_DECRYPT) {
73 *decrypt_error = true;
74 } else if (rx_stats->rs_status & ATH9K_RXERR_MIC) {
75 if (ieee80211_is_ctl(fc))
76 /*
77 * Sometimes, we get invalid
78 * MIC failures on valid control frames.
79 * Remove these mic errors.
80 */
81 rx_stats->rs_status &= ~ATH9K_RXERR_MIC;
82 else
83 rxs->flag |= RX_FLAG_MMIC_ERROR;
84 }
85 /*
86 * Reject error frames with the exception of
87 * decryption and MIC failures. For monitor mode,
88 * we also ignore the CRC error.
89 */
90 if (ah->opmode == NL80211_IFTYPE_MONITOR) {
91 if (rx_stats->rs_status &
92 ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC |
93 ATH9K_RXERR_CRC))
94 return false;
95 } else {
96 if (rx_stats->rs_status &
97 ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC)) {
98 return false;
99 }
100 }
101 }
102 return true;
103}
104
105static u8 ath9k_process_rate(struct ath_common *common,
106 struct ieee80211_hw *hw,
107 struct ath_rx_status *rx_stats,
108 struct ieee80211_rx_status *rxs,
109 struct sk_buff *skb)
110{
111 struct ieee80211_supported_band *sband;
112 enum ieee80211_band band;
113 unsigned int i = 0;
114
115 band = hw->conf.channel->band;
116 sband = hw->wiphy->bands[band];
117
118 if (rx_stats->rs_rate & 0x80) {
119 /* HT rate */
120 rxs->flag |= RX_FLAG_HT;
121 if (rx_stats->rs_flags & ATH9K_RX_2040)
122 rxs->flag |= RX_FLAG_40MHZ;
123 if (rx_stats->rs_flags & ATH9K_RX_GI)
124 rxs->flag |= RX_FLAG_SHORT_GI;
125 return rx_stats->rs_rate & 0x7f;
126 }
127
128 for (i = 0; i < sband->n_bitrates; i++) {
129 if (sband->bitrates[i].hw_value == rx_stats->rs_rate)
130 return i;
131 if (sband->bitrates[i].hw_value_short == rx_stats->rs_rate) {
132 rxs->flag |= RX_FLAG_SHORTPRE;
133 return i;
134 }
135 }
136
137 /* No valid hardware bitrate found -- we should not get here */
138 ath_print(common, ATH_DBG_XMIT, "unsupported hw bitrate detected "
139 "0x%02x using 1 Mbit\n", rx_stats->rs_rate);
140 if ((common->debug_mask & ATH_DBG_XMIT))
141 print_hex_dump_bytes("", DUMP_PREFIX_NONE, skb->data, skb->len);
142
143 return 0;
144}
145
146static void ath9k_process_rssi(struct ath_common *common,
147 struct ieee80211_hw *hw,
148 struct sk_buff *skb,
149 struct ath_rx_status *rx_stats)
150{
151 struct ath_hw *ah = common->ah;
152 struct ieee80211_sta *sta;
153 struct ieee80211_hdr *hdr;
154 struct ath_node *an;
155 int last_rssi = ATH_RSSI_DUMMY_MARKER;
156 __le16 fc;
157
158 hdr = (struct ieee80211_hdr *)skb->data;
159 fc = hdr->frame_control;
160
161 rcu_read_lock();
162 /*
163 * XXX: use ieee80211_find_sta! This requires quite a bit of work
164 * under the current ath9k virtual wiphy implementation as we have
165 * no way of tying a vif to wiphy. Typically vifs are attached to
166 * at least one sdata of a wiphy on mac80211 but with ath9k virtual
167 * wiphy you'd have to iterate over every wiphy and each sdata.
168 */
169 sta = ieee80211_find_sta_by_hw(hw, hdr->addr2);
170 if (sta) {
171 an = (struct ath_node *) sta->drv_priv;
172 if (rx_stats->rs_rssi != ATH9K_RSSI_BAD &&
173 !rx_stats->rs_moreaggr)
174 ATH_RSSI_LPF(an->last_rssi, rx_stats->rs_rssi);
175 last_rssi = an->last_rssi;
176 }
177 rcu_read_unlock();
178
179 if (likely(last_rssi != ATH_RSSI_DUMMY_MARKER))
180 rx_stats->rs_rssi = ATH_EP_RND(last_rssi,
181 ATH_RSSI_EP_MULTIPLIER);
182 if (rx_stats->rs_rssi < 0)
183 rx_stats->rs_rssi = 0;
184 else if (rx_stats->rs_rssi > 127)
185 rx_stats->rs_rssi = 127;
186
187 /* Update Beacon RSSI, this is used by ANI. */
188 if (ieee80211_is_beacon(fc))
189 ah->stats.avgbrssi = rx_stats->rs_rssi;
190}
191
192/*
193 * For Decrypt or Demic errors, we only mark packet status here and always push
194 * up the frame up to let mac80211 handle the actual error case, be it no
195 * decryption key or real decryption error. This let us keep statistics there.
196 */
197int ath9k_cmn_rx_skb_preprocess(struct ath_common *common,
198 struct ieee80211_hw *hw,
199 struct sk_buff *skb,
200 struct ath_rx_status *rx_stats,
201 struct ieee80211_rx_status *rx_status,
202 bool *decrypt_error)
203{
204 struct ath_hw *ah = common->ah;
205
206 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
207 if (!ath9k_rx_accept(common, skb, rx_status, rx_stats, decrypt_error))
208 return -EINVAL;
209
210 ath9k_process_rssi(common, hw, skb, rx_stats);
211
212 rx_status->rate_idx = ath9k_process_rate(common, hw,
213 rx_stats, rx_status, skb);
214 rx_status->mactime = ath9k_hw_extend_tsf(ah, rx_stats->rs_tstamp);
215 rx_status->band = hw->conf.channel->band;
216 rx_status->freq = hw->conf.channel->center_freq;
217 rx_status->noise = common->ani.noise_floor;
218 rx_status->signal = ATH_DEFAULT_NOISE_FLOOR + rx_stats->rs_rssi;
219 rx_status->antenna = rx_stats->rs_antenna;
220 rx_status->flag |= RX_FLAG_TSFT;
221
222 return 0;
223}
224EXPORT_SYMBOL(ath9k_cmn_rx_skb_preprocess);
225
226void ath9k_cmn_rx_skb_postprocess(struct ath_common *common,
227 struct sk_buff *skb,
228 struct ath_rx_status *rx_stats,
229 struct ieee80211_rx_status *rxs,
230 bool decrypt_error)
231{
232 struct ath_hw *ah = common->ah;
233 struct ieee80211_hdr *hdr;
234 int hdrlen, padpos, padsize;
235 u8 keyix;
236 __le16 fc;
237
238 /* see if any padding is done by the hw and remove it */
239 hdr = (struct ieee80211_hdr *) skb->data;
240 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
241 padpos = 24;
242 fc = hdr->frame_control;
243 if ((fc & cpu_to_le16(IEEE80211_FCTL_FROMDS|IEEE80211_FCTL_TODS)) ==
244 cpu_to_le16(IEEE80211_FCTL_FROMDS|IEEE80211_FCTL_TODS)) {
245 padpos += 6; /* ETH_ALEN */
246 }
247 if ((fc & cpu_to_le16(IEEE80211_STYPE_QOS_DATA|IEEE80211_FCTL_FTYPE)) ==
248 cpu_to_le16(IEEE80211_STYPE_QOS_DATA|IEEE80211_FTYPE_DATA)) {
249 padpos += 2;
250 }
251
252 /* The MAC header is padded to have 32-bit boundary if the
253 * packet payload is non-zero. The general calculation for
254 * padsize would take into account odd header lengths:
255 * padsize = (4 - padpos % 4) % 4; However, since only
256 * even-length headers are used, padding can only be 0 or 2
257 * bytes and we can optimize this a bit. In addition, we must
258 * not try to remove padding from short control frames that do
259 * not have payload. */
260 padsize = padpos & 3;
261 if (padsize && skb->len>=padpos+padsize+FCS_LEN) {
262 memmove(skb->data + padsize, skb->data, padpos);
263 skb_pull(skb, padsize);
264 }
265
266 keyix = rx_stats->rs_keyix;
267
268 if (!(keyix == ATH9K_RXKEYIX_INVALID) && !decrypt_error) {
269 rxs->flag |= RX_FLAG_DECRYPTED;
270 } else if (ieee80211_has_protected(fc)
271 && !decrypt_error && skb->len >= hdrlen + 4) {
272 keyix = skb->data[hdrlen + 3] >> 6;
273
274 if (test_bit(keyix, common->keymap))
275 rxs->flag |= RX_FLAG_DECRYPTED;
276 }
277 if (ah->sw_mgmt_crypto &&
278 (rxs->flag & RX_FLAG_DECRYPTED) &&
279 ieee80211_is_mgmt(fc))
280 /* Use software decrypt for management frames. */
281 rxs->flag &= ~RX_FLAG_DECRYPTED;
282}
283EXPORT_SYMBOL(ath9k_cmn_rx_skb_postprocess);
284
285static int __init ath9k_cmn_init(void)
286{
287 return 0;
288}
289module_init(ath9k_cmn_init);
290
291static void __exit ath9k_cmn_exit(void)
292{
293 return;
294}
295module_exit(ath9k_cmn_exit);
diff --git a/drivers/net/wireless/ath/ath9k/common.h b/drivers/net/wireless/ath/ath9k/common.h
new file mode 100644
index 000000000000..4e1176029356
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/common.h
@@ -0,0 +1,124 @@
1/*
2 * Copyright (c) 2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <net/mac80211.h>
18
19#include "../ath.h"
20#include "../debug.h"
21
22#include "hw.h"
23
24/* Common header for Atheros 802.11n base driver cores */
25
26#define WME_NUM_TID 16
27#define WME_BA_BMP_SIZE 64
28#define WME_MAX_BA WME_BA_BMP_SIZE
29#define ATH_TID_MAX_BUFS (2 * WME_MAX_BA)
30
31#define WME_AC_BE 0
32#define WME_AC_BK 1
33#define WME_AC_VI 2
34#define WME_AC_VO 3
35#define WME_NUM_AC 4
36
37#define ATH_RSSI_DUMMY_MARKER 0x127
38#define ATH_RSSI_LPF_LEN 10
39#define RSSI_LPF_THRESHOLD -20
40#define ATH_RSSI_EP_MULTIPLIER (1<<7)
41#define ATH_EP_MUL(x, mul) ((x) * (mul))
42#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), ATH_RSSI_EP_MULTIPLIER))
43#define ATH_LPF_RSSI(x, y, len) \
44 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y))
45#define ATH_RSSI_LPF(x, y) do { \
46 if ((y) >= RSSI_LPF_THRESHOLD) \
47 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \
48} while (0)
49#define ATH_EP_RND(x, mul) \
50 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
51
52struct ath_atx_ac {
53 int sched;
54 int qnum;
55 struct list_head list;
56 struct list_head tid_q;
57};
58
59struct ath_buf_state {
60 int bfs_nframes;
61 u16 bfs_al;
62 u16 bfs_frmlen;
63 int bfs_seqno;
64 int bfs_tidno;
65 int bfs_retries;
66 u8 bf_type;
67 u32 bfs_keyix;
68 enum ath9k_key_type bfs_keytype;
69};
70
71struct ath_buf {
72 struct list_head list;
73 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
74 an aggregate) */
75 struct ath_buf *bf_next; /* next subframe in the aggregate */
76 struct sk_buff *bf_mpdu; /* enclosing frame structure */
77 struct ath_desc *bf_desc; /* virtual addr of desc */
78 dma_addr_t bf_daddr; /* physical addr of desc */
79 dma_addr_t bf_buf_addr; /* physical addr of data buffer */
80 bool bf_stale;
81 u16 bf_flags;
82 struct ath_buf_state bf_state;
83 dma_addr_t bf_dmacontext;
84 struct ath_wiphy *aphy;
85};
86
87struct ath_atx_tid {
88 struct list_head list;
89 struct list_head buf_q;
90 struct ath_node *an;
91 struct ath_atx_ac *ac;
92 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS];
93 u16 seq_start;
94 u16 seq_next;
95 u16 baw_size;
96 int tidno;
97 int baw_head; /* first un-acked tx buffer */
98 int baw_tail; /* next unused tx buffer slot */
99 int sched;
100 int paused;
101 u8 state;
102};
103
104struct ath_node {
105 struct ath_common *common;
106 struct ath_atx_tid tid[WME_NUM_TID];
107 struct ath_atx_ac ac[WME_NUM_AC];
108 u16 maxampdu;
109 u8 mpdudensity;
110 int last_rssi;
111};
112
113int ath9k_cmn_rx_skb_preprocess(struct ath_common *common,
114 struct ieee80211_hw *hw,
115 struct sk_buff *skb,
116 struct ath_rx_status *rx_stats,
117 struct ieee80211_rx_status *rx_status,
118 bool *decrypt_error);
119
120void ath9k_cmn_rx_skb_postprocess(struct ath_common *common,
121 struct sk_buff *skb,
122 struct ath_rx_status *rx_stats,
123 struct ieee80211_rx_status *rxs,
124 bool decrypt_error);
diff --git a/drivers/net/wireless/ath/ath9k/debug.c b/drivers/net/wireless/ath/ath9k/debug.c
index 2be4c2252047..06f1fcfb03e9 100644
--- a/drivers/net/wireless/ath/ath9k/debug.c
+++ b/drivers/net/wireless/ath/ath9k/debug.c
@@ -18,26 +18,13 @@
18 18
19#include "ath9k.h" 19#include "ath9k.h"
20 20
21static unsigned int ath9k_debug = DBG_DEFAULT; 21#define REG_WRITE_D(_ah, _reg, _val) \
22module_param_named(debug, ath9k_debug, uint, 0); 22 ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg))
23#define REG_READ_D(_ah, _reg) \
24 ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
23 25
24static struct dentry *ath9k_debugfs_root; 26static struct dentry *ath9k_debugfs_root;
25 27
26void DPRINTF(struct ath_softc *sc, int dbg_mask, const char *fmt, ...)
27{
28 if (!sc)
29 return;
30
31 if (sc->debug.debug_mask & dbg_mask) {
32 va_list args;
33
34 va_start(args, fmt);
35 printk(KERN_DEBUG "ath9k: ");
36 vprintk(fmt, args);
37 va_end(args);
38 }
39}
40
41static int ath9k_debugfs_open(struct inode *inode, struct file *file) 28static int ath9k_debugfs_open(struct inode *inode, struct file *file)
42{ 29{
43 file->private_data = inode->i_private; 30 file->private_data = inode->i_private;
@@ -48,10 +35,11 @@ static ssize_t read_file_debug(struct file *file, char __user *user_buf,
48 size_t count, loff_t *ppos) 35 size_t count, loff_t *ppos)
49{ 36{
50 struct ath_softc *sc = file->private_data; 37 struct ath_softc *sc = file->private_data;
38 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
51 char buf[32]; 39 char buf[32];
52 unsigned int len; 40 unsigned int len;
53 41
54 len = snprintf(buf, sizeof(buf), "0x%08x\n", sc->debug.debug_mask); 42 len = snprintf(buf, sizeof(buf), "0x%08x\n", common->debug_mask);
55 return simple_read_from_buffer(user_buf, count, ppos, buf, len); 43 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
56} 44}
57 45
@@ -59,6 +47,7 @@ static ssize_t write_file_debug(struct file *file, const char __user *user_buf,
59 size_t count, loff_t *ppos) 47 size_t count, loff_t *ppos)
60{ 48{
61 struct ath_softc *sc = file->private_data; 49 struct ath_softc *sc = file->private_data;
50 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
62 unsigned long mask; 51 unsigned long mask;
63 char buf[32]; 52 char buf[32];
64 ssize_t len; 53 ssize_t len;
@@ -71,7 +60,7 @@ static ssize_t write_file_debug(struct file *file, const char __user *user_buf,
71 if (strict_strtoul(buf, 0, &mask)) 60 if (strict_strtoul(buf, 0, &mask))
72 return -EINVAL; 61 return -EINVAL;
73 62
74 sc->debug.debug_mask = mask; 63 common->debug_mask = mask;
75 return count; 64 return count;
76} 65}
77 66
@@ -95,7 +84,7 @@ static ssize_t read_file_dma(struct file *file, char __user *user_buf,
95 84
96 ath9k_ps_wakeup(sc); 85 ath9k_ps_wakeup(sc);
97 86
98 REG_WRITE(ah, AR_MACMISC, 87 REG_WRITE_D(ah, AR_MACMISC,
99 ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) | 88 ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) |
100 (AR_MACMISC_MISC_OBS_BUS_1 << 89 (AR_MACMISC_MISC_OBS_BUS_1 <<
101 AR_MACMISC_MISC_OBS_BUS_MSB_S))); 90 AR_MACMISC_MISC_OBS_BUS_MSB_S)));
@@ -107,7 +96,7 @@ static ssize_t read_file_dma(struct file *file, char __user *user_buf,
107 if (i % 4 == 0) 96 if (i % 4 == 0)
108 len += snprintf(buf + len, sizeof(buf) - len, "\n"); 97 len += snprintf(buf + len, sizeof(buf) - len, "\n");
109 98
110 val[i] = REG_READ(ah, AR_DMADBG_0 + (i * sizeof(u32))); 99 val[i] = REG_READ_D(ah, AR_DMADBG_0 + (i * sizeof(u32)));
111 len += snprintf(buf + len, sizeof(buf) - len, "%d: %08x ", 100 len += snprintf(buf + len, sizeof(buf) - len, "%d: %08x ",
112 i, val[i]); 101 i, val[i]);
113 } 102 }
@@ -157,9 +146,9 @@ static ssize_t read_file_dma(struct file *file, char __user *user_buf,
157 (val[6] & 0x0001e000) >> 13, (val[6] & 0x001e0000) >> 17); 146 (val[6] & 0x0001e000) >> 13, (val[6] & 0x001e0000) >> 17);
158 147
159 len += snprintf(buf + len, sizeof(buf) - len, "pcu observe: 0x%x \n", 148 len += snprintf(buf + len, sizeof(buf) - len, "pcu observe: 0x%x \n",
160 REG_READ(ah, AR_OBS_BUS_1)); 149 REG_READ_D(ah, AR_OBS_BUS_1));
161 len += snprintf(buf + len, sizeof(buf) - len, 150 len += snprintf(buf + len, sizeof(buf) - len,
162 "AR_CR: 0x%x \n", REG_READ(ah, AR_CR)); 151 "AR_CR: 0x%x \n", REG_READ_D(ah, AR_CR));
163 152
164 ath9k_ps_restore(sc); 153 ath9k_ps_restore(sc);
165 154
@@ -268,14 +257,17 @@ static const struct file_operations fops_interrupt = {
268 257
269void ath_debug_stat_rc(struct ath_softc *sc, struct sk_buff *skb) 258void ath_debug_stat_rc(struct ath_softc *sc, struct sk_buff *skb)
270{ 259{
271 struct ath_tx_info_priv *tx_info_priv = NULL;
272 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 260 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
273 struct ieee80211_tx_rate *rates = tx_info->status.rates; 261 struct ieee80211_tx_rate *rates = tx_info->status.rates;
274 int final_ts_idx, idx; 262 int final_ts_idx = 0, idx, i;
275 struct ath_rc_stats *stats; 263 struct ath_rc_stats *stats;
276 264
277 tx_info_priv = ATH_TX_INFO_PRIV(tx_info); 265 for (i = 0; i < IEEE80211_TX_MAX_RATES; i++) {
278 final_ts_idx = tx_info_priv->tx.ts_rateindex; 266 if (!rates[i].count)
267 break;
268
269 final_ts_idx = i;
270 }
279 idx = rates[final_ts_idx].idx; 271 idx = rates[final_ts_idx].idx;
280 stats = &sc->debug.stats.rcstats[idx]; 272 stats = &sc->debug.stats.rcstats[idx];
281 stats->success++; 273 stats->success++;
@@ -376,12 +368,12 @@ static ssize_t read_file_wiphy(struct file *file, char __user *user_buf,
376 aphy->chan_idx, aphy->chan_is_ht); 368 aphy->chan_idx, aphy->chan_is_ht);
377 } 369 }
378 370
379 put_unaligned_le32(REG_READ(sc->sc_ah, AR_STA_ID0), addr); 371 put_unaligned_le32(REG_READ_D(sc->sc_ah, AR_STA_ID0), addr);
380 put_unaligned_le16(REG_READ(sc->sc_ah, AR_STA_ID1) & 0xffff, addr + 4); 372 put_unaligned_le16(REG_READ_D(sc->sc_ah, AR_STA_ID1) & 0xffff, addr + 4);
381 len += snprintf(buf + len, sizeof(buf) - len, 373 len += snprintf(buf + len, sizeof(buf) - len,
382 "addr: %pM\n", addr); 374 "addr: %pM\n", addr);
383 put_unaligned_le32(REG_READ(sc->sc_ah, AR_BSSMSKL), addr); 375 put_unaligned_le32(REG_READ_D(sc->sc_ah, AR_BSSMSKL), addr);
384 put_unaligned_le16(REG_READ(sc->sc_ah, AR_BSSMSKU) & 0xffff, addr + 4); 376 put_unaligned_le16(REG_READ_D(sc->sc_ah, AR_BSSMSKU) & 0xffff, addr + 4);
385 len += snprintf(buf + len, sizeof(buf) - len, 377 len += snprintf(buf + len, sizeof(buf) - len,
386 "addrmask: %pM\n", addr); 378 "addrmask: %pM\n", addr);
387 379
@@ -568,9 +560,10 @@ static const struct file_operations fops_xmit = {
568 .owner = THIS_MODULE 560 .owner = THIS_MODULE
569}; 561};
570 562
571int ath9k_init_debug(struct ath_softc *sc) 563int ath9k_init_debug(struct ath_hw *ah)
572{ 564{
573 sc->debug.debug_mask = ath9k_debug; 565 struct ath_common *common = ath9k_hw_common(ah);
566 struct ath_softc *sc = (struct ath_softc *) common->priv;
574 567
575 if (!ath9k_debugfs_root) 568 if (!ath9k_debugfs_root)
576 return -ENOENT; 569 return -ENOENT;
@@ -619,12 +612,15 @@ int ath9k_init_debug(struct ath_softc *sc)
619 612
620 return 0; 613 return 0;
621err: 614err:
622 ath9k_exit_debug(sc); 615 ath9k_exit_debug(ah);
623 return -ENOMEM; 616 return -ENOMEM;
624} 617}
625 618
626void ath9k_exit_debug(struct ath_softc *sc) 619void ath9k_exit_debug(struct ath_hw *ah)
627{ 620{
621 struct ath_common *common = ath9k_hw_common(ah);
622 struct ath_softc *sc = (struct ath_softc *) common->priv;
623
628 debugfs_remove(sc->debug.debugfs_xmit); 624 debugfs_remove(sc->debug.debugfs_xmit);
629 debugfs_remove(sc->debug.debugfs_wiphy); 625 debugfs_remove(sc->debug.debugfs_wiphy);
630 debugfs_remove(sc->debug.debugfs_rcstat); 626 debugfs_remove(sc->debug.debugfs_rcstat);
diff --git a/drivers/net/wireless/ath/ath9k/debug.h b/drivers/net/wireless/ath/ath9k/debug.h
index 7241f4748338..749e85d57551 100644
--- a/drivers/net/wireless/ath/ath9k/debug.h
+++ b/drivers/net/wireless/ath/ath9k/debug.h
@@ -17,25 +17,7 @@
17#ifndef DEBUG_H 17#ifndef DEBUG_H
18#define DEBUG_H 18#define DEBUG_H
19 19
20enum ATH_DEBUG { 20#include "hw.h"
21 ATH_DBG_RESET = 0x00000001,
22 ATH_DBG_QUEUE = 0x00000002,
23 ATH_DBG_EEPROM = 0x00000004,
24 ATH_DBG_CALIBRATE = 0x00000008,
25 ATH_DBG_INTERRUPT = 0x00000010,
26 ATH_DBG_REGULATORY = 0x00000020,
27 ATH_DBG_ANI = 0x00000040,
28 ATH_DBG_XMIT = 0x00000080,
29 ATH_DBG_BEACON = 0x00000100,
30 ATH_DBG_CONFIG = 0x00000200,
31 ATH_DBG_FATAL = 0x00000400,
32 ATH_DBG_PS = 0x00000800,
33 ATH_DBG_HWTIMER = 0x00001000,
34 ATH_DBG_BTCOEX = 0x00002000,
35 ATH_DBG_ANY = 0xffffffff
36};
37
38#define DBG_DEFAULT (ATH_DBG_FATAL)
39 21
40struct ath_txq; 22struct ath_txq;
41struct ath_buf; 23struct ath_buf;
@@ -140,7 +122,6 @@ struct ath_stats {
140}; 122};
141 123
142struct ath9k_debug { 124struct ath9k_debug {
143 int debug_mask;
144 struct dentry *debugfs_phy; 125 struct dentry *debugfs_phy;
145 struct dentry *debugfs_debug; 126 struct dentry *debugfs_debug;
146 struct dentry *debugfs_dma; 127 struct dentry *debugfs_dma;
@@ -151,9 +132,9 @@ struct ath9k_debug {
151 struct ath_stats stats; 132 struct ath_stats stats;
152}; 133};
153 134
154void DPRINTF(struct ath_softc *sc, int dbg_mask, const char *fmt, ...); 135int ath9k_init_debug(struct ath_hw *ah);
155int ath9k_init_debug(struct ath_softc *sc); 136void ath9k_exit_debug(struct ath_hw *ah);
156void ath9k_exit_debug(struct ath_softc *sc); 137
157int ath9k_debug_create_root(void); 138int ath9k_debug_create_root(void);
158void ath9k_debug_remove_root(void); 139void ath9k_debug_remove_root(void);
159void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status); 140void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
@@ -165,17 +146,12 @@ void ath_debug_stat_retries(struct ath_softc *sc, int rix,
165 146
166#else 147#else
167 148
168static inline void DPRINTF(struct ath_softc *sc, int dbg_mask, 149static inline int ath9k_init_debug(struct ath_hw *ah)
169 const char *fmt, ...)
170{
171}
172
173static inline int ath9k_init_debug(struct ath_softc *sc)
174{ 150{
175 return 0; 151 return 0;
176} 152}
177 153
178static inline void ath9k_exit_debug(struct ath_softc *sc) 154static inline void ath9k_exit_debug(struct ath_hw *ah)
179{ 155{
180} 156}
181 157
diff --git a/drivers/net/wireless/ath/ath9k/eeprom.c b/drivers/net/wireless/ath/ath9k/eeprom.c
index b6e52d0f8c48..dacaae934148 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom.c
@@ -14,7 +14,7 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17#include "ath9k.h" 17#include "hw.h"
18 18
19static inline u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz) 19static inline u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz)
20{ 20{
@@ -83,11 +83,9 @@ bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize,
83 return false; 83 return false;
84} 84}
85 85
86bool ath9k_hw_nvram_read(struct ath_hw *ah, u32 off, u16 *data) 86bool ath9k_hw_nvram_read(struct ath_common *common, u32 off, u16 *data)
87{ 87{
88 struct ath_softc *sc = ah->ah_sc; 88 return common->bus_ops->eeprom_read(common, off, data);
89
90 return sc->bus_ops->eeprom_read(ah, off, data);
91} 89}
92 90
93void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList, 91void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
diff --git a/drivers/net/wireless/ath/ath9k/eeprom.h b/drivers/net/wireless/ath/ath9k/eeprom.h
index 4fe33f7eee9d..2f2993b50e2f 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom.h
+++ b/drivers/net/wireless/ath/ath9k/eeprom.h
@@ -17,6 +17,7 @@
17#ifndef EEPROM_H 17#ifndef EEPROM_H
18#define EEPROM_H 18#define EEPROM_H
19 19
20#include "../ath.h"
20#include <net/cfg80211.h> 21#include <net/cfg80211.h>
21 22
22#define AH_USE_EEPROM 0x1 23#define AH_USE_EEPROM 0x1
@@ -133,6 +134,7 @@
133#define AR5416_EEP_MINOR_VER_17 0x11 134#define AR5416_EEP_MINOR_VER_17 0x11
134#define AR5416_EEP_MINOR_VER_19 0x13 135#define AR5416_EEP_MINOR_VER_19 0x13
135#define AR5416_EEP_MINOR_VER_20 0x14 136#define AR5416_EEP_MINOR_VER_20 0x14
137#define AR5416_EEP_MINOR_VER_21 0x15
136#define AR5416_EEP_MINOR_VER_22 0x16 138#define AR5416_EEP_MINOR_VER_22 0x16
137 139
138#define AR5416_NUM_5G_CAL_PIERS 8 140#define AR5416_NUM_5G_CAL_PIERS 8
@@ -153,7 +155,7 @@
153#define AR5416_BCHAN_UNUSED 0xFF 155#define AR5416_BCHAN_UNUSED 0xFF
154#define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64 156#define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
155#define AR5416_MAX_CHAINS 3 157#define AR5416_MAX_CHAINS 3
156#define AR5416_PWR_TABLE_OFFSET -5 158#define AR5416_PWR_TABLE_OFFSET_DB -5
157 159
158/* Rx gain type values */ 160/* Rx gain type values */
159#define AR5416_EEP_RXGAIN_23DB_BACKOFF 0 161#define AR5416_EEP_RXGAIN_23DB_BACKOFF 0
@@ -301,7 +303,7 @@ struct base_eep_header {
301 u8 txGainType; 303 u8 txGainType;
302 u8 rcChainMask; 304 u8 rcChainMask;
303 u8 desiredScaleCCK; 305 u8 desiredScaleCCK;
304 u8 power_table_offset; 306 u8 pwr_table_offset;
305 u8 frac_n_5g; 307 u8 frac_n_5g;
306 u8 futureBase_3[21]; 308 u8 futureBase_3[21];
307} __packed; 309} __packed;
@@ -638,6 +640,7 @@ struct ar9287_eeprom {
638} __packed; 640} __packed;
639 641
640enum reg_ext_bitmap { 642enum reg_ext_bitmap {
643 REG_EXT_FCC_MIDBAND = 0,
641 REG_EXT_JAPAN_MIDBAND = 1, 644 REG_EXT_JAPAN_MIDBAND = 1,
642 REG_EXT_FCC_DFS_HT40 = 2, 645 REG_EXT_FCC_DFS_HT40 = 2,
643 REG_EXT_JAPAN_NONDFS_HT40 = 3, 646 REG_EXT_JAPAN_NONDFS_HT40 = 3,
@@ -684,7 +687,7 @@ int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight,
684 int16_t targetRight); 687 int16_t targetRight);
685bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize, 688bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize,
686 u16 *indexL, u16 *indexR); 689 u16 *indexL, u16 *indexR);
687bool ath9k_hw_nvram_read(struct ath_hw *ah, u32 off, u16 *data); 690bool ath9k_hw_nvram_read(struct ath_common *common, u32 off, u16 *data);
688void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList, 691void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
689 u8 *pVpdList, u16 numIntercepts, 692 u8 *pVpdList, u16 numIntercepts,
690 u8 *pRetVpdList); 693 u8 *pRetVpdList);
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_4k.c b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
index b8eca7be5f3a..68db16690abf 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_4k.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
@@ -14,7 +14,7 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17#include "ath9k.h" 17#include "hw.h"
18 18
19static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah) 19static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah)
20{ 20{
@@ -29,20 +29,21 @@ static int ath9k_hw_4k_get_eeprom_rev(struct ath_hw *ah)
29static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah) 29static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
30{ 30{
31#define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16)) 31#define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
32 struct ath_common *common = ath9k_hw_common(ah);
32 u16 *eep_data = (u16 *)&ah->eeprom.map4k; 33 u16 *eep_data = (u16 *)&ah->eeprom.map4k;
33 int addr, eep_start_loc = 0; 34 int addr, eep_start_loc = 0;
34 35
35 eep_start_loc = 64; 36 eep_start_loc = 64;
36 37
37 if (!ath9k_hw_use_flash(ah)) { 38 if (!ath9k_hw_use_flash(ah)) {
38 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 39 ath_print(common, ATH_DBG_EEPROM,
39 "Reading from EEPROM, not flash\n"); 40 "Reading from EEPROM, not flash\n");
40 } 41 }
41 42
42 for (addr = 0; addr < SIZE_EEPROM_4K; addr++) { 43 for (addr = 0; addr < SIZE_EEPROM_4K; addr++) {
43 if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data)) { 44 if (!ath9k_hw_nvram_read(common, addr + eep_start_loc, eep_data)) {
44 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 45 ath_print(common, ATH_DBG_EEPROM,
45 "Unable to read eeprom region \n"); 46 "Unable to read eeprom region \n");
46 return false; 47 return false;
47 } 48 }
48 eep_data++; 49 eep_data++;
@@ -55,6 +56,7 @@ static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
55static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah) 56static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
56{ 57{
57#define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16)) 58#define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
59 struct ath_common *common = ath9k_hw_common(ah);
58 struct ar5416_eeprom_4k *eep = 60 struct ar5416_eeprom_4k *eep =
59 (struct ar5416_eeprom_4k *) &ah->eeprom.map4k; 61 (struct ar5416_eeprom_4k *) &ah->eeprom.map4k;
60 u16 *eepdata, temp, magic, magic2; 62 u16 *eepdata, temp, magic, magic2;
@@ -64,15 +66,15 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
64 66
65 67
66 if (!ath9k_hw_use_flash(ah)) { 68 if (!ath9k_hw_use_flash(ah)) {
67 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET, 69 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET,
68 &magic)) { 70 &magic)) {
69 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 71 ath_print(common, ATH_DBG_FATAL,
70 "Reading Magic # failed\n"); 72 "Reading Magic # failed\n");
71 return false; 73 return false;
72 } 74 }
73 75
74 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 76 ath_print(common, ATH_DBG_EEPROM,
75 "Read Magic = 0x%04X\n", magic); 77 "Read Magic = 0x%04X\n", magic);
76 78
77 if (magic != AR5416_EEPROM_MAGIC) { 79 if (magic != AR5416_EEPROM_MAGIC) {
78 magic2 = swab16(magic); 80 magic2 = swab16(magic);
@@ -87,16 +89,16 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
87 eepdata++; 89 eepdata++;
88 } 90 }
89 } else { 91 } else {
90 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 92 ath_print(common, ATH_DBG_FATAL,
91 "Invalid EEPROM Magic. " 93 "Invalid EEPROM Magic. "
92 "endianness mismatch.\n"); 94 "endianness mismatch.\n");
93 return -EINVAL; 95 return -EINVAL;
94 } 96 }
95 } 97 }
96 } 98 }
97 99
98 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n", 100 ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
99 need_swap ? "True" : "False"); 101 need_swap ? "True" : "False");
100 102
101 if (need_swap) 103 if (need_swap)
102 el = swab16(ah->eeprom.map4k.baseEepHeader.length); 104 el = swab16(ah->eeprom.map4k.baseEepHeader.length);
@@ -117,8 +119,8 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
117 u32 integer; 119 u32 integer;
118 u16 word; 120 u16 word;
119 121
120 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 122 ath_print(common, ATH_DBG_EEPROM,
121 "EEPROM Endianness is not native.. Changing\n"); 123 "EEPROM Endianness is not native.. Changing\n");
122 124
123 word = swab16(eep->baseEepHeader.length); 125 word = swab16(eep->baseEepHeader.length);
124 eep->baseEepHeader.length = word; 126 eep->baseEepHeader.length = word;
@@ -160,9 +162,9 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
160 162
161 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER || 163 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
162 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) { 164 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
163 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 165 ath_print(common, ATH_DBG_FATAL,
164 "Bad EEPROM checksum 0x%x or revision 0x%04x\n", 166 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
165 sum, ah->eep_ops->get_eeprom_ver(ah)); 167 sum, ah->eep_ops->get_eeprom_ver(ah));
166 return -EINVAL; 168 return -EINVAL;
167 } 169 }
168 170
@@ -208,6 +210,8 @@ static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
208 return pBase->rxMask; 210 return pBase->rxMask;
209 case EEP_FRAC_N_5G: 211 case EEP_FRAC_N_5G:
210 return 0; 212 return 0;
213 case EEP_PWR_TABLE_OFFSET:
214 return AR5416_PWR_TABLE_OFFSET_DB;
211 default: 215 default:
212 return 0; 216 return 0;
213 } 217 }
@@ -385,6 +389,7 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
385 struct ath9k_channel *chan, 389 struct ath9k_channel *chan,
386 int16_t *pTxPowerIndexOffset) 390 int16_t *pTxPowerIndexOffset)
387{ 391{
392 struct ath_common *common = ath9k_hw_common(ah);
388 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k; 393 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
389 struct cal_data_per_freq_4k *pRawDataset; 394 struct cal_data_per_freq_4k *pRawDataset;
390 u8 *pCalBChans = NULL; 395 u8 *pCalBChans = NULL;
@@ -470,21 +475,21 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
470 ((pdadcValues[4 * j + 3] & 0xFF) << 24); 475 ((pdadcValues[4 * j + 3] & 0xFF) << 24);
471 REG_WRITE(ah, regOffset, reg32); 476 REG_WRITE(ah, regOffset, reg32);
472 477
473 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 478 ath_print(common, ATH_DBG_EEPROM,
474 "PDADC (%d,%4x): %4.4x %8.8x\n", 479 "PDADC (%d,%4x): %4.4x %8.8x\n",
475 i, regChainOffset, regOffset, 480 i, regChainOffset, regOffset,
476 reg32); 481 reg32);
477 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 482 ath_print(common, ATH_DBG_EEPROM,
478 "PDADC: Chain %d | " 483 "PDADC: Chain %d | "
479 "PDADC %3d Value %3d | " 484 "PDADC %3d Value %3d | "
480 "PDADC %3d Value %3d | " 485 "PDADC %3d Value %3d | "
481 "PDADC %3d Value %3d | " 486 "PDADC %3d Value %3d | "
482 "PDADC %3d Value %3d |\n", 487 "PDADC %3d Value %3d |\n",
483 i, 4 * j, pdadcValues[4 * j], 488 i, 4 * j, pdadcValues[4 * j],
484 4 * j + 1, pdadcValues[4 * j + 1], 489 4 * j + 1, pdadcValues[4 * j + 1],
485 4 * j + 2, pdadcValues[4 * j + 2], 490 4 * j + 2, pdadcValues[4 * j + 2],
486 4 * j + 3, 491 4 * j + 3,
487 pdadcValues[4 * j + 3]); 492 pdadcValues[4 * j + 3]);
488 493
489 regOffset += 4; 494 regOffset += 4;
490 } 495 }
@@ -750,7 +755,7 @@ static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
750 755
751 if (AR_SREV_9280_10_OR_LATER(ah)) { 756 if (AR_SREV_9280_10_OR_LATER(ah)) {
752 for (i = 0; i < Ar5416RateSize; i++) 757 for (i = 0; i < Ar5416RateSize; i++)
753 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2; 758 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2;
754 } 759 }
755 760
756 /* OFDM power per rate */ 761 /* OFDM power per rate */
@@ -1107,6 +1112,10 @@ static void ath9k_hw_4k_set_board_values(struct ath_hw *ah,
1107 1112
1108 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, 1113 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
1109 pModal->txEndToRxOn); 1114 pModal->txEndToRxOn);
1115
1116 if (AR_SREV_9271_10(ah))
1117 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
1118 pModal->txEndToRxOn);
1110 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62, 1119 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
1111 pModal->thresh62); 1120 pModal->thresh62);
1112 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62, 1121 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,
@@ -1148,20 +1157,21 @@ static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1148{ 1157{
1149#define EEP_MAP4K_SPURCHAN \ 1158#define EEP_MAP4K_SPURCHAN \
1150 (ah->eeprom.map4k.modalHeader.spurChans[i].spurChan) 1159 (ah->eeprom.map4k.modalHeader.spurChans[i].spurChan)
1160 struct ath_common *common = ath9k_hw_common(ah);
1151 1161
1152 u16 spur_val = AR_NO_SPUR; 1162 u16 spur_val = AR_NO_SPUR;
1153 1163
1154 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 1164 ath_print(common, ATH_DBG_ANI,
1155 "Getting spur idx %d is2Ghz. %d val %x\n", 1165 "Getting spur idx %d is2Ghz. %d val %x\n",
1156 i, is2GHz, ah->config.spurchans[i][is2GHz]); 1166 i, is2GHz, ah->config.spurchans[i][is2GHz]);
1157 1167
1158 switch (ah->config.spurmode) { 1168 switch (ah->config.spurmode) {
1159 case SPUR_DISABLE: 1169 case SPUR_DISABLE:
1160 break; 1170 break;
1161 case SPUR_ENABLE_IOCTL: 1171 case SPUR_ENABLE_IOCTL:
1162 spur_val = ah->config.spurchans[i][is2GHz]; 1172 spur_val = ah->config.spurchans[i][is2GHz];
1163 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 1173 ath_print(common, ATH_DBG_ANI,
1164 "Getting spur val from new loc. %d\n", spur_val); 1174 "Getting spur val from new loc. %d\n", spur_val);
1165 break; 1175 break;
1166 case SPUR_ENABLE_EEPROM: 1176 case SPUR_ENABLE_EEPROM:
1167 spur_val = EEP_MAP4K_SPURCHAN; 1177 spur_val = EEP_MAP4K_SPURCHAN;
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_9287.c b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
index c20c21a79b21..839d05a1df29 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_9287.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
@@ -14,7 +14,7 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17#include "ath9k.h" 17#include "hw.h"
18 18
19static int ath9k_hw_AR9287_get_eeprom_ver(struct ath_hw *ah) 19static int ath9k_hw_AR9287_get_eeprom_ver(struct ath_hw *ah)
20{ 20{
@@ -29,20 +29,22 @@ static int ath9k_hw_AR9287_get_eeprom_rev(struct ath_hw *ah)
29static bool ath9k_hw_AR9287_fill_eeprom(struct ath_hw *ah) 29static bool ath9k_hw_AR9287_fill_eeprom(struct ath_hw *ah)
30{ 30{
31 struct ar9287_eeprom *eep = &ah->eeprom.map9287; 31 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
32 struct ath_common *common = ath9k_hw_common(ah);
32 u16 *eep_data; 33 u16 *eep_data;
33 int addr, eep_start_loc = AR9287_EEP_START_LOC; 34 int addr, eep_start_loc = AR9287_EEP_START_LOC;
34 eep_data = (u16 *)eep; 35 eep_data = (u16 *)eep;
35 36
36 if (!ath9k_hw_use_flash(ah)) { 37 if (!ath9k_hw_use_flash(ah)) {
37 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 38 ath_print(common, ATH_DBG_EEPROM,
38 "Reading from EEPROM, not flash\n"); 39 "Reading from EEPROM, not flash\n");
39 } 40 }
40 41
41 for (addr = 0; addr < sizeof(struct ar9287_eeprom) / sizeof(u16); 42 for (addr = 0; addr < sizeof(struct ar9287_eeprom) / sizeof(u16);
42 addr++) { 43 addr++) {
43 if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data)) { 44 if (!ath9k_hw_nvram_read(common,
44 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 45 addr + eep_start_loc, eep_data)) {
45 "Unable to read eeprom region \n"); 46 ath_print(common, ATH_DBG_EEPROM,
47 "Unable to read eeprom region \n");
46 return false; 48 return false;
47 } 49 }
48 eep_data++; 50 eep_data++;
@@ -57,17 +59,18 @@ static int ath9k_hw_AR9287_check_eeprom(struct ath_hw *ah)
57 int i, addr; 59 int i, addr;
58 bool need_swap = false; 60 bool need_swap = false;
59 struct ar9287_eeprom *eep = &ah->eeprom.map9287; 61 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
62 struct ath_common *common = ath9k_hw_common(ah);
60 63
61 if (!ath9k_hw_use_flash(ah)) { 64 if (!ath9k_hw_use_flash(ah)) {
62 if (!ath9k_hw_nvram_read 65 if (!ath9k_hw_nvram_read(common,
63 (ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) { 66 AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
64 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 67 ath_print(common, ATH_DBG_FATAL,
65 "Reading Magic # failed\n"); 68 "Reading Magic # failed\n");
66 return false; 69 return false;
67 } 70 }
68 71
69 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 72 ath_print(common, ATH_DBG_EEPROM,
70 "Read Magic = 0x%04X\n", magic); 73 "Read Magic = 0x%04X\n", magic);
71 if (magic != AR5416_EEPROM_MAGIC) { 74 if (magic != AR5416_EEPROM_MAGIC) {
72 magic2 = swab16(magic); 75 magic2 = swab16(magic);
73 76
@@ -83,15 +86,15 @@ static int ath9k_hw_AR9287_check_eeprom(struct ath_hw *ah)
83 eepdata++; 86 eepdata++;
84 } 87 }
85 } else { 88 } else {
86 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 89 ath_print(common, ATH_DBG_FATAL,
87 "Invalid EEPROM Magic. " 90 "Invalid EEPROM Magic. "
88 "endianness mismatch.\n"); 91 "endianness mismatch.\n");
89 return -EINVAL; 92 return -EINVAL;
90 } 93 }
91 } 94 }
92 } 95 }
93 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n", need_swap ? 96 ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n", need_swap ?
94 "True" : "False"); 97 "True" : "False");
95 98
96 if (need_swap) 99 if (need_swap)
97 el = swab16(ah->eeprom.map9287.baseEepHeader.length); 100 el = swab16(ah->eeprom.map9287.baseEepHeader.length);
@@ -148,9 +151,9 @@ static int ath9k_hw_AR9287_check_eeprom(struct ath_hw *ah)
148 151
149 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR9287_EEP_VER 152 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR9287_EEP_VER
150 || ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) { 153 || ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
151 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 154 ath_print(common, ATH_DBG_FATAL,
152 "Bad EEPROM checksum 0x%x or revision 0x%04x\n", 155 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
153 sum, ah->eep_ops->get_eeprom_ver(ah)); 156 sum, ah->eep_ops->get_eeprom_ver(ah));
154 return -EINVAL; 157 return -EINVAL;
155 } 158 }
156 159
@@ -436,6 +439,7 @@ static void ath9k_hw_set_AR9287_power_cal_table(struct ath_hw *ah,
436 struct ath9k_channel *chan, 439 struct ath9k_channel *chan,
437 int16_t *pTxPowerIndexOffset) 440 int16_t *pTxPowerIndexOffset)
438{ 441{
442 struct ath_common *common = ath9k_hw_common(ah);
439 struct cal_data_per_freq_ar9287 *pRawDataset; 443 struct cal_data_per_freq_ar9287 *pRawDataset;
440 struct cal_data_op_loop_ar9287 *pRawDatasetOpenLoop; 444 struct cal_data_op_loop_ar9287 *pRawDatasetOpenLoop;
441 u8 *pCalBChans = NULL; 445 u8 *pCalBChans = NULL;
@@ -564,24 +568,25 @@ static void ath9k_hw_set_AR9287_power_cal_table(struct ath_hw *ah,
564 & 0xFF) << 24) ; 568 & 0xFF) << 24) ;
565 REG_WRITE(ah, regOffset, reg32); 569 REG_WRITE(ah, regOffset, reg32);
566 570
567 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 571 ath_print(common, ATH_DBG_EEPROM,
568 "PDADC (%d,%4x): %4.4x %8.8x\n", 572 "PDADC (%d,%4x): %4.4x "
569 i, regChainOffset, regOffset, 573 "%8.8x\n",
570 reg32); 574 i, regChainOffset, regOffset,
571 575 reg32);
572 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 576
573 "PDADC: Chain %d | " 577 ath_print(common, ATH_DBG_EEPROM,
574 "PDADC %3d Value %3d | " 578 "PDADC: Chain %d | "
575 "PDADC %3d Value %3d | " 579 "PDADC %3d Value %3d | "
576 "PDADC %3d Value %3d | " 580 "PDADC %3d Value %3d | "
577 "PDADC %3d Value %3d |\n", 581 "PDADC %3d Value %3d | "
578 i, 4 * j, pdadcValues[4 * j], 582 "PDADC %3d Value %3d |\n",
579 4 * j + 1, 583 i, 4 * j, pdadcValues[4 * j],
580 pdadcValues[4 * j + 1], 584 4 * j + 1,
581 4 * j + 2, 585 pdadcValues[4 * j + 1],
582 pdadcValues[4 * j + 2], 586 4 * j + 2,
583 4 * j + 3, 587 pdadcValues[4 * j + 2],
584 pdadcValues[4 * j + 3]); 588 4 * j + 3,
589 pdadcValues[4 * j + 3]);
585 590
586 regOffset += 4; 591 regOffset += 4;
587 } 592 }
@@ -831,6 +836,7 @@ static void ath9k_hw_AR9287_set_txpower(struct ath_hw *ah,
831{ 836{
832#define INCREASE_MAXPOW_BY_TWO_CHAIN 6 837#define INCREASE_MAXPOW_BY_TWO_CHAIN 6
833#define INCREASE_MAXPOW_BY_THREE_CHAIN 10 838#define INCREASE_MAXPOW_BY_THREE_CHAIN 10
839 struct ath_common *common = ath9k_hw_common(ah);
834 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 840 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
835 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287; 841 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
836 struct modal_eep_ar9287_header *pModal = &pEepData->modalHeader; 842 struct modal_eep_ar9287_header *pModal = &pEepData->modalHeader;
@@ -966,8 +972,8 @@ static void ath9k_hw_AR9287_set_txpower(struct ath_hw *ah,
966 INCREASE_MAXPOW_BY_THREE_CHAIN; 972 INCREASE_MAXPOW_BY_THREE_CHAIN;
967 break; 973 break;
968 default: 974 default:
969 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 975 ath_print(common, ATH_DBG_EEPROM,
970 "Invalid chainmask configuration\n"); 976 "Invalid chainmask configuration\n");
971 break; 977 break;
972 } 978 }
973} 979}
@@ -1138,19 +1144,20 @@ static u16 ath9k_hw_AR9287_get_spur_channel(struct ath_hw *ah,
1138{ 1144{
1139#define EEP_MAP9287_SPURCHAN \ 1145#define EEP_MAP9287_SPURCHAN \
1140 (ah->eeprom.map9287.modalHeader.spurChans[i].spurChan) 1146 (ah->eeprom.map9287.modalHeader.spurChans[i].spurChan)
1147 struct ath_common *common = ath9k_hw_common(ah);
1141 u16 spur_val = AR_NO_SPUR; 1148 u16 spur_val = AR_NO_SPUR;
1142 1149
1143 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 1150 ath_print(common, ATH_DBG_ANI,
1144 "Getting spur idx %d is2Ghz. %d val %x\n", 1151 "Getting spur idx %d is2Ghz. %d val %x\n",
1145 i, is2GHz, ah->config.spurchans[i][is2GHz]); 1152 i, is2GHz, ah->config.spurchans[i][is2GHz]);
1146 1153
1147 switch (ah->config.spurmode) { 1154 switch (ah->config.spurmode) {
1148 case SPUR_DISABLE: 1155 case SPUR_DISABLE:
1149 break; 1156 break;
1150 case SPUR_ENABLE_IOCTL: 1157 case SPUR_ENABLE_IOCTL:
1151 spur_val = ah->config.spurchans[i][is2GHz]; 1158 spur_val = ah->config.spurchans[i][is2GHz];
1152 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 1159 ath_print(common, ATH_DBG_ANI,
1153 "Getting spur val from new loc. %d\n", spur_val); 1160 "Getting spur val from new loc. %d\n", spur_val);
1154 break; 1161 break;
1155 case SPUR_ENABLE_EEPROM: 1162 case SPUR_ENABLE_EEPROM:
1156 spur_val = EEP_MAP9287_SPURCHAN; 1163 spur_val = EEP_MAP9287_SPURCHAN;
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_def.c b/drivers/net/wireless/ath/ath9k/eeprom_def.c
index 4071fc91da0a..404a0341242c 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_def.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_def.c
@@ -14,7 +14,7 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17#include "ath9k.h" 17#include "hw.h"
18 18
19static void ath9k_get_txgain_index(struct ath_hw *ah, 19static void ath9k_get_txgain_index(struct ath_hw *ah,
20 struct ath9k_channel *chan, 20 struct ath9k_channel *chan,
@@ -89,14 +89,15 @@ static int ath9k_hw_def_get_eeprom_rev(struct ath_hw *ah)
89static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah) 89static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
90{ 90{
91#define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16)) 91#define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16))
92 struct ath_common *common = ath9k_hw_common(ah);
92 u16 *eep_data = (u16 *)&ah->eeprom.def; 93 u16 *eep_data = (u16 *)&ah->eeprom.def;
93 int addr, ar5416_eep_start_loc = 0x100; 94 int addr, ar5416_eep_start_loc = 0x100;
94 95
95 for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) { 96 for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) {
96 if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc, 97 if (!ath9k_hw_nvram_read(common, addr + ar5416_eep_start_loc,
97 eep_data)) { 98 eep_data)) {
98 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 99 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
99 "Unable to read eeprom region\n"); 100 "Unable to read eeprom region\n");
100 return false; 101 return false;
101 } 102 }
102 eep_data++; 103 eep_data++;
@@ -109,19 +110,20 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
109{ 110{
110 struct ar5416_eeprom_def *eep = 111 struct ar5416_eeprom_def *eep =
111 (struct ar5416_eeprom_def *) &ah->eeprom.def; 112 (struct ar5416_eeprom_def *) &ah->eeprom.def;
113 struct ath_common *common = ath9k_hw_common(ah);
112 u16 *eepdata, temp, magic, magic2; 114 u16 *eepdata, temp, magic, magic2;
113 u32 sum = 0, el; 115 u32 sum = 0, el;
114 bool need_swap = false; 116 bool need_swap = false;
115 int i, addr, size; 117 int i, addr, size;
116 118
117 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) { 119 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
118 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Reading Magic # failed\n"); 120 ath_print(common, ATH_DBG_FATAL, "Reading Magic # failed\n");
119 return false; 121 return false;
120 } 122 }
121 123
122 if (!ath9k_hw_use_flash(ah)) { 124 if (!ath9k_hw_use_flash(ah)) {
123 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 125 ath_print(common, ATH_DBG_EEPROM,
124 "Read Magic = 0x%04X\n", magic); 126 "Read Magic = 0x%04X\n", magic);
125 127
126 if (magic != AR5416_EEPROM_MAGIC) { 128 if (magic != AR5416_EEPROM_MAGIC) {
127 magic2 = swab16(magic); 129 magic2 = swab16(magic);
@@ -137,16 +139,16 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
137 eepdata++; 139 eepdata++;
138 } 140 }
139 } else { 141 } else {
140 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 142 ath_print(common, ATH_DBG_FATAL,
141 "Invalid EEPROM Magic. " 143 "Invalid EEPROM Magic. "
142 "Endianness mismatch.\n"); 144 "Endianness mismatch.\n");
143 return -EINVAL; 145 return -EINVAL;
144 } 146 }
145 } 147 }
146 } 148 }
147 149
148 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n", 150 ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
149 need_swap ? "True" : "False"); 151 need_swap ? "True" : "False");
150 152
151 if (need_swap) 153 if (need_swap)
152 el = swab16(ah->eeprom.def.baseEepHeader.length); 154 el = swab16(ah->eeprom.def.baseEepHeader.length);
@@ -167,8 +169,8 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
167 u32 integer, j; 169 u32 integer, j;
168 u16 word; 170 u16 word;
169 171
170 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 172 ath_print(common, ATH_DBG_EEPROM,
171 "EEPROM Endianness is not native.. Changing.\n"); 173 "EEPROM Endianness is not native.. Changing.\n");
172 174
173 word = swab16(eep->baseEepHeader.length); 175 word = swab16(eep->baseEepHeader.length);
174 eep->baseEepHeader.length = word; 176 eep->baseEepHeader.length = word;
@@ -214,8 +216,8 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
214 216
215 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER || 217 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
216 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) { 218 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
217 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 219 ath_print(common, ATH_DBG_FATAL,
218 "Bad EEPROM checksum 0x%x or revision 0x%04x\n", 220 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
219 sum, ah->eep_ops->get_eeprom_ver(ah)); 221 sum, ah->eep_ops->get_eeprom_ver(ah));
220 return -EINVAL; 222 return -EINVAL;
221 } 223 }
@@ -289,6 +291,11 @@ static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
289 return pBase->frac_n_5g; 291 return pBase->frac_n_5g;
290 else 292 else
291 return 0; 293 return 0;
294 case EEP_PWR_TABLE_OFFSET:
295 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_21)
296 return pBase->pwr_table_offset;
297 else
298 return AR5416_PWR_TABLE_OFFSET_DB;
292 default: 299 default:
293 return 0; 300 return 0;
294 } 301 }
@@ -739,6 +746,76 @@ static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hw *ah,
739 return; 746 return;
740} 747}
741 748
749static int16_t ath9k_change_gain_boundary_setting(struct ath_hw *ah,
750 u16 *gb,
751 u16 numXpdGain,
752 u16 pdGainOverlap_t2,
753 int8_t pwr_table_offset,
754 int16_t *diff)
755
756{
757 u16 k;
758
759 /* Prior to writing the boundaries or the pdadc vs. power table
760 * into the chip registers the default starting point on the pdadc
761 * vs. power table needs to be checked and the curve boundaries
762 * adjusted accordingly
763 */
764 if (AR_SREV_9280_20_OR_LATER(ah)) {
765 u16 gb_limit;
766
767 if (AR5416_PWR_TABLE_OFFSET_DB != pwr_table_offset) {
768 /* get the difference in dB */
769 *diff = (u16)(pwr_table_offset - AR5416_PWR_TABLE_OFFSET_DB);
770 /* get the number of half dB steps */
771 *diff *= 2;
772 /* change the original gain boundary settings
773 * by the number of half dB steps
774 */
775 for (k = 0; k < numXpdGain; k++)
776 gb[k] = (u16)(gb[k] - *diff);
777 }
778 /* Because of a hardware limitation, ensure the gain boundary
779 * is not larger than (63 - overlap)
780 */
781 gb_limit = (u16)(AR5416_MAX_RATE_POWER - pdGainOverlap_t2);
782
783 for (k = 0; k < numXpdGain; k++)
784 gb[k] = (u16)min(gb_limit, gb[k]);
785 }
786
787 return *diff;
788}
789
790static void ath9k_adjust_pdadc_values(struct ath_hw *ah,
791 int8_t pwr_table_offset,
792 int16_t diff,
793 u8 *pdadcValues)
794{
795#define NUM_PDADC(diff) (AR5416_NUM_PDADC_VALUES - diff)
796 u16 k;
797
798 /* If this is a board that has a pwrTableOffset that differs from
799 * the default AR5416_PWR_TABLE_OFFSET_DB then the start of the
800 * pdadc vs pwr table needs to be adjusted prior to writing to the
801 * chip.
802 */
803 if (AR_SREV_9280_20_OR_LATER(ah)) {
804 if (AR5416_PWR_TABLE_OFFSET_DB != pwr_table_offset) {
805 /* shift the table to start at the new offset */
806 for (k = 0; k < (u16)NUM_PDADC(diff); k++ ) {
807 pdadcValues[k] = pdadcValues[k + diff];
808 }
809
810 /* fill the back of the table */
811 for (k = (u16)NUM_PDADC(diff); k < NUM_PDADC(0); k++) {
812 pdadcValues[k] = pdadcValues[NUM_PDADC(diff)];
813 }
814 }
815 }
816#undef NUM_PDADC
817}
818
742static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah, 819static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
743 struct ath9k_channel *chan, 820 struct ath9k_channel *chan,
744 int16_t *pTxPowerIndexOffset) 821 int16_t *pTxPowerIndexOffset)
@@ -746,7 +823,7 @@ static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
746#define SM_PD_GAIN(x) SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##x) 823#define SM_PD_GAIN(x) SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##x)
747#define SM_PDGAIN_B(x, y) \ 824#define SM_PDGAIN_B(x, y) \
748 SM((gainBoundaries[x]), AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##y) 825 SM((gainBoundaries[x]), AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##y)
749 826 struct ath_common *common = ath9k_hw_common(ah);
750 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def; 827 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
751 struct cal_data_per_freq *pRawDataset; 828 struct cal_data_per_freq *pRawDataset;
752 u8 *pCalBChans = NULL; 829 u8 *pCalBChans = NULL;
@@ -754,15 +831,18 @@ static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
754 static u8 pdadcValues[AR5416_NUM_PDADC_VALUES]; 831 static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
755 u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK]; 832 u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
756 u16 numPiers, i, j; 833 u16 numPiers, i, j;
757 int16_t tMinCalPower; 834 int16_t tMinCalPower, diff = 0;
758 u16 numXpdGain, xpdMask; 835 u16 numXpdGain, xpdMask;
759 u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 }; 836 u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
760 u32 reg32, regOffset, regChainOffset; 837 u32 reg32, regOffset, regChainOffset;
761 int16_t modalIdx; 838 int16_t modalIdx;
839 int8_t pwr_table_offset;
762 840
763 modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0; 841 modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
764 xpdMask = pEepData->modalHeader[modalIdx].xpdGain; 842 xpdMask = pEepData->modalHeader[modalIdx].xpdGain;
765 843
844 pwr_table_offset = ah->eep_ops->get_eeprom(ah, EEP_PWR_TABLE_OFFSET);
845
766 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= 846 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
767 AR5416_EEP_MINOR_VER_2) { 847 AR5416_EEP_MINOR_VER_2) {
768 pdGainOverlap_t2 = 848 pdGainOverlap_t2 =
@@ -842,6 +922,13 @@ static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
842 numXpdGain); 922 numXpdGain);
843 } 923 }
844 924
925 diff = ath9k_change_gain_boundary_setting(ah,
926 gainBoundaries,
927 numXpdGain,
928 pdGainOverlap_t2,
929 pwr_table_offset,
930 &diff);
931
845 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) { 932 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
846 if (OLC_FOR_AR9280_20_LATER) { 933 if (OLC_FOR_AR9280_20_LATER) {
847 REG_WRITE(ah, 934 REG_WRITE(ah,
@@ -862,6 +949,10 @@ static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
862 } 949 }
863 } 950 }
864 951
952
953 ath9k_adjust_pdadc_values(ah, pwr_table_offset,
954 diff, pdadcValues);
955
865 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset; 956 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
866 for (j = 0; j < 32; j++) { 957 for (j = 0; j < 32; j++) {
867 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) | 958 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) |
@@ -870,20 +961,20 @@ static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
870 ((pdadcValues[4 * j + 3] & 0xFF) << 24); 961 ((pdadcValues[4 * j + 3] & 0xFF) << 24);
871 REG_WRITE(ah, regOffset, reg32); 962 REG_WRITE(ah, regOffset, reg32);
872 963
873 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 964 ath_print(common, ATH_DBG_EEPROM,
874 "PDADC (%d,%4x): %4.4x %8.8x\n", 965 "PDADC (%d,%4x): %4.4x %8.8x\n",
875 i, regChainOffset, regOffset, 966 i, regChainOffset, regOffset,
876 reg32); 967 reg32);
877 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 968 ath_print(common, ATH_DBG_EEPROM,
878 "PDADC: Chain %d | PDADC %3d " 969 "PDADC: Chain %d | PDADC %3d "
879 "Value %3d | PDADC %3d Value %3d | " 970 "Value %3d | PDADC %3d Value %3d | "
880 "PDADC %3d Value %3d | PDADC %3d " 971 "PDADC %3d Value %3d | PDADC %3d "
881 "Value %3d |\n", 972 "Value %3d |\n",
882 i, 4 * j, pdadcValues[4 * j], 973 i, 4 * j, pdadcValues[4 * j],
883 4 * j + 1, pdadcValues[4 * j + 1], 974 4 * j + 1, pdadcValues[4 * j + 1],
884 4 * j + 2, pdadcValues[4 * j + 2], 975 4 * j + 2, pdadcValues[4 * j + 2],
885 4 * j + 3, 976 4 * j + 3,
886 pdadcValues[4 * j + 3]); 977 pdadcValues[4 * j + 3]);
887 978
888 regOffset += 4; 979 regOffset += 4;
889 } 980 }
@@ -1197,8 +1288,13 @@ static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
1197 } 1288 }
1198 1289
1199 if (AR_SREV_9280_10_OR_LATER(ah)) { 1290 if (AR_SREV_9280_10_OR_LATER(ah)) {
1200 for (i = 0; i < Ar5416RateSize; i++) 1291 for (i = 0; i < Ar5416RateSize; i++) {
1201 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2; 1292 int8_t pwr_table_offset;
1293
1294 pwr_table_offset = ah->eep_ops->get_eeprom(ah,
1295 EEP_PWR_TABLE_OFFSET);
1296 ratesArray[i] -= pwr_table_offset * 2;
1297 }
1202 } 1298 }
1203 1299
1204 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, 1300 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
@@ -1297,7 +1393,7 @@ static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
1297 1393
1298 if (AR_SREV_9280_10_OR_LATER(ah)) 1394 if (AR_SREV_9280_10_OR_LATER(ah))
1299 regulatory->max_power_level = 1395 regulatory->max_power_level =
1300 ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2; 1396 ratesArray[i] + AR5416_PWR_TABLE_OFFSET_DB * 2;
1301 else 1397 else
1302 regulatory->max_power_level = ratesArray[i]; 1398 regulatory->max_power_level = ratesArray[i];
1303 1399
@@ -1311,8 +1407,8 @@ static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
1311 regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN; 1407 regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
1312 break; 1408 break;
1313 default: 1409 default:
1314 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 1410 ath_print(ath9k_hw_common(ah), ATH_DBG_EEPROM,
1315 "Invalid chainmask configuration\n"); 1411 "Invalid chainmask configuration\n");
1316 break; 1412 break;
1317 } 1413 }
1318} 1414}
@@ -1349,20 +1445,21 @@ static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1349{ 1445{
1350#define EEP_DEF_SPURCHAN \ 1446#define EEP_DEF_SPURCHAN \
1351 (ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan) 1447 (ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan)
1448 struct ath_common *common = ath9k_hw_common(ah);
1352 1449
1353 u16 spur_val = AR_NO_SPUR; 1450 u16 spur_val = AR_NO_SPUR;
1354 1451
1355 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 1452 ath_print(common, ATH_DBG_ANI,
1356 "Getting spur idx %d is2Ghz. %d val %x\n", 1453 "Getting spur idx %d is2Ghz. %d val %x\n",
1357 i, is2GHz, ah->config.spurchans[i][is2GHz]); 1454 i, is2GHz, ah->config.spurchans[i][is2GHz]);
1358 1455
1359 switch (ah->config.spurmode) { 1456 switch (ah->config.spurmode) {
1360 case SPUR_DISABLE: 1457 case SPUR_DISABLE:
1361 break; 1458 break;
1362 case SPUR_ENABLE_IOCTL: 1459 case SPUR_ENABLE_IOCTL:
1363 spur_val = ah->config.spurchans[i][is2GHz]; 1460 spur_val = ah->config.spurchans[i][is2GHz];
1364 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 1461 ath_print(common, ATH_DBG_ANI,
1365 "Getting spur val from new loc. %d\n", spur_val); 1462 "Getting spur val from new loc. %d\n", spur_val);
1366 break; 1463 break;
1367 case SPUR_ENABLE_EEPROM: 1464 case SPUR_ENABLE_EEPROM:
1368 spur_val = EEP_DEF_SPURCHAN; 1465 spur_val = EEP_DEF_SPURCHAN;
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index ca7694caf364..53a7b980d8f6 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -16,9 +16,9 @@
16 16
17#include <linux/io.h> 17#include <linux/io.h>
18#include <asm/unaligned.h> 18#include <asm/unaligned.h>
19#include <linux/pci.h>
20 19
21#include "ath9k.h" 20#include "hw.h"
21#include "rc.h"
22#include "initvals.h" 22#include "initvals.h"
23 23
24#define ATH9K_CLOCK_RATE_CCK 22 24#define ATH9K_CLOCK_RATE_CCK 22
@@ -26,13 +26,27 @@
26#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44 26#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
27 27
28static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); 28static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
29static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan, 29static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
30 enum ath9k_ht_macmode macmode);
31static u32 ath9k_hw_ini_fixup(struct ath_hw *ah, 30static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
32 struct ar5416_eeprom_def *pEepData, 31 struct ar5416_eeprom_def *pEepData,
33 u32 reg, u32 value); 32 u32 reg, u32 value);
34static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan); 33
35static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan); 34MODULE_AUTHOR("Atheros Communications");
35MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
36MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
37MODULE_LICENSE("Dual BSD/GPL");
38
39static int __init ath9k_init(void)
40{
41 return 0;
42}
43module_init(ath9k_init);
44
45static void __exit ath9k_exit(void)
46{
47 return;
48}
49module_exit(ath9k_exit);
36 50
37/********************/ 51/********************/
38/* Helper Functions */ 52/* Helper Functions */
@@ -40,7 +54,7 @@ static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan
40 54
41static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks) 55static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
42{ 56{
43 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; 57 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
44 58
45 if (!ah->curchan) /* should really check for CCK instead */ 59 if (!ah->curchan) /* should really check for CCK instead */
46 return clks / ATH9K_CLOCK_RATE_CCK; 60 return clks / ATH9K_CLOCK_RATE_CCK;
@@ -52,7 +66,7 @@ static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
52 66
53static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks) 67static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
54{ 68{
55 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; 69 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
56 70
57 if (conf_is_ht40(conf)) 71 if (conf_is_ht40(conf))
58 return ath9k_hw_mac_usec(ah, clks) / 2; 72 return ath9k_hw_mac_usec(ah, clks) / 2;
@@ -62,7 +76,7 @@ static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
62 76
63static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs) 77static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
64{ 78{
65 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; 79 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
66 80
67 if (!ah->curchan) /* should really check for CCK instead */ 81 if (!ah->curchan) /* should really check for CCK instead */
68 return usecs *ATH9K_CLOCK_RATE_CCK; 82 return usecs *ATH9K_CLOCK_RATE_CCK;
@@ -73,7 +87,7 @@ static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
73 87
74static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) 88static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
75{ 89{
76 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; 90 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
77 91
78 if (conf_is_ht40(conf)) 92 if (conf_is_ht40(conf))
79 return ath9k_hw_mac_clks(ah, usecs) * 2; 93 return ath9k_hw_mac_clks(ah, usecs) * 2;
@@ -81,38 +95,6 @@ static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
81 return ath9k_hw_mac_clks(ah, usecs); 95 return ath9k_hw_mac_clks(ah, usecs);
82} 96}
83 97
84/*
85 * Read and write, they both share the same lock. We do this to serialize
86 * reads and writes on Atheros 802.11n PCI devices only. This is required
87 * as the FIFO on these devices can only accept sanely 2 requests. After
88 * that the device goes bananas. Serializing the reads/writes prevents this
89 * from happening.
90 */
91
92void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val)
93{
94 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
95 unsigned long flags;
96 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
97 iowrite32(val, ah->ah_sc->mem + reg_offset);
98 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
99 } else
100 iowrite32(val, ah->ah_sc->mem + reg_offset);
101}
102
103unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset)
104{
105 u32 val;
106 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
107 unsigned long flags;
108 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
109 val = ioread32(ah->ah_sc->mem + reg_offset);
110 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
111 } else
112 val = ioread32(ah->ah_sc->mem + reg_offset);
113 return val;
114}
115
116bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) 98bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
117{ 99{
118 int i; 100 int i;
@@ -126,12 +108,13 @@ bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
126 udelay(AH_TIME_QUANTUM); 108 udelay(AH_TIME_QUANTUM);
127 } 109 }
128 110
129 DPRINTF(ah->ah_sc, ATH_DBG_ANY, 111 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
130 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 112 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
131 timeout, reg, REG_READ(ah, reg), mask, val); 113 timeout, reg, REG_READ(ah, reg), mask, val);
132 114
133 return false; 115 return false;
134} 116}
117EXPORT_SYMBOL(ath9k_hw_wait);
135 118
136u32 ath9k_hw_reverse_bits(u32 val, u32 n) 119u32 ath9k_hw_reverse_bits(u32 val, u32 n)
137{ 120{
@@ -210,15 +193,16 @@ u16 ath9k_hw_computetxtime(struct ath_hw *ah,
210 } 193 }
211 break; 194 break;
212 default: 195 default:
213 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 196 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
214 "Unknown phy %u (rate ix %u)\n", 197 "Unknown phy %u (rate ix %u)\n",
215 rates->info[rateix].phy, rateix); 198 rates->info[rateix].phy, rateix);
216 txTime = 0; 199 txTime = 0;
217 break; 200 break;
218 } 201 }
219 202
220 return txTime; 203 return txTime;
221} 204}
205EXPORT_SYMBOL(ath9k_hw_computetxtime);
222 206
223void ath9k_hw_get_channel_centers(struct ath_hw *ah, 207void ath9k_hw_get_channel_centers(struct ath_hw *ah,
224 struct ath9k_channel *chan, 208 struct ath9k_channel *chan,
@@ -245,10 +229,9 @@ void ath9k_hw_get_channel_centers(struct ath_hw *ah,
245 229
246 centers->ctl_center = 230 centers->ctl_center =
247 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); 231 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
232 /* 25 MHz spacing is supported by hw but not on upper layers */
248 centers->ext_center = 233 centers->ext_center =
249 centers->synth_center + (extoff * 234 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
250 ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
251 HT40_CHANNEL_CENTER_SHIFT : 15));
252} 235}
253 236
254/******************/ 237/******************/
@@ -317,6 +300,7 @@ static void ath9k_hw_disablepcie(struct ath_hw *ah)
317 300
318static bool ath9k_hw_chip_test(struct ath_hw *ah) 301static bool ath9k_hw_chip_test(struct ath_hw *ah)
319{ 302{
303 struct ath_common *common = ath9k_hw_common(ah);
320 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) }; 304 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
321 u32 regHold[2]; 305 u32 regHold[2];
322 u32 patternData[4] = { 0x55555555, 306 u32 patternData[4] = { 0x55555555,
@@ -335,10 +319,11 @@ static bool ath9k_hw_chip_test(struct ath_hw *ah)
335 REG_WRITE(ah, addr, wrData); 319 REG_WRITE(ah, addr, wrData);
336 rdData = REG_READ(ah, addr); 320 rdData = REG_READ(ah, addr);
337 if (rdData != wrData) { 321 if (rdData != wrData) {
338 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 322 ath_print(common, ATH_DBG_FATAL,
339 "address test failed " 323 "address test failed "
340 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 324 "addr: 0x%08x - wr:0x%08x != "
341 addr, wrData, rdData); 325 "rd:0x%08x\n",
326 addr, wrData, rdData);
342 return false; 327 return false;
343 } 328 }
344 } 329 }
@@ -347,10 +332,11 @@ static bool ath9k_hw_chip_test(struct ath_hw *ah)
347 REG_WRITE(ah, addr, wrData); 332 REG_WRITE(ah, addr, wrData);
348 rdData = REG_READ(ah, addr); 333 rdData = REG_READ(ah, addr);
349 if (wrData != rdData) { 334 if (wrData != rdData) {
350 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 335 ath_print(common, ATH_DBG_FATAL,
351 "address test failed " 336 "address test failed "
352 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 337 "addr: 0x%08x - wr:0x%08x != "
353 addr, wrData, rdData); 338 "rd:0x%08x\n",
339 addr, wrData, rdData);
354 return false; 340 return false;
355 } 341 }
356 } 342 }
@@ -404,8 +390,6 @@ static void ath9k_hw_init_config(struct ath_hw *ah)
404 ah->config.cck_trig_high = 200; 390 ah->config.cck_trig_high = 200;
405 ah->config.cck_trig_low = 100; 391 ah->config.cck_trig_low = 100;
406 ah->config.enable_ani = 1; 392 ah->config.enable_ani = 1;
407 ah->config.diversity_control = ATH9K_ANT_VARIABLE;
408 ah->config.antenna_switch_swap = 0;
409 393
410 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 394 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
411 ah->config.spurchans[i][0] = AR_NO_SPUR; 395 ah->config.spurchans[i][0] = AR_NO_SPUR;
@@ -433,6 +417,7 @@ static void ath9k_hw_init_config(struct ath_hw *ah)
433 if (num_possible_cpus() > 1) 417 if (num_possible_cpus() > 1)
434 ah->config.serialize_regmode = SER_REG_MODE_AUTO; 418 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
435} 419}
420EXPORT_SYMBOL(ath9k_hw_init);
436 421
437static void ath9k_hw_init_defaults(struct ath_hw *ah) 422static void ath9k_hw_init_defaults(struct ath_hw *ah)
438{ 423{
@@ -459,27 +444,9 @@ static void ath9k_hw_init_defaults(struct ath_hw *ah)
459 ah->acktimeout = (u32) -1; 444 ah->acktimeout = (u32) -1;
460 ah->ctstimeout = (u32) -1; 445 ah->ctstimeout = (u32) -1;
461 ah->globaltxtimeout = (u32) -1; 446 ah->globaltxtimeout = (u32) -1;
462
463 ah->gbeacon_rate = 0;
464
465 ah->power_mode = ATH9K_PM_UNDEFINED; 447 ah->power_mode = ATH9K_PM_UNDEFINED;
466} 448}
467 449
468static int ath9k_hw_rfattach(struct ath_hw *ah)
469{
470 bool rfStatus = false;
471 int ecode = 0;
472
473 rfStatus = ath9k_hw_init_rf(ah, &ecode);
474 if (!rfStatus) {
475 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
476 "RF setup failed, status: %u\n", ecode);
477 return ecode;
478 }
479
480 return 0;
481}
482
483static int ath9k_hw_rf_claim(struct ath_hw *ah) 450static int ath9k_hw_rf_claim(struct ath_hw *ah)
484{ 451{
485 u32 val; 452 u32 val;
@@ -497,9 +464,9 @@ static int ath9k_hw_rf_claim(struct ath_hw *ah)
497 case AR_RAD2122_SREV_MAJOR: 464 case AR_RAD2122_SREV_MAJOR:
498 break; 465 break;
499 default: 466 default:
500 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 467 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
501 "Radio Chip Rev 0x%02X not supported\n", 468 "Radio Chip Rev 0x%02X not supported\n",
502 val & AR_RADIO_SREV_MAJOR); 469 val & AR_RADIO_SREV_MAJOR);
503 return -EOPNOTSUPP; 470 return -EOPNOTSUPP;
504 } 471 }
505 472
@@ -510,6 +477,7 @@ static int ath9k_hw_rf_claim(struct ath_hw *ah)
510 477
511static int ath9k_hw_init_macaddr(struct ath_hw *ah) 478static int ath9k_hw_init_macaddr(struct ath_hw *ah)
512{ 479{
480 struct ath_common *common = ath9k_hw_common(ah);
513 u32 sum; 481 u32 sum;
514 int i; 482 int i;
515 u16 eeval; 483 u16 eeval;
@@ -518,8 +486,8 @@ static int ath9k_hw_init_macaddr(struct ath_hw *ah)
518 for (i = 0; i < 3; i++) { 486 for (i = 0; i < 3; i++) {
519 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i)); 487 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
520 sum += eeval; 488 sum += eeval;
521 ah->macaddr[2 * i] = eeval >> 8; 489 common->macaddr[2 * i] = eeval >> 8;
522 ah->macaddr[2 * i + 1] = eeval & 0xff; 490 common->macaddr[2 * i + 1] = eeval & 0xff;
523 } 491 }
524 if (sum == 0 || sum == 0xffff * 3) 492 if (sum == 0 || sum == 0xffff * 3)
525 return -EADDRNOTAVAIL; 493 return -EADDRNOTAVAIL;
@@ -590,12 +558,20 @@ static int ath9k_hw_post_init(struct ath_hw *ah)
590 if (ecode != 0) 558 if (ecode != 0)
591 return ecode; 559 return ecode;
592 560
593 DPRINTF(ah->ah_sc, ATH_DBG_CONFIG, "Eeprom VER: %d, REV: %d\n", 561 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
594 ah->eep_ops->get_eeprom_ver(ah), ah->eep_ops->get_eeprom_rev(ah)); 562 "Eeprom VER: %d, REV: %d\n",
595 563 ah->eep_ops->get_eeprom_ver(ah),
596 ecode = ath9k_hw_rfattach(ah); 564 ah->eep_ops->get_eeprom_rev(ah));
597 if (ecode != 0) 565
598 return ecode; 566 if (!AR_SREV_9280_10_OR_LATER(ah)) {
567 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
568 if (ecode) {
569 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
570 "Failed allocating banks for "
571 "external radio\n");
572 return ecode;
573 }
574 }
599 575
600 if (!AR_SREV_9100(ah)) { 576 if (!AR_SREV_9100(ah)) {
601 ath9k_hw_ani_setup(ah); 577 ath9k_hw_ani_setup(ah);
@@ -617,6 +593,7 @@ static bool ath9k_hw_devid_supported(u16 devid)
617 case AR9285_DEVID_PCIE: 593 case AR9285_DEVID_PCIE:
618 case AR5416_DEVID_AR9287_PCI: 594 case AR5416_DEVID_AR9287_PCI:
619 case AR5416_DEVID_AR9287_PCIE: 595 case AR5416_DEVID_AR9287_PCIE:
596 case AR9271_USB:
620 return true; 597 return true;
621 default: 598 default:
622 break; 599 break;
@@ -634,9 +611,8 @@ static bool ath9k_hw_macversion_supported(u32 macversion)
634 case AR_SREV_VERSION_9280: 611 case AR_SREV_VERSION_9280:
635 case AR_SREV_VERSION_9285: 612 case AR_SREV_VERSION_9285:
636 case AR_SREV_VERSION_9287: 613 case AR_SREV_VERSION_9287:
637 return true;
638 /* Not yet */
639 case AR_SREV_VERSION_9271: 614 case AR_SREV_VERSION_9271:
615 return true;
640 default: 616 default:
641 break; 617 break;
642 } 618 }
@@ -670,10 +646,13 @@ static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
670static void ath9k_hw_init_mode_regs(struct ath_hw *ah) 646static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
671{ 647{
672 if (AR_SREV_9271(ah)) { 648 if (AR_SREV_9271(ah)) {
673 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271_1_0, 649 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
674 ARRAY_SIZE(ar9271Modes_9271_1_0), 6); 650 ARRAY_SIZE(ar9271Modes_9271), 6);
675 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271_1_0, 651 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
676 ARRAY_SIZE(ar9271Common_9271_1_0), 2); 652 ARRAY_SIZE(ar9271Common_9271), 2);
653 INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
654 ar9271Modes_9271_1_0_only,
655 ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
677 return; 656 return;
678 } 657 }
679 658
@@ -905,21 +884,27 @@ static void ath9k_hw_init_11a_eeprom_fix(struct ath_hw *ah)
905 884
906int ath9k_hw_init(struct ath_hw *ah) 885int ath9k_hw_init(struct ath_hw *ah)
907{ 886{
887 struct ath_common *common = ath9k_hw_common(ah);
908 int r = 0; 888 int r = 0;
909 889
910 if (!ath9k_hw_devid_supported(ah->hw_version.devid)) 890 if (!ath9k_hw_devid_supported(ah->hw_version.devid)) {
891 ath_print(common, ATH_DBG_FATAL,
892 "Unsupported device ID: 0x%0x\n",
893 ah->hw_version.devid);
911 return -EOPNOTSUPP; 894 return -EOPNOTSUPP;
895 }
912 896
913 ath9k_hw_init_defaults(ah); 897 ath9k_hw_init_defaults(ah);
914 ath9k_hw_init_config(ah); 898 ath9k_hw_init_config(ah);
915 899
916 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 900 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
917 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Couldn't reset chip\n"); 901 ath_print(common, ATH_DBG_FATAL,
902 "Couldn't reset chip\n");
918 return -EIO; 903 return -EIO;
919 } 904 }
920 905
921 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 906 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
922 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Couldn't wakeup chip\n"); 907 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
923 return -EIO; 908 return -EIO;
924 } 909 }
925 910
@@ -934,14 +919,14 @@ int ath9k_hw_init(struct ath_hw *ah)
934 } 919 }
935 } 920 }
936 921
937 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "serialize_regmode is %d\n", 922 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
938 ah->config.serialize_regmode); 923 ah->config.serialize_regmode);
939 924
940 if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) { 925 if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
941 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 926 ath_print(common, ATH_DBG_FATAL,
942 "Mac Chip Rev 0x%02x.%x is not supported by " 927 "Mac Chip Rev 0x%02x.%x is not supported by "
943 "this driver\n", ah->hw_version.macVersion, 928 "this driver\n", ah->hw_version.macVersion,
944 ah->hw_version.macRev); 929 ah->hw_version.macRev);
945 return -EOPNOTSUPP; 930 return -EOPNOTSUPP;
946 } 931 }
947 932
@@ -959,8 +944,14 @@ int ath9k_hw_init(struct ath_hw *ah)
959 ath9k_hw_init_cal_settings(ah); 944 ath9k_hw_init_cal_settings(ah);
960 945
961 ah->ani_function = ATH9K_ANI_ALL; 946 ah->ani_function = ATH9K_ANI_ALL;
962 if (AR_SREV_9280_10_OR_LATER(ah)) 947 if (AR_SREV_9280_10_OR_LATER(ah)) {
963 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; 948 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
949 ah->ath9k_hw_rf_set_freq = &ath9k_hw_ar9280_set_channel;
950 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_9280_spur_mitigate;
951 } else {
952 ah->ath9k_hw_rf_set_freq = &ath9k_hw_set_channel;
953 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_spur_mitigate;
954 }
964 955
965 ath9k_hw_init_mode_regs(ah); 956 ath9k_hw_init_mode_regs(ah);
966 957
@@ -969,6 +960,16 @@ int ath9k_hw_init(struct ath_hw *ah)
969 else 960 else
970 ath9k_hw_disablepcie(ah); 961 ath9k_hw_disablepcie(ah);
971 962
963 /* Support for Japan ch.14 (2484) spread */
964 if (AR_SREV_9287_11_OR_LATER(ah)) {
965 INIT_INI_ARRAY(&ah->iniCckfirNormal,
966 ar9287Common_normal_cck_fir_coeff_92871_1,
967 ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
968 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
969 ar9287Common_japan_2484_cck_fir_coeff_92871_1,
970 ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
971 }
972
972 r = ath9k_hw_post_init(ah); 973 r = ath9k_hw_post_init(ah);
973 if (r) 974 if (r)
974 return r; 975 return r;
@@ -979,8 +980,8 @@ int ath9k_hw_init(struct ath_hw *ah)
979 980
980 r = ath9k_hw_init_macaddr(ah); 981 r = ath9k_hw_init_macaddr(ah);
981 if (r) { 982 if (r) {
982 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 983 ath_print(common, ATH_DBG_FATAL,
983 "Failed to initialize MAC address\n"); 984 "Failed to initialize MAC address\n");
984 return r; 985 return r;
985 } 986 }
986 987
@@ -991,6 +992,8 @@ int ath9k_hw_init(struct ath_hw *ah)
991 992
992 ath9k_init_nfcal_hist_buffer(ah); 993 ath9k_init_nfcal_hist_buffer(ah);
993 994
995 common->state = ATH_HW_INITIALIZED;
996
994 return 0; 997 return 0;
995} 998}
996 999
@@ -1027,6 +1030,22 @@ static void ath9k_hw_init_qos(struct ath_hw *ah)
1027 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 1030 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
1028} 1031}
1029 1032
1033static void ath9k_hw_change_target_baud(struct ath_hw *ah, u32 freq, u32 baud)
1034{
1035 u32 lcr;
1036 u32 baud_divider = freq * 1000 * 1000 / 16 / baud;
1037
1038 lcr = REG_READ(ah , 0x5100c);
1039 lcr |= 0x80;
1040
1041 REG_WRITE(ah, 0x5100c, lcr);
1042 REG_WRITE(ah, 0x51004, (baud_divider >> 8));
1043 REG_WRITE(ah, 0x51000, (baud_divider & 0xff));
1044
1045 lcr &= ~0x80;
1046 REG_WRITE(ah, 0x5100c, lcr);
1047}
1048
1030static void ath9k_hw_init_pll(struct ath_hw *ah, 1049static void ath9k_hw_init_pll(struct ath_hw *ah,
1031 struct ath9k_channel *chan) 1050 struct ath9k_channel *chan)
1032{ 1051{
@@ -1090,6 +1109,26 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
1090 } 1109 }
1091 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 1110 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1092 1111
1112 /* Switch the core clock for ar9271 to 117Mhz */
1113 if (AR_SREV_9271(ah)) {
1114 if ((pll == 0x142c) || (pll == 0x2850) ) {
1115 udelay(500);
1116 /* set CLKOBS to output AHB clock */
1117 REG_WRITE(ah, 0x7020, 0xe);
1118 /*
1119 * 0x304: 117Mhz, ahb_ratio: 1x1
1120 * 0x306: 40Mhz, ahb_ratio: 1x1
1121 */
1122 REG_WRITE(ah, 0x50040, 0x304);
1123 /*
1124 * makes adjustments for the baud dividor to keep the
1125 * targetted baud rate based on the used core clock.
1126 */
1127 ath9k_hw_change_target_baud(ah, AR9271_CORE_CLOCK,
1128 AR9271_TARGET_BAUD_RATE);
1129 }
1130 }
1131
1093 udelay(RTC_PLL_SETTLE_DELAY); 1132 udelay(RTC_PLL_SETTLE_DELAY);
1094 1133
1095 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 1134 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
@@ -1107,7 +1146,7 @@ static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1107 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, 1146 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1108 AR_PHY_SWAP_ALT_CHAIN); 1147 AR_PHY_SWAP_ALT_CHAIN);
1109 case 0x3: 1148 case 0x3:
1110 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) { 1149 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
1111 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7); 1150 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1112 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7); 1151 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1113 break; 1152 break;
@@ -1164,7 +1203,8 @@ static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1164static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) 1203static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1165{ 1204{
1166 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) { 1205 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1167 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us); 1206 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1207 "bad ack timeout %u\n", us);
1168 ah->acktimeout = (u32) -1; 1208 ah->acktimeout = (u32) -1;
1169 return false; 1209 return false;
1170 } else { 1210 } else {
@@ -1178,7 +1218,8 @@ static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1178static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) 1218static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1179{ 1219{
1180 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) { 1220 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1181 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us); 1221 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1222 "bad cts timeout %u\n", us);
1182 ah->ctstimeout = (u32) -1; 1223 ah->ctstimeout = (u32) -1;
1183 return false; 1224 return false;
1184 } else { 1225 } else {
@@ -1192,8 +1233,8 @@ static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1192static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) 1233static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1193{ 1234{
1194 if (tu > 0xFFFF) { 1235 if (tu > 0xFFFF) {
1195 DPRINTF(ah->ah_sc, ATH_DBG_XMIT, 1236 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
1196 "bad global tx timeout %u\n", tu); 1237 "bad global tx timeout %u\n", tu);
1197 ah->globaltxtimeout = (u32) -1; 1238 ah->globaltxtimeout = (u32) -1;
1198 return false; 1239 return false;
1199 } else { 1240 } else {
@@ -1205,8 +1246,8 @@ static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1205 1246
1206static void ath9k_hw_init_user_settings(struct ath_hw *ah) 1247static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1207{ 1248{
1208 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->misc_mode 0x%x\n", 1249 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1209 ah->misc_mode); 1250 ah->misc_mode);
1210 1251
1211 if (ah->misc_mode != 0) 1252 if (ah->misc_mode != 0)
1212 REG_WRITE(ah, AR_PCU_MISC, 1253 REG_WRITE(ah, AR_PCU_MISC,
@@ -1229,14 +1270,23 @@ const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1229 1270
1230void ath9k_hw_detach(struct ath_hw *ah) 1271void ath9k_hw_detach(struct ath_hw *ah)
1231{ 1272{
1273 struct ath_common *common = ath9k_hw_common(ah);
1274
1275 if (common->state <= ATH_HW_INITIALIZED)
1276 goto free_hw;
1277
1232 if (!AR_SREV_9100(ah)) 1278 if (!AR_SREV_9100(ah))
1233 ath9k_hw_ani_disable(ah); 1279 ath9k_hw_ani_disable(ah);
1234 1280
1235 ath9k_hw_rf_free(ah);
1236 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 1281 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1282
1283free_hw:
1284 if (!AR_SREV_9280_10_OR_LATER(ah))
1285 ath9k_hw_rf_free_ext_banks(ah);
1237 kfree(ah); 1286 kfree(ah);
1238 ah = NULL; 1287 ah = NULL;
1239} 1288}
1289EXPORT_SYMBOL(ath9k_hw_detach);
1240 1290
1241/*******/ 1291/*******/
1242/* INI */ 1292/* INI */
@@ -1254,7 +1304,8 @@ static void ath9k_hw_override_ini(struct ath_hw *ah,
1254 * AR9271 1.1 1304 * AR9271 1.1
1255 */ 1305 */
1256 if (AR_SREV_9271_10(ah)) { 1306 if (AR_SREV_9271_10(ah)) {
1257 val = REG_READ(ah, AR_PHY_SPECTRAL_SCAN) | AR_PHY_SPECTRAL_SCAN_ENABLE; 1307 val = REG_READ(ah, AR_PHY_SPECTRAL_SCAN) |
1308 AR_PHY_SPECTRAL_SCAN_ENABLE;
1258 REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val); 1309 REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
1259 } 1310 }
1260 else if (AR_SREV_9271_11(ah)) 1311 else if (AR_SREV_9271_11(ah))
@@ -1298,28 +1349,29 @@ static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1298 u32 reg, u32 value) 1349 u32 reg, u32 value)
1299{ 1350{
1300 struct base_eep_header *pBase = &(pEepData->baseEepHeader); 1351 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1352 struct ath_common *common = ath9k_hw_common(ah);
1301 1353
1302 switch (ah->hw_version.devid) { 1354 switch (ah->hw_version.devid) {
1303 case AR9280_DEVID_PCI: 1355 case AR9280_DEVID_PCI:
1304 if (reg == 0x7894) { 1356 if (reg == 0x7894) {
1305 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 1357 ath_print(common, ATH_DBG_EEPROM,
1306 "ini VAL: %x EEPROM: %x\n", value, 1358 "ini VAL: %x EEPROM: %x\n", value,
1307 (pBase->version & 0xff)); 1359 (pBase->version & 0xff));
1308 1360
1309 if ((pBase->version & 0xff) > 0x0a) { 1361 if ((pBase->version & 0xff) > 0x0a) {
1310 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 1362 ath_print(common, ATH_DBG_EEPROM,
1311 "PWDCLKIND: %d\n", 1363 "PWDCLKIND: %d\n",
1312 pBase->pwdclkind); 1364 pBase->pwdclkind);
1313 value &= ~AR_AN_TOP2_PWDCLKIND; 1365 value &= ~AR_AN_TOP2_PWDCLKIND;
1314 value |= AR_AN_TOP2_PWDCLKIND & 1366 value |= AR_AN_TOP2_PWDCLKIND &
1315 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S); 1367 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1316 } else { 1368 } else {
1317 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 1369 ath_print(common, ATH_DBG_EEPROM,
1318 "PWDCLKIND Earlier Rev\n"); 1370 "PWDCLKIND Earlier Rev\n");
1319 } 1371 }
1320 1372
1321 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 1373 ath_print(common, ATH_DBG_EEPROM,
1322 "final ini VAL: %x\n", value); 1374 "final ini VAL: %x\n", value);
1323 } 1375 }
1324 break; 1376 break;
1325 } 1377 }
@@ -1374,8 +1426,7 @@ static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1374} 1426}
1375 1427
1376static int ath9k_hw_process_ini(struct ath_hw *ah, 1428static int ath9k_hw_process_ini(struct ath_hw *ah,
1377 struct ath9k_channel *chan, 1429 struct ath9k_channel *chan)
1378 enum ath9k_ht_macmode macmode)
1379{ 1430{
1380 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 1431 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1381 int i, regWrites = 0; 1432 int i, regWrites = 0;
@@ -1469,7 +1520,11 @@ static int ath9k_hw_process_ini(struct ath_hw *ah,
1469 DO_DELAY(regWrites); 1520 DO_DELAY(regWrites);
1470 } 1521 }
1471 1522
1472 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites); 1523 ath9k_hw_write_regs(ah, freqIndex, regWrites);
1524
1525 if (AR_SREV_9271_10(ah))
1526 REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
1527 modesIndex, regWrites);
1473 1528
1474 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) { 1529 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1475 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex, 1530 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
@@ -1477,7 +1532,7 @@ static int ath9k_hw_process_ini(struct ath_hw *ah,
1477 } 1532 }
1478 1533
1479 ath9k_hw_override_ini(ah, chan); 1534 ath9k_hw_override_ini(ah, chan);
1480 ath9k_hw_set_regs(ah, chan, macmode); 1535 ath9k_hw_set_regs(ah, chan);
1481 ath9k_hw_init_chain_masks(ah); 1536 ath9k_hw_init_chain_masks(ah);
1482 1537
1483 if (OLC_FOR_AR9280_20_LATER) 1538 if (OLC_FOR_AR9280_20_LATER)
@@ -1491,8 +1546,8 @@ static int ath9k_hw_process_ini(struct ath_hw *ah,
1491 (u32) regulatory->power_limit)); 1546 (u32) regulatory->power_limit));
1492 1547
1493 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) { 1548 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1494 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 1549 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1495 "ar5416SetRfRegs failed\n"); 1550 "ar5416SetRfRegs failed\n");
1496 return -EIO; 1551 return -EIO;
1497 } 1552 }
1498 1553
@@ -1697,16 +1752,14 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1697 1752
1698 REG_WRITE(ah, AR_RTC_RC, 0); 1753 REG_WRITE(ah, AR_RTC_RC, 0);
1699 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { 1754 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1700 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 1755 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1701 "RTC stuck in MAC reset\n"); 1756 "RTC stuck in MAC reset\n");
1702 return false; 1757 return false;
1703 } 1758 }
1704 1759
1705 if (!AR_SREV_9100(ah)) 1760 if (!AR_SREV_9100(ah))
1706 REG_WRITE(ah, AR_RC, 0); 1761 REG_WRITE(ah, AR_RC, 0);
1707 1762
1708 ath9k_hw_init_pll(ah, NULL);
1709
1710 if (AR_SREV_9100(ah)) 1763 if (AR_SREV_9100(ah))
1711 udelay(50); 1764 udelay(50);
1712 1765
@@ -1734,7 +1787,8 @@ static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1734 AR_RTC_STATUS_M, 1787 AR_RTC_STATUS_M,
1735 AR_RTC_STATUS_ON, 1788 AR_RTC_STATUS_ON,
1736 AH_WAIT_TIMEOUT)) { 1789 AH_WAIT_TIMEOUT)) {
1737 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n"); 1790 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1791 "RTC not waking up\n");
1738 return false; 1792 return false;
1739 } 1793 }
1740 1794
@@ -1759,8 +1813,7 @@ static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1759 } 1813 }
1760} 1814}
1761 1815
1762static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan, 1816static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan)
1763 enum ath9k_ht_macmode macmode)
1764{ 1817{
1765 u32 phymode; 1818 u32 phymode;
1766 u32 enableDacFifo = 0; 1819 u32 enableDacFifo = 0;
@@ -1779,12 +1832,10 @@ static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
1779 (chan->chanmode == CHANNEL_G_HT40PLUS)) 1832 (chan->chanmode == CHANNEL_G_HT40PLUS))
1780 phymode |= AR_PHY_FC_DYN2040_PRI_CH; 1833 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1781 1834
1782 if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1783 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1784 } 1835 }
1785 REG_WRITE(ah, AR_PHY_TURBO, phymode); 1836 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1786 1837
1787 ath9k_hw_set11nmac2040(ah, macmode); 1838 ath9k_hw_set11nmac2040(ah);
1788 1839
1789 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); 1840 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1790 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); 1841 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
@@ -1810,17 +1861,19 @@ static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1810} 1861}
1811 1862
1812static bool ath9k_hw_channel_change(struct ath_hw *ah, 1863static bool ath9k_hw_channel_change(struct ath_hw *ah,
1813 struct ath9k_channel *chan, 1864 struct ath9k_channel *chan)
1814 enum ath9k_ht_macmode macmode)
1815{ 1865{
1816 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 1866 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1867 struct ath_common *common = ath9k_hw_common(ah);
1817 struct ieee80211_channel *channel = chan->chan; 1868 struct ieee80211_channel *channel = chan->chan;
1818 u32 synthDelay, qnum; 1869 u32 synthDelay, qnum;
1870 int r;
1819 1871
1820 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1872 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1821 if (ath9k_hw_numtxpending(ah, qnum)) { 1873 if (ath9k_hw_numtxpending(ah, qnum)) {
1822 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, 1874 ath_print(common, ATH_DBG_QUEUE,
1823 "Transmit frames pending on queue %d\n", qnum); 1875 "Transmit frames pending on "
1876 "queue %d\n", qnum);
1824 return false; 1877 return false;
1825 } 1878 }
1826 } 1879 }
@@ -1828,21 +1881,18 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1828 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); 1881 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1829 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, 1882 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1830 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) { 1883 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1831 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 1884 ath_print(common, ATH_DBG_FATAL,
1832 "Could not kill baseband RX\n"); 1885 "Could not kill baseband RX\n");
1833 return false; 1886 return false;
1834 } 1887 }
1835 1888
1836 ath9k_hw_set_regs(ah, chan, macmode); 1889 ath9k_hw_set_regs(ah, chan);
1837 1890
1838 if (AR_SREV_9280_10_OR_LATER(ah)) { 1891 r = ah->ath9k_hw_rf_set_freq(ah, chan);
1839 ath9k_hw_ar9280_set_channel(ah, chan); 1892 if (r) {
1840 } else { 1893 ath_print(common, ATH_DBG_FATAL,
1841 if (!(ath9k_hw_set_channel(ah, chan))) { 1894 "Failed to set channel\n");
1842 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 1895 return false;
1843 "Failed to set channel\n");
1844 return false;
1845 }
1846 } 1896 }
1847 1897
1848 ah->eep_ops->set_txpower(ah, chan, 1898 ah->eep_ops->set_txpower(ah, chan,
@@ -1865,10 +1915,7 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1865 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1915 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1866 ath9k_hw_set_delta_slope(ah, chan); 1916 ath9k_hw_set_delta_slope(ah, chan);
1867 1917
1868 if (AR_SREV_9280_10_OR_LATER(ah)) 1918 ah->ath9k_hw_spur_mitigate_freq(ah, chan);
1869 ath9k_hw_9280_spur_mitigate(ah, chan);
1870 else
1871 ath9k_hw_spur_mitigate(ah, chan);
1872 1919
1873 if (!chan->oneTimeCalsDone) 1920 if (!chan->oneTimeCalsDone)
1874 chan->oneTimeCalsDone = true; 1921 chan->oneTimeCalsDone = true;
@@ -1876,457 +1923,6 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1876 return true; 1923 return true;
1877} 1924}
1878 1925
1879static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1880{
1881 int bb_spur = AR_NO_SPUR;
1882 int freq;
1883 int bin, cur_bin;
1884 int bb_spur_off, spur_subchannel_sd;
1885 int spur_freq_sd;
1886 int spur_delta_phase;
1887 int denominator;
1888 int upper, lower, cur_vit_mask;
1889 int tmp, newVal;
1890 int i;
1891 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1892 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1893 };
1894 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1895 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1896 };
1897 int inc[4] = { 0, 100, 0, 0 };
1898 struct chan_centers centers;
1899
1900 int8_t mask_m[123];
1901 int8_t mask_p[123];
1902 int8_t mask_amt;
1903 int tmp_mask;
1904 int cur_bb_spur;
1905 bool is2GHz = IS_CHAN_2GHZ(chan);
1906
1907 memset(&mask_m, 0, sizeof(int8_t) * 123);
1908 memset(&mask_p, 0, sizeof(int8_t) * 123);
1909
1910 ath9k_hw_get_channel_centers(ah, chan, &centers);
1911 freq = centers.synth_center;
1912
1913 ah->config.spurmode = SPUR_ENABLE_EEPROM;
1914 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1915 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1916
1917 if (is2GHz)
1918 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1919 else
1920 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1921
1922 if (AR_NO_SPUR == cur_bb_spur)
1923 break;
1924 cur_bb_spur = cur_bb_spur - freq;
1925
1926 if (IS_CHAN_HT40(chan)) {
1927 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1928 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1929 bb_spur = cur_bb_spur;
1930 break;
1931 }
1932 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1933 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1934 bb_spur = cur_bb_spur;
1935 break;
1936 }
1937 }
1938
1939 if (AR_NO_SPUR == bb_spur) {
1940 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1941 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1942 return;
1943 } else {
1944 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1945 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1946 }
1947
1948 bin = bb_spur * 320;
1949
1950 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1951
1952 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1953 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1954 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1955 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1956 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1957
1958 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1959 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1960 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1961 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1962 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1963 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1964
1965 if (IS_CHAN_HT40(chan)) {
1966 if (bb_spur < 0) {
1967 spur_subchannel_sd = 1;
1968 bb_spur_off = bb_spur + 10;
1969 } else {
1970 spur_subchannel_sd = 0;
1971 bb_spur_off = bb_spur - 10;
1972 }
1973 } else {
1974 spur_subchannel_sd = 0;
1975 bb_spur_off = bb_spur;
1976 }
1977
1978 if (IS_CHAN_HT40(chan))
1979 spur_delta_phase =
1980 ((bb_spur * 262144) /
1981 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1982 else
1983 spur_delta_phase =
1984 ((bb_spur * 524288) /
1985 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1986
1987 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1988 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1989
1990 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1991 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1992 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1993 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1994
1995 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1996 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1997
1998 cur_bin = -6000;
1999 upper = bin + 100;
2000 lower = bin - 100;
2001
2002 for (i = 0; i < 4; i++) {
2003 int pilot_mask = 0;
2004 int chan_mask = 0;
2005 int bp = 0;
2006 for (bp = 0; bp < 30; bp++) {
2007 if ((cur_bin > lower) && (cur_bin < upper)) {
2008 pilot_mask = pilot_mask | 0x1 << bp;
2009 chan_mask = chan_mask | 0x1 << bp;
2010 }
2011 cur_bin += 100;
2012 }
2013 cur_bin += inc[i];
2014 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2015 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2016 }
2017
2018 cur_vit_mask = 6100;
2019 upper = bin + 120;
2020 lower = bin - 120;
2021
2022 for (i = 0; i < 123; i++) {
2023 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2024
2025 /* workaround for gcc bug #37014 */
2026 volatile int tmp_v = abs(cur_vit_mask - bin);
2027
2028 if (tmp_v < 75)
2029 mask_amt = 1;
2030 else
2031 mask_amt = 0;
2032 if (cur_vit_mask < 0)
2033 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2034 else
2035 mask_p[cur_vit_mask / 100] = mask_amt;
2036 }
2037 cur_vit_mask -= 100;
2038 }
2039
2040 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2041 | (mask_m[48] << 26) | (mask_m[49] << 24)
2042 | (mask_m[50] << 22) | (mask_m[51] << 20)
2043 | (mask_m[52] << 18) | (mask_m[53] << 16)
2044 | (mask_m[54] << 14) | (mask_m[55] << 12)
2045 | (mask_m[56] << 10) | (mask_m[57] << 8)
2046 | (mask_m[58] << 6) | (mask_m[59] << 4)
2047 | (mask_m[60] << 2) | (mask_m[61] << 0);
2048 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2049 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2050
2051 tmp_mask = (mask_m[31] << 28)
2052 | (mask_m[32] << 26) | (mask_m[33] << 24)
2053 | (mask_m[34] << 22) | (mask_m[35] << 20)
2054 | (mask_m[36] << 18) | (mask_m[37] << 16)
2055 | (mask_m[48] << 14) | (mask_m[39] << 12)
2056 | (mask_m[40] << 10) | (mask_m[41] << 8)
2057 | (mask_m[42] << 6) | (mask_m[43] << 4)
2058 | (mask_m[44] << 2) | (mask_m[45] << 0);
2059 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2060 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2061
2062 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2063 | (mask_m[18] << 26) | (mask_m[18] << 24)
2064 | (mask_m[20] << 22) | (mask_m[20] << 20)
2065 | (mask_m[22] << 18) | (mask_m[22] << 16)
2066 | (mask_m[24] << 14) | (mask_m[24] << 12)
2067 | (mask_m[25] << 10) | (mask_m[26] << 8)
2068 | (mask_m[27] << 6) | (mask_m[28] << 4)
2069 | (mask_m[29] << 2) | (mask_m[30] << 0);
2070 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2071 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2072
2073 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2074 | (mask_m[2] << 26) | (mask_m[3] << 24)
2075 | (mask_m[4] << 22) | (mask_m[5] << 20)
2076 | (mask_m[6] << 18) | (mask_m[7] << 16)
2077 | (mask_m[8] << 14) | (mask_m[9] << 12)
2078 | (mask_m[10] << 10) | (mask_m[11] << 8)
2079 | (mask_m[12] << 6) | (mask_m[13] << 4)
2080 | (mask_m[14] << 2) | (mask_m[15] << 0);
2081 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2082 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2083
2084 tmp_mask = (mask_p[15] << 28)
2085 | (mask_p[14] << 26) | (mask_p[13] << 24)
2086 | (mask_p[12] << 22) | (mask_p[11] << 20)
2087 | (mask_p[10] << 18) | (mask_p[9] << 16)
2088 | (mask_p[8] << 14) | (mask_p[7] << 12)
2089 | (mask_p[6] << 10) | (mask_p[5] << 8)
2090 | (mask_p[4] << 6) | (mask_p[3] << 4)
2091 | (mask_p[2] << 2) | (mask_p[1] << 0);
2092 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2093 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2094
2095 tmp_mask = (mask_p[30] << 28)
2096 | (mask_p[29] << 26) | (mask_p[28] << 24)
2097 | (mask_p[27] << 22) | (mask_p[26] << 20)
2098 | (mask_p[25] << 18) | (mask_p[24] << 16)
2099 | (mask_p[23] << 14) | (mask_p[22] << 12)
2100 | (mask_p[21] << 10) | (mask_p[20] << 8)
2101 | (mask_p[19] << 6) | (mask_p[18] << 4)
2102 | (mask_p[17] << 2) | (mask_p[16] << 0);
2103 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2104 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2105
2106 tmp_mask = (mask_p[45] << 28)
2107 | (mask_p[44] << 26) | (mask_p[43] << 24)
2108 | (mask_p[42] << 22) | (mask_p[41] << 20)
2109 | (mask_p[40] << 18) | (mask_p[39] << 16)
2110 | (mask_p[38] << 14) | (mask_p[37] << 12)
2111 | (mask_p[36] << 10) | (mask_p[35] << 8)
2112 | (mask_p[34] << 6) | (mask_p[33] << 4)
2113 | (mask_p[32] << 2) | (mask_p[31] << 0);
2114 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2115 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2116
2117 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2118 | (mask_p[59] << 26) | (mask_p[58] << 24)
2119 | (mask_p[57] << 22) | (mask_p[56] << 20)
2120 | (mask_p[55] << 18) | (mask_p[54] << 16)
2121 | (mask_p[53] << 14) | (mask_p[52] << 12)
2122 | (mask_p[51] << 10) | (mask_p[50] << 8)
2123 | (mask_p[49] << 6) | (mask_p[48] << 4)
2124 | (mask_p[47] << 2) | (mask_p[46] << 0);
2125 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2126 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2127}
2128
2129static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
2130{
2131 int bb_spur = AR_NO_SPUR;
2132 int bin, cur_bin;
2133 int spur_freq_sd;
2134 int spur_delta_phase;
2135 int denominator;
2136 int upper, lower, cur_vit_mask;
2137 int tmp, new;
2138 int i;
2139 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
2140 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
2141 };
2142 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2143 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2144 };
2145 int inc[4] = { 0, 100, 0, 0 };
2146
2147 int8_t mask_m[123];
2148 int8_t mask_p[123];
2149 int8_t mask_amt;
2150 int tmp_mask;
2151 int cur_bb_spur;
2152 bool is2GHz = IS_CHAN_2GHZ(chan);
2153
2154 memset(&mask_m, 0, sizeof(int8_t) * 123);
2155 memset(&mask_p, 0, sizeof(int8_t) * 123);
2156
2157 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2158 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
2159 if (AR_NO_SPUR == cur_bb_spur)
2160 break;
2161 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2162 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2163 bb_spur = cur_bb_spur;
2164 break;
2165 }
2166 }
2167
2168 if (AR_NO_SPUR == bb_spur)
2169 return;
2170
2171 bin = bb_spur * 32;
2172
2173 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2174 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2175 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2176 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2177 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2178
2179 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2180
2181 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2182 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2183 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2184 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2185 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2186 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2187
2188 spur_delta_phase = ((bb_spur * 524288) / 100) &
2189 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2190
2191 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2192 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2193
2194 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2195 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2196 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2197 REG_WRITE(ah, AR_PHY_TIMING11, new);
2198
2199 cur_bin = -6000;
2200 upper = bin + 100;
2201 lower = bin - 100;
2202
2203 for (i = 0; i < 4; i++) {
2204 int pilot_mask = 0;
2205 int chan_mask = 0;
2206 int bp = 0;
2207 for (bp = 0; bp < 30; bp++) {
2208 if ((cur_bin > lower) && (cur_bin < upper)) {
2209 pilot_mask = pilot_mask | 0x1 << bp;
2210 chan_mask = chan_mask | 0x1 << bp;
2211 }
2212 cur_bin += 100;
2213 }
2214 cur_bin += inc[i];
2215 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2216 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2217 }
2218
2219 cur_vit_mask = 6100;
2220 upper = bin + 120;
2221 lower = bin - 120;
2222
2223 for (i = 0; i < 123; i++) {
2224 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2225
2226 /* workaround for gcc bug #37014 */
2227 volatile int tmp_v = abs(cur_vit_mask - bin);
2228
2229 if (tmp_v < 75)
2230 mask_amt = 1;
2231 else
2232 mask_amt = 0;
2233 if (cur_vit_mask < 0)
2234 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2235 else
2236 mask_p[cur_vit_mask / 100] = mask_amt;
2237 }
2238 cur_vit_mask -= 100;
2239 }
2240
2241 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2242 | (mask_m[48] << 26) | (mask_m[49] << 24)
2243 | (mask_m[50] << 22) | (mask_m[51] << 20)
2244 | (mask_m[52] << 18) | (mask_m[53] << 16)
2245 | (mask_m[54] << 14) | (mask_m[55] << 12)
2246 | (mask_m[56] << 10) | (mask_m[57] << 8)
2247 | (mask_m[58] << 6) | (mask_m[59] << 4)
2248 | (mask_m[60] << 2) | (mask_m[61] << 0);
2249 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2250 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2251
2252 tmp_mask = (mask_m[31] << 28)
2253 | (mask_m[32] << 26) | (mask_m[33] << 24)
2254 | (mask_m[34] << 22) | (mask_m[35] << 20)
2255 | (mask_m[36] << 18) | (mask_m[37] << 16)
2256 | (mask_m[48] << 14) | (mask_m[39] << 12)
2257 | (mask_m[40] << 10) | (mask_m[41] << 8)
2258 | (mask_m[42] << 6) | (mask_m[43] << 4)
2259 | (mask_m[44] << 2) | (mask_m[45] << 0);
2260 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2261 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2262
2263 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2264 | (mask_m[18] << 26) | (mask_m[18] << 24)
2265 | (mask_m[20] << 22) | (mask_m[20] << 20)
2266 | (mask_m[22] << 18) | (mask_m[22] << 16)
2267 | (mask_m[24] << 14) | (mask_m[24] << 12)
2268 | (mask_m[25] << 10) | (mask_m[26] << 8)
2269 | (mask_m[27] << 6) | (mask_m[28] << 4)
2270 | (mask_m[29] << 2) | (mask_m[30] << 0);
2271 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2272 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2273
2274 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2275 | (mask_m[2] << 26) | (mask_m[3] << 24)
2276 | (mask_m[4] << 22) | (mask_m[5] << 20)
2277 | (mask_m[6] << 18) | (mask_m[7] << 16)
2278 | (mask_m[8] << 14) | (mask_m[9] << 12)
2279 | (mask_m[10] << 10) | (mask_m[11] << 8)
2280 | (mask_m[12] << 6) | (mask_m[13] << 4)
2281 | (mask_m[14] << 2) | (mask_m[15] << 0);
2282 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2283 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2284
2285 tmp_mask = (mask_p[15] << 28)
2286 | (mask_p[14] << 26) | (mask_p[13] << 24)
2287 | (mask_p[12] << 22) | (mask_p[11] << 20)
2288 | (mask_p[10] << 18) | (mask_p[9] << 16)
2289 | (mask_p[8] << 14) | (mask_p[7] << 12)
2290 | (mask_p[6] << 10) | (mask_p[5] << 8)
2291 | (mask_p[4] << 6) | (mask_p[3] << 4)
2292 | (mask_p[2] << 2) | (mask_p[1] << 0);
2293 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2294 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2295
2296 tmp_mask = (mask_p[30] << 28)
2297 | (mask_p[29] << 26) | (mask_p[28] << 24)
2298 | (mask_p[27] << 22) | (mask_p[26] << 20)
2299 | (mask_p[25] << 18) | (mask_p[24] << 16)
2300 | (mask_p[23] << 14) | (mask_p[22] << 12)
2301 | (mask_p[21] << 10) | (mask_p[20] << 8)
2302 | (mask_p[19] << 6) | (mask_p[18] << 4)
2303 | (mask_p[17] << 2) | (mask_p[16] << 0);
2304 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2305 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2306
2307 tmp_mask = (mask_p[45] << 28)
2308 | (mask_p[44] << 26) | (mask_p[43] << 24)
2309 | (mask_p[42] << 22) | (mask_p[41] << 20)
2310 | (mask_p[40] << 18) | (mask_p[39] << 16)
2311 | (mask_p[38] << 14) | (mask_p[37] << 12)
2312 | (mask_p[36] << 10) | (mask_p[35] << 8)
2313 | (mask_p[34] << 6) | (mask_p[33] << 4)
2314 | (mask_p[32] << 2) | (mask_p[31] << 0);
2315 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2316 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2317
2318 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2319 | (mask_p[59] << 26) | (mask_p[58] << 24)
2320 | (mask_p[57] << 22) | (mask_p[56] << 20)
2321 | (mask_p[55] << 18) | (mask_p[54] << 16)
2322 | (mask_p[53] << 14) | (mask_p[52] << 12)
2323 | (mask_p[51] << 10) | (mask_p[50] << 8)
2324 | (mask_p[49] << 6) | (mask_p[48] << 4)
2325 | (mask_p[47] << 2) | (mask_p[46] << 0);
2326 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2327 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2328}
2329
2330static void ath9k_enable_rfkill(struct ath_hw *ah) 1926static void ath9k_enable_rfkill(struct ath_hw *ah)
2331{ 1927{
2332 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, 1928 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
@@ -2342,17 +1938,16 @@ static void ath9k_enable_rfkill(struct ath_hw *ah)
2342int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 1938int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2343 bool bChannelChange) 1939 bool bChannelChange)
2344{ 1940{
1941 struct ath_common *common = ath9k_hw_common(ah);
2345 u32 saveLedState; 1942 u32 saveLedState;
2346 struct ath_softc *sc = ah->ah_sc;
2347 struct ath9k_channel *curchan = ah->curchan; 1943 struct ath9k_channel *curchan = ah->curchan;
2348 u32 saveDefAntenna; 1944 u32 saveDefAntenna;
2349 u32 macStaId1; 1945 u32 macStaId1;
2350 u64 tsf = 0; 1946 u64 tsf = 0;
2351 int i, rx_chainmask, r; 1947 int i, rx_chainmask, r;
2352 1948
2353 ah->extprotspacing = sc->ht_extprotspacing; 1949 ah->txchainmask = common->tx_chainmask;
2354 ah->txchainmask = sc->tx_chainmask; 1950 ah->rxchainmask = common->rx_chainmask;
2355 ah->rxchainmask = sc->rx_chainmask;
2356 1951
2357 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1952 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2358 return -EIO; 1953 return -EIO;
@@ -2369,7 +1964,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2369 !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) || 1964 !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
2370 IS_CHAN_A_5MHZ_SPACED(ah->curchan))) { 1965 IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
2371 1966
2372 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) { 1967 if (ath9k_hw_channel_change(ah, chan)) {
2373 ath9k_hw_loadnf(ah, ah->curchan); 1968 ath9k_hw_loadnf(ah, ah->curchan);
2374 ath9k_hw_start_nfcal(ah); 1969 ath9k_hw_start_nfcal(ah);
2375 return 0; 1970 return 0;
@@ -2400,7 +1995,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2400 } 1995 }
2401 1996
2402 if (!ath9k_hw_chip_reset(ah, chan)) { 1997 if (!ath9k_hw_chip_reset(ah, chan)) {
2403 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Chip reset failed\n"); 1998 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
2404 return -EINVAL; 1999 return -EINVAL;
2405 } 2000 }
2406 2001
@@ -2429,7 +2024,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2429 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, 2024 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2430 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET); 2025 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2431 } 2026 }
2432 r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width); 2027 r = ath9k_hw_process_ini(ah, chan);
2433 if (r) 2028 if (r)
2434 return r; 2029 return r;
2435 2030
@@ -2453,17 +2048,11 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2453 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 2048 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2454 ath9k_hw_set_delta_slope(ah, chan); 2049 ath9k_hw_set_delta_slope(ah, chan);
2455 2050
2456 if (AR_SREV_9280_10_OR_LATER(ah)) 2051 ah->ath9k_hw_spur_mitigate_freq(ah, chan);
2457 ath9k_hw_9280_spur_mitigate(ah, chan);
2458 else
2459 ath9k_hw_spur_mitigate(ah, chan);
2460
2461 ah->eep_ops->set_board_values(ah, chan); 2052 ah->eep_ops->set_board_values(ah, chan);
2462 2053
2463 ath9k_hw_decrease_chain_power(ah, chan); 2054 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
2464 2055 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
2465 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ah->macaddr));
2466 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4)
2467 | macStaId1 2056 | macStaId1
2468 | AR_STA_ID1_RTS_USE_DEF 2057 | AR_STA_ID1_RTS_USE_DEF
2469 | (ah->config. 2058 | (ah->config.
@@ -2471,24 +2060,19 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2471 | ah->sta_id1_defaults); 2060 | ah->sta_id1_defaults);
2472 ath9k_hw_set_operating_mode(ah, ah->opmode); 2061 ath9k_hw_set_operating_mode(ah, ah->opmode);
2473 2062
2474 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask)); 2063 ath_hw_setbssidmask(common);
2475 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
2476 2064
2477 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 2065 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2478 2066
2479 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid)); 2067 ath9k_hw_write_associd(ah);
2480 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
2481 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2482 2068
2483 REG_WRITE(ah, AR_ISR, ~0); 2069 REG_WRITE(ah, AR_ISR, ~0);
2484 2070
2485 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 2071 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2486 2072
2487 if (AR_SREV_9280_10_OR_LATER(ah)) 2073 r = ah->ath9k_hw_rf_set_freq(ah, chan);
2488 ath9k_hw_ar9280_set_channel(ah, chan); 2074 if (r)
2489 else 2075 return r;
2490 if (!(ath9k_hw_set_channel(ah, chan)))
2491 return -EIO;
2492 2076
2493 for (i = 0; i < AR_NUM_DCU; i++) 2077 for (i = 0; i < AR_NUM_DCU; i++)
2494 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 2078 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
@@ -2558,13 +2142,13 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2558 u32 mask; 2142 u32 mask;
2559 mask = REG_READ(ah, AR_CFG); 2143 mask = REG_READ(ah, AR_CFG);
2560 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 2144 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2561 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 2145 ath_print(common, ATH_DBG_RESET,
2562 "CFG Byte Swap Set 0x%x\n", mask); 2146 "CFG Byte Swap Set 0x%x\n", mask);
2563 } else { 2147 } else {
2564 mask = 2148 mask =
2565 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 2149 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2566 REG_WRITE(ah, AR_CFG, mask); 2150 REG_WRITE(ah, AR_CFG, mask);
2567 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 2151 ath_print(common, ATH_DBG_RESET,
2568 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG)); 2152 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2569 } 2153 }
2570 } else { 2154 } else {
@@ -2577,11 +2161,12 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2577#endif 2161#endif
2578 } 2162 }
2579 2163
2580 if (ah->ah_sc->sc_flags & SC_OP_BTCOEX_ENABLED) 2164 if (ah->btcoex_hw.enabled)
2581 ath9k_hw_btcoex_enable(ah); 2165 ath9k_hw_btcoex_enable(ah);
2582 2166
2583 return 0; 2167 return 0;
2584} 2168}
2169EXPORT_SYMBOL(ath9k_hw_reset);
2585 2170
2586/************************/ 2171/************************/
2587/* Key Cache Management */ 2172/* Key Cache Management */
@@ -2592,8 +2177,8 @@ bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2592 u32 keyType; 2177 u32 keyType;
2593 2178
2594 if (entry >= ah->caps.keycache_size) { 2179 if (entry >= ah->caps.keycache_size) {
2595 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 2180 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2596 "keychache entry %u out of range\n", entry); 2181 "keychache entry %u out of range\n", entry);
2597 return false; 2182 return false;
2598 } 2183 }
2599 2184
@@ -2620,14 +2205,15 @@ bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2620 2205
2621 return true; 2206 return true;
2622} 2207}
2208EXPORT_SYMBOL(ath9k_hw_keyreset);
2623 2209
2624bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac) 2210bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2625{ 2211{
2626 u32 macHi, macLo; 2212 u32 macHi, macLo;
2627 2213
2628 if (entry >= ah->caps.keycache_size) { 2214 if (entry >= ah->caps.keycache_size) {
2629 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 2215 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2630 "keychache entry %u out of range\n", entry); 2216 "keychache entry %u out of range\n", entry);
2631 return false; 2217 return false;
2632 } 2218 }
2633 2219
@@ -2648,18 +2234,20 @@ bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2648 2234
2649 return true; 2235 return true;
2650} 2236}
2237EXPORT_SYMBOL(ath9k_hw_keysetmac);
2651 2238
2652bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry, 2239bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2653 const struct ath9k_keyval *k, 2240 const struct ath9k_keyval *k,
2654 const u8 *mac) 2241 const u8 *mac)
2655{ 2242{
2656 const struct ath9k_hw_capabilities *pCap = &ah->caps; 2243 const struct ath9k_hw_capabilities *pCap = &ah->caps;
2244 struct ath_common *common = ath9k_hw_common(ah);
2657 u32 key0, key1, key2, key3, key4; 2245 u32 key0, key1, key2, key3, key4;
2658 u32 keyType; 2246 u32 keyType;
2659 2247
2660 if (entry >= pCap->keycache_size) { 2248 if (entry >= pCap->keycache_size) {
2661 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 2249 ath_print(common, ATH_DBG_FATAL,
2662 "keycache entry %u out of range\n", entry); 2250 "keycache entry %u out of range\n", entry);
2663 return false; 2251 return false;
2664 } 2252 }
2665 2253
@@ -2669,9 +2257,9 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2669 break; 2257 break;
2670 case ATH9K_CIPHER_AES_CCM: 2258 case ATH9K_CIPHER_AES_CCM:
2671 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) { 2259 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2672 DPRINTF(ah->ah_sc, ATH_DBG_ANY, 2260 ath_print(common, ATH_DBG_ANY,
2673 "AES-CCM not supported by mac rev 0x%x\n", 2261 "AES-CCM not supported by mac rev 0x%x\n",
2674 ah->hw_version.macRev); 2262 ah->hw_version.macRev);
2675 return false; 2263 return false;
2676 } 2264 }
2677 keyType = AR_KEYTABLE_TYPE_CCM; 2265 keyType = AR_KEYTABLE_TYPE_CCM;
@@ -2680,15 +2268,15 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2680 keyType = AR_KEYTABLE_TYPE_TKIP; 2268 keyType = AR_KEYTABLE_TYPE_TKIP;
2681 if (ATH9K_IS_MIC_ENABLED(ah) 2269 if (ATH9K_IS_MIC_ENABLED(ah)
2682 && entry + 64 >= pCap->keycache_size) { 2270 && entry + 64 >= pCap->keycache_size) {
2683 DPRINTF(ah->ah_sc, ATH_DBG_ANY, 2271 ath_print(common, ATH_DBG_ANY,
2684 "entry %u inappropriate for TKIP\n", entry); 2272 "entry %u inappropriate for TKIP\n", entry);
2685 return false; 2273 return false;
2686 } 2274 }
2687 break; 2275 break;
2688 case ATH9K_CIPHER_WEP: 2276 case ATH9K_CIPHER_WEP:
2689 if (k->kv_len < WLAN_KEY_LEN_WEP40) { 2277 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
2690 DPRINTF(ah->ah_sc, ATH_DBG_ANY, 2278 ath_print(common, ATH_DBG_ANY,
2691 "WEP key length %u too small\n", k->kv_len); 2279 "WEP key length %u too small\n", k->kv_len);
2692 return false; 2280 return false;
2693 } 2281 }
2694 if (k->kv_len <= WLAN_KEY_LEN_WEP40) 2282 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
@@ -2702,8 +2290,8 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2702 keyType = AR_KEYTABLE_TYPE_CLR; 2290 keyType = AR_KEYTABLE_TYPE_CLR;
2703 break; 2291 break;
2704 default: 2292 default:
2705 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 2293 ath_print(common, ATH_DBG_FATAL,
2706 "cipher %u not supported\n", k->kv_type); 2294 "cipher %u not supported\n", k->kv_type);
2707 return false; 2295 return false;
2708 } 2296 }
2709 2297
@@ -2845,6 +2433,7 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2845 2433
2846 return true; 2434 return true;
2847} 2435}
2436EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
2848 2437
2849bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry) 2438bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2850{ 2439{
@@ -2855,6 +2444,7 @@ bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2855 } 2444 }
2856 return false; 2445 return false;
2857} 2446}
2447EXPORT_SYMBOL(ath9k_hw_keyisvalid);
2858 2448
2859/******************************/ 2449/******************************/
2860/* Power Management (Chipset) */ 2450/* Power Management (Chipset) */
@@ -2869,8 +2459,9 @@ static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2869 if (!AR_SREV_9100(ah)) 2459 if (!AR_SREV_9100(ah))
2870 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 2460 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2871 2461
2872 REG_CLR_BIT(ah, (AR_RTC_RESET), 2462 if(!AR_SREV_5416(ah))
2873 AR_RTC_RESET_EN); 2463 REG_CLR_BIT(ah, (AR_RTC_RESET),
2464 AR_RTC_RESET_EN);
2874 } 2465 }
2875} 2466}
2876 2467
@@ -2902,6 +2493,7 @@ static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2902 ATH9K_RESET_POWER_ON) != true) { 2493 ATH9K_RESET_POWER_ON) != true) {
2903 return false; 2494 return false;
2904 } 2495 }
2496 ath9k_hw_init_pll(ah, NULL);
2905 } 2497 }
2906 if (AR_SREV_9100(ah)) 2498 if (AR_SREV_9100(ah))
2907 REG_SET_BIT(ah, AR_RTC_RESET, 2499 REG_SET_BIT(ah, AR_RTC_RESET,
@@ -2920,8 +2512,9 @@ static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2920 AR_RTC_FORCE_WAKE_EN); 2512 AR_RTC_FORCE_WAKE_EN);
2921 } 2513 }
2922 if (i == 0) { 2514 if (i == 0) {
2923 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 2515 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2924 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20); 2516 "Failed to wakeup in %uus\n",
2517 POWER_UP_TIME / 20);
2925 return false; 2518 return false;
2926 } 2519 }
2927 } 2520 }
@@ -2931,9 +2524,9 @@ static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2931 return true; 2524 return true;
2932} 2525}
2933 2526
2934static bool ath9k_hw_setpower_nolock(struct ath_hw *ah, 2527bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2935 enum ath9k_power_mode mode)
2936{ 2528{
2529 struct ath_common *common = ath9k_hw_common(ah);
2937 int status = true, setChip = true; 2530 int status = true, setChip = true;
2938 static const char *modes[] = { 2531 static const char *modes[] = {
2939 "AWAKE", 2532 "AWAKE",
@@ -2945,8 +2538,8 @@ static bool ath9k_hw_setpower_nolock(struct ath_hw *ah,
2945 if (ah->power_mode == mode) 2538 if (ah->power_mode == mode)
2946 return status; 2539 return status;
2947 2540
2948 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s -> %s\n", 2541 ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
2949 modes[ah->power_mode], modes[mode]); 2542 modes[ah->power_mode], modes[mode]);
2950 2543
2951 switch (mode) { 2544 switch (mode) {
2952 case ATH9K_PM_AWAKE: 2545 case ATH9K_PM_AWAKE:
@@ -2960,59 +2553,15 @@ static bool ath9k_hw_setpower_nolock(struct ath_hw *ah,
2960 ath9k_set_power_network_sleep(ah, setChip); 2553 ath9k_set_power_network_sleep(ah, setChip);
2961 break; 2554 break;
2962 default: 2555 default:
2963 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 2556 ath_print(common, ATH_DBG_FATAL,
2964 "Unknown power mode %u\n", mode); 2557 "Unknown power mode %u\n", mode);
2965 return false; 2558 return false;
2966 } 2559 }
2967 ah->power_mode = mode; 2560 ah->power_mode = mode;
2968 2561
2969 return status; 2562 return status;
2970} 2563}
2971 2564EXPORT_SYMBOL(ath9k_hw_setpower);
2972bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2973{
2974 unsigned long flags;
2975 bool ret;
2976
2977 spin_lock_irqsave(&ah->ah_sc->sc_pm_lock, flags);
2978 ret = ath9k_hw_setpower_nolock(ah, mode);
2979 spin_unlock_irqrestore(&ah->ah_sc->sc_pm_lock, flags);
2980
2981 return ret;
2982}
2983
2984void ath9k_ps_wakeup(struct ath_softc *sc)
2985{
2986 unsigned long flags;
2987
2988 spin_lock_irqsave(&sc->sc_pm_lock, flags);
2989 if (++sc->ps_usecount != 1)
2990 goto unlock;
2991
2992 ath9k_hw_setpower_nolock(sc->sc_ah, ATH9K_PM_AWAKE);
2993
2994 unlock:
2995 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2996}
2997
2998void ath9k_ps_restore(struct ath_softc *sc)
2999{
3000 unsigned long flags;
3001
3002 spin_lock_irqsave(&sc->sc_pm_lock, flags);
3003 if (--sc->ps_usecount != 0)
3004 goto unlock;
3005
3006 if (sc->ps_enabled &&
3007 !(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
3008 SC_OP_WAIT_FOR_CAB |
3009 SC_OP_WAIT_FOR_PSPOLL_DATA |
3010 SC_OP_WAIT_FOR_TX_ACK)))
3011 ath9k_hw_setpower_nolock(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
3012
3013 unlock:
3014 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
3015}
3016 2565
3017/* 2566/*
3018 * Helper for ASPM support. 2567 * Helper for ASPM support.
@@ -3145,6 +2694,7 @@ void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
3145 } 2694 }
3146 } 2695 }
3147} 2696}
2697EXPORT_SYMBOL(ath9k_hw_configpcipowersave);
3148 2698
3149/**********************/ 2699/**********************/
3150/* Interrupt Handling */ 2700/* Interrupt Handling */
@@ -3168,6 +2718,7 @@ bool ath9k_hw_intrpend(struct ath_hw *ah)
3168 2718
3169 return false; 2719 return false;
3170} 2720}
2721EXPORT_SYMBOL(ath9k_hw_intrpend);
3171 2722
3172bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked) 2723bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
3173{ 2724{
@@ -3176,6 +2727,7 @@ bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
3176 struct ath9k_hw_capabilities *pCap = &ah->caps; 2727 struct ath9k_hw_capabilities *pCap = &ah->caps;
3177 u32 sync_cause = 0; 2728 u32 sync_cause = 0;
3178 bool fatal_int = false; 2729 bool fatal_int = false;
2730 struct ath_common *common = ath9k_hw_common(ah);
3179 2731
3180 if (!AR_SREV_9100(ah)) { 2732 if (!AR_SREV_9100(ah)) {
3181 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) { 2733 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
@@ -3249,8 +2801,8 @@ bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
3249 } 2801 }
3250 2802
3251 if (isr & AR_ISR_RXORN) { 2803 if (isr & AR_ISR_RXORN) {
3252 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, 2804 ath_print(common, ATH_DBG_INTERRUPT,
3253 "receive FIFO overrun interrupt\n"); 2805 "receive FIFO overrun interrupt\n");
3254 } 2806 }
3255 2807
3256 if (!AR_SREV_9100(ah)) { 2808 if (!AR_SREV_9100(ah)) {
@@ -3292,25 +2844,25 @@ bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
3292 2844
3293 if (fatal_int) { 2845 if (fatal_int) {
3294 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) { 2846 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
3295 DPRINTF(ah->ah_sc, ATH_DBG_ANY, 2847 ath_print(common, ATH_DBG_ANY,
3296 "received PCI FATAL interrupt\n"); 2848 "received PCI FATAL interrupt\n");
3297 } 2849 }
3298 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) { 2850 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
3299 DPRINTF(ah->ah_sc, ATH_DBG_ANY, 2851 ath_print(common, ATH_DBG_ANY,
3300 "received PCI PERR interrupt\n"); 2852 "received PCI PERR interrupt\n");
3301 } 2853 }
3302 *masked |= ATH9K_INT_FATAL; 2854 *masked |= ATH9K_INT_FATAL;
3303 } 2855 }
3304 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { 2856 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
3305 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, 2857 ath_print(common, ATH_DBG_INTERRUPT,
3306 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n"); 2858 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
3307 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); 2859 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
3308 REG_WRITE(ah, AR_RC, 0); 2860 REG_WRITE(ah, AR_RC, 0);
3309 *masked |= ATH9K_INT_FATAL; 2861 *masked |= ATH9K_INT_FATAL;
3310 } 2862 }
3311 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) { 2863 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
3312 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, 2864 ath_print(common, ATH_DBG_INTERRUPT,
3313 "AR_INTR_SYNC_LOCAL_TIMEOUT\n"); 2865 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
3314 } 2866 }
3315 2867
3316 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); 2868 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
@@ -3319,17 +2871,19 @@ bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
3319 2871
3320 return true; 2872 return true;
3321} 2873}
2874EXPORT_SYMBOL(ath9k_hw_getisr);
3322 2875
3323enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints) 2876enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3324{ 2877{
3325 u32 omask = ah->mask_reg; 2878 u32 omask = ah->mask_reg;
3326 u32 mask, mask2; 2879 u32 mask, mask2;
3327 struct ath9k_hw_capabilities *pCap = &ah->caps; 2880 struct ath9k_hw_capabilities *pCap = &ah->caps;
2881 struct ath_common *common = ath9k_hw_common(ah);
3328 2882
3329 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints); 2883 ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
3330 2884
3331 if (omask & ATH9K_INT_GLOBAL) { 2885 if (omask & ATH9K_INT_GLOBAL) {
3332 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n"); 2886 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
3333 REG_WRITE(ah, AR_IER, AR_IER_DISABLE); 2887 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3334 (void) REG_READ(ah, AR_IER); 2888 (void) REG_READ(ah, AR_IER);
3335 if (!AR_SREV_9100(ah)) { 2889 if (!AR_SREV_9100(ah)) {
@@ -3386,7 +2940,7 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3386 mask2 |= AR_IMR_S2_CST; 2940 mask2 |= AR_IMR_S2_CST;
3387 } 2941 }
3388 2942
3389 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask); 2943 ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
3390 REG_WRITE(ah, AR_IMR, mask); 2944 REG_WRITE(ah, AR_IMR, mask);
3391 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM | 2945 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3392 AR_IMR_S2_DTIM | 2946 AR_IMR_S2_DTIM |
@@ -3406,7 +2960,7 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3406 } 2960 }
3407 2961
3408 if (ints & ATH9K_INT_GLOBAL) { 2962 if (ints & ATH9K_INT_GLOBAL) {
3409 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n"); 2963 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
3410 REG_WRITE(ah, AR_IER, AR_IER_ENABLE); 2964 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3411 if (!AR_SREV_9100(ah)) { 2965 if (!AR_SREV_9100(ah)) {
3412 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 2966 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
@@ -3419,12 +2973,13 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3419 REG_WRITE(ah, AR_INTR_SYNC_MASK, 2973 REG_WRITE(ah, AR_INTR_SYNC_MASK,
3420 AR_INTR_SYNC_DEFAULT); 2974 AR_INTR_SYNC_DEFAULT);
3421 } 2975 }
3422 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n", 2976 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3423 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER)); 2977 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3424 } 2978 }
3425 2979
3426 return omask; 2980 return omask;
3427} 2981}
2982EXPORT_SYMBOL(ath9k_hw_set_interrupts);
3428 2983
3429/*******************/ 2984/*******************/
3430/* Beacon Handling */ 2985/* Beacon Handling */
@@ -3467,9 +3022,9 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3467 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 3022 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3468 break; 3023 break;
3469 default: 3024 default:
3470 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, 3025 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
3471 "%s: unsupported opmode: %d\n", 3026 "%s: unsupported opmode: %d\n",
3472 __func__, ah->opmode); 3027 __func__, ah->opmode);
3473 return; 3028 return;
3474 break; 3029 break;
3475 } 3030 }
@@ -3481,18 +3036,19 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3481 3036
3482 beacon_period &= ~ATH9K_BEACON_ENA; 3037 beacon_period &= ~ATH9K_BEACON_ENA;
3483 if (beacon_period & ATH9K_BEACON_RESET_TSF) { 3038 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3484 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3485 ath9k_hw_reset_tsf(ah); 3039 ath9k_hw_reset_tsf(ah);
3486 } 3040 }
3487 3041
3488 REG_SET_BIT(ah, AR_TIMER_MODE, flags); 3042 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3489} 3043}
3044EXPORT_SYMBOL(ath9k_hw_beaconinit);
3490 3045
3491void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 3046void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3492 const struct ath9k_beacon_state *bs) 3047 const struct ath9k_beacon_state *bs)
3493{ 3048{
3494 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; 3049 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3495 struct ath9k_hw_capabilities *pCap = &ah->caps; 3050 struct ath9k_hw_capabilities *pCap = &ah->caps;
3051 struct ath_common *common = ath9k_hw_common(ah);
3496 3052
3497 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); 3053 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3498 3054
@@ -3518,10 +3074,10 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3518 else 3074 else
3519 nextTbtt = bs->bs_nexttbtt; 3075 nextTbtt = bs->bs_nexttbtt;
3520 3076
3521 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim); 3077 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3522 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt); 3078 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3523 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval); 3079 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3524 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod); 3080 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3525 3081
3526 REG_WRITE(ah, AR_NEXT_DTIM, 3082 REG_WRITE(ah, AR_NEXT_DTIM,
3527 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); 3083 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
@@ -3549,6 +3105,7 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3549 /* TSF Out of Range Threshold */ 3105 /* TSF Out of Range Threshold */
3550 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); 3106 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3551} 3107}
3108EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
3552 3109
3553/*******************/ 3110/*******************/
3554/* HW Capabilities */ 3111/* HW Capabilities */
@@ -3558,7 +3115,8 @@ void ath9k_hw_fill_cap_info(struct ath_hw *ah)
3558{ 3115{
3559 struct ath9k_hw_capabilities *pCap = &ah->caps; 3116 struct ath9k_hw_capabilities *pCap = &ah->caps;
3560 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 3117 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3561 struct ath_btcoex_info *btcoex_info = &ah->ah_sc->btcoex_info; 3118 struct ath_common *common = ath9k_hw_common(ah);
3119 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
3562 3120
3563 u16 capField = 0, eeval; 3121 u16 capField = 0, eeval;
3564 3122
@@ -3579,8 +3137,8 @@ void ath9k_hw_fill_cap_info(struct ath_hw *ah)
3579 regulatory->current_rd += 5; 3137 regulatory->current_rd += 5;
3580 else if (regulatory->current_rd == 0x41) 3138 else if (regulatory->current_rd == 0x41)
3581 regulatory->current_rd = 0x43; 3139 regulatory->current_rd = 0x43;
3582 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, 3140 ath_print(common, ATH_DBG_REGULATORY,
3583 "regdomain mapped to 0x%x\n", regulatory->current_rd); 3141 "regdomain mapped to 0x%x\n", regulatory->current_rd);
3584 } 3142 }
3585 3143
3586 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); 3144 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
@@ -3719,7 +3277,10 @@ void ath9k_hw_fill_cap_info(struct ath_hw *ah)
3719 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN; 3277 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3720 } 3278 }
3721 3279
3722 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND; 3280 /* Advertise midband for AR5416 with FCC midband set in eeprom */
3281 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
3282 AR_SREV_5416(ah))
3283 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3723 3284
3724 pCap->num_antcfg_5ghz = 3285 pCap->num_antcfg_5ghz =
3725 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ); 3286 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
@@ -3727,18 +3288,18 @@ void ath9k_hw_fill_cap_info(struct ath_hw *ah)
3727 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ); 3288 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3728 3289
3729 if (AR_SREV_9280_10_OR_LATER(ah) && 3290 if (AR_SREV_9280_10_OR_LATER(ah) &&
3730 ath_btcoex_supported(ah->hw_version.subsysid)) { 3291 ath9k_hw_btcoex_supported(ah)) {
3731 btcoex_info->btactive_gpio = ATH_BTACTIVE_GPIO; 3292 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
3732 btcoex_info->wlanactive_gpio = ATH_WLANACTIVE_GPIO; 3293 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
3733 3294
3734 if (AR_SREV_9285(ah)) { 3295 if (AR_SREV_9285(ah)) {
3735 btcoex_info->btcoex_scheme = ATH_BTCOEX_CFG_3WIRE; 3296 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
3736 btcoex_info->btpriority_gpio = ATH_BTPRIORITY_GPIO; 3297 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
3737 } else { 3298 } else {
3738 btcoex_info->btcoex_scheme = ATH_BTCOEX_CFG_2WIRE; 3299 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
3739 } 3300 }
3740 } else { 3301 } else {
3741 btcoex_info->btcoex_scheme = ATH_BTCOEX_CFG_NONE; 3302 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
3742 } 3303 }
3743} 3304}
3744 3305
@@ -3812,6 +3373,7 @@ bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3812 return false; 3373 return false;
3813 } 3374 }
3814} 3375}
3376EXPORT_SYMBOL(ath9k_hw_getcapability);
3815 3377
3816bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type, 3378bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3817 u32 capability, u32 setting, int *status) 3379 u32 capability, u32 setting, int *status)
@@ -3845,6 +3407,7 @@ bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3845 return false; 3407 return false;
3846 } 3408 }
3847} 3409}
3410EXPORT_SYMBOL(ath9k_hw_setcapability);
3848 3411
3849/****************************/ 3412/****************************/
3850/* GPIO / RFKILL / Antennae */ 3413/* GPIO / RFKILL / Antennae */
@@ -3882,7 +3445,7 @@ void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3882{ 3445{
3883 u32 gpio_shift; 3446 u32 gpio_shift;
3884 3447
3885 ASSERT(gpio < ah->caps.num_gpio_pins); 3448 BUG_ON(gpio >= ah->caps.num_gpio_pins);
3886 3449
3887 gpio_shift = gpio << 1; 3450 gpio_shift = gpio << 1;
3888 3451
@@ -3891,6 +3454,7 @@ void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3891 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), 3454 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3892 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 3455 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3893} 3456}
3457EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
3894 3458
3895u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) 3459u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3896{ 3460{
@@ -3909,6 +3473,7 @@ u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3909 else 3473 else
3910 return MS_REG_READ(AR, gpio) != 0; 3474 return MS_REG_READ(AR, gpio) != 0;
3911} 3475}
3476EXPORT_SYMBOL(ath9k_hw_gpio_get);
3912 3477
3913void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 3478void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3914 u32 ah_signal_type) 3479 u32 ah_signal_type)
@@ -3924,67 +3489,26 @@ void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3924 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), 3489 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3925 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 3490 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3926} 3491}
3492EXPORT_SYMBOL(ath9k_hw_cfg_output);
3927 3493
3928void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) 3494void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3929{ 3495{
3930 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), 3496 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3931 AR_GPIO_BIT(gpio)); 3497 AR_GPIO_BIT(gpio));
3932} 3498}
3499EXPORT_SYMBOL(ath9k_hw_set_gpio);
3933 3500
3934u32 ath9k_hw_getdefantenna(struct ath_hw *ah) 3501u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3935{ 3502{
3936 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7; 3503 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3937} 3504}
3505EXPORT_SYMBOL(ath9k_hw_getdefantenna);
3938 3506
3939void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) 3507void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3940{ 3508{
3941 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 3509 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3942} 3510}
3943 3511EXPORT_SYMBOL(ath9k_hw_setantenna);
3944bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
3945 enum ath9k_ant_setting settings,
3946 struct ath9k_channel *chan,
3947 u8 *tx_chainmask,
3948 u8 *rx_chainmask,
3949 u8 *antenna_cfgd)
3950{
3951 static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3952
3953 if (AR_SREV_9280(ah)) {
3954 if (!tx_chainmask_cfg) {
3955
3956 tx_chainmask_cfg = *tx_chainmask;
3957 rx_chainmask_cfg = *rx_chainmask;
3958 }
3959
3960 switch (settings) {
3961 case ATH9K_ANT_FIXED_A:
3962 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3963 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3964 *antenna_cfgd = true;
3965 break;
3966 case ATH9K_ANT_FIXED_B:
3967 if (ah->caps.tx_chainmask >
3968 ATH9K_ANTENNA1_CHAINMASK) {
3969 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3970 }
3971 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3972 *antenna_cfgd = true;
3973 break;
3974 case ATH9K_ANT_VARIABLE:
3975 *tx_chainmask = tx_chainmask_cfg;
3976 *rx_chainmask = rx_chainmask_cfg;
3977 *antenna_cfgd = true;
3978 break;
3979 default:
3980 break;
3981 }
3982 } else {
3983 ah->config.diversity_control = settings;
3984 }
3985
3986 return true;
3987}
3988 3512
3989/*********************/ 3513/*********************/
3990/* General Operation */ 3514/* General Operation */
@@ -4002,6 +3526,7 @@ u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
4002 3526
4003 return bits; 3527 return bits;
4004} 3528}
3529EXPORT_SYMBOL(ath9k_hw_getrxfilter);
4005 3530
4006void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) 3531void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
4007{ 3532{
@@ -4023,19 +3548,30 @@ void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
4023 REG_WRITE(ah, AR_RXCFG, 3548 REG_WRITE(ah, AR_RXCFG,
4024 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA); 3549 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
4025} 3550}
3551EXPORT_SYMBOL(ath9k_hw_setrxfilter);
4026 3552
4027bool ath9k_hw_phy_disable(struct ath_hw *ah) 3553bool ath9k_hw_phy_disable(struct ath_hw *ah)
4028{ 3554{
4029 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM); 3555 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
3556 return false;
3557
3558 ath9k_hw_init_pll(ah, NULL);
3559 return true;
4030} 3560}
3561EXPORT_SYMBOL(ath9k_hw_phy_disable);
4031 3562
4032bool ath9k_hw_disable(struct ath_hw *ah) 3563bool ath9k_hw_disable(struct ath_hw *ah)
4033{ 3564{
4034 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 3565 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
4035 return false; 3566 return false;
4036 3567
4037 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD); 3568 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
3569 return false;
3570
3571 ath9k_hw_init_pll(ah, NULL);
3572 return true;
4038} 3573}
3574EXPORT_SYMBOL(ath9k_hw_disable);
4039 3575
4040void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit) 3576void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
4041{ 3577{
@@ -4052,35 +3588,36 @@ void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
4052 min((u32) MAX_RATE_POWER, 3588 min((u32) MAX_RATE_POWER,
4053 (u32) regulatory->power_limit)); 3589 (u32) regulatory->power_limit));
4054} 3590}
3591EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
4055 3592
4056void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac) 3593void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
4057{ 3594{
4058 memcpy(ah->macaddr, mac, ETH_ALEN); 3595 memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
4059} 3596}
3597EXPORT_SYMBOL(ath9k_hw_setmac);
4060 3598
4061void ath9k_hw_setopmode(struct ath_hw *ah) 3599void ath9k_hw_setopmode(struct ath_hw *ah)
4062{ 3600{
4063 ath9k_hw_set_operating_mode(ah, ah->opmode); 3601 ath9k_hw_set_operating_mode(ah, ah->opmode);
4064} 3602}
3603EXPORT_SYMBOL(ath9k_hw_setopmode);
4065 3604
4066void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) 3605void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
4067{ 3606{
4068 REG_WRITE(ah, AR_MCAST_FIL0, filter0); 3607 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
4069 REG_WRITE(ah, AR_MCAST_FIL1, filter1); 3608 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
4070} 3609}
3610EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
4071 3611
4072void ath9k_hw_setbssidmask(struct ath_softc *sc) 3612void ath9k_hw_write_associd(struct ath_hw *ah)
4073{ 3613{
4074 REG_WRITE(sc->sc_ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask)); 3614 struct ath_common *common = ath9k_hw_common(ah);
4075 REG_WRITE(sc->sc_ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
4076}
4077 3615
4078void ath9k_hw_write_associd(struct ath_softc *sc) 3616 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
4079{ 3617 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
4080 REG_WRITE(sc->sc_ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid)); 3618 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
4081 REG_WRITE(sc->sc_ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
4082 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
4083} 3619}
3620EXPORT_SYMBOL(ath9k_hw_write_associd);
4084 3621
4085u64 ath9k_hw_gettsf64(struct ath_hw *ah) 3622u64 ath9k_hw_gettsf64(struct ath_hw *ah)
4086{ 3623{
@@ -4091,24 +3628,25 @@ u64 ath9k_hw_gettsf64(struct ath_hw *ah)
4091 3628
4092 return tsf; 3629 return tsf;
4093} 3630}
3631EXPORT_SYMBOL(ath9k_hw_gettsf64);
4094 3632
4095void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) 3633void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
4096{ 3634{
4097 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); 3635 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
4098 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); 3636 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
4099} 3637}
3638EXPORT_SYMBOL(ath9k_hw_settsf64);
4100 3639
4101void ath9k_hw_reset_tsf(struct ath_hw *ah) 3640void ath9k_hw_reset_tsf(struct ath_hw *ah)
4102{ 3641{
4103 ath9k_ps_wakeup(ah->ah_sc);
4104 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, 3642 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
4105 AH_TSF_WRITE_TIMEOUT)) 3643 AH_TSF_WRITE_TIMEOUT))
4106 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 3644 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
4107 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); 3645 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
4108 3646
4109 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 3647 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
4110 ath9k_ps_restore(ah->ah_sc);
4111} 3648}
3649EXPORT_SYMBOL(ath9k_hw_reset_tsf);
4112 3650
4113void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting) 3651void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
4114{ 3652{
@@ -4117,11 +3655,28 @@ void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
4117 else 3655 else
4118 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; 3656 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
4119} 3657}
3658EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
3659
3660/*
3661 * Extend 15-bit time stamp from rx descriptor to
3662 * a full 64-bit TSF using the current h/w TSF.
3663*/
3664u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
3665{
3666 u64 tsf;
3667
3668 tsf = ath9k_hw_gettsf64(ah);
3669 if ((tsf & 0x7fff) < rstamp)
3670 tsf -= 0x8000;
3671 return (tsf & ~0x7fff) | rstamp;
3672}
3673EXPORT_SYMBOL(ath9k_hw_extend_tsf);
4120 3674
4121bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us) 3675bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
4122{ 3676{
4123 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) { 3677 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
4124 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us); 3678 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
3679 "bad slot time %u\n", us);
4125 ah->slottime = (u32) -1; 3680 ah->slottime = (u32) -1;
4126 return false; 3681 return false;
4127 } else { 3682 } else {
@@ -4130,13 +3685,14 @@ bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
4130 return true; 3685 return true;
4131 } 3686 }
4132} 3687}
3688EXPORT_SYMBOL(ath9k_hw_setslottime);
4133 3689
4134void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode) 3690void ath9k_hw_set11nmac2040(struct ath_hw *ah)
4135{ 3691{
3692 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
4136 u32 macmode; 3693 u32 macmode;
4137 3694
4138 if (mode == ATH9K_HT_MACMODE_2040 && 3695 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
4139 !ah->config.cwm_ignore_extcca)
4140 macmode = AR_2040_JOINED_RX_CLEAR; 3696 macmode = AR_2040_JOINED_RX_CLEAR;
4141 else 3697 else
4142 macmode = 0; 3698 macmode = 0;
@@ -4193,6 +3749,7 @@ u32 ath9k_hw_gettsf32(struct ath_hw *ah)
4193{ 3749{
4194 return REG_READ(ah, AR_TSF_L32); 3750 return REG_READ(ah, AR_TSF_L32);
4195} 3751}
3752EXPORT_SYMBOL(ath9k_hw_gettsf32);
4196 3753
4197struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 3754struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
4198 void (*trigger)(void *), 3755 void (*trigger)(void *),
@@ -4206,8 +3763,9 @@ struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
4206 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); 3763 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
4207 3764
4208 if (timer == NULL) { 3765 if (timer == NULL) {
4209 printk(KERN_DEBUG "Failed to allocate memory" 3766 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
4210 "for hw timer[%d]\n", timer_index); 3767 "Failed to allocate memory"
3768 "for hw timer[%d]\n", timer_index);
4211 return NULL; 3769 return NULL;
4212 } 3770 }
4213 3771
@@ -4220,10 +3778,12 @@ struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
4220 3778
4221 return timer; 3779 return timer;
4222} 3780}
3781EXPORT_SYMBOL(ath_gen_timer_alloc);
4223 3782
4224void ath_gen_timer_start(struct ath_hw *ah, 3783void ath9k_hw_gen_timer_start(struct ath_hw *ah,
4225 struct ath_gen_timer *timer, 3784 struct ath_gen_timer *timer,
4226 u32 timer_next, u32 timer_period) 3785 u32 timer_next,
3786 u32 timer_period)
4227{ 3787{
4228 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3788 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4229 u32 tsf; 3789 u32 tsf;
@@ -4234,8 +3794,9 @@ void ath_gen_timer_start(struct ath_hw *ah,
4234 3794
4235 tsf = ath9k_hw_gettsf32(ah); 3795 tsf = ath9k_hw_gettsf32(ah);
4236 3796
4237 DPRINTF(ah->ah_sc, ATH_DBG_HWTIMER, "curent tsf %x period %x" 3797 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
4238 "timer_next %x\n", tsf, timer_period, timer_next); 3798 "curent tsf %x period %x"
3799 "timer_next %x\n", tsf, timer_period, timer_next);
4239 3800
4240 /* 3801 /*
4241 * Pull timer_next forward if the current TSF already passed it 3802 * Pull timer_next forward if the current TSF already passed it
@@ -4258,15 +3819,10 @@ void ath_gen_timer_start(struct ath_hw *ah,
4258 REG_SET_BIT(ah, AR_IMR_S5, 3819 REG_SET_BIT(ah, AR_IMR_S5,
4259 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 3820 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
4260 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 3821 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
4261
4262 if ((ah->ah_sc->imask & ATH9K_INT_GENTIMER) == 0) {
4263 ath9k_hw_set_interrupts(ah, 0);
4264 ah->ah_sc->imask |= ATH9K_INT_GENTIMER;
4265 ath9k_hw_set_interrupts(ah, ah->ah_sc->imask);
4266 }
4267} 3822}
3823EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
4268 3824
4269void ath_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) 3825void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
4270{ 3826{
4271 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3827 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4272 3828
@@ -4285,14 +3841,8 @@ void ath_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
4285 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 3841 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
4286 3842
4287 clear_bit(timer->index, &timer_table->timer_mask.timer_bits); 3843 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
4288
4289 /* if no timer is enabled, turn off interrupt mask */
4290 if (timer_table->timer_mask.val == 0) {
4291 ath9k_hw_set_interrupts(ah, 0);
4292 ah->ah_sc->imask &= ~ATH9K_INT_GENTIMER;
4293 ath9k_hw_set_interrupts(ah, ah->ah_sc->imask);
4294 }
4295} 3844}
3845EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
4296 3846
4297void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) 3847void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
4298{ 3848{
@@ -4302,6 +3852,7 @@ void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
4302 timer_table->timers[timer->index] = NULL; 3852 timer_table->timers[timer->index] = NULL;
4303 kfree(timer); 3853 kfree(timer);
4304} 3854}
3855EXPORT_SYMBOL(ath_gen_timer_free);
4305 3856
4306/* 3857/*
4307 * Generic Timer Interrupts handling 3858 * Generic Timer Interrupts handling
@@ -4310,6 +3861,7 @@ void ath_gen_timer_isr(struct ath_hw *ah)
4310{ 3861{
4311 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3862 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4312 struct ath_gen_timer *timer; 3863 struct ath_gen_timer *timer;
3864 struct ath_common *common = ath9k_hw_common(ah);
4313 u32 trigger_mask, thresh_mask, index; 3865 u32 trigger_mask, thresh_mask, index;
4314 3866
4315 /* get hardware generic timer interrupt status */ 3867 /* get hardware generic timer interrupt status */
@@ -4324,8 +3876,8 @@ void ath_gen_timer_isr(struct ath_hw *ah)
4324 index = rightmost_index(timer_table, &thresh_mask); 3876 index = rightmost_index(timer_table, &thresh_mask);
4325 timer = timer_table->timers[index]; 3877 timer = timer_table->timers[index];
4326 BUG_ON(!timer); 3878 BUG_ON(!timer);
4327 DPRINTF(ah->ah_sc, ATH_DBG_HWTIMER, 3879 ath_print(common, ATH_DBG_HWTIMER,
4328 "TSF overflow for Gen timer %d\n", index); 3880 "TSF overflow for Gen timer %d\n", index);
4329 timer->overflow(timer->arg); 3881 timer->overflow(timer->arg);
4330 } 3882 }
4331 3883
@@ -4333,21 +3885,95 @@ void ath_gen_timer_isr(struct ath_hw *ah)
4333 index = rightmost_index(timer_table, &trigger_mask); 3885 index = rightmost_index(timer_table, &trigger_mask);
4334 timer = timer_table->timers[index]; 3886 timer = timer_table->timers[index];
4335 BUG_ON(!timer); 3887 BUG_ON(!timer);
4336 DPRINTF(ah->ah_sc, ATH_DBG_HWTIMER, 3888 ath_print(common, ATH_DBG_HWTIMER,
4337 "Gen timer[%d] trigger\n", index); 3889 "Gen timer[%d] trigger\n", index);
4338 timer->trigger(timer->arg); 3890 timer->trigger(timer->arg);
4339 } 3891 }
4340} 3892}
3893EXPORT_SYMBOL(ath_gen_timer_isr);
3894
3895static struct {
3896 u32 version;
3897 const char * name;
3898} ath_mac_bb_names[] = {
3899 /* Devices with external radios */
3900 { AR_SREV_VERSION_5416_PCI, "5416" },
3901 { AR_SREV_VERSION_5416_PCIE, "5418" },
3902 { AR_SREV_VERSION_9100, "9100" },
3903 { AR_SREV_VERSION_9160, "9160" },
3904 /* Single-chip solutions */
3905 { AR_SREV_VERSION_9280, "9280" },
3906 { AR_SREV_VERSION_9285, "9285" },
3907 { AR_SREV_VERSION_9287, "9287" },
3908 { AR_SREV_VERSION_9271, "9271" },
3909};
3910
3911/* For devices with external radios */
3912static struct {
3913 u16 version;
3914 const char * name;
3915} ath_rf_names[] = {
3916 { 0, "5133" },
3917 { AR_RAD5133_SREV_MAJOR, "5133" },
3918 { AR_RAD5122_SREV_MAJOR, "5122" },
3919 { AR_RAD2133_SREV_MAJOR, "2133" },
3920 { AR_RAD2122_SREV_MAJOR, "2122" }
3921};
3922
3923/*
3924 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3925 */
3926static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
3927{
3928 int i;
3929
3930 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3931 if (ath_mac_bb_names[i].version == mac_bb_version) {
3932 return ath_mac_bb_names[i].name;
3933 }
3934 }
3935
3936 return "????";
3937}
4341 3938
4342/* 3939/*
4343 * Primitive to disable ASPM 3940 * Return the RF name. "????" is returned if the RF is unknown.
3941 * Used for devices with external radios.
4344 */ 3942 */
4345void ath_pcie_aspm_disable(struct ath_softc *sc) 3943static const char *ath9k_hw_rf_name(u16 rf_version)
4346{ 3944{
4347 struct pci_dev *pdev = to_pci_dev(sc->dev); 3945 int i;
4348 u8 aspm; 3946
3947 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3948 if (ath_rf_names[i].version == rf_version) {
3949 return ath_rf_names[i].name;
3950 }
3951 }
3952
3953 return "????";
3954}
3955
3956void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3957{
3958 int used;
3959
3960 /* chipsets >= AR9280 are single-chip */
3961 if (AR_SREV_9280_10_OR_LATER(ah)) {
3962 used = snprintf(hw_name, len,
3963 "Atheros AR%s Rev:%x",
3964 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3965 ah->hw_version.macRev);
3966 }
3967 else {
3968 used = snprintf(hw_name, len,
3969 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3970 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3971 ah->hw_version.macRev,
3972 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
3973 AR_RADIO_SREV_MAJOR)),
3974 ah->hw_version.phyRev);
3975 }
4349 3976
4350 pci_read_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, &aspm); 3977 hw_name[used] = '\0';
4351 aspm &= ~(ATH_PCIE_CAP_LINK_L0S | ATH_PCIE_CAP_LINK_L1);
4352 pci_write_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, aspm);
4353} 3978}
3979EXPORT_SYMBOL(ath9k_hw_name);
diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
index b89234571829..f8f5e997162c 100644
--- a/drivers/net/wireless/ath/ath9k/hw.h
+++ b/drivers/net/wireless/ath/ath9k/hw.h
@@ -27,17 +27,24 @@
27#include "calib.h" 27#include "calib.h"
28#include "reg.h" 28#include "reg.h"
29#include "phy.h" 29#include "phy.h"
30#include "btcoex.h"
30 31
31#include "../regd.h" 32#include "../regd.h"
33#include "../debug.h"
32 34
33#define ATHEROS_VENDOR_ID 0x168c 35#define ATHEROS_VENDOR_ID 0x168c
36
34#define AR5416_DEVID_PCI 0x0023 37#define AR5416_DEVID_PCI 0x0023
35#define AR5416_DEVID_PCIE 0x0024 38#define AR5416_DEVID_PCIE 0x0024
36#define AR9160_DEVID_PCI 0x0027 39#define AR9160_DEVID_PCI 0x0027
37#define AR9280_DEVID_PCI 0x0029 40#define AR9280_DEVID_PCI 0x0029
38#define AR9280_DEVID_PCIE 0x002a 41#define AR9280_DEVID_PCIE 0x002a
39#define AR9285_DEVID_PCIE 0x002b 42#define AR9285_DEVID_PCIE 0x002b
43
40#define AR5416_AR9100_DEVID 0x000b 44#define AR5416_AR9100_DEVID 0x000b
45
46#define AR9271_USB 0x9271
47
41#define AR_SUBVENDOR_ID_NOG 0x0e11 48#define AR_SUBVENDOR_ID_NOG 0x0e11
42#define AR_SUBVENDOR_ID_NEW_A 0x7065 49#define AR_SUBVENDOR_ID_NEW_A 0x7065
43#define AR5416_MAGIC 0x19641014 50#define AR5416_MAGIC 0x19641014
@@ -49,9 +56,18 @@
49#define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa 56#define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
50#define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab 57#define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
51 58
59#define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
60
61#define ATH_DEFAULT_NOISE_FLOOR -95
62
63#define ATH9K_RSSI_BAD 0x80
64
52/* Register read/write primitives */ 65/* Register read/write primitives */
53#define REG_WRITE(_ah, _reg, _val) ath9k_iowrite32((_ah), (_reg), (_val)) 66#define REG_WRITE(_ah, _reg, _val) \
54#define REG_READ(_ah, _reg) ath9k_ioread32((_ah), (_reg)) 67 ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg))
68
69#define REG_READ(_ah, _reg) \
70 ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
55 71
56#define SM(_v, _f) (((_v) << _f##_S) & _f) 72#define SM(_v, _f) (((_v) << _f##_S) & _f)
57#define MS(_v, _f) (((_v) & _f) >> _f##_S) 73#define MS(_v, _f) (((_v) & _f) >> _f##_S)
@@ -91,7 +107,7 @@
91#define AR_GPIO_BIT(_gpio) (1 << (_gpio)) 107#define AR_GPIO_BIT(_gpio) (1 << (_gpio))
92 108
93#define BASE_ACTIVATE_DELAY 100 109#define BASE_ACTIVATE_DELAY 100
94#define RTC_PLL_SETTLE_DELAY 1000 110#define RTC_PLL_SETTLE_DELAY 100
95#define COEF_SCALE_S 24 111#define COEF_SCALE_S 24
96#define HT40_CHANNEL_CENTER_SHIFT 10 112#define HT40_CHANNEL_CENTER_SHIFT 10
97 113
@@ -132,12 +148,6 @@ enum wireless_mode {
132 ATH9K_MODE_MAX, 148 ATH9K_MODE_MAX,
133}; 149};
134 150
135enum ath9k_ant_setting {
136 ATH9K_ANT_VARIABLE = 0,
137 ATH9K_ANT_FIXED_A,
138 ATH9K_ANT_FIXED_B
139};
140
141enum ath9k_hw_caps { 151enum ath9k_hw_caps {
142 ATH9K_HW_CAP_MIC_AESCCM = BIT(0), 152 ATH9K_HW_CAP_MIC_AESCCM = BIT(0),
143 ATH9K_HW_CAP_MIC_CKIP = BIT(1), 153 ATH9K_HW_CAP_MIC_CKIP = BIT(1),
@@ -201,8 +211,6 @@ struct ath9k_ops_config {
201 u32 cck_trig_high; 211 u32 cck_trig_high;
202 u32 cck_trig_low; 212 u32 cck_trig_low;
203 u32 enable_ani; 213 u32 enable_ani;
204 enum ath9k_ant_setting diversity_control;
205 u16 antenna_switch_swap;
206 int serialize_regmode; 214 int serialize_regmode;
207 bool intr_mitigation; 215 bool intr_mitigation;
208#define SPUR_DISABLE 0 216#define SPUR_DISABLE 0
@@ -407,7 +415,7 @@ struct ath9k_hw_version {
407 * Using de Bruijin sequence to to look up 1's index in a 32 bit number 415 * Using de Bruijin sequence to to look up 1's index in a 32 bit number
408 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001 416 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
409 */ 417 */
410#define debruijn32 0x077CB531UL 418#define debruijn32 0x077CB531U
411 419
412struct ath_gen_timer_configuration { 420struct ath_gen_timer_configuration {
413 u32 next_addr; 421 u32 next_addr;
@@ -433,7 +441,8 @@ struct ath_gen_timer_table {
433}; 441};
434 442
435struct ath_hw { 443struct ath_hw {
436 struct ath_softc *ah_sc; 444 struct ieee80211_hw *hw;
445 struct ath_common common;
437 struct ath9k_hw_version hw_version; 446 struct ath9k_hw_version hw_version;
438 struct ath9k_ops_config config; 447 struct ath9k_ops_config config;
439 struct ath9k_hw_capabilities caps; 448 struct ath9k_hw_capabilities caps;
@@ -450,7 +459,6 @@ struct ath_hw {
450 459
451 bool sw_mgmt_crypto; 460 bool sw_mgmt_crypto;
452 bool is_pciexpress; 461 bool is_pciexpress;
453 u8 macaddr[ETH_ALEN];
454 u16 tx_trig_level; 462 u16 tx_trig_level;
455 u16 rfsilent; 463 u16 rfsilent;
456 u32 rfkill_gpio; 464 u32 rfkill_gpio;
@@ -523,7 +531,14 @@ struct ath_hw {
523 DONT_USE_32KHZ, 531 DONT_USE_32KHZ,
524 } enable_32kHz_clock; 532 } enable_32kHz_clock;
525 533
526 /* RF */ 534 /* Callback for radio frequency change */
535 int (*ath9k_hw_rf_set_freq)(struct ath_hw *ah, struct ath9k_channel *chan);
536
537 /* Callback for baseband spur frequency */
538 void (*ath9k_hw_spur_mitigate_freq)(struct ath_hw *ah,
539 struct ath9k_channel *chan);
540
541 /* Used to program the radio on non single-chip devices */
527 u32 *analogBank0Data; 542 u32 *analogBank0Data;
528 u32 *analogBank1Data; 543 u32 *analogBank1Data;
529 u32 *analogBank2Data; 544 u32 *analogBank2Data;
@@ -540,7 +555,6 @@ struct ath_hw {
540 u32 acktimeout; 555 u32 acktimeout;
541 u32 ctstimeout; 556 u32 ctstimeout;
542 u32 globaltxtimeout; 557 u32 globaltxtimeout;
543 u8 gbeacon_rate;
544 558
545 /* ANI */ 559 /* ANI */
546 u32 proc_phyerr; 560 u32 proc_phyerr;
@@ -553,8 +567,10 @@ struct ath_hw {
553 int firpwr[5]; 567 int firpwr[5];
554 enum ath9k_ani_cmd ani_function; 568 enum ath9k_ani_cmd ani_function;
555 569
570 /* Bluetooth coexistance */
571 struct ath_btcoex_hw btcoex_hw;
572
556 u32 intr_txqs; 573 u32 intr_txqs;
557 enum ath9k_ht_extprotspacing extprotspacing;
558 u8 txchainmask; 574 u8 txchainmask;
559 u8 rxchainmask; 575 u8 rxchainmask;
560 576
@@ -578,17 +594,29 @@ struct ath_hw {
578 struct ar5416IniArray iniModesAdditional; 594 struct ar5416IniArray iniModesAdditional;
579 struct ar5416IniArray iniModesRxGain; 595 struct ar5416IniArray iniModesRxGain;
580 struct ar5416IniArray iniModesTxGain; 596 struct ar5416IniArray iniModesTxGain;
597 struct ar5416IniArray iniModes_9271_1_0_only;
598 struct ar5416IniArray iniCckfirNormal;
599 struct ar5416IniArray iniCckfirJapan2484;
581 600
582 u32 intr_gen_timer_trigger; 601 u32 intr_gen_timer_trigger;
583 u32 intr_gen_timer_thresh; 602 u32 intr_gen_timer_thresh;
584 struct ath_gen_timer_table hw_gen_timers; 603 struct ath_gen_timer_table hw_gen_timers;
585}; 604};
586 605
606static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
607{
608 return &ah->common;
609}
610
611static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
612{
613 return &(ath9k_hw_common(ah)->regulatory);
614}
615
587/* Initialization, Detach, Reset */ 616/* Initialization, Detach, Reset */
588const char *ath9k_hw_probe(u16 vendorid, u16 devid); 617const char *ath9k_hw_probe(u16 vendorid, u16 devid);
589void ath9k_hw_detach(struct ath_hw *ah); 618void ath9k_hw_detach(struct ath_hw *ah);
590int ath9k_hw_init(struct ath_hw *ah); 619int ath9k_hw_init(struct ath_hw *ah);
591void ath9k_hw_rf_free(struct ath_hw *ah);
592int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 620int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
593 bool bChannelChange); 621 bool bChannelChange);
594void ath9k_hw_fill_cap_info(struct ath_hw *ah); 622void ath9k_hw_fill_cap_info(struct ath_hw *ah);
@@ -613,11 +641,6 @@ void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
613void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val); 641void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
614u32 ath9k_hw_getdefantenna(struct ath_hw *ah); 642u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
615void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna); 643void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
616bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
617 enum ath9k_ant_setting settings,
618 struct ath9k_channel *chan,
619 u8 *tx_chainmask, u8 *rx_chainmask,
620 u8 *antenna_cfgd);
621 644
622/* General Operation */ 645/* General Operation */
623bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout); 646bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
@@ -637,19 +660,21 @@ void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit);
637void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac); 660void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac);
638void ath9k_hw_setopmode(struct ath_hw *ah); 661void ath9k_hw_setopmode(struct ath_hw *ah);
639void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1); 662void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
640void ath9k_hw_setbssidmask(struct ath_softc *sc); 663void ath9k_hw_setbssidmask(struct ath_hw *ah);
641void ath9k_hw_write_associd(struct ath_softc *sc); 664void ath9k_hw_write_associd(struct ath_hw *ah);
642u64 ath9k_hw_gettsf64(struct ath_hw *ah); 665u64 ath9k_hw_gettsf64(struct ath_hw *ah);
643void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64); 666void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
644void ath9k_hw_reset_tsf(struct ath_hw *ah); 667void ath9k_hw_reset_tsf(struct ath_hw *ah);
645void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting); 668void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
669u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp);
646bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us); 670bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us);
647void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode); 671void ath9k_hw_set11nmac2040(struct ath_hw *ah);
648void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period); 672void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
649void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 673void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
650 const struct ath9k_beacon_state *bs); 674 const struct ath9k_beacon_state *bs);
651bool ath9k_hw_setpower(struct ath_hw *ah, 675
652 enum ath9k_power_mode mode); 676bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
677
653void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off); 678void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off);
654 679
655/* Interrupt Handling */ 680/* Interrupt Handling */
@@ -663,16 +688,20 @@ struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
663 void (*overflow)(void *), 688 void (*overflow)(void *),
664 void *arg, 689 void *arg,
665 u8 timer_index); 690 u8 timer_index);
666void ath_gen_timer_start(struct ath_hw *ah, struct ath_gen_timer *timer, 691void ath9k_hw_gen_timer_start(struct ath_hw *ah,
667 u32 timer_next, u32 timer_period); 692 struct ath_gen_timer *timer,
668void ath_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer); 693 u32 timer_next,
694 u32 timer_period);
695void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
696
669void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer); 697void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
670void ath_gen_timer_isr(struct ath_hw *hw); 698void ath_gen_timer_isr(struct ath_hw *hw);
671u32 ath9k_hw_gettsf32(struct ath_hw *ah); 699u32 ath9k_hw_gettsf32(struct ath_hw *ah);
672 700
701void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
702
673#define ATH_PCIE_CAP_LINK_CTRL 0x70 703#define ATH_PCIE_CAP_LINK_CTRL 0x70
674#define ATH_PCIE_CAP_LINK_L0S 1 704#define ATH_PCIE_CAP_LINK_L0S 1
675#define ATH_PCIE_CAP_LINK_L1 2 705#define ATH_PCIE_CAP_LINK_L1 2
676 706
677void ath_pcie_aspm_disable(struct ath_softc *sc);
678#endif 707#endif
diff --git a/drivers/net/wireless/ath/ath9k/initvals.h b/drivers/net/wireless/ath/ath9k/initvals.h
index 8622265a030a..8a3bf3ab998d 100644
--- a/drivers/net/wireless/ath/ath9k/initvals.h
+++ b/drivers/net/wireless/ath/ath9k/initvals.h
@@ -21,6 +21,8 @@ static const u32 ar5416Modes[][6] = {
21 { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 }, 21 { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },
22 { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 }, 22 { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
23 { 0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf }, 23 { 0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf },
24 { 0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810, 0x08f04810 },
25 { 0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a, 0x0000320a },
24 { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 }, 26 { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
25 { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 }, 27 { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
26 { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e }, 28 { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
@@ -31,11 +33,11 @@ static const u32 ar5416Modes[][6] = {
31 { 0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 }, 33 { 0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
32 { 0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 }, 34 { 0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
33 { 0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 }, 35 { 0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
34 { 0x00009850, 0x6c48b4e0, 0x6c48b4e0, 0x6c48b0de, 0x6c48b0de, 0x6c48b0de }, 36 { 0x00009850, 0x6c48b4e0, 0x6d48b4e0, 0x6d48b0de, 0x6c48b0de, 0x6c48b0de },
35 { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e }, 37 { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e },
36 { 0x0000985c, 0x31395d5e, 0x31395d5e, 0x31395d5e, 0x31395d5e, 0x31395d5e }, 38 { 0x0000985c, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e, 0x31395d5e },
37 { 0x00009860, 0x00049d18, 0x00049d18, 0x00049d18, 0x00049d18, 0x00049d18 }, 39 { 0x00009860, 0x00049d18, 0x00049d18, 0x00049d18, 0x00049d18, 0x00049d18 },
38 { 0x0000c864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 }, 40 { 0x00009864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
39 { 0x00009868, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190 }, 41 { 0x00009868, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190 },
40 { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 }, 42 { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 },
41 { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 }, 43 { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
@@ -46,10 +48,10 @@ static const u32 ar5416Modes[][6] = {
46 { 0x0000a960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80, 0x00012d80 }, 48 { 0x0000a960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80, 0x00012d80 },
47 { 0x0000b960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80, 0x00012d80 }, 49 { 0x0000b960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80, 0x00012d80 },
48 { 0x00009964, 0x00000000, 0x00000000, 0x00001120, 0x00001120, 0x00001120 }, 50 { 0x00009964, 0x00000000, 0x00000000, 0x00001120, 0x00001120, 0x00001120 },
49 { 0x0000c9bc, 0x001a0a00, 0x001a0a00, 0x001a0a00, 0x001a0a00, 0x001a0a00 }, 51 { 0x000099bc, 0x001a0a00, 0x001a0a00, 0x001a0a00, 0x001a0a00, 0x001a0a00 },
50 { 0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, 0x038919be }, 52 { 0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, 0x038919be },
51 { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 }, 53 { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
52 { 0x000099c8, 0x60f6532c, 0x60f6532c, 0x60f6532c, 0x60f6532c, 0x60f6532c }, 54 { 0x000099c8, 0x6af6532c, 0x6af6532c, 0x6af6532c, 0x6af6532c, 0x6af6532c },
53 { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 }, 55 { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
54 { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 }, 56 { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
55 { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, 57 { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
@@ -199,7 +201,6 @@ static const u32 ar5416Common[][2] = {
199 { 0x00008110, 0x00000168 }, 201 { 0x00008110, 0x00000168 },
200 { 0x00008118, 0x000100aa }, 202 { 0x00008118, 0x000100aa },
201 { 0x0000811c, 0x00003210 }, 203 { 0x0000811c, 0x00003210 },
202 { 0x00008120, 0x08f04800 },
203 { 0x00008124, 0x00000000 }, 204 { 0x00008124, 0x00000000 },
204 { 0x00008128, 0x00000000 }, 205 { 0x00008128, 0x00000000 },
205 { 0x0000812c, 0x00000000 }, 206 { 0x0000812c, 0x00000000 },
@@ -215,7 +216,6 @@ static const u32 ar5416Common[][2] = {
215 { 0x00008178, 0x00000100 }, 216 { 0x00008178, 0x00000100 },
216 { 0x0000817c, 0x00000000 }, 217 { 0x0000817c, 0x00000000 },
217 { 0x000081c4, 0x00000000 }, 218 { 0x000081c4, 0x00000000 },
218 { 0x000081d0, 0x00003210 },
219 { 0x000081ec, 0x00000000 }, 219 { 0x000081ec, 0x00000000 },
220 { 0x000081f0, 0x00000000 }, 220 { 0x000081f0, 0x00000000 },
221 { 0x000081f4, 0x00000000 }, 221 { 0x000081f4, 0x00000000 },
@@ -246,6 +246,7 @@ static const u32 ar5416Common[][2] = {
246 { 0x00008258, 0x00000000 }, 246 { 0x00008258, 0x00000000 },
247 { 0x0000825c, 0x400000ff }, 247 { 0x0000825c, 0x400000ff },
248 { 0x00008260, 0x00080922 }, 248 { 0x00008260, 0x00080922 },
249 { 0x00008264, 0xa8000010 },
249 { 0x00008270, 0x00000000 }, 250 { 0x00008270, 0x00000000 },
250 { 0x00008274, 0x40000000 }, 251 { 0x00008274, 0x40000000 },
251 { 0x00008278, 0x003e4180 }, 252 { 0x00008278, 0x003e4180 },
@@ -406,9 +407,9 @@ static const u32 ar5416Common[][2] = {
406 { 0x0000a25c, 0x0f0f0f01 }, 407 { 0x0000a25c, 0x0f0f0f01 },
407 { 0x0000a260, 0xdfa91f01 }, 408 { 0x0000a260, 0xdfa91f01 },
408 { 0x0000a268, 0x00000000 }, 409 { 0x0000a268, 0x00000000 },
409 { 0x0000a26c, 0x0ebae9c6 }, 410 { 0x0000a26c, 0x0e79e5c6 },
410 { 0x0000b26c, 0x0ebae9c6 }, 411 { 0x0000b26c, 0x0e79e5c6 },
411 { 0x0000c26c, 0x0ebae9c6 }, 412 { 0x0000c26c, 0x0e79e5c6 },
412 { 0x0000d270, 0x00820820 }, 413 { 0x0000d270, 0x00820820 },
413 { 0x0000a278, 0x1ce739ce }, 414 { 0x0000a278, 0x1ce739ce },
414 { 0x0000a27c, 0x051701ce }, 415 { 0x0000a27c, 0x051701ce },
@@ -2551,26 +2552,27 @@ static const u32 ar9280Modes_9280_2[][6] = {
2551 { 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 }, 2552 { 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 },
2552 { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 }, 2553 { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
2553 { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 }, 2554 { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
2554 { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e }, 2555 { 0x00009824, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e },
2555 { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 }, 2556 { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
2556 { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e }, 2557 { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
2557 { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 }, 2558 { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
2558 { 0x00009840, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e, 0x206a012e }, 2559 { 0x00009840, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e, 0x206a012e },
2559 { 0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0, 0x037216a0 }, 2560 { 0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0, 0x037216a0 },
2560 { 0x00009850, 0x6c4000e2, 0x6c4000e2, 0x6d4000e2, 0x6c4000e2, 0x6c4000e2 }, 2561 { 0x00009850, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2, 0x6c4000e2 },
2561 { 0x00009858, 0x7ec88d2e, 0x7ec88d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e }, 2562 { 0x00009858, 0x7ec88d2e, 0x7ec88d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
2562 { 0x0000985c, 0x31395d5e, 0x31395d5e, 0x3139605e, 0x31395d5e, 0x31395d5e }, 2563 { 0x0000985c, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e, 0x31395d5e },
2563 { 0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20, 0x00048d18 }, 2564 { 0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20, 0x00048d18 },
2564 { 0x00009864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 }, 2565 { 0x00009864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
2565 { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 }, 2566 { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
2566 { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 }, 2567 { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 },
2567 { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 }, 2568 { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
2568 { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 }, 2569 { 0x00009918, 0x0000000a, 0x00000014, 0x00000268, 0x0000000b, 0x00000016 },
2569 { 0x00009924, 0xd00a8a0b, 0xd00a8a0b, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d }, 2570 { 0x00009924, 0xd00a8a0b, 0xd00a8a0b, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d },
2570 { 0x00009944, 0xffbc1010, 0xffbc1010, 0xffbc1010, 0xffbc1010, 0xffbc1010 }, 2571 { 0x00009944, 0xffbc1010, 0xffbc1010, 0xffbc1010, 0xffbc1010, 0xffbc1010 },
2571 { 0x00009960, 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 }, 2572 { 0x00009960, 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 },
2572 { 0x0000a960, 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 }, 2573 { 0x0000a960, 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 },
2573 { 0x00009964, 0x00000210, 0x00000210, 0x00000210, 0x00000210, 0x00000210 }, 2574 { 0x00009964, 0x00000210, 0x00000210, 0x00000210, 0x00000210, 0x00000210 },
2575 { 0x0000c968, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce, 0x000003ce },
2574 { 0x000099b8, 0x0000001c, 0x0000001c, 0x0000001c, 0x0000001c, 0x0000001c }, 2576 { 0x000099b8, 0x0000001c, 0x0000001c, 0x0000001c, 0x0000001c, 0x0000001c },
2575 { 0x000099bc, 0x00000a00, 0x00000a00, 0x00000c00, 0x00000c00, 0x00000c00 }, 2577 { 0x000099bc, 0x00000a00, 0x00000a00, 0x00000c00, 0x00000c00, 0x00000c00 },
2576 { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 }, 2578 { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
@@ -2585,8 +2587,10 @@ static const u32 ar9280Modes_9280_2[][6] = {
2585 { 0x0000b20c, 0x00000014, 0x00000014, 0x0001f019, 0x0001f019, 0x0001f019 }, 2587 { 0x0000b20c, 0x00000014, 0x00000014, 0x0001f019, 0x0001f019, 0x0001f019 },
2586 { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a }, 2588 { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
2587 { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 }, 2589 { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
2590 { 0x0000a23c, 0x13c88000, 0x13c88000, 0x13c88001, 0x13c88000, 0x13c88000 },
2588 { 0x0000a250, 0x001ff000, 0x001ff000, 0x0004a000, 0x0004a000, 0x0004a000 }, 2591 { 0x0000a250, 0x001ff000, 0x001ff000, 0x0004a000, 0x0004a000, 0x0004a000 },
2589 { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e }, 2592 { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
2593 { 0x0000a388, 0x0c000000, 0x0c000000, 0x08000000, 0x0c000000, 0x0c000000 },
2590 { 0x0000a3d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, 2594 { 0x0000a3d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
2591 { 0x00007894, 0x5a508000, 0x5a508000, 0x5a508000, 0x5a508000, 0x5a508000 }, 2595 { 0x00007894, 0x5a508000, 0x5a508000, 0x5a508000, 0x5a508000, 0x5a508000 },
2592}; 2596};
@@ -2813,7 +2817,6 @@ static const u32 ar9280Common_9280_2[][2] = {
2813 { 0x00009958, 0x2108ecff }, 2817 { 0x00009958, 0x2108ecff },
2814 { 0x00009940, 0x14750604 }, 2818 { 0x00009940, 0x14750604 },
2815 { 0x0000c95c, 0x004b6a8e }, 2819 { 0x0000c95c, 0x004b6a8e },
2816 { 0x0000c968, 0x000003ce },
2817 { 0x00009970, 0x190fb515 }, 2820 { 0x00009970, 0x190fb515 },
2818 { 0x00009974, 0x00000000 }, 2821 { 0x00009974, 0x00000000 },
2819 { 0x00009978, 0x00000001 }, 2822 { 0x00009978, 0x00000001 },
@@ -2849,7 +2852,6 @@ static const u32 ar9280Common_9280_2[][2] = {
2849 { 0x0000a22c, 0x233f7180 }, 2852 { 0x0000a22c, 0x233f7180 },
2850 { 0x0000a234, 0x20202020 }, 2853 { 0x0000a234, 0x20202020 },
2851 { 0x0000a238, 0x20202020 }, 2854 { 0x0000a238, 0x20202020 },
2852 { 0x0000a23c, 0x13c88000 },
2853 { 0x0000a240, 0x38490a20 }, 2855 { 0x0000a240, 0x38490a20 },
2854 { 0x0000a244, 0x00007bb6 }, 2856 { 0x0000a244, 0x00007bb6 },
2855 { 0x0000a248, 0x0fff3ffc }, 2857 { 0x0000a248, 0x0fff3ffc },
@@ -2859,8 +2861,8 @@ static const u32 ar9280Common_9280_2[][2] = {
2859 { 0x0000a25c, 0x0f0f0f01 }, 2861 { 0x0000a25c, 0x0f0f0f01 },
2860 { 0x0000a260, 0xdfa91f01 }, 2862 { 0x0000a260, 0xdfa91f01 },
2861 { 0x0000a268, 0x00000000 }, 2863 { 0x0000a268, 0x00000000 },
2862 { 0x0000a26c, 0x0ebae9c6 }, 2864 { 0x0000a26c, 0x0e79e5c6 },
2863 { 0x0000b26c, 0x0ebae9c6 }, 2865 { 0x0000b26c, 0x0e79e5c6 },
2864 { 0x0000d270, 0x00820820 }, 2866 { 0x0000d270, 0x00820820 },
2865 { 0x0000a278, 0x1ce739ce }, 2867 { 0x0000a278, 0x1ce739ce },
2866 { 0x0000d35c, 0x07ffffef }, 2868 { 0x0000d35c, 0x07ffffef },
@@ -2874,7 +2876,6 @@ static const u32 ar9280Common_9280_2[][2] = {
2874 { 0x0000d37c, 0x7fffffe2 }, 2876 { 0x0000d37c, 0x7fffffe2 },
2875 { 0x0000d380, 0x7f3c7bba }, 2877 { 0x0000d380, 0x7f3c7bba },
2876 { 0x0000d384, 0xf3307ff0 }, 2878 { 0x0000d384, 0xf3307ff0 },
2877 { 0x0000a388, 0x0c000000 },
2878 { 0x0000a38c, 0x20202020 }, 2879 { 0x0000a38c, 0x20202020 },
2879 { 0x0000a390, 0x20202020 }, 2880 { 0x0000a390, 0x20202020 },
2880 { 0x0000a394, 0x1ce739ce }, 2881 { 0x0000a394, 0x1ce739ce },
@@ -2940,7 +2941,7 @@ static const u32 ar9280Modes_fast_clock_9280_2[][3] = {
2940 { 0x0000801c, 0x148ec02b, 0x148ec057 }, 2941 { 0x0000801c, 0x148ec02b, 0x148ec057 },
2941 { 0x00008318, 0x000044c0, 0x00008980 }, 2942 { 0x00008318, 0x000044c0, 0x00008980 },
2942 { 0x00009820, 0x02020200, 0x02020200 }, 2943 { 0x00009820, 0x02020200, 0x02020200 },
2943 { 0x00009824, 0x00000f0f, 0x00000f0f }, 2944 { 0x00009824, 0x01000f0f, 0x01000f0f },
2944 { 0x00009828, 0x0b020001, 0x0b020001 }, 2945 { 0x00009828, 0x0b020001, 0x0b020001 },
2945 { 0x00009834, 0x00000f0f, 0x00000f0f }, 2946 { 0x00009834, 0x00000f0f, 0x00000f0f },
2946 { 0x00009844, 0x03721821, 0x03721821 }, 2947 { 0x00009844, 0x03721821, 0x03721821 },
@@ -3348,6 +3349,8 @@ static const u32 ar9280Modes_backoff_13db_rxgain_9280_2[][6] = {
3348}; 3349};
3349 3350
3350static const u32 ar9280Modes_high_power_tx_gain_9280_2[][6] = { 3351static const u32 ar9280Modes_high_power_tx_gain_9280_2[][6] = {
3352 { 0x0000a274, 0x0a19e652, 0x0a19e652, 0x0a1aa652, 0x0a1aa652, 0x0a1aa652 },
3353 { 0x0000a27c, 0x050739ce, 0x050739ce, 0x050739ce, 0x050739ce, 0x050739ce },
3351 { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, 3354 { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
3352 { 0x0000a304, 0x00003002, 0x00003002, 0x00004002, 0x00004002, 0x00004002 }, 3355 { 0x0000a304, 0x00003002, 0x00003002, 0x00004002, 0x00004002, 0x00004002 },
3353 { 0x0000a308, 0x00006004, 0x00006004, 0x00007008, 0x00007008, 0x00007008 }, 3356 { 0x0000a308, 0x00006004, 0x00006004, 0x00007008, 0x00007008, 0x00007008 },
@@ -3376,11 +3379,11 @@ static const u32 ar9280Modes_high_power_tx_gain_9280_2[][6] = {
3376 { 0x00007840, 0x00172000, 0x00172000, 0x00172000, 0x00172000, 0x00172000 }, 3379 { 0x00007840, 0x00172000, 0x00172000, 0x00172000, 0x00172000, 0x00172000 },
3377 { 0x00007820, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480 }, 3380 { 0x00007820, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480 },
3378 { 0x00007844, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480 }, 3381 { 0x00007844, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480 },
3379 { 0x0000a274, 0x0a19e652, 0x0a19e652, 0x0a1aa652, 0x0a1aa652, 0x0a1aa652 },
3380 { 0x0000a27c, 0x050739ce, 0x050739ce, 0x050739ce, 0x050739ce, 0x050739ce },
3381}; 3382};
3382 3383
3383static const u32 ar9280Modes_original_tx_gain_9280_2[][6] = { 3384static const u32 ar9280Modes_original_tx_gain_9280_2[][6] = {
3385 { 0x0000a274, 0x0a19c652, 0x0a19c652, 0x0a1aa652, 0x0a1aa652, 0x0a1aa652 },
3386 { 0x0000a27c, 0x050701ce, 0x050701ce, 0x050701ce, 0x050701ce, 0x050701ce },
3384 { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, 3387 { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
3385 { 0x0000a304, 0x00003002, 0x00003002, 0x00003002, 0x00003002, 0x00003002 }, 3388 { 0x0000a304, 0x00003002, 0x00003002, 0x00003002, 0x00003002, 0x00003002 },
3386 { 0x0000a308, 0x00006004, 0x00006004, 0x00008009, 0x00008009, 0x00008009 }, 3389 { 0x0000a308, 0x00006004, 0x00006004, 0x00008009, 0x00008009, 0x00008009 },
@@ -3409,8 +3412,6 @@ static const u32 ar9280Modes_original_tx_gain_9280_2[][6] = {
3409 { 0x00007840, 0x00392000, 0x00392000, 0x00392000, 0x00392000, 0x00392000 }, 3412 { 0x00007840, 0x00392000, 0x00392000, 0x00392000, 0x00392000, 0x00392000 },
3410 { 0x00007820, 0x92592480, 0x92592480, 0x92592480, 0x92592480, 0x92592480 }, 3413 { 0x00007820, 0x92592480, 0x92592480, 0x92592480, 0x92592480, 0x92592480 },
3411 { 0x00007844, 0x92592480, 0x92592480, 0x92592480, 0x92592480, 0x92592480 }, 3414 { 0x00007844, 0x92592480, 0x92592480, 0x92592480, 0x92592480, 0x92592480 },
3412 { 0x0000a274, 0x0a19c652, 0x0a19c652, 0x0a1aa652, 0x0a1aa652, 0x0a1aa652 },
3413 { 0x0000a27c, 0x050701ce, 0x050701ce, 0x050701ce, 0x050701ce, 0x050701ce },
3414}; 3415};
3415 3416
3416static const u32 ar9280PciePhy_clkreq_off_L1_9280[][2] = { 3417static const u32 ar9280PciePhy_clkreq_off_L1_9280[][2] = {
@@ -5918,9 +5919,6 @@ static const u_int32_t ar9287Common_9287_1_1[][2] = {
5918 { 0x000099ec, 0x0cc80caa }, 5919 { 0x000099ec, 0x0cc80caa },
5919 { 0x000099f0, 0x00000000 }, 5920 { 0x000099f0, 0x00000000 },
5920 { 0x000099fc, 0x00001042 }, 5921 { 0x000099fc, 0x00001042 },
5921 { 0x0000a1f4, 0x00fffeff },
5922 { 0x0000a1f8, 0x00f5f9ff },
5923 { 0x0000a1fc, 0xb79f6427 },
5924 { 0x0000a208, 0x803e4788 }, 5922 { 0x0000a208, 0x803e4788 },
5925 { 0x0000a210, 0x4080a333 }, 5923 { 0x0000a210, 0x4080a333 },
5926 { 0x0000a214, 0x40206c10 }, 5924 { 0x0000a214, 0x40206c10 },
@@ -5980,7 +5978,7 @@ static const u_int32_t ar9287Common_9287_1_1[][2] = {
5980 { 0x0000b3f4, 0x00000000 }, 5978 { 0x0000b3f4, 0x00000000 },
5981 { 0x0000a7d8, 0x000003f1 }, 5979 { 0x0000a7d8, 0x000003f1 },
5982 { 0x00007800, 0x00000800 }, 5980 { 0x00007800, 0x00000800 },
5983 { 0x00007804, 0x6c35ffc2 }, 5981 { 0x00007804, 0x6c35ffd2 },
5984 { 0x00007808, 0x6db6c000 }, 5982 { 0x00007808, 0x6db6c000 },
5985 { 0x0000780c, 0x6db6cb30 }, 5983 { 0x0000780c, 0x6db6cb30 },
5986 { 0x00007810, 0x6db6cb6c }, 5984 { 0x00007810, 0x6db6cb6c },
@@ -6000,7 +5998,7 @@ static const u_int32_t ar9287Common_9287_1_1[][2] = {
6000 { 0x00007848, 0x934934a8 }, 5998 { 0x00007848, 0x934934a8 },
6001 { 0x00007850, 0x00000000 }, 5999 { 0x00007850, 0x00000000 },
6002 { 0x00007854, 0x00000800 }, 6000 { 0x00007854, 0x00000800 },
6003 { 0x00007858, 0x6c35ffc2 }, 6001 { 0x00007858, 0x6c35ffd2 },
6004 { 0x0000785c, 0x6db6c000 }, 6002 { 0x0000785c, 0x6db6c000 },
6005 { 0x00007860, 0x6db6cb30 }, 6003 { 0x00007860, 0x6db6cb30 },
6006 { 0x00007864, 0x6db6cb6c }, 6004 { 0x00007864, 0x6db6cb6c },
@@ -6027,6 +6025,22 @@ static const u_int32_t ar9287Common_9287_1_1[][2] = {
6027 { 0x000078b8, 0x2a850160 }, 6025 { 0x000078b8, 0x2a850160 },
6028}; 6026};
6029 6027
6028/*
6029 * For Japanese regulatory requirements, 2484 MHz requires the following three
6030 * registers be programmed differently from the channel between 2412 and 2472 MHz.
6031 */
6032static const u_int32_t ar9287Common_normal_cck_fir_coeff_92871_1[][2] = {
6033 { 0x0000a1f4, 0x00fffeff },
6034 { 0x0000a1f8, 0x00f5f9ff },
6035 { 0x0000a1fc, 0xb79f6427 },
6036};
6037
6038static const u_int32_t ar9287Common_japan_2484_cck_fir_coeff_92871_1[][2] = {
6039 { 0x0000a1f4, 0x00000000 },
6040 { 0x0000a1f8, 0xefff0301 },
6041 { 0x0000a1fc, 0xca9228ee },
6042};
6043
6030static const u_int32_t ar9287Modes_tx_gain_9287_1_1[][6] = { 6044static const u_int32_t ar9287Modes_tx_gain_9287_1_1[][6] = {
6031 /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */ 6045 /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
6032 { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, 6046 { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
@@ -6365,8 +6379,8 @@ static const u_int32_t ar9287PciePhy_clkreq_off_L1_9287_1_1[][2] = {
6365}; 6379};
6366 6380
6367 6381
6368/* AR9271 initialization values automaticaly created: 03/23/09 */ 6382/* AR9271 initialization values automaticaly created: 06/04/09 */
6369static const u_int32_t ar9271Modes_9271_1_0[][6] = { 6383static const u_int32_t ar9271Modes_9271[][6] = {
6370 { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 }, 6384 { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
6371 { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 }, 6385 { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
6372 { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 }, 6386 { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
@@ -6376,8 +6390,8 @@ static const u_int32_t ar9271Modes_9271_1_0[][6] = {
6376 { 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 }, 6390 { 0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440, 0x00006880 },
6377 { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 }, 6391 { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
6378 { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 }, 6392 { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
6379 { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e }, 6393 { 0x00009824, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e },
6380 { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 }, 6394 { 0x00009828, 0x3a020001, 0x3a020001, 0x3a020001, 0x3a020001, 0x3a020001 },
6381 { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e }, 6395 { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
6382 { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 }, 6396 { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
6383 { 0x00009840, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e }, 6397 { 0x00009840, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e, 0x206a012e },
@@ -6391,6 +6405,7 @@ static const u_int32_t ar9271Modes_9271_1_0[][6] = {
6391 { 0x00009864, 0x0000fe00, 0x0000fe00, 0x0001ce00, 0x0001ce00, 0x0001ce00 }, 6405 { 0x00009864, 0x0000fe00, 0x0000fe00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
6392 { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 }, 6406 { 0x00009868, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0 },
6393 { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 }, 6407 { 0x0000986c, 0x06903081, 0x06903081, 0x06903881, 0x06903881, 0x06903881 },
6408 { 0x00009910, 0x30002310, 0x30002310, 0x30002310, 0x30002310, 0x30002310 },
6394 { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 }, 6409 { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
6395 { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 }, 6410 { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
6396 { 0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d, 0xd00a800d }, 6411 { 0x00009924, 0xd00a8007, 0xd00a8007, 0xd00a800d, 0xd00a800d, 0xd00a800d },
@@ -6401,7 +6416,7 @@ static const u_int32_t ar9271Modes_9271_1_0[][6] = {
6401 { 0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00 }, 6416 { 0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00 },
6402 { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 }, 6417 { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
6403 { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 }, 6418 { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
6404 { 0x000099c8, 0x6af65329, 0x6af65329, 0x6af65329, 0x6af65329, 0x6af65329 }, 6419 { 0x000099c8, 0x6af6532f, 0x6af6532f, 0x6af6532f, 0x6af6532f, 0x6af6532f },
6405 { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 }, 6420 { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
6406 { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 }, 6421 { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
6407 { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, 6422 { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
@@ -6690,7 +6705,7 @@ static const u_int32_t ar9271Modes_9271_1_0[][6] = {
6690 { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e }, 6705 { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
6691}; 6706};
6692 6707
6693static const u_int32_t ar9271Common_9271_1_0[][2] = { 6708static const u_int32_t ar9271Common_9271[][2] = {
6694 { 0x0000000c, 0x00000000 }, 6709 { 0x0000000c, 0x00000000 },
6695 { 0x00000030, 0x00020045 }, 6710 { 0x00000030, 0x00020045 },
6696 { 0x00000034, 0x00000005 }, 6711 { 0x00000034, 0x00000005 },
@@ -6786,7 +6801,7 @@ static const u_int32_t ar9271Common_9271_1_0[][2] = {
6786 { 0x0000803c, 0x00000000 }, 6801 { 0x0000803c, 0x00000000 },
6787 { 0x00008048, 0x00000000 }, 6802 { 0x00008048, 0x00000000 },
6788 { 0x00008054, 0x00000000 }, 6803 { 0x00008054, 0x00000000 },
6789 { 0x00008058, 0x02000000 }, 6804 { 0x00008058, 0x00000000 },
6790 { 0x0000805c, 0x000fc78f }, 6805 { 0x0000805c, 0x000fc78f },
6791 { 0x00008060, 0x0000000f }, 6806 { 0x00008060, 0x0000000f },
6792 { 0x00008064, 0x00000000 }, 6807 { 0x00008064, 0x00000000 },
@@ -6817,7 +6832,7 @@ static const u_int32_t ar9271Common_9271_1_0[][2] = {
6817 { 0x00008110, 0x00000168 }, 6832 { 0x00008110, 0x00000168 },
6818 { 0x00008118, 0x000100aa }, 6833 { 0x00008118, 0x000100aa },
6819 { 0x0000811c, 0x00003210 }, 6834 { 0x0000811c, 0x00003210 },
6820 { 0x00008120, 0x08f04814 }, 6835 { 0x00008120, 0x08f04810 },
6821 { 0x00008124, 0x00000000 }, 6836 { 0x00008124, 0x00000000 },
6822 { 0x00008128, 0x00000000 }, 6837 { 0x00008128, 0x00000000 },
6823 { 0x0000812c, 0x00000000 }, 6838 { 0x0000812c, 0x00000000 },
@@ -6864,7 +6879,7 @@ static const u_int32_t ar9271Common_9271_1_0[][2] = {
6864 { 0x00008258, 0x00000000 }, 6879 { 0x00008258, 0x00000000 },
6865 { 0x0000825c, 0x400000ff }, 6880 { 0x0000825c, 0x400000ff },
6866 { 0x00008260, 0x00080922 }, 6881 { 0x00008260, 0x00080922 },
6867 { 0x00008264, 0xa8a00010 }, 6882 { 0x00008264, 0x88a00010 },
6868 { 0x00008270, 0x00000000 }, 6883 { 0x00008270, 0x00000000 },
6869 { 0x00008274, 0x40000000 }, 6884 { 0x00008274, 0x40000000 },
6870 { 0x00008278, 0x003e4180 }, 6885 { 0x00008278, 0x003e4180 },
@@ -6896,7 +6911,7 @@ static const u_int32_t ar9271Common_9271_1_0[][2] = {
6896 { 0x00007814, 0x924934a8 }, 6911 { 0x00007814, 0x924934a8 },
6897 { 0x0000781c, 0x00000000 }, 6912 { 0x0000781c, 0x00000000 },
6898 { 0x00007820, 0x00000c04 }, 6913 { 0x00007820, 0x00000c04 },
6899 { 0x00007824, 0x00d86bff }, 6914 { 0x00007824, 0x00d8abff },
6900 { 0x00007828, 0x66964300 }, 6915 { 0x00007828, 0x66964300 },
6901 { 0x0000782c, 0x8db6d961 }, 6916 { 0x0000782c, 0x8db6d961 },
6902 { 0x00007830, 0x8db6d96c }, 6917 { 0x00007830, 0x8db6d96c },
@@ -6930,7 +6945,6 @@ static const u_int32_t ar9271Common_9271_1_0[][2] = {
6930 { 0x00009904, 0x00000000 }, 6945 { 0x00009904, 0x00000000 },
6931 { 0x00009908, 0x00000000 }, 6946 { 0x00009908, 0x00000000 },
6932 { 0x0000990c, 0x00000000 }, 6947 { 0x0000990c, 0x00000000 },
6933 { 0x00009910, 0x30002310 },
6934 { 0x0000991c, 0x10000fff }, 6948 { 0x0000991c, 0x10000fff },
6935 { 0x00009920, 0x04900000 }, 6949 { 0x00009920, 0x04900000 },
6936 { 0x00009928, 0x00000001 }, 6950 { 0x00009928, 0x00000001 },
@@ -6944,7 +6958,7 @@ static const u_int32_t ar9271Common_9271_1_0[][2] = {
6944 { 0x00009954, 0x5f3ca3de }, 6958 { 0x00009954, 0x5f3ca3de },
6945 { 0x00009958, 0x0108ecff }, 6959 { 0x00009958, 0x0108ecff },
6946 { 0x00009968, 0x000003ce }, 6960 { 0x00009968, 0x000003ce },
6947 { 0x00009970, 0x192bb515 }, 6961 { 0x00009970, 0x192bb514 },
6948 { 0x00009974, 0x00000000 }, 6962 { 0x00009974, 0x00000000 },
6949 { 0x00009978, 0x00000001 }, 6963 { 0x00009978, 0x00000001 },
6950 { 0x0000997c, 0x00000000 }, 6964 { 0x0000997c, 0x00000000 },
@@ -7031,3 +7045,8 @@ static const u_int32_t ar9271Common_9271_1_0[][2] = {
7031 { 0x0000d380, 0x7f3c7bba }, 7045 { 0x0000d380, 0x7f3c7bba },
7032 { 0x0000d384, 0xf3307ff0 }, 7046 { 0x0000d384, 0xf3307ff0 },
7033}; 7047};
7048
7049static const u_int32_t ar9271Modes_9271_1_0_only[][6] = {
7050 { 0x00009910, 0x30002311, 0x30002311, 0x30002311, 0x30002311, 0x30002311 },
7051 { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
7052};
diff --git a/drivers/net/wireless/ath/ath9k/mac.c b/drivers/net/wireless/ath/ath9k/mac.c
index 800bfab94635..46466ffebcb0 100644
--- a/drivers/net/wireless/ath/ath9k/mac.c
+++ b/drivers/net/wireless/ath/ath9k/mac.c
@@ -14,16 +14,16 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17#include "ath9k.h" 17#include "hw.h"
18 18
19static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah, 19static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah,
20 struct ath9k_tx_queue_info *qi) 20 struct ath9k_tx_queue_info *qi)
21{ 21{
22 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, 22 ath_print(ath9k_hw_common(ah), ATH_DBG_INTERRUPT,
23 "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n", 23 "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
24 ah->txok_interrupt_mask, ah->txerr_interrupt_mask, 24 ah->txok_interrupt_mask, ah->txerr_interrupt_mask,
25 ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask, 25 ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask,
26 ah->txurn_interrupt_mask); 26 ah->txurn_interrupt_mask);
27 27
28 REG_WRITE(ah, AR_IMR_S0, 28 REG_WRITE(ah, AR_IMR_S0,
29 SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK) 29 SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK)
@@ -39,17 +39,21 @@ u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q)
39{ 39{
40 return REG_READ(ah, AR_QTXDP(q)); 40 return REG_READ(ah, AR_QTXDP(q));
41} 41}
42EXPORT_SYMBOL(ath9k_hw_gettxbuf);
42 43
43void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp) 44void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp)
44{ 45{
45 REG_WRITE(ah, AR_QTXDP(q), txdp); 46 REG_WRITE(ah, AR_QTXDP(q), txdp);
46} 47}
48EXPORT_SYMBOL(ath9k_hw_puttxbuf);
47 49
48void ath9k_hw_txstart(struct ath_hw *ah, u32 q) 50void ath9k_hw_txstart(struct ath_hw *ah, u32 q)
49{ 51{
50 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Enable TXE on queue: %u\n", q); 52 ath_print(ath9k_hw_common(ah), ATH_DBG_QUEUE,
53 "Enable TXE on queue: %u\n", q);
51 REG_WRITE(ah, AR_Q_TXE, 1 << q); 54 REG_WRITE(ah, AR_Q_TXE, 1 << q);
52} 55}
56EXPORT_SYMBOL(ath9k_hw_txstart);
53 57
54u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q) 58u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q)
55{ 59{
@@ -64,6 +68,7 @@ u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q)
64 68
65 return npend; 69 return npend;
66} 70}
71EXPORT_SYMBOL(ath9k_hw_numtxpending);
67 72
68bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel) 73bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel)
69{ 74{
@@ -93,27 +98,28 @@ bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel)
93 98
94 return newLevel != curLevel; 99 return newLevel != curLevel;
95} 100}
101EXPORT_SYMBOL(ath9k_hw_updatetxtriglevel);
96 102
97bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q) 103bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
98{ 104{
99#define ATH9K_TX_STOP_DMA_TIMEOUT 4000 /* usec */ 105#define ATH9K_TX_STOP_DMA_TIMEOUT 4000 /* usec */
100#define ATH9K_TIME_QUANTUM 100 /* usec */ 106#define ATH9K_TIME_QUANTUM 100 /* usec */
101 107 struct ath_common *common = ath9k_hw_common(ah);
102 struct ath9k_hw_capabilities *pCap = &ah->caps; 108 struct ath9k_hw_capabilities *pCap = &ah->caps;
103 struct ath9k_tx_queue_info *qi; 109 struct ath9k_tx_queue_info *qi;
104 u32 tsfLow, j, wait; 110 u32 tsfLow, j, wait;
105 u32 wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM; 111 u32 wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM;
106 112
107 if (q >= pCap->total_queues) { 113 if (q >= pCap->total_queues) {
108 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Stopping TX DMA, " 114 ath_print(common, ATH_DBG_QUEUE, "Stopping TX DMA, "
109 "invalid queue: %u\n", q); 115 "invalid queue: %u\n", q);
110 return false; 116 return false;
111 } 117 }
112 118
113 qi = &ah->txq[q]; 119 qi = &ah->txq[q];
114 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 120 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
115 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Stopping TX DMA, " 121 ath_print(common, ATH_DBG_QUEUE, "Stopping TX DMA, "
116 "inactive queue: %u\n", q); 122 "inactive queue: %u\n", q);
117 return false; 123 return false;
118 } 124 }
119 125
@@ -126,9 +132,9 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
126 } 132 }
127 133
128 if (ath9k_hw_numtxpending(ah, q)) { 134 if (ath9k_hw_numtxpending(ah, q)) {
129 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, 135 ath_print(common, ATH_DBG_QUEUE,
130 "%s: Num of pending TX Frames %d on Q %d\n", 136 "%s: Num of pending TX Frames %d on Q %d\n",
131 __func__, ath9k_hw_numtxpending(ah, q), q); 137 __func__, ath9k_hw_numtxpending(ah, q), q);
132 138
133 for (j = 0; j < 2; j++) { 139 for (j = 0; j < 2; j++) {
134 tsfLow = REG_READ(ah, AR_TSF_L32); 140 tsfLow = REG_READ(ah, AR_TSF_L32);
@@ -142,9 +148,9 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
142 if ((REG_READ(ah, AR_TSF_L32) >> 10) == (tsfLow >> 10)) 148 if ((REG_READ(ah, AR_TSF_L32) >> 10) == (tsfLow >> 10))
143 break; 149 break;
144 150
145 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, 151 ath_print(common, ATH_DBG_QUEUE,
146 "TSF has moved while trying to set " 152 "TSF has moved while trying to set "
147 "quiet time TSF: 0x%08x\n", tsfLow); 153 "quiet time TSF: 0x%08x\n", tsfLow);
148 } 154 }
149 155
150 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 156 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
@@ -155,9 +161,9 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
155 wait = wait_time; 161 wait = wait_time;
156 while (ath9k_hw_numtxpending(ah, q)) { 162 while (ath9k_hw_numtxpending(ah, q)) {
157 if ((--wait) == 0) { 163 if ((--wait) == 0) {
158 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, 164 ath_print(common, ATH_DBG_QUEUE,
159 "Failed to stop TX DMA in 100 " 165 "Failed to stop TX DMA in 100 "
160 "msec after killing last frame\n"); 166 "msec after killing last frame\n");
161 break; 167 break;
162 } 168 }
163 udelay(ATH9K_TIME_QUANTUM); 169 udelay(ATH9K_TIME_QUANTUM);
@@ -172,6 +178,7 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
172#undef ATH9K_TX_STOP_DMA_TIMEOUT 178#undef ATH9K_TX_STOP_DMA_TIMEOUT
173#undef ATH9K_TIME_QUANTUM 179#undef ATH9K_TIME_QUANTUM
174} 180}
181EXPORT_SYMBOL(ath9k_hw_stoptxdma);
175 182
176void ath9k_hw_filltxdesc(struct ath_hw *ah, struct ath_desc *ds, 183void ath9k_hw_filltxdesc(struct ath_hw *ah, struct ath_desc *ds,
177 u32 segLen, bool firstSeg, 184 u32 segLen, bool firstSeg,
@@ -198,6 +205,7 @@ void ath9k_hw_filltxdesc(struct ath_hw *ah, struct ath_desc *ds,
198 ads->ds_txstatus6 = ads->ds_txstatus7 = 0; 205 ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
199 ads->ds_txstatus8 = ads->ds_txstatus9 = 0; 206 ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
200} 207}
208EXPORT_SYMBOL(ath9k_hw_filltxdesc);
201 209
202void ath9k_hw_cleartxdesc(struct ath_hw *ah, struct ath_desc *ds) 210void ath9k_hw_cleartxdesc(struct ath_hw *ah, struct ath_desc *ds)
203{ 211{
@@ -209,6 +217,7 @@ void ath9k_hw_cleartxdesc(struct ath_hw *ah, struct ath_desc *ds)
209 ads->ds_txstatus6 = ads->ds_txstatus7 = 0; 217 ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
210 ads->ds_txstatus8 = ads->ds_txstatus9 = 0; 218 ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
211} 219}
220EXPORT_SYMBOL(ath9k_hw_cleartxdesc);
212 221
213int ath9k_hw_txprocdesc(struct ath_hw *ah, struct ath_desc *ds) 222int ath9k_hw_txprocdesc(struct ath_hw *ah, struct ath_desc *ds)
214{ 223{
@@ -284,6 +293,7 @@ int ath9k_hw_txprocdesc(struct ath_hw *ah, struct ath_desc *ds)
284 293
285 return 0; 294 return 0;
286} 295}
296EXPORT_SYMBOL(ath9k_hw_txprocdesc);
287 297
288void ath9k_hw_set11n_txdesc(struct ath_hw *ah, struct ath_desc *ds, 298void ath9k_hw_set11n_txdesc(struct ath_hw *ah, struct ath_desc *ds,
289 u32 pktLen, enum ath9k_pkt_type type, u32 txPower, 299 u32 pktLen, enum ath9k_pkt_type type, u32 txPower,
@@ -319,6 +329,7 @@ void ath9k_hw_set11n_txdesc(struct ath_hw *ah, struct ath_desc *ds,
319 ads->ds_ctl11 = 0; 329 ads->ds_ctl11 = 0;
320 } 330 }
321} 331}
332EXPORT_SYMBOL(ath9k_hw_set11n_txdesc);
322 333
323void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, struct ath_desc *ds, 334void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, struct ath_desc *ds,
324 struct ath_desc *lastds, 335 struct ath_desc *lastds,
@@ -374,6 +385,7 @@ void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, struct ath_desc *ds,
374 last_ads->ds_ctl2 = ads->ds_ctl2; 385 last_ads->ds_ctl2 = ads->ds_ctl2;
375 last_ads->ds_ctl3 = ads->ds_ctl3; 386 last_ads->ds_ctl3 = ads->ds_ctl3;
376} 387}
388EXPORT_SYMBOL(ath9k_hw_set11n_ratescenario);
377 389
378void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, struct ath_desc *ds, 390void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, struct ath_desc *ds,
379 u32 aggrLen) 391 u32 aggrLen)
@@ -384,6 +396,7 @@ void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, struct ath_desc *ds,
384 ads->ds_ctl6 &= ~AR_AggrLen; 396 ads->ds_ctl6 &= ~AR_AggrLen;
385 ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen); 397 ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen);
386} 398}
399EXPORT_SYMBOL(ath9k_hw_set11n_aggr_first);
387 400
388void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, struct ath_desc *ds, 401void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, struct ath_desc *ds,
389 u32 numDelims) 402 u32 numDelims)
@@ -398,6 +411,7 @@ void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, struct ath_desc *ds,
398 ctl6 |= SM(numDelims, AR_PadDelim); 411 ctl6 |= SM(numDelims, AR_PadDelim);
399 ads->ds_ctl6 = ctl6; 412 ads->ds_ctl6 = ctl6;
400} 413}
414EXPORT_SYMBOL(ath9k_hw_set11n_aggr_middle);
401 415
402void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, struct ath_desc *ds) 416void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, struct ath_desc *ds)
403{ 417{
@@ -407,6 +421,7 @@ void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, struct ath_desc *ds)
407 ads->ds_ctl1 &= ~AR_MoreAggr; 421 ads->ds_ctl1 &= ~AR_MoreAggr;
408 ads->ds_ctl6 &= ~AR_PadDelim; 422 ads->ds_ctl6 &= ~AR_PadDelim;
409} 423}
424EXPORT_SYMBOL(ath9k_hw_set11n_aggr_last);
410 425
411void ath9k_hw_clr11n_aggr(struct ath_hw *ah, struct ath_desc *ds) 426void ath9k_hw_clr11n_aggr(struct ath_hw *ah, struct ath_desc *ds)
412{ 427{
@@ -414,6 +429,7 @@ void ath9k_hw_clr11n_aggr(struct ath_hw *ah, struct ath_desc *ds)
414 429
415 ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr); 430 ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
416} 431}
432EXPORT_SYMBOL(ath9k_hw_clr11n_aggr);
417 433
418void ath9k_hw_set11n_burstduration(struct ath_hw *ah, struct ath_desc *ds, 434void ath9k_hw_set11n_burstduration(struct ath_hw *ah, struct ath_desc *ds,
419 u32 burstDuration) 435 u32 burstDuration)
@@ -423,6 +439,7 @@ void ath9k_hw_set11n_burstduration(struct ath_hw *ah, struct ath_desc *ds,
423 ads->ds_ctl2 &= ~AR_BurstDur; 439 ads->ds_ctl2 &= ~AR_BurstDur;
424 ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur); 440 ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
425} 441}
442EXPORT_SYMBOL(ath9k_hw_set11n_burstduration);
426 443
427void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, struct ath_desc *ds, 444void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, struct ath_desc *ds,
428 u32 vmf) 445 u32 vmf)
@@ -440,28 +457,30 @@ void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs)
440 *txqs &= ah->intr_txqs; 457 *txqs &= ah->intr_txqs;
441 ah->intr_txqs &= ~(*txqs); 458 ah->intr_txqs &= ~(*txqs);
442} 459}
460EXPORT_SYMBOL(ath9k_hw_gettxintrtxqs);
443 461
444bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q, 462bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
445 const struct ath9k_tx_queue_info *qinfo) 463 const struct ath9k_tx_queue_info *qinfo)
446{ 464{
447 u32 cw; 465 u32 cw;
466 struct ath_common *common = ath9k_hw_common(ah);
448 struct ath9k_hw_capabilities *pCap = &ah->caps; 467 struct ath9k_hw_capabilities *pCap = &ah->caps;
449 struct ath9k_tx_queue_info *qi; 468 struct ath9k_tx_queue_info *qi;
450 469
451 if (q >= pCap->total_queues) { 470 if (q >= pCap->total_queues) {
452 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Set TXQ properties, " 471 ath_print(common, ATH_DBG_QUEUE, "Set TXQ properties, "
453 "invalid queue: %u\n", q); 472 "invalid queue: %u\n", q);
454 return false; 473 return false;
455 } 474 }
456 475
457 qi = &ah->txq[q]; 476 qi = &ah->txq[q];
458 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 477 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
459 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Set TXQ properties, " 478 ath_print(common, ATH_DBG_QUEUE, "Set TXQ properties, "
460 "inactive queue: %u\n", q); 479 "inactive queue: %u\n", q);
461 return false; 480 return false;
462 } 481 }
463 482
464 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Set queue properties for: %u\n", q); 483 ath_print(common, ATH_DBG_QUEUE, "Set queue properties for: %u\n", q);
465 484
466 qi->tqi_ver = qinfo->tqi_ver; 485 qi->tqi_ver = qinfo->tqi_ver;
467 qi->tqi_subtype = qinfo->tqi_subtype; 486 qi->tqi_subtype = qinfo->tqi_subtype;
@@ -510,23 +529,25 @@ bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
510 529
511 return true; 530 return true;
512} 531}
532EXPORT_SYMBOL(ath9k_hw_set_txq_props);
513 533
514bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q, 534bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
515 struct ath9k_tx_queue_info *qinfo) 535 struct ath9k_tx_queue_info *qinfo)
516{ 536{
537 struct ath_common *common = ath9k_hw_common(ah);
517 struct ath9k_hw_capabilities *pCap = &ah->caps; 538 struct ath9k_hw_capabilities *pCap = &ah->caps;
518 struct ath9k_tx_queue_info *qi; 539 struct ath9k_tx_queue_info *qi;
519 540
520 if (q >= pCap->total_queues) { 541 if (q >= pCap->total_queues) {
521 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Get TXQ properties, " 542 ath_print(common, ATH_DBG_QUEUE, "Get TXQ properties, "
522 "invalid queue: %u\n", q); 543 "invalid queue: %u\n", q);
523 return false; 544 return false;
524 } 545 }
525 546
526 qi = &ah->txq[q]; 547 qi = &ah->txq[q];
527 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 548 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
528 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Get TXQ properties, " 549 ath_print(common, ATH_DBG_QUEUE, "Get TXQ properties, "
529 "inactive queue: %u\n", q); 550 "inactive queue: %u\n", q);
530 return false; 551 return false;
531 } 552 }
532 553
@@ -547,10 +568,12 @@ bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
547 568
548 return true; 569 return true;
549} 570}
571EXPORT_SYMBOL(ath9k_hw_get_txq_props);
550 572
551int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type, 573int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
552 const struct ath9k_tx_queue_info *qinfo) 574 const struct ath9k_tx_queue_info *qinfo)
553{ 575{
576 struct ath_common *common = ath9k_hw_common(ah);
554 struct ath9k_tx_queue_info *qi; 577 struct ath9k_tx_queue_info *qi;
555 struct ath9k_hw_capabilities *pCap = &ah->caps; 578 struct ath9k_hw_capabilities *pCap = &ah->caps;
556 int q; 579 int q;
@@ -574,23 +597,23 @@ int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
574 ATH9K_TX_QUEUE_INACTIVE) 597 ATH9K_TX_QUEUE_INACTIVE)
575 break; 598 break;
576 if (q == pCap->total_queues) { 599 if (q == pCap->total_queues) {
577 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 600 ath_print(common, ATH_DBG_FATAL,
578 "No available TX queue\n"); 601 "No available TX queue\n");
579 return -1; 602 return -1;
580 } 603 }
581 break; 604 break;
582 default: 605 default:
583 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Invalid TX queue type: %u\n", 606 ath_print(common, ATH_DBG_FATAL,
584 type); 607 "Invalid TX queue type: %u\n", type);
585 return -1; 608 return -1;
586 } 609 }
587 610
588 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Setup TX queue: %u\n", q); 611 ath_print(common, ATH_DBG_QUEUE, "Setup TX queue: %u\n", q);
589 612
590 qi = &ah->txq[q]; 613 qi = &ah->txq[q];
591 if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) { 614 if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) {
592 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 615 ath_print(common, ATH_DBG_FATAL,
593 "TX queue: %u already active\n", q); 616 "TX queue: %u already active\n", q);
594 return -1; 617 return -1;
595 } 618 }
596 memset(qi, 0, sizeof(struct ath9k_tx_queue_info)); 619 memset(qi, 0, sizeof(struct ath9k_tx_queue_info));
@@ -613,25 +636,27 @@ int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
613 636
614 return q; 637 return q;
615} 638}
639EXPORT_SYMBOL(ath9k_hw_setuptxqueue);
616 640
617bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q) 641bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
618{ 642{
619 struct ath9k_hw_capabilities *pCap = &ah->caps; 643 struct ath9k_hw_capabilities *pCap = &ah->caps;
644 struct ath_common *common = ath9k_hw_common(ah);
620 struct ath9k_tx_queue_info *qi; 645 struct ath9k_tx_queue_info *qi;
621 646
622 if (q >= pCap->total_queues) { 647 if (q >= pCap->total_queues) {
623 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Release TXQ, " 648 ath_print(common, ATH_DBG_QUEUE, "Release TXQ, "
624 "invalid queue: %u\n", q); 649 "invalid queue: %u\n", q);
625 return false; 650 return false;
626 } 651 }
627 qi = &ah->txq[q]; 652 qi = &ah->txq[q];
628 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 653 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
629 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Release TXQ, " 654 ath_print(common, ATH_DBG_QUEUE, "Release TXQ, "
630 "inactive queue: %u\n", q); 655 "inactive queue: %u\n", q);
631 return false; 656 return false;
632 } 657 }
633 658
634 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Release TX queue: %u\n", q); 659 ath_print(common, ATH_DBG_QUEUE, "Release TX queue: %u\n", q);
635 660
636 qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE; 661 qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE;
637 ah->txok_interrupt_mask &= ~(1 << q); 662 ah->txok_interrupt_mask &= ~(1 << q);
@@ -643,28 +668,30 @@ bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
643 668
644 return true; 669 return true;
645} 670}
671EXPORT_SYMBOL(ath9k_hw_releasetxqueue);
646 672
647bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q) 673bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
648{ 674{
649 struct ath9k_hw_capabilities *pCap = &ah->caps; 675 struct ath9k_hw_capabilities *pCap = &ah->caps;
676 struct ath_common *common = ath9k_hw_common(ah);
650 struct ath9k_channel *chan = ah->curchan; 677 struct ath9k_channel *chan = ah->curchan;
651 struct ath9k_tx_queue_info *qi; 678 struct ath9k_tx_queue_info *qi;
652 u32 cwMin, chanCwMin, value; 679 u32 cwMin, chanCwMin, value;
653 680
654 if (q >= pCap->total_queues) { 681 if (q >= pCap->total_queues) {
655 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Reset TXQ, " 682 ath_print(common, ATH_DBG_QUEUE, "Reset TXQ, "
656 "invalid queue: %u\n", q); 683 "invalid queue: %u\n", q);
657 return false; 684 return false;
658 } 685 }
659 686
660 qi = &ah->txq[q]; 687 qi = &ah->txq[q];
661 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 688 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
662 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Reset TXQ, " 689 ath_print(common, ATH_DBG_QUEUE, "Reset TXQ, "
663 "inactive queue: %u\n", q); 690 "inactive queue: %u\n", q);
664 return true; 691 return true;
665 } 692 }
666 693
667 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Reset TX queue: %u\n", q); 694 ath_print(common, ATH_DBG_QUEUE, "Reset TX queue: %u\n", q);
668 695
669 if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) { 696 if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) {
670 if (chan && IS_CHAN_B(chan)) 697 if (chan && IS_CHAN_B(chan))
@@ -799,6 +826,7 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
799 826
800 return true; 827 return true;
801} 828}
829EXPORT_SYMBOL(ath9k_hw_resettxqueue);
802 830
803int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds, 831int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
804 u32 pa, struct ath_desc *nds, u64 tsf) 832 u32 pa, struct ath_desc *nds, u64 tsf)
@@ -880,6 +908,7 @@ int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
880 908
881 return 0; 909 return 0;
882} 910}
911EXPORT_SYMBOL(ath9k_hw_rxprocdesc);
883 912
884void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds, 913void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
885 u32 size, u32 flags) 914 u32 size, u32 flags)
@@ -895,6 +924,7 @@ void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
895 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 924 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
896 memset(&(ads->u), 0, sizeof(ads->u)); 925 memset(&(ads->u), 0, sizeof(ads->u));
897} 926}
927EXPORT_SYMBOL(ath9k_hw_setuprxdesc);
898 928
899bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set) 929bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set)
900{ 930{
@@ -911,8 +941,9 @@ bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set)
911 AR_DIAG_RX_ABORT)); 941 AR_DIAG_RX_ABORT));
912 942
913 reg = REG_READ(ah, AR_OBS_BUS_1); 943 reg = REG_READ(ah, AR_OBS_BUS_1);
914 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 944 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
915 "RX failed to go idle in 10 ms RXSM=0x%x\n", reg); 945 "RX failed to go idle in 10 ms RXSM=0x%x\n",
946 reg);
916 947
917 return false; 948 return false;
918 } 949 }
@@ -923,16 +954,19 @@ bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set)
923 954
924 return true; 955 return true;
925} 956}
957EXPORT_SYMBOL(ath9k_hw_setrxabort);
926 958
927void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp) 959void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp)
928{ 960{
929 REG_WRITE(ah, AR_RXDP, rxdp); 961 REG_WRITE(ah, AR_RXDP, rxdp);
930} 962}
963EXPORT_SYMBOL(ath9k_hw_putrxbuf);
931 964
932void ath9k_hw_rxena(struct ath_hw *ah) 965void ath9k_hw_rxena(struct ath_hw *ah)
933{ 966{
934 REG_WRITE(ah, AR_CR, AR_CR_RXE); 967 REG_WRITE(ah, AR_CR, AR_CR_RXE);
935} 968}
969EXPORT_SYMBOL(ath9k_hw_rxena);
936 970
937void ath9k_hw_startpcureceive(struct ath_hw *ah) 971void ath9k_hw_startpcureceive(struct ath_hw *ah)
938{ 972{
@@ -942,6 +976,7 @@ void ath9k_hw_startpcureceive(struct ath_hw *ah)
942 976
943 REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); 977 REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
944} 978}
979EXPORT_SYMBOL(ath9k_hw_startpcureceive);
945 980
946void ath9k_hw_stoppcurecv(struct ath_hw *ah) 981void ath9k_hw_stoppcurecv(struct ath_hw *ah)
947{ 982{
@@ -949,12 +984,13 @@ void ath9k_hw_stoppcurecv(struct ath_hw *ah)
949 984
950 ath9k_hw_disable_mib_counters(ah); 985 ath9k_hw_disable_mib_counters(ah);
951} 986}
987EXPORT_SYMBOL(ath9k_hw_stoppcurecv);
952 988
953bool ath9k_hw_stopdmarecv(struct ath_hw *ah) 989bool ath9k_hw_stopdmarecv(struct ath_hw *ah)
954{ 990{
955#define AH_RX_STOP_DMA_TIMEOUT 10000 /* usec */ 991#define AH_RX_STOP_DMA_TIMEOUT 10000 /* usec */
956#define AH_RX_TIME_QUANTUM 100 /* usec */ 992#define AH_RX_TIME_QUANTUM 100 /* usec */
957 993 struct ath_common *common = ath9k_hw_common(ah);
958 int i; 994 int i;
959 995
960 REG_WRITE(ah, AR_CR, AR_CR_RXD); 996 REG_WRITE(ah, AR_CR, AR_CR_RXD);
@@ -967,12 +1003,12 @@ bool ath9k_hw_stopdmarecv(struct ath_hw *ah)
967 } 1003 }
968 1004
969 if (i == 0) { 1005 if (i == 0) {
970 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 1006 ath_print(common, ATH_DBG_FATAL,
971 "DMA failed to stop in %d ms " 1007 "DMA failed to stop in %d ms "
972 "AR_CR=0x%08x AR_DIAG_SW=0x%08x\n", 1008 "AR_CR=0x%08x AR_DIAG_SW=0x%08x\n",
973 AH_RX_STOP_DMA_TIMEOUT / 1000, 1009 AH_RX_STOP_DMA_TIMEOUT / 1000,
974 REG_READ(ah, AR_CR), 1010 REG_READ(ah, AR_CR),
975 REG_READ(ah, AR_DIAG_SW)); 1011 REG_READ(ah, AR_DIAG_SW));
976 return false; 1012 return false;
977 } else { 1013 } else {
978 return true; 1014 return true;
@@ -981,3 +1017,17 @@ bool ath9k_hw_stopdmarecv(struct ath_hw *ah)
981#undef AH_RX_TIME_QUANTUM 1017#undef AH_RX_TIME_QUANTUM
982#undef AH_RX_STOP_DMA_TIMEOUT 1018#undef AH_RX_STOP_DMA_TIMEOUT
983} 1019}
1020EXPORT_SYMBOL(ath9k_hw_stopdmarecv);
1021
1022int ath9k_hw_beaconq_setup(struct ath_hw *ah)
1023{
1024 struct ath9k_tx_queue_info qi;
1025
1026 memset(&qi, 0, sizeof(qi));
1027 qi.tqi_aifs = 1;
1028 qi.tqi_cwmin = 0;
1029 qi.tqi_cwmax = 0;
1030 /* NB: don't enable any interrupts */
1031 return ath9k_hw_setuptxqueue(ah, ATH9K_TX_QUEUE_BEACON, &qi);
1032}
1033EXPORT_SYMBOL(ath9k_hw_beaconq_setup);
diff --git a/drivers/net/wireless/ath/ath9k/mac.h b/drivers/net/wireless/ath/ath9k/mac.h
index f56e77da6c3e..fefb65dafb1c 100644
--- a/drivers/net/wireless/ath/ath9k/mac.h
+++ b/drivers/net/wireless/ath/ath9k/mac.h
@@ -614,16 +614,6 @@ enum ath9k_cipher {
614 ATH9K_CIPHER_MIC = 127 614 ATH9K_CIPHER_MIC = 127
615}; 615};
616 616
617enum ath9k_ht_macmode {
618 ATH9K_HT_MACMODE_20 = 0,
619 ATH9K_HT_MACMODE_2040 = 1,
620};
621
622enum ath9k_ht_extprotspacing {
623 ATH9K_HT_EXTPROTSPACING_20 = 0,
624 ATH9K_HT_EXTPROTSPACING_25 = 1,
625};
626
627struct ath_hw; 617struct ath_hw;
628struct ath9k_channel; 618struct ath9k_channel;
629struct ath_rate_table; 619struct ath_rate_table;
@@ -677,5 +667,6 @@ void ath9k_hw_rxena(struct ath_hw *ah);
677void ath9k_hw_startpcureceive(struct ath_hw *ah); 667void ath9k_hw_startpcureceive(struct ath_hw *ah);
678void ath9k_hw_stoppcurecv(struct ath_hw *ah); 668void ath9k_hw_stoppcurecv(struct ath_hw *ah);
679bool ath9k_hw_stopdmarecv(struct ath_hw *ah); 669bool ath9k_hw_stopdmarecv(struct ath_hw *ah);
670int ath9k_hw_beaconq_setup(struct ath_hw *ah);
680 671
681#endif /* MAC_H */ 672#endif /* MAC_H */
diff --git a/drivers/net/wireless/ath/ath9k/main.c b/drivers/net/wireless/ath/ath9k/main.c
index 43d2be9867fc..cbf5d2a1bb26 100644
--- a/drivers/net/wireless/ath/ath9k/main.c
+++ b/drivers/net/wireless/ath/ath9k/main.c
@@ -16,6 +16,7 @@
16 16
17#include <linux/nl80211.h> 17#include <linux/nl80211.h>
18#include "ath9k.h" 18#include "ath9k.h"
19#include "btcoex.h"
19 20
20static char *dev_info = "ath9k"; 21static char *dev_info = "ath9k";
21 22
@@ -28,6 +29,10 @@ static int modparam_nohwcrypt;
28module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444); 29module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
29MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption"); 30MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
30 31
32static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
33module_param_named(debug, ath9k_debug, uint, 0);
34MODULE_PARM_DESC(debug, "Debugging mask");
35
31/* We use the hw_value as an index into our private channel structure */ 36/* We use the hw_value as an index into our private channel structure */
32 37
33#define CHAN2G(_freq, _idx) { \ 38#define CHAN2G(_freq, _idx) { \
@@ -224,8 +229,9 @@ static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
224 } 229 }
225 sband->n_bitrates++; 230 sband->n_bitrates++;
226 231
227 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n", 232 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
228 rate[i].bitrate / 10, rate[i].hw_value); 233 "Rate: %2dMbps, ratecode: %2d\n",
234 rate[i].bitrate / 10, rate[i].hw_value);
229 } 235 }
230} 236}
231 237
@@ -242,6 +248,51 @@ static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
242 return channel; 248 return channel;
243} 249}
244 250
251static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
252{
253 unsigned long flags;
254 bool ret;
255
256 spin_lock_irqsave(&sc->sc_pm_lock, flags);
257 ret = ath9k_hw_setpower(sc->sc_ah, mode);
258 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
259
260 return ret;
261}
262
263void ath9k_ps_wakeup(struct ath_softc *sc)
264{
265 unsigned long flags;
266
267 spin_lock_irqsave(&sc->sc_pm_lock, flags);
268 if (++sc->ps_usecount != 1)
269 goto unlock;
270
271 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
272
273 unlock:
274 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
275}
276
277void ath9k_ps_restore(struct ath_softc *sc)
278{
279 unsigned long flags;
280
281 spin_lock_irqsave(&sc->sc_pm_lock, flags);
282 if (--sc->ps_usecount != 0)
283 goto unlock;
284
285 if (sc->ps_enabled &&
286 !(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
287 SC_OP_WAIT_FOR_CAB |
288 SC_OP_WAIT_FOR_PSPOLL_DATA |
289 SC_OP_WAIT_FOR_TX_ACK)))
290 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
291
292 unlock:
293 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
294}
295
245/* 296/*
246 * Set/change channels. If the channel is really being changed, it's done 297 * Set/change channels. If the channel is really being changed, it's done
247 * by reseting the chip. To accomplish this we must first cleanup any pending 298 * by reseting the chip. To accomplish this we must first cleanup any pending
@@ -251,6 +302,8 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
251 struct ath9k_channel *hchan) 302 struct ath9k_channel *hchan)
252{ 303{
253 struct ath_hw *ah = sc->sc_ah; 304 struct ath_hw *ah = sc->sc_ah;
305 struct ath_common *common = ath9k_hw_common(ah);
306 struct ieee80211_conf *conf = &common->hw->conf;
254 bool fastcc = true, stopped; 307 bool fastcc = true, stopped;
255 struct ieee80211_channel *channel = hw->conf.channel; 308 struct ieee80211_channel *channel = hw->conf.channel;
256 int r; 309 int r;
@@ -280,19 +333,19 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
280 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET)) 333 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
281 fastcc = false; 334 fastcc = false;
282 335
283 DPRINTF(sc, ATH_DBG_CONFIG, 336 ath_print(common, ATH_DBG_CONFIG,
284 "(%u MHz) -> (%u MHz), chanwidth: %d\n", 337 "(%u MHz) -> (%u MHz), conf_is_ht40: %d\n",
285 sc->sc_ah->curchan->channel, 338 sc->sc_ah->curchan->channel,
286 channel->center_freq, sc->tx_chan_width); 339 channel->center_freq, conf_is_ht40(conf));
287 340
288 spin_lock_bh(&sc->sc_resetlock); 341 spin_lock_bh(&sc->sc_resetlock);
289 342
290 r = ath9k_hw_reset(ah, hchan, fastcc); 343 r = ath9k_hw_reset(ah, hchan, fastcc);
291 if (r) { 344 if (r) {
292 DPRINTF(sc, ATH_DBG_FATAL, 345 ath_print(common, ATH_DBG_FATAL,
293 "Unable to reset channel (%u Mhz) " 346 "Unable to reset channel (%u Mhz) "
294 "reset status %d\n", 347 "reset status %d\n",
295 channel->center_freq, r); 348 channel->center_freq, r);
296 spin_unlock_bh(&sc->sc_resetlock); 349 spin_unlock_bh(&sc->sc_resetlock);
297 goto ps_restore; 350 goto ps_restore;
298 } 351 }
@@ -301,8 +354,8 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
301 sc->sc_flags &= ~SC_OP_FULL_RESET; 354 sc->sc_flags &= ~SC_OP_FULL_RESET;
302 355
303 if (ath_startrecv(sc) != 0) { 356 if (ath_startrecv(sc) != 0) {
304 DPRINTF(sc, ATH_DBG_FATAL, 357 ath_print(common, ATH_DBG_FATAL,
305 "Unable to restart recv logic\n"); 358 "Unable to restart recv logic\n");
306 r = -EIO; 359 r = -EIO;
307 goto ps_restore; 360 goto ps_restore;
308 } 361 }
@@ -327,6 +380,7 @@ static void ath_ani_calibrate(unsigned long data)
327{ 380{
328 struct ath_softc *sc = (struct ath_softc *)data; 381 struct ath_softc *sc = (struct ath_softc *)data;
329 struct ath_hw *ah = sc->sc_ah; 382 struct ath_hw *ah = sc->sc_ah;
383 struct ath_common *common = ath9k_hw_common(ah);
330 bool longcal = false; 384 bool longcal = false;
331 bool shortcal = false; 385 bool shortcal = false;
332 bool aniflag = false; 386 bool aniflag = false;
@@ -351,33 +405,34 @@ static void ath_ani_calibrate(unsigned long data)
351 ath9k_ps_wakeup(sc); 405 ath9k_ps_wakeup(sc);
352 406
353 /* Long calibration runs independently of short calibration. */ 407 /* Long calibration runs independently of short calibration. */
354 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) { 408 if ((timestamp - common->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
355 longcal = true; 409 longcal = true;
356 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies); 410 ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
357 sc->ani.longcal_timer = timestamp; 411 common->ani.longcal_timer = timestamp;
358 } 412 }
359 413
360 /* Short calibration applies only while caldone is false */ 414 /* Short calibration applies only while caldone is false */
361 if (!sc->ani.caldone) { 415 if (!common->ani.caldone) {
362 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) { 416 if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
363 shortcal = true; 417 shortcal = true;
364 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies); 418 ath_print(common, ATH_DBG_ANI,
365 sc->ani.shortcal_timer = timestamp; 419 "shortcal @%lu\n", jiffies);
366 sc->ani.resetcal_timer = timestamp; 420 common->ani.shortcal_timer = timestamp;
421 common->ani.resetcal_timer = timestamp;
367 } 422 }
368 } else { 423 } else {
369 if ((timestamp - sc->ani.resetcal_timer) >= 424 if ((timestamp - common->ani.resetcal_timer) >=
370 ATH_RESTART_CALINTERVAL) { 425 ATH_RESTART_CALINTERVAL) {
371 sc->ani.caldone = ath9k_hw_reset_calvalid(ah); 426 common->ani.caldone = ath9k_hw_reset_calvalid(ah);
372 if (sc->ani.caldone) 427 if (common->ani.caldone)
373 sc->ani.resetcal_timer = timestamp; 428 common->ani.resetcal_timer = timestamp;
374 } 429 }
375 } 430 }
376 431
377 /* Verify whether we must check ANI */ 432 /* Verify whether we must check ANI */
378 if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) { 433 if ((timestamp - common->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
379 aniflag = true; 434 aniflag = true;
380 sc->ani.checkani_timer = timestamp; 435 common->ani.checkani_timer = timestamp;
381 } 436 }
382 437
383 /* Skip all processing if there's nothing to do. */ 438 /* Skip all processing if there's nothing to do. */
@@ -388,16 +443,21 @@ static void ath_ani_calibrate(unsigned long data)
388 443
389 /* Perform calibration if necessary */ 444 /* Perform calibration if necessary */
390 if (longcal || shortcal) { 445 if (longcal || shortcal) {
391 sc->ani.caldone = ath9k_hw_calibrate(ah, ah->curchan, 446 common->ani.caldone =
392 sc->rx_chainmask, longcal); 447 ath9k_hw_calibrate(ah,
448 ah->curchan,
449 common->rx_chainmask,
450 longcal);
393 451
394 if (longcal) 452 if (longcal)
395 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah, 453 common->ani.noise_floor = ath9k_hw_getchan_noise(ah,
396 ah->curchan); 454 ah->curchan);
397 455
398 DPRINTF(sc, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n", 456 ath_print(common, ATH_DBG_ANI,
399 ah->curchan->channel, ah->curchan->channelFlags, 457 " calibrate chan %u/%x nf: %d\n",
400 sc->ani.noise_floor); 458 ah->curchan->channel,
459 ah->curchan->channelFlags,
460 common->ani.noise_floor);
401 } 461 }
402 } 462 }
403 463
@@ -413,21 +473,21 @@ set_timer:
413 cal_interval = ATH_LONG_CALINTERVAL; 473 cal_interval = ATH_LONG_CALINTERVAL;
414 if (sc->sc_ah->config.enable_ani) 474 if (sc->sc_ah->config.enable_ani)
415 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL); 475 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
416 if (!sc->ani.caldone) 476 if (!common->ani.caldone)
417 cal_interval = min(cal_interval, (u32)short_cal_interval); 477 cal_interval = min(cal_interval, (u32)short_cal_interval);
418 478
419 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval)); 479 mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
420} 480}
421 481
422static void ath_start_ani(struct ath_softc *sc) 482static void ath_start_ani(struct ath_common *common)
423{ 483{
424 unsigned long timestamp = jiffies_to_msecs(jiffies); 484 unsigned long timestamp = jiffies_to_msecs(jiffies);
425 485
426 sc->ani.longcal_timer = timestamp; 486 common->ani.longcal_timer = timestamp;
427 sc->ani.shortcal_timer = timestamp; 487 common->ani.shortcal_timer = timestamp;
428 sc->ani.checkani_timer = timestamp; 488 common->ani.checkani_timer = timestamp;
429 489
430 mod_timer(&sc->ani.timer, 490 mod_timer(&common->ani.timer,
431 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL)); 491 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
432} 492}
433 493
@@ -439,17 +499,22 @@ static void ath_start_ani(struct ath_softc *sc)
439 */ 499 */
440void ath_update_chainmask(struct ath_softc *sc, int is_ht) 500void ath_update_chainmask(struct ath_softc *sc, int is_ht)
441{ 501{
502 struct ath_hw *ah = sc->sc_ah;
503 struct ath_common *common = ath9k_hw_common(ah);
504
442 if ((sc->sc_flags & SC_OP_SCANNING) || is_ht || 505 if ((sc->sc_flags & SC_OP_SCANNING) || is_ht ||
443 (sc->btcoex_info.btcoex_scheme != ATH_BTCOEX_CFG_NONE)) { 506 (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) {
444 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask; 507 common->tx_chainmask = ah->caps.tx_chainmask;
445 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask; 508 common->rx_chainmask = ah->caps.rx_chainmask;
446 } else { 509 } else {
447 sc->tx_chainmask = 1; 510 common->tx_chainmask = 1;
448 sc->rx_chainmask = 1; 511 common->rx_chainmask = 1;
449 } 512 }
450 513
451 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n", 514 ath_print(common, ATH_DBG_CONFIG,
452 sc->tx_chainmask, sc->rx_chainmask); 515 "tx chmask: %d, rx chmask: %d\n",
516 common->tx_chainmask,
517 common->rx_chainmask);
453} 518}
454 519
455static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta) 520static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
@@ -478,6 +543,9 @@ static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
478static void ath9k_tasklet(unsigned long data) 543static void ath9k_tasklet(unsigned long data)
479{ 544{
480 struct ath_softc *sc = (struct ath_softc *)data; 545 struct ath_softc *sc = (struct ath_softc *)data;
546 struct ath_hw *ah = sc->sc_ah;
547 struct ath_common *common = ath9k_hw_common(ah);
548
481 u32 status = sc->intrstatus; 549 u32 status = sc->intrstatus;
482 550
483 ath9k_ps_wakeup(sc); 551 ath9k_ps_wakeup(sc);
@@ -502,16 +570,17 @@ static void ath9k_tasklet(unsigned long data)
502 * TSF sync does not look correct; remain awake to sync with 570 * TSF sync does not look correct; remain awake to sync with
503 * the next Beacon. 571 * the next Beacon.
504 */ 572 */
505 DPRINTF(sc, ATH_DBG_PS, "TSFOOR - Sync with next Beacon\n"); 573 ath_print(common, ATH_DBG_PS,
574 "TSFOOR - Sync with next Beacon\n");
506 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC; 575 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
507 } 576 }
508 577
509 if (sc->btcoex_info.btcoex_scheme == ATH_BTCOEX_CFG_3WIRE) 578 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
510 if (status & ATH9K_INT_GENTIMER) 579 if (status & ATH9K_INT_GENTIMER)
511 ath_gen_timer_isr(sc->sc_ah); 580 ath_gen_timer_isr(sc->sc_ah);
512 581
513 /* re-enable hardware interrupt */ 582 /* re-enable hardware interrupt */
514 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask); 583 ath9k_hw_set_interrupts(ah, sc->imask);
515 ath9k_ps_restore(sc); 584 ath9k_ps_restore(sc);
516} 585}
517 586
@@ -602,7 +671,7 @@ irqreturn_t ath_isr(int irq, void *dev)
602 if (status & ATH9K_INT_TIM_TIMER) { 671 if (status & ATH9K_INT_TIM_TIMER) {
603 /* Clear RxAbort bit so that we can 672 /* Clear RxAbort bit so that we can
604 * receive frames */ 673 * receive frames */
605 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE); 674 ath9k_setpower(sc, ATH9K_PM_AWAKE);
606 ath9k_hw_setrxabort(sc->sc_ah, 0); 675 ath9k_hw_setrxabort(sc->sc_ah, 0);
607 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON; 676 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
608 } 677 }
@@ -664,10 +733,11 @@ static u32 ath_get_extchanmode(struct ath_softc *sc,
664 return chanmode; 733 return chanmode;
665} 734}
666 735
667static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key, 736static int ath_setkey_tkip(struct ath_common *common, u16 keyix, const u8 *key,
668 struct ath9k_keyval *hk, const u8 *addr, 737 struct ath9k_keyval *hk, const u8 *addr,
669 bool authenticator) 738 bool authenticator)
670{ 739{
740 struct ath_hw *ah = common->ah;
671 const u8 *key_rxmic; 741 const u8 *key_rxmic;
672 const u8 *key_txmic; 742 const u8 *key_txmic;
673 743
@@ -687,42 +757,42 @@ static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
687 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic)); 757 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
688 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic)); 758 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
689 } 759 }
690 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr); 760 return ath9k_hw_set_keycache_entry(ah, keyix, hk, addr);
691 } 761 }
692 if (!sc->splitmic) { 762 if (!common->splitmic) {
693 /* TX and RX keys share the same key cache entry. */ 763 /* TX and RX keys share the same key cache entry. */
694 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic)); 764 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
695 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic)); 765 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
696 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr); 766 return ath9k_hw_set_keycache_entry(ah, keyix, hk, addr);
697 } 767 }
698 768
699 /* Separate key cache entries for TX and RX */ 769 /* Separate key cache entries for TX and RX */
700 770
701 /* TX key goes at first index, RX key at +32. */ 771 /* TX key goes at first index, RX key at +32. */
702 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic)); 772 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
703 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) { 773 if (!ath9k_hw_set_keycache_entry(ah, keyix, hk, NULL)) {
704 /* TX MIC entry failed. No need to proceed further */ 774 /* TX MIC entry failed. No need to proceed further */
705 DPRINTF(sc, ATH_DBG_FATAL, 775 ath_print(common, ATH_DBG_FATAL,
706 "Setting TX MIC Key Failed\n"); 776 "Setting TX MIC Key Failed\n");
707 return 0; 777 return 0;
708 } 778 }
709 779
710 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic)); 780 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
711 /* XXX delete tx key on failure? */ 781 /* XXX delete tx key on failure? */
712 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr); 782 return ath9k_hw_set_keycache_entry(ah, keyix + 32, hk, addr);
713} 783}
714 784
715static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc) 785static int ath_reserve_key_cache_slot_tkip(struct ath_common *common)
716{ 786{
717 int i; 787 int i;
718 788
719 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) { 789 for (i = IEEE80211_WEP_NKID; i < common->keymax / 2; i++) {
720 if (test_bit(i, sc->keymap) || 790 if (test_bit(i, common->keymap) ||
721 test_bit(i + 64, sc->keymap)) 791 test_bit(i + 64, common->keymap))
722 continue; /* At least one part of TKIP key allocated */ 792 continue; /* At least one part of TKIP key allocated */
723 if (sc->splitmic && 793 if (common->splitmic &&
724 (test_bit(i + 32, sc->keymap) || 794 (test_bit(i + 32, common->keymap) ||
725 test_bit(i + 64 + 32, sc->keymap))) 795 test_bit(i + 64 + 32, common->keymap)))
726 continue; /* At least one part of TKIP key allocated */ 796 continue; /* At least one part of TKIP key allocated */
727 797
728 /* Found a free slot for a TKIP key */ 798 /* Found a free slot for a TKIP key */
@@ -731,60 +801,60 @@ static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
731 return -1; 801 return -1;
732} 802}
733 803
734static int ath_reserve_key_cache_slot(struct ath_softc *sc) 804static int ath_reserve_key_cache_slot(struct ath_common *common)
735{ 805{
736 int i; 806 int i;
737 807
738 /* First, try to find slots that would not be available for TKIP. */ 808 /* First, try to find slots that would not be available for TKIP. */
739 if (sc->splitmic) { 809 if (common->splitmic) {
740 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) { 810 for (i = IEEE80211_WEP_NKID; i < common->keymax / 4; i++) {
741 if (!test_bit(i, sc->keymap) && 811 if (!test_bit(i, common->keymap) &&
742 (test_bit(i + 32, sc->keymap) || 812 (test_bit(i + 32, common->keymap) ||
743 test_bit(i + 64, sc->keymap) || 813 test_bit(i + 64, common->keymap) ||
744 test_bit(i + 64 + 32, sc->keymap))) 814 test_bit(i + 64 + 32, common->keymap)))
745 return i; 815 return i;
746 if (!test_bit(i + 32, sc->keymap) && 816 if (!test_bit(i + 32, common->keymap) &&
747 (test_bit(i, sc->keymap) || 817 (test_bit(i, common->keymap) ||
748 test_bit(i + 64, sc->keymap) || 818 test_bit(i + 64, common->keymap) ||
749 test_bit(i + 64 + 32, sc->keymap))) 819 test_bit(i + 64 + 32, common->keymap)))
750 return i + 32; 820 return i + 32;
751 if (!test_bit(i + 64, sc->keymap) && 821 if (!test_bit(i + 64, common->keymap) &&
752 (test_bit(i , sc->keymap) || 822 (test_bit(i , common->keymap) ||
753 test_bit(i + 32, sc->keymap) || 823 test_bit(i + 32, common->keymap) ||
754 test_bit(i + 64 + 32, sc->keymap))) 824 test_bit(i + 64 + 32, common->keymap)))
755 return i + 64; 825 return i + 64;
756 if (!test_bit(i + 64 + 32, sc->keymap) && 826 if (!test_bit(i + 64 + 32, common->keymap) &&
757 (test_bit(i, sc->keymap) || 827 (test_bit(i, common->keymap) ||
758 test_bit(i + 32, sc->keymap) || 828 test_bit(i + 32, common->keymap) ||
759 test_bit(i + 64, sc->keymap))) 829 test_bit(i + 64, common->keymap)))
760 return i + 64 + 32; 830 return i + 64 + 32;
761 } 831 }
762 } else { 832 } else {
763 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) { 833 for (i = IEEE80211_WEP_NKID; i < common->keymax / 2; i++) {
764 if (!test_bit(i, sc->keymap) && 834 if (!test_bit(i, common->keymap) &&
765 test_bit(i + 64, sc->keymap)) 835 test_bit(i + 64, common->keymap))
766 return i; 836 return i;
767 if (test_bit(i, sc->keymap) && 837 if (test_bit(i, common->keymap) &&
768 !test_bit(i + 64, sc->keymap)) 838 !test_bit(i + 64, common->keymap))
769 return i + 64; 839 return i + 64;
770 } 840 }
771 } 841 }
772 842
773 /* No partially used TKIP slots, pick any available slot */ 843 /* No partially used TKIP slots, pick any available slot */
774 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) { 844 for (i = IEEE80211_WEP_NKID; i < common->keymax; i++) {
775 /* Do not allow slots that could be needed for TKIP group keys 845 /* Do not allow slots that could be needed for TKIP group keys
776 * to be used. This limitation could be removed if we know that 846 * to be used. This limitation could be removed if we know that
777 * TKIP will not be used. */ 847 * TKIP will not be used. */
778 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID) 848 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
779 continue; 849 continue;
780 if (sc->splitmic) { 850 if (common->splitmic) {
781 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID) 851 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
782 continue; 852 continue;
783 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID) 853 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
784 continue; 854 continue;
785 } 855 }
786 856
787 if (!test_bit(i, sc->keymap)) 857 if (!test_bit(i, common->keymap))
788 return i; /* Found a free slot for a key */ 858 return i; /* Found a free slot for a key */
789 } 859 }
790 860
@@ -792,11 +862,12 @@ static int ath_reserve_key_cache_slot(struct ath_softc *sc)
792 return -1; 862 return -1;
793} 863}
794 864
795static int ath_key_config(struct ath_softc *sc, 865static int ath_key_config(struct ath_common *common,
796 struct ieee80211_vif *vif, 866 struct ieee80211_vif *vif,
797 struct ieee80211_sta *sta, 867 struct ieee80211_sta *sta,
798 struct ieee80211_key_conf *key) 868 struct ieee80211_key_conf *key)
799{ 869{
870 struct ath_hw *ah = common->ah;
800 struct ath9k_keyval hk; 871 struct ath9k_keyval hk;
801 const u8 *mac = NULL; 872 const u8 *mac = NULL;
802 int ret = 0; 873 int ret = 0;
@@ -842,54 +913,57 @@ static int ath_key_config(struct ath_softc *sc,
842 mac = sta->addr; 913 mac = sta->addr;
843 914
844 if (key->alg == ALG_TKIP) 915 if (key->alg == ALG_TKIP)
845 idx = ath_reserve_key_cache_slot_tkip(sc); 916 idx = ath_reserve_key_cache_slot_tkip(common);
846 else 917 else
847 idx = ath_reserve_key_cache_slot(sc); 918 idx = ath_reserve_key_cache_slot(common);
848 if (idx < 0) 919 if (idx < 0)
849 return -ENOSPC; /* no free key cache entries */ 920 return -ENOSPC; /* no free key cache entries */
850 } 921 }
851 922
852 if (key->alg == ALG_TKIP) 923 if (key->alg == ALG_TKIP)
853 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac, 924 ret = ath_setkey_tkip(common, idx, key->key, &hk, mac,
854 vif->type == NL80211_IFTYPE_AP); 925 vif->type == NL80211_IFTYPE_AP);
855 else 926 else
856 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac); 927 ret = ath9k_hw_set_keycache_entry(ah, idx, &hk, mac);
857 928
858 if (!ret) 929 if (!ret)
859 return -EIO; 930 return -EIO;
860 931
861 set_bit(idx, sc->keymap); 932 set_bit(idx, common->keymap);
862 if (key->alg == ALG_TKIP) { 933 if (key->alg == ALG_TKIP) {
863 set_bit(idx + 64, sc->keymap); 934 set_bit(idx + 64, common->keymap);
864 if (sc->splitmic) { 935 if (common->splitmic) {
865 set_bit(idx + 32, sc->keymap); 936 set_bit(idx + 32, common->keymap);
866 set_bit(idx + 64 + 32, sc->keymap); 937 set_bit(idx + 64 + 32, common->keymap);
867 } 938 }
868 } 939 }
869 940
870 return idx; 941 return idx;
871} 942}
872 943
873static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key) 944static void ath_key_delete(struct ath_common *common, struct ieee80211_key_conf *key)
874{ 945{
875 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx); 946 struct ath_hw *ah = common->ah;
947
948 ath9k_hw_keyreset(ah, key->hw_key_idx);
876 if (key->hw_key_idx < IEEE80211_WEP_NKID) 949 if (key->hw_key_idx < IEEE80211_WEP_NKID)
877 return; 950 return;
878 951
879 clear_bit(key->hw_key_idx, sc->keymap); 952 clear_bit(key->hw_key_idx, common->keymap);
880 if (key->alg != ALG_TKIP) 953 if (key->alg != ALG_TKIP)
881 return; 954 return;
882 955
883 clear_bit(key->hw_key_idx + 64, sc->keymap); 956 clear_bit(key->hw_key_idx + 64, common->keymap);
884 if (sc->splitmic) { 957 if (common->splitmic) {
885 clear_bit(key->hw_key_idx + 32, sc->keymap); 958 clear_bit(key->hw_key_idx + 32, common->keymap);
886 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap); 959 clear_bit(key->hw_key_idx + 64 + 32, common->keymap);
887 } 960 }
888} 961}
889 962
890static void setup_ht_cap(struct ath_softc *sc, 963static void setup_ht_cap(struct ath_softc *sc,
891 struct ieee80211_sta_ht_cap *ht_info) 964 struct ieee80211_sta_ht_cap *ht_info)
892{ 965{
966 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
893 u8 tx_streams, rx_streams; 967 u8 tx_streams, rx_streams;
894 968
895 ht_info->ht_supported = true; 969 ht_info->ht_supported = true;
@@ -903,12 +977,15 @@ static void setup_ht_cap(struct ath_softc *sc,
903 977
904 /* set up supported mcs set */ 978 /* set up supported mcs set */
905 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs)); 979 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
906 tx_streams = !(sc->tx_chainmask & (sc->tx_chainmask - 1)) ? 1 : 2; 980 tx_streams = !(common->tx_chainmask & (common->tx_chainmask - 1)) ?
907 rx_streams = !(sc->rx_chainmask & (sc->rx_chainmask - 1)) ? 1 : 2; 981 1 : 2;
982 rx_streams = !(common->rx_chainmask & (common->rx_chainmask - 1)) ?
983 1 : 2;
908 984
909 if (tx_streams != rx_streams) { 985 if (tx_streams != rx_streams) {
910 DPRINTF(sc, ATH_DBG_CONFIG, "TX streams %d, RX streams: %d\n", 986 ath_print(common, ATH_DBG_CONFIG,
911 tx_streams, rx_streams); 987 "TX streams %d, RX streams: %d\n",
988 tx_streams, rx_streams);
912 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; 989 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
913 ht_info->mcs.tx_params |= ((tx_streams - 1) << 990 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
914 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); 991 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
@@ -925,14 +1002,17 @@ static void ath9k_bss_assoc_info(struct ath_softc *sc,
925 struct ieee80211_vif *vif, 1002 struct ieee80211_vif *vif,
926 struct ieee80211_bss_conf *bss_conf) 1003 struct ieee80211_bss_conf *bss_conf)
927{ 1004{
1005 struct ath_hw *ah = sc->sc_ah;
1006 struct ath_common *common = ath9k_hw_common(ah);
928 1007
929 if (bss_conf->assoc) { 1008 if (bss_conf->assoc) {
930 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n", 1009 ath_print(common, ATH_DBG_CONFIG,
931 bss_conf->aid, sc->curbssid); 1010 "Bss Info ASSOC %d, bssid: %pM\n",
1011 bss_conf->aid, common->curbssid);
932 1012
933 /* New association, store aid */ 1013 /* New association, store aid */
934 sc->curaid = bss_conf->aid; 1014 common->curaid = bss_conf->aid;
935 ath9k_hw_write_associd(sc); 1015 ath9k_hw_write_associd(ah);
936 1016
937 /* 1017 /*
938 * Request a re-configuration of Beacon related timers 1018 * Request a re-configuration of Beacon related timers
@@ -947,12 +1027,12 @@ static void ath9k_bss_assoc_info(struct ath_softc *sc,
947 /* Reset rssi stats */ 1027 /* Reset rssi stats */
948 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; 1028 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
949 1029
950 ath_start_ani(sc); 1030 ath_start_ani(common);
951 } else { 1031 } else {
952 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISASSOC\n"); 1032 ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
953 sc->curaid = 0; 1033 common->curaid = 0;
954 /* Stop ANI */ 1034 /* Stop ANI */
955 del_timer_sync(&sc->ani.timer); 1035 del_timer_sync(&common->ani.timer);
956 } 1036 }
957} 1037}
958 1038
@@ -1042,8 +1122,8 @@ static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1042 1122
1043 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev); 1123 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1044 if (ret) 1124 if (ret)
1045 DPRINTF(sc, ATH_DBG_FATAL, 1125 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1046 "Failed to register led:%s", led->name); 1126 "Failed to register led:%s", led->name);
1047 else 1127 else
1048 led->registered = 1; 1128 led->registered = 1;
1049 return ret; 1129 return ret;
@@ -1124,10 +1204,11 @@ fail:
1124 ath_deinit_leds(sc); 1204 ath_deinit_leds(sc);
1125} 1205}
1126 1206
1127void ath_radio_enable(struct ath_softc *sc) 1207void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
1128{ 1208{
1129 struct ath_hw *ah = sc->sc_ah; 1209 struct ath_hw *ah = sc->sc_ah;
1130 struct ieee80211_channel *channel = sc->hw->conf.channel; 1210 struct ath_common *common = ath9k_hw_common(ah);
1211 struct ieee80211_channel *channel = hw->conf.channel;
1131 int r; 1212 int r;
1132 1213
1133 ath9k_ps_wakeup(sc); 1214 ath9k_ps_wakeup(sc);
@@ -1139,17 +1220,17 @@ void ath_radio_enable(struct ath_softc *sc)
1139 spin_lock_bh(&sc->sc_resetlock); 1220 spin_lock_bh(&sc->sc_resetlock);
1140 r = ath9k_hw_reset(ah, ah->curchan, false); 1221 r = ath9k_hw_reset(ah, ah->curchan, false);
1141 if (r) { 1222 if (r) {
1142 DPRINTF(sc, ATH_DBG_FATAL, 1223 ath_print(common, ATH_DBG_FATAL,
1143 "Unable to reset channel %u (%uMhz) ", 1224 "Unable to reset channel %u (%uMhz) ",
1144 "reset status %d\n", 1225 "reset status %d\n",
1145 channel->center_freq, r); 1226 channel->center_freq, r);
1146 } 1227 }
1147 spin_unlock_bh(&sc->sc_resetlock); 1228 spin_unlock_bh(&sc->sc_resetlock);
1148 1229
1149 ath_update_txpow(sc); 1230 ath_update_txpow(sc);
1150 if (ath_startrecv(sc) != 0) { 1231 if (ath_startrecv(sc) != 0) {
1151 DPRINTF(sc, ATH_DBG_FATAL, 1232 ath_print(common, ATH_DBG_FATAL,
1152 "Unable to restart recv logic\n"); 1233 "Unable to restart recv logic\n");
1153 return; 1234 return;
1154 } 1235 }
1155 1236
@@ -1164,18 +1245,18 @@ void ath_radio_enable(struct ath_softc *sc)
1164 AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1245 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1165 ath9k_hw_set_gpio(ah, ah->led_pin, 0); 1246 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
1166 1247
1167 ieee80211_wake_queues(sc->hw); 1248 ieee80211_wake_queues(hw);
1168 ath9k_ps_restore(sc); 1249 ath9k_ps_restore(sc);
1169} 1250}
1170 1251
1171void ath_radio_disable(struct ath_softc *sc) 1252void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
1172{ 1253{
1173 struct ath_hw *ah = sc->sc_ah; 1254 struct ath_hw *ah = sc->sc_ah;
1174 struct ieee80211_channel *channel = sc->hw->conf.channel; 1255 struct ieee80211_channel *channel = hw->conf.channel;
1175 int r; 1256 int r;
1176 1257
1177 ath9k_ps_wakeup(sc); 1258 ath9k_ps_wakeup(sc);
1178 ieee80211_stop_queues(sc->hw); 1259 ieee80211_stop_queues(hw);
1179 1260
1180 /* Disable LED */ 1261 /* Disable LED */
1181 ath9k_hw_set_gpio(ah, ah->led_pin, 1); 1262 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
@@ -1189,22 +1270,22 @@ void ath_radio_disable(struct ath_softc *sc)
1189 ath_flushrecv(sc); /* flush recv queue */ 1270 ath_flushrecv(sc); /* flush recv queue */
1190 1271
1191 if (!ah->curchan) 1272 if (!ah->curchan)
1192 ah->curchan = ath_get_curchannel(sc, sc->hw); 1273 ah->curchan = ath_get_curchannel(sc, hw);
1193 1274
1194 spin_lock_bh(&sc->sc_resetlock); 1275 spin_lock_bh(&sc->sc_resetlock);
1195 r = ath9k_hw_reset(ah, ah->curchan, false); 1276 r = ath9k_hw_reset(ah, ah->curchan, false);
1196 if (r) { 1277 if (r) {
1197 DPRINTF(sc, ATH_DBG_FATAL, 1278 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1198 "Unable to reset channel %u (%uMhz) " 1279 "Unable to reset channel %u (%uMhz) "
1199 "reset status %d\n", 1280 "reset status %d\n",
1200 channel->center_freq, r); 1281 channel->center_freq, r);
1201 } 1282 }
1202 spin_unlock_bh(&sc->sc_resetlock); 1283 spin_unlock_bh(&sc->sc_resetlock);
1203 1284
1204 ath9k_hw_phy_disable(ah); 1285 ath9k_hw_phy_disable(ah);
1205 ath9k_hw_configpcipowersave(ah, 1, 1); 1286 ath9k_hw_configpcipowersave(ah, 1, 1);
1206 ath9k_ps_restore(sc); 1287 ath9k_ps_restore(sc);
1207 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 1288 ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
1208} 1289}
1209 1290
1210/*******************/ 1291/*******************/
@@ -1236,23 +1317,26 @@ static void ath_start_rfkill_poll(struct ath_softc *sc)
1236 wiphy_rfkill_start_polling(sc->hw->wiphy); 1317 wiphy_rfkill_start_polling(sc->hw->wiphy);
1237} 1318}
1238 1319
1239void ath_cleanup(struct ath_softc *sc) 1320static void ath9k_uninit_hw(struct ath_softc *sc)
1240{ 1321{
1241 ath_detach(sc); 1322 struct ath_hw *ah = sc->sc_ah;
1242 free_irq(sc->irq, sc); 1323
1243 ath_bus_cleanup(sc); 1324 BUG_ON(!ah);
1244 kfree(sc->sec_wiphy); 1325
1245 ieee80211_free_hw(sc->hw); 1326 ath9k_exit_debug(ah);
1327 ath9k_hw_detach(ah);
1328 sc->sc_ah = NULL;
1246} 1329}
1247 1330
1248void ath_detach(struct ath_softc *sc) 1331static void ath_clean_core(struct ath_softc *sc)
1249{ 1332{
1250 struct ieee80211_hw *hw = sc->hw; 1333 struct ieee80211_hw *hw = sc->hw;
1334 struct ath_hw *ah = sc->sc_ah;
1251 int i = 0; 1335 int i = 0;
1252 1336
1253 ath9k_ps_wakeup(sc); 1337 ath9k_ps_wakeup(sc);
1254 1338
1255 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n"); 1339 dev_dbg(sc->dev, "Detach ATH hw\n");
1256 1340
1257 ath_deinit_leds(sc); 1341 ath_deinit_leds(sc);
1258 wiphy_rfkill_stop_polling(sc->hw->wiphy); 1342 wiphy_rfkill_stop_polling(sc->hw->wiphy);
@@ -1273,20 +1357,36 @@ void ath_detach(struct ath_softc *sc)
1273 tasklet_kill(&sc->bcon_tasklet); 1357 tasklet_kill(&sc->bcon_tasklet);
1274 1358
1275 if (!(sc->sc_flags & SC_OP_INVALID)) 1359 if (!(sc->sc_flags & SC_OP_INVALID))
1276 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); 1360 ath9k_setpower(sc, ATH9K_PM_AWAKE);
1277 1361
1278 /* cleanup tx queues */ 1362 /* cleanup tx queues */
1279 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 1363 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1280 if (ATH_TXQ_SETUP(sc, i)) 1364 if (ATH_TXQ_SETUP(sc, i))
1281 ath_tx_cleanupq(sc, &sc->tx.txq[i]); 1365 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1282 1366
1283 if ((sc->btcoex_info.no_stomp_timer) && 1367 if ((sc->btcoex.no_stomp_timer) &&
1284 sc->btcoex_info.btcoex_scheme == ATH_BTCOEX_CFG_3WIRE) 1368 ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
1285 ath_gen_timer_free(sc->sc_ah, sc->btcoex_info.no_stomp_timer); 1369 ath_gen_timer_free(ah, sc->btcoex.no_stomp_timer);
1370}
1286 1371
1287 ath9k_hw_detach(sc->sc_ah); 1372void ath_detach(struct ath_softc *sc)
1288 sc->sc_ah = NULL; 1373{
1289 ath9k_exit_debug(sc); 1374 ath_clean_core(sc);
1375 ath9k_uninit_hw(sc);
1376}
1377
1378void ath_cleanup(struct ath_softc *sc)
1379{
1380 struct ath_hw *ah = sc->sc_ah;
1381 struct ath_common *common = ath9k_hw_common(ah);
1382
1383 ath_clean_core(sc);
1384 free_irq(sc->irq, sc);
1385 ath_bus_cleanup(common);
1386 kfree(sc->sec_wiphy);
1387 ieee80211_free_hw(sc->hw);
1388
1389 ath9k_uninit_hw(sc);
1290} 1390}
1291 1391
1292static int ath9k_reg_notifier(struct wiphy *wiphy, 1392static int ath9k_reg_notifier(struct wiphy *wiphy,
@@ -1295,29 +1395,245 @@ static int ath9k_reg_notifier(struct wiphy *wiphy,
1295 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 1395 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1296 struct ath_wiphy *aphy = hw->priv; 1396 struct ath_wiphy *aphy = hw->priv;
1297 struct ath_softc *sc = aphy->sc; 1397 struct ath_softc *sc = aphy->sc;
1298 struct ath_regulatory *reg = &sc->common.regulatory; 1398 struct ath_regulatory *reg = ath9k_hw_regulatory(sc->sc_ah);
1299 1399
1300 return ath_reg_notifier_apply(wiphy, request, reg); 1400 return ath_reg_notifier_apply(wiphy, request, reg);
1301} 1401}
1302 1402
1303/* 1403/*
1404 * Detects if there is any priority bt traffic
1405 */
1406static void ath_detect_bt_priority(struct ath_softc *sc)
1407{
1408 struct ath_btcoex *btcoex = &sc->btcoex;
1409 struct ath_hw *ah = sc->sc_ah;
1410
1411 if (ath9k_hw_gpio_get(sc->sc_ah, ah->btcoex_hw.btpriority_gpio))
1412 btcoex->bt_priority_cnt++;
1413
1414 if (time_after(jiffies, btcoex->bt_priority_time +
1415 msecs_to_jiffies(ATH_BT_PRIORITY_TIME_THRESHOLD))) {
1416 if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) {
1417 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_BTCOEX,
1418 "BT priority traffic detected");
1419 sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED;
1420 } else {
1421 sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
1422 }
1423
1424 btcoex->bt_priority_cnt = 0;
1425 btcoex->bt_priority_time = jiffies;
1426 }
1427}
1428
1429/*
1430 * Configures appropriate weight based on stomp type.
1431 */
1432static void ath9k_btcoex_bt_stomp(struct ath_softc *sc,
1433 enum ath_stomp_type stomp_type)
1434{
1435 struct ath_hw *ah = sc->sc_ah;
1436
1437 switch (stomp_type) {
1438 case ATH_BTCOEX_STOMP_ALL:
1439 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1440 AR_STOMP_ALL_WLAN_WGHT);
1441 break;
1442 case ATH_BTCOEX_STOMP_LOW:
1443 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1444 AR_STOMP_LOW_WLAN_WGHT);
1445 break;
1446 case ATH_BTCOEX_STOMP_NONE:
1447 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1448 AR_STOMP_NONE_WLAN_WGHT);
1449 break;
1450 default:
1451 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
1452 "Invalid Stomptype\n");
1453 break;
1454 }
1455
1456 ath9k_hw_btcoex_enable(ah);
1457}
1458
1459static void ath9k_gen_timer_start(struct ath_hw *ah,
1460 struct ath_gen_timer *timer,
1461 u32 timer_next,
1462 u32 timer_period)
1463{
1464 struct ath_common *common = ath9k_hw_common(ah);
1465 struct ath_softc *sc = (struct ath_softc *) common->priv;
1466
1467 ath9k_hw_gen_timer_start(ah, timer, timer_next, timer_period);
1468
1469 if ((sc->imask & ATH9K_INT_GENTIMER) == 0) {
1470 ath9k_hw_set_interrupts(ah, 0);
1471 sc->imask |= ATH9K_INT_GENTIMER;
1472 ath9k_hw_set_interrupts(ah, sc->imask);
1473 }
1474}
1475
1476static void ath9k_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
1477{
1478 struct ath_common *common = ath9k_hw_common(ah);
1479 struct ath_softc *sc = (struct ath_softc *) common->priv;
1480 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
1481
1482 ath9k_hw_gen_timer_stop(ah, timer);
1483
1484 /* if no timer is enabled, turn off interrupt mask */
1485 if (timer_table->timer_mask.val == 0) {
1486 ath9k_hw_set_interrupts(ah, 0);
1487 sc->imask &= ~ATH9K_INT_GENTIMER;
1488 ath9k_hw_set_interrupts(ah, sc->imask);
1489 }
1490}
1491
1492/*
1493 * This is the master bt coex timer which runs for every
1494 * 45ms, bt traffic will be given priority during 55% of this
1495 * period while wlan gets remaining 45%
1496 */
1497static void ath_btcoex_period_timer(unsigned long data)
1498{
1499 struct ath_softc *sc = (struct ath_softc *) data;
1500 struct ath_hw *ah = sc->sc_ah;
1501 struct ath_btcoex *btcoex = &sc->btcoex;
1502
1503 ath_detect_bt_priority(sc);
1504
1505 spin_lock_bh(&btcoex->btcoex_lock);
1506
1507 ath9k_btcoex_bt_stomp(sc, btcoex->bt_stomp_type);
1508
1509 spin_unlock_bh(&btcoex->btcoex_lock);
1510
1511 if (btcoex->btcoex_period != btcoex->btcoex_no_stomp) {
1512 if (btcoex->hw_timer_enabled)
1513 ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer);
1514
1515 ath9k_gen_timer_start(ah,
1516 btcoex->no_stomp_timer,
1517 (ath9k_hw_gettsf32(ah) +
1518 btcoex->btcoex_no_stomp),
1519 btcoex->btcoex_no_stomp * 10);
1520 btcoex->hw_timer_enabled = true;
1521 }
1522
1523 mod_timer(&btcoex->period_timer, jiffies +
1524 msecs_to_jiffies(ATH_BTCOEX_DEF_BT_PERIOD));
1525}
1526
1527/*
1528 * Generic tsf based hw timer which configures weight
1529 * registers to time slice between wlan and bt traffic
1530 */
1531static void ath_btcoex_no_stomp_timer(void *arg)
1532{
1533 struct ath_softc *sc = (struct ath_softc *)arg;
1534 struct ath_hw *ah = sc->sc_ah;
1535 struct ath_btcoex *btcoex = &sc->btcoex;
1536
1537 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
1538 "no stomp timer running \n");
1539
1540 spin_lock_bh(&btcoex->btcoex_lock);
1541
1542 if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_LOW)
1543 ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_NONE);
1544 else if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_ALL)
1545 ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_LOW);
1546
1547 spin_unlock_bh(&btcoex->btcoex_lock);
1548}
1549
1550static int ath_init_btcoex_timer(struct ath_softc *sc)
1551{
1552 struct ath_btcoex *btcoex = &sc->btcoex;
1553
1554 btcoex->btcoex_period = ATH_BTCOEX_DEF_BT_PERIOD * 1000;
1555 btcoex->btcoex_no_stomp = (100 - ATH_BTCOEX_DEF_DUTY_CYCLE) *
1556 btcoex->btcoex_period / 100;
1557
1558 setup_timer(&btcoex->period_timer, ath_btcoex_period_timer,
1559 (unsigned long) sc);
1560
1561 spin_lock_init(&btcoex->btcoex_lock);
1562
1563 btcoex->no_stomp_timer = ath_gen_timer_alloc(sc->sc_ah,
1564 ath_btcoex_no_stomp_timer,
1565 ath_btcoex_no_stomp_timer,
1566 (void *) sc, AR_FIRST_NDP_TIMER);
1567
1568 if (!btcoex->no_stomp_timer)
1569 return -ENOMEM;
1570
1571 return 0;
1572}
1573
1574/*
1575 * Read and write, they both share the same lock. We do this to serialize
1576 * reads and writes on Atheros 802.11n PCI devices only. This is required
1577 * as the FIFO on these devices can only accept sanely 2 requests. After
1578 * that the device goes bananas. Serializing the reads/writes prevents this
1579 * from happening.
1580 */
1581
1582static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
1583{
1584 struct ath_hw *ah = (struct ath_hw *) hw_priv;
1585 struct ath_common *common = ath9k_hw_common(ah);
1586 struct ath_softc *sc = (struct ath_softc *) common->priv;
1587
1588 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
1589 unsigned long flags;
1590 spin_lock_irqsave(&sc->sc_serial_rw, flags);
1591 iowrite32(val, sc->mem + reg_offset);
1592 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
1593 } else
1594 iowrite32(val, sc->mem + reg_offset);
1595}
1596
1597static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
1598{
1599 struct ath_hw *ah = (struct ath_hw *) hw_priv;
1600 struct ath_common *common = ath9k_hw_common(ah);
1601 struct ath_softc *sc = (struct ath_softc *) common->priv;
1602 u32 val;
1603
1604 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
1605 unsigned long flags;
1606 spin_lock_irqsave(&sc->sc_serial_rw, flags);
1607 val = ioread32(sc->mem + reg_offset);
1608 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
1609 } else
1610 val = ioread32(sc->mem + reg_offset);
1611 return val;
1612}
1613
1614static const struct ath_ops ath9k_common_ops = {
1615 .read = ath9k_ioread32,
1616 .write = ath9k_iowrite32,
1617};
1618
1619/*
1304 * Initialize and fill ath_softc, ath_sofct is the 1620 * Initialize and fill ath_softc, ath_sofct is the
1305 * "Software Carrier" struct. Historically it has existed 1621 * "Software Carrier" struct. Historically it has existed
1306 * to allow the separation between hardware specific 1622 * to allow the separation between hardware specific
1307 * variables (now in ath_hw) and driver specific variables. 1623 * variables (now in ath_hw) and driver specific variables.
1308 */ 1624 */
1309static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid) 1625static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
1626 const struct ath_bus_ops *bus_ops)
1310{ 1627{
1311 struct ath_hw *ah = NULL; 1628 struct ath_hw *ah = NULL;
1629 struct ath_common *common;
1312 int r = 0, i; 1630 int r = 0, i;
1313 int csz = 0; 1631 int csz = 0;
1632 int qnum;
1314 1633
1315 /* XXX: hardware will not be ready until ath_open() being called */ 1634 /* XXX: hardware will not be ready until ath_open() being called */
1316 sc->sc_flags |= SC_OP_INVALID; 1635 sc->sc_flags |= SC_OP_INVALID;
1317 1636
1318 if (ath9k_init_debug(sc) < 0)
1319 printk(KERN_ERR "Unable to create debugfs files\n");
1320
1321 spin_lock_init(&sc->wiphy_lock); 1637 spin_lock_init(&sc->wiphy_lock);
1322 spin_lock_init(&sc->sc_resetlock); 1638 spin_lock_init(&sc->sc_resetlock);
1323 spin_lock_init(&sc->sc_serial_rw); 1639 spin_lock_init(&sc->sc_serial_rw);
@@ -1328,47 +1644,58 @@ static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid)
1328 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet, 1644 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
1329 (unsigned long)sc); 1645 (unsigned long)sc);
1330 1646
1331 /*
1332 * Cache line size is used to size and align various
1333 * structures used to communicate with the hardware.
1334 */
1335 ath_read_cachesize(sc, &csz);
1336 /* XXX assert csz is non-zero */
1337 sc->common.cachelsz = csz << 2; /* convert to bytes */
1338
1339 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL); 1647 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
1340 if (!ah) { 1648 if (!ah)
1341 r = -ENOMEM; 1649 return -ENOMEM;
1342 goto bad_no_ah;
1343 }
1344 1650
1345 ah->ah_sc = sc;
1346 ah->hw_version.devid = devid; 1651 ah->hw_version.devid = devid;
1347 ah->hw_version.subsysid = subsysid; 1652 ah->hw_version.subsysid = subsysid;
1348 sc->sc_ah = ah; 1653 sc->sc_ah = ah;
1349 1654
1655 common = ath9k_hw_common(ah);
1656 common->ops = &ath9k_common_ops;
1657 common->bus_ops = bus_ops;
1658 common->ah = ah;
1659 common->hw = sc->hw;
1660 common->priv = sc;
1661 common->debug_mask = ath9k_debug;
1662
1663 /*
1664 * Cache line size is used to size and align various
1665 * structures used to communicate with the hardware.
1666 */
1667 ath_read_cachesize(common, &csz);
1668 /* XXX assert csz is non-zero */
1669 common->cachelsz = csz << 2; /* convert to bytes */
1670
1350 r = ath9k_hw_init(ah); 1671 r = ath9k_hw_init(ah);
1351 if (r) { 1672 if (r) {
1352 DPRINTF(sc, ATH_DBG_FATAL, 1673 ath_print(common, ATH_DBG_FATAL,
1353 "Unable to initialize hardware; " 1674 "Unable to initialize hardware; "
1354 "initialization status: %d\n", r); 1675 "initialization status: %d\n", r);
1355 goto bad; 1676 goto bad_free_hw;
1677 }
1678
1679 if (ath9k_init_debug(ah) < 0) {
1680 ath_print(common, ATH_DBG_FATAL,
1681 "Unable to create debugfs files\n");
1682 goto bad_free_hw;
1356 } 1683 }
1357 1684
1358 /* Get the hardware key cache size. */ 1685 /* Get the hardware key cache size. */
1359 sc->keymax = ah->caps.keycache_size; 1686 common->keymax = ah->caps.keycache_size;
1360 if (sc->keymax > ATH_KEYMAX) { 1687 if (common->keymax > ATH_KEYMAX) {
1361 DPRINTF(sc, ATH_DBG_ANY, 1688 ath_print(common, ATH_DBG_ANY,
1362 "Warning, using only %u entries in %u key cache\n", 1689 "Warning, using only %u entries in %u key cache\n",
1363 ATH_KEYMAX, sc->keymax); 1690 ATH_KEYMAX, common->keymax);
1364 sc->keymax = ATH_KEYMAX; 1691 common->keymax = ATH_KEYMAX;
1365 } 1692 }
1366 1693
1367 /* 1694 /*
1368 * Reset the key cache since some parts do not 1695 * Reset the key cache since some parts do not
1369 * reset the contents on initial power up. 1696 * reset the contents on initial power up.
1370 */ 1697 */
1371 for (i = 0; i < sc->keymax; i++) 1698 for (i = 0; i < common->keymax; i++)
1372 ath9k_hw_keyreset(ah, (u16) i); 1699 ath9k_hw_keyreset(ah, (u16) i);
1373 1700
1374 /* default to MONITOR mode */ 1701 /* default to MONITOR mode */
@@ -1386,17 +1713,17 @@ static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid)
1386 * priority. Note that the hal handles reseting 1713 * priority. Note that the hal handles reseting
1387 * these queues at the needed time. 1714 * these queues at the needed time.
1388 */ 1715 */
1389 sc->beacon.beaconq = ath_beaconq_setup(ah); 1716 sc->beacon.beaconq = ath9k_hw_beaconq_setup(ah);
1390 if (sc->beacon.beaconq == -1) { 1717 if (sc->beacon.beaconq == -1) {
1391 DPRINTF(sc, ATH_DBG_FATAL, 1718 ath_print(common, ATH_DBG_FATAL,
1392 "Unable to setup a beacon xmit queue\n"); 1719 "Unable to setup a beacon xmit queue\n");
1393 r = -EIO; 1720 r = -EIO;
1394 goto bad2; 1721 goto bad2;
1395 } 1722 }
1396 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0); 1723 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1397 if (sc->beacon.cabq == NULL) { 1724 if (sc->beacon.cabq == NULL) {
1398 DPRINTF(sc, ATH_DBG_FATAL, 1725 ath_print(common, ATH_DBG_FATAL,
1399 "Unable to setup CAB xmit queue\n"); 1726 "Unable to setup CAB xmit queue\n");
1400 r = -EIO; 1727 r = -EIO;
1401 goto bad2; 1728 goto bad2;
1402 } 1729 }
@@ -1410,27 +1737,27 @@ static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid)
1410 /* Setup data queues */ 1737 /* Setup data queues */
1411 /* NB: ensure BK queue is the lowest priority h/w queue */ 1738 /* NB: ensure BK queue is the lowest priority h/w queue */
1412 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) { 1739 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1413 DPRINTF(sc, ATH_DBG_FATAL, 1740 ath_print(common, ATH_DBG_FATAL,
1414 "Unable to setup xmit queue for BK traffic\n"); 1741 "Unable to setup xmit queue for BK traffic\n");
1415 r = -EIO; 1742 r = -EIO;
1416 goto bad2; 1743 goto bad2;
1417 } 1744 }
1418 1745
1419 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) { 1746 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1420 DPRINTF(sc, ATH_DBG_FATAL, 1747 ath_print(common, ATH_DBG_FATAL,
1421 "Unable to setup xmit queue for BE traffic\n"); 1748 "Unable to setup xmit queue for BE traffic\n");
1422 r = -EIO; 1749 r = -EIO;
1423 goto bad2; 1750 goto bad2;
1424 } 1751 }
1425 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) { 1752 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1426 DPRINTF(sc, ATH_DBG_FATAL, 1753 ath_print(common, ATH_DBG_FATAL,
1427 "Unable to setup xmit queue for VI traffic\n"); 1754 "Unable to setup xmit queue for VI traffic\n");
1428 r = -EIO; 1755 r = -EIO;
1429 goto bad2; 1756 goto bad2;
1430 } 1757 }
1431 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) { 1758 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1432 DPRINTF(sc, ATH_DBG_FATAL, 1759 ath_print(common, ATH_DBG_FATAL,
1433 "Unable to setup xmit queue for VO traffic\n"); 1760 "Unable to setup xmit queue for VO traffic\n");
1434 r = -EIO; 1761 r = -EIO;
1435 goto bad2; 1762 goto bad2;
1436 } 1763 }
@@ -1438,8 +1765,8 @@ static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid)
1438 /* Initializes the noise floor to a reasonable default value. 1765 /* Initializes the noise floor to a reasonable default value.
1439 * Later on this will be updated during ANI processing. */ 1766 * Later on this will be updated during ANI processing. */
1440 1767
1441 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR; 1768 common->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1442 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc); 1769 setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc);
1443 1770
1444 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER, 1771 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1445 ATH9K_CIPHER_TKIP, NULL)) { 1772 ATH9K_CIPHER_TKIP, NULL)) {
@@ -1465,7 +1792,7 @@ static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid)
1465 ATH9K_CIPHER_MIC, NULL) 1792 ATH9K_CIPHER_MIC, NULL)
1466 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT, 1793 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1467 0, NULL)) 1794 0, NULL))
1468 sc->splitmic = 1; 1795 common->splitmic = 1;
1469 1796
1470 /* turn on mcast key search if possible */ 1797 /* turn on mcast key search if possible */
1471 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL)) 1798 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
@@ -1480,14 +1807,14 @@ static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid)
1480 sc->sc_flags |= SC_OP_RXAGGR; 1807 sc->sc_flags |= SC_OP_RXAGGR;
1481 } 1808 }
1482 1809
1483 sc->tx_chainmask = ah->caps.tx_chainmask; 1810 common->tx_chainmask = ah->caps.tx_chainmask;
1484 sc->rx_chainmask = ah->caps.rx_chainmask; 1811 common->rx_chainmask = ah->caps.rx_chainmask;
1485 1812
1486 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL); 1813 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1487 sc->rx.defant = ath9k_hw_getdefantenna(ah); 1814 sc->rx.defant = ath9k_hw_getdefantenna(ah);
1488 1815
1489 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) 1816 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1490 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN); 1817 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
1491 1818
1492 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */ 1819 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
1493 1820
@@ -1515,10 +1842,24 @@ static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid)
1515 ARRAY_SIZE(ath9k_5ghz_chantable); 1842 ARRAY_SIZE(ath9k_5ghz_chantable);
1516 } 1843 }
1517 1844
1518 if (sc->btcoex_info.btcoex_scheme != ATH_BTCOEX_CFG_NONE) { 1845 switch (ah->btcoex_hw.scheme) {
1519 r = ath9k_hw_btcoex_init(ah); 1846 case ATH_BTCOEX_CFG_NONE:
1847 break;
1848 case ATH_BTCOEX_CFG_2WIRE:
1849 ath9k_hw_btcoex_init_2wire(ah);
1850 break;
1851 case ATH_BTCOEX_CFG_3WIRE:
1852 ath9k_hw_btcoex_init_3wire(ah);
1853 r = ath_init_btcoex_timer(sc);
1520 if (r) 1854 if (r)
1521 goto bad2; 1855 goto bad2;
1856 qnum = ath_tx_get_qnum(sc, ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
1857 ath9k_hw_init_btcoex_hw(ah, qnum);
1858 sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
1859 break;
1860 default:
1861 WARN_ON(1);
1862 break;
1522 } 1863 }
1523 1864
1524 return 0; 1865 return 0;
@@ -1527,12 +1868,9 @@ bad2:
1527 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 1868 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1528 if (ATH_TXQ_SETUP(sc, i)) 1869 if (ATH_TXQ_SETUP(sc, i))
1529 ath_tx_cleanupq(sc, &sc->tx.txq[i]); 1870 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1530bad:
1531 ath9k_hw_detach(ah);
1532 sc->sc_ah = NULL;
1533bad_no_ah:
1534 ath9k_exit_debug(sc);
1535 1871
1872bad_free_hw:
1873 ath9k_uninit_hw(sc);
1536 return r; 1874 return r;
1537} 1875}
1538 1876
@@ -1555,7 +1893,7 @@ void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
1555 BIT(NL80211_IFTYPE_ADHOC) | 1893 BIT(NL80211_IFTYPE_ADHOC) |
1556 BIT(NL80211_IFTYPE_MESH_POINT); 1894 BIT(NL80211_IFTYPE_MESH_POINT);
1557 1895
1558 hw->wiphy->ps_default = false; 1896 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
1559 1897
1560 hw->queues = 4; 1898 hw->queues = 4;
1561 hw->max_rates = 4; 1899 hw->max_rates = 4;
@@ -1576,34 +1914,40 @@ void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
1576} 1914}
1577 1915
1578/* Device driver core initialization */ 1916/* Device driver core initialization */
1579int ath_init_device(u16 devid, struct ath_softc *sc, u16 subsysid) 1917int ath_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
1918 const struct ath_bus_ops *bus_ops)
1580{ 1919{
1581 struct ieee80211_hw *hw = sc->hw; 1920 struct ieee80211_hw *hw = sc->hw;
1921 struct ath_common *common;
1922 struct ath_hw *ah;
1582 int error = 0, i; 1923 int error = 0, i;
1583 struct ath_regulatory *reg; 1924 struct ath_regulatory *reg;
1584 1925
1585 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n"); 1926 dev_dbg(sc->dev, "Attach ATH hw\n");
1586 1927
1587 error = ath_init_softc(devid, sc, subsysid); 1928 error = ath_init_softc(devid, sc, subsysid, bus_ops);
1588 if (error != 0) 1929 if (error != 0)
1589 return error; 1930 return error;
1590 1931
1932 ah = sc->sc_ah;
1933 common = ath9k_hw_common(ah);
1934
1591 /* get mac address from hardware and set in mac80211 */ 1935 /* get mac address from hardware and set in mac80211 */
1592 1936
1593 SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr); 1937 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
1594 1938
1595 ath_set_hw_capab(sc, hw); 1939 ath_set_hw_capab(sc, hw);
1596 1940
1597 error = ath_regd_init(&sc->common.regulatory, sc->hw->wiphy, 1941 error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
1598 ath9k_reg_notifier); 1942 ath9k_reg_notifier);
1599 if (error) 1943 if (error)
1600 return error; 1944 return error;
1601 1945
1602 reg = &sc->common.regulatory; 1946 reg = &common->regulatory;
1603 1947
1604 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) { 1948 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1605 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap); 1949 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1606 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) 1950 if (test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes))
1607 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap); 1951 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1608 } 1952 }
1609 1953
@@ -1641,9 +1985,7 @@ error_attach:
1641 if (ATH_TXQ_SETUP(sc, i)) 1985 if (ATH_TXQ_SETUP(sc, i))
1642 ath_tx_cleanupq(sc, &sc->tx.txq[i]); 1986 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1643 1987
1644 ath9k_hw_detach(sc->sc_ah); 1988 ath9k_uninit_hw(sc);
1645 sc->sc_ah = NULL;
1646 ath9k_exit_debug(sc);
1647 1989
1648 return error; 1990 return error;
1649} 1991}
@@ -1651,6 +1993,7 @@ error_attach:
1651int ath_reset(struct ath_softc *sc, bool retry_tx) 1993int ath_reset(struct ath_softc *sc, bool retry_tx)
1652{ 1994{
1653 struct ath_hw *ah = sc->sc_ah; 1995 struct ath_hw *ah = sc->sc_ah;
1996 struct ath_common *common = ath9k_hw_common(ah);
1654 struct ieee80211_hw *hw = sc->hw; 1997 struct ieee80211_hw *hw = sc->hw;
1655 int r; 1998 int r;
1656 1999
@@ -1662,12 +2005,13 @@ int ath_reset(struct ath_softc *sc, bool retry_tx)
1662 spin_lock_bh(&sc->sc_resetlock); 2005 spin_lock_bh(&sc->sc_resetlock);
1663 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false); 2006 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1664 if (r) 2007 if (r)
1665 DPRINTF(sc, ATH_DBG_FATAL, 2008 ath_print(common, ATH_DBG_FATAL,
1666 "Unable to reset hardware; reset status %d\n", r); 2009 "Unable to reset hardware; reset status %d\n", r);
1667 spin_unlock_bh(&sc->sc_resetlock); 2010 spin_unlock_bh(&sc->sc_resetlock);
1668 2011
1669 if (ath_startrecv(sc) != 0) 2012 if (ath_startrecv(sc) != 0)
1670 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n"); 2013 ath_print(common, ATH_DBG_FATAL,
2014 "Unable to start recv logic\n");
1671 2015
1672 /* 2016 /*
1673 * We may be doing a reset in response to a request 2017 * We may be doing a reset in response to a request
@@ -1710,19 +2054,20 @@ int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1710 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) 2054 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1711#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0) 2055#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1712#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096) 2056#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1713 2057 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1714 struct ath_desc *ds; 2058 struct ath_desc *ds;
1715 struct ath_buf *bf; 2059 struct ath_buf *bf;
1716 int i, bsize, error; 2060 int i, bsize, error;
1717 2061
1718 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n", 2062 ath_print(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1719 name, nbuf, ndesc); 2063 name, nbuf, ndesc);
1720 2064
1721 INIT_LIST_HEAD(head); 2065 INIT_LIST_HEAD(head);
1722 /* ath_desc must be a multiple of DWORDs */ 2066 /* ath_desc must be a multiple of DWORDs */
1723 if ((sizeof(struct ath_desc) % 4) != 0) { 2067 if ((sizeof(struct ath_desc) % 4) != 0) {
1724 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n"); 2068 ath_print(common, ATH_DBG_FATAL,
1725 ASSERT((sizeof(struct ath_desc) % 4) == 0); 2069 "ath_desc not DWORD aligned\n");
2070 BUG_ON((sizeof(struct ath_desc) % 4) != 0);
1726 error = -ENOMEM; 2071 error = -ENOMEM;
1727 goto fail; 2072 goto fail;
1728 } 2073 }
@@ -1755,9 +2100,9 @@ int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1755 goto fail; 2100 goto fail;
1756 } 2101 }
1757 ds = dd->dd_desc; 2102 ds = dd->dd_desc;
1758 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n", 2103 ath_print(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1759 name, ds, (u32) dd->dd_desc_len, 2104 name, ds, (u32) dd->dd_desc_len,
1760 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len); 2105 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1761 2106
1762 /* allocate buffers */ 2107 /* allocate buffers */
1763 bsize = sizeof(struct ath_buf) * nbuf; 2108 bsize = sizeof(struct ath_buf) * nbuf;
@@ -1780,7 +2125,7 @@ int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1780 * descriptor fetch. 2125 * descriptor fetch.
1781 */ 2126 */
1782 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) { 2127 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1783 ASSERT((caddr_t) bf->bf_desc < 2128 BUG_ON((caddr_t) bf->bf_desc >=
1784 ((caddr_t) dd->dd_desc + 2129 ((caddr_t) dd->dd_desc +
1785 dd->dd_desc_len)); 2130 dd->dd_desc_len));
1786 2131
@@ -1884,31 +2229,50 @@ void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1884 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM; 2229 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1885 } 2230 }
1886 2231
1887 sc->tx_chan_width = ATH9K_HT_MACMODE_20; 2232 if (conf_is_ht(conf))
1888
1889 if (conf_is_ht(conf)) {
1890 if (conf_is_ht40(conf))
1891 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1892
1893 ichan->chanmode = ath_get_extchanmode(sc, chan, 2233 ichan->chanmode = ath_get_extchanmode(sc, chan,
1894 conf->channel_type); 2234 conf->channel_type);
1895 }
1896} 2235}
1897 2236
1898/**********************/ 2237/**********************/
1899/* mac80211 callbacks */ 2238/* mac80211 callbacks */
1900/**********************/ 2239/**********************/
1901 2240
2241/*
2242 * (Re)start btcoex timers
2243 */
2244static void ath9k_btcoex_timer_resume(struct ath_softc *sc)
2245{
2246 struct ath_btcoex *btcoex = &sc->btcoex;
2247 struct ath_hw *ah = sc->sc_ah;
2248
2249 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
2250 "Starting btcoex timers");
2251
2252 /* make sure duty cycle timer is also stopped when resuming */
2253 if (btcoex->hw_timer_enabled)
2254 ath9k_gen_timer_stop(sc->sc_ah, btcoex->no_stomp_timer);
2255
2256 btcoex->bt_priority_cnt = 0;
2257 btcoex->bt_priority_time = jiffies;
2258 sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
2259
2260 mod_timer(&btcoex->period_timer, jiffies);
2261}
2262
1902static int ath9k_start(struct ieee80211_hw *hw) 2263static int ath9k_start(struct ieee80211_hw *hw)
1903{ 2264{
1904 struct ath_wiphy *aphy = hw->priv; 2265 struct ath_wiphy *aphy = hw->priv;
1905 struct ath_softc *sc = aphy->sc; 2266 struct ath_softc *sc = aphy->sc;
2267 struct ath_hw *ah = sc->sc_ah;
2268 struct ath_common *common = ath9k_hw_common(ah);
1906 struct ieee80211_channel *curchan = hw->conf.channel; 2269 struct ieee80211_channel *curchan = hw->conf.channel;
1907 struct ath9k_channel *init_channel; 2270 struct ath9k_channel *init_channel;
1908 int r; 2271 int r;
1909 2272
1910 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with " 2273 ath_print(common, ATH_DBG_CONFIG,
1911 "initial channel: %d MHz\n", curchan->center_freq); 2274 "Starting driver with initial channel: %d MHz\n",
2275 curchan->center_freq);
1912 2276
1913 mutex_lock(&sc->mutex); 2277 mutex_lock(&sc->mutex);
1914 2278
@@ -1940,7 +2304,7 @@ static int ath9k_start(struct ieee80211_hw *hw)
1940 init_channel = ath_get_curchannel(sc, hw); 2304 init_channel = ath_get_curchannel(sc, hw);
1941 2305
1942 /* Reset SERDES registers */ 2306 /* Reset SERDES registers */
1943 ath9k_hw_configpcipowersave(sc->sc_ah, 0, 0); 2307 ath9k_hw_configpcipowersave(ah, 0, 0);
1944 2308
1945 /* 2309 /*
1946 * The basic interface to setting the hardware in a good 2310 * The basic interface to setting the hardware in a good
@@ -1950,12 +2314,12 @@ static int ath9k_start(struct ieee80211_hw *hw)
1950 * and then setup of the interrupt mask. 2314 * and then setup of the interrupt mask.
1951 */ 2315 */
1952 spin_lock_bh(&sc->sc_resetlock); 2316 spin_lock_bh(&sc->sc_resetlock);
1953 r = ath9k_hw_reset(sc->sc_ah, init_channel, false); 2317 r = ath9k_hw_reset(ah, init_channel, false);
1954 if (r) { 2318 if (r) {
1955 DPRINTF(sc, ATH_DBG_FATAL, 2319 ath_print(common, ATH_DBG_FATAL,
1956 "Unable to reset hardware; reset status %d " 2320 "Unable to reset hardware; reset status %d "
1957 "(freq %u MHz)\n", r, 2321 "(freq %u MHz)\n", r,
1958 curchan->center_freq); 2322 curchan->center_freq);
1959 spin_unlock_bh(&sc->sc_resetlock); 2323 spin_unlock_bh(&sc->sc_resetlock);
1960 goto mutex_unlock; 2324 goto mutex_unlock;
1961 } 2325 }
@@ -1975,7 +2339,8 @@ static int ath9k_start(struct ieee80211_hw *hw)
1975 * here except setup the interrupt mask. 2339 * here except setup the interrupt mask.
1976 */ 2340 */
1977 if (ath_startrecv(sc) != 0) { 2341 if (ath_startrecv(sc) != 0) {
1978 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n"); 2342 ath_print(common, ATH_DBG_FATAL,
2343 "Unable to start recv logic\n");
1979 r = -EIO; 2344 r = -EIO;
1980 goto mutex_unlock; 2345 goto mutex_unlock;
1981 } 2346 }
@@ -1985,10 +2350,10 @@ static int ath9k_start(struct ieee80211_hw *hw)
1985 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN 2350 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1986 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL; 2351 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1987 2352
1988 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT) 2353 if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
1989 sc->imask |= ATH9K_INT_GTT; 2354 sc->imask |= ATH9K_INT_GTT;
1990 2355
1991 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) 2356 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
1992 sc->imask |= ATH9K_INT_CST; 2357 sc->imask |= ATH9K_INT_CST;
1993 2358
1994 ath_cache_conf_rate(sc, &hw->conf); 2359 ath_cache_conf_rate(sc, &hw->conf);
@@ -1997,21 +2362,22 @@ static int ath9k_start(struct ieee80211_hw *hw)
1997 2362
1998 /* Disable BMISS interrupt when we're not associated */ 2363 /* Disable BMISS interrupt when we're not associated */
1999 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS); 2364 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2000 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask); 2365 ath9k_hw_set_interrupts(ah, sc->imask);
2001 2366
2002 ieee80211_wake_queues(hw); 2367 ieee80211_wake_queues(hw);
2003 2368
2004 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); 2369 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
2005 2370
2006 if ((sc->btcoex_info.btcoex_scheme != ATH_BTCOEX_CFG_NONE) && 2371 if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
2007 !(sc->sc_flags & SC_OP_BTCOEX_ENABLED)) { 2372 !ah->btcoex_hw.enabled) {
2008 ath_btcoex_set_weight(&sc->btcoex_info, AR_BT_COEX_WGHT, 2373 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
2009 AR_STOMP_LOW_WLAN_WGHT); 2374 AR_STOMP_LOW_WLAN_WGHT);
2010 ath9k_hw_btcoex_enable(sc->sc_ah); 2375 ath9k_hw_btcoex_enable(ah);
2011 2376
2012 ath_pcie_aspm_disable(sc); 2377 if (common->bus_ops->bt_coex_prep)
2013 if (sc->btcoex_info.btcoex_scheme == ATH_BTCOEX_CFG_3WIRE) 2378 common->bus_ops->bt_coex_prep(common);
2014 ath_btcoex_timer_resume(sc, &sc->btcoex_info); 2379 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
2380 ath9k_btcoex_timer_resume(sc);
2015 } 2381 }
2016 2382
2017mutex_unlock: 2383mutex_unlock:
@@ -2026,12 +2392,14 @@ static int ath9k_tx(struct ieee80211_hw *hw,
2026 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 2392 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2027 struct ath_wiphy *aphy = hw->priv; 2393 struct ath_wiphy *aphy = hw->priv;
2028 struct ath_softc *sc = aphy->sc; 2394 struct ath_softc *sc = aphy->sc;
2395 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2029 struct ath_tx_control txctl; 2396 struct ath_tx_control txctl;
2030 int hdrlen, padsize; 2397 int hdrlen, padsize;
2031 2398
2032 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) { 2399 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
2033 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state " 2400 ath_print(common, ATH_DBG_XMIT,
2034 "%d\n", wiphy_name(hw->wiphy), aphy->state); 2401 "ath9k: %s: TX in unexpected wiphy state "
2402 "%d\n", wiphy_name(hw->wiphy), aphy->state);
2035 goto exit; 2403 goto exit;
2036 } 2404 }
2037 2405
@@ -2044,8 +2412,8 @@ static int ath9k_tx(struct ieee80211_hw *hw,
2044 if (ieee80211_is_data(hdr->frame_control) && 2412 if (ieee80211_is_data(hdr->frame_control) &&
2045 !ieee80211_is_nullfunc(hdr->frame_control) && 2413 !ieee80211_is_nullfunc(hdr->frame_control) &&
2046 !ieee80211_has_pm(hdr->frame_control)) { 2414 !ieee80211_has_pm(hdr->frame_control)) {
2047 DPRINTF(sc, ATH_DBG_PS, "Add PM=1 for a TX frame " 2415 ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame "
2048 "while in PS mode\n"); 2416 "while in PS mode\n");
2049 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 2417 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2050 } 2418 }
2051 } 2419 }
@@ -2060,11 +2428,12 @@ static int ath9k_tx(struct ieee80211_hw *hw,
2060 ath9k_ps_wakeup(sc); 2428 ath9k_ps_wakeup(sc);
2061 ath9k_hw_setrxabort(sc->sc_ah, 0); 2429 ath9k_hw_setrxabort(sc->sc_ah, 0);
2062 if (ieee80211_is_pspoll(hdr->frame_control)) { 2430 if (ieee80211_is_pspoll(hdr->frame_control)) {
2063 DPRINTF(sc, ATH_DBG_PS, "Sending PS-Poll to pick a " 2431 ath_print(common, ATH_DBG_PS,
2064 "buffered frame\n"); 2432 "Sending PS-Poll to pick a buffered frame\n");
2065 sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA; 2433 sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2066 } else { 2434 } else {
2067 DPRINTF(sc, ATH_DBG_PS, "Wake up to complete TX\n"); 2435 ath_print(common, ATH_DBG_PS,
2436 "Wake up to complete TX\n");
2068 sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK; 2437 sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2069 } 2438 }
2070 /* 2439 /*
@@ -2106,10 +2475,10 @@ static int ath9k_tx(struct ieee80211_hw *hw,
2106 if (!txctl.txq) 2475 if (!txctl.txq)
2107 goto exit; 2476 goto exit;
2108 2477
2109 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb); 2478 ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2110 2479
2111 if (ath_tx_start(hw, skb, &txctl) != 0) { 2480 if (ath_tx_start(hw, skb, &txctl) != 0) {
2112 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n"); 2481 ath_print(common, ATH_DBG_XMIT, "TX failed\n");
2113 goto exit; 2482 goto exit;
2114 } 2483 }
2115 2484
@@ -2119,10 +2488,28 @@ exit:
2119 return 0; 2488 return 0;
2120} 2489}
2121 2490
2491/*
2492 * Pause btcoex timer and bt duty cycle timer
2493 */
2494static void ath9k_btcoex_timer_pause(struct ath_softc *sc)
2495{
2496 struct ath_btcoex *btcoex = &sc->btcoex;
2497 struct ath_hw *ah = sc->sc_ah;
2498
2499 del_timer_sync(&btcoex->period_timer);
2500
2501 if (btcoex->hw_timer_enabled)
2502 ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer);
2503
2504 btcoex->hw_timer_enabled = false;
2505}
2506
2122static void ath9k_stop(struct ieee80211_hw *hw) 2507static void ath9k_stop(struct ieee80211_hw *hw)
2123{ 2508{
2124 struct ath_wiphy *aphy = hw->priv; 2509 struct ath_wiphy *aphy = hw->priv;
2125 struct ath_softc *sc = aphy->sc; 2510 struct ath_softc *sc = aphy->sc;
2511 struct ath_hw *ah = sc->sc_ah;
2512 struct ath_common *common = ath9k_hw_common(ah);
2126 2513
2127 mutex_lock(&sc->mutex); 2514 mutex_lock(&sc->mutex);
2128 2515
@@ -2137,7 +2524,7 @@ static void ath9k_stop(struct ieee80211_hw *hw)
2137 } 2524 }
2138 2525
2139 if (sc->sc_flags & SC_OP_INVALID) { 2526 if (sc->sc_flags & SC_OP_INVALID) {
2140 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n"); 2527 ath_print(common, ATH_DBG_ANY, "Device not present\n");
2141 mutex_unlock(&sc->mutex); 2528 mutex_unlock(&sc->mutex);
2142 return; 2529 return;
2143 } 2530 }
@@ -2147,33 +2534,33 @@ static void ath9k_stop(struct ieee80211_hw *hw)
2147 return; /* another wiphy still in use */ 2534 return; /* another wiphy still in use */
2148 } 2535 }
2149 2536
2150 if (sc->sc_flags & SC_OP_BTCOEX_ENABLED) { 2537 if (ah->btcoex_hw.enabled) {
2151 ath9k_hw_btcoex_disable(sc->sc_ah); 2538 ath9k_hw_btcoex_disable(ah);
2152 if (sc->btcoex_info.btcoex_scheme == ATH_BTCOEX_CFG_3WIRE) 2539 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
2153 ath_btcoex_timer_pause(sc, &sc->btcoex_info); 2540 ath9k_btcoex_timer_pause(sc);
2154 } 2541 }
2155 2542
2156 /* make sure h/w will not generate any interrupt 2543 /* make sure h/w will not generate any interrupt
2157 * before setting the invalid flag. */ 2544 * before setting the invalid flag. */
2158 ath9k_hw_set_interrupts(sc->sc_ah, 0); 2545 ath9k_hw_set_interrupts(ah, 0);
2159 2546
2160 if (!(sc->sc_flags & SC_OP_INVALID)) { 2547 if (!(sc->sc_flags & SC_OP_INVALID)) {
2161 ath_drain_all_txq(sc, false); 2548 ath_drain_all_txq(sc, false);
2162 ath_stoprecv(sc); 2549 ath_stoprecv(sc);
2163 ath9k_hw_phy_disable(sc->sc_ah); 2550 ath9k_hw_phy_disable(ah);
2164 } else 2551 } else
2165 sc->rx.rxlink = NULL; 2552 sc->rx.rxlink = NULL;
2166 2553
2167 /* disable HAL and put h/w to sleep */ 2554 /* disable HAL and put h/w to sleep */
2168 ath9k_hw_disable(sc->sc_ah); 2555 ath9k_hw_disable(ah);
2169 ath9k_hw_configpcipowersave(sc->sc_ah, 1, 1); 2556 ath9k_hw_configpcipowersave(ah, 1, 1);
2170 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP); 2557 ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
2171 2558
2172 sc->sc_flags |= SC_OP_INVALID; 2559 sc->sc_flags |= SC_OP_INVALID;
2173 2560
2174 mutex_unlock(&sc->mutex); 2561 mutex_unlock(&sc->mutex);
2175 2562
2176 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n"); 2563 ath_print(common, ATH_DBG_CONFIG, "Driver halt\n");
2177} 2564}
2178 2565
2179static int ath9k_add_interface(struct ieee80211_hw *hw, 2566static int ath9k_add_interface(struct ieee80211_hw *hw,
@@ -2181,6 +2568,7 @@ static int ath9k_add_interface(struct ieee80211_hw *hw,
2181{ 2568{
2182 struct ath_wiphy *aphy = hw->priv; 2569 struct ath_wiphy *aphy = hw->priv;
2183 struct ath_softc *sc = aphy->sc; 2570 struct ath_softc *sc = aphy->sc;
2571 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2184 struct ath_vif *avp = (void *)conf->vif->drv_priv; 2572 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2185 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED; 2573 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2186 int ret = 0; 2574 int ret = 0;
@@ -2207,13 +2595,14 @@ static int ath9k_add_interface(struct ieee80211_hw *hw,
2207 ic_opmode = conf->type; 2595 ic_opmode = conf->type;
2208 break; 2596 break;
2209 default: 2597 default:
2210 DPRINTF(sc, ATH_DBG_FATAL, 2598 ath_print(common, ATH_DBG_FATAL,
2211 "Interface type %d not yet supported\n", conf->type); 2599 "Interface type %d not yet supported\n", conf->type);
2212 ret = -EOPNOTSUPP; 2600 ret = -EOPNOTSUPP;
2213 goto out; 2601 goto out;
2214 } 2602 }
2215 2603
2216 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode); 2604 ath_print(common, ATH_DBG_CONFIG,
2605 "Attach a VIF of type: %d\n", ic_opmode);
2217 2606
2218 /* Set the VIF opmode */ 2607 /* Set the VIF opmode */
2219 avp->av_opmode = ic_opmode; 2608 avp->av_opmode = ic_opmode;
@@ -2251,7 +2640,7 @@ static int ath9k_add_interface(struct ieee80211_hw *hw,
2251 if (conf->type == NL80211_IFTYPE_AP || 2640 if (conf->type == NL80211_IFTYPE_AP ||
2252 conf->type == NL80211_IFTYPE_ADHOC || 2641 conf->type == NL80211_IFTYPE_ADHOC ||
2253 conf->type == NL80211_IFTYPE_MONITOR) 2642 conf->type == NL80211_IFTYPE_MONITOR)
2254 ath_start_ani(sc); 2643 ath_start_ani(common);
2255 2644
2256out: 2645out:
2257 mutex_unlock(&sc->mutex); 2646 mutex_unlock(&sc->mutex);
@@ -2263,15 +2652,16 @@ static void ath9k_remove_interface(struct ieee80211_hw *hw,
2263{ 2652{
2264 struct ath_wiphy *aphy = hw->priv; 2653 struct ath_wiphy *aphy = hw->priv;
2265 struct ath_softc *sc = aphy->sc; 2654 struct ath_softc *sc = aphy->sc;
2655 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2266 struct ath_vif *avp = (void *)conf->vif->drv_priv; 2656 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2267 int i; 2657 int i;
2268 2658
2269 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n"); 2659 ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n");
2270 2660
2271 mutex_lock(&sc->mutex); 2661 mutex_lock(&sc->mutex);
2272 2662
2273 /* Stop ANI */ 2663 /* Stop ANI */
2274 del_timer_sync(&sc->ani.timer); 2664 del_timer_sync(&common->ani.timer);
2275 2665
2276 /* Reclaim beacon resources */ 2666 /* Reclaim beacon resources */
2277 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) || 2667 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
@@ -2301,27 +2691,43 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2301{ 2691{
2302 struct ath_wiphy *aphy = hw->priv; 2692 struct ath_wiphy *aphy = hw->priv;
2303 struct ath_softc *sc = aphy->sc; 2693 struct ath_softc *sc = aphy->sc;
2694 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2304 struct ieee80211_conf *conf = &hw->conf; 2695 struct ieee80211_conf *conf = &hw->conf;
2305 struct ath_hw *ah = sc->sc_ah; 2696 struct ath_hw *ah = sc->sc_ah;
2306 bool all_wiphys_idle = false, disable_radio = false; 2697 bool disable_radio;
2307 2698
2308 mutex_lock(&sc->mutex); 2699 mutex_lock(&sc->mutex);
2309 2700
2310 /* Leave this as the first check */ 2701 /*
2702 * Leave this as the first check because we need to turn on the
2703 * radio if it was disabled before prior to processing the rest
2704 * of the changes. Likewise we must only disable the radio towards
2705 * the end.
2706 */
2311 if (changed & IEEE80211_CONF_CHANGE_IDLE) { 2707 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
2708 bool enable_radio;
2709 bool all_wiphys_idle;
2710 bool idle = !!(conf->flags & IEEE80211_CONF_IDLE);
2312 2711
2313 spin_lock_bh(&sc->wiphy_lock); 2712 spin_lock_bh(&sc->wiphy_lock);
2314 all_wiphys_idle = ath9k_all_wiphys_idle(sc); 2713 all_wiphys_idle = ath9k_all_wiphys_idle(sc);
2714 ath9k_set_wiphy_idle(aphy, idle);
2715
2716 if (!idle && all_wiphys_idle)
2717 enable_radio = true;
2718
2719 /*
2720 * After we unlock here its possible another wiphy
2721 * can be re-renabled so to account for that we will
2722 * only disable the radio toward the end of this routine
2723 * if by then all wiphys are still idle.
2724 */
2315 spin_unlock_bh(&sc->wiphy_lock); 2725 spin_unlock_bh(&sc->wiphy_lock);
2316 2726
2317 if (conf->flags & IEEE80211_CONF_IDLE){ 2727 if (enable_radio) {
2318 if (all_wiphys_idle) 2728 ath_radio_enable(sc, hw);
2319 disable_radio = true; 2729 ath_print(common, ATH_DBG_CONFIG,
2320 } 2730 "not-idle: enabling radio\n");
2321 else if (all_wiphys_idle) {
2322 ath_radio_enable(sc);
2323 DPRINTF(sc, ATH_DBG_CONFIG,
2324 "not-idle: enabling radio\n");
2325 } 2731 }
2326 } 2732 }
2327 2733
@@ -2339,7 +2745,7 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2339 sc->ps_enabled = true; 2745 sc->ps_enabled = true;
2340 } else { 2746 } else {
2341 sc->ps_enabled = false; 2747 sc->ps_enabled = false;
2342 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); 2748 ath9k_setpower(sc, ATH9K_PM_AWAKE);
2343 if (!(ah->caps.hw_caps & 2749 if (!(ah->caps.hw_caps &
2344 ATH9K_HW_CAP_AUTOSLEEP)) { 2750 ATH9K_HW_CAP_AUTOSLEEP)) {
2345 ath9k_hw_setrxabort(sc->sc_ah, 0); 2751 ath9k_hw_setrxabort(sc->sc_ah, 0);
@@ -2374,8 +2780,8 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2374 goto skip_chan_change; 2780 goto skip_chan_change;
2375 } 2781 }
2376 2782
2377 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n", 2783 ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2378 curchan->center_freq); 2784 curchan->center_freq);
2379 2785
2380 /* XXX: remove me eventualy */ 2786 /* XXX: remove me eventualy */
2381 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]); 2787 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
@@ -2383,7 +2789,8 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2383 ath_update_chainmask(sc, conf_is_ht(conf)); 2789 ath_update_chainmask(sc, conf_is_ht(conf));
2384 2790
2385 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) { 2791 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
2386 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n"); 2792 ath_print(common, ATH_DBG_FATAL,
2793 "Unable to set channel\n");
2387 mutex_unlock(&sc->mutex); 2794 mutex_unlock(&sc->mutex);
2388 return -EINVAL; 2795 return -EINVAL;
2389 } 2796 }
@@ -2393,9 +2800,13 @@ skip_chan_change:
2393 if (changed & IEEE80211_CONF_CHANGE_POWER) 2800 if (changed & IEEE80211_CONF_CHANGE_POWER)
2394 sc->config.txpowlimit = 2 * conf->power_level; 2801 sc->config.txpowlimit = 2 * conf->power_level;
2395 2802
2803 spin_lock_bh(&sc->wiphy_lock);
2804 disable_radio = ath9k_all_wiphys_idle(sc);
2805 spin_unlock_bh(&sc->wiphy_lock);
2806
2396 if (disable_radio) { 2807 if (disable_radio) {
2397 DPRINTF(sc, ATH_DBG_CONFIG, "idle: disabling radio\n"); 2808 ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
2398 ath_radio_disable(sc); 2809 ath_radio_disable(sc, hw);
2399 } 2810 }
2400 2811
2401 mutex_unlock(&sc->mutex); 2812 mutex_unlock(&sc->mutex);
@@ -2431,7 +2842,8 @@ static void ath9k_configure_filter(struct ieee80211_hw *hw,
2431 ath9k_hw_setrxfilter(sc->sc_ah, rfilt); 2842 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2432 ath9k_ps_restore(sc); 2843 ath9k_ps_restore(sc);
2433 2844
2434 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", rfilt); 2845 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
2846 "Set HW RX filter: 0x%x\n", rfilt);
2435} 2847}
2436 2848
2437static void ath9k_sta_notify(struct ieee80211_hw *hw, 2849static void ath9k_sta_notify(struct ieee80211_hw *hw,
@@ -2459,6 +2871,7 @@ static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2459{ 2871{
2460 struct ath_wiphy *aphy = hw->priv; 2872 struct ath_wiphy *aphy = hw->priv;
2461 struct ath_softc *sc = aphy->sc; 2873 struct ath_softc *sc = aphy->sc;
2874 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2462 struct ath9k_tx_queue_info qi; 2875 struct ath9k_tx_queue_info qi;
2463 int ret = 0, qnum; 2876 int ret = 0, qnum;
2464 2877
@@ -2475,15 +2888,15 @@ static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2475 qi.tqi_burstTime = params->txop; 2888 qi.tqi_burstTime = params->txop;
2476 qnum = ath_get_hal_qnum(queue, sc); 2889 qnum = ath_get_hal_qnum(queue, sc);
2477 2890
2478 DPRINTF(sc, ATH_DBG_CONFIG, 2891 ath_print(common, ATH_DBG_CONFIG,
2479 "Configure tx [queue/halq] [%d/%d], " 2892 "Configure tx [queue/halq] [%d/%d], "
2480 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", 2893 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2481 queue, qnum, params->aifs, params->cw_min, 2894 queue, qnum, params->aifs, params->cw_min,
2482 params->cw_max, params->txop); 2895 params->cw_max, params->txop);
2483 2896
2484 ret = ath_txq_update(sc, qnum, &qi); 2897 ret = ath_txq_update(sc, qnum, &qi);
2485 if (ret) 2898 if (ret)
2486 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n"); 2899 ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n");
2487 2900
2488 mutex_unlock(&sc->mutex); 2901 mutex_unlock(&sc->mutex);
2489 2902
@@ -2498,6 +2911,7 @@ static int ath9k_set_key(struct ieee80211_hw *hw,
2498{ 2911{
2499 struct ath_wiphy *aphy = hw->priv; 2912 struct ath_wiphy *aphy = hw->priv;
2500 struct ath_softc *sc = aphy->sc; 2913 struct ath_softc *sc = aphy->sc;
2914 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2501 int ret = 0; 2915 int ret = 0;
2502 2916
2503 if (modparam_nohwcrypt) 2917 if (modparam_nohwcrypt)
@@ -2505,11 +2919,11 @@ static int ath9k_set_key(struct ieee80211_hw *hw,
2505 2919
2506 mutex_lock(&sc->mutex); 2920 mutex_lock(&sc->mutex);
2507 ath9k_ps_wakeup(sc); 2921 ath9k_ps_wakeup(sc);
2508 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW Key\n"); 2922 ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n");
2509 2923
2510 switch (cmd) { 2924 switch (cmd) {
2511 case SET_KEY: 2925 case SET_KEY:
2512 ret = ath_key_config(sc, vif, sta, key); 2926 ret = ath_key_config(common, vif, sta, key);
2513 if (ret >= 0) { 2927 if (ret >= 0) {
2514 key->hw_key_idx = ret; 2928 key->hw_key_idx = ret;
2515 /* push IV and Michael MIC generation to stack */ 2929 /* push IV and Michael MIC generation to stack */
@@ -2522,7 +2936,7 @@ static int ath9k_set_key(struct ieee80211_hw *hw,
2522 } 2936 }
2523 break; 2937 break;
2524 case DISABLE_KEY: 2938 case DISABLE_KEY:
2525 ath_key_delete(sc, key); 2939 ath_key_delete(common, key);
2526 break; 2940 break;
2527 default: 2941 default:
2528 ret = -EINVAL; 2942 ret = -EINVAL;
@@ -2542,94 +2956,67 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2542 struct ath_wiphy *aphy = hw->priv; 2956 struct ath_wiphy *aphy = hw->priv;
2543 struct ath_softc *sc = aphy->sc; 2957 struct ath_softc *sc = aphy->sc;
2544 struct ath_hw *ah = sc->sc_ah; 2958 struct ath_hw *ah = sc->sc_ah;
2959 struct ath_common *common = ath9k_hw_common(ah);
2545 struct ath_vif *avp = (void *)vif->drv_priv; 2960 struct ath_vif *avp = (void *)vif->drv_priv;
2546 u32 rfilt = 0; 2961 int error;
2547 int error, i;
2548 2962
2549 mutex_lock(&sc->mutex); 2963 mutex_lock(&sc->mutex);
2550 2964
2551 /* 2965 if (changed & BSS_CHANGED_BSSID) {
2552 * TODO: Need to decide which hw opmode to use for 2966 /* Set BSSID */
2553 * multi-interface cases 2967 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
2554 * XXX: This belongs into add_interface! 2968 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2555 */ 2969 common->curaid = 0;
2556 if (vif->type == NL80211_IFTYPE_AP && 2970 ath9k_hw_write_associd(ah);
2557 ah->opmode != NL80211_IFTYPE_AP) {
2558 ah->opmode = NL80211_IFTYPE_STATION;
2559 ath9k_hw_setopmode(ah);
2560 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2561 sc->curaid = 0;
2562 ath9k_hw_write_associd(sc);
2563 /* Request full reset to get hw opmode changed properly */
2564 sc->sc_flags |= SC_OP_FULL_RESET;
2565 }
2566
2567 if ((changed & BSS_CHANGED_BSSID) &&
2568 !is_zero_ether_addr(bss_conf->bssid)) {
2569 switch (vif->type) {
2570 case NL80211_IFTYPE_STATION:
2571 case NL80211_IFTYPE_ADHOC:
2572 case NL80211_IFTYPE_MESH_POINT:
2573 /* Set BSSID */
2574 memcpy(sc->curbssid, bss_conf->bssid, ETH_ALEN);
2575 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2576 sc->curaid = 0;
2577 ath9k_hw_write_associd(sc);
2578
2579 /* Set aggregation protection mode parameters */
2580 sc->config.ath_aggr_prot = 0;
2581
2582 DPRINTF(sc, ATH_DBG_CONFIG,
2583 "RX filter 0x%x bssid %pM aid 0x%x\n",
2584 rfilt, sc->curbssid, sc->curaid);
2585
2586 /* need to reconfigure the beacon */
2587 sc->sc_flags &= ~SC_OP_BEACONS ;
2588 2971
2589 break; 2972 /* Set aggregation protection mode parameters */
2590 default: 2973 sc->config.ath_aggr_prot = 0;
2591 break; 2974
2592 } 2975 /* Only legacy IBSS for now */
2976 if (vif->type == NL80211_IFTYPE_ADHOC)
2977 ath_update_chainmask(sc, 0);
2978
2979 ath_print(common, ATH_DBG_CONFIG,
2980 "BSSID: %pM aid: 0x%x\n",
2981 common->curbssid, common->curaid);
2982
2983 /* need to reconfigure the beacon */
2984 sc->sc_flags &= ~SC_OP_BEACONS ;
2593 } 2985 }
2594 2986
2595 if ((vif->type == NL80211_IFTYPE_ADHOC) || 2987 /* Enable transmission of beacons (AP, IBSS, MESH) */
2596 (vif->type == NL80211_IFTYPE_AP) || 2988 if ((changed & BSS_CHANGED_BEACON) ||
2597 (vif->type == NL80211_IFTYPE_MESH_POINT)) { 2989 ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
2598 if ((changed & BSS_CHANGED_BEACON) || 2990 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2599 (changed & BSS_CHANGED_BEACON_ENABLED && 2991 error = ath_beacon_alloc(aphy, vif);
2600 bss_conf->enable_beacon)) { 2992 if (!error)
2601 /* 2993 ath_beacon_config(sc, vif);
2602 * Allocate and setup the beacon frame. 2994 }
2603 *
2604 * Stop any previous beacon DMA. This may be
2605 * necessary, for example, when an ibss merge
2606 * causes reconfiguration; we may be called
2607 * with beacon transmission active.
2608 */
2609 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2610 2995
2996 /* Disable transmission of beacons */
2997 if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon)
2998 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2999
3000 if (changed & BSS_CHANGED_BEACON_INT) {
3001 sc->beacon_interval = bss_conf->beacon_int;
3002 /*
3003 * In case of AP mode, the HW TSF has to be reset
3004 * when the beacon interval changes.
3005 */
3006 if (vif->type == NL80211_IFTYPE_AP) {
3007 sc->sc_flags |= SC_OP_TSF_RESET;
3008 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2611 error = ath_beacon_alloc(aphy, vif); 3009 error = ath_beacon_alloc(aphy, vif);
2612 if (!error) 3010 if (!error)
2613 ath_beacon_config(sc, vif); 3011 ath_beacon_config(sc, vif);
3012 } else {
3013 ath_beacon_config(sc, vif);
2614 } 3014 }
2615 } 3015 }
2616 3016
2617 /* Check for WLAN_CAPABILITY_PRIVACY ? */
2618 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2619 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2620 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2621 ath9k_hw_keysetmac(sc->sc_ah,
2622 (u16)i,
2623 sc->curbssid);
2624 }
2625
2626 /* Only legacy IBSS for now */
2627 if (vif->type == NL80211_IFTYPE_ADHOC)
2628 ath_update_chainmask(sc, 0);
2629
2630 if (changed & BSS_CHANGED_ERP_PREAMBLE) { 3017 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2631 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n", 3018 ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2632 bss_conf->use_short_preamble); 3019 bss_conf->use_short_preamble);
2633 if (bss_conf->use_short_preamble) 3020 if (bss_conf->use_short_preamble)
2634 sc->sc_flags |= SC_OP_PREAMBLE_SHORT; 3021 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2635 else 3022 else
@@ -2637,8 +3024,8 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2637 } 3024 }
2638 3025
2639 if (changed & BSS_CHANGED_ERP_CTS_PROT) { 3026 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2640 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n", 3027 ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2641 bss_conf->use_cts_prot); 3028 bss_conf->use_cts_prot);
2642 if (bss_conf->use_cts_prot && 3029 if (bss_conf->use_cts_prot &&
2643 hw->conf.channel->band != IEEE80211_BAND_5GHZ) 3030 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2644 sc->sc_flags |= SC_OP_PROTECT_ENABLE; 3031 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
@@ -2647,23 +3034,11 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2647 } 3034 }
2648 3035
2649 if (changed & BSS_CHANGED_ASSOC) { 3036 if (changed & BSS_CHANGED_ASSOC) {
2650 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n", 3037 ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2651 bss_conf->assoc); 3038 bss_conf->assoc);
2652 ath9k_bss_assoc_info(sc, vif, bss_conf); 3039 ath9k_bss_assoc_info(sc, vif, bss_conf);
2653 } 3040 }
2654 3041
2655 /*
2656 * The HW TSF has to be reset when the beacon interval changes.
2657 * We set the flag here, and ath_beacon_config_ap() would take this
2658 * into account when it gets called through the subsequent
2659 * config_interface() call - with IFCC_BEACON in the changed field.
2660 */
2661
2662 if (changed & BSS_CHANGED_BEACON_INT) {
2663 sc->sc_flags |= SC_OP_TSF_RESET;
2664 sc->beacon_interval = bss_conf->beacon_int;
2665 }
2666
2667 mutex_unlock(&sc->mutex); 3042 mutex_unlock(&sc->mutex);
2668} 3043}
2669 3044
@@ -2696,11 +3071,16 @@ static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2696 struct ath_softc *sc = aphy->sc; 3071 struct ath_softc *sc = aphy->sc;
2697 3072
2698 mutex_lock(&sc->mutex); 3073 mutex_lock(&sc->mutex);
3074
3075 ath9k_ps_wakeup(sc);
2699 ath9k_hw_reset_tsf(sc->sc_ah); 3076 ath9k_hw_reset_tsf(sc->sc_ah);
3077 ath9k_ps_restore(sc);
3078
2700 mutex_unlock(&sc->mutex); 3079 mutex_unlock(&sc->mutex);
2701} 3080}
2702 3081
2703static int ath9k_ampdu_action(struct ieee80211_hw *hw, 3082static int ath9k_ampdu_action(struct ieee80211_hw *hw,
3083 struct ieee80211_vif *vif,
2704 enum ieee80211_ampdu_mlme_action action, 3084 enum ieee80211_ampdu_mlme_action action,
2705 struct ieee80211_sta *sta, 3085 struct ieee80211_sta *sta,
2706 u16 tid, u16 *ssn) 3086 u16 tid, u16 *ssn)
@@ -2718,17 +3098,18 @@ static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2718 break; 3098 break;
2719 case IEEE80211_AMPDU_TX_START: 3099 case IEEE80211_AMPDU_TX_START:
2720 ath_tx_aggr_start(sc, sta, tid, ssn); 3100 ath_tx_aggr_start(sc, sta, tid, ssn);
2721 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid); 3101 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2722 break; 3102 break;
2723 case IEEE80211_AMPDU_TX_STOP: 3103 case IEEE80211_AMPDU_TX_STOP:
2724 ath_tx_aggr_stop(sc, sta, tid); 3104 ath_tx_aggr_stop(sc, sta, tid);
2725 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid); 3105 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2726 break; 3106 break;
2727 case IEEE80211_AMPDU_TX_OPERATIONAL: 3107 case IEEE80211_AMPDU_TX_OPERATIONAL:
2728 ath_tx_aggr_resume(sc, sta, tid); 3108 ath_tx_aggr_resume(sc, sta, tid);
2729 break; 3109 break;
2730 default: 3110 default:
2731 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n"); 3111 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
3112 "Unknown AMPDU action\n");
2732 } 3113 }
2733 3114
2734 return ret; 3115 return ret;
@@ -2796,64 +3177,6 @@ struct ieee80211_ops ath9k_ops = {
2796 .rfkill_poll = ath9k_rfkill_poll_state, 3177 .rfkill_poll = ath9k_rfkill_poll_state,
2797}; 3178};
2798 3179
2799static struct {
2800 u32 version;
2801 const char * name;
2802} ath_mac_bb_names[] = {
2803 { AR_SREV_VERSION_5416_PCI, "5416" },
2804 { AR_SREV_VERSION_5416_PCIE, "5418" },
2805 { AR_SREV_VERSION_9100, "9100" },
2806 { AR_SREV_VERSION_9160, "9160" },
2807 { AR_SREV_VERSION_9280, "9280" },
2808 { AR_SREV_VERSION_9285, "9285" },
2809 { AR_SREV_VERSION_9287, "9287" }
2810};
2811
2812static struct {
2813 u16 version;
2814 const char * name;
2815} ath_rf_names[] = {
2816 { 0, "5133" },
2817 { AR_RAD5133_SREV_MAJOR, "5133" },
2818 { AR_RAD5122_SREV_MAJOR, "5122" },
2819 { AR_RAD2133_SREV_MAJOR, "2133" },
2820 { AR_RAD2122_SREV_MAJOR, "2122" }
2821};
2822
2823/*
2824 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2825 */
2826const char *
2827ath_mac_bb_name(u32 mac_bb_version)
2828{
2829 int i;
2830
2831 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2832 if (ath_mac_bb_names[i].version == mac_bb_version) {
2833 return ath_mac_bb_names[i].name;
2834 }
2835 }
2836
2837 return "????";
2838}
2839
2840/*
2841 * Return the RF name. "????" is returned if the RF is unknown.
2842 */
2843const char *
2844ath_rf_name(u16 rf_version)
2845{
2846 int i;
2847
2848 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2849 if (ath_rf_names[i].version == rf_version) {
2850 return ath_rf_names[i].name;
2851 }
2852 }
2853
2854 return "????";
2855}
2856
2857static int __init ath9k_init(void) 3180static int __init ath9k_init(void)
2858{ 3181{
2859 int error; 3182 int error;
diff --git a/drivers/net/wireless/ath/ath9k/pci.c b/drivers/net/wireless/ath/ath9k/pci.c
index 903dd8ad9d43..5321f735e5a0 100644
--- a/drivers/net/wireless/ath/ath9k/pci.c
+++ b/drivers/net/wireless/ath/ath9k/pci.c
@@ -31,8 +31,9 @@ static struct pci_device_id ath_pci_id_table[] __devinitdata = {
31}; 31};
32 32
33/* return bus cachesize in 4B word units */ 33/* return bus cachesize in 4B word units */
34static void ath_pci_read_cachesize(struct ath_softc *sc, int *csz) 34static void ath_pci_read_cachesize(struct ath_common *common, int *csz)
35{ 35{
36 struct ath_softc *sc = (struct ath_softc *) common->priv;
36 u8 u8tmp; 37 u8 u8tmp;
37 38
38 pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp); 39 pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp);
@@ -48,8 +49,9 @@ static void ath_pci_read_cachesize(struct ath_softc *sc, int *csz)
48 *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */ 49 *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */
49} 50}
50 51
51static void ath_pci_cleanup(struct ath_softc *sc) 52static void ath_pci_cleanup(struct ath_common *common)
52{ 53{
54 struct ath_softc *sc = (struct ath_softc *) common->priv;
53 struct pci_dev *pdev = to_pci_dev(sc->dev); 55 struct pci_dev *pdev = to_pci_dev(sc->dev);
54 56
55 pci_iounmap(pdev, sc->mem); 57 pci_iounmap(pdev, sc->mem);
@@ -57,9 +59,11 @@ static void ath_pci_cleanup(struct ath_softc *sc)
57 pci_release_region(pdev, 0); 59 pci_release_region(pdev, 0);
58} 60}
59 61
60static bool ath_pci_eeprom_read(struct ath_hw *ah, u32 off, u16 *data) 62static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data)
61{ 63{
62 (void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S)); 64 struct ath_hw *ah = (struct ath_hw *) common->ah;
65
66 common->ops->read(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
63 67
64 if (!ath9k_hw_wait(ah, 68 if (!ath9k_hw_wait(ah,
65 AR_EEPROM_STATUS_DATA, 69 AR_EEPROM_STATUS_DATA,
@@ -69,16 +73,34 @@ static bool ath_pci_eeprom_read(struct ath_hw *ah, u32 off, u16 *data)
69 return false; 73 return false;
70 } 74 }
71 75
72 *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA), 76 *data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA),
73 AR_EEPROM_STATUS_DATA_VAL); 77 AR_EEPROM_STATUS_DATA_VAL);
74 78
75 return true; 79 return true;
76} 80}
77 81
78static struct ath_bus_ops ath_pci_bus_ops = { 82/*
83 * Bluetooth coexistance requires disabling ASPM.
84 */
85static void ath_pci_bt_coex_prep(struct ath_common *common)
86{
87 struct ath_softc *sc = (struct ath_softc *) common->priv;
88 struct pci_dev *pdev = to_pci_dev(sc->dev);
89 u8 aspm;
90
91 if (!pdev->is_pcie)
92 return;
93
94 pci_read_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, &aspm);
95 aspm &= ~(ATH_PCIE_CAP_LINK_L0S | ATH_PCIE_CAP_LINK_L1);
96 pci_write_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, aspm);
97}
98
99const static struct ath_bus_ops ath_pci_bus_ops = {
79 .read_cachesize = ath_pci_read_cachesize, 100 .read_cachesize = ath_pci_read_cachesize,
80 .cleanup = ath_pci_cleanup, 101 .cleanup = ath_pci_cleanup,
81 .eeprom_read = ath_pci_eeprom_read, 102 .eeprom_read = ath_pci_eeprom_read,
103 .bt_coex_prep = ath_pci_bt_coex_prep,
82}; 104};
83 105
84static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 106static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
@@ -92,6 +114,7 @@ static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
92 u32 val; 114 u32 val;
93 int ret = 0; 115 int ret = 0;
94 struct ath_hw *ah; 116 struct ath_hw *ah;
117 char hw_name[64];
95 118
96 if (pci_enable_device(pdev)) 119 if (pci_enable_device(pdev))
97 return -EIO; 120 return -EIO;
@@ -177,10 +200,9 @@ static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
177 sc->hw = hw; 200 sc->hw = hw;
178 sc->dev = &pdev->dev; 201 sc->dev = &pdev->dev;
179 sc->mem = mem; 202 sc->mem = mem;
180 sc->bus_ops = &ath_pci_bus_ops;
181 203
182 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &subsysid); 204 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &subsysid);
183 ret = ath_init_device(id->device, sc, subsysid); 205 ret = ath_init_device(id->device, sc, subsysid, &ath_pci_bus_ops);
184 if (ret) { 206 if (ret) {
185 dev_err(&pdev->dev, "failed to initialize device\n"); 207 dev_err(&pdev->dev, "failed to initialize device\n");
186 goto bad3; 208 goto bad3;
@@ -197,14 +219,11 @@ static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
197 sc->irq = pdev->irq; 219 sc->irq = pdev->irq;
198 220
199 ah = sc->sc_ah; 221 ah = sc->sc_ah;
222 ath9k_hw_name(ah, hw_name, sizeof(hw_name));
200 printk(KERN_INFO 223 printk(KERN_INFO
201 "%s: Atheros AR%s MAC/BB Rev:%x " 224 "%s: %s mem=0x%lx, irq=%d\n",
202 "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
203 wiphy_name(hw->wiphy), 225 wiphy_name(hw->wiphy),
204 ath_mac_bb_name(ah->hw_version.macVersion), 226 hw_name,
205 ah->hw_version.macRev,
206 ath_rf_name((ah->hw_version.analog5GhzRev & AR_RADIO_SREV_MAJOR)),
207 ah->hw_version.phyRev,
208 (unsigned long)mem, pdev->irq); 227 (unsigned long)mem, pdev->irq);
209 228
210 return 0; 229 return 0;
diff --git a/drivers/net/wireless/ath/ath9k/phy.c b/drivers/net/wireless/ath/ath9k/phy.c
index 63bf9a307c6a..c3b59390fe38 100644
--- a/drivers/net/wireless/ath/ath9k/phy.c
+++ b/drivers/net/wireless/ath/ath9k/phy.c
@@ -14,90 +14,70 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17#include "ath9k.h" 17/**
18 * DOC: Programming Atheros 802.11n analog front end radios
19 *
20 * AR5416 MAC based PCI devices and AR518 MAC based PCI-Express
21 * devices have either an external AR2133 analog front end radio for single
22 * band 2.4 GHz communication or an AR5133 analog front end radio for dual
23 * band 2.4 GHz / 5 GHz communication.
24 *
25 * All devices after the AR5416 and AR5418 family starting with the AR9280
26 * have their analog front radios, MAC/BB and host PCIe/USB interface embedded
27 * into a single-chip and require less programming.
28 *
29 * The following single-chips exist with a respective embedded radio:
30 *
31 * AR9280 - 11n dual-band 2x2 MIMO for PCIe
32 * AR9281 - 11n single-band 1x2 MIMO for PCIe
33 * AR9285 - 11n single-band 1x1 for PCIe
34 * AR9287 - 11n single-band 2x2 MIMO for PCIe
35 *
36 * AR9220 - 11n dual-band 2x2 MIMO for PCI
37 * AR9223 - 11n single-band 2x2 MIMO for PCI
38 *
39 * AR9287 - 11n single-band 1x1 MIMO for USB
40 */
18 41
19void 42#include "hw.h"
20ath9k_hw_write_regs(struct ath_hw *ah, u32 modesIndex, u32 freqIndex,
21 int regWrites)
22{
23 REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
24}
25 43
26bool 44/**
27ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) 45 * ath9k_hw_write_regs - ??
46 *
47 * @ah: atheros hardware structure
48 * @freqIndex:
49 * @regWrites:
50 *
51 * Used for both the chipsets with an external AR2133/AR5133 radios and
52 * single-chip devices.
53 */
54void ath9k_hw_write_regs(struct ath_hw *ah, u32 freqIndex, int regWrites)
28{ 55{
29 u32 channelSel = 0; 56 REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
30 u32 bModeSynth = 0;
31 u32 aModeRefSel = 0;
32 u32 reg32 = 0;
33 u16 freq;
34 struct chan_centers centers;
35
36 ath9k_hw_get_channel_centers(ah, chan, &centers);
37 freq = centers.synth_center;
38
39 if (freq < 4800) {
40 u32 txctl;
41
42 if (((freq - 2192) % 5) == 0) {
43 channelSel = ((freq - 672) * 2 - 3040) / 10;
44 bModeSynth = 0;
45 } else if (((freq - 2224) % 5) == 0) {
46 channelSel = ((freq - 704) * 2 - 3040) / 10;
47 bModeSynth = 1;
48 } else {
49 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
50 "Invalid channel %u MHz\n", freq);
51 return false;
52 }
53
54 channelSel = (channelSel << 2) & 0xff;
55 channelSel = ath9k_hw_reverse_bits(channelSel, 8);
56
57 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
58 if (freq == 2484) {
59
60 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
61 txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
62 } else {
63 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
64 txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
65 }
66
67 } else if ((freq % 20) == 0 && freq >= 5120) {
68 channelSel =
69 ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
70 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
71 } else if ((freq % 10) == 0) {
72 channelSel =
73 ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
74 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
75 aModeRefSel = ath9k_hw_reverse_bits(2, 2);
76 else
77 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
78 } else if ((freq % 5) == 0) {
79 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
80 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
81 } else {
82 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
83 "Invalid channel %u MHz\n", freq);
84 return false;
85 }
86
87 reg32 =
88 (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
89 (1 << 5) | 0x1;
90
91 REG_WRITE(ah, AR_PHY(0x37), reg32);
92
93 ah->curchan = chan;
94 ah->curchan_rad_index = -1;
95
96 return true;
97} 57}
98 58
99void ath9k_hw_ar9280_set_channel(struct ath_hw *ah, 59/**
100 struct ath9k_channel *chan) 60 * ath9k_hw_ar9280_set_channel - set channel on single-chip device
61 * @ah: atheros hardware structure
62 * @chan:
63 *
64 * This is the function to change channel on single-chip devices, that is
65 * all devices after ar9280.
66 *
67 * This function takes the channel value in MHz and sets
68 * hardware channel value. Assumes writes have been enabled to analog bus.
69 *
70 * Actual Expression,
71 *
72 * For 2GHz channel,
73 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
74 * (freq_ref = 40MHz)
75 *
76 * For 5GHz channel,
77 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
78 * (freq_ref = 40MHz/(24>>amodeRefSel))
79 */
80int ath9k_hw_ar9280_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
101{ 81{
102 u16 bMode, fracMode, aModeRefSel = 0; 82 u16 bMode, fracMode, aModeRefSel = 0;
103 u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0; 83 u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
@@ -110,22 +90,34 @@ void ath9k_hw_ar9280_set_channel(struct ath_hw *ah,
110 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL); 90 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL);
111 reg32 &= 0xc0000000; 91 reg32 &= 0xc0000000;
112 92
113 if (freq < 4800) { 93 if (freq < 4800) { /* 2 GHz, fractional mode */
114 u32 txctl; 94 u32 txctl;
95 int regWrites = 0;
115 96
116 bMode = 1; 97 bMode = 1;
117 fracMode = 1; 98 fracMode = 1;
118 aModeRefSel = 0; 99 aModeRefSel = 0;
119 channelSel = (freq * 0x10000) / 15; 100 channelSel = (freq * 0x10000) / 15;
120 101
121 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); 102 if (AR_SREV_9287_11_OR_LATER(ah)) {
122 if (freq == 2484) { 103 if (freq == 2484) {
123 104 /* Enable channel spreading for channel 14 */
124 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, 105 REG_WRITE_ARRAY(&ah->iniCckfirJapan2484,
125 txctl | AR_PHY_CCK_TX_CTRL_JAPAN); 106 1, regWrites);
107 } else {
108 REG_WRITE_ARRAY(&ah->iniCckfirNormal,
109 1, regWrites);
110 }
126 } else { 111 } else {
127 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, 112 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
128 txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN); 113 if (freq == 2484) {
114 /* Enable channel spreading for channel 14 */
115 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
116 txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
117 } else {
118 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
119 txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);
120 }
129 } 121 }
130 } else { 122 } else {
131 bMode = 0; 123 bMode = 0;
@@ -143,10 +135,15 @@ void ath9k_hw_ar9280_set_channel(struct ath_hw *ah,
143 case 1: 135 case 1:
144 default: 136 default:
145 aModeRefSel = 0; 137 aModeRefSel = 0;
138 /*
139 * Enable 2G (fractional) mode for channels
140 * which are 5MHz spaced.
141 */
146 fracMode = 1; 142 fracMode = 1;
147 refDivA = 1; 143 refDivA = 1;
148 channelSel = (freq * 0x8000) / 15; 144 channelSel = (freq * 0x8000) / 15;
149 145
146 /* RefDivA setting */
150 REG_RMW_FIELD(ah, AR_AN_SYNTH9, 147 REG_RMW_FIELD(ah, AR_AN_SYNTH9,
151 AR_AN_SYNTH9_REFDIVA, refDivA); 148 AR_AN_SYNTH9_REFDIVA, refDivA);
152 149
@@ -168,12 +165,284 @@ void ath9k_hw_ar9280_set_channel(struct ath_hw *ah,
168 165
169 ah->curchan = chan; 166 ah->curchan = chan;
170 ah->curchan_rad_index = -1; 167 ah->curchan_rad_index = -1;
168
169 return 0;
170}
171
172/**
173 * ath9k_hw_9280_spur_mitigate - convert baseband spur frequency
174 * @ah: atheros hardware structure
175 * @chan:
176 *
177 * For single-chip solutions. Converts to baseband spur frequency given the
178 * input channel frequency and compute register settings below.
179 */
180void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
181{
182 int bb_spur = AR_NO_SPUR;
183 int freq;
184 int bin, cur_bin;
185 int bb_spur_off, spur_subchannel_sd;
186 int spur_freq_sd;
187 int spur_delta_phase;
188 int denominator;
189 int upper, lower, cur_vit_mask;
190 int tmp, newVal;
191 int i;
192 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
193 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
194 };
195 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
196 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
197 };
198 int inc[4] = { 0, 100, 0, 0 };
199 struct chan_centers centers;
200
201 int8_t mask_m[123];
202 int8_t mask_p[123];
203 int8_t mask_amt;
204 int tmp_mask;
205 int cur_bb_spur;
206 bool is2GHz = IS_CHAN_2GHZ(chan);
207
208 memset(&mask_m, 0, sizeof(int8_t) * 123);
209 memset(&mask_p, 0, sizeof(int8_t) * 123);
210
211 ath9k_hw_get_channel_centers(ah, chan, &centers);
212 freq = centers.synth_center;
213
214 ah->config.spurmode = SPUR_ENABLE_EEPROM;
215 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
216 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
217
218 if (is2GHz)
219 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
220 else
221 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
222
223 if (AR_NO_SPUR == cur_bb_spur)
224 break;
225 cur_bb_spur = cur_bb_spur - freq;
226
227 if (IS_CHAN_HT40(chan)) {
228 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
229 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
230 bb_spur = cur_bb_spur;
231 break;
232 }
233 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
234 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
235 bb_spur = cur_bb_spur;
236 break;
237 }
238 }
239
240 if (AR_NO_SPUR == bb_spur) {
241 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
242 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
243 return;
244 } else {
245 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
246 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
247 }
248
249 bin = bb_spur * 320;
250
251 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
252
253 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
254 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
255 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
256 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
257 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
258
259 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
260 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
261 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
262 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
263 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
264 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
265
266 if (IS_CHAN_HT40(chan)) {
267 if (bb_spur < 0) {
268 spur_subchannel_sd = 1;
269 bb_spur_off = bb_spur + 10;
270 } else {
271 spur_subchannel_sd = 0;
272 bb_spur_off = bb_spur - 10;
273 }
274 } else {
275 spur_subchannel_sd = 0;
276 bb_spur_off = bb_spur;
277 }
278
279 if (IS_CHAN_HT40(chan))
280 spur_delta_phase =
281 ((bb_spur * 262144) /
282 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
283 else
284 spur_delta_phase =
285 ((bb_spur * 524288) /
286 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
287
288 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
289 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
290
291 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
292 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
293 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
294 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
295
296 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
297 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
298
299 cur_bin = -6000;
300 upper = bin + 100;
301 lower = bin - 100;
302
303 for (i = 0; i < 4; i++) {
304 int pilot_mask = 0;
305 int chan_mask = 0;
306 int bp = 0;
307 for (bp = 0; bp < 30; bp++) {
308 if ((cur_bin > lower) && (cur_bin < upper)) {
309 pilot_mask = pilot_mask | 0x1 << bp;
310 chan_mask = chan_mask | 0x1 << bp;
311 }
312 cur_bin += 100;
313 }
314 cur_bin += inc[i];
315 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
316 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
317 }
318
319 cur_vit_mask = 6100;
320 upper = bin + 120;
321 lower = bin - 120;
322
323 for (i = 0; i < 123; i++) {
324 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
325
326 /* workaround for gcc bug #37014 */
327 volatile int tmp_v = abs(cur_vit_mask - bin);
328
329 if (tmp_v < 75)
330 mask_amt = 1;
331 else
332 mask_amt = 0;
333 if (cur_vit_mask < 0)
334 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
335 else
336 mask_p[cur_vit_mask / 100] = mask_amt;
337 }
338 cur_vit_mask -= 100;
339 }
340
341 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
342 | (mask_m[48] << 26) | (mask_m[49] << 24)
343 | (mask_m[50] << 22) | (mask_m[51] << 20)
344 | (mask_m[52] << 18) | (mask_m[53] << 16)
345 | (mask_m[54] << 14) | (mask_m[55] << 12)
346 | (mask_m[56] << 10) | (mask_m[57] << 8)
347 | (mask_m[58] << 6) | (mask_m[59] << 4)
348 | (mask_m[60] << 2) | (mask_m[61] << 0);
349 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
350 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
351
352 tmp_mask = (mask_m[31] << 28)
353 | (mask_m[32] << 26) | (mask_m[33] << 24)
354 | (mask_m[34] << 22) | (mask_m[35] << 20)
355 | (mask_m[36] << 18) | (mask_m[37] << 16)
356 | (mask_m[48] << 14) | (mask_m[39] << 12)
357 | (mask_m[40] << 10) | (mask_m[41] << 8)
358 | (mask_m[42] << 6) | (mask_m[43] << 4)
359 | (mask_m[44] << 2) | (mask_m[45] << 0);
360 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
361 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
362
363 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
364 | (mask_m[18] << 26) | (mask_m[18] << 24)
365 | (mask_m[20] << 22) | (mask_m[20] << 20)
366 | (mask_m[22] << 18) | (mask_m[22] << 16)
367 | (mask_m[24] << 14) | (mask_m[24] << 12)
368 | (mask_m[25] << 10) | (mask_m[26] << 8)
369 | (mask_m[27] << 6) | (mask_m[28] << 4)
370 | (mask_m[29] << 2) | (mask_m[30] << 0);
371 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
372 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
373
374 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
375 | (mask_m[2] << 26) | (mask_m[3] << 24)
376 | (mask_m[4] << 22) | (mask_m[5] << 20)
377 | (mask_m[6] << 18) | (mask_m[7] << 16)
378 | (mask_m[8] << 14) | (mask_m[9] << 12)
379 | (mask_m[10] << 10) | (mask_m[11] << 8)
380 | (mask_m[12] << 6) | (mask_m[13] << 4)
381 | (mask_m[14] << 2) | (mask_m[15] << 0);
382 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
383 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
384
385 tmp_mask = (mask_p[15] << 28)
386 | (mask_p[14] << 26) | (mask_p[13] << 24)
387 | (mask_p[12] << 22) | (mask_p[11] << 20)
388 | (mask_p[10] << 18) | (mask_p[9] << 16)
389 | (mask_p[8] << 14) | (mask_p[7] << 12)
390 | (mask_p[6] << 10) | (mask_p[5] << 8)
391 | (mask_p[4] << 6) | (mask_p[3] << 4)
392 | (mask_p[2] << 2) | (mask_p[1] << 0);
393 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
394 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
395
396 tmp_mask = (mask_p[30] << 28)
397 | (mask_p[29] << 26) | (mask_p[28] << 24)
398 | (mask_p[27] << 22) | (mask_p[26] << 20)
399 | (mask_p[25] << 18) | (mask_p[24] << 16)
400 | (mask_p[23] << 14) | (mask_p[22] << 12)
401 | (mask_p[21] << 10) | (mask_p[20] << 8)
402 | (mask_p[19] << 6) | (mask_p[18] << 4)
403 | (mask_p[17] << 2) | (mask_p[16] << 0);
404 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
405 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
406
407 tmp_mask = (mask_p[45] << 28)
408 | (mask_p[44] << 26) | (mask_p[43] << 24)
409 | (mask_p[42] << 22) | (mask_p[41] << 20)
410 | (mask_p[40] << 18) | (mask_p[39] << 16)
411 | (mask_p[38] << 14) | (mask_p[37] << 12)
412 | (mask_p[36] << 10) | (mask_p[35] << 8)
413 | (mask_p[34] << 6) | (mask_p[33] << 4)
414 | (mask_p[32] << 2) | (mask_p[31] << 0);
415 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
416 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
417
418 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
419 | (mask_p[59] << 26) | (mask_p[58] << 24)
420 | (mask_p[57] << 22) | (mask_p[56] << 20)
421 | (mask_p[55] << 18) | (mask_p[54] << 16)
422 | (mask_p[53] << 14) | (mask_p[52] << 12)
423 | (mask_p[51] << 10) | (mask_p[50] << 8)
424 | (mask_p[49] << 6) | (mask_p[48] << 4)
425 | (mask_p[47] << 2) | (mask_p[46] << 0);
426 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
427 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
171} 428}
172 429
173static void 430/* All code below is for non single-chip solutions */
174ath9k_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32, 431
175 u32 numBits, u32 firstBit, 432/**
176 u32 column) 433 * ath9k_phy_modify_rx_buffer() - perform analog swizzling of parameters
434 * @rfbuf:
435 * @reg32:
436 * @numBits:
437 * @firstBit:
438 * @column:
439 *
440 * Performs analog "swizzling" of parameters into their location.
441 * Used on external AR2133/AR5133 radios.
442 */
443static void ath9k_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
444 u32 numBits, u32 firstBit,
445 u32 column)
177{ 446{
178 u32 tmp32, mask, arrayEntry, lastBit; 447 u32 tmp32, mask, arrayEntry, lastBit;
179 int32_t bitPosition, bitsLeft; 448 int32_t bitPosition, bitsLeft;
@@ -197,26 +466,466 @@ ath9k_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
197 } 466 }
198} 467}
199 468
200bool 469/*
201ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan, 470 * Fix on 2.4 GHz band for orientation sensitivity issue by increasing
202 u16 modesIndex) 471 * rf_pwd_icsyndiv.
472 *
473 * Theoretical Rules:
474 * if 2 GHz band
475 * if forceBiasAuto
476 * if synth_freq < 2412
477 * bias = 0
478 * else if 2412 <= synth_freq <= 2422
479 * bias = 1
480 * else // synth_freq > 2422
481 * bias = 2
482 * else if forceBias > 0
483 * bias = forceBias & 7
484 * else
485 * no change, use value from ini file
486 * else
487 * no change, invalid band
488 *
489 * 1st Mod:
490 * 2422 also uses value of 2
491 * <approved>
492 *
493 * 2nd Mod:
494 * Less than 2412 uses value of 0, 2412 and above uses value of 2
495 */
496static void ath9k_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
497{
498 struct ath_common *common = ath9k_hw_common(ah);
499 u32 tmp_reg;
500 int reg_writes = 0;
501 u32 new_bias = 0;
502
503 if (!AR_SREV_5416(ah) || synth_freq >= 3000) {
504 return;
505 }
506
507 BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
508
509 if (synth_freq < 2412)
510 new_bias = 0;
511 else if (synth_freq < 2422)
512 new_bias = 1;
513 else
514 new_bias = 2;
515
516 /* pre-reverse this field */
517 tmp_reg = ath9k_hw_reverse_bits(new_bias, 3);
518
519 ath_print(common, ATH_DBG_CONFIG,
520 "Force rf_pwd_icsyndiv to %1d on %4d\n",
521 new_bias, synth_freq);
522
523 /* swizzle rf_pwd_icsyndiv */
524 ath9k_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3);
525
526 /* write Bank 6 with new params */
527 REG_WRITE_RF_ARRAY(&ah->iniBank6, ah->analogBank6Data, reg_writes);
528}
529
530/**
531 * ath9k_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios
532 * @ah: atheros hardware stucture
533 * @chan:
534 *
535 * For the external AR2133/AR5133 radios, takes the MHz channel value and set
536 * the channel value. Assumes writes enabled to analog bus and bank6 register
537 * cache in ah->analogBank6Data.
538 */
539int ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
540{
541 struct ath_common *common = ath9k_hw_common(ah);
542 u32 channelSel = 0;
543 u32 bModeSynth = 0;
544 u32 aModeRefSel = 0;
545 u32 reg32 = 0;
546 u16 freq;
547 struct chan_centers centers;
548
549 ath9k_hw_get_channel_centers(ah, chan, &centers);
550 freq = centers.synth_center;
551
552 if (freq < 4800) {
553 u32 txctl;
554
555 if (((freq - 2192) % 5) == 0) {
556 channelSel = ((freq - 672) * 2 - 3040) / 10;
557 bModeSynth = 0;
558 } else if (((freq - 2224) % 5) == 0) {
559 channelSel = ((freq - 704) * 2 - 3040) / 10;
560 bModeSynth = 1;
561 } else {
562 ath_print(common, ATH_DBG_FATAL,
563 "Invalid channel %u MHz\n", freq);
564 return -EINVAL;
565 }
566
567 channelSel = (channelSel << 2) & 0xff;
568 channelSel = ath9k_hw_reverse_bits(channelSel, 8);
569
570 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
571 if (freq == 2484) {
572
573 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
574 txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
575 } else {
576 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
577 txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
578 }
579
580 } else if ((freq % 20) == 0 && freq >= 5120) {
581 channelSel =
582 ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
583 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
584 } else if ((freq % 10) == 0) {
585 channelSel =
586 ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
587 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
588 aModeRefSel = ath9k_hw_reverse_bits(2, 2);
589 else
590 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
591 } else if ((freq % 5) == 0) {
592 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
593 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
594 } else {
595 ath_print(common, ATH_DBG_FATAL,
596 "Invalid channel %u MHz\n", freq);
597 return -EINVAL;
598 }
599
600 ath9k_hw_force_bias(ah, freq);
601
602 reg32 =
603 (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
604 (1 << 5) | 0x1;
605
606 REG_WRITE(ah, AR_PHY(0x37), reg32);
607
608 ah->curchan = chan;
609 ah->curchan_rad_index = -1;
610
611 return 0;
612}
613
614/**
615 * ath9k_hw_spur_mitigate - convert baseband spur frequency for external radios
616 * @ah: atheros hardware structure
617 * @chan:
618 *
619 * For non single-chip solutions. Converts to baseband spur frequency given the
620 * input channel frequency and compute register settings below.
621 */
622void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
623{
624 int bb_spur = AR_NO_SPUR;
625 int bin, cur_bin;
626 int spur_freq_sd;
627 int spur_delta_phase;
628 int denominator;
629 int upper, lower, cur_vit_mask;
630 int tmp, new;
631 int i;
632 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
633 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
634 };
635 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
636 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
637 };
638 int inc[4] = { 0, 100, 0, 0 };
639
640 int8_t mask_m[123];
641 int8_t mask_p[123];
642 int8_t mask_amt;
643 int tmp_mask;
644 int cur_bb_spur;
645 bool is2GHz = IS_CHAN_2GHZ(chan);
646
647 memset(&mask_m, 0, sizeof(int8_t) * 123);
648 memset(&mask_p, 0, sizeof(int8_t) * 123);
649
650 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
651 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
652 if (AR_NO_SPUR == cur_bb_spur)
653 break;
654 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
655 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
656 bb_spur = cur_bb_spur;
657 break;
658 }
659 }
660
661 if (AR_NO_SPUR == bb_spur)
662 return;
663
664 bin = bb_spur * 32;
665
666 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
667 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
668 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
669 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
670 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
671
672 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
673
674 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
675 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
676 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
677 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
678 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
679 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
680
681 spur_delta_phase = ((bb_spur * 524288) / 100) &
682 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
683
684 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
685 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
686
687 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
688 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
689 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
690 REG_WRITE(ah, AR_PHY_TIMING11, new);
691
692 cur_bin = -6000;
693 upper = bin + 100;
694 lower = bin - 100;
695
696 for (i = 0; i < 4; i++) {
697 int pilot_mask = 0;
698 int chan_mask = 0;
699 int bp = 0;
700 for (bp = 0; bp < 30; bp++) {
701 if ((cur_bin > lower) && (cur_bin < upper)) {
702 pilot_mask = pilot_mask | 0x1 << bp;
703 chan_mask = chan_mask | 0x1 << bp;
704 }
705 cur_bin += 100;
706 }
707 cur_bin += inc[i];
708 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
709 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
710 }
711
712 cur_vit_mask = 6100;
713 upper = bin + 120;
714 lower = bin - 120;
715
716 for (i = 0; i < 123; i++) {
717 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
718
719 /* workaround for gcc bug #37014 */
720 volatile int tmp_v = abs(cur_vit_mask - bin);
721
722 if (tmp_v < 75)
723 mask_amt = 1;
724 else
725 mask_amt = 0;
726 if (cur_vit_mask < 0)
727 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
728 else
729 mask_p[cur_vit_mask / 100] = mask_amt;
730 }
731 cur_vit_mask -= 100;
732 }
733
734 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
735 | (mask_m[48] << 26) | (mask_m[49] << 24)
736 | (mask_m[50] << 22) | (mask_m[51] << 20)
737 | (mask_m[52] << 18) | (mask_m[53] << 16)
738 | (mask_m[54] << 14) | (mask_m[55] << 12)
739 | (mask_m[56] << 10) | (mask_m[57] << 8)
740 | (mask_m[58] << 6) | (mask_m[59] << 4)
741 | (mask_m[60] << 2) | (mask_m[61] << 0);
742 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
743 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
744
745 tmp_mask = (mask_m[31] << 28)
746 | (mask_m[32] << 26) | (mask_m[33] << 24)
747 | (mask_m[34] << 22) | (mask_m[35] << 20)
748 | (mask_m[36] << 18) | (mask_m[37] << 16)
749 | (mask_m[48] << 14) | (mask_m[39] << 12)
750 | (mask_m[40] << 10) | (mask_m[41] << 8)
751 | (mask_m[42] << 6) | (mask_m[43] << 4)
752 | (mask_m[44] << 2) | (mask_m[45] << 0);
753 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
754 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
755
756 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
757 | (mask_m[18] << 26) | (mask_m[18] << 24)
758 | (mask_m[20] << 22) | (mask_m[20] << 20)
759 | (mask_m[22] << 18) | (mask_m[22] << 16)
760 | (mask_m[24] << 14) | (mask_m[24] << 12)
761 | (mask_m[25] << 10) | (mask_m[26] << 8)
762 | (mask_m[27] << 6) | (mask_m[28] << 4)
763 | (mask_m[29] << 2) | (mask_m[30] << 0);
764 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
765 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
766
767 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
768 | (mask_m[2] << 26) | (mask_m[3] << 24)
769 | (mask_m[4] << 22) | (mask_m[5] << 20)
770 | (mask_m[6] << 18) | (mask_m[7] << 16)
771 | (mask_m[8] << 14) | (mask_m[9] << 12)
772 | (mask_m[10] << 10) | (mask_m[11] << 8)
773 | (mask_m[12] << 6) | (mask_m[13] << 4)
774 | (mask_m[14] << 2) | (mask_m[15] << 0);
775 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
776 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
777
778 tmp_mask = (mask_p[15] << 28)
779 | (mask_p[14] << 26) | (mask_p[13] << 24)
780 | (mask_p[12] << 22) | (mask_p[11] << 20)
781 | (mask_p[10] << 18) | (mask_p[9] << 16)
782 | (mask_p[8] << 14) | (mask_p[7] << 12)
783 | (mask_p[6] << 10) | (mask_p[5] << 8)
784 | (mask_p[4] << 6) | (mask_p[3] << 4)
785 | (mask_p[2] << 2) | (mask_p[1] << 0);
786 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
787 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
788
789 tmp_mask = (mask_p[30] << 28)
790 | (mask_p[29] << 26) | (mask_p[28] << 24)
791 | (mask_p[27] << 22) | (mask_p[26] << 20)
792 | (mask_p[25] << 18) | (mask_p[24] << 16)
793 | (mask_p[23] << 14) | (mask_p[22] << 12)
794 | (mask_p[21] << 10) | (mask_p[20] << 8)
795 | (mask_p[19] << 6) | (mask_p[18] << 4)
796 | (mask_p[17] << 2) | (mask_p[16] << 0);
797 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
798 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
799
800 tmp_mask = (mask_p[45] << 28)
801 | (mask_p[44] << 26) | (mask_p[43] << 24)
802 | (mask_p[42] << 22) | (mask_p[41] << 20)
803 | (mask_p[40] << 18) | (mask_p[39] << 16)
804 | (mask_p[38] << 14) | (mask_p[37] << 12)
805 | (mask_p[36] << 10) | (mask_p[35] << 8)
806 | (mask_p[34] << 6) | (mask_p[33] << 4)
807 | (mask_p[32] << 2) | (mask_p[31] << 0);
808 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
809 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
810
811 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
812 | (mask_p[59] << 26) | (mask_p[58] << 24)
813 | (mask_p[57] << 22) | (mask_p[56] << 20)
814 | (mask_p[55] << 18) | (mask_p[54] << 16)
815 | (mask_p[53] << 14) | (mask_p[52] << 12)
816 | (mask_p[51] << 10) | (mask_p[50] << 8)
817 | (mask_p[49] << 6) | (mask_p[48] << 4)
818 | (mask_p[47] << 2) | (mask_p[46] << 0);
819 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
820 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
821}
822
823/**
824 * ath9k_hw_rf_alloc_ext_banks - allocates banks for external radio programming
825 * @ah: atheros hardware structure
826 *
827 * Only required for older devices with external AR2133/AR5133 radios.
828 */
829int ath9k_hw_rf_alloc_ext_banks(struct ath_hw *ah)
830{
831#define ATH_ALLOC_BANK(bank, size) do { \
832 bank = kzalloc((sizeof(u32) * size), GFP_KERNEL); \
833 if (!bank) { \
834 ath_print(common, ATH_DBG_FATAL, \
835 "Cannot allocate RF banks\n"); \
836 return -ENOMEM; \
837 } \
838 } while (0);
839
840 struct ath_common *common = ath9k_hw_common(ah);
841
842 BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
843
844 ATH_ALLOC_BANK(ah->analogBank0Data, ah->iniBank0.ia_rows);
845 ATH_ALLOC_BANK(ah->analogBank1Data, ah->iniBank1.ia_rows);
846 ATH_ALLOC_BANK(ah->analogBank2Data, ah->iniBank2.ia_rows);
847 ATH_ALLOC_BANK(ah->analogBank3Data, ah->iniBank3.ia_rows);
848 ATH_ALLOC_BANK(ah->analogBank6Data, ah->iniBank6.ia_rows);
849 ATH_ALLOC_BANK(ah->analogBank6TPCData, ah->iniBank6TPC.ia_rows);
850 ATH_ALLOC_BANK(ah->analogBank7Data, ah->iniBank7.ia_rows);
851 ATH_ALLOC_BANK(ah->addac5416_21,
852 ah->iniAddac.ia_rows * ah->iniAddac.ia_columns);
853 ATH_ALLOC_BANK(ah->bank6Temp, ah->iniBank6.ia_rows);
854
855 return 0;
856#undef ATH_ALLOC_BANK
857}
858
859
860/**
861 * ath9k_hw_rf_free_ext_banks - Free memory for analog bank scratch buffers
862 * @ah: atheros hardware struture
863 * For the external AR2133/AR5133 radios banks.
864 */
865void
866ath9k_hw_rf_free_ext_banks(struct ath_hw *ah)
867{
868#define ATH_FREE_BANK(bank) do { \
869 kfree(bank); \
870 bank = NULL; \
871 } while (0);
872
873 BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
874
875 ATH_FREE_BANK(ah->analogBank0Data);
876 ATH_FREE_BANK(ah->analogBank1Data);
877 ATH_FREE_BANK(ah->analogBank2Data);
878 ATH_FREE_BANK(ah->analogBank3Data);
879 ATH_FREE_BANK(ah->analogBank6Data);
880 ATH_FREE_BANK(ah->analogBank6TPCData);
881 ATH_FREE_BANK(ah->analogBank7Data);
882 ATH_FREE_BANK(ah->addac5416_21);
883 ATH_FREE_BANK(ah->bank6Temp);
884
885#undef ATH_FREE_BANK
886}
887
888/* *
889 * ath9k_hw_set_rf_regs - programs rf registers based on EEPROM
890 * @ah: atheros hardware structure
891 * @chan:
892 * @modesIndex:
893 *
894 * Used for the external AR2133/AR5133 radios.
895 *
896 * Reads the EEPROM header info from the device structure and programs
897 * all rf registers. This routine requires access to the analog
898 * rf device. This is not required for single-chip devices.
899 */
900bool ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan,
901 u16 modesIndex)
203{ 902{
204 u32 eepMinorRev; 903 u32 eepMinorRev;
205 u32 ob5GHz = 0, db5GHz = 0; 904 u32 ob5GHz = 0, db5GHz = 0;
206 u32 ob2GHz = 0, db2GHz = 0; 905 u32 ob2GHz = 0, db2GHz = 0;
207 int regWrites = 0; 906 int regWrites = 0;
208 907
908 /*
909 * Software does not need to program bank data
910 * for single chip devices, that is AR9280 or anything
911 * after that.
912 */
209 if (AR_SREV_9280_10_OR_LATER(ah)) 913 if (AR_SREV_9280_10_OR_LATER(ah))
210 return true; 914 return true;
211 915
916 /* Setup rf parameters */
212 eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV); 917 eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
213 918
919 /* Setup Bank 0 Write */
214 RF_BANK_SETUP(ah->analogBank0Data, &ah->iniBank0, 1); 920 RF_BANK_SETUP(ah->analogBank0Data, &ah->iniBank0, 1);
215 921
922 /* Setup Bank 1 Write */
216 RF_BANK_SETUP(ah->analogBank1Data, &ah->iniBank1, 1); 923 RF_BANK_SETUP(ah->analogBank1Data, &ah->iniBank1, 1);
217 924
925 /* Setup Bank 2 Write */
218 RF_BANK_SETUP(ah->analogBank2Data, &ah->iniBank2, 1); 926 RF_BANK_SETUP(ah->analogBank2Data, &ah->iniBank2, 1);
219 927
928 /* Setup Bank 6 Write */
220 RF_BANK_SETUP(ah->analogBank3Data, &ah->iniBank3, 929 RF_BANK_SETUP(ah->analogBank3Data, &ah->iniBank3,
221 modesIndex); 930 modesIndex);
222 { 931 {
@@ -227,6 +936,7 @@ ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan,
227 } 936 }
228 } 937 }
229 938
939 /* Only the 5 or 2 GHz OB/DB need to be set for a mode */
230 if (eepMinorRev >= 2) { 940 if (eepMinorRev >= 2) {
231 if (IS_CHAN_2GHZ(chan)) { 941 if (IS_CHAN_2GHZ(chan)) {
232 ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2); 942 ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2);
@@ -245,8 +955,10 @@ ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan,
245 } 955 }
246 } 956 }
247 957
958 /* Setup Bank 7 Setup */
248 RF_BANK_SETUP(ah->analogBank7Data, &ah->iniBank7, 1); 959 RF_BANK_SETUP(ah->analogBank7Data, &ah->iniBank7, 1);
249 960
961 /* Write Analog registers */
250 REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data, 962 REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
251 regWrites); 963 regWrites);
252 REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data, 964 REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data,
@@ -262,137 +974,3 @@ ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan,
262 974
263 return true; 975 return true;
264} 976}
265
266void
267ath9k_hw_rf_free(struct ath_hw *ah)
268{
269#define ATH_FREE_BANK(bank) do { \
270 kfree(bank); \
271 bank = NULL; \
272 } while (0);
273
274 ATH_FREE_BANK(ah->analogBank0Data);
275 ATH_FREE_BANK(ah->analogBank1Data);
276 ATH_FREE_BANK(ah->analogBank2Data);
277 ATH_FREE_BANK(ah->analogBank3Data);
278 ATH_FREE_BANK(ah->analogBank6Data);
279 ATH_FREE_BANK(ah->analogBank6TPCData);
280 ATH_FREE_BANK(ah->analogBank7Data);
281 ATH_FREE_BANK(ah->addac5416_21);
282 ATH_FREE_BANK(ah->bank6Temp);
283#undef ATH_FREE_BANK
284}
285
286bool ath9k_hw_init_rf(struct ath_hw *ah, int *status)
287{
288 if (!AR_SREV_9280_10_OR_LATER(ah)) {
289 ah->analogBank0Data =
290 kzalloc((sizeof(u32) *
291 ah->iniBank0.ia_rows), GFP_KERNEL);
292 ah->analogBank1Data =
293 kzalloc((sizeof(u32) *
294 ah->iniBank1.ia_rows), GFP_KERNEL);
295 ah->analogBank2Data =
296 kzalloc((sizeof(u32) *
297 ah->iniBank2.ia_rows), GFP_KERNEL);
298 ah->analogBank3Data =
299 kzalloc((sizeof(u32) *
300 ah->iniBank3.ia_rows), GFP_KERNEL);
301 ah->analogBank6Data =
302 kzalloc((sizeof(u32) *
303 ah->iniBank6.ia_rows), GFP_KERNEL);
304 ah->analogBank6TPCData =
305 kzalloc((sizeof(u32) *
306 ah->iniBank6TPC.ia_rows), GFP_KERNEL);
307 ah->analogBank7Data =
308 kzalloc((sizeof(u32) *
309 ah->iniBank7.ia_rows), GFP_KERNEL);
310
311 if (ah->analogBank0Data == NULL
312 || ah->analogBank1Data == NULL
313 || ah->analogBank2Data == NULL
314 || ah->analogBank3Data == NULL
315 || ah->analogBank6Data == NULL
316 || ah->analogBank6TPCData == NULL
317 || ah->analogBank7Data == NULL) {
318 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
319 "Cannot allocate RF banks\n");
320 *status = -ENOMEM;
321 return false;
322 }
323
324 ah->addac5416_21 =
325 kzalloc((sizeof(u32) *
326 ah->iniAddac.ia_rows *
327 ah->iniAddac.ia_columns), GFP_KERNEL);
328 if (ah->addac5416_21 == NULL) {
329 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
330 "Cannot allocate addac5416_21\n");
331 *status = -ENOMEM;
332 return false;
333 }
334
335 ah->bank6Temp =
336 kzalloc((sizeof(u32) *
337 ah->iniBank6.ia_rows), GFP_KERNEL);
338 if (ah->bank6Temp == NULL) {
339 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
340 "Cannot allocate bank6Temp\n");
341 *status = -ENOMEM;
342 return false;
343 }
344 }
345
346 return true;
347}
348
349void
350ath9k_hw_decrease_chain_power(struct ath_hw *ah, struct ath9k_channel *chan)
351{
352 int i, regWrites = 0;
353 u32 bank6SelMask;
354 u32 *bank6Temp = ah->bank6Temp;
355
356 switch (ah->config.diversity_control) {
357 case ATH9K_ANT_FIXED_A:
358 bank6SelMask =
359 (ah->config.antenna_switch_swap & ANTSWAP_AB) ?
360 REDUCE_CHAIN_0 : REDUCE_CHAIN_1;
361 break;
362 case ATH9K_ANT_FIXED_B:
363 bank6SelMask =
364 (ah->config.antenna_switch_swap & ANTSWAP_AB) ?
365 REDUCE_CHAIN_1 : REDUCE_CHAIN_0;
366 break;
367 case ATH9K_ANT_VARIABLE:
368 return;
369 break;
370 default:
371 return;
372 break;
373 }
374
375 for (i = 0; i < ah->iniBank6.ia_rows; i++)
376 bank6Temp[i] = ah->analogBank6Data[i];
377
378 REG_WRITE(ah, AR_PHY_BASE + 0xD8, bank6SelMask);
379
380 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 189, 0);
381 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 190, 0);
382 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 191, 0);
383 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 192, 0);
384 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 193, 0);
385 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 222, 0);
386 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 245, 0);
387 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 246, 0);
388 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 247, 0);
389
390 REG_WRITE_RF_ARRAY(&ah->iniBank6, bank6Temp, regWrites);
391
392 REG_WRITE(ah, AR_PHY_BASE + 0xD8, 0x00000053);
393#ifdef ALTER_SWITCH
394 REG_WRITE(ah, PHY_SWITCH_CHAIN_0,
395 (REG_READ(ah, PHY_SWITCH_CHAIN_0) & ~0x38)
396 | ((REG_READ(ah, PHY_SWITCH_CHAIN_0) >> 3) & 0x38));
397#endif
398}
diff --git a/drivers/net/wireless/ath/ath9k/phy.h b/drivers/net/wireless/ath/ath9k/phy.h
index dfda6f444648..31de27dc0c4a 100644
--- a/drivers/net/wireless/ath/ath9k/phy.h
+++ b/drivers/net/wireless/ath/ath9k/phy.h
@@ -17,20 +17,23 @@
17#ifndef PHY_H 17#ifndef PHY_H
18#define PHY_H 18#define PHY_H
19 19
20void ath9k_hw_ar9280_set_channel(struct ath_hw *ah, 20/* Common between single chip and non single-chip solutions */
21 struct ath9k_channel 21void ath9k_hw_write_regs(struct ath_hw *ah, u32 freqIndex, int regWrites);
22 *chan); 22
23bool ath9k_hw_set_channel(struct ath_hw *ah, 23/* Single chip radio settings */
24 struct ath9k_channel *chan); 24int ath9k_hw_ar9280_set_channel(struct ath_hw *ah, struct ath9k_channel *chan);
25void ath9k_hw_write_regs(struct ath_hw *ah, u32 modesIndex, 25void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
26 u32 freqIndex, int regWrites); 26
27/* Routines below are for non single-chip solutions */
28int ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan);
29void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
30
31int ath9k_hw_rf_alloc_ext_banks(struct ath_hw *ah);
32void ath9k_hw_rf_free_ext_banks(struct ath_hw *ah);
33
27bool ath9k_hw_set_rf_regs(struct ath_hw *ah, 34bool ath9k_hw_set_rf_regs(struct ath_hw *ah,
28 struct ath9k_channel *chan, 35 struct ath9k_channel *chan,
29 u16 modesIndex); 36 u16 modesIndex);
30void ath9k_hw_decrease_chain_power(struct ath_hw *ah,
31 struct ath9k_channel *chan);
32bool ath9k_hw_init_rf(struct ath_hw *ah,
33 int *status);
34 37
35#define AR_PHY_BASE 0x9800 38#define AR_PHY_BASE 0x9800
36#define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2)) 39#define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2))
@@ -45,6 +48,7 @@ bool ath9k_hw_init_rf(struct ath_hw *ah,
45#define AR_PHY_FC_DYN2040_EN 0x00000004 48#define AR_PHY_FC_DYN2040_EN 0x00000004
46#define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008 49#define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008
47#define AR_PHY_FC_DYN2040_PRI_CH 0x00000010 50#define AR_PHY_FC_DYN2040_PRI_CH 0x00000010
51/* For 25 MHz channel spacing -- not used but supported by hw */
48#define AR_PHY_FC_DYN2040_EXT_CH 0x00000020 52#define AR_PHY_FC_DYN2040_EXT_CH 0x00000020
49#define AR_PHY_FC_HT_EN 0x00000040 53#define AR_PHY_FC_HT_EN 0x00000040
50#define AR_PHY_FC_SHORT_GI_40 0x00000080 54#define AR_PHY_FC_SHORT_GI_40 0x00000080
@@ -185,8 +189,20 @@ bool ath9k_hw_init_rf(struct ath_hw *ah,
185#define AR_PHY_PLL_CTL_44_2133 0xeb 189#define AR_PHY_PLL_CTL_44_2133 0xeb
186#define AR_PHY_PLL_CTL_40_2133 0xea 190#define AR_PHY_PLL_CTL_40_2133 0xea
187 191
188#define AR_PHY_SPECTRAL_SCAN 0x9912 192#define AR_PHY_SPECTRAL_SCAN 0x9910 /* AR9280 spectral scan configuration register */
189#define AR_PHY_SPECTRAL_SCAN_ENABLE 0x1 193#define AR_PHY_SPECTRAL_SCAN_ENABLE 0x1
194#define AR_PHY_SPECTRAL_SCAN_ENA 0x00000001 /* Enable spectral scan, reg 68, bit 0 */
195#define AR_PHY_SPECTRAL_SCAN_ENA_S 0 /* Enable spectral scan, reg 68, bit 0 */
196#define AR_PHY_SPECTRAL_SCAN_ACTIVE 0x00000002 /* Activate spectral scan reg 68, bit 1*/
197#define AR_PHY_SPECTRAL_SCAN_ACTIVE_S 1 /* Activate spectral scan reg 68, bit 1*/
198#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD 0x000000F0 /* Interval for FFT reports, reg 68, bits 4-7*/
199#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S 4
200#define AR_PHY_SPECTRAL_SCAN_PERIOD 0x0000FF00 /* Interval for FFT reports, reg 68, bits 8-15*/
201#define AR_PHY_SPECTRAL_SCAN_PERIOD_S 8
202#define AR_PHY_SPECTRAL_SCAN_COUNT 0x00FF0000 /* Number of reports, reg 68, bits 16-23*/
203#define AR_PHY_SPECTRAL_SCAN_COUNT_S 16
204#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x01000000 /* Short repeat, reg 68, bit 24*/
205#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 24 /* Short repeat, reg 68, bit 24*/
190 206
191#define AR_PHY_RX_DELAY 0x9914 207#define AR_PHY_RX_DELAY 0x9914
192#define AR_PHY_SEARCH_START_DELAY 0x9918 208#define AR_PHY_SEARCH_START_DELAY 0x9918
diff --git a/drivers/net/wireless/ath/ath9k/rc.c b/drivers/net/wireless/ath/ath9k/rc.c
index 1895d63aad0a..1d96777b4cd2 100644
--- a/drivers/net/wireless/ath/ath9k/rc.c
+++ b/drivers/net/wireless/ath/ath9k/rc.c
@@ -425,7 +425,7 @@ static void ath_rc_init_valid_txmask(struct ath_rate_priv *ath_rc_priv)
425static inline void ath_rc_set_valid_txmask(struct ath_rate_priv *ath_rc_priv, 425static inline void ath_rc_set_valid_txmask(struct ath_rate_priv *ath_rc_priv,
426 u8 index, int valid_tx_rate) 426 u8 index, int valid_tx_rate)
427{ 427{
428 ASSERT(index <= ath_rc_priv->rate_table_size); 428 BUG_ON(index > ath_rc_priv->rate_table_size);
429 ath_rc_priv->valid_rate_index[index] = valid_tx_rate ? 1 : 0; 429 ath_rc_priv->valid_rate_index[index] = valid_tx_rate ? 1 : 0;
430} 430}
431 431
@@ -859,12 +859,12 @@ static void ath_get_rate(void *priv, struct ieee80211_sta *sta, void *priv_sta,
859static bool ath_rc_update_per(struct ath_softc *sc, 859static bool ath_rc_update_per(struct ath_softc *sc,
860 const struct ath_rate_table *rate_table, 860 const struct ath_rate_table *rate_table,
861 struct ath_rate_priv *ath_rc_priv, 861 struct ath_rate_priv *ath_rc_priv,
862 struct ath_tx_info_priv *tx_info_priv, 862 struct ieee80211_tx_info *tx_info,
863 int tx_rate, int xretries, int retries, 863 int tx_rate, int xretries, int retries,
864 u32 now_msec) 864 u32 now_msec)
865{ 865{
866 bool state_change = false; 866 bool state_change = false;
867 int count; 867 int count, n_bad_frames;
868 u8 last_per; 868 u8 last_per;
869 static u32 nretry_to_per_lookup[10] = { 869 static u32 nretry_to_per_lookup[10] = {
870 100 * 0 / 1, 870 100 * 0 / 1,
@@ -880,6 +880,7 @@ static bool ath_rc_update_per(struct ath_softc *sc,
880 }; 880 };
881 881
882 last_per = ath_rc_priv->per[tx_rate]; 882 last_per = ath_rc_priv->per[tx_rate];
883 n_bad_frames = tx_info->status.ampdu_len - tx_info->status.ampdu_ack_len;
883 884
884 if (xretries) { 885 if (xretries) {
885 if (xretries == 1) { 886 if (xretries == 1) {
@@ -907,7 +908,7 @@ static bool ath_rc_update_per(struct ath_softc *sc,
907 if (retries >= count) 908 if (retries >= count)
908 retries = count - 1; 909 retries = count - 1;
909 910
910 if (tx_info_priv->n_bad_frames) { 911 if (n_bad_frames) {
911 /* new_PER = 7/8*old_PER + 1/8*(currentPER) 912 /* new_PER = 7/8*old_PER + 1/8*(currentPER)
912 * Assuming that n_frames is not 0. The current PER 913 * Assuming that n_frames is not 0. The current PER
913 * from the retries is 100 * retries / (retries+1), 914 * from the retries is 100 * retries / (retries+1),
@@ -920,14 +921,14 @@ static bool ath_rc_update_per(struct ath_softc *sc,
920 * the above PER. The expression below is a 921 * the above PER. The expression below is a
921 * simplified version of the sum of these two terms. 922 * simplified version of the sum of these two terms.
922 */ 923 */
923 if (tx_info_priv->n_frames > 0) { 924 if (tx_info->status.ampdu_len > 0) {
924 int n_frames, n_bad_frames; 925 int n_frames, n_bad_tries;
925 u8 cur_per, new_per; 926 u8 cur_per, new_per;
926 927
927 n_bad_frames = retries * tx_info_priv->n_frames + 928 n_bad_tries = retries * tx_info->status.ampdu_len +
928 tx_info_priv->n_bad_frames; 929 n_bad_frames;
929 n_frames = tx_info_priv->n_frames * (retries + 1); 930 n_frames = tx_info->status.ampdu_len * (retries + 1);
930 cur_per = (100 * n_bad_frames / n_frames) >> 3; 931 cur_per = (100 * n_bad_tries / n_frames) >> 3;
931 new_per = (u8)(last_per - (last_per >> 3) + cur_per); 932 new_per = (u8)(last_per - (last_per >> 3) + cur_per);
932 ath_rc_priv->per[tx_rate] = new_per; 933 ath_rc_priv->per[tx_rate] = new_per;
933 } 934 }
@@ -943,8 +944,7 @@ static bool ath_rc_update_per(struct ath_softc *sc,
943 * this was a probe. Otherwise, ignore the probe. 944 * this was a probe. Otherwise, ignore the probe.
944 */ 945 */
945 if (ath_rc_priv->probe_rate && ath_rc_priv->probe_rate == tx_rate) { 946 if (ath_rc_priv->probe_rate && ath_rc_priv->probe_rate == tx_rate) {
946 if (retries > 0 || 2 * tx_info_priv->n_bad_frames > 947 if (retries > 0 || 2 * n_bad_frames > tx_info->status.ampdu_len) {
947 tx_info_priv->n_frames) {
948 /* 948 /*
949 * Since we probed with just a single attempt, 949 * Since we probed with just a single attempt,
950 * any retries means the probe failed. Also, 950 * any retries means the probe failed. Also,
@@ -1003,7 +1003,7 @@ static bool ath_rc_update_per(struct ath_softc *sc,
1003 1003
1004static void ath_rc_update_ht(struct ath_softc *sc, 1004static void ath_rc_update_ht(struct ath_softc *sc,
1005 struct ath_rate_priv *ath_rc_priv, 1005 struct ath_rate_priv *ath_rc_priv,
1006 struct ath_tx_info_priv *tx_info_priv, 1006 struct ieee80211_tx_info *tx_info,
1007 int tx_rate, int xretries, int retries) 1007 int tx_rate, int xretries, int retries)
1008{ 1008{
1009 u32 now_msec = jiffies_to_msecs(jiffies); 1009 u32 now_msec = jiffies_to_msecs(jiffies);
@@ -1020,7 +1020,7 @@ static void ath_rc_update_ht(struct ath_softc *sc,
1020 1020
1021 /* Update PER first */ 1021 /* Update PER first */
1022 state_change = ath_rc_update_per(sc, rate_table, ath_rc_priv, 1022 state_change = ath_rc_update_per(sc, rate_table, ath_rc_priv,
1023 tx_info_priv, tx_rate, xretries, 1023 tx_info, tx_rate, xretries,
1024 retries, now_msec); 1024 retries, now_msec);
1025 1025
1026 /* 1026 /*
@@ -1098,7 +1098,6 @@ static void ath_rc_tx_status(struct ath_softc *sc,
1098 struct ieee80211_tx_info *tx_info, 1098 struct ieee80211_tx_info *tx_info,
1099 int final_ts_idx, int xretries, int long_retry) 1099 int final_ts_idx, int xretries, int long_retry)
1100{ 1100{
1101 struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info);
1102 const struct ath_rate_table *rate_table; 1101 const struct ath_rate_table *rate_table;
1103 struct ieee80211_tx_rate *rates = tx_info->status.rates; 1102 struct ieee80211_tx_rate *rates = tx_info->status.rates;
1104 u8 flags; 1103 u8 flags;
@@ -1124,9 +1123,8 @@ static void ath_rc_tx_status(struct ath_softc *sc,
1124 return; 1123 return;
1125 1124
1126 rix = ath_rc_get_rateindex(rate_table, &rates[i]); 1125 rix = ath_rc_get_rateindex(rate_table, &rates[i]);
1127 ath_rc_update_ht(sc, ath_rc_priv, 1126 ath_rc_update_ht(sc, ath_rc_priv, tx_info,
1128 tx_info_priv, rix, 1127 rix, xretries ? 1 : 2,
1129 xretries ? 1 : 2,
1130 rates[i].count); 1128 rates[i].count);
1131 } 1129 }
1132 } 1130 }
@@ -1149,8 +1147,7 @@ static void ath_rc_tx_status(struct ath_softc *sc,
1149 return; 1147 return;
1150 1148
1151 rix = ath_rc_get_rateindex(rate_table, &rates[i]); 1149 rix = ath_rc_get_rateindex(rate_table, &rates[i]);
1152 ath_rc_update_ht(sc, ath_rc_priv, tx_info_priv, rix, 1150 ath_rc_update_ht(sc, ath_rc_priv, tx_info, rix, xretries, long_retry);
1153 xretries, long_retry);
1154} 1151}
1155 1152
1156static const 1153static const
@@ -1160,6 +1157,7 @@ struct ath_rate_table *ath_choose_rate_table(struct ath_softc *sc,
1160 bool is_cw_40) 1157 bool is_cw_40)
1161{ 1158{
1162 int mode = 0; 1159 int mode = 0;
1160 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1163 1161
1164 switch(band) { 1162 switch(band) {
1165 case IEEE80211_BAND_2GHZ: 1163 case IEEE80211_BAND_2GHZ:
@@ -1177,13 +1175,14 @@ struct ath_rate_table *ath_choose_rate_table(struct ath_softc *sc,
1177 mode = ATH9K_MODE_11NA_HT40PLUS; 1175 mode = ATH9K_MODE_11NA_HT40PLUS;
1178 break; 1176 break;
1179 default: 1177 default:
1180 DPRINTF(sc, ATH_DBG_CONFIG, "Invalid band\n"); 1178 ath_print(common, ATH_DBG_CONFIG, "Invalid band\n");
1181 return NULL; 1179 return NULL;
1182 } 1180 }
1183 1181
1184 BUG_ON(mode >= ATH9K_MODE_MAX); 1182 BUG_ON(mode >= ATH9K_MODE_MAX);
1185 1183
1186 DPRINTF(sc, ATH_DBG_CONFIG, "Choosing rate table for mode: %d\n", mode); 1184 ath_print(common, ATH_DBG_CONFIG,
1185 "Choosing rate table for mode: %d\n", mode);
1187 return sc->hw_rate_table[mode]; 1186 return sc->hw_rate_table[mode];
1188} 1187}
1189 1188
@@ -1194,11 +1193,13 @@ static void ath_rc_init(struct ath_softc *sc,
1194 const struct ath_rate_table *rate_table) 1193 const struct ath_rate_table *rate_table)
1195{ 1194{
1196 struct ath_rateset *rateset = &ath_rc_priv->neg_rates; 1195 struct ath_rateset *rateset = &ath_rc_priv->neg_rates;
1196 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1197 u8 *ht_mcs = (u8 *)&ath_rc_priv->neg_ht_rates; 1197 u8 *ht_mcs = (u8 *)&ath_rc_priv->neg_ht_rates;
1198 u8 i, j, k, hi = 0, hthi = 0; 1198 u8 i, j, k, hi = 0, hthi = 0;
1199 1199
1200 if (!rate_table) { 1200 if (!rate_table) {
1201 DPRINTF(sc, ATH_DBG_FATAL, "Rate table not initialized\n"); 1201 ath_print(common, ATH_DBG_FATAL,
1202 "Rate table not initialized\n");
1202 return; 1203 return;
1203 } 1204 }
1204 1205
@@ -1239,7 +1240,7 @@ static void ath_rc_init(struct ath_softc *sc,
1239 1240
1240 ath_rc_priv->rate_table_size = hi + 1; 1241 ath_rc_priv->rate_table_size = hi + 1;
1241 ath_rc_priv->rate_max_phy = 0; 1242 ath_rc_priv->rate_max_phy = 0;
1242 ASSERT(ath_rc_priv->rate_table_size <= RATE_TABLE_SIZE); 1243 BUG_ON(ath_rc_priv->rate_table_size > RATE_TABLE_SIZE);
1243 1244
1244 for (i = 0, k = 0; i < WLAN_RC_PHY_MAX; i++) { 1245 for (i = 0, k = 0; i < WLAN_RC_PHY_MAX; i++) {
1245 for (j = 0; j < ath_rc_priv->valid_phy_ratecnt[i]; j++) { 1246 for (j = 0; j < ath_rc_priv->valid_phy_ratecnt[i]; j++) {
@@ -1253,16 +1254,17 @@ static void ath_rc_init(struct ath_softc *sc,
1253 1254
1254 ath_rc_priv->rate_max_phy = ath_rc_priv->valid_phy_rateidx[i][j-1]; 1255 ath_rc_priv->rate_max_phy = ath_rc_priv->valid_phy_rateidx[i][j-1];
1255 } 1256 }
1256 ASSERT(ath_rc_priv->rate_table_size <= RATE_TABLE_SIZE); 1257 BUG_ON(ath_rc_priv->rate_table_size > RATE_TABLE_SIZE);
1257 ASSERT(k <= RATE_TABLE_SIZE); 1258 BUG_ON(k > RATE_TABLE_SIZE);
1258 1259
1259 ath_rc_priv->max_valid_rate = k; 1260 ath_rc_priv->max_valid_rate = k;
1260 ath_rc_sort_validrates(rate_table, ath_rc_priv); 1261 ath_rc_sort_validrates(rate_table, ath_rc_priv);
1261 ath_rc_priv->rate_max_phy = ath_rc_priv->valid_rate_index[k-4]; 1262 ath_rc_priv->rate_max_phy = ath_rc_priv->valid_rate_index[k-4];
1262 sc->cur_rate_table = rate_table; 1263 sc->cur_rate_table = rate_table;
1263 1264
1264 DPRINTF(sc, ATH_DBG_CONFIG, "RC Initialized with capabilities: 0x%x\n", 1265 ath_print(common, ATH_DBG_CONFIG,
1265 ath_rc_priv->ht_cap); 1266 "RC Initialized with capabilities: 0x%x\n",
1267 ath_rc_priv->ht_cap);
1266} 1268}
1267 1269
1268static u8 ath_rc_build_ht_caps(struct ath_softc *sc, struct ieee80211_sta *sta, 1270static u8 ath_rc_build_ht_caps(struct ath_softc *sc, struct ieee80211_sta *sta,
@@ -1296,23 +1298,30 @@ static void ath_tx_status(void *priv, struct ieee80211_supported_band *sband,
1296{ 1298{
1297 struct ath_softc *sc = priv; 1299 struct ath_softc *sc = priv;
1298 struct ath_rate_priv *ath_rc_priv = priv_sta; 1300 struct ath_rate_priv *ath_rc_priv = priv_sta;
1299 struct ath_tx_info_priv *tx_info_priv = NULL;
1300 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1301 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1301 struct ieee80211_hdr *hdr; 1302 struct ieee80211_hdr *hdr;
1302 int final_ts_idx, tx_status = 0, is_underrun = 0; 1303 int final_ts_idx = 0, tx_status = 0, is_underrun = 0;
1304 int long_retry = 0;
1303 __le16 fc; 1305 __le16 fc;
1306 int i;
1304 1307
1305 hdr = (struct ieee80211_hdr *)skb->data; 1308 hdr = (struct ieee80211_hdr *)skb->data;
1306 fc = hdr->frame_control; 1309 fc = hdr->frame_control;
1307 tx_info_priv = ATH_TX_INFO_PRIV(tx_info); 1310 for (i = 0; i < IEEE80211_TX_MAX_RATES; i++) {
1308 final_ts_idx = tx_info_priv->tx.ts_rateindex; 1311 struct ieee80211_tx_rate *rate = &tx_info->status.rates[i];
1312 if (!rate->count)
1313 break;
1314
1315 final_ts_idx = i;
1316 long_retry = rate->count - 1;
1317 }
1309 1318
1310 if (!priv_sta || !ieee80211_is_data(fc) || 1319 if (!priv_sta || !ieee80211_is_data(fc) ||
1311 !tx_info_priv->update_rc) 1320 !(tx_info->pad[0] & ATH_TX_INFO_UPDATE_RC))
1312 goto exit; 1321 return;
1313 1322
1314 if (tx_info_priv->tx.ts_status & ATH9K_TXERR_FILT) 1323 if (tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED)
1315 goto exit; 1324 return;
1316 1325
1317 /* 1326 /*
1318 * If underrun error is seen assume it as an excessive retry only 1327 * If underrun error is seen assume it as an excessive retry only
@@ -1320,20 +1329,17 @@ static void ath_tx_status(void *priv, struct ieee80211_supported_band *sband,
1320 * Adjust the long retry as if the frame was tried hw->max_rate_tries 1329 * Adjust the long retry as if the frame was tried hw->max_rate_tries
1321 * times. This affects how ratectrl updates PER for the failed rate. 1330 * times. This affects how ratectrl updates PER for the failed rate.
1322 */ 1331 */
1323 if (tx_info_priv->tx.ts_flags & 1332 if ((tx_info->pad[0] & ATH_TX_INFO_UNDERRUN) &&
1324 (ATH9K_TX_DATA_UNDERRUN | ATH9K_TX_DELIM_UNDERRUN) && 1333 (sc->sc_ah->tx_trig_level >= ath_rc_priv->tx_triglevel_max)) {
1325 ((sc->sc_ah->tx_trig_level) >= ath_rc_priv->tx_triglevel_max)) {
1326 tx_status = 1; 1334 tx_status = 1;
1327 is_underrun = 1; 1335 is_underrun = 1;
1328 } 1336 }
1329 1337
1330 if ((tx_info_priv->tx.ts_status & ATH9K_TXERR_XRETRY) || 1338 if (tx_info->pad[0] & ATH_TX_INFO_XRETRY)
1331 (tx_info_priv->tx.ts_status & ATH9K_TXERR_FIFO))
1332 tx_status = 1; 1339 tx_status = 1;
1333 1340
1334 ath_rc_tx_status(sc, ath_rc_priv, tx_info, final_ts_idx, tx_status, 1341 ath_rc_tx_status(sc, ath_rc_priv, tx_info, final_ts_idx, tx_status,
1335 (is_underrun) ? sc->hw->max_rate_tries : 1342 (is_underrun) ? sc->hw->max_rate_tries : long_retry);
1336 tx_info_priv->tx.ts_longretry);
1337 1343
1338 /* Check if aggregation has to be enabled for this tid */ 1344 /* Check if aggregation has to be enabled for this tid */
1339 if (conf_is_ht(&sc->hw->conf) && 1345 if (conf_is_ht(&sc->hw->conf) &&
@@ -1347,13 +1353,11 @@ static void ath_tx_status(void *priv, struct ieee80211_supported_band *sband,
1347 an = (struct ath_node *)sta->drv_priv; 1353 an = (struct ath_node *)sta->drv_priv;
1348 1354
1349 if(ath_tx_aggr_check(sc, an, tid)) 1355 if(ath_tx_aggr_check(sc, an, tid))
1350 ieee80211_start_tx_ba_session(sc->hw, hdr->addr1, tid); 1356 ieee80211_start_tx_ba_session(sta, tid);
1351 } 1357 }
1352 } 1358 }
1353 1359
1354 ath_debug_stat_rc(sc, skb); 1360 ath_debug_stat_rc(sc, skb);
1355exit:
1356 kfree(tx_info_priv);
1357} 1361}
1358 1362
1359static void ath_rate_init(void *priv, struct ieee80211_supported_band *sband, 1363static void ath_rate_init(void *priv, struct ieee80211_supported_band *sband,
@@ -1438,9 +1442,9 @@ static void ath_rate_update(void *priv, struct ieee80211_supported_band *sband,
1438 oper_cw40, oper_sgi40); 1442 oper_cw40, oper_sgi40);
1439 ath_rc_init(sc, priv_sta, sband, sta, rate_table); 1443 ath_rc_init(sc, priv_sta, sband, sta, rate_table);
1440 1444
1441 DPRINTF(sc, ATH_DBG_CONFIG, 1445 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
1442 "Operating HT Bandwidth changed to: %d\n", 1446 "Operating HT Bandwidth changed to: %d\n",
1443 sc->hw->conf.channel_type); 1447 sc->hw->conf.channel_type);
1444 } 1448 }
1445 } 1449 }
1446} 1450}
@@ -1463,8 +1467,8 @@ static void *ath_rate_alloc_sta(void *priv, struct ieee80211_sta *sta, gfp_t gfp
1463 1467
1464 rate_priv = kzalloc(sizeof(struct ath_rate_priv), gfp); 1468 rate_priv = kzalloc(sizeof(struct ath_rate_priv), gfp);
1465 if (!rate_priv) { 1469 if (!rate_priv) {
1466 DPRINTF(sc, ATH_DBG_FATAL, 1470 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1467 "Unable to allocate private rc structure\n"); 1471 "Unable to allocate private rc structure\n");
1468 return NULL; 1472 return NULL;
1469 } 1473 }
1470 1474
diff --git a/drivers/net/wireless/ath/ath9k/rc.h b/drivers/net/wireless/ath/ath9k/rc.h
index fa21a628ddd0..51f85ecbe88d 100644
--- a/drivers/net/wireless/ath/ath9k/rc.h
+++ b/drivers/net/wireless/ath/ath9k/rc.h
@@ -19,6 +19,8 @@
19#ifndef RC_H 19#ifndef RC_H
20#define RC_H 20#define RC_H
21 21
22#include "hw.h"
23
22struct ath_softc; 24struct ath_softc;
23 25
24#define ATH_RATE_MAX 30 26#define ATH_RATE_MAX 30
@@ -165,24 +167,18 @@ struct ath_rate_priv {
165 struct ath_rate_softc *asc; 167 struct ath_rate_softc *asc;
166}; 168};
167 169
170#define ATH_TX_INFO_FRAME_TYPE_INTERNAL (1 << 0)
171#define ATH_TX_INFO_FRAME_TYPE_PAUSE (1 << 1)
172#define ATH_TX_INFO_UPDATE_RC (1 << 2)
173#define ATH_TX_INFO_XRETRY (1 << 3)
174#define ATH_TX_INFO_UNDERRUN (1 << 4)
175
168enum ath9k_internal_frame_type { 176enum ath9k_internal_frame_type {
169 ATH9K_NOT_INTERNAL, 177 ATH9K_NOT_INTERNAL,
170 ATH9K_INT_PAUSE, 178 ATH9K_INT_PAUSE,
171 ATH9K_INT_UNPAUSE 179 ATH9K_INT_UNPAUSE
172}; 180};
173 181
174struct ath_tx_info_priv {
175 struct ath_wiphy *aphy;
176 struct ath_tx_status tx;
177 int n_frames;
178 int n_bad_frames;
179 bool update_rc;
180 enum ath9k_internal_frame_type frame_type;
181};
182
183#define ATH_TX_INFO_PRIV(tx_info) \
184 ((struct ath_tx_info_priv *)((tx_info)->rate_driver_data[0]))
185
186void ath_rate_attach(struct ath_softc *sc); 182void ath_rate_attach(struct ath_softc *sc);
187u8 ath_rate_findrateix(struct ath_softc *sc, u8 dot11_rate); 183u8 ath_rate_findrateix(struct ath_softc *sc, u8 dot11_rate);
188int ath_rate_control_register(void); 184int ath_rate_control_register(void);
diff --git a/drivers/net/wireless/ath/ath9k/recv.c b/drivers/net/wireless/ath/ath9k/recv.c
index ec0abf823995..477365e5ae69 100644
--- a/drivers/net/wireless/ath/ath9k/recv.c
+++ b/drivers/net/wireless/ath/ath9k/recv.c
@@ -48,6 +48,7 @@ static struct ieee80211_hw * ath_get_virt_hw(struct ath_softc *sc,
48static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf) 48static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf)
49{ 49{
50 struct ath_hw *ah = sc->sc_ah; 50 struct ath_hw *ah = sc->sc_ah;
51 struct ath_common *common = ath9k_hw_common(ah);
51 struct ath_desc *ds; 52 struct ath_desc *ds;
52 struct sk_buff *skb; 53 struct sk_buff *skb;
53 54
@@ -59,14 +60,16 @@ static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf)
59 60
60 /* virtual addr of the beginning of the buffer. */ 61 /* virtual addr of the beginning of the buffer. */
61 skb = bf->bf_mpdu; 62 skb = bf->bf_mpdu;
62 ASSERT(skb != NULL); 63 BUG_ON(skb == NULL);
63 ds->ds_vdata = skb->data; 64 ds->ds_vdata = skb->data;
64 65
65 /* setup rx descriptors. The rx.bufsize here tells the harware 66 /*
67 * setup rx descriptors. The rx_bufsize here tells the hardware
66 * how much data it can DMA to us and that we are prepared 68 * how much data it can DMA to us and that we are prepared
67 * to process */ 69 * to process
70 */
68 ath9k_hw_setuprxdesc(ah, ds, 71 ath9k_hw_setuprxdesc(ah, ds,
69 sc->rx.bufsize, 72 common->rx_bufsize,
70 0); 73 0);
71 74
72 if (sc->rx.rxlink == NULL) 75 if (sc->rx.rxlink == NULL)
@@ -86,192 +89,11 @@ static void ath_setdefantenna(struct ath_softc *sc, u32 antenna)
86 sc->rx.rxotherant = 0; 89 sc->rx.rxotherant = 0;
87} 90}
88 91
89/*
90 * Extend 15-bit time stamp from rx descriptor to
91 * a full 64-bit TSF using the current h/w TSF.
92*/
93static u64 ath_extend_tsf(struct ath_softc *sc, u32 rstamp)
94{
95 u64 tsf;
96
97 tsf = ath9k_hw_gettsf64(sc->sc_ah);
98 if ((tsf & 0x7fff) < rstamp)
99 tsf -= 0x8000;
100 return (tsf & ~0x7fff) | rstamp;
101}
102
103/*
104 * For Decrypt or Demic errors, we only mark packet status here and always push
105 * up the frame up to let mac80211 handle the actual error case, be it no
106 * decryption key or real decryption error. This let us keep statistics there.
107 */
108static int ath_rx_prepare(struct sk_buff *skb, struct ath_desc *ds,
109 struct ieee80211_rx_status *rx_status, bool *decrypt_error,
110 struct ath_softc *sc)
111{
112 struct ieee80211_hdr *hdr;
113 u8 ratecode;
114 __le16 fc;
115 struct ieee80211_hw *hw;
116 struct ieee80211_sta *sta;
117 struct ath_node *an;
118 int last_rssi = ATH_RSSI_DUMMY_MARKER;
119
120
121 hdr = (struct ieee80211_hdr *)skb->data;
122 fc = hdr->frame_control;
123 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
124 hw = ath_get_virt_hw(sc, hdr);
125
126 if (ds->ds_rxstat.rs_more) {
127 /*
128 * Frame spans multiple descriptors; this cannot happen yet
129 * as we don't support jumbograms. If not in monitor mode,
130 * discard the frame. Enable this if you want to see
131 * error frames in Monitor mode.
132 */
133 if (sc->sc_ah->opmode != NL80211_IFTYPE_MONITOR)
134 goto rx_next;
135 } else if (ds->ds_rxstat.rs_status != 0) {
136 if (ds->ds_rxstat.rs_status & ATH9K_RXERR_CRC)
137 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
138 if (ds->ds_rxstat.rs_status & ATH9K_RXERR_PHY)
139 goto rx_next;
140
141 if (ds->ds_rxstat.rs_status & ATH9K_RXERR_DECRYPT) {
142 *decrypt_error = true;
143 } else if (ds->ds_rxstat.rs_status & ATH9K_RXERR_MIC) {
144 if (ieee80211_is_ctl(fc))
145 /*
146 * Sometimes, we get invalid
147 * MIC failures on valid control frames.
148 * Remove these mic errors.
149 */
150 ds->ds_rxstat.rs_status &= ~ATH9K_RXERR_MIC;
151 else
152 rx_status->flag |= RX_FLAG_MMIC_ERROR;
153 }
154 /*
155 * Reject error frames with the exception of
156 * decryption and MIC failures. For monitor mode,
157 * we also ignore the CRC error.
158 */
159 if (sc->sc_ah->opmode == NL80211_IFTYPE_MONITOR) {
160 if (ds->ds_rxstat.rs_status &
161 ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC |
162 ATH9K_RXERR_CRC))
163 goto rx_next;
164 } else {
165 if (ds->ds_rxstat.rs_status &
166 ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC)) {
167 goto rx_next;
168 }
169 }
170 }
171
172 ratecode = ds->ds_rxstat.rs_rate;
173
174 if (ratecode & 0x80) {
175 /* HT rate */
176 rx_status->flag |= RX_FLAG_HT;
177 if (ds->ds_rxstat.rs_flags & ATH9K_RX_2040)
178 rx_status->flag |= RX_FLAG_40MHZ;
179 if (ds->ds_rxstat.rs_flags & ATH9K_RX_GI)
180 rx_status->flag |= RX_FLAG_SHORT_GI;
181 rx_status->rate_idx = ratecode & 0x7f;
182 } else {
183 int i = 0, cur_band, n_rates;
184
185 cur_band = hw->conf.channel->band;
186 n_rates = sc->sbands[cur_band].n_bitrates;
187
188 for (i = 0; i < n_rates; i++) {
189 if (sc->sbands[cur_band].bitrates[i].hw_value ==
190 ratecode) {
191 rx_status->rate_idx = i;
192 break;
193 }
194
195 if (sc->sbands[cur_band].bitrates[i].hw_value_short ==
196 ratecode) {
197 rx_status->rate_idx = i;
198 rx_status->flag |= RX_FLAG_SHORTPRE;
199 break;
200 }
201 }
202 }
203
204 rcu_read_lock();
205 sta = ieee80211_find_sta(sc->hw, hdr->addr2);
206 if (sta) {
207 an = (struct ath_node *) sta->drv_priv;
208 if (ds->ds_rxstat.rs_rssi != ATH9K_RSSI_BAD &&
209 !ds->ds_rxstat.rs_moreaggr)
210 ATH_RSSI_LPF(an->last_rssi, ds->ds_rxstat.rs_rssi);
211 last_rssi = an->last_rssi;
212 }
213 rcu_read_unlock();
214
215 if (likely(last_rssi != ATH_RSSI_DUMMY_MARKER))
216 ds->ds_rxstat.rs_rssi = ATH_EP_RND(last_rssi,
217 ATH_RSSI_EP_MULTIPLIER);
218 if (ds->ds_rxstat.rs_rssi < 0)
219 ds->ds_rxstat.rs_rssi = 0;
220 else if (ds->ds_rxstat.rs_rssi > 127)
221 ds->ds_rxstat.rs_rssi = 127;
222
223 /* Update Beacon RSSI, this is used by ANI. */
224 if (ieee80211_is_beacon(fc))
225 sc->sc_ah->stats.avgbrssi = ds->ds_rxstat.rs_rssi;
226
227 rx_status->mactime = ath_extend_tsf(sc, ds->ds_rxstat.rs_tstamp);
228 rx_status->band = hw->conf.channel->band;
229 rx_status->freq = hw->conf.channel->center_freq;
230 rx_status->noise = sc->ani.noise_floor;
231 rx_status->signal = ATH_DEFAULT_NOISE_FLOOR + ds->ds_rxstat.rs_rssi;
232 rx_status->antenna = ds->ds_rxstat.rs_antenna;
233
234 /*
235 * Theory for reporting quality:
236 *
237 * At a hardware RSSI of 45 you will be able to use MCS 7 reliably.
238 * At a hardware RSSI of 45 you will be able to use MCS 15 reliably.
239 * At a hardware RSSI of 35 you should be able use 54 Mbps reliably.
240 *
241 * MCS 7 is the highets MCS index usable by a 1-stream device.
242 * MCS 15 is the highest MCS index usable by a 2-stream device.
243 *
244 * All ath9k devices are either 1-stream or 2-stream.
245 *
246 * How many bars you see is derived from the qual reporting.
247 *
248 * A more elaborate scheme can be used here but it requires tables
249 * of SNR/throughput for each possible mode used. For the MCS table
250 * you can refer to the wireless wiki:
251 *
252 * http://wireless.kernel.org/en/developers/Documentation/ieee80211/802.11n
253 *
254 */
255 if (conf_is_ht(&hw->conf))
256 rx_status->qual = ds->ds_rxstat.rs_rssi * 100 / 45;
257 else
258 rx_status->qual = ds->ds_rxstat.rs_rssi * 100 / 35;
259
260 /* rssi can be more than 45 though, anything above that
261 * should be considered at 100% */
262 if (rx_status->qual > 100)
263 rx_status->qual = 100;
264
265 rx_status->flag |= RX_FLAG_TSFT;
266
267 return 1;
268rx_next:
269 return 0;
270}
271
272static void ath_opmode_init(struct ath_softc *sc) 92static void ath_opmode_init(struct ath_softc *sc)
273{ 93{
274 struct ath_hw *ah = sc->sc_ah; 94 struct ath_hw *ah = sc->sc_ah;
95 struct ath_common *common = ath9k_hw_common(ah);
96
275 u32 rfilt, mfilt[2]; 97 u32 rfilt, mfilt[2];
276 98
277 /* configure rx filter */ 99 /* configure rx filter */
@@ -280,13 +102,13 @@ static void ath_opmode_init(struct ath_softc *sc)
280 102
281 /* configure bssid mask */ 103 /* configure bssid mask */
282 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) 104 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
283 ath9k_hw_setbssidmask(sc); 105 ath_hw_setbssidmask(common);
284 106
285 /* configure operational mode */ 107 /* configure operational mode */
286 ath9k_hw_setopmode(ah); 108 ath9k_hw_setopmode(ah);
287 109
288 /* Handle any link-level address change. */ 110 /* Handle any link-level address change. */
289 ath9k_hw_setmac(ah, sc->sc_ah->macaddr); 111 ath9k_hw_setmac(ah, common->macaddr);
290 112
291 /* calculate and install multicast filter */ 113 /* calculate and install multicast filter */
292 mfilt[0] = mfilt[1] = ~0; 114 mfilt[0] = mfilt[1] = ~0;
@@ -295,6 +117,7 @@ static void ath_opmode_init(struct ath_softc *sc)
295 117
296int ath_rx_init(struct ath_softc *sc, int nbufs) 118int ath_rx_init(struct ath_softc *sc, int nbufs)
297{ 119{
120 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
298 struct sk_buff *skb; 121 struct sk_buff *skb;
299 struct ath_buf *bf; 122 struct ath_buf *bf;
300 int error = 0; 123 int error = 0;
@@ -303,24 +126,24 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
303 sc->sc_flags &= ~SC_OP_RXFLUSH; 126 sc->sc_flags &= ~SC_OP_RXFLUSH;
304 spin_lock_init(&sc->rx.rxbuflock); 127 spin_lock_init(&sc->rx.rxbuflock);
305 128
306 sc->rx.bufsize = roundup(IEEE80211_MAX_MPDU_LEN, 129 common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN,
307 min(sc->common.cachelsz, (u16)64)); 130 min(common->cachelsz, (u16)64));
308 131
309 DPRINTF(sc, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n", 132 ath_print(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n",
310 sc->common.cachelsz, sc->rx.bufsize); 133 common->cachelsz, common->rx_bufsize);
311 134
312 /* Initialize rx descriptors */ 135 /* Initialize rx descriptors */
313 136
314 error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf, 137 error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
315 "rx", nbufs, 1); 138 "rx", nbufs, 1);
316 if (error != 0) { 139 if (error != 0) {
317 DPRINTF(sc, ATH_DBG_FATAL, 140 ath_print(common, ATH_DBG_FATAL,
318 "failed to allocate rx descriptors: %d\n", error); 141 "failed to allocate rx descriptors: %d\n", error);
319 goto err; 142 goto err;
320 } 143 }
321 144
322 list_for_each_entry(bf, &sc->rx.rxbuf, list) { 145 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
323 skb = ath_rxbuf_alloc(&sc->common, sc->rx.bufsize, GFP_KERNEL); 146 skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_KERNEL);
324 if (skb == NULL) { 147 if (skb == NULL) {
325 error = -ENOMEM; 148 error = -ENOMEM;
326 goto err; 149 goto err;
@@ -328,14 +151,14 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
328 151
329 bf->bf_mpdu = skb; 152 bf->bf_mpdu = skb;
330 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, 153 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
331 sc->rx.bufsize, 154 common->rx_bufsize,
332 DMA_FROM_DEVICE); 155 DMA_FROM_DEVICE);
333 if (unlikely(dma_mapping_error(sc->dev, 156 if (unlikely(dma_mapping_error(sc->dev,
334 bf->bf_buf_addr))) { 157 bf->bf_buf_addr))) {
335 dev_kfree_skb_any(skb); 158 dev_kfree_skb_any(skb);
336 bf->bf_mpdu = NULL; 159 bf->bf_mpdu = NULL;
337 DPRINTF(sc, ATH_DBG_FATAL, 160 ath_print(common, ATH_DBG_FATAL,
338 "dma_mapping_error() on RX init\n"); 161 "dma_mapping_error() on RX init\n");
339 error = -ENOMEM; 162 error = -ENOMEM;
340 goto err; 163 goto err;
341 } 164 }
@@ -352,6 +175,8 @@ err:
352 175
353void ath_rx_cleanup(struct ath_softc *sc) 176void ath_rx_cleanup(struct ath_softc *sc)
354{ 177{
178 struct ath_hw *ah = sc->sc_ah;
179 struct ath_common *common = ath9k_hw_common(ah);
355 struct sk_buff *skb; 180 struct sk_buff *skb;
356 struct ath_buf *bf; 181 struct ath_buf *bf;
357 182
@@ -359,7 +184,7 @@ void ath_rx_cleanup(struct ath_softc *sc)
359 skb = bf->bf_mpdu; 184 skb = bf->bf_mpdu;
360 if (skb) { 185 if (skb) {
361 dma_unmap_single(sc->dev, bf->bf_buf_addr, 186 dma_unmap_single(sc->dev, bf->bf_buf_addr,
362 sc->rx.bufsize, DMA_FROM_DEVICE); 187 common->rx_bufsize, DMA_FROM_DEVICE);
363 dev_kfree_skb(skb); 188 dev_kfree_skb(skb);
364 } 189 }
365 } 190 }
@@ -420,7 +245,10 @@ u32 ath_calcrxfilter(struct ath_softc *sc)
420 else 245 else
421 rfilt |= ATH9K_RX_FILTER_BEACON; 246 rfilt |= ATH9K_RX_FILTER_BEACON;
422 247
423 if (sc->rx.rxfilter & FIF_PSPOLL) 248 if ((AR_SREV_9280_10_OR_LATER(sc->sc_ah) ||
249 AR_SREV_9285_10_OR_LATER(sc->sc_ah)) &&
250 (sc->sc_ah->opmode == NL80211_IFTYPE_AP) &&
251 (sc->rx.rxfilter & FIF_PSPOLL))
424 rfilt |= ATH9K_RX_FILTER_PSPOLL; 252 rfilt |= ATH9K_RX_FILTER_PSPOLL;
425 253
426 if (conf_is_ht(&sc->hw->conf)) 254 if (conf_is_ht(&sc->hw->conf))
@@ -527,20 +355,22 @@ static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb)
527static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb) 355static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
528{ 356{
529 struct ieee80211_mgmt *mgmt; 357 struct ieee80211_mgmt *mgmt;
358 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
530 359
531 if (skb->len < 24 + 8 + 2 + 2) 360 if (skb->len < 24 + 8 + 2 + 2)
532 return; 361 return;
533 362
534 mgmt = (struct ieee80211_mgmt *)skb->data; 363 mgmt = (struct ieee80211_mgmt *)skb->data;
535 if (memcmp(sc->curbssid, mgmt->bssid, ETH_ALEN) != 0) 364 if (memcmp(common->curbssid, mgmt->bssid, ETH_ALEN) != 0)
536 return; /* not from our current AP */ 365 return; /* not from our current AP */
537 366
538 sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON; 367 sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON;
539 368
540 if (sc->sc_flags & SC_OP_BEACON_SYNC) { 369 if (sc->sc_flags & SC_OP_BEACON_SYNC) {
541 sc->sc_flags &= ~SC_OP_BEACON_SYNC; 370 sc->sc_flags &= ~SC_OP_BEACON_SYNC;
542 DPRINTF(sc, ATH_DBG_PS, "Reconfigure Beacon timers based on " 371 ath_print(common, ATH_DBG_PS,
543 "timestamp from the AP\n"); 372 "Reconfigure Beacon timers based on "
373 "timestamp from the AP\n");
544 ath_beacon_config(sc, NULL); 374 ath_beacon_config(sc, NULL);
545 } 375 }
546 376
@@ -552,8 +382,8 @@ static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
552 * a backup trigger for returning into NETWORK SLEEP state, 382 * a backup trigger for returning into NETWORK SLEEP state,
553 * so we are waiting for it as well. 383 * so we are waiting for it as well.
554 */ 384 */
555 DPRINTF(sc, ATH_DBG_PS, "Received DTIM beacon indicating " 385 ath_print(common, ATH_DBG_PS, "Received DTIM beacon indicating "
556 "buffered broadcast/multicast frame(s)\n"); 386 "buffered broadcast/multicast frame(s)\n");
557 sc->sc_flags |= SC_OP_WAIT_FOR_CAB | SC_OP_WAIT_FOR_BEACON; 387 sc->sc_flags |= SC_OP_WAIT_FOR_CAB | SC_OP_WAIT_FOR_BEACON;
558 return; 388 return;
559 } 389 }
@@ -565,13 +395,15 @@ static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
565 * been delivered. 395 * been delivered.
566 */ 396 */
567 sc->sc_flags &= ~SC_OP_WAIT_FOR_CAB; 397 sc->sc_flags &= ~SC_OP_WAIT_FOR_CAB;
568 DPRINTF(sc, ATH_DBG_PS, "PS wait for CAB frames timed out\n"); 398 ath_print(common, ATH_DBG_PS,
399 "PS wait for CAB frames timed out\n");
569 } 400 }
570} 401}
571 402
572static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb) 403static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb)
573{ 404{
574 struct ieee80211_hdr *hdr; 405 struct ieee80211_hdr *hdr;
406 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
575 407
576 hdr = (struct ieee80211_hdr *)skb->data; 408 hdr = (struct ieee80211_hdr *)skb->data;
577 409
@@ -589,14 +421,15 @@ static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb)
589 * point. 421 * point.
590 */ 422 */
591 sc->sc_flags &= ~SC_OP_WAIT_FOR_CAB; 423 sc->sc_flags &= ~SC_OP_WAIT_FOR_CAB;
592 DPRINTF(sc, ATH_DBG_PS, "All PS CAB frames received, back to " 424 ath_print(common, ATH_DBG_PS,
593 "sleep\n"); 425 "All PS CAB frames received, back to sleep\n");
594 } else if ((sc->sc_flags & SC_OP_WAIT_FOR_PSPOLL_DATA) && 426 } else if ((sc->sc_flags & SC_OP_WAIT_FOR_PSPOLL_DATA) &&
595 !is_multicast_ether_addr(hdr->addr1) && 427 !is_multicast_ether_addr(hdr->addr1) &&
596 !ieee80211_has_morefrags(hdr->frame_control)) { 428 !ieee80211_has_morefrags(hdr->frame_control)) {
597 sc->sc_flags &= ~SC_OP_WAIT_FOR_PSPOLL_DATA; 429 sc->sc_flags &= ~SC_OP_WAIT_FOR_PSPOLL_DATA;
598 DPRINTF(sc, ATH_DBG_PS, "Going back to sleep after having " 430 ath_print(common, ATH_DBG_PS,
599 "received PS-Poll data (0x%x)\n", 431 "Going back to sleep after having received "
432 "PS-Poll data (0x%x)\n",
600 sc->sc_flags & (SC_OP_WAIT_FOR_BEACON | 433 sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
601 SC_OP_WAIT_FOR_CAB | 434 SC_OP_WAIT_FOR_CAB |
602 SC_OP_WAIT_FOR_PSPOLL_DATA | 435 SC_OP_WAIT_FOR_PSPOLL_DATA |
@@ -604,8 +437,9 @@ static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb)
604 } 437 }
605} 438}
606 439
607static void ath_rx_send_to_mac80211(struct ath_softc *sc, struct sk_buff *skb, 440static void ath_rx_send_to_mac80211(struct ieee80211_hw *hw,
608 struct ieee80211_rx_status *rx_status) 441 struct ath_softc *sc, struct sk_buff *skb,
442 struct ieee80211_rx_status *rxs)
609{ 443{
610 struct ieee80211_hdr *hdr; 444 struct ieee80211_hdr *hdr;
611 445
@@ -625,19 +459,14 @@ static void ath_rx_send_to_mac80211(struct ath_softc *sc, struct sk_buff *skb,
625 if (aphy == NULL) 459 if (aphy == NULL)
626 continue; 460 continue;
627 nskb = skb_copy(skb, GFP_ATOMIC); 461 nskb = skb_copy(skb, GFP_ATOMIC);
628 if (nskb) { 462 if (!nskb)
629 memcpy(IEEE80211_SKB_RXCB(nskb), rx_status, 463 continue;
630 sizeof(*rx_status)); 464 ieee80211_rx(aphy->hw, nskb);
631 ieee80211_rx(aphy->hw, nskb);
632 }
633 } 465 }
634 memcpy(IEEE80211_SKB_RXCB(skb), rx_status, sizeof(*rx_status));
635 ieee80211_rx(sc->hw, skb); 466 ieee80211_rx(sc->hw, skb);
636 } else { 467 } else
637 /* Deliver unicast frames based on receiver address */ 468 /* Deliver unicast frames based on receiver address */
638 memcpy(IEEE80211_SKB_RXCB(skb), rx_status, sizeof(*rx_status)); 469 ieee80211_rx(hw, skb);
639 ieee80211_rx(ath_get_virt_hw(sc, hdr), skb);
640 }
641} 470}
642 471
643int ath_rx_tasklet(struct ath_softc *sc, int flush) 472int ath_rx_tasklet(struct ath_softc *sc, int flush)
@@ -648,14 +477,20 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
648 477
649 struct ath_buf *bf; 478 struct ath_buf *bf;
650 struct ath_desc *ds; 479 struct ath_desc *ds;
480 struct ath_rx_status *rx_stats;
651 struct sk_buff *skb = NULL, *requeue_skb; 481 struct sk_buff *skb = NULL, *requeue_skb;
652 struct ieee80211_rx_status rx_status; 482 struct ieee80211_rx_status *rxs;
653 struct ath_hw *ah = sc->sc_ah; 483 struct ath_hw *ah = sc->sc_ah;
484 struct ath_common *common = ath9k_hw_common(ah);
485 /*
486 * The hw can techncically differ from common->hw when using ath9k
487 * virtual wiphy so to account for that we iterate over the active
488 * wiphys and find the appropriate wiphy and therefore hw.
489 */
490 struct ieee80211_hw *hw = NULL;
654 struct ieee80211_hdr *hdr; 491 struct ieee80211_hdr *hdr;
655 int hdrlen, padsize, retval; 492 int retval;
656 bool decrypt_error = false; 493 bool decrypt_error = false;
657 u8 keyix;
658 __le16 fc;
659 494
660 spin_lock_bh(&sc->rx.rxbuflock); 495 spin_lock_bh(&sc->rx.rxbuflock);
661 496
@@ -727,9 +562,15 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
727 * 2. requeueing the same buffer to h/w 562 * 2. requeueing the same buffer to h/w
728 */ 563 */
729 dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr, 564 dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
730 sc->rx.bufsize, 565 common->rx_bufsize,
731 DMA_FROM_DEVICE); 566 DMA_FROM_DEVICE);
732 567
568 hdr = (struct ieee80211_hdr *) skb->data;
569 rxs = IEEE80211_SKB_RXCB(skb);
570
571 hw = ath_get_virt_hw(sc, hdr);
572 rx_stats = &ds->ds_rxstat;
573
733 /* 574 /*
734 * If we're asked to flush receive queue, directly 575 * If we're asked to flush receive queue, directly
735 * chain it back at the queue without processing it. 576 * chain it back at the queue without processing it.
@@ -737,19 +578,14 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
737 if (flush) 578 if (flush)
738 goto requeue; 579 goto requeue;
739 580
740 if (!ds->ds_rxstat.rs_datalen) 581 retval = ath9k_cmn_rx_skb_preprocess(common, hw, skb, rx_stats,
741 goto requeue; 582 rxs, &decrypt_error);
742 583 if (retval)
743 /* The status portion of the descriptor could get corrupted. */
744 if (sc->rx.bufsize < ds->ds_rxstat.rs_datalen)
745 goto requeue;
746
747 if (!ath_rx_prepare(skb, ds, &rx_status, &decrypt_error, sc))
748 goto requeue; 584 goto requeue;
749 585
750 /* Ensure we always have an skb to requeue once we are done 586 /* Ensure we always have an skb to requeue once we are done
751 * processing the current buffer's skb */ 587 * processing the current buffer's skb */
752 requeue_skb = ath_rxbuf_alloc(&sc->common, sc->rx.bufsize, GFP_ATOMIC); 588 requeue_skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_ATOMIC);
753 589
754 /* If there is no memory we ignore the current RX'd frame, 590 /* If there is no memory we ignore the current RX'd frame,
755 * tell hardware it can give us a new frame using the old 591 * tell hardware it can give us a new frame using the old
@@ -760,60 +596,26 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
760 596
761 /* Unmap the frame */ 597 /* Unmap the frame */
762 dma_unmap_single(sc->dev, bf->bf_buf_addr, 598 dma_unmap_single(sc->dev, bf->bf_buf_addr,
763 sc->rx.bufsize, 599 common->rx_bufsize,
764 DMA_FROM_DEVICE); 600 DMA_FROM_DEVICE);
765 601
766 skb_put(skb, ds->ds_rxstat.rs_datalen); 602 skb_put(skb, rx_stats->rs_datalen);
767
768 /* see if any padding is done by the hw and remove it */
769 hdr = (struct ieee80211_hdr *)skb->data;
770 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
771 fc = hdr->frame_control;
772
773 /* The MAC header is padded to have 32-bit boundary if the
774 * packet payload is non-zero. The general calculation for
775 * padsize would take into account odd header lengths:
776 * padsize = (4 - hdrlen % 4) % 4; However, since only
777 * even-length headers are used, padding can only be 0 or 2
778 * bytes and we can optimize this a bit. In addition, we must
779 * not try to remove padding from short control frames that do
780 * not have payload. */
781 padsize = hdrlen & 3;
782 if (padsize && hdrlen >= 24) {
783 memmove(skb->data + padsize, skb->data, hdrlen);
784 skb_pull(skb, padsize);
785 }
786
787 keyix = ds->ds_rxstat.rs_keyix;
788 603
789 if (!(keyix == ATH9K_RXKEYIX_INVALID) && !decrypt_error) { 604 ath9k_cmn_rx_skb_postprocess(common, skb, rx_stats,
790 rx_status.flag |= RX_FLAG_DECRYPTED; 605 rxs, decrypt_error);
791 } else if (ieee80211_has_protected(fc)
792 && !decrypt_error && skb->len >= hdrlen + 4) {
793 keyix = skb->data[hdrlen + 3] >> 6;
794
795 if (test_bit(keyix, sc->keymap))
796 rx_status.flag |= RX_FLAG_DECRYPTED;
797 }
798 if (ah->sw_mgmt_crypto &&
799 (rx_status.flag & RX_FLAG_DECRYPTED) &&
800 ieee80211_is_mgmt(fc)) {
801 /* Use software decrypt for management frames. */
802 rx_status.flag &= ~RX_FLAG_DECRYPTED;
803 }
804 606
805 /* We will now give hardware our shiny new allocated skb */ 607 /* We will now give hardware our shiny new allocated skb */
806 bf->bf_mpdu = requeue_skb; 608 bf->bf_mpdu = requeue_skb;
807 bf->bf_buf_addr = dma_map_single(sc->dev, requeue_skb->data, 609 bf->bf_buf_addr = dma_map_single(sc->dev, requeue_skb->data,
808 sc->rx.bufsize, 610 common->rx_bufsize,
809 DMA_FROM_DEVICE); 611 DMA_FROM_DEVICE);
810 if (unlikely(dma_mapping_error(sc->dev, 612 if (unlikely(dma_mapping_error(sc->dev,
811 bf->bf_buf_addr))) { 613 bf->bf_buf_addr))) {
812 dev_kfree_skb_any(requeue_skb); 614 dev_kfree_skb_any(requeue_skb);
813 bf->bf_mpdu = NULL; 615 bf->bf_mpdu = NULL;
814 DPRINTF(sc, ATH_DBG_FATAL, 616 ath_print(common, ATH_DBG_FATAL,
815 "dma_mapping_error() on RX\n"); 617 "dma_mapping_error() on RX\n");
816 ath_rx_send_to_mac80211(sc, skb, &rx_status); 618 ath_rx_send_to_mac80211(hw, sc, skb, rxs);
817 break; 619 break;
818 } 620 }
819 bf->bf_dmacontext = bf->bf_buf_addr; 621 bf->bf_dmacontext = bf->bf_buf_addr;
@@ -824,7 +626,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
824 */ 626 */
825 if (sc->rx.defant != ds->ds_rxstat.rs_antenna) { 627 if (sc->rx.defant != ds->ds_rxstat.rs_antenna) {
826 if (++sc->rx.rxotherant >= 3) 628 if (++sc->rx.rxotherant >= 3)
827 ath_setdefantenna(sc, ds->ds_rxstat.rs_antenna); 629 ath_setdefantenna(sc, rx_stats->rs_antenna);
828 } else { 630 } else {
829 sc->rx.rxotherant = 0; 631 sc->rx.rxotherant = 0;
830 } 632 }
@@ -834,7 +636,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
834 SC_OP_WAIT_FOR_PSPOLL_DATA))) 636 SC_OP_WAIT_FOR_PSPOLL_DATA)))
835 ath_rx_ps(sc, skb); 637 ath_rx_ps(sc, skb);
836 638
837 ath_rx_send_to_mac80211(sc, skb, &rx_status); 639 ath_rx_send_to_mac80211(hw, sc, skb, rxs);
838 640
839requeue: 641requeue:
840 list_move_tail(&bf->list, &sc->rx.rxbuf); 642 list_move_tail(&bf->list, &sc->rx.rxbuf);
diff --git a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h
index d83b77f821e9..49ec25f020f0 100644
--- a/drivers/net/wireless/ath/ath9k/reg.h
+++ b/drivers/net/wireless/ath/ath9k/reg.h
@@ -17,6 +17,8 @@
17#ifndef REG_H 17#ifndef REG_H
18#define REG_H 18#define REG_H
19 19
20#include "../reg.h"
21
20#define AR_CR 0x0008 22#define AR_CR 0x0008
21#define AR_CR_RXE 0x00000004 23#define AR_CR_RXE 0x00000004
22#define AR_CR_RXD 0x00000020 24#define AR_CR_RXD 0x00000020
@@ -969,10 +971,10 @@ enum {
969#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_S 4 971#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_S 4
970#define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF 0x00000080 972#define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF 0x00000080
971#define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF_S 7 973#define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF_S 7
974#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB 0x00000400
975#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB_S 10
972#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB 0x00001000 976#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB 0x00001000
973#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB_S 12 977#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB_S 12
974#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB 0x00001000
975#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB_S 1
976#define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB 0x00008000 978#define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB 0x00008000
977#define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB_S 15 979#define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB_S 15
978#define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000 980#define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000
@@ -1421,9 +1423,6 @@ enum {
1421#define AR_SLEEP2_BEACON_TIMEOUT 0xFFE00000 1423#define AR_SLEEP2_BEACON_TIMEOUT 0xFFE00000
1422#define AR_SLEEP2_BEACON_TIMEOUT_S 21 1424#define AR_SLEEP2_BEACON_TIMEOUT_S 21
1423 1425
1424#define AR_BSSMSKL 0x80e0
1425#define AR_BSSMSKU 0x80e4
1426
1427#define AR_TPC 0x80e8 1426#define AR_TPC 0x80e8
1428#define AR_TPC_ACK 0x0000003f 1427#define AR_TPC_ACK 0x0000003f
1429#define AR_TPC_ACK_S 0x00 1428#define AR_TPC_ACK_S 0x00
@@ -1705,4 +1704,7 @@ enum {
1705#define AR_KEYTABLE_MAC0(_n) (AR_KEYTABLE(_n) + 24) 1704#define AR_KEYTABLE_MAC0(_n) (AR_KEYTABLE(_n) + 24)
1706#define AR_KEYTABLE_MAC1(_n) (AR_KEYTABLE(_n) + 28) 1705#define AR_KEYTABLE_MAC1(_n) (AR_KEYTABLE(_n) + 28)
1707 1706
1707#define AR9271_CORE_CLOCK 117 /* clock to 117Mhz */
1708#define AR9271_TARGET_BAUD_RATE 19200 /* 115200 */
1709
1708#endif 1710#endif
diff --git a/drivers/net/wireless/ath/ath9k/virtual.c b/drivers/net/wireless/ath/ath9k/virtual.c
index 19b88f8177fd..cd26caaf44e7 100644
--- a/drivers/net/wireless/ath/ath9k/virtual.c
+++ b/drivers/net/wireless/ath/ath9k/virtual.c
@@ -40,6 +40,7 @@ void ath9k_set_bssid_mask(struct ieee80211_hw *hw)
40{ 40{
41 struct ath_wiphy *aphy = hw->priv; 41 struct ath_wiphy *aphy = hw->priv;
42 struct ath_softc *sc = aphy->sc; 42 struct ath_softc *sc = aphy->sc;
43 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
43 struct ath9k_vif_iter_data iter_data; 44 struct ath9k_vif_iter_data iter_data;
44 int i, j; 45 int i, j;
45 u8 mask[ETH_ALEN]; 46 u8 mask[ETH_ALEN];
@@ -51,7 +52,7 @@ void ath9k_set_bssid_mask(struct ieee80211_hw *hw)
51 */ 52 */
52 iter_data.addr = kmalloc(ETH_ALEN, GFP_ATOMIC); 53 iter_data.addr = kmalloc(ETH_ALEN, GFP_ATOMIC);
53 if (iter_data.addr) { 54 if (iter_data.addr) {
54 memcpy(iter_data.addr, sc->sc_ah->macaddr, ETH_ALEN); 55 memcpy(iter_data.addr, common->macaddr, ETH_ALEN);
55 iter_data.count = 1; 56 iter_data.count = 1;
56 } else 57 } else
57 iter_data.count = 0; 58 iter_data.count = 0;
@@ -86,20 +87,21 @@ void ath9k_set_bssid_mask(struct ieee80211_hw *hw)
86 kfree(iter_data.addr); 87 kfree(iter_data.addr);
87 88
88 /* Invert the mask and configure hardware */ 89 /* Invert the mask and configure hardware */
89 sc->bssidmask[0] = ~mask[0]; 90 common->bssidmask[0] = ~mask[0];
90 sc->bssidmask[1] = ~mask[1]; 91 common->bssidmask[1] = ~mask[1];
91 sc->bssidmask[2] = ~mask[2]; 92 common->bssidmask[2] = ~mask[2];
92 sc->bssidmask[3] = ~mask[3]; 93 common->bssidmask[3] = ~mask[3];
93 sc->bssidmask[4] = ~mask[4]; 94 common->bssidmask[4] = ~mask[4];
94 sc->bssidmask[5] = ~mask[5]; 95 common->bssidmask[5] = ~mask[5];
95 96
96 ath9k_hw_setbssidmask(sc); 97 ath_hw_setbssidmask(common);
97} 98}
98 99
99int ath9k_wiphy_add(struct ath_softc *sc) 100int ath9k_wiphy_add(struct ath_softc *sc)
100{ 101{
101 int i, error; 102 int i, error;
102 struct ath_wiphy *aphy; 103 struct ath_wiphy *aphy;
104 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
103 struct ieee80211_hw *hw; 105 struct ieee80211_hw *hw;
104 u8 addr[ETH_ALEN]; 106 u8 addr[ETH_ALEN];
105 107
@@ -138,7 +140,7 @@ int ath9k_wiphy_add(struct ath_softc *sc)
138 sc->sec_wiphy[i] = aphy; 140 sc->sec_wiphy[i] = aphy;
139 spin_unlock_bh(&sc->wiphy_lock); 141 spin_unlock_bh(&sc->wiphy_lock);
140 142
141 memcpy(addr, sc->sc_ah->macaddr, ETH_ALEN); 143 memcpy(addr, common->macaddr, ETH_ALEN);
142 addr[0] |= 0x02; /* Locally managed address */ 144 addr[0] |= 0x02; /* Locally managed address */
143 /* 145 /*
144 * XOR virtual wiphy index into the least significant bits to generate 146 * XOR virtual wiphy index into the least significant bits to generate
@@ -296,6 +298,7 @@ static void ath9k_wiphy_unpause_channel(struct ath_softc *sc)
296void ath9k_wiphy_chan_work(struct work_struct *work) 298void ath9k_wiphy_chan_work(struct work_struct *work)
297{ 299{
298 struct ath_softc *sc = container_of(work, struct ath_softc, chan_work); 300 struct ath_softc *sc = container_of(work, struct ath_softc, chan_work);
301 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
299 struct ath_wiphy *aphy = sc->next_wiphy; 302 struct ath_wiphy *aphy = sc->next_wiphy;
300 303
301 if (aphy == NULL) 304 if (aphy == NULL)
@@ -311,6 +314,10 @@ void ath9k_wiphy_chan_work(struct work_struct *work)
311 /* XXX: remove me eventually */ 314 /* XXX: remove me eventually */
312 ath9k_update_ichannel(sc, aphy->hw, 315 ath9k_update_ichannel(sc, aphy->hw,
313 &sc->sc_ah->channels[sc->chan_idx]); 316 &sc->sc_ah->channels[sc->chan_idx]);
317
318 /* sync hw configuration for hw code */
319 common->hw = aphy->hw;
320
314 ath_update_chainmask(sc, sc->chan_is_ht); 321 ath_update_chainmask(sc, sc->chan_is_ht);
315 if (ath_set_channel(sc, aphy->hw, 322 if (ath_set_channel(sc, aphy->hw,
316 &sc->sc_ah->channels[sc->chan_idx]) < 0) { 323 &sc->sc_ah->channels[sc->chan_idx]) < 0) {
@@ -331,13 +338,11 @@ void ath9k_wiphy_chan_work(struct work_struct *work)
331void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb) 338void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb)
332{ 339{
333 struct ath_wiphy *aphy = hw->priv; 340 struct ath_wiphy *aphy = hw->priv;
334 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
335 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 341 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
336 struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info);
337 342
338 if (tx_info_priv && tx_info_priv->frame_type == ATH9K_INT_PAUSE && 343 if ((tx_info->pad[0] & ATH_TX_INFO_FRAME_TYPE_PAUSE) &&
339 aphy->state == ATH_WIPHY_PAUSING) { 344 aphy->state == ATH_WIPHY_PAUSING) {
340 if (!(info->flags & IEEE80211_TX_STAT_ACK)) { 345 if (!(tx_info->flags & IEEE80211_TX_STAT_ACK)) {
341 printk(KERN_DEBUG "ath9k: %s: no ACK for pause " 346 printk(KERN_DEBUG "ath9k: %s: no ACK for pause "
342 "frame\n", wiphy_name(hw->wiphy)); 347 "frame\n", wiphy_name(hw->wiphy));
343 /* 348 /*
@@ -356,9 +361,6 @@ void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb)
356 } 361 }
357 } 362 }
358 363
359 kfree(tx_info_priv);
360 tx_info->rate_driver_data[0] = NULL;
361
362 dev_kfree_skb(skb); 364 dev_kfree_skb(skb);
363} 365}
364 366
@@ -519,8 +521,9 @@ int ath9k_wiphy_select(struct ath_wiphy *aphy)
519 * frame being completed) 521 * frame being completed)
520 */ 522 */
521 spin_unlock_bh(&sc->wiphy_lock); 523 spin_unlock_bh(&sc->wiphy_lock);
522 ath_radio_disable(sc); 524 ath_radio_disable(sc, aphy->hw);
523 ath_radio_enable(sc); 525 ath_radio_enable(sc, aphy->hw);
526 /* Only the primary wiphy hw is used for queuing work */
524 ieee80211_queue_work(aphy->sc->hw, 527 ieee80211_queue_work(aphy->sc->hw,
525 &aphy->sc->chan_work); 528 &aphy->sc->chan_work);
526 return -EBUSY; /* previous select still in progress */ 529 return -EBUSY; /* previous select still in progress */
@@ -666,15 +669,78 @@ void ath9k_wiphy_set_scheduler(struct ath_softc *sc, unsigned int msec_int)
666bool ath9k_all_wiphys_idle(struct ath_softc *sc) 669bool ath9k_all_wiphys_idle(struct ath_softc *sc)
667{ 670{
668 unsigned int i; 671 unsigned int i;
669 if (sc->pri_wiphy->state != ATH_WIPHY_INACTIVE) { 672 if (!sc->pri_wiphy->idle)
670 return false; 673 return false;
671 }
672 for (i = 0; i < sc->num_sec_wiphy; i++) { 674 for (i = 0; i < sc->num_sec_wiphy; i++) {
673 struct ath_wiphy *aphy = sc->sec_wiphy[i]; 675 struct ath_wiphy *aphy = sc->sec_wiphy[i];
674 if (!aphy) 676 if (!aphy)
675 continue; 677 continue;
676 if (aphy->state != ATH_WIPHY_INACTIVE) 678 if (!aphy->idle)
677 return false; 679 return false;
678 } 680 }
679 return true; 681 return true;
680} 682}
683
684/* caller must hold wiphy_lock */
685void ath9k_set_wiphy_idle(struct ath_wiphy *aphy, bool idle)
686{
687 struct ath_softc *sc = aphy->sc;
688
689 aphy->idle = idle;
690 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
691 "Marking %s as %s\n",
692 wiphy_name(aphy->hw->wiphy),
693 idle ? "idle" : "not-idle");
694}
695/* Only bother starting a queue on an active virtual wiphy */
696void ath_mac80211_start_queue(struct ath_softc *sc, u16 skb_queue)
697{
698 struct ieee80211_hw *hw = sc->pri_wiphy->hw;
699 unsigned int i;
700
701 spin_lock_bh(&sc->wiphy_lock);
702
703 /* Start the primary wiphy */
704 if (sc->pri_wiphy->state == ATH_WIPHY_ACTIVE) {
705 ieee80211_wake_queue(hw, skb_queue);
706 goto unlock;
707 }
708
709 /* Now start the secondary wiphy queues */
710 for (i = 0; i < sc->num_sec_wiphy; i++) {
711 struct ath_wiphy *aphy = sc->sec_wiphy[i];
712 if (!aphy)
713 continue;
714 if (aphy->state != ATH_WIPHY_ACTIVE)
715 continue;
716
717 hw = aphy->hw;
718 ieee80211_wake_queue(hw, skb_queue);
719 break;
720 }
721
722unlock:
723 spin_unlock_bh(&sc->wiphy_lock);
724}
725
726/* Go ahead and propagate information to all virtual wiphys, it won't hurt */
727void ath_mac80211_stop_queue(struct ath_softc *sc, u16 skb_queue)
728{
729 struct ieee80211_hw *hw = sc->pri_wiphy->hw;
730 unsigned int i;
731
732 spin_lock_bh(&sc->wiphy_lock);
733
734 /* Stop the primary wiphy */
735 ieee80211_stop_queue(hw, skb_queue);
736
737 /* Now stop the secondary wiphy queues */
738 for (i = 0; i < sc->num_sec_wiphy; i++) {
739 struct ath_wiphy *aphy = sc->sec_wiphy[i];
740 if (!aphy)
741 continue;
742 hw = aphy->hw;
743 ieee80211_stop_queue(hw, skb_queue);
744 }
745 spin_unlock_bh(&sc->wiphy_lock);
746}
diff --git a/drivers/net/wireless/ath/ath9k/xmit.c b/drivers/net/wireless/ath/ath9k/xmit.c
index 42551a48c8ac..745d91995d78 100644
--- a/drivers/net/wireless/ath/ath9k/xmit.c
+++ b/drivers/net/wireless/ath/ath9k/xmit.c
@@ -107,7 +107,7 @@ static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
107{ 107{
108 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum]; 108 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
109 109
110 ASSERT(tid->paused > 0); 110 BUG_ON(tid->paused <= 0);
111 spin_lock_bh(&txq->axq_lock); 111 spin_lock_bh(&txq->axq_lock);
112 112
113 tid->paused--; 113 tid->paused--;
@@ -131,7 +131,7 @@ static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
131 struct list_head bf_head; 131 struct list_head bf_head;
132 INIT_LIST_HEAD(&bf_head); 132 INIT_LIST_HEAD(&bf_head);
133 133
134 ASSERT(tid->paused > 0); 134 BUG_ON(tid->paused <= 0);
135 spin_lock_bh(&txq->axq_lock); 135 spin_lock_bh(&txq->axq_lock);
136 136
137 tid->paused--; 137 tid->paused--;
@@ -143,7 +143,7 @@ static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
143 143
144 while (!list_empty(&tid->buf_q)) { 144 while (!list_empty(&tid->buf_q)) {
145 bf = list_first_entry(&tid->buf_q, struct ath_buf, list); 145 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
146 ASSERT(!bf_isretried(bf)); 146 BUG_ON(bf_isretried(bf));
147 list_move_tail(&bf->list, &bf_head); 147 list_move_tail(&bf->list, &bf_head);
148 ath_tx_send_ht_normal(sc, txq, tid, &bf_head); 148 ath_tx_send_ht_normal(sc, txq, tid, &bf_head);
149 } 149 }
@@ -178,7 +178,7 @@ static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
178 index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno); 178 index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno);
179 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 179 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
180 180
181 ASSERT(tid->tx_buf[cindex] == NULL); 181 BUG_ON(tid->tx_buf[cindex] != NULL);
182 tid->tx_buf[cindex] = bf; 182 tid->tx_buf[cindex] = bf;
183 183
184 if (index >= ((tid->baw_tail - tid->baw_head) & 184 if (index >= ((tid->baw_tail - tid->baw_head) &
@@ -251,6 +251,7 @@ static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
251 251
252 ATH_TXBUF_RESET(tbf); 252 ATH_TXBUF_RESET(tbf);
253 253
254 tbf->aphy = bf->aphy;
254 tbf->bf_mpdu = bf->bf_mpdu; 255 tbf->bf_mpdu = bf->bf_mpdu;
255 tbf->bf_buf_addr = bf->bf_buf_addr; 256 tbf->bf_buf_addr = bf->bf_buf_addr;
256 *(tbf->bf_desc) = *(bf->bf_desc); 257 *(tbf->bf_desc) = *(bf->bf_desc);
@@ -267,7 +268,9 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
267 struct ath_node *an = NULL; 268 struct ath_node *an = NULL;
268 struct sk_buff *skb; 269 struct sk_buff *skb;
269 struct ieee80211_sta *sta; 270 struct ieee80211_sta *sta;
271 struct ieee80211_hw *hw;
270 struct ieee80211_hdr *hdr; 272 struct ieee80211_hdr *hdr;
273 struct ieee80211_tx_info *tx_info;
271 struct ath_atx_tid *tid = NULL; 274 struct ath_atx_tid *tid = NULL;
272 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf; 275 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
273 struct ath_desc *ds = bf_last->bf_desc; 276 struct ath_desc *ds = bf_last->bf_desc;
@@ -280,9 +283,13 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
280 skb = bf->bf_mpdu; 283 skb = bf->bf_mpdu;
281 hdr = (struct ieee80211_hdr *)skb->data; 284 hdr = (struct ieee80211_hdr *)skb->data;
282 285
286 tx_info = IEEE80211_SKB_CB(skb);
287 hw = bf->aphy->hw;
288
283 rcu_read_lock(); 289 rcu_read_lock();
284 290
285 sta = ieee80211_find_sta(sc->hw, hdr->addr1); 291 /* XXX: use ieee80211_find_sta! */
292 sta = ieee80211_find_sta_by_hw(hw, hdr->addr1);
286 if (!sta) { 293 if (!sta) {
287 rcu_read_unlock(); 294 rcu_read_unlock();
288 return; 295 return;
@@ -358,7 +365,7 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
358 else 365 else
359 INIT_LIST_HEAD(&bf_head); 366 INIT_LIST_HEAD(&bf_head);
360 } else { 367 } else {
361 ASSERT(!list_empty(bf_q)); 368 BUG_ON(list_empty(bf_q));
362 list_move_tail(&bf->list, &bf_head); 369 list_move_tail(&bf->list, &bf_head);
363 } 370 }
364 371
@@ -456,7 +463,6 @@ static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
456 struct sk_buff *skb; 463 struct sk_buff *skb;
457 struct ieee80211_tx_info *tx_info; 464 struct ieee80211_tx_info *tx_info;
458 struct ieee80211_tx_rate *rates; 465 struct ieee80211_tx_rate *rates;
459 struct ath_tx_info_priv *tx_info_priv;
460 u32 max_4ms_framelen, frmlen; 466 u32 max_4ms_framelen, frmlen;
461 u16 aggr_limit, legacy = 0; 467 u16 aggr_limit, legacy = 0;
462 int i; 468 int i;
@@ -464,7 +470,6 @@ static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
464 skb = bf->bf_mpdu; 470 skb = bf->bf_mpdu;
465 tx_info = IEEE80211_SKB_CB(skb); 471 tx_info = IEEE80211_SKB_CB(skb);
466 rates = tx_info->control.rates; 472 rates = tx_info->control.rates;
467 tx_info_priv = (struct ath_tx_info_priv *)tx_info->rate_driver_data[0];
468 473
469 /* 474 /*
470 * Find the lowest frame length among the rate series that will have a 475 * Find the lowest frame length among the rate series that will have a
@@ -694,7 +699,6 @@ static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
694 /* anchor last desc of aggregate */ 699 /* anchor last desc of aggregate */
695 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc); 700 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc);
696 701
697 txq->axq_aggr_depth++;
698 ath_tx_txqaddbuf(sc, txq, &bf_q); 702 ath_tx_txqaddbuf(sc, txq, &bf_q);
699 TX_STAT_INC(txq->axq_qnum, a_aggr); 703 TX_STAT_INC(txq->axq_qnum, a_aggr);
700 704
@@ -815,6 +819,7 @@ static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
815struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 819struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
816{ 820{
817 struct ath_hw *ah = sc->sc_ah; 821 struct ath_hw *ah = sc->sc_ah;
822 struct ath_common *common = ath9k_hw_common(ah);
818 struct ath9k_tx_queue_info qi; 823 struct ath9k_tx_queue_info qi;
819 int qnum; 824 int qnum;
820 825
@@ -854,9 +859,9 @@ struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
854 return NULL; 859 return NULL;
855 } 860 }
856 if (qnum >= ARRAY_SIZE(sc->tx.txq)) { 861 if (qnum >= ARRAY_SIZE(sc->tx.txq)) {
857 DPRINTF(sc, ATH_DBG_FATAL, 862 ath_print(common, ATH_DBG_FATAL,
858 "qnum %u out of range, max %u!\n", 863 "qnum %u out of range, max %u!\n",
859 qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq)); 864 qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq));
860 ath9k_hw_releasetxqueue(ah, qnum); 865 ath9k_hw_releasetxqueue(ah, qnum);
861 return NULL; 866 return NULL;
862 } 867 }
@@ -869,8 +874,6 @@ struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
869 INIT_LIST_HEAD(&txq->axq_acq); 874 INIT_LIST_HEAD(&txq->axq_acq);
870 spin_lock_init(&txq->axq_lock); 875 spin_lock_init(&txq->axq_lock);
871 txq->axq_depth = 0; 876 txq->axq_depth = 0;
872 txq->axq_aggr_depth = 0;
873 txq->axq_linkbuf = NULL;
874 txq->axq_tx_inprogress = false; 877 txq->axq_tx_inprogress = false;
875 sc->tx.txqsetup |= 1<<qnum; 878 sc->tx.txqsetup |= 1<<qnum;
876 } 879 }
@@ -884,9 +887,9 @@ int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
884 switch (qtype) { 887 switch (qtype) {
885 case ATH9K_TX_QUEUE_DATA: 888 case ATH9K_TX_QUEUE_DATA:
886 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) { 889 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
887 DPRINTF(sc, ATH_DBG_FATAL, 890 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
888 "HAL AC %u out of range, max %zu!\n", 891 "HAL AC %u out of range, max %zu!\n",
889 haltype, ARRAY_SIZE(sc->tx.hwq_map)); 892 haltype, ARRAY_SIZE(sc->tx.hwq_map));
890 return -1; 893 return -1;
891 } 894 }
892 qnum = sc->tx.hwq_map[haltype]; 895 qnum = sc->tx.hwq_map[haltype];
@@ -906,18 +909,19 @@ int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
906struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb) 909struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb)
907{ 910{
908 struct ath_txq *txq = NULL; 911 struct ath_txq *txq = NULL;
912 u16 skb_queue = skb_get_queue_mapping(skb);
909 int qnum; 913 int qnum;
910 914
911 qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc); 915 qnum = ath_get_hal_qnum(skb_queue, sc);
912 txq = &sc->tx.txq[qnum]; 916 txq = &sc->tx.txq[qnum];
913 917
914 spin_lock_bh(&txq->axq_lock); 918 spin_lock_bh(&txq->axq_lock);
915 919
916 if (txq->axq_depth >= (ATH_TXBUF - 20)) { 920 if (txq->axq_depth >= (ATH_TXBUF - 20)) {
917 DPRINTF(sc, ATH_DBG_XMIT, 921 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_XMIT,
918 "TX queue: %d is full, depth: %d\n", 922 "TX queue: %d is full, depth: %d\n",
919 qnum, txq->axq_depth); 923 qnum, txq->axq_depth);
920 ieee80211_stop_queue(sc->hw, skb_get_queue_mapping(skb)); 924 ath_mac80211_stop_queue(sc, skb_queue);
921 txq->stopped = 1; 925 txq->stopped = 1;
922 spin_unlock_bh(&txq->axq_lock); 926 spin_unlock_bh(&txq->axq_lock);
923 return NULL; 927 return NULL;
@@ -945,7 +949,7 @@ int ath_txq_update(struct ath_softc *sc, int qnum,
945 return 0; 949 return 0;
946 } 950 }
947 951
948 ASSERT(sc->tx.txq[qnum].axq_qnum == qnum); 952 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
949 953
950 ath9k_hw_get_txq_props(ah, qnum, &qi); 954 ath9k_hw_get_txq_props(ah, qnum, &qi);
951 qi.tqi_aifs = qinfo->tqi_aifs; 955 qi.tqi_aifs = qinfo->tqi_aifs;
@@ -955,8 +959,8 @@ int ath_txq_update(struct ath_softc *sc, int qnum,
955 qi.tqi_readyTime = qinfo->tqi_readyTime; 959 qi.tqi_readyTime = qinfo->tqi_readyTime;
956 960
957 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) { 961 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
958 DPRINTF(sc, ATH_DBG_FATAL, 962 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
959 "Unable to update hardware queue %u!\n", qnum); 963 "Unable to update hardware queue %u!\n", qnum);
960 error = -EIO; 964 error = -EIO;
961 } else { 965 } else {
962 ath9k_hw_resettxqueue(ah, qnum); 966 ath9k_hw_resettxqueue(ah, qnum);
@@ -1004,7 +1008,6 @@ void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1004 1008
1005 if (list_empty(&txq->axq_q)) { 1009 if (list_empty(&txq->axq_q)) {
1006 txq->axq_link = NULL; 1010 txq->axq_link = NULL;
1007 txq->axq_linkbuf = NULL;
1008 spin_unlock_bh(&txq->axq_lock); 1011 spin_unlock_bh(&txq->axq_lock);
1009 break; 1012 break;
1010 } 1013 }
@@ -1055,6 +1058,7 @@ void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1055void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx) 1058void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1056{ 1059{
1057 struct ath_hw *ah = sc->sc_ah; 1060 struct ath_hw *ah = sc->sc_ah;
1061 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1058 struct ath_txq *txq; 1062 struct ath_txq *txq;
1059 int i, npend = 0; 1063 int i, npend = 0;
1060 1064
@@ -1076,14 +1080,15 @@ void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1076 if (npend) { 1080 if (npend) {
1077 int r; 1081 int r;
1078 1082
1079 DPRINTF(sc, ATH_DBG_XMIT, "Unable to stop TxDMA. Reset HAL!\n"); 1083 ath_print(common, ATH_DBG_XMIT,
1084 "Unable to stop TxDMA. Reset HAL!\n");
1080 1085
1081 spin_lock_bh(&sc->sc_resetlock); 1086 spin_lock_bh(&sc->sc_resetlock);
1082 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, true); 1087 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, true);
1083 if (r) 1088 if (r)
1084 DPRINTF(sc, ATH_DBG_FATAL, 1089 ath_print(common, ATH_DBG_FATAL,
1085 "Unable to reset hardware; reset status %d\n", 1090 "Unable to reset hardware; reset status %d\n",
1086 r); 1091 r);
1087 spin_unlock_bh(&sc->sc_resetlock); 1092 spin_unlock_bh(&sc->sc_resetlock);
1088 } 1093 }
1089 1094
@@ -1147,8 +1152,8 @@ int ath_tx_setup(struct ath_softc *sc, int haltype)
1147 struct ath_txq *txq; 1152 struct ath_txq *txq;
1148 1153
1149 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) { 1154 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
1150 DPRINTF(sc, ATH_DBG_FATAL, 1155 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1151 "HAL AC %u out of range, max %zu!\n", 1156 "HAL AC %u out of range, max %zu!\n",
1152 haltype, ARRAY_SIZE(sc->tx.hwq_map)); 1157 haltype, ARRAY_SIZE(sc->tx.hwq_map));
1153 return 0; 1158 return 0;
1154 } 1159 }
@@ -1172,6 +1177,7 @@ static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1172 struct list_head *head) 1177 struct list_head *head)
1173{ 1178{
1174 struct ath_hw *ah = sc->sc_ah; 1179 struct ath_hw *ah = sc->sc_ah;
1180 struct ath_common *common = ath9k_hw_common(ah);
1175 struct ath_buf *bf; 1181 struct ath_buf *bf;
1176 1182
1177 /* 1183 /*
@@ -1186,21 +1192,20 @@ static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1186 1192
1187 list_splice_tail_init(head, &txq->axq_q); 1193 list_splice_tail_init(head, &txq->axq_q);
1188 txq->axq_depth++; 1194 txq->axq_depth++;
1189 txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list);
1190 1195
1191 DPRINTF(sc, ATH_DBG_QUEUE, 1196 ath_print(common, ATH_DBG_QUEUE,
1192 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth); 1197 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1193 1198
1194 if (txq->axq_link == NULL) { 1199 if (txq->axq_link == NULL) {
1195 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 1200 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1196 DPRINTF(sc, ATH_DBG_XMIT, 1201 ath_print(common, ATH_DBG_XMIT,
1197 "TXDP[%u] = %llx (%p)\n", 1202 "TXDP[%u] = %llx (%p)\n",
1198 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc); 1203 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1199 } else { 1204 } else {
1200 *txq->axq_link = bf->bf_daddr; 1205 *txq->axq_link = bf->bf_daddr;
1201 DPRINTF(sc, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n", 1206 ath_print(common, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n",
1202 txq->axq_qnum, txq->axq_link, 1207 txq->axq_qnum, txq->axq_link,
1203 ito64(bf->bf_daddr), bf->bf_desc); 1208 ito64(bf->bf_daddr), bf->bf_desc);
1204 } 1209 }
1205 txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link); 1210 txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link);
1206 ath9k_hw_txstart(ah, txq->axq_qnum); 1211 ath9k_hw_txstart(ah, txq->axq_qnum);
@@ -1452,6 +1457,7 @@ static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf,
1452 1457
1453static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf) 1458static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
1454{ 1459{
1460 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1455 const struct ath_rate_table *rt = sc->cur_rate_table; 1461 const struct ath_rate_table *rt = sc->cur_rate_table;
1456 struct ath9k_11n_rate_series series[4]; 1462 struct ath9k_11n_rate_series series[4];
1457 struct sk_buff *skb; 1463 struct sk_buff *skb;
@@ -1507,7 +1513,7 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
1507 1513
1508 rix = rates[i].idx; 1514 rix = rates[i].idx;
1509 series[i].Tries = rates[i].count; 1515 series[i].Tries = rates[i].count;
1510 series[i].ChSel = sc->tx_chainmask; 1516 series[i].ChSel = common->tx_chainmask;
1511 1517
1512 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) 1518 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1513 series[i].Rate = rt->info[rix].ratecode | 1519 series[i].Rate = rt->info[rix].ratecode |
@@ -1546,24 +1552,29 @@ static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf,
1546 struct ath_softc *sc = aphy->sc; 1552 struct ath_softc *sc = aphy->sc;
1547 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1553 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1548 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1554 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1549 struct ath_tx_info_priv *tx_info_priv;
1550 int hdrlen; 1555 int hdrlen;
1551 __le16 fc; 1556 __le16 fc;
1552 1557
1553 tx_info_priv = kzalloc(sizeof(*tx_info_priv), GFP_ATOMIC); 1558 tx_info->pad[0] = 0;
1554 if (unlikely(!tx_info_priv)) 1559 switch (txctl->frame_type) {
1555 return -ENOMEM; 1560 case ATH9K_NOT_INTERNAL:
1556 tx_info->rate_driver_data[0] = tx_info_priv; 1561 break;
1557 tx_info_priv->aphy = aphy; 1562 case ATH9K_INT_PAUSE:
1558 tx_info_priv->frame_type = txctl->frame_type; 1563 tx_info->pad[0] |= ATH_TX_INFO_FRAME_TYPE_PAUSE;
1564 /* fall through */
1565 case ATH9K_INT_UNPAUSE:
1566 tx_info->pad[0] |= ATH_TX_INFO_FRAME_TYPE_INTERNAL;
1567 break;
1568 }
1559 hdrlen = ieee80211_get_hdrlen_from_skb(skb); 1569 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1560 fc = hdr->frame_control; 1570 fc = hdr->frame_control;
1561 1571
1562 ATH_TXBUF_RESET(bf); 1572 ATH_TXBUF_RESET(bf);
1563 1573
1574 bf->aphy = aphy;
1564 bf->bf_frmlen = skb->len + FCS_LEN - (hdrlen & 3); 1575 bf->bf_frmlen = skb->len + FCS_LEN - (hdrlen & 3);
1565 1576
1566 if (conf_is_ht(&sc->hw->conf) && !is_pae(skb)) 1577 if (conf_is_ht(&hw->conf) && !is_pae(skb))
1567 bf->bf_state.bf_type |= BUF_HT; 1578 bf->bf_state.bf_type |= BUF_HT;
1568 1579
1569 bf->bf_flags = setup_tx_flags(sc, skb, txctl->txq); 1580 bf->bf_flags = setup_tx_flags(sc, skb, txctl->txq);
@@ -1585,9 +1596,8 @@ static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf,
1585 skb->len, DMA_TO_DEVICE); 1596 skb->len, DMA_TO_DEVICE);
1586 if (unlikely(dma_mapping_error(sc->dev, bf->bf_dmacontext))) { 1597 if (unlikely(dma_mapping_error(sc->dev, bf->bf_dmacontext))) {
1587 bf->bf_mpdu = NULL; 1598 bf->bf_mpdu = NULL;
1588 kfree(tx_info_priv); 1599 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1589 tx_info->rate_driver_data[0] = NULL; 1600 "dma_mapping_error() on TX\n");
1590 DPRINTF(sc, ATH_DBG_FATAL, "dma_mapping_error() on TX\n");
1591 return -ENOMEM; 1601 return -ENOMEM;
1592 } 1602 }
1593 1603
@@ -1669,12 +1679,13 @@ int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1669{ 1679{
1670 struct ath_wiphy *aphy = hw->priv; 1680 struct ath_wiphy *aphy = hw->priv;
1671 struct ath_softc *sc = aphy->sc; 1681 struct ath_softc *sc = aphy->sc;
1682 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1672 struct ath_buf *bf; 1683 struct ath_buf *bf;
1673 int r; 1684 int r;
1674 1685
1675 bf = ath_tx_get_buffer(sc); 1686 bf = ath_tx_get_buffer(sc);
1676 if (!bf) { 1687 if (!bf) {
1677 DPRINTF(sc, ATH_DBG_XMIT, "TX buffers are full\n"); 1688 ath_print(common, ATH_DBG_XMIT, "TX buffers are full\n");
1678 return -1; 1689 return -1;
1679 } 1690 }
1680 1691
@@ -1682,7 +1693,7 @@ int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1682 if (unlikely(r)) { 1693 if (unlikely(r)) {
1683 struct ath_txq *txq = txctl->txq; 1694 struct ath_txq *txq = txctl->txq;
1684 1695
1685 DPRINTF(sc, ATH_DBG_FATAL, "TX mem alloc failure\n"); 1696 ath_print(common, ATH_DBG_FATAL, "TX mem alloc failure\n");
1686 1697
1687 /* upon ath_tx_processq() this TX queue will be resumed, we 1698 /* upon ath_tx_processq() this TX queue will be resumed, we
1688 * guarantee this will happen by knowing beforehand that 1699 * guarantee this will happen by knowing beforehand that
@@ -1690,8 +1701,7 @@ int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1690 * on the queue */ 1701 * on the queue */
1691 spin_lock_bh(&txq->axq_lock); 1702 spin_lock_bh(&txq->axq_lock);
1692 if (sc->tx.txq[txq->axq_qnum].axq_depth > 1) { 1703 if (sc->tx.txq[txq->axq_qnum].axq_depth > 1) {
1693 ieee80211_stop_queue(sc->hw, 1704 ath_mac80211_stop_queue(sc, skb_get_queue_mapping(skb));
1694 skb_get_queue_mapping(skb));
1695 txq->stopped = 1; 1705 txq->stopped = 1;
1696 } 1706 }
1697 spin_unlock_bh(&txq->axq_lock); 1707 spin_unlock_bh(&txq->axq_lock);
@@ -1712,6 +1722,7 @@ void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
1712{ 1722{
1713 struct ath_wiphy *aphy = hw->priv; 1723 struct ath_wiphy *aphy = hw->priv;
1714 struct ath_softc *sc = aphy->sc; 1724 struct ath_softc *sc = aphy->sc;
1725 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1715 int hdrlen, padsize; 1726 int hdrlen, padsize;
1716 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1727 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1717 struct ath_tx_control txctl; 1728 struct ath_tx_control txctl;
@@ -1736,7 +1747,8 @@ void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
1736 if (hdrlen & 3) { 1747 if (hdrlen & 3) {
1737 padsize = hdrlen % 4; 1748 padsize = hdrlen % 4;
1738 if (skb_headroom(skb) < padsize) { 1749 if (skb_headroom(skb) < padsize) {
1739 DPRINTF(sc, ATH_DBG_XMIT, "TX CABQ padding failed\n"); 1750 ath_print(common, ATH_DBG_XMIT,
1751 "TX CABQ padding failed\n");
1740 dev_kfree_skb_any(skb); 1752 dev_kfree_skb_any(skb);
1741 return; 1753 return;
1742 } 1754 }
@@ -1746,10 +1758,11 @@ void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
1746 1758
1747 txctl.txq = sc->beacon.cabq; 1759 txctl.txq = sc->beacon.cabq;
1748 1760
1749 DPRINTF(sc, ATH_DBG_XMIT, "transmitting CABQ packet, skb: %p\n", skb); 1761 ath_print(common, ATH_DBG_XMIT,
1762 "transmitting CABQ packet, skb: %p\n", skb);
1750 1763
1751 if (ath_tx_start(hw, skb, &txctl) != 0) { 1764 if (ath_tx_start(hw, skb, &txctl) != 0) {
1752 DPRINTF(sc, ATH_DBG_XMIT, "CABQ TX failed\n"); 1765 ath_print(common, ATH_DBG_XMIT, "CABQ TX failed\n");
1753 goto exit; 1766 goto exit;
1754 } 1767 }
1755 1768
@@ -1763,26 +1776,17 @@ exit:
1763/*****************/ 1776/*****************/
1764 1777
1765static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, 1778static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1766 int tx_flags) 1779 struct ath_wiphy *aphy, int tx_flags)
1767{ 1780{
1768 struct ieee80211_hw *hw = sc->hw; 1781 struct ieee80211_hw *hw = sc->hw;
1769 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1782 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1770 struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info); 1783 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1771 int hdrlen, padsize; 1784 int hdrlen, padsize;
1772 int frame_type = ATH9K_NOT_INTERNAL;
1773 1785
1774 DPRINTF(sc, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb); 1786 ath_print(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
1775 1787
1776 if (tx_info_priv) { 1788 if (aphy)
1777 hw = tx_info_priv->aphy->hw; 1789 hw = aphy->hw;
1778 frame_type = tx_info_priv->frame_type;
1779 }
1780
1781 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK ||
1782 tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED) {
1783 kfree(tx_info_priv);
1784 tx_info->rate_driver_data[0] = NULL;
1785 }
1786 1790
1787 if (tx_flags & ATH_TX_BAR) 1791 if (tx_flags & ATH_TX_BAR)
1788 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK; 1792 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
@@ -1805,18 +1809,19 @@ static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1805 1809
1806 if (sc->sc_flags & SC_OP_WAIT_FOR_TX_ACK) { 1810 if (sc->sc_flags & SC_OP_WAIT_FOR_TX_ACK) {
1807 sc->sc_flags &= ~SC_OP_WAIT_FOR_TX_ACK; 1811 sc->sc_flags &= ~SC_OP_WAIT_FOR_TX_ACK;
1808 DPRINTF(sc, ATH_DBG_PS, "Going back to sleep after having " 1812 ath_print(common, ATH_DBG_PS,
1809 "received TX status (0x%x)\n", 1813 "Going back to sleep after having "
1814 "received TX status (0x%x)\n",
1810 sc->sc_flags & (SC_OP_WAIT_FOR_BEACON | 1815 sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
1811 SC_OP_WAIT_FOR_CAB | 1816 SC_OP_WAIT_FOR_CAB |
1812 SC_OP_WAIT_FOR_PSPOLL_DATA | 1817 SC_OP_WAIT_FOR_PSPOLL_DATA |
1813 SC_OP_WAIT_FOR_TX_ACK)); 1818 SC_OP_WAIT_FOR_TX_ACK));
1814 } 1819 }
1815 1820
1816 if (frame_type == ATH9K_NOT_INTERNAL) 1821 if (unlikely(tx_info->pad[0] & ATH_TX_INFO_FRAME_TYPE_INTERNAL))
1817 ieee80211_tx_status(hw, skb);
1818 else
1819 ath9k_tx_status(hw, skb); 1822 ath9k_tx_status(hw, skb);
1823 else
1824 ieee80211_tx_status(hw, skb);
1820} 1825}
1821 1826
1822static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, 1827static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
@@ -1839,7 +1844,7 @@ static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
1839 } 1844 }
1840 1845
1841 dma_unmap_single(sc->dev, bf->bf_dmacontext, skb->len, DMA_TO_DEVICE); 1846 dma_unmap_single(sc->dev, bf->bf_dmacontext, skb->len, DMA_TO_DEVICE);
1842 ath_tx_complete(sc, skb, tx_flags); 1847 ath_tx_complete(sc, skb, bf->aphy, tx_flags);
1843 ath_debug_stat_tx(sc, txq, bf); 1848 ath_debug_stat_tx(sc, txq, bf);
1844 1849
1845 /* 1850 /*
@@ -1887,8 +1892,7 @@ static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds,
1887 struct sk_buff *skb = bf->bf_mpdu; 1892 struct sk_buff *skb = bf->bf_mpdu;
1888 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1893 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1889 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1894 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1890 struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info); 1895 struct ieee80211_hw *hw = bf->aphy->hw;
1891 struct ieee80211_hw *hw = tx_info_priv->aphy->hw;
1892 u8 i, tx_rateindex; 1896 u8 i, tx_rateindex;
1893 1897
1894 if (txok) 1898 if (txok)
@@ -1897,17 +1901,22 @@ static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds,
1897 tx_rateindex = ds->ds_txstat.ts_rateindex; 1901 tx_rateindex = ds->ds_txstat.ts_rateindex;
1898 WARN_ON(tx_rateindex >= hw->max_rates); 1902 WARN_ON(tx_rateindex >= hw->max_rates);
1899 1903
1900 tx_info_priv->update_rc = update_rc; 1904 if (update_rc)
1905 tx_info->pad[0] |= ATH_TX_INFO_UPDATE_RC;
1901 if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) 1906 if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT)
1902 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED; 1907 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1903 1908
1904 if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 && 1909 if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 &&
1905 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) { 1910 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) {
1906 if (ieee80211_is_data(hdr->frame_control)) { 1911 if (ieee80211_is_data(hdr->frame_control)) {
1907 memcpy(&tx_info_priv->tx, &ds->ds_txstat, 1912 if (ds->ds_txstat.ts_flags &
1908 sizeof(tx_info_priv->tx)); 1913 (ATH9K_TX_DATA_UNDERRUN | ATH9K_TX_DELIM_UNDERRUN))
1909 tx_info_priv->n_frames = bf->bf_nframes; 1914 tx_info->pad[0] |= ATH_TX_INFO_UNDERRUN;
1910 tx_info_priv->n_bad_frames = nbad; 1915 if ((ds->ds_txstat.ts_status & ATH9K_TXERR_XRETRY) ||
1916 (ds->ds_txstat.ts_status & ATH9K_TXERR_FIFO))
1917 tx_info->pad[0] |= ATH_TX_INFO_XRETRY;
1918 tx_info->status.ampdu_len = bf->bf_nframes;
1919 tx_info->status.ampdu_ack_len = bf->bf_nframes - nbad;
1911 } 1920 }
1912 } 1921 }
1913 1922
@@ -1926,7 +1935,7 @@ static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq)
1926 sc->tx.txq[txq->axq_qnum].axq_depth <= (ATH_TXBUF - 20)) { 1935 sc->tx.txq[txq->axq_qnum].axq_depth <= (ATH_TXBUF - 20)) {
1927 qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc); 1936 qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc);
1928 if (qnum != -1) { 1937 if (qnum != -1) {
1929 ieee80211_wake_queue(sc->hw, qnum); 1938 ath_mac80211_start_queue(sc, qnum);
1930 txq->stopped = 0; 1939 txq->stopped = 0;
1931 } 1940 }
1932 } 1941 }
@@ -1936,21 +1945,21 @@ static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq)
1936static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 1945static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
1937{ 1946{
1938 struct ath_hw *ah = sc->sc_ah; 1947 struct ath_hw *ah = sc->sc_ah;
1948 struct ath_common *common = ath9k_hw_common(ah);
1939 struct ath_buf *bf, *lastbf, *bf_held = NULL; 1949 struct ath_buf *bf, *lastbf, *bf_held = NULL;
1940 struct list_head bf_head; 1950 struct list_head bf_head;
1941 struct ath_desc *ds; 1951 struct ath_desc *ds;
1942 int txok; 1952 int txok;
1943 int status; 1953 int status;
1944 1954
1945 DPRINTF(sc, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n", 1955 ath_print(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
1946 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum), 1956 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
1947 txq->axq_link); 1957 txq->axq_link);
1948 1958
1949 for (;;) { 1959 for (;;) {
1950 spin_lock_bh(&txq->axq_lock); 1960 spin_lock_bh(&txq->axq_lock);
1951 if (list_empty(&txq->axq_q)) { 1961 if (list_empty(&txq->axq_q)) {
1952 txq->axq_link = NULL; 1962 txq->axq_link = NULL;
1953 txq->axq_linkbuf = NULL;
1954 spin_unlock_bh(&txq->axq_lock); 1963 spin_unlock_bh(&txq->axq_lock);
1955 break; 1964 break;
1956 } 1965 }
@@ -1984,10 +1993,6 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
1984 spin_unlock_bh(&txq->axq_lock); 1993 spin_unlock_bh(&txq->axq_lock);
1985 break; 1994 break;
1986 } 1995 }
1987 if (bf->bf_desc == txq->axq_lastdsWithCTS)
1988 txq->axq_lastdsWithCTS = NULL;
1989 if (ds == txq->axq_gatingds)
1990 txq->axq_gatingds = NULL;
1991 1996
1992 /* 1997 /*
1993 * Remove ath_buf's of the same transmit unit from txq, 1998 * Remove ath_buf's of the same transmit unit from txq,
@@ -2001,9 +2006,6 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2001 &txq->axq_q, lastbf->list.prev); 2006 &txq->axq_q, lastbf->list.prev);
2002 2007
2003 txq->axq_depth--; 2008 txq->axq_depth--;
2004 if (bf_isaggr(bf))
2005 txq->axq_aggr_depth--;
2006
2007 txok = (ds->ds_txstat.ts_status == 0); 2009 txok = (ds->ds_txstat.ts_status == 0);
2008 txq->axq_tx_inprogress = false; 2010 txq->axq_tx_inprogress = false;
2009 spin_unlock_bh(&txq->axq_lock); 2011 spin_unlock_bh(&txq->axq_lock);
@@ -2064,8 +2066,11 @@ static void ath_tx_complete_poll_work(struct work_struct *work)
2064 } 2066 }
2065 2067
2066 if (needreset) { 2068 if (needreset) {
2067 DPRINTF(sc, ATH_DBG_RESET, "tx hung, resetting the chip\n"); 2069 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
2070 "tx hung, resetting the chip\n");
2071 ath9k_ps_wakeup(sc);
2068 ath_reset(sc, false); 2072 ath_reset(sc, false);
2073 ath9k_ps_restore(sc);
2069 } 2074 }
2070 2075
2071 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 2076 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
@@ -2093,6 +2098,7 @@ void ath_tx_tasklet(struct ath_softc *sc)
2093 2098
2094int ath_tx_init(struct ath_softc *sc, int nbufs) 2099int ath_tx_init(struct ath_softc *sc, int nbufs)
2095{ 2100{
2101 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2096 int error = 0; 2102 int error = 0;
2097 2103
2098 spin_lock_init(&sc->tx.txbuflock); 2104 spin_lock_init(&sc->tx.txbuflock);
@@ -2100,16 +2106,16 @@ int ath_tx_init(struct ath_softc *sc, int nbufs)
2100 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf, 2106 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2101 "tx", nbufs, 1); 2107 "tx", nbufs, 1);
2102 if (error != 0) { 2108 if (error != 0) {
2103 DPRINTF(sc, ATH_DBG_FATAL, 2109 ath_print(common, ATH_DBG_FATAL,
2104 "Failed to allocate tx descriptors: %d\n", error); 2110 "Failed to allocate tx descriptors: %d\n", error);
2105 goto err; 2111 goto err;
2106 } 2112 }
2107 2113
2108 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf, 2114 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2109 "beacon", ATH_BCBUF, 1); 2115 "beacon", ATH_BCBUF, 1);
2110 if (error != 0) { 2116 if (error != 0) {
2111 DPRINTF(sc, ATH_DBG_FATAL, 2117 ath_print(common, ATH_DBG_FATAL,
2112 "Failed to allocate beacon descriptors: %d\n", error); 2118 "Failed to allocate beacon descriptors: %d\n", error);
2113 goto err; 2119 goto err;
2114 } 2120 }
2115 2121
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-15 14:24:46 -0500