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-rw-r--r--drivers/net/wireless/ath/ath9k/Makefile16
-rw-r--r--drivers/net/wireless/ath/ath9k/ani.c217
-rw-r--r--drivers/net/wireless/ath/ath9k/ani.h1
-rw-r--r--drivers/net/wireless/ath/ath9k/ar5008_initvals.h742
-rw-r--r--drivers/net/wireless/ath/ath9k/ar5008_phy.c1374
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9001_initvals.h1254
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9002_calib.c1000
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9002_hw.c598
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9002_initvals.h (renamed from drivers/net/wireless/ath/ath9k/initvals.h)2060
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9002_mac.c480
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9002_phy.c535
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9002_phy.h572
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_calib.c803
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_eeprom.c1860
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_eeprom.h323
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_hw.c205
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_initvals.h1784
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_mac.c614
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_mac.h120
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_phy.c1134
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_phy.h847
-rw-r--r--drivers/net/wireless/ath/ath9k/ath9k.h24
-rw-r--r--drivers/net/wireless/ath/ath9k/beacon.c5
-rw-r--r--drivers/net/wireless/ath/ath9k/calib.c1089
-rw-r--r--drivers/net/wireless/ath/ath9k/calib.h19
-rw-r--r--drivers/net/wireless/ath/ath9k/common.c1
-rw-r--r--drivers/net/wireless/ath/ath9k/common.h4
-rw-r--r--drivers/net/wireless/ath/ath9k/debug.c22
-rw-r--r--drivers/net/wireless/ath/ath9k/debug.h4
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom.c9
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom.h25
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_4k.c17
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_9287.c9
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_def.c15
-rw-r--r--drivers/net/wireless/ath/ath9k/hif_usb.c148
-rw-r--r--drivers/net/wireless/ath/ath9k/hif_usb.h1
-rw-r--r--drivers/net/wireless/ath/ath9k/htc.h21
-rw-r--r--drivers/net/wireless/ath/ath9k/htc_drv_beacon.c29
-rw-r--r--drivers/net/wireless/ath/ath9k/htc_drv_init.c112
-rw-r--r--drivers/net/wireless/ath/ath9k/htc_drv_main.c104
-rw-r--r--drivers/net/wireless/ath/ath9k/htc_drv_txrx.c66
-rw-r--r--drivers/net/wireless/ath/ath9k/htc_hst.c13
-rw-r--r--drivers/net/wireless/ath/ath9k/htc_hst.h24
-rw-r--r--drivers/net/wireless/ath/ath9k/hw-ops.h280
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.c1786
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.h261
-rw-r--r--drivers/net/wireless/ath/ath9k/init.c83
-rw-r--r--drivers/net/wireless/ath/ath9k/mac.c492
-rw-r--r--drivers/net/wireless/ath/ath9k/mac.h67
-rw-r--r--drivers/net/wireless/ath/ath9k/main.c102
-rw-r--r--drivers/net/wireless/ath/ath9k/pci.c1
-rw-r--r--drivers/net/wireless/ath/ath9k/phy.c978
-rw-r--r--drivers/net/wireless/ath/ath9k/phy.h584
-rw-r--r--drivers/net/wireless/ath/ath9k/rc.c13
-rw-r--r--drivers/net/wireless/ath/ath9k/recv.c518
-rw-r--r--drivers/net/wireless/ath/ath9k/reg.h167
-rw-r--r--drivers/net/wireless/ath/ath9k/wmi.c19
-rw-r--r--drivers/net/wireless/ath/ath9k/wmi.h23
-rw-r--r--drivers/net/wireless/ath/ath9k/xmit.c490
59 files changed, 16998 insertions, 7166 deletions
diff --git a/drivers/net/wireless/ath/ath9k/Makefile b/drivers/net/wireless/ath/ath9k/Makefile
index 97133beda269..dd112be218ab 100644
--- a/drivers/net/wireless/ath/ath9k/Makefile
+++ b/drivers/net/wireless/ath/ath9k/Makefile
@@ -13,16 +13,26 @@ ath9k-$(CONFIG_ATH9K_DEBUGFS) += debug.o
13 13
14obj-$(CONFIG_ATH9K) += ath9k.o 14obj-$(CONFIG_ATH9K) += ath9k.o
15 15
16ath9k_hw-y:= hw.o \ 16ath9k_hw-y:= \
17 ar9002_hw.o \
18 ar9003_hw.o \
19 hw.o \
20 ar9003_phy.o \
21 ar9002_phy.o \
22 ar5008_phy.o \
23 ar9002_calib.o \
24 ar9003_calib.o \
25 calib.o \
17 eeprom.o \ 26 eeprom.o \
18 eeprom_def.o \ 27 eeprom_def.o \
19 eeprom_4k.o \ 28 eeprom_4k.o \
20 eeprom_9287.o \ 29 eeprom_9287.o \
21 calib.o \
22 ani.o \ 30 ani.o \
23 phy.o \
24 btcoex.o \ 31 btcoex.o \
25 mac.o \ 32 mac.o \
33 ar9002_mac.o \
34 ar9003_mac.o \
35 ar9003_eeprom.o
26 36
27obj-$(CONFIG_ATH9K_HW) += ath9k_hw.o 37obj-$(CONFIG_ATH9K_HW) += ath9k_hw.o
28 38
diff --git a/drivers/net/wireless/ath/ath9k/ani.c b/drivers/net/wireless/ath/ath9k/ani.c
index 2a0cd64c2bfb..ba8b20f01594 100644
--- a/drivers/net/wireless/ath/ath9k/ani.c
+++ b/drivers/net/wireless/ath/ath9k/ani.c
@@ -15,6 +15,7 @@
15 */ 15 */
16 16
17#include "hw.h" 17#include "hw.h"
18#include "hw-ops.h"
18 19
19static int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah, 20static int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah,
20 struct ath9k_channel *chan) 21 struct ath9k_channel *chan)
@@ -37,190 +38,6 @@ static int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah,
37 return 0; 38 return 0;
38} 39}
39 40
40static bool ath9k_hw_ani_control(struct ath_hw *ah,
41 enum ath9k_ani_cmd cmd, int param)
42{
43 struct ar5416AniState *aniState = ah->curani;
44 struct ath_common *common = ath9k_hw_common(ah);
45
46 switch (cmd & ah->ani_function) {
47 case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
48 u32 level = param;
49
50 if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
51 ath_print(common, ATH_DBG_ANI,
52 "level out of range (%u > %u)\n",
53 level,
54 (unsigned)ARRAY_SIZE(ah->totalSizeDesired));
55 return false;
56 }
57
58 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
59 AR_PHY_DESIRED_SZ_TOT_DES,
60 ah->totalSizeDesired[level]);
61 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
62 AR_PHY_AGC_CTL1_COARSE_LOW,
63 ah->coarse_low[level]);
64 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
65 AR_PHY_AGC_CTL1_COARSE_HIGH,
66 ah->coarse_high[level]);
67 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
68 AR_PHY_FIND_SIG_FIRPWR,
69 ah->firpwr[level]);
70
71 if (level > aniState->noiseImmunityLevel)
72 ah->stats.ast_ani_niup++;
73 else if (level < aniState->noiseImmunityLevel)
74 ah->stats.ast_ani_nidown++;
75 aniState->noiseImmunityLevel = level;
76 break;
77 }
78 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
79 const int m1ThreshLow[] = { 127, 50 };
80 const int m2ThreshLow[] = { 127, 40 };
81 const int m1Thresh[] = { 127, 0x4d };
82 const int m2Thresh[] = { 127, 0x40 };
83 const int m2CountThr[] = { 31, 16 };
84 const int m2CountThrLow[] = { 63, 48 };
85 u32 on = param ? 1 : 0;
86
87 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
88 AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
89 m1ThreshLow[on]);
90 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
91 AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
92 m2ThreshLow[on]);
93 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
94 AR_PHY_SFCORR_M1_THRESH,
95 m1Thresh[on]);
96 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
97 AR_PHY_SFCORR_M2_THRESH,
98 m2Thresh[on]);
99 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
100 AR_PHY_SFCORR_M2COUNT_THR,
101 m2CountThr[on]);
102 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
103 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
104 m2CountThrLow[on]);
105
106 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
107 AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
108 m1ThreshLow[on]);
109 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
110 AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
111 m2ThreshLow[on]);
112 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
113 AR_PHY_SFCORR_EXT_M1_THRESH,
114 m1Thresh[on]);
115 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
116 AR_PHY_SFCORR_EXT_M2_THRESH,
117 m2Thresh[on]);
118
119 if (on)
120 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
121 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
122 else
123 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
124 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
125
126 if (!on != aniState->ofdmWeakSigDetectOff) {
127 if (on)
128 ah->stats.ast_ani_ofdmon++;
129 else
130 ah->stats.ast_ani_ofdmoff++;
131 aniState->ofdmWeakSigDetectOff = !on;
132 }
133 break;
134 }
135 case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
136 const int weakSigThrCck[] = { 8, 6 };
137 u32 high = param ? 1 : 0;
138
139 REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
140 AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
141 weakSigThrCck[high]);
142 if (high != aniState->cckWeakSigThreshold) {
143 if (high)
144 ah->stats.ast_ani_cckhigh++;
145 else
146 ah->stats.ast_ani_ccklow++;
147 aniState->cckWeakSigThreshold = high;
148 }
149 break;
150 }
151 case ATH9K_ANI_FIRSTEP_LEVEL:{
152 const int firstep[] = { 0, 4, 8 };
153 u32 level = param;
154
155 if (level >= ARRAY_SIZE(firstep)) {
156 ath_print(common, ATH_DBG_ANI,
157 "level out of range (%u > %u)\n",
158 level,
159 (unsigned) ARRAY_SIZE(firstep));
160 return false;
161 }
162 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
163 AR_PHY_FIND_SIG_FIRSTEP,
164 firstep[level]);
165 if (level > aniState->firstepLevel)
166 ah->stats.ast_ani_stepup++;
167 else if (level < aniState->firstepLevel)
168 ah->stats.ast_ani_stepdown++;
169 aniState->firstepLevel = level;
170 break;
171 }
172 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
173 const int cycpwrThr1[] =
174 { 2, 4, 6, 8, 10, 12, 14, 16 };
175 u32 level = param;
176
177 if (level >= ARRAY_SIZE(cycpwrThr1)) {
178 ath_print(common, ATH_DBG_ANI,
179 "level out of range (%u > %u)\n",
180 level,
181 (unsigned) ARRAY_SIZE(cycpwrThr1));
182 return false;
183 }
184 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
185 AR_PHY_TIMING5_CYCPWR_THR1,
186 cycpwrThr1[level]);
187 if (level > aniState->spurImmunityLevel)
188 ah->stats.ast_ani_spurup++;
189 else if (level < aniState->spurImmunityLevel)
190 ah->stats.ast_ani_spurdown++;
191 aniState->spurImmunityLevel = level;
192 break;
193 }
194 case ATH9K_ANI_PRESENT:
195 break;
196 default:
197 ath_print(common, ATH_DBG_ANI,
198 "invalid cmd %u\n", cmd);
199 return false;
200 }
201
202 ath_print(common, ATH_DBG_ANI, "ANI parameters:\n");
203 ath_print(common, ATH_DBG_ANI,
204 "noiseImmunityLevel=%d, spurImmunityLevel=%d, "
205 "ofdmWeakSigDetectOff=%d\n",
206 aniState->noiseImmunityLevel,
207 aniState->spurImmunityLevel,
208 !aniState->ofdmWeakSigDetectOff);
209 ath_print(common, ATH_DBG_ANI,
210 "cckWeakSigThreshold=%d, "
211 "firstepLevel=%d, listenTime=%d\n",
212 aniState->cckWeakSigThreshold,
213 aniState->firstepLevel,
214 aniState->listenTime);
215 ath_print(common, ATH_DBG_ANI,
216 "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
217 aniState->cycleCount,
218 aniState->ofdmPhyErrCount,
219 aniState->cckPhyErrCount);
220
221 return true;
222}
223
224static void ath9k_hw_update_mibstats(struct ath_hw *ah, 41static void ath9k_hw_update_mibstats(struct ath_hw *ah,
225 struct ath9k_mib_stats *stats) 42 struct ath9k_mib_stats *stats)
226{ 43{
@@ -262,11 +79,17 @@ static void ath9k_ani_restart(struct ath_hw *ah)
262 "Writing ofdmbase=%u cckbase=%u\n", 79 "Writing ofdmbase=%u cckbase=%u\n",
263 aniState->ofdmPhyErrBase, 80 aniState->ofdmPhyErrBase,
264 aniState->cckPhyErrBase); 81 aniState->cckPhyErrBase);
82
83 ENABLE_REGWRITE_BUFFER(ah);
84
265 REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase); 85 REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase);
266 REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase); 86 REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase);
267 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 87 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
268 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 88 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
269 89
90 REGWRITE_BUFFER_FLUSH(ah);
91 DISABLE_REGWRITE_BUFFER(ah);
92
270 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); 93 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
271 94
272 aniState->ofdmPhyErrCount = 0; 95 aniState->ofdmPhyErrCount = 0;
@@ -540,8 +363,14 @@ void ath9k_ani_reset(struct ath_hw *ah)
540 ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) & 363 ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) &
541 ~ATH9K_RX_FILTER_PHYERR); 364 ~ATH9K_RX_FILTER_PHYERR);
542 ath9k_ani_restart(ah); 365 ath9k_ani_restart(ah);
366
367 ENABLE_REGWRITE_BUFFER(ah);
368
543 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 369 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
544 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 370 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
371
372 REGWRITE_BUFFER_FLUSH(ah);
373 DISABLE_REGWRITE_BUFFER(ah);
545} 374}
546 375
547void ath9k_hw_ani_monitor(struct ath_hw *ah, 376void ath9k_hw_ani_monitor(struct ath_hw *ah,
@@ -639,6 +468,8 @@ void ath9k_enable_mib_counters(struct ath_hw *ah)
639 468
640 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); 469 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
641 470
471 ENABLE_REGWRITE_BUFFER(ah);
472
642 REG_WRITE(ah, AR_FILT_OFDM, 0); 473 REG_WRITE(ah, AR_FILT_OFDM, 0);
643 REG_WRITE(ah, AR_FILT_CCK, 0); 474 REG_WRITE(ah, AR_FILT_CCK, 0);
644 REG_WRITE(ah, AR_MIBC, 475 REG_WRITE(ah, AR_MIBC,
@@ -646,6 +477,9 @@ void ath9k_enable_mib_counters(struct ath_hw *ah)
646 & 0x0f); 477 & 0x0f);
647 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 478 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
648 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 479 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
480
481 REGWRITE_BUFFER_FLUSH(ah);
482 DISABLE_REGWRITE_BUFFER(ah);
649} 483}
650 484
651/* Freeze the MIB counters, get the stats and then clear them */ 485/* Freeze the MIB counters, get the stats and then clear them */
@@ -809,20 +643,17 @@ void ath9k_hw_ani_init(struct ath_hw *ah)
809 ath_print(common, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n", 643 ath_print(common, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n",
810 ah->ani[0].cckPhyErrBase); 644 ah->ani[0].cckPhyErrBase);
811 645
646 ENABLE_REGWRITE_BUFFER(ah);
647
812 REG_WRITE(ah, AR_PHY_ERR_1, ah->ani[0].ofdmPhyErrBase); 648 REG_WRITE(ah, AR_PHY_ERR_1, ah->ani[0].ofdmPhyErrBase);
813 REG_WRITE(ah, AR_PHY_ERR_2, ah->ani[0].cckPhyErrBase); 649 REG_WRITE(ah, AR_PHY_ERR_2, ah->ani[0].cckPhyErrBase);
650
651 REGWRITE_BUFFER_FLUSH(ah);
652 DISABLE_REGWRITE_BUFFER(ah);
653
814 ath9k_enable_mib_counters(ah); 654 ath9k_enable_mib_counters(ah);
815 655
816 ah->aniperiod = ATH9K_ANI_PERIOD; 656 ah->aniperiod = ATH9K_ANI_PERIOD;
817 if (ah->config.enable_ani) 657 if (ah->config.enable_ani)
818 ah->proc_phyerr |= HAL_PROCESS_ANI; 658 ah->proc_phyerr |= HAL_PROCESS_ANI;
819} 659}
820
821void ath9k_hw_ani_disable(struct ath_hw *ah)
822{
823 ath_print(ath9k_hw_common(ah), ATH_DBG_ANI, "Disabling ANI\n");
824
825 ath9k_hw_disable_mib_counters(ah);
826 REG_WRITE(ah, AR_PHY_ERR_1, 0);
827 REG_WRITE(ah, AR_PHY_ERR_2, 0);
828}
diff --git a/drivers/net/wireless/ath/ath9k/ani.h b/drivers/net/wireless/ath/ath9k/ani.h
index 4e1ab94a5153..3356762ea384 100644
--- a/drivers/net/wireless/ath/ath9k/ani.h
+++ b/drivers/net/wireless/ath/ath9k/ani.h
@@ -118,6 +118,5 @@ u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hw *ah, u32 *rxc_pcnt,
118void ath9k_hw_procmibevent(struct ath_hw *ah); 118void ath9k_hw_procmibevent(struct ath_hw *ah);
119void ath9k_hw_ani_setup(struct ath_hw *ah); 119void ath9k_hw_ani_setup(struct ath_hw *ah);
120void ath9k_hw_ani_init(struct ath_hw *ah); 120void ath9k_hw_ani_init(struct ath_hw *ah);
121void ath9k_hw_ani_disable(struct ath_hw *ah);
122 121
123#endif /* ANI_H */ 122#endif /* ANI_H */
diff --git a/drivers/net/wireless/ath/ath9k/ar5008_initvals.h b/drivers/net/wireless/ath/ath9k/ar5008_initvals.h
new file mode 100644
index 000000000000..025c31ac6146
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/ar5008_initvals.h
@@ -0,0 +1,742 @@
1/*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef INITVALS_AR5008_H
18#define INITVALS_AR5008_H
19
20static const u32 ar5416Modes[][6] = {
21 { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
22 { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
23 { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
24 { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },
25 { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
26 { 0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf },
27 { 0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810, 0x08f04810 },
28 { 0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a, 0x0000320a },
29 { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
30 { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
31 { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
32 { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
33 { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
34 { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
35 { 0x00009844, 0x1372161e, 0x1372161e, 0x137216a0, 0x137216a0, 0x137216a0 },
36 { 0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
37 { 0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
38 { 0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
39 { 0x00009850, 0x6c48b4e0, 0x6d48b4e0, 0x6d48b0de, 0x6c48b0de, 0x6c48b0de },
40 { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e },
41 { 0x0000985c, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e, 0x31395d5e },
42 { 0x00009860, 0x00049d18, 0x00049d18, 0x00049d18, 0x00049d18, 0x00049d18 },
43 { 0x00009864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
44 { 0x00009868, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190 },
45 { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 },
46 { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
47 { 0x00009918, 0x000001b8, 0x00000370, 0x00000268, 0x00000134, 0x00000134 },
48 { 0x00009924, 0xd0058a0b, 0xd0058a0b, 0xd0058a0b, 0xd0058a0b, 0xd0058a0b },
49 { 0x00009944, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020 },
50 { 0x00009960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80, 0x00012d80 },
51 { 0x0000a960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80, 0x00012d80 },
52 { 0x0000b960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80, 0x00012d80 },
53 { 0x00009964, 0x00000000, 0x00000000, 0x00001120, 0x00001120, 0x00001120 },
54 { 0x000099bc, 0x001a0a00, 0x001a0a00, 0x001a0a00, 0x001a0a00, 0x001a0a00 },
55 { 0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, 0x038919be },
56 { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
57 { 0x000099c8, 0x6af6532c, 0x6af6532c, 0x6af6532c, 0x6af6532c, 0x6af6532c },
58 { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
59 { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
60 { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
61 { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
62 { 0x0000a204, 0x00000880, 0x00000880, 0x00000880, 0x00000880, 0x00000880 },
63 { 0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788, 0xd03e4788 },
64 { 0x0000a20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 },
65 { 0x0000b20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 },
66 { 0x0000c20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 },
67 { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
68 { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
69 { 0x0000a274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa, 0x0a1a7caa },
70 { 0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 },
71 { 0x0000a304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402, 0x2e032402 },
72 { 0x0000a308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06, 0x4a0a3c06 },
73 { 0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b, 0x621a540b },
74 { 0x0000a310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b, 0x764f6c1b },
75 { 0x0000a314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a, 0x845b7a5a },
76 { 0x0000a318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf, 0x950f8ccf },
77 { 0x0000a31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f, 0xa5cf9b4f },
78 { 0x0000a320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f, 0xbddfaf1f },
79 { 0x0000a324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f, 0xd1ffc93f },
80 { 0x0000a328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000, 0x00000000 },
81 { 0x0000a32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
82 { 0x0000a330, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
83 { 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
84};
85
86static const u32 ar5416Common[][2] = {
87 { 0x0000000c, 0x00000000 },
88 { 0x00000030, 0x00020015 },
89 { 0x00000034, 0x00000005 },
90 { 0x00000040, 0x00000000 },
91 { 0x00000044, 0x00000008 },
92 { 0x00000048, 0x00000008 },
93 { 0x0000004c, 0x00000010 },
94 { 0x00000050, 0x00000000 },
95 { 0x00000054, 0x0000001f },
96 { 0x00000800, 0x00000000 },
97 { 0x00000804, 0x00000000 },
98 { 0x00000808, 0x00000000 },
99 { 0x0000080c, 0x00000000 },
100 { 0x00000810, 0x00000000 },
101 { 0x00000814, 0x00000000 },
102 { 0x00000818, 0x00000000 },
103 { 0x0000081c, 0x00000000 },
104 { 0x00000820, 0x00000000 },
105 { 0x00000824, 0x00000000 },
106 { 0x00001040, 0x002ffc0f },
107 { 0x00001044, 0x002ffc0f },
108 { 0x00001048, 0x002ffc0f },
109 { 0x0000104c, 0x002ffc0f },
110 { 0x00001050, 0x002ffc0f },
111 { 0x00001054, 0x002ffc0f },
112 { 0x00001058, 0x002ffc0f },
113 { 0x0000105c, 0x002ffc0f },
114 { 0x00001060, 0x002ffc0f },
115 { 0x00001064, 0x002ffc0f },
116 { 0x00001230, 0x00000000 },
117 { 0x00001270, 0x00000000 },
118 { 0x00001038, 0x00000000 },
119 { 0x00001078, 0x00000000 },
120 { 0x000010b8, 0x00000000 },
121 { 0x000010f8, 0x00000000 },
122 { 0x00001138, 0x00000000 },
123 { 0x00001178, 0x00000000 },
124 { 0x000011b8, 0x00000000 },
125 { 0x000011f8, 0x00000000 },
126 { 0x00001238, 0x00000000 },
127 { 0x00001278, 0x00000000 },
128 { 0x000012b8, 0x00000000 },
129 { 0x000012f8, 0x00000000 },
130 { 0x00001338, 0x00000000 },
131 { 0x00001378, 0x00000000 },
132 { 0x000013b8, 0x00000000 },
133 { 0x000013f8, 0x00000000 },
134 { 0x00001438, 0x00000000 },
135 { 0x00001478, 0x00000000 },
136 { 0x000014b8, 0x00000000 },
137 { 0x000014f8, 0x00000000 },
138 { 0x00001538, 0x00000000 },
139 { 0x00001578, 0x00000000 },
140 { 0x000015b8, 0x00000000 },
141 { 0x000015f8, 0x00000000 },
142 { 0x00001638, 0x00000000 },
143 { 0x00001678, 0x00000000 },
144 { 0x000016b8, 0x00000000 },
145 { 0x000016f8, 0x00000000 },
146 { 0x00001738, 0x00000000 },
147 { 0x00001778, 0x00000000 },
148 { 0x000017b8, 0x00000000 },
149 { 0x000017f8, 0x00000000 },
150 { 0x0000103c, 0x00000000 },
151 { 0x0000107c, 0x00000000 },
152 { 0x000010bc, 0x00000000 },
153 { 0x000010fc, 0x00000000 },
154 { 0x0000113c, 0x00000000 },
155 { 0x0000117c, 0x00000000 },
156 { 0x000011bc, 0x00000000 },
157 { 0x000011fc, 0x00000000 },
158 { 0x0000123c, 0x00000000 },
159 { 0x0000127c, 0x00000000 },
160 { 0x000012bc, 0x00000000 },
161 { 0x000012fc, 0x00000000 },
162 { 0x0000133c, 0x00000000 },
163 { 0x0000137c, 0x00000000 },
164 { 0x000013bc, 0x00000000 },
165 { 0x000013fc, 0x00000000 },
166 { 0x0000143c, 0x00000000 },
167 { 0x0000147c, 0x00000000 },
168 { 0x00004030, 0x00000002 },
169 { 0x0000403c, 0x00000002 },
170 { 0x00007010, 0x00000000 },
171 { 0x00007038, 0x000004c2 },
172 { 0x00008004, 0x00000000 },
173 { 0x00008008, 0x00000000 },
174 { 0x0000800c, 0x00000000 },
175 { 0x00008018, 0x00000700 },
176 { 0x00008020, 0x00000000 },
177 { 0x00008038, 0x00000000 },
178 { 0x0000803c, 0x00000000 },
179 { 0x00008048, 0x40000000 },
180 { 0x00008054, 0x00000000 },
181 { 0x00008058, 0x00000000 },
182 { 0x0000805c, 0x000fc78f },
183 { 0x00008060, 0x0000000f },
184 { 0x00008064, 0x00000000 },
185 { 0x000080c0, 0x2a82301a },
186 { 0x000080c4, 0x05dc01e0 },
187 { 0x000080c8, 0x1f402710 },
188 { 0x000080cc, 0x01f40000 },
189 { 0x000080d0, 0x00001e00 },
190 { 0x000080d4, 0x00000000 },
191 { 0x000080d8, 0x00400000 },
192 { 0x000080e0, 0xffffffff },
193 { 0x000080e4, 0x0000ffff },
194 { 0x000080e8, 0x003f3f3f },
195 { 0x000080ec, 0x00000000 },
196 { 0x000080f0, 0x00000000 },
197 { 0x000080f4, 0x00000000 },
198 { 0x000080f8, 0x00000000 },
199 { 0x000080fc, 0x00020000 },
200 { 0x00008100, 0x00020000 },
201 { 0x00008104, 0x00000001 },
202 { 0x00008108, 0x00000052 },
203 { 0x0000810c, 0x00000000 },
204 { 0x00008110, 0x00000168 },
205 { 0x00008118, 0x000100aa },
206 { 0x0000811c, 0x00003210 },
207 { 0x00008124, 0x00000000 },
208 { 0x00008128, 0x00000000 },
209 { 0x0000812c, 0x00000000 },
210 { 0x00008130, 0x00000000 },
211 { 0x00008134, 0x00000000 },
212 { 0x00008138, 0x00000000 },
213 { 0x0000813c, 0x00000000 },
214 { 0x00008144, 0xffffffff },
215 { 0x00008168, 0x00000000 },
216 { 0x0000816c, 0x00000000 },
217 { 0x00008170, 0x32143320 },
218 { 0x00008174, 0xfaa4fa50 },
219 { 0x00008178, 0x00000100 },
220 { 0x0000817c, 0x00000000 },
221 { 0x000081c4, 0x00000000 },
222 { 0x000081ec, 0x00000000 },
223 { 0x000081f0, 0x00000000 },
224 { 0x000081f4, 0x00000000 },
225 { 0x000081f8, 0x00000000 },
226 { 0x000081fc, 0x00000000 },
227 { 0x00008200, 0x00000000 },
228 { 0x00008204, 0x00000000 },
229 { 0x00008208, 0x00000000 },
230 { 0x0000820c, 0x00000000 },
231 { 0x00008210, 0x00000000 },
232 { 0x00008214, 0x00000000 },
233 { 0x00008218, 0x00000000 },
234 { 0x0000821c, 0x00000000 },
235 { 0x00008220, 0x00000000 },
236 { 0x00008224, 0x00000000 },
237 { 0x00008228, 0x00000000 },
238 { 0x0000822c, 0x00000000 },
239 { 0x00008230, 0x00000000 },
240 { 0x00008234, 0x00000000 },
241 { 0x00008238, 0x00000000 },
242 { 0x0000823c, 0x00000000 },
243 { 0x00008240, 0x00100000 },
244 { 0x00008244, 0x0010f400 },
245 { 0x00008248, 0x00000100 },
246 { 0x0000824c, 0x0001e800 },
247 { 0x00008250, 0x00000000 },
248 { 0x00008254, 0x00000000 },
249 { 0x00008258, 0x00000000 },
250 { 0x0000825c, 0x400000ff },
251 { 0x00008260, 0x00080922 },
252 { 0x00008264, 0x88000010 },
253 { 0x00008270, 0x00000000 },
254 { 0x00008274, 0x40000000 },
255 { 0x00008278, 0x003e4180 },
256 { 0x0000827c, 0x00000000 },
257 { 0x00008284, 0x0000002c },
258 { 0x00008288, 0x0000002c },
259 { 0x0000828c, 0x00000000 },
260 { 0x00008294, 0x00000000 },
261 { 0x00008298, 0x00000000 },
262 { 0x00008300, 0x00000000 },
263 { 0x00008304, 0x00000000 },
264 { 0x00008308, 0x00000000 },
265 { 0x0000830c, 0x00000000 },
266 { 0x00008310, 0x00000000 },
267 { 0x00008314, 0x00000000 },
268 { 0x00008318, 0x00000000 },
269 { 0x00008328, 0x00000000 },
270 { 0x0000832c, 0x00000007 },
271 { 0x00008330, 0x00000302 },
272 { 0x00008334, 0x00000e00 },
273 { 0x00008338, 0x00070000 },
274 { 0x0000833c, 0x00000000 },
275 { 0x00008340, 0x000107ff },
276 { 0x00009808, 0x00000000 },
277 { 0x0000980c, 0xad848e19 },
278 { 0x00009810, 0x7d14e000 },
279 { 0x00009814, 0x9c0a9f6b },
280 { 0x0000981c, 0x00000000 },
281 { 0x0000982c, 0x0000a000 },
282 { 0x00009830, 0x00000000 },
283 { 0x0000983c, 0x00200400 },
284 { 0x00009840, 0x206a002e },
285 { 0x0000984c, 0x1284233c },
286 { 0x00009854, 0x00000859 },
287 { 0x00009900, 0x00000000 },
288 { 0x00009904, 0x00000000 },
289 { 0x00009908, 0x00000000 },
290 { 0x0000990c, 0x00000000 },
291 { 0x0000991c, 0x10000fff },
292 { 0x00009920, 0x05100000 },
293 { 0x0000a920, 0x05100000 },
294 { 0x0000b920, 0x05100000 },
295 { 0x00009928, 0x00000001 },
296 { 0x0000992c, 0x00000004 },
297 { 0x00009934, 0x1e1f2022 },
298 { 0x00009938, 0x0a0b0c0d },
299 { 0x0000993c, 0x00000000 },
300 { 0x00009948, 0x9280b212 },
301 { 0x0000994c, 0x00020028 },
302 { 0x00009954, 0x5d50e188 },
303 { 0x00009958, 0x00081fff },
304 { 0x0000c95c, 0x004b6a8e },
305 { 0x0000c968, 0x000003ce },
306 { 0x00009970, 0x190fb515 },
307 { 0x00009974, 0x00000000 },
308 { 0x00009978, 0x00000001 },
309 { 0x0000997c, 0x00000000 },
310 { 0x00009980, 0x00000000 },
311 { 0x00009984, 0x00000000 },
312 { 0x00009988, 0x00000000 },
313 { 0x0000998c, 0x00000000 },
314 { 0x00009990, 0x00000000 },
315 { 0x00009994, 0x00000000 },
316 { 0x00009998, 0x00000000 },
317 { 0x0000999c, 0x00000000 },
318 { 0x000099a0, 0x00000000 },
319 { 0x000099a4, 0x00000001 },
320 { 0x000099a8, 0x001fff00 },
321 { 0x000099ac, 0x00000000 },
322 { 0x000099b0, 0x03051000 },
323 { 0x000099dc, 0x00000000 },
324 { 0x000099e0, 0x00000200 },
325 { 0x000099e4, 0xaaaaaaaa },
326 { 0x000099e8, 0x3c466478 },
327 { 0x000099ec, 0x000000aa },
328 { 0x000099fc, 0x00001042 },
329 { 0x00009b00, 0x00000000 },
330 { 0x00009b04, 0x00000001 },
331 { 0x00009b08, 0x00000002 },
332 { 0x00009b0c, 0x00000003 },
333 { 0x00009b10, 0x00000004 },
334 { 0x00009b14, 0x00000005 },
335 { 0x00009b18, 0x00000008 },
336 { 0x00009b1c, 0x00000009 },
337 { 0x00009b20, 0x0000000a },
338 { 0x00009b24, 0x0000000b },
339 { 0x00009b28, 0x0000000c },
340 { 0x00009b2c, 0x0000000d },
341 { 0x00009b30, 0x00000010 },
342 { 0x00009b34, 0x00000011 },
343 { 0x00009b38, 0x00000012 },
344 { 0x00009b3c, 0x00000013 },
345 { 0x00009b40, 0x00000014 },
346 { 0x00009b44, 0x00000015 },
347 { 0x00009b48, 0x00000018 },
348 { 0x00009b4c, 0x00000019 },
349 { 0x00009b50, 0x0000001a },
350 { 0x00009b54, 0x0000001b },
351 { 0x00009b58, 0x0000001c },
352 { 0x00009b5c, 0x0000001d },
353 { 0x00009b60, 0x00000020 },
354 { 0x00009b64, 0x00000021 },
355 { 0x00009b68, 0x00000022 },
356 { 0x00009b6c, 0x00000023 },
357 { 0x00009b70, 0x00000024 },
358 { 0x00009b74, 0x00000025 },
359 { 0x00009b78, 0x00000028 },
360 { 0x00009b7c, 0x00000029 },
361 { 0x00009b80, 0x0000002a },
362 { 0x00009b84, 0x0000002b },
363 { 0x00009b88, 0x0000002c },
364 { 0x00009b8c, 0x0000002d },
365 { 0x00009b90, 0x00000030 },
366 { 0x00009b94, 0x00000031 },
367 { 0x00009b98, 0x00000032 },
368 { 0x00009b9c, 0x00000033 },
369 { 0x00009ba0, 0x00000034 },
370 { 0x00009ba4, 0x00000035 },
371 { 0x00009ba8, 0x00000035 },
372 { 0x00009bac, 0x00000035 },
373 { 0x00009bb0, 0x00000035 },
374 { 0x00009bb4, 0x00000035 },
375 { 0x00009bb8, 0x00000035 },
376 { 0x00009bbc, 0x00000035 },
377 { 0x00009bc0, 0x00000035 },
378 { 0x00009bc4, 0x00000035 },
379 { 0x00009bc8, 0x00000035 },
380 { 0x00009bcc, 0x00000035 },
381 { 0x00009bd0, 0x00000035 },
382 { 0x00009bd4, 0x00000035 },
383 { 0x00009bd8, 0x00000035 },
384 { 0x00009bdc, 0x00000035 },
385 { 0x00009be0, 0x00000035 },
386 { 0x00009be4, 0x00000035 },
387 { 0x00009be8, 0x00000035 },
388 { 0x00009bec, 0x00000035 },
389 { 0x00009bf0, 0x00000035 },
390 { 0x00009bf4, 0x00000035 },
391 { 0x00009bf8, 0x00000010 },
392 { 0x00009bfc, 0x0000001a },
393 { 0x0000a210, 0x40806333 },
394 { 0x0000a214, 0x00106c10 },
395 { 0x0000a218, 0x009c4060 },
396 { 0x0000a220, 0x018830c6 },
397 { 0x0000a224, 0x00000400 },
398 { 0x0000a228, 0x00000bb5 },
399 { 0x0000a22c, 0x00000011 },
400 { 0x0000a234, 0x20202020 },
401 { 0x0000a238, 0x20202020 },
402 { 0x0000a23c, 0x13c889af },
403 { 0x0000a240, 0x38490a20 },
404 { 0x0000a244, 0x00007bb6 },
405 { 0x0000a248, 0x0fff3ffc },
406 { 0x0000a24c, 0x00000001 },
407 { 0x0000a250, 0x0000a000 },
408 { 0x0000a254, 0x00000000 },
409 { 0x0000a258, 0x0cc75380 },
410 { 0x0000a25c, 0x0f0f0f01 },
411 { 0x0000a260, 0xdfa91f01 },
412 { 0x0000a268, 0x00000000 },
413 { 0x0000a26c, 0x0e79e5c6 },
414 { 0x0000b26c, 0x0e79e5c6 },
415 { 0x0000c26c, 0x0e79e5c6 },
416 { 0x0000d270, 0x00820820 },
417 { 0x0000a278, 0x1ce739ce },
418 { 0x0000a27c, 0x051701ce },
419 { 0x0000a338, 0x00000000 },
420 { 0x0000a33c, 0x00000000 },
421 { 0x0000a340, 0x00000000 },
422 { 0x0000a344, 0x00000000 },
423 { 0x0000a348, 0x3fffffff },
424 { 0x0000a34c, 0x3fffffff },
425 { 0x0000a350, 0x3fffffff },
426 { 0x0000a354, 0x0003ffff },
427 { 0x0000a358, 0x79a8aa1f },
428 { 0x0000d35c, 0x07ffffef },
429 { 0x0000d360, 0x0fffffe7 },
430 { 0x0000d364, 0x17ffffe5 },
431 { 0x0000d368, 0x1fffffe4 },
432 { 0x0000d36c, 0x37ffffe3 },
433 { 0x0000d370, 0x3fffffe3 },
434 { 0x0000d374, 0x57ffffe3 },
435 { 0x0000d378, 0x5fffffe2 },
436 { 0x0000d37c, 0x7fffffe2 },
437 { 0x0000d380, 0x7f3c7bba },
438 { 0x0000d384, 0xf3307ff0 },
439 { 0x0000a388, 0x08000000 },
440 { 0x0000a38c, 0x20202020 },
441 { 0x0000a390, 0x20202020 },
442 { 0x0000a394, 0x1ce739ce },
443 { 0x0000a398, 0x000001ce },
444 { 0x0000a39c, 0x00000001 },
445 { 0x0000a3a0, 0x00000000 },
446 { 0x0000a3a4, 0x00000000 },
447 { 0x0000a3a8, 0x00000000 },
448 { 0x0000a3ac, 0x00000000 },
449 { 0x0000a3b0, 0x00000000 },
450 { 0x0000a3b4, 0x00000000 },
451 { 0x0000a3b8, 0x00000000 },
452 { 0x0000a3bc, 0x00000000 },
453 { 0x0000a3c0, 0x00000000 },
454 { 0x0000a3c4, 0x00000000 },
455 { 0x0000a3c8, 0x00000246 },
456 { 0x0000a3cc, 0x20202020 },
457 { 0x0000a3d0, 0x20202020 },
458 { 0x0000a3d4, 0x20202020 },
459 { 0x0000a3dc, 0x1ce739ce },
460 { 0x0000a3e0, 0x000001ce },
461};
462
463static const u32 ar5416Bank0[][2] = {
464 { 0x000098b0, 0x1e5795e5 },
465 { 0x000098e0, 0x02008020 },
466};
467
468static const u32 ar5416BB_RfGain[][3] = {
469 { 0x00009a00, 0x00000000, 0x00000000 },
470 { 0x00009a04, 0x00000040, 0x00000040 },
471 { 0x00009a08, 0x00000080, 0x00000080 },
472 { 0x00009a0c, 0x000001a1, 0x00000141 },
473 { 0x00009a10, 0x000001e1, 0x00000181 },
474 { 0x00009a14, 0x00000021, 0x000001c1 },
475 { 0x00009a18, 0x00000061, 0x00000001 },
476 { 0x00009a1c, 0x00000168, 0x00000041 },
477 { 0x00009a20, 0x000001a8, 0x000001a8 },
478 { 0x00009a24, 0x000001e8, 0x000001e8 },
479 { 0x00009a28, 0x00000028, 0x00000028 },
480 { 0x00009a2c, 0x00000068, 0x00000068 },
481 { 0x00009a30, 0x00000189, 0x000000a8 },
482 { 0x00009a34, 0x000001c9, 0x00000169 },
483 { 0x00009a38, 0x00000009, 0x000001a9 },
484 { 0x00009a3c, 0x00000049, 0x000001e9 },
485 { 0x00009a40, 0x00000089, 0x00000029 },
486 { 0x00009a44, 0x00000170, 0x00000069 },
487 { 0x00009a48, 0x000001b0, 0x00000190 },
488 { 0x00009a4c, 0x000001f0, 0x000001d0 },
489 { 0x00009a50, 0x00000030, 0x00000010 },
490 { 0x00009a54, 0x00000070, 0x00000050 },
491 { 0x00009a58, 0x00000191, 0x00000090 },
492 { 0x00009a5c, 0x000001d1, 0x00000151 },
493 { 0x00009a60, 0x00000011, 0x00000191 },
494 { 0x00009a64, 0x00000051, 0x000001d1 },
495 { 0x00009a68, 0x00000091, 0x00000011 },
496 { 0x00009a6c, 0x000001b8, 0x00000051 },
497 { 0x00009a70, 0x000001f8, 0x00000198 },
498 { 0x00009a74, 0x00000038, 0x000001d8 },
499 { 0x00009a78, 0x00000078, 0x00000018 },
500 { 0x00009a7c, 0x00000199, 0x00000058 },
501 { 0x00009a80, 0x000001d9, 0x00000098 },
502 { 0x00009a84, 0x00000019, 0x00000159 },
503 { 0x00009a88, 0x00000059, 0x00000199 },
504 { 0x00009a8c, 0x00000099, 0x000001d9 },
505 { 0x00009a90, 0x000000d9, 0x00000019 },
506 { 0x00009a94, 0x000000f9, 0x00000059 },
507 { 0x00009a98, 0x000000f9, 0x00000099 },
508 { 0x00009a9c, 0x000000f9, 0x000000d9 },
509 { 0x00009aa0, 0x000000f9, 0x000000f9 },
510 { 0x00009aa4, 0x000000f9, 0x000000f9 },
511 { 0x00009aa8, 0x000000f9, 0x000000f9 },
512 { 0x00009aac, 0x000000f9, 0x000000f9 },
513 { 0x00009ab0, 0x000000f9, 0x000000f9 },
514 { 0x00009ab4, 0x000000f9, 0x000000f9 },
515 { 0x00009ab8, 0x000000f9, 0x000000f9 },
516 { 0x00009abc, 0x000000f9, 0x000000f9 },
517 { 0x00009ac0, 0x000000f9, 0x000000f9 },
518 { 0x00009ac4, 0x000000f9, 0x000000f9 },
519 { 0x00009ac8, 0x000000f9, 0x000000f9 },
520 { 0x00009acc, 0x000000f9, 0x000000f9 },
521 { 0x00009ad0, 0x000000f9, 0x000000f9 },
522 { 0x00009ad4, 0x000000f9, 0x000000f9 },
523 { 0x00009ad8, 0x000000f9, 0x000000f9 },
524 { 0x00009adc, 0x000000f9, 0x000000f9 },
525 { 0x00009ae0, 0x000000f9, 0x000000f9 },
526 { 0x00009ae4, 0x000000f9, 0x000000f9 },
527 { 0x00009ae8, 0x000000f9, 0x000000f9 },
528 { 0x00009aec, 0x000000f9, 0x000000f9 },
529 { 0x00009af0, 0x000000f9, 0x000000f9 },
530 { 0x00009af4, 0x000000f9, 0x000000f9 },
531 { 0x00009af8, 0x000000f9, 0x000000f9 },
532 { 0x00009afc, 0x000000f9, 0x000000f9 },
533};
534
535static const u32 ar5416Bank1[][2] = {
536 { 0x000098b0, 0x02108421 },
537 { 0x000098ec, 0x00000008 },
538};
539
540static const u32 ar5416Bank2[][2] = {
541 { 0x000098b0, 0x0e73ff17 },
542 { 0x000098e0, 0x00000420 },
543};
544
545static const u32 ar5416Bank3[][3] = {
546 { 0x000098f0, 0x01400018, 0x01c00018 },
547};
548
549static const u32 ar5416Bank6[][3] = {
550
551 { 0x0000989c, 0x00000000, 0x00000000 },
552 { 0x0000989c, 0x00000000, 0x00000000 },
553 { 0x0000989c, 0x00000000, 0x00000000 },
554 { 0x0000989c, 0x00e00000, 0x00e00000 },
555 { 0x0000989c, 0x005e0000, 0x005e0000 },
556 { 0x0000989c, 0x00120000, 0x00120000 },
557 { 0x0000989c, 0x00620000, 0x00620000 },
558 { 0x0000989c, 0x00020000, 0x00020000 },
559 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
560 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
561 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
562 { 0x0000989c, 0x40ff0000, 0x40ff0000 },
563 { 0x0000989c, 0x005f0000, 0x005f0000 },
564 { 0x0000989c, 0x00870000, 0x00870000 },
565 { 0x0000989c, 0x00f90000, 0x00f90000 },
566 { 0x0000989c, 0x007b0000, 0x007b0000 },
567 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
568 { 0x0000989c, 0x00f50000, 0x00f50000 },
569 { 0x0000989c, 0x00dc0000, 0x00dc0000 },
570 { 0x0000989c, 0x00110000, 0x00110000 },
571 { 0x0000989c, 0x006100a8, 0x006100a8 },
572 { 0x0000989c, 0x004210a2, 0x004210a2 },
573 { 0x0000989c, 0x0014008f, 0x0014008f },
574 { 0x0000989c, 0x00c40003, 0x00c40003 },
575 { 0x0000989c, 0x003000f2, 0x003000f2 },
576 { 0x0000989c, 0x00440016, 0x00440016 },
577 { 0x0000989c, 0x00410040, 0x00410040 },
578 { 0x0000989c, 0x0001805e, 0x0001805e },
579 { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
580 { 0x0000989c, 0x000000f1, 0x000000f1 },
581 { 0x0000989c, 0x00002081, 0x00002081 },
582 { 0x0000989c, 0x000000d4, 0x000000d4 },
583 { 0x000098d0, 0x0000000f, 0x0010000f },
584};
585
586static const u32 ar5416Bank6TPC[][3] = {
587 { 0x0000989c, 0x00000000, 0x00000000 },
588 { 0x0000989c, 0x00000000, 0x00000000 },
589 { 0x0000989c, 0x00000000, 0x00000000 },
590 { 0x0000989c, 0x00e00000, 0x00e00000 },
591 { 0x0000989c, 0x005e0000, 0x005e0000 },
592 { 0x0000989c, 0x00120000, 0x00120000 },
593 { 0x0000989c, 0x00620000, 0x00620000 },
594 { 0x0000989c, 0x00020000, 0x00020000 },
595 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
596 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
597 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
598 { 0x0000989c, 0x40ff0000, 0x40ff0000 },
599 { 0x0000989c, 0x005f0000, 0x005f0000 },
600 { 0x0000989c, 0x00870000, 0x00870000 },
601 { 0x0000989c, 0x00f90000, 0x00f90000 },
602 { 0x0000989c, 0x007b0000, 0x007b0000 },
603 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
604 { 0x0000989c, 0x00f50000, 0x00f50000 },
605 { 0x0000989c, 0x00dc0000, 0x00dc0000 },
606 { 0x0000989c, 0x00110000, 0x00110000 },
607 { 0x0000989c, 0x006100a8, 0x006100a8 },
608 { 0x0000989c, 0x00423022, 0x00423022 },
609 { 0x0000989c, 0x201400df, 0x201400df },
610 { 0x0000989c, 0x00c40002, 0x00c40002 },
611 { 0x0000989c, 0x003000f2, 0x003000f2 },
612 { 0x0000989c, 0x00440016, 0x00440016 },
613 { 0x0000989c, 0x00410040, 0x00410040 },
614 { 0x0000989c, 0x0001805e, 0x0001805e },
615 { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
616 { 0x0000989c, 0x000000e1, 0x000000e1 },
617 { 0x0000989c, 0x00007081, 0x00007081 },
618 { 0x0000989c, 0x000000d4, 0x000000d4 },
619 { 0x000098d0, 0x0000000f, 0x0010000f },
620};
621
622static const u32 ar5416Bank7[][2] = {
623 { 0x0000989c, 0x00000500 },
624 { 0x0000989c, 0x00000800 },
625 { 0x000098cc, 0x0000000e },
626};
627
628static const u32 ar5416Addac[][2] = {
629 {0x0000989c, 0x00000000 },
630 {0x0000989c, 0x00000003 },
631 {0x0000989c, 0x00000000 },
632 {0x0000989c, 0x0000000c },
633 {0x0000989c, 0x00000000 },
634 {0x0000989c, 0x00000030 },
635 {0x0000989c, 0x00000000 },
636 {0x0000989c, 0x00000000 },
637 {0x0000989c, 0x00000000 },
638 {0x0000989c, 0x00000000 },
639 {0x0000989c, 0x00000000 },
640 {0x0000989c, 0x00000000 },
641 {0x0000989c, 0x00000000 },
642 {0x0000989c, 0x00000000 },
643 {0x0000989c, 0x00000000 },
644 {0x0000989c, 0x00000000 },
645 {0x0000989c, 0x00000000 },
646 {0x0000989c, 0x00000000 },
647 {0x0000989c, 0x00000060 },
648 {0x0000989c, 0x00000000 },
649 {0x0000989c, 0x00000000 },
650 {0x0000989c, 0x00000000 },
651 {0x0000989c, 0x00000000 },
652 {0x0000989c, 0x00000000 },
653 {0x0000989c, 0x00000000 },
654 {0x0000989c, 0x00000000 },
655 {0x0000989c, 0x00000000 },
656 {0x0000989c, 0x00000000 },
657 {0x0000989c, 0x00000000 },
658 {0x0000989c, 0x00000000 },
659 {0x0000989c, 0x00000000 },
660 {0x0000989c, 0x00000058 },
661 {0x0000989c, 0x00000000 },
662 {0x0000989c, 0x00000000 },
663 {0x0000989c, 0x00000000 },
664 {0x0000989c, 0x00000000 },
665 {0x000098cc, 0x00000000 },
666};
667
668static const u32 ar5416Modes_9100[][6] = {
669 { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
670 { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
671 { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
672 { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },
673 { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
674 { 0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf },
675 { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
676 { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
677 { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
678 { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
679 { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
680 { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
681 { 0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0, 0x037216a0 },
682 { 0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
683 { 0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
684 { 0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
685 { 0x00009850, 0x6d48b4e2, 0x6d48b4e2, 0x6d48b0e2, 0x6d48b0e2, 0x6d48b0e2 },
686 { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec86d2e, 0x7ec84d2e, 0x7ec82d2e },
687 { 0x0000985c, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e },
688 { 0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20, 0x00048d18 },
689 { 0x0000c864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
690 { 0x00009868, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0 },
691 { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 },
692 { 0x00009914, 0x000007d0, 0x000007d0, 0x00000898, 0x00000898, 0x000007d0 },
693 { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
694 { 0x00009924, 0xd00a8a07, 0xd00a8a07, 0xd00a8a11, 0xd00a8a0d, 0xd00a8a0d },
695 { 0x00009940, 0x00754604, 0x00754604, 0xfff81204, 0xfff81204, 0xfff81204 },
696 { 0x00009944, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020 },
697 { 0x00009954, 0x5f3ca3de, 0x5f3ca3de, 0xe250a51e, 0xe250a51e, 0xe250a51e },
698 { 0x00009958, 0x2108ecff, 0x2108ecff, 0x3388ffff, 0x3388ffff, 0x3388ffff },
699#ifdef TB243
700 { 0x00009960, 0x00000900, 0x00000900, 0x00009b40, 0x00009b40, 0x00012d80 },
701 { 0x0000a960, 0x00000900, 0x00000900, 0x00009b40, 0x00009b40, 0x00012d80 },
702 { 0x0000b960, 0x00000900, 0x00000900, 0x00009b40, 0x00009b40, 0x00012d80 },
703 { 0x00009964, 0x00000000, 0x00000000, 0x00002210, 0x00002210, 0x00001120 },
704#else
705 { 0x00009960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0 },
706 { 0x0000a960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0 },
707 { 0x0000b960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0 },
708 { 0x00009964, 0x00001120, 0x00001120, 0x00001120, 0x00001120, 0x00001120 },
709#endif
710 { 0x0000c9bc, 0x001a0600, 0x001a0600, 0x001a1000, 0x001a0c00, 0x001a0c00 },
711 { 0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, 0x038919be },
712 { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
713 { 0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329 },
714 { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
715 { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
716 { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
717 { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
718 { 0x0000a204, 0x00000880, 0x00000880, 0x00000880, 0x00000880, 0x00000880 },
719 { 0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788, 0xd03e4788 },
720 { 0x0000a20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
721 { 0x0000b20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
722 { 0x0000c20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
723 { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
724 { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
725 { 0x0000a274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa, 0x0a1a7caa },
726 { 0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 },
727 { 0x0000a304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402, 0x2e032402 },
728 { 0x0000a308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06, 0x4a0a3c06 },
729 { 0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b, 0x621a540b },
730 { 0x0000a310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b, 0x764f6c1b },
731 { 0x0000a314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a, 0x845b7a5a },
732 { 0x0000a318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf, 0x950f8ccf },
733 { 0x0000a31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f, 0xa5cf9b4f },
734 { 0x0000a320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f, 0xbddfaf1f },
735 { 0x0000a324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f, 0xd1ffc93f },
736 { 0x0000a328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000, 0x00000000 },
737 { 0x0000a32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
738 { 0x0000a330, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
739 { 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
740};
741
742#endif /* INITVALS_AR5008_H */
diff --git a/drivers/net/wireless/ath/ath9k/ar5008_phy.c b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
new file mode 100644
index 000000000000..b2c17c98bb38
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
@@ -0,0 +1,1374 @@
1/*
2 * Copyright (c) 2008-2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "hw.h"
18#include "hw-ops.h"
19#include "../regd.h"
20#include "ar9002_phy.h"
21
22/* All code below is for non single-chip solutions */
23
24/**
25 * ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters
26 * @rfbuf:
27 * @reg32:
28 * @numBits:
29 * @firstBit:
30 * @column:
31 *
32 * Performs analog "swizzling" of parameters into their location.
33 * Used on external AR2133/AR5133 radios.
34 */
35static void ar5008_hw_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
36 u32 numBits, u32 firstBit,
37 u32 column)
38{
39 u32 tmp32, mask, arrayEntry, lastBit;
40 int32_t bitPosition, bitsLeft;
41
42 tmp32 = ath9k_hw_reverse_bits(reg32, numBits);
43 arrayEntry = (firstBit - 1) / 8;
44 bitPosition = (firstBit - 1) % 8;
45 bitsLeft = numBits;
46 while (bitsLeft > 0) {
47 lastBit = (bitPosition + bitsLeft > 8) ?
48 8 : bitPosition + bitsLeft;
49 mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) <<
50 (column * 8);
51 rfBuf[arrayEntry] &= ~mask;
52 rfBuf[arrayEntry] |= ((tmp32 << bitPosition) <<
53 (column * 8)) & mask;
54 bitsLeft -= 8 - bitPosition;
55 tmp32 = tmp32 >> (8 - bitPosition);
56 bitPosition = 0;
57 arrayEntry++;
58 }
59}
60
61/*
62 * Fix on 2.4 GHz band for orientation sensitivity issue by increasing
63 * rf_pwd_icsyndiv.
64 *
65 * Theoretical Rules:
66 * if 2 GHz band
67 * if forceBiasAuto
68 * if synth_freq < 2412
69 * bias = 0
70 * else if 2412 <= synth_freq <= 2422
71 * bias = 1
72 * else // synth_freq > 2422
73 * bias = 2
74 * else if forceBias > 0
75 * bias = forceBias & 7
76 * else
77 * no change, use value from ini file
78 * else
79 * no change, invalid band
80 *
81 * 1st Mod:
82 * 2422 also uses value of 2
83 * <approved>
84 *
85 * 2nd Mod:
86 * Less than 2412 uses value of 0, 2412 and above uses value of 2
87 */
88static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
89{
90 struct ath_common *common = ath9k_hw_common(ah);
91 u32 tmp_reg;
92 int reg_writes = 0;
93 u32 new_bias = 0;
94
95 if (!AR_SREV_5416(ah) || synth_freq >= 3000)
96 return;
97
98 BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
99
100 if (synth_freq < 2412)
101 new_bias = 0;
102 else if (synth_freq < 2422)
103 new_bias = 1;
104 else
105 new_bias = 2;
106
107 /* pre-reverse this field */
108 tmp_reg = ath9k_hw_reverse_bits(new_bias, 3);
109
110 ath_print(common, ATH_DBG_CONFIG,
111 "Force rf_pwd_icsyndiv to %1d on %4d\n",
112 new_bias, synth_freq);
113
114 /* swizzle rf_pwd_icsyndiv */
115 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3);
116
117 /* write Bank 6 with new params */
118 REG_WRITE_RF_ARRAY(&ah->iniBank6, ah->analogBank6Data, reg_writes);
119}
120
121/**
122 * ar5008_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios
123 * @ah: atheros hardware stucture
124 * @chan:
125 *
126 * For the external AR2133/AR5133 radios, takes the MHz channel value and set
127 * the channel value. Assumes writes enabled to analog bus and bank6 register
128 * cache in ah->analogBank6Data.
129 */
130static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
131{
132 struct ath_common *common = ath9k_hw_common(ah);
133 u32 channelSel = 0;
134 u32 bModeSynth = 0;
135 u32 aModeRefSel = 0;
136 u32 reg32 = 0;
137 u16 freq;
138 struct chan_centers centers;
139
140 ath9k_hw_get_channel_centers(ah, chan, &centers);
141 freq = centers.synth_center;
142
143 if (freq < 4800) {
144 u32 txctl;
145
146 if (((freq - 2192) % 5) == 0) {
147 channelSel = ((freq - 672) * 2 - 3040) / 10;
148 bModeSynth = 0;
149 } else if (((freq - 2224) % 5) == 0) {
150 channelSel = ((freq - 704) * 2 - 3040) / 10;
151 bModeSynth = 1;
152 } else {
153 ath_print(common, ATH_DBG_FATAL,
154 "Invalid channel %u MHz\n", freq);
155 return -EINVAL;
156 }
157
158 channelSel = (channelSel << 2) & 0xff;
159 channelSel = ath9k_hw_reverse_bits(channelSel, 8);
160
161 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
162 if (freq == 2484) {
163
164 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
165 txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
166 } else {
167 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
168 txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
169 }
170
171 } else if ((freq % 20) == 0 && freq >= 5120) {
172 channelSel =
173 ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
174 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
175 } else if ((freq % 10) == 0) {
176 channelSel =
177 ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
178 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
179 aModeRefSel = ath9k_hw_reverse_bits(2, 2);
180 else
181 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
182 } else if ((freq % 5) == 0) {
183 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
184 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
185 } else {
186 ath_print(common, ATH_DBG_FATAL,
187 "Invalid channel %u MHz\n", freq);
188 return -EINVAL;
189 }
190
191 ar5008_hw_force_bias(ah, freq);
192
193 reg32 =
194 (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
195 (1 << 5) | 0x1;
196
197 REG_WRITE(ah, AR_PHY(0x37), reg32);
198
199 ah->curchan = chan;
200 ah->curchan_rad_index = -1;
201
202 return 0;
203}
204
205/**
206 * ar5008_hw_spur_mitigate - convert baseband spur frequency for external radios
207 * @ah: atheros hardware structure
208 * @chan:
209 *
210 * For non single-chip solutions. Converts to baseband spur frequency given the
211 * input channel frequency and compute register settings below.
212 */
213static void ar5008_hw_spur_mitigate(struct ath_hw *ah,
214 struct ath9k_channel *chan)
215{
216 int bb_spur = AR_NO_SPUR;
217 int bin, cur_bin;
218 int spur_freq_sd;
219 int spur_delta_phase;
220 int denominator;
221 int upper, lower, cur_vit_mask;
222 int tmp, new;
223 int i;
224 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
225 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
226 };
227 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
228 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
229 };
230 int inc[4] = { 0, 100, 0, 0 };
231
232 int8_t mask_m[123];
233 int8_t mask_p[123];
234 int8_t mask_amt;
235 int tmp_mask;
236 int cur_bb_spur;
237 bool is2GHz = IS_CHAN_2GHZ(chan);
238
239 memset(&mask_m, 0, sizeof(int8_t) * 123);
240 memset(&mask_p, 0, sizeof(int8_t) * 123);
241
242 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
243 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
244 if (AR_NO_SPUR == cur_bb_spur)
245 break;
246 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
247 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
248 bb_spur = cur_bb_spur;
249 break;
250 }
251 }
252
253 if (AR_NO_SPUR == bb_spur)
254 return;
255
256 bin = bb_spur * 32;
257
258 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
259 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
260 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
261 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
262 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
263
264 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
265
266 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
267 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
268 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
269 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
270 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
271 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
272
273 spur_delta_phase = ((bb_spur * 524288) / 100) &
274 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
275
276 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
277 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
278
279 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
280 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
281 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
282 REG_WRITE(ah, AR_PHY_TIMING11, new);
283
284 cur_bin = -6000;
285 upper = bin + 100;
286 lower = bin - 100;
287
288 for (i = 0; i < 4; i++) {
289 int pilot_mask = 0;
290 int chan_mask = 0;
291 int bp = 0;
292 for (bp = 0; bp < 30; bp++) {
293 if ((cur_bin > lower) && (cur_bin < upper)) {
294 pilot_mask = pilot_mask | 0x1 << bp;
295 chan_mask = chan_mask | 0x1 << bp;
296 }
297 cur_bin += 100;
298 }
299 cur_bin += inc[i];
300 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
301 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
302 }
303
304 cur_vit_mask = 6100;
305 upper = bin + 120;
306 lower = bin - 120;
307
308 for (i = 0; i < 123; i++) {
309 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
310
311 /* workaround for gcc bug #37014 */
312 volatile int tmp_v = abs(cur_vit_mask - bin);
313
314 if (tmp_v < 75)
315 mask_amt = 1;
316 else
317 mask_amt = 0;
318 if (cur_vit_mask < 0)
319 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
320 else
321 mask_p[cur_vit_mask / 100] = mask_amt;
322 }
323 cur_vit_mask -= 100;
324 }
325
326 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
327 | (mask_m[48] << 26) | (mask_m[49] << 24)
328 | (mask_m[50] << 22) | (mask_m[51] << 20)
329 | (mask_m[52] << 18) | (mask_m[53] << 16)
330 | (mask_m[54] << 14) | (mask_m[55] << 12)
331 | (mask_m[56] << 10) | (mask_m[57] << 8)
332 | (mask_m[58] << 6) | (mask_m[59] << 4)
333 | (mask_m[60] << 2) | (mask_m[61] << 0);
334 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
335 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
336
337 tmp_mask = (mask_m[31] << 28)
338 | (mask_m[32] << 26) | (mask_m[33] << 24)
339 | (mask_m[34] << 22) | (mask_m[35] << 20)
340 | (mask_m[36] << 18) | (mask_m[37] << 16)
341 | (mask_m[48] << 14) | (mask_m[39] << 12)
342 | (mask_m[40] << 10) | (mask_m[41] << 8)
343 | (mask_m[42] << 6) | (mask_m[43] << 4)
344 | (mask_m[44] << 2) | (mask_m[45] << 0);
345 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
346 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
347
348 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
349 | (mask_m[18] << 26) | (mask_m[18] << 24)
350 | (mask_m[20] << 22) | (mask_m[20] << 20)
351 | (mask_m[22] << 18) | (mask_m[22] << 16)
352 | (mask_m[24] << 14) | (mask_m[24] << 12)
353 | (mask_m[25] << 10) | (mask_m[26] << 8)
354 | (mask_m[27] << 6) | (mask_m[28] << 4)
355 | (mask_m[29] << 2) | (mask_m[30] << 0);
356 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
357 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
358
359 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
360 | (mask_m[2] << 26) | (mask_m[3] << 24)
361 | (mask_m[4] << 22) | (mask_m[5] << 20)
362 | (mask_m[6] << 18) | (mask_m[7] << 16)
363 | (mask_m[8] << 14) | (mask_m[9] << 12)
364 | (mask_m[10] << 10) | (mask_m[11] << 8)
365 | (mask_m[12] << 6) | (mask_m[13] << 4)
366 | (mask_m[14] << 2) | (mask_m[15] << 0);
367 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
368 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
369
370 tmp_mask = (mask_p[15] << 28)
371 | (mask_p[14] << 26) | (mask_p[13] << 24)
372 | (mask_p[12] << 22) | (mask_p[11] << 20)
373 | (mask_p[10] << 18) | (mask_p[9] << 16)
374 | (mask_p[8] << 14) | (mask_p[7] << 12)
375 | (mask_p[6] << 10) | (mask_p[5] << 8)
376 | (mask_p[4] << 6) | (mask_p[3] << 4)
377 | (mask_p[2] << 2) | (mask_p[1] << 0);
378 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
379 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
380
381 tmp_mask = (mask_p[30] << 28)
382 | (mask_p[29] << 26) | (mask_p[28] << 24)
383 | (mask_p[27] << 22) | (mask_p[26] << 20)
384 | (mask_p[25] << 18) | (mask_p[24] << 16)
385 | (mask_p[23] << 14) | (mask_p[22] << 12)
386 | (mask_p[21] << 10) | (mask_p[20] << 8)
387 | (mask_p[19] << 6) | (mask_p[18] << 4)
388 | (mask_p[17] << 2) | (mask_p[16] << 0);
389 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
390 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
391
392 tmp_mask = (mask_p[45] << 28)
393 | (mask_p[44] << 26) | (mask_p[43] << 24)
394 | (mask_p[42] << 22) | (mask_p[41] << 20)
395 | (mask_p[40] << 18) | (mask_p[39] << 16)
396 | (mask_p[38] << 14) | (mask_p[37] << 12)
397 | (mask_p[36] << 10) | (mask_p[35] << 8)
398 | (mask_p[34] << 6) | (mask_p[33] << 4)
399 | (mask_p[32] << 2) | (mask_p[31] << 0);
400 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
401 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
402
403 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
404 | (mask_p[59] << 26) | (mask_p[58] << 24)
405 | (mask_p[57] << 22) | (mask_p[56] << 20)
406 | (mask_p[55] << 18) | (mask_p[54] << 16)
407 | (mask_p[53] << 14) | (mask_p[52] << 12)
408 | (mask_p[51] << 10) | (mask_p[50] << 8)
409 | (mask_p[49] << 6) | (mask_p[48] << 4)
410 | (mask_p[47] << 2) | (mask_p[46] << 0);
411 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
412 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
413}
414
415/**
416 * ar5008_hw_rf_alloc_ext_banks - allocates banks for external radio programming
417 * @ah: atheros hardware structure
418 *
419 * Only required for older devices with external AR2133/AR5133 radios.
420 */
421static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah)
422{
423#define ATH_ALLOC_BANK(bank, size) do { \
424 bank = kzalloc((sizeof(u32) * size), GFP_KERNEL); \
425 if (!bank) { \
426 ath_print(common, ATH_DBG_FATAL, \
427 "Cannot allocate RF banks\n"); \
428 return -ENOMEM; \
429 } \
430 } while (0);
431
432 struct ath_common *common = ath9k_hw_common(ah);
433
434 BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
435
436 ATH_ALLOC_BANK(ah->analogBank0Data, ah->iniBank0.ia_rows);
437 ATH_ALLOC_BANK(ah->analogBank1Data, ah->iniBank1.ia_rows);
438 ATH_ALLOC_BANK(ah->analogBank2Data, ah->iniBank2.ia_rows);
439 ATH_ALLOC_BANK(ah->analogBank3Data, ah->iniBank3.ia_rows);
440 ATH_ALLOC_BANK(ah->analogBank6Data, ah->iniBank6.ia_rows);
441 ATH_ALLOC_BANK(ah->analogBank6TPCData, ah->iniBank6TPC.ia_rows);
442 ATH_ALLOC_BANK(ah->analogBank7Data, ah->iniBank7.ia_rows);
443 ATH_ALLOC_BANK(ah->addac5416_21,
444 ah->iniAddac.ia_rows * ah->iniAddac.ia_columns);
445 ATH_ALLOC_BANK(ah->bank6Temp, ah->iniBank6.ia_rows);
446
447 return 0;
448#undef ATH_ALLOC_BANK
449}
450
451
452/**
453 * ar5008_hw_rf_free_ext_banks - Free memory for analog bank scratch buffers
454 * @ah: atheros hardware struture
455 * For the external AR2133/AR5133 radios banks.
456 */
457static void ar5008_hw_rf_free_ext_banks(struct ath_hw *ah)
458{
459#define ATH_FREE_BANK(bank) do { \
460 kfree(bank); \
461 bank = NULL; \
462 } while (0);
463
464 BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
465
466 ATH_FREE_BANK(ah->analogBank0Data);
467 ATH_FREE_BANK(ah->analogBank1Data);
468 ATH_FREE_BANK(ah->analogBank2Data);
469 ATH_FREE_BANK(ah->analogBank3Data);
470 ATH_FREE_BANK(ah->analogBank6Data);
471 ATH_FREE_BANK(ah->analogBank6TPCData);
472 ATH_FREE_BANK(ah->analogBank7Data);
473 ATH_FREE_BANK(ah->addac5416_21);
474 ATH_FREE_BANK(ah->bank6Temp);
475
476#undef ATH_FREE_BANK
477}
478
479/* *
480 * ar5008_hw_set_rf_regs - programs rf registers based on EEPROM
481 * @ah: atheros hardware structure
482 * @chan:
483 * @modesIndex:
484 *
485 * Used for the external AR2133/AR5133 radios.
486 *
487 * Reads the EEPROM header info from the device structure and programs
488 * all rf registers. This routine requires access to the analog
489 * rf device. This is not required for single-chip devices.
490 */
491static bool ar5008_hw_set_rf_regs(struct ath_hw *ah,
492 struct ath9k_channel *chan,
493 u16 modesIndex)
494{
495 u32 eepMinorRev;
496 u32 ob5GHz = 0, db5GHz = 0;
497 u32 ob2GHz = 0, db2GHz = 0;
498 int regWrites = 0;
499
500 /*
501 * Software does not need to program bank data
502 * for single chip devices, that is AR9280 or anything
503 * after that.
504 */
505 if (AR_SREV_9280_10_OR_LATER(ah))
506 return true;
507
508 /* Setup rf parameters */
509 eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
510
511 /* Setup Bank 0 Write */
512 RF_BANK_SETUP(ah->analogBank0Data, &ah->iniBank0, 1);
513
514 /* Setup Bank 1 Write */
515 RF_BANK_SETUP(ah->analogBank1Data, &ah->iniBank1, 1);
516
517 /* Setup Bank 2 Write */
518 RF_BANK_SETUP(ah->analogBank2Data, &ah->iniBank2, 1);
519
520 /* Setup Bank 6 Write */
521 RF_BANK_SETUP(ah->analogBank3Data, &ah->iniBank3,
522 modesIndex);
523 {
524 int i;
525 for (i = 0; i < ah->iniBank6TPC.ia_rows; i++) {
526 ah->analogBank6Data[i] =
527 INI_RA(&ah->iniBank6TPC, i, modesIndex);
528 }
529 }
530
531 /* Only the 5 or 2 GHz OB/DB need to be set for a mode */
532 if (eepMinorRev >= 2) {
533 if (IS_CHAN_2GHZ(chan)) {
534 ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2);
535 db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2);
536 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
537 ob2GHz, 3, 197, 0);
538 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
539 db2GHz, 3, 194, 0);
540 } else {
541 ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5);
542 db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5);
543 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
544 ob5GHz, 3, 203, 0);
545 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
546 db5GHz, 3, 200, 0);
547 }
548 }
549
550 /* Setup Bank 7 Setup */
551 RF_BANK_SETUP(ah->analogBank7Data, &ah->iniBank7, 1);
552
553 /* Write Analog registers */
554 REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
555 regWrites);
556 REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data,
557 regWrites);
558 REG_WRITE_RF_ARRAY(&ah->iniBank2, ah->analogBank2Data,
559 regWrites);
560 REG_WRITE_RF_ARRAY(&ah->iniBank3, ah->analogBank3Data,
561 regWrites);
562 REG_WRITE_RF_ARRAY(&ah->iniBank6TPC, ah->analogBank6Data,
563 regWrites);
564 REG_WRITE_RF_ARRAY(&ah->iniBank7, ah->analogBank7Data,
565 regWrites);
566
567 return true;
568}
569
570static void ar5008_hw_init_bb(struct ath_hw *ah,
571 struct ath9k_channel *chan)
572{
573 u32 synthDelay;
574
575 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
576 if (IS_CHAN_B(chan))
577 synthDelay = (4 * synthDelay) / 22;
578 else
579 synthDelay /= 10;
580
581 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
582
583 udelay(synthDelay + BASE_ACTIVATE_DELAY);
584}
585
586static void ar5008_hw_init_chain_masks(struct ath_hw *ah)
587{
588 int rx_chainmask, tx_chainmask;
589
590 rx_chainmask = ah->rxchainmask;
591 tx_chainmask = ah->txchainmask;
592
593 ENABLE_REGWRITE_BUFFER(ah);
594
595 switch (rx_chainmask) {
596 case 0x5:
597 DISABLE_REGWRITE_BUFFER(ah);
598 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
599 AR_PHY_SWAP_ALT_CHAIN);
600 ENABLE_REGWRITE_BUFFER(ah);
601 case 0x3:
602 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
603 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
604 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
605 break;
606 }
607 case 0x1:
608 case 0x2:
609 case 0x7:
610 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
611 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
612 break;
613 default:
614 break;
615 }
616
617 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
618
619 REGWRITE_BUFFER_FLUSH(ah);
620 DISABLE_REGWRITE_BUFFER(ah);
621
622 if (tx_chainmask == 0x5) {
623 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
624 AR_PHY_SWAP_ALT_CHAIN);
625 }
626 if (AR_SREV_9100(ah))
627 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
628 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
629}
630
631static void ar5008_hw_override_ini(struct ath_hw *ah,
632 struct ath9k_channel *chan)
633{
634 u32 val;
635
636 /*
637 * Set the RX_ABORT and RX_DIS and clear if off only after
638 * RXE is set for MAC. This prevents frames with corrupted
639 * descriptor status.
640 */
641 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
642
643 if (AR_SREV_9280_10_OR_LATER(ah)) {
644 val = REG_READ(ah, AR_PCU_MISC_MODE2);
645
646 if (!AR_SREV_9271(ah))
647 val &= ~AR_PCU_MISC_MODE2_HWWAR1;
648
649 if (AR_SREV_9287_10_OR_LATER(ah))
650 val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
651
652 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
653 }
654
655 if (!AR_SREV_5416_20_OR_LATER(ah) ||
656 AR_SREV_9280_10_OR_LATER(ah))
657 return;
658 /*
659 * Disable BB clock gating
660 * Necessary to avoid issues on AR5416 2.0
661 */
662 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
663
664 /*
665 * Disable RIFS search on some chips to avoid baseband
666 * hang issues.
667 */
668 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
669 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
670 val &= ~AR_PHY_RIFS_INIT_DELAY;
671 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
672 }
673}
674
675static void ar5008_hw_set_channel_regs(struct ath_hw *ah,
676 struct ath9k_channel *chan)
677{
678 u32 phymode;
679 u32 enableDacFifo = 0;
680
681 if (AR_SREV_9285_10_OR_LATER(ah))
682 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
683 AR_PHY_FC_ENABLE_DAC_FIFO);
684
685 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
686 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
687
688 if (IS_CHAN_HT40(chan)) {
689 phymode |= AR_PHY_FC_DYN2040_EN;
690
691 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
692 (chan->chanmode == CHANNEL_G_HT40PLUS))
693 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
694
695 }
696 REG_WRITE(ah, AR_PHY_TURBO, phymode);
697
698 ath9k_hw_set11nmac2040(ah);
699
700 ENABLE_REGWRITE_BUFFER(ah);
701
702 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
703 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
704
705 REGWRITE_BUFFER_FLUSH(ah);
706 DISABLE_REGWRITE_BUFFER(ah);
707}
708
709
710static int ar5008_hw_process_ini(struct ath_hw *ah,
711 struct ath9k_channel *chan)
712{
713 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
714 int i, regWrites = 0;
715 struct ieee80211_channel *channel = chan->chan;
716 u32 modesIndex, freqIndex;
717
718 switch (chan->chanmode) {
719 case CHANNEL_A:
720 case CHANNEL_A_HT20:
721 modesIndex = 1;
722 freqIndex = 1;
723 break;
724 case CHANNEL_A_HT40PLUS:
725 case CHANNEL_A_HT40MINUS:
726 modesIndex = 2;
727 freqIndex = 1;
728 break;
729 case CHANNEL_G:
730 case CHANNEL_G_HT20:
731 case CHANNEL_B:
732 modesIndex = 4;
733 freqIndex = 2;
734 break;
735 case CHANNEL_G_HT40PLUS:
736 case CHANNEL_G_HT40MINUS:
737 modesIndex = 3;
738 freqIndex = 2;
739 break;
740
741 default:
742 return -EINVAL;
743 }
744
745 if (AR_SREV_9287_12_OR_LATER(ah)) {
746 /* Enable ASYNC FIFO */
747 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
748 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
749 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
750 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
751 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
752 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
753 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
754 }
755
756 /*
757 * Set correct baseband to analog shift setting to
758 * access analog chips.
759 */
760 REG_WRITE(ah, AR_PHY(0), 0x00000007);
761
762 /* Write ADDAC shifts */
763 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
764 ah->eep_ops->set_addac(ah, chan);
765
766 if (AR_SREV_5416_22_OR_LATER(ah)) {
767 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
768 } else {
769 struct ar5416IniArray temp;
770 u32 addacSize =
771 sizeof(u32) * ah->iniAddac.ia_rows *
772 ah->iniAddac.ia_columns;
773
774 /* For AR5416 2.0/2.1 */
775 memcpy(ah->addac5416_21,
776 ah->iniAddac.ia_array, addacSize);
777
778 /* override CLKDRV value at [row, column] = [31, 1] */
779 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
780
781 temp.ia_array = ah->addac5416_21;
782 temp.ia_columns = ah->iniAddac.ia_columns;
783 temp.ia_rows = ah->iniAddac.ia_rows;
784 REG_WRITE_ARRAY(&temp, 1, regWrites);
785 }
786
787 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
788
789 ENABLE_REGWRITE_BUFFER(ah);
790
791 for (i = 0; i < ah->iniModes.ia_rows; i++) {
792 u32 reg = INI_RA(&ah->iniModes, i, 0);
793 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
794
795 if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup)
796 val &= ~AR_AN_TOP2_PWDCLKIND;
797
798 REG_WRITE(ah, reg, val);
799
800 if (reg >= 0x7800 && reg < 0x78a0
801 && ah->config.analog_shiftreg) {
802 udelay(100);
803 }
804
805 DO_DELAY(regWrites);
806 }
807
808 REGWRITE_BUFFER_FLUSH(ah);
809 DISABLE_REGWRITE_BUFFER(ah);
810
811 if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
812 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
813
814 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
815 AR_SREV_9287_10_OR_LATER(ah))
816 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
817
818 if (AR_SREV_9271_10(ah))
819 REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
820 modesIndex, regWrites);
821
822 ENABLE_REGWRITE_BUFFER(ah);
823
824 /* Write common array parameters */
825 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
826 u32 reg = INI_RA(&ah->iniCommon, i, 0);
827 u32 val = INI_RA(&ah->iniCommon, i, 1);
828
829 REG_WRITE(ah, reg, val);
830
831 if (reg >= 0x7800 && reg < 0x78a0
832 && ah->config.analog_shiftreg) {
833 udelay(100);
834 }
835
836 DO_DELAY(regWrites);
837 }
838
839 REGWRITE_BUFFER_FLUSH(ah);
840 DISABLE_REGWRITE_BUFFER(ah);
841
842 if (AR_SREV_9271(ah)) {
843 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1)
844 REG_WRITE_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
845 modesIndex, regWrites);
846 else
847 REG_WRITE_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
848 modesIndex, regWrites);
849 }
850
851 REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
852
853 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) {
854 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
855 regWrites);
856 }
857
858 ar5008_hw_override_ini(ah, chan);
859 ar5008_hw_set_channel_regs(ah, chan);
860 ar5008_hw_init_chain_masks(ah);
861 ath9k_olc_init(ah);
862
863 /* Set TX power */
864 ah->eep_ops->set_txpower(ah, chan,
865 ath9k_regd_get_ctl(regulatory, chan),
866 channel->max_antenna_gain * 2,
867 channel->max_power * 2,
868 min((u32) MAX_RATE_POWER,
869 (u32) regulatory->power_limit));
870
871 /* Write analog registers */
872 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
873 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
874 "ar5416SetRfRegs failed\n");
875 return -EIO;
876 }
877
878 return 0;
879}
880
881static void ar5008_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
882{
883 u32 rfMode = 0;
884
885 if (chan == NULL)
886 return;
887
888 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
889 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
890
891 if (!AR_SREV_9280_10_OR_LATER(ah))
892 rfMode |= (IS_CHAN_5GHZ(chan)) ?
893 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
894
895 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
896 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
897
898 REG_WRITE(ah, AR_PHY_MODE, rfMode);
899}
900
901static void ar5008_hw_mark_phy_inactive(struct ath_hw *ah)
902{
903 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
904}
905
906static void ar5008_hw_set_delta_slope(struct ath_hw *ah,
907 struct ath9k_channel *chan)
908{
909 u32 coef_scaled, ds_coef_exp, ds_coef_man;
910 u32 clockMhzScaled = 0x64000000;
911 struct chan_centers centers;
912
913 if (IS_CHAN_HALF_RATE(chan))
914 clockMhzScaled = clockMhzScaled >> 1;
915 else if (IS_CHAN_QUARTER_RATE(chan))
916 clockMhzScaled = clockMhzScaled >> 2;
917
918 ath9k_hw_get_channel_centers(ah, chan, &centers);
919 coef_scaled = clockMhzScaled / centers.synth_center;
920
921 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
922 &ds_coef_exp);
923
924 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
925 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
926 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
927 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
928
929 coef_scaled = (9 * coef_scaled) / 10;
930
931 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
932 &ds_coef_exp);
933
934 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
935 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
936 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
937 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
938}
939
940static bool ar5008_hw_rfbus_req(struct ath_hw *ah)
941{
942 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
943 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
944 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
945}
946
947static void ar5008_hw_rfbus_done(struct ath_hw *ah)
948{
949 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
950 if (IS_CHAN_B(ah->curchan))
951 synthDelay = (4 * synthDelay) / 22;
952 else
953 synthDelay /= 10;
954
955 udelay(synthDelay + BASE_ACTIVATE_DELAY);
956
957 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
958}
959
960static void ar5008_hw_enable_rfkill(struct ath_hw *ah)
961{
962 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
963 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
964
965 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
966 AR_GPIO_INPUT_MUX2_RFSILENT);
967
968 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
969 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
970}
971
972static void ar5008_restore_chainmask(struct ath_hw *ah)
973{
974 int rx_chainmask = ah->rxchainmask;
975
976 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
977 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
978 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
979 }
980}
981
982static void ar5008_set_diversity(struct ath_hw *ah, bool value)
983{
984 u32 v = REG_READ(ah, AR_PHY_CCK_DETECT);
985 if (value)
986 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
987 else
988 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
989 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
990}
991
992static u32 ar9100_hw_compute_pll_control(struct ath_hw *ah,
993 struct ath9k_channel *chan)
994{
995 if (chan && IS_CHAN_5GHZ(chan))
996 return 0x1450;
997 return 0x1458;
998}
999
1000static u32 ar9160_hw_compute_pll_control(struct ath_hw *ah,
1001 struct ath9k_channel *chan)
1002{
1003 u32 pll;
1004
1005 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1006
1007 if (chan && IS_CHAN_HALF_RATE(chan))
1008 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1009 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1010 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1011
1012 if (chan && IS_CHAN_5GHZ(chan))
1013 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1014 else
1015 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1016
1017 return pll;
1018}
1019
1020static u32 ar5008_hw_compute_pll_control(struct ath_hw *ah,
1021 struct ath9k_channel *chan)
1022{
1023 u32 pll;
1024
1025 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1026
1027 if (chan && IS_CHAN_HALF_RATE(chan))
1028 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1029 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1030 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1031
1032 if (chan && IS_CHAN_5GHZ(chan))
1033 pll |= SM(0xa, AR_RTC_PLL_DIV);
1034 else
1035 pll |= SM(0xb, AR_RTC_PLL_DIV);
1036
1037 return pll;
1038}
1039
1040static bool ar5008_hw_ani_control(struct ath_hw *ah,
1041 enum ath9k_ani_cmd cmd, int param)
1042{
1043 struct ar5416AniState *aniState = ah->curani;
1044 struct ath_common *common = ath9k_hw_common(ah);
1045
1046 switch (cmd & ah->ani_function) {
1047 case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
1048 u32 level = param;
1049
1050 if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
1051 ath_print(common, ATH_DBG_ANI,
1052 "level out of range (%u > %u)\n",
1053 level,
1054 (unsigned)ARRAY_SIZE(ah->totalSizeDesired));
1055 return false;
1056 }
1057
1058 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
1059 AR_PHY_DESIRED_SZ_TOT_DES,
1060 ah->totalSizeDesired[level]);
1061 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
1062 AR_PHY_AGC_CTL1_COARSE_LOW,
1063 ah->coarse_low[level]);
1064 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
1065 AR_PHY_AGC_CTL1_COARSE_HIGH,
1066 ah->coarse_high[level]);
1067 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1068 AR_PHY_FIND_SIG_FIRPWR,
1069 ah->firpwr[level]);
1070
1071 if (level > aniState->noiseImmunityLevel)
1072 ah->stats.ast_ani_niup++;
1073 else if (level < aniState->noiseImmunityLevel)
1074 ah->stats.ast_ani_nidown++;
1075 aniState->noiseImmunityLevel = level;
1076 break;
1077 }
1078 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
1079 const int m1ThreshLow[] = { 127, 50 };
1080 const int m2ThreshLow[] = { 127, 40 };
1081 const int m1Thresh[] = { 127, 0x4d };
1082 const int m2Thresh[] = { 127, 0x40 };
1083 const int m2CountThr[] = { 31, 16 };
1084 const int m2CountThrLow[] = { 63, 48 };
1085 u32 on = param ? 1 : 0;
1086
1087 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1088 AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
1089 m1ThreshLow[on]);
1090 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1091 AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
1092 m2ThreshLow[on]);
1093 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1094 AR_PHY_SFCORR_M1_THRESH,
1095 m1Thresh[on]);
1096 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1097 AR_PHY_SFCORR_M2_THRESH,
1098 m2Thresh[on]);
1099 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1100 AR_PHY_SFCORR_M2COUNT_THR,
1101 m2CountThr[on]);
1102 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1103 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
1104 m2CountThrLow[on]);
1105
1106 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1107 AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
1108 m1ThreshLow[on]);
1109 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1110 AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
1111 m2ThreshLow[on]);
1112 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1113 AR_PHY_SFCORR_EXT_M1_THRESH,
1114 m1Thresh[on]);
1115 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1116 AR_PHY_SFCORR_EXT_M2_THRESH,
1117 m2Thresh[on]);
1118
1119 if (on)
1120 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
1121 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1122 else
1123 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
1124 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1125
1126 if (!on != aniState->ofdmWeakSigDetectOff) {
1127 if (on)
1128 ah->stats.ast_ani_ofdmon++;
1129 else
1130 ah->stats.ast_ani_ofdmoff++;
1131 aniState->ofdmWeakSigDetectOff = !on;
1132 }
1133 break;
1134 }
1135 case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
1136 const int weakSigThrCck[] = { 8, 6 };
1137 u32 high = param ? 1 : 0;
1138
1139 REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
1140 AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
1141 weakSigThrCck[high]);
1142 if (high != aniState->cckWeakSigThreshold) {
1143 if (high)
1144 ah->stats.ast_ani_cckhigh++;
1145 else
1146 ah->stats.ast_ani_ccklow++;
1147 aniState->cckWeakSigThreshold = high;
1148 }
1149 break;
1150 }
1151 case ATH9K_ANI_FIRSTEP_LEVEL:{
1152 const int firstep[] = { 0, 4, 8 };
1153 u32 level = param;
1154
1155 if (level >= ARRAY_SIZE(firstep)) {
1156 ath_print(common, ATH_DBG_ANI,
1157 "level out of range (%u > %u)\n",
1158 level,
1159 (unsigned) ARRAY_SIZE(firstep));
1160 return false;
1161 }
1162 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1163 AR_PHY_FIND_SIG_FIRSTEP,
1164 firstep[level]);
1165 if (level > aniState->firstepLevel)
1166 ah->stats.ast_ani_stepup++;
1167 else if (level < aniState->firstepLevel)
1168 ah->stats.ast_ani_stepdown++;
1169 aniState->firstepLevel = level;
1170 break;
1171 }
1172 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
1173 const int cycpwrThr1[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
1174 u32 level = param;
1175
1176 if (level >= ARRAY_SIZE(cycpwrThr1)) {
1177 ath_print(common, ATH_DBG_ANI,
1178 "level out of range (%u > %u)\n",
1179 level,
1180 (unsigned) ARRAY_SIZE(cycpwrThr1));
1181 return false;
1182 }
1183 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1184 AR_PHY_TIMING5_CYCPWR_THR1,
1185 cycpwrThr1[level]);
1186 if (level > aniState->spurImmunityLevel)
1187 ah->stats.ast_ani_spurup++;
1188 else if (level < aniState->spurImmunityLevel)
1189 ah->stats.ast_ani_spurdown++;
1190 aniState->spurImmunityLevel = level;
1191 break;
1192 }
1193 case ATH9K_ANI_PRESENT:
1194 break;
1195 default:
1196 ath_print(common, ATH_DBG_ANI,
1197 "invalid cmd %u\n", cmd);
1198 return false;
1199 }
1200
1201 ath_print(common, ATH_DBG_ANI, "ANI parameters:\n");
1202 ath_print(common, ATH_DBG_ANI,
1203 "noiseImmunityLevel=%d, spurImmunityLevel=%d, "
1204 "ofdmWeakSigDetectOff=%d\n",
1205 aniState->noiseImmunityLevel,
1206 aniState->spurImmunityLevel,
1207 !aniState->ofdmWeakSigDetectOff);
1208 ath_print(common, ATH_DBG_ANI,
1209 "cckWeakSigThreshold=%d, "
1210 "firstepLevel=%d, listenTime=%d\n",
1211 aniState->cckWeakSigThreshold,
1212 aniState->firstepLevel,
1213 aniState->listenTime);
1214 ath_print(common, ATH_DBG_ANI,
1215 "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
1216 aniState->cycleCount,
1217 aniState->ofdmPhyErrCount,
1218 aniState->cckPhyErrCount);
1219
1220 return true;
1221}
1222
1223static void ar5008_hw_do_getnf(struct ath_hw *ah,
1224 int16_t nfarray[NUM_NF_READINGS])
1225{
1226 struct ath_common *common = ath9k_hw_common(ah);
1227 int16_t nf;
1228
1229 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
1230 if (nf & 0x100)
1231 nf = 0 - ((nf ^ 0x1ff) + 1);
1232 ath_print(common, ATH_DBG_CALIBRATE,
1233 "NF calibrated [ctl] [chain 0] is %d\n", nf);
1234 nfarray[0] = nf;
1235
1236 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR);
1237 if (nf & 0x100)
1238 nf = 0 - ((nf ^ 0x1ff) + 1);
1239 ath_print(common, ATH_DBG_CALIBRATE,
1240 "NF calibrated [ctl] [chain 1] is %d\n", nf);
1241 nfarray[1] = nf;
1242
1243 nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR);
1244 if (nf & 0x100)
1245 nf = 0 - ((nf ^ 0x1ff) + 1);
1246 ath_print(common, ATH_DBG_CALIBRATE,
1247 "NF calibrated [ctl] [chain 2] is %d\n", nf);
1248 nfarray[2] = nf;
1249
1250 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
1251 if (nf & 0x100)
1252 nf = 0 - ((nf ^ 0x1ff) + 1);
1253 ath_print(common, ATH_DBG_CALIBRATE,
1254 "NF calibrated [ext] [chain 0] is %d\n", nf);
1255 nfarray[3] = nf;
1256
1257 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR);
1258 if (nf & 0x100)
1259 nf = 0 - ((nf ^ 0x1ff) + 1);
1260 ath_print(common, ATH_DBG_CALIBRATE,
1261 "NF calibrated [ext] [chain 1] is %d\n", nf);
1262 nfarray[4] = nf;
1263
1264 nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR);
1265 if (nf & 0x100)
1266 nf = 0 - ((nf ^ 0x1ff) + 1);
1267 ath_print(common, ATH_DBG_CALIBRATE,
1268 "NF calibrated [ext] [chain 2] is %d\n", nf);
1269 nfarray[5] = nf;
1270}
1271
1272static void ar5008_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
1273{
1274 struct ath9k_nfcal_hist *h;
1275 int i, j;
1276 int32_t val;
1277 const u32 ar5416_cca_regs[6] = {
1278 AR_PHY_CCA,
1279 AR_PHY_CH1_CCA,
1280 AR_PHY_CH2_CCA,
1281 AR_PHY_EXT_CCA,
1282 AR_PHY_CH1_EXT_CCA,
1283 AR_PHY_CH2_EXT_CCA
1284 };
1285 u8 chainmask, rx_chain_status;
1286
1287 rx_chain_status = REG_READ(ah, AR_PHY_RX_CHAINMASK);
1288 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
1289 chainmask = 0x9;
1290 else if (AR_SREV_9280(ah) || AR_SREV_9287(ah)) {
1291 if ((rx_chain_status & 0x2) || (rx_chain_status & 0x4))
1292 chainmask = 0x1B;
1293 else
1294 chainmask = 0x09;
1295 } else {
1296 if (rx_chain_status & 0x4)
1297 chainmask = 0x3F;
1298 else if (rx_chain_status & 0x2)
1299 chainmask = 0x1B;
1300 else
1301 chainmask = 0x09;
1302 }
1303
1304 h = ah->nfCalHist;
1305
1306 for (i = 0; i < NUM_NF_READINGS; i++) {
1307 if (chainmask & (1 << i)) {
1308 val = REG_READ(ah, ar5416_cca_regs[i]);
1309 val &= 0xFFFFFE00;
1310 val |= (((u32) (h[i].privNF) << 1) & 0x1ff);
1311 REG_WRITE(ah, ar5416_cca_regs[i], val);
1312 }
1313 }
1314
1315 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
1316 AR_PHY_AGC_CONTROL_ENABLE_NF);
1317 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
1318 AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
1319 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
1320
1321 for (j = 0; j < 5; j++) {
1322 if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
1323 AR_PHY_AGC_CONTROL_NF) == 0)
1324 break;
1325 udelay(50);
1326 }
1327
1328 ENABLE_REGWRITE_BUFFER(ah);
1329
1330 for (i = 0; i < NUM_NF_READINGS; i++) {
1331 if (chainmask & (1 << i)) {
1332 val = REG_READ(ah, ar5416_cca_regs[i]);
1333 val &= 0xFFFFFE00;
1334 val |= (((u32) (-50) << 1) & 0x1ff);
1335 REG_WRITE(ah, ar5416_cca_regs[i], val);
1336 }
1337 }
1338
1339 REGWRITE_BUFFER_FLUSH(ah);
1340 DISABLE_REGWRITE_BUFFER(ah);
1341}
1342
1343void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
1344{
1345 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1346
1347 priv_ops->rf_set_freq = ar5008_hw_set_channel;
1348 priv_ops->spur_mitigate_freq = ar5008_hw_spur_mitigate;
1349
1350 priv_ops->rf_alloc_ext_banks = ar5008_hw_rf_alloc_ext_banks;
1351 priv_ops->rf_free_ext_banks = ar5008_hw_rf_free_ext_banks;
1352 priv_ops->set_rf_regs = ar5008_hw_set_rf_regs;
1353 priv_ops->set_channel_regs = ar5008_hw_set_channel_regs;
1354 priv_ops->init_bb = ar5008_hw_init_bb;
1355 priv_ops->process_ini = ar5008_hw_process_ini;
1356 priv_ops->set_rfmode = ar5008_hw_set_rfmode;
1357 priv_ops->mark_phy_inactive = ar5008_hw_mark_phy_inactive;
1358 priv_ops->set_delta_slope = ar5008_hw_set_delta_slope;
1359 priv_ops->rfbus_req = ar5008_hw_rfbus_req;
1360 priv_ops->rfbus_done = ar5008_hw_rfbus_done;
1361 priv_ops->enable_rfkill = ar5008_hw_enable_rfkill;
1362 priv_ops->restore_chainmask = ar5008_restore_chainmask;
1363 priv_ops->set_diversity = ar5008_set_diversity;
1364 priv_ops->ani_control = ar5008_hw_ani_control;
1365 priv_ops->do_getnf = ar5008_hw_do_getnf;
1366 priv_ops->loadnf = ar5008_hw_loadnf;
1367
1368 if (AR_SREV_9100(ah))
1369 priv_ops->compute_pll_control = ar9100_hw_compute_pll_control;
1370 else if (AR_SREV_9160_10_OR_LATER(ah))
1371 priv_ops->compute_pll_control = ar9160_hw_compute_pll_control;
1372 else
1373 priv_ops->compute_pll_control = ar5008_hw_compute_pll_control;
1374}
diff --git a/drivers/net/wireless/ath/ath9k/ar9001_initvals.h b/drivers/net/wireless/ath/ath9k/ar9001_initvals.h
new file mode 100644
index 000000000000..0b94bd385b0a
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/ar9001_initvals.h
@@ -0,0 +1,1254 @@
1
2static const u32 ar5416Common_9100[][2] = {
3 { 0x0000000c, 0x00000000 },
4 { 0x00000030, 0x00020015 },
5 { 0x00000034, 0x00000005 },
6 { 0x00000040, 0x00000000 },
7 { 0x00000044, 0x00000008 },
8 { 0x00000048, 0x00000008 },
9 { 0x0000004c, 0x00000010 },
10 { 0x00000050, 0x00000000 },
11 { 0x00000054, 0x0000001f },
12 { 0x00000800, 0x00000000 },
13 { 0x00000804, 0x00000000 },
14 { 0x00000808, 0x00000000 },
15 { 0x0000080c, 0x00000000 },
16 { 0x00000810, 0x00000000 },
17 { 0x00000814, 0x00000000 },
18 { 0x00000818, 0x00000000 },
19 { 0x0000081c, 0x00000000 },
20 { 0x00000820, 0x00000000 },
21 { 0x00000824, 0x00000000 },
22 { 0x00001040, 0x002ffc0f },
23 { 0x00001044, 0x002ffc0f },
24 { 0x00001048, 0x002ffc0f },
25 { 0x0000104c, 0x002ffc0f },
26 { 0x00001050, 0x002ffc0f },
27 { 0x00001054, 0x002ffc0f },
28 { 0x00001058, 0x002ffc0f },
29 { 0x0000105c, 0x002ffc0f },
30 { 0x00001060, 0x002ffc0f },
31 { 0x00001064, 0x002ffc0f },
32 { 0x00001230, 0x00000000 },
33 { 0x00001270, 0x00000000 },
34 { 0x00001038, 0x00000000 },
35 { 0x00001078, 0x00000000 },
36 { 0x000010b8, 0x00000000 },
37 { 0x000010f8, 0x00000000 },
38 { 0x00001138, 0x00000000 },
39 { 0x00001178, 0x00000000 },
40 { 0x000011b8, 0x00000000 },
41 { 0x000011f8, 0x00000000 },
42 { 0x00001238, 0x00000000 },
43 { 0x00001278, 0x00000000 },
44 { 0x000012b8, 0x00000000 },
45 { 0x000012f8, 0x00000000 },
46 { 0x00001338, 0x00000000 },
47 { 0x00001378, 0x00000000 },
48 { 0x000013b8, 0x00000000 },
49 { 0x000013f8, 0x00000000 },
50 { 0x00001438, 0x00000000 },
51 { 0x00001478, 0x00000000 },
52 { 0x000014b8, 0x00000000 },
53 { 0x000014f8, 0x00000000 },
54 { 0x00001538, 0x00000000 },
55 { 0x00001578, 0x00000000 },
56 { 0x000015b8, 0x00000000 },
57 { 0x000015f8, 0x00000000 },
58 { 0x00001638, 0x00000000 },
59 { 0x00001678, 0x00000000 },
60 { 0x000016b8, 0x00000000 },
61 { 0x000016f8, 0x00000000 },
62 { 0x00001738, 0x00000000 },
63 { 0x00001778, 0x00000000 },
64 { 0x000017b8, 0x00000000 },
65 { 0x000017f8, 0x00000000 },
66 { 0x0000103c, 0x00000000 },
67 { 0x0000107c, 0x00000000 },
68 { 0x000010bc, 0x00000000 },
69 { 0x000010fc, 0x00000000 },
70 { 0x0000113c, 0x00000000 },
71 { 0x0000117c, 0x00000000 },
72 { 0x000011bc, 0x00000000 },
73 { 0x000011fc, 0x00000000 },
74 { 0x0000123c, 0x00000000 },
75 { 0x0000127c, 0x00000000 },
76 { 0x000012bc, 0x00000000 },
77 { 0x000012fc, 0x00000000 },
78 { 0x0000133c, 0x00000000 },
79 { 0x0000137c, 0x00000000 },
80 { 0x000013bc, 0x00000000 },
81 { 0x000013fc, 0x00000000 },
82 { 0x0000143c, 0x00000000 },
83 { 0x0000147c, 0x00000000 },
84 { 0x00020010, 0x00000003 },
85 { 0x00020038, 0x000004c2 },
86 { 0x00008004, 0x00000000 },
87 { 0x00008008, 0x00000000 },
88 { 0x0000800c, 0x00000000 },
89 { 0x00008018, 0x00000700 },
90 { 0x00008020, 0x00000000 },
91 { 0x00008038, 0x00000000 },
92 { 0x0000803c, 0x00000000 },
93 { 0x00008048, 0x40000000 },
94 { 0x00008054, 0x00004000 },
95 { 0x00008058, 0x00000000 },
96 { 0x0000805c, 0x000fc78f },
97 { 0x00008060, 0x0000000f },
98 { 0x00008064, 0x00000000 },
99 { 0x000080c0, 0x2a82301a },
100 { 0x000080c4, 0x05dc01e0 },
101 { 0x000080c8, 0x1f402710 },
102 { 0x000080cc, 0x01f40000 },
103 { 0x000080d0, 0x00001e00 },
104 { 0x000080d4, 0x00000000 },
105 { 0x000080d8, 0x00400000 },
106 { 0x000080e0, 0xffffffff },
107 { 0x000080e4, 0x0000ffff },
108 { 0x000080e8, 0x003f3f3f },
109 { 0x000080ec, 0x00000000 },
110 { 0x000080f0, 0x00000000 },
111 { 0x000080f4, 0x00000000 },
112 { 0x000080f8, 0x00000000 },
113 { 0x000080fc, 0x00020000 },
114 { 0x00008100, 0x00020000 },
115 { 0x00008104, 0x00000001 },
116 { 0x00008108, 0x00000052 },
117 { 0x0000810c, 0x00000000 },
118 { 0x00008110, 0x00000168 },
119 { 0x00008118, 0x000100aa },
120 { 0x0000811c, 0x00003210 },
121 { 0x00008120, 0x08f04800 },
122 { 0x00008124, 0x00000000 },
123 { 0x00008128, 0x00000000 },
124 { 0x0000812c, 0x00000000 },
125 { 0x00008130, 0x00000000 },
126 { 0x00008134, 0x00000000 },
127 { 0x00008138, 0x00000000 },
128 { 0x0000813c, 0x00000000 },
129 { 0x00008144, 0x00000000 },
130 { 0x00008168, 0x00000000 },
131 { 0x0000816c, 0x00000000 },
132 { 0x00008170, 0x32143320 },
133 { 0x00008174, 0xfaa4fa50 },
134 { 0x00008178, 0x00000100 },
135 { 0x0000817c, 0x00000000 },
136 { 0x000081c4, 0x00000000 },
137 { 0x000081d0, 0x00003210 },
138 { 0x000081ec, 0x00000000 },
139 { 0x000081f0, 0x00000000 },
140 { 0x000081f4, 0x00000000 },
141 { 0x000081f8, 0x00000000 },
142 { 0x000081fc, 0x00000000 },
143 { 0x00008200, 0x00000000 },
144 { 0x00008204, 0x00000000 },
145 { 0x00008208, 0x00000000 },
146 { 0x0000820c, 0x00000000 },
147 { 0x00008210, 0x00000000 },
148 { 0x00008214, 0x00000000 },
149 { 0x00008218, 0x00000000 },
150 { 0x0000821c, 0x00000000 },
151 { 0x00008220, 0x00000000 },
152 { 0x00008224, 0x00000000 },
153 { 0x00008228, 0x00000000 },
154 { 0x0000822c, 0x00000000 },
155 { 0x00008230, 0x00000000 },
156 { 0x00008234, 0x00000000 },
157 { 0x00008238, 0x00000000 },
158 { 0x0000823c, 0x00000000 },
159 { 0x00008240, 0x00100000 },
160 { 0x00008244, 0x0010f400 },
161 { 0x00008248, 0x00000100 },
162 { 0x0000824c, 0x0001e800 },
163 { 0x00008250, 0x00000000 },
164 { 0x00008254, 0x00000000 },
165 { 0x00008258, 0x00000000 },
166 { 0x0000825c, 0x400000ff },
167 { 0x00008260, 0x00080922 },
168 { 0x00008270, 0x00000000 },
169 { 0x00008274, 0x40000000 },
170 { 0x00008278, 0x003e4180 },
171 { 0x0000827c, 0x00000000 },
172 { 0x00008284, 0x0000002c },
173 { 0x00008288, 0x0000002c },
174 { 0x0000828c, 0x00000000 },
175 { 0x00008294, 0x00000000 },
176 { 0x00008298, 0x00000000 },
177 { 0x00008300, 0x00000000 },
178 { 0x00008304, 0x00000000 },
179 { 0x00008308, 0x00000000 },
180 { 0x0000830c, 0x00000000 },
181 { 0x00008310, 0x00000000 },
182 { 0x00008314, 0x00000000 },
183 { 0x00008318, 0x00000000 },
184 { 0x00008328, 0x00000000 },
185 { 0x0000832c, 0x00000007 },
186 { 0x00008330, 0x00000302 },
187 { 0x00008334, 0x00000e00 },
188 { 0x00008338, 0x00000000 },
189 { 0x0000833c, 0x00000000 },
190 { 0x00008340, 0x000107ff },
191 { 0x00009808, 0x00000000 },
192 { 0x0000980c, 0xad848e19 },
193 { 0x00009810, 0x7d14e000 },
194 { 0x00009814, 0x9c0a9f6b },
195 { 0x0000981c, 0x00000000 },
196 { 0x0000982c, 0x0000a000 },
197 { 0x00009830, 0x00000000 },
198 { 0x0000983c, 0x00200400 },
199 { 0x00009840, 0x206a01ae },
200 { 0x0000984c, 0x1284233c },
201 { 0x00009854, 0x00000859 },
202 { 0x00009900, 0x00000000 },
203 { 0x00009904, 0x00000000 },
204 { 0x00009908, 0x00000000 },
205 { 0x0000990c, 0x00000000 },
206 { 0x0000991c, 0x10000fff },
207 { 0x00009920, 0x05100000 },
208 { 0x0000a920, 0x05100000 },
209 { 0x0000b920, 0x05100000 },
210 { 0x00009928, 0x00000001 },
211 { 0x0000992c, 0x00000004 },
212 { 0x00009934, 0x1e1f2022 },
213 { 0x00009938, 0x0a0b0c0d },
214 { 0x0000993c, 0x00000000 },
215 { 0x00009948, 0x9280b212 },
216 { 0x0000994c, 0x00020028 },
217 { 0x0000c95c, 0x004b6a8e },
218 { 0x0000c968, 0x000003ce },
219 { 0x00009970, 0x190fb515 },
220 { 0x00009974, 0x00000000 },
221 { 0x00009978, 0x00000001 },
222 { 0x0000997c, 0x00000000 },
223 { 0x00009980, 0x00000000 },
224 { 0x00009984, 0x00000000 },
225 { 0x00009988, 0x00000000 },
226 { 0x0000998c, 0x00000000 },
227 { 0x00009990, 0x00000000 },
228 { 0x00009994, 0x00000000 },
229 { 0x00009998, 0x00000000 },
230 { 0x0000999c, 0x00000000 },
231 { 0x000099a0, 0x00000000 },
232 { 0x000099a4, 0x00000001 },
233 { 0x000099a8, 0x201fff00 },
234 { 0x000099ac, 0x006f0000 },
235 { 0x000099b0, 0x03051000 },
236 { 0x000099dc, 0x00000000 },
237 { 0x000099e0, 0x00000200 },
238 { 0x000099e4, 0xaaaaaaaa },
239 { 0x000099e8, 0x3c466478 },
240 { 0x000099ec, 0x0cc80caa },
241 { 0x000099fc, 0x00001042 },
242 { 0x00009b00, 0x00000000 },
243 { 0x00009b04, 0x00000001 },
244 { 0x00009b08, 0x00000002 },
245 { 0x00009b0c, 0x00000003 },
246 { 0x00009b10, 0x00000004 },
247 { 0x00009b14, 0x00000005 },
248 { 0x00009b18, 0x00000008 },
249 { 0x00009b1c, 0x00000009 },
250 { 0x00009b20, 0x0000000a },
251 { 0x00009b24, 0x0000000b },
252 { 0x00009b28, 0x0000000c },
253 { 0x00009b2c, 0x0000000d },
254 { 0x00009b30, 0x00000010 },
255 { 0x00009b34, 0x00000011 },
256 { 0x00009b38, 0x00000012 },
257 { 0x00009b3c, 0x00000013 },
258 { 0x00009b40, 0x00000014 },
259 { 0x00009b44, 0x00000015 },
260 { 0x00009b48, 0x00000018 },
261 { 0x00009b4c, 0x00000019 },
262 { 0x00009b50, 0x0000001a },
263 { 0x00009b54, 0x0000001b },
264 { 0x00009b58, 0x0000001c },
265 { 0x00009b5c, 0x0000001d },
266 { 0x00009b60, 0x00000020 },
267 { 0x00009b64, 0x00000021 },
268 { 0x00009b68, 0x00000022 },
269 { 0x00009b6c, 0x00000023 },
270 { 0x00009b70, 0x00000024 },
271 { 0x00009b74, 0x00000025 },
272 { 0x00009b78, 0x00000028 },
273 { 0x00009b7c, 0x00000029 },
274 { 0x00009b80, 0x0000002a },
275 { 0x00009b84, 0x0000002b },
276 { 0x00009b88, 0x0000002c },
277 { 0x00009b8c, 0x0000002d },
278 { 0x00009b90, 0x00000030 },
279 { 0x00009b94, 0x00000031 },
280 { 0x00009b98, 0x00000032 },
281 { 0x00009b9c, 0x00000033 },
282 { 0x00009ba0, 0x00000034 },
283 { 0x00009ba4, 0x00000035 },
284 { 0x00009ba8, 0x00000035 },
285 { 0x00009bac, 0x00000035 },
286 { 0x00009bb0, 0x00000035 },
287 { 0x00009bb4, 0x00000035 },
288 { 0x00009bb8, 0x00000035 },
289 { 0x00009bbc, 0x00000035 },
290 { 0x00009bc0, 0x00000035 },
291 { 0x00009bc4, 0x00000035 },
292 { 0x00009bc8, 0x00000035 },
293 { 0x00009bcc, 0x00000035 },
294 { 0x00009bd0, 0x00000035 },
295 { 0x00009bd4, 0x00000035 },
296 { 0x00009bd8, 0x00000035 },
297 { 0x00009bdc, 0x00000035 },
298 { 0x00009be0, 0x00000035 },
299 { 0x00009be4, 0x00000035 },
300 { 0x00009be8, 0x00000035 },
301 { 0x00009bec, 0x00000035 },
302 { 0x00009bf0, 0x00000035 },
303 { 0x00009bf4, 0x00000035 },
304 { 0x00009bf8, 0x00000010 },
305 { 0x00009bfc, 0x0000001a },
306 { 0x0000a210, 0x40806333 },
307 { 0x0000a214, 0x00106c10 },
308 { 0x0000a218, 0x009c4060 },
309 { 0x0000a220, 0x018830c6 },
310 { 0x0000a224, 0x00000400 },
311 { 0x0000a228, 0x001a0bb5 },
312 { 0x0000a22c, 0x00000000 },
313 { 0x0000a234, 0x20202020 },
314 { 0x0000a238, 0x20202020 },
315 { 0x0000a23c, 0x13c889ae },
316 { 0x0000a240, 0x38490a20 },
317 { 0x0000a244, 0x00007bb6 },
318 { 0x0000a248, 0x0fff3ffc },
319 { 0x0000a24c, 0x00000001 },
320 { 0x0000a250, 0x0000a000 },
321 { 0x0000a254, 0x00000000 },
322 { 0x0000a258, 0x0cc75380 },
323 { 0x0000a25c, 0x0f0f0f01 },
324 { 0x0000a260, 0xdfa91f01 },
325 { 0x0000a268, 0x00000001 },
326 { 0x0000a26c, 0x0ebae9c6 },
327 { 0x0000b26c, 0x0ebae9c6 },
328 { 0x0000c26c, 0x0ebae9c6 },
329 { 0x0000d270, 0x00820820 },
330 { 0x0000a278, 0x1ce739ce },
331 { 0x0000a27c, 0x050701ce },
332 { 0x0000a338, 0x00000000 },
333 { 0x0000a33c, 0x00000000 },
334 { 0x0000a340, 0x00000000 },
335 { 0x0000a344, 0x00000000 },
336 { 0x0000a348, 0x3fffffff },
337 { 0x0000a34c, 0x3fffffff },
338 { 0x0000a350, 0x3fffffff },
339 { 0x0000a354, 0x0003ffff },
340 { 0x0000a358, 0x79a8aa33 },
341 { 0x0000d35c, 0x07ffffef },
342 { 0x0000d360, 0x0fffffe7 },
343 { 0x0000d364, 0x17ffffe5 },
344 { 0x0000d368, 0x1fffffe4 },
345 { 0x0000d36c, 0x37ffffe3 },
346 { 0x0000d370, 0x3fffffe3 },
347 { 0x0000d374, 0x57ffffe3 },
348 { 0x0000d378, 0x5fffffe2 },
349 { 0x0000d37c, 0x7fffffe2 },
350 { 0x0000d380, 0x7f3c7bba },
351 { 0x0000d384, 0xf3307ff0 },
352 { 0x0000a388, 0x0c000000 },
353 { 0x0000a38c, 0x20202020 },
354 { 0x0000a390, 0x20202020 },
355 { 0x0000a394, 0x1ce739ce },
356 { 0x0000a398, 0x000001ce },
357 { 0x0000a39c, 0x00000001 },
358 { 0x0000a3a0, 0x00000000 },
359 { 0x0000a3a4, 0x00000000 },
360 { 0x0000a3a8, 0x00000000 },
361 { 0x0000a3ac, 0x00000000 },
362 { 0x0000a3b0, 0x00000000 },
363 { 0x0000a3b4, 0x00000000 },
364 { 0x0000a3b8, 0x00000000 },
365 { 0x0000a3bc, 0x00000000 },
366 { 0x0000a3c0, 0x00000000 },
367 { 0x0000a3c4, 0x00000000 },
368 { 0x0000a3c8, 0x00000246 },
369 { 0x0000a3cc, 0x20202020 },
370 { 0x0000a3d0, 0x20202020 },
371 { 0x0000a3d4, 0x20202020 },
372 { 0x0000a3dc, 0x1ce739ce },
373 { 0x0000a3e0, 0x000001ce },
374};
375
376static const u32 ar5416Bank0_9100[][2] = {
377 { 0x000098b0, 0x1e5795e5 },
378 { 0x000098e0, 0x02008020 },
379};
380
381static const u32 ar5416BB_RfGain_9100[][3] = {
382 { 0x00009a00, 0x00000000, 0x00000000 },
383 { 0x00009a04, 0x00000040, 0x00000040 },
384 { 0x00009a08, 0x00000080, 0x00000080 },
385 { 0x00009a0c, 0x000001a1, 0x00000141 },
386 { 0x00009a10, 0x000001e1, 0x00000181 },
387 { 0x00009a14, 0x00000021, 0x000001c1 },
388 { 0x00009a18, 0x00000061, 0x00000001 },
389 { 0x00009a1c, 0x00000168, 0x00000041 },
390 { 0x00009a20, 0x000001a8, 0x000001a8 },
391 { 0x00009a24, 0x000001e8, 0x000001e8 },
392 { 0x00009a28, 0x00000028, 0x00000028 },
393 { 0x00009a2c, 0x00000068, 0x00000068 },
394 { 0x00009a30, 0x00000189, 0x000000a8 },
395 { 0x00009a34, 0x000001c9, 0x00000169 },
396 { 0x00009a38, 0x00000009, 0x000001a9 },
397 { 0x00009a3c, 0x00000049, 0x000001e9 },
398 { 0x00009a40, 0x00000089, 0x00000029 },
399 { 0x00009a44, 0x00000170, 0x00000069 },
400 { 0x00009a48, 0x000001b0, 0x00000190 },
401 { 0x00009a4c, 0x000001f0, 0x000001d0 },
402 { 0x00009a50, 0x00000030, 0x00000010 },
403 { 0x00009a54, 0x00000070, 0x00000050 },
404 { 0x00009a58, 0x00000191, 0x00000090 },
405 { 0x00009a5c, 0x000001d1, 0x00000151 },
406 { 0x00009a60, 0x00000011, 0x00000191 },
407 { 0x00009a64, 0x00000051, 0x000001d1 },
408 { 0x00009a68, 0x00000091, 0x00000011 },
409 { 0x00009a6c, 0x000001b8, 0x00000051 },
410 { 0x00009a70, 0x000001f8, 0x00000198 },
411 { 0x00009a74, 0x00000038, 0x000001d8 },
412 { 0x00009a78, 0x00000078, 0x00000018 },
413 { 0x00009a7c, 0x00000199, 0x00000058 },
414 { 0x00009a80, 0x000001d9, 0x00000098 },
415 { 0x00009a84, 0x00000019, 0x00000159 },
416 { 0x00009a88, 0x00000059, 0x00000199 },
417 { 0x00009a8c, 0x00000099, 0x000001d9 },
418 { 0x00009a90, 0x000000d9, 0x00000019 },
419 { 0x00009a94, 0x000000f9, 0x00000059 },
420 { 0x00009a98, 0x000000f9, 0x00000099 },
421 { 0x00009a9c, 0x000000f9, 0x000000d9 },
422 { 0x00009aa0, 0x000000f9, 0x000000f9 },
423 { 0x00009aa4, 0x000000f9, 0x000000f9 },
424 { 0x00009aa8, 0x000000f9, 0x000000f9 },
425 { 0x00009aac, 0x000000f9, 0x000000f9 },
426 { 0x00009ab0, 0x000000f9, 0x000000f9 },
427 { 0x00009ab4, 0x000000f9, 0x000000f9 },
428 { 0x00009ab8, 0x000000f9, 0x000000f9 },
429 { 0x00009abc, 0x000000f9, 0x000000f9 },
430 { 0x00009ac0, 0x000000f9, 0x000000f9 },
431 { 0x00009ac4, 0x000000f9, 0x000000f9 },
432 { 0x00009ac8, 0x000000f9, 0x000000f9 },
433 { 0x00009acc, 0x000000f9, 0x000000f9 },
434 { 0x00009ad0, 0x000000f9, 0x000000f9 },
435 { 0x00009ad4, 0x000000f9, 0x000000f9 },
436 { 0x00009ad8, 0x000000f9, 0x000000f9 },
437 { 0x00009adc, 0x000000f9, 0x000000f9 },
438 { 0x00009ae0, 0x000000f9, 0x000000f9 },
439 { 0x00009ae4, 0x000000f9, 0x000000f9 },
440 { 0x00009ae8, 0x000000f9, 0x000000f9 },
441 { 0x00009aec, 0x000000f9, 0x000000f9 },
442 { 0x00009af0, 0x000000f9, 0x000000f9 },
443 { 0x00009af4, 0x000000f9, 0x000000f9 },
444 { 0x00009af8, 0x000000f9, 0x000000f9 },
445 { 0x00009afc, 0x000000f9, 0x000000f9 },
446};
447
448static const u32 ar5416Bank1_9100[][2] = {
449 { 0x000098b0, 0x02108421},
450 { 0x000098ec, 0x00000008},
451};
452
453static const u32 ar5416Bank2_9100[][2] = {
454 { 0x000098b0, 0x0e73ff17},
455 { 0x000098e0, 0x00000420},
456};
457
458static const u32 ar5416Bank3_9100[][3] = {
459 { 0x000098f0, 0x01400018, 0x01c00018 },
460};
461
462static const u32 ar5416Bank6_9100[][3] = {
463
464 { 0x0000989c, 0x00000000, 0x00000000 },
465 { 0x0000989c, 0x00000000, 0x00000000 },
466 { 0x0000989c, 0x00000000, 0x00000000 },
467 { 0x0000989c, 0x00e00000, 0x00e00000 },
468 { 0x0000989c, 0x005e0000, 0x005e0000 },
469 { 0x0000989c, 0x00120000, 0x00120000 },
470 { 0x0000989c, 0x00620000, 0x00620000 },
471 { 0x0000989c, 0x00020000, 0x00020000 },
472 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
473 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
474 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
475 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
476 { 0x0000989c, 0x005f0000, 0x005f0000 },
477 { 0x0000989c, 0x00870000, 0x00870000 },
478 { 0x0000989c, 0x00f90000, 0x00f90000 },
479 { 0x0000989c, 0x007b0000, 0x007b0000 },
480 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
481 { 0x0000989c, 0x00f50000, 0x00f50000 },
482 { 0x0000989c, 0x00dc0000, 0x00dc0000 },
483 { 0x0000989c, 0x00110000, 0x00110000 },
484 { 0x0000989c, 0x006100a8, 0x006100a8 },
485 { 0x0000989c, 0x004210a2, 0x004210a2 },
486 { 0x0000989c, 0x0014000f, 0x0014000f },
487 { 0x0000989c, 0x00c40002, 0x00c40002 },
488 { 0x0000989c, 0x003000f2, 0x003000f2 },
489 { 0x0000989c, 0x00440016, 0x00440016 },
490 { 0x0000989c, 0x00410040, 0x00410040 },
491 { 0x0000989c, 0x000180d6, 0x000180d6 },
492 { 0x0000989c, 0x0000c0aa, 0x0000c0aa },
493 { 0x0000989c, 0x000000b1, 0x000000b1 },
494 { 0x0000989c, 0x00002000, 0x00002000 },
495 { 0x0000989c, 0x000000d4, 0x000000d4 },
496 { 0x000098d0, 0x0000000f, 0x0010000f },
497};
498
499
500static const u32 ar5416Bank6TPC_9100[][3] = {
501
502 { 0x0000989c, 0x00000000, 0x00000000 },
503 { 0x0000989c, 0x00000000, 0x00000000 },
504 { 0x0000989c, 0x00000000, 0x00000000 },
505 { 0x0000989c, 0x00e00000, 0x00e00000 },
506 { 0x0000989c, 0x005e0000, 0x005e0000 },
507 { 0x0000989c, 0x00120000, 0x00120000 },
508 { 0x0000989c, 0x00620000, 0x00620000 },
509 { 0x0000989c, 0x00020000, 0x00020000 },
510 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
511 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
512 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
513 { 0x0000989c, 0x40ff0000, 0x40ff0000 },
514 { 0x0000989c, 0x005f0000, 0x005f0000 },
515 { 0x0000989c, 0x00870000, 0x00870000 },
516 { 0x0000989c, 0x00f90000, 0x00f90000 },
517 { 0x0000989c, 0x007b0000, 0x007b0000 },
518 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
519 { 0x0000989c, 0x00f50000, 0x00f50000 },
520 { 0x0000989c, 0x00dc0000, 0x00dc0000 },
521 { 0x0000989c, 0x00110000, 0x00110000 },
522 { 0x0000989c, 0x006100a8, 0x006100a8 },
523 { 0x0000989c, 0x00423022, 0x00423022 },
524 { 0x0000989c, 0x2014008f, 0x2014008f },
525 { 0x0000989c, 0x00c40002, 0x00c40002 },
526 { 0x0000989c, 0x003000f2, 0x003000f2 },
527 { 0x0000989c, 0x00440016, 0x00440016 },
528 { 0x0000989c, 0x00410040, 0x00410040 },
529 { 0x0000989c, 0x0001805e, 0x0001805e },
530 { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
531 { 0x0000989c, 0x000000e1, 0x000000e1 },
532 { 0x0000989c, 0x00007080, 0x00007080 },
533 { 0x0000989c, 0x000000d4, 0x000000d4 },
534 { 0x000098d0, 0x0000000f, 0x0010000f },
535};
536
537static const u32 ar5416Bank7_9100[][2] = {
538 { 0x0000989c, 0x00000500 },
539 { 0x0000989c, 0x00000800 },
540 { 0x000098cc, 0x0000000e },
541};
542
543static const u32 ar5416Addac_9100[][2] = {
544 {0x0000989c, 0x00000000 },
545 {0x0000989c, 0x00000000 },
546 {0x0000989c, 0x00000000 },
547 {0x0000989c, 0x00000000 },
548 {0x0000989c, 0x00000000 },
549 {0x0000989c, 0x00000000 },
550 {0x0000989c, 0x00000000 },
551 {0x0000989c, 0x00000010 },
552 {0x0000989c, 0x00000000 },
553 {0x0000989c, 0x00000000 },
554 {0x0000989c, 0x00000000 },
555 {0x0000989c, 0x00000000 },
556 {0x0000989c, 0x00000000 },
557 {0x0000989c, 0x00000000 },
558 {0x0000989c, 0x00000000 },
559 {0x0000989c, 0x00000000 },
560 {0x0000989c, 0x00000000 },
561 {0x0000989c, 0x00000000 },
562 {0x0000989c, 0x00000000 },
563 {0x0000989c, 0x00000000 },
564 {0x0000989c, 0x00000000 },
565 {0x0000989c, 0x000000c0 },
566 {0x0000989c, 0x00000015 },
567 {0x0000989c, 0x00000000 },
568 {0x0000989c, 0x00000000 },
569 {0x0000989c, 0x00000000 },
570 {0x0000989c, 0x00000000 },
571 {0x0000989c, 0x00000000 },
572 {0x0000989c, 0x00000000 },
573 {0x0000989c, 0x00000000 },
574 {0x0000989c, 0x00000000 },
575 {0x000098cc, 0x00000000 },
576};
577
578static const u32 ar5416Modes_9160[][6] = {
579 { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
580 { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
581 { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
582 { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },
583 { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
584 { 0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf },
585 { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
586 { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
587 { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
588 { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
589 { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
590 { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
591 { 0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0, 0x037216a0 },
592 { 0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
593 { 0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
594 { 0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
595 { 0x00009850, 0x6c48b4e2, 0x6c48b4e2, 0x6c48b0e2, 0x6c48b0e2, 0x6c48b0e2 },
596 { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e },
597 { 0x0000985c, 0x31395d5e, 0x31395d5e, 0x31395d5e, 0x31395d5e, 0x31395d5e },
598 { 0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20, 0x00048d18 },
599 { 0x0000c864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
600 { 0x00009868, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0 },
601 { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 },
602 { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
603 { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
604 { 0x00009924, 0xd00a8a07, 0xd00a8a07, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d },
605 { 0x00009944, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020 },
606 { 0x00009960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40 },
607 { 0x0000a960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40 },
608 { 0x0000b960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40 },
609 { 0x00009964, 0x00001120, 0x00001120, 0x00001120, 0x00001120, 0x00001120 },
610 { 0x0000c968, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce, 0x000003ce },
611 { 0x0000c9bc, 0x001a0600, 0x001a0600, 0x001a0c00, 0x001a0c00, 0x001a0c00 },
612 { 0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, 0x038919be },
613 { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
614 { 0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329 },
615 { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
616 { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
617 { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
618 { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
619 { 0x0000a204, 0x00000880, 0x00000880, 0x00000880, 0x00000880, 0x00000880 },
620 { 0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788, 0xd03e4788 },
621 { 0x0000a20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
622 { 0x0000b20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
623 { 0x0000c20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
624 { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
625 { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
626 { 0x0000a274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa, 0x0a1a7caa },
627 { 0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 },
628 { 0x0000a304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402, 0x2e032402 },
629 { 0x0000a308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06, 0x4a0a3c06 },
630 { 0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b, 0x621a540b },
631 { 0x0000a310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b, 0x764f6c1b },
632 { 0x0000a314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a, 0x845b7a5a },
633 { 0x0000a318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf, 0x950f8ccf },
634 { 0x0000a31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f, 0xa5cf9b4f },
635 { 0x0000a320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f, 0xbddfaf1f },
636 { 0x0000a324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f, 0xd1ffc93f },
637 { 0x0000a328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000, 0x00000000 },
638 { 0x0000a32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
639 { 0x0000a330, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
640 { 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
641};
642
643static const u32 ar5416Common_9160[][2] = {
644 { 0x0000000c, 0x00000000 },
645 { 0x00000030, 0x00020015 },
646 { 0x00000034, 0x00000005 },
647 { 0x00000040, 0x00000000 },
648 { 0x00000044, 0x00000008 },
649 { 0x00000048, 0x00000008 },
650 { 0x0000004c, 0x00000010 },
651 { 0x00000050, 0x00000000 },
652 { 0x00000054, 0x0000001f },
653 { 0x00000800, 0x00000000 },
654 { 0x00000804, 0x00000000 },
655 { 0x00000808, 0x00000000 },
656 { 0x0000080c, 0x00000000 },
657 { 0x00000810, 0x00000000 },
658 { 0x00000814, 0x00000000 },
659 { 0x00000818, 0x00000000 },
660 { 0x0000081c, 0x00000000 },
661 { 0x00000820, 0x00000000 },
662 { 0x00000824, 0x00000000 },
663 { 0x00001040, 0x002ffc0f },
664 { 0x00001044, 0x002ffc0f },
665 { 0x00001048, 0x002ffc0f },
666 { 0x0000104c, 0x002ffc0f },
667 { 0x00001050, 0x002ffc0f },
668 { 0x00001054, 0x002ffc0f },
669 { 0x00001058, 0x002ffc0f },
670 { 0x0000105c, 0x002ffc0f },
671 { 0x00001060, 0x002ffc0f },
672 { 0x00001064, 0x002ffc0f },
673 { 0x00001230, 0x00000000 },
674 { 0x00001270, 0x00000000 },
675 { 0x00001038, 0x00000000 },
676 { 0x00001078, 0x00000000 },
677 { 0x000010b8, 0x00000000 },
678 { 0x000010f8, 0x00000000 },
679 { 0x00001138, 0x00000000 },
680 { 0x00001178, 0x00000000 },
681 { 0x000011b8, 0x00000000 },
682 { 0x000011f8, 0x00000000 },
683 { 0x00001238, 0x00000000 },
684 { 0x00001278, 0x00000000 },
685 { 0x000012b8, 0x00000000 },
686 { 0x000012f8, 0x00000000 },
687 { 0x00001338, 0x00000000 },
688 { 0x00001378, 0x00000000 },
689 { 0x000013b8, 0x00000000 },
690 { 0x000013f8, 0x00000000 },
691 { 0x00001438, 0x00000000 },
692 { 0x00001478, 0x00000000 },
693 { 0x000014b8, 0x00000000 },
694 { 0x000014f8, 0x00000000 },
695 { 0x00001538, 0x00000000 },
696 { 0x00001578, 0x00000000 },
697 { 0x000015b8, 0x00000000 },
698 { 0x000015f8, 0x00000000 },
699 { 0x00001638, 0x00000000 },
700 { 0x00001678, 0x00000000 },
701 { 0x000016b8, 0x00000000 },
702 { 0x000016f8, 0x00000000 },
703 { 0x00001738, 0x00000000 },
704 { 0x00001778, 0x00000000 },
705 { 0x000017b8, 0x00000000 },
706 { 0x000017f8, 0x00000000 },
707 { 0x0000103c, 0x00000000 },
708 { 0x0000107c, 0x00000000 },
709 { 0x000010bc, 0x00000000 },
710 { 0x000010fc, 0x00000000 },
711 { 0x0000113c, 0x00000000 },
712 { 0x0000117c, 0x00000000 },
713 { 0x000011bc, 0x00000000 },
714 { 0x000011fc, 0x00000000 },
715 { 0x0000123c, 0x00000000 },
716 { 0x0000127c, 0x00000000 },
717 { 0x000012bc, 0x00000000 },
718 { 0x000012fc, 0x00000000 },
719 { 0x0000133c, 0x00000000 },
720 { 0x0000137c, 0x00000000 },
721 { 0x000013bc, 0x00000000 },
722 { 0x000013fc, 0x00000000 },
723 { 0x0000143c, 0x00000000 },
724 { 0x0000147c, 0x00000000 },
725 { 0x00004030, 0x00000002 },
726 { 0x0000403c, 0x00000002 },
727 { 0x00007010, 0x00000020 },
728 { 0x00007038, 0x000004c2 },
729 { 0x00008004, 0x00000000 },
730 { 0x00008008, 0x00000000 },
731 { 0x0000800c, 0x00000000 },
732 { 0x00008018, 0x00000700 },
733 { 0x00008020, 0x00000000 },
734 { 0x00008038, 0x00000000 },
735 { 0x0000803c, 0x00000000 },
736 { 0x00008048, 0x40000000 },
737 { 0x00008054, 0x00000000 },
738 { 0x00008058, 0x00000000 },
739 { 0x0000805c, 0x000fc78f },
740 { 0x00008060, 0x0000000f },
741 { 0x00008064, 0x00000000 },
742 { 0x000080c0, 0x2a82301a },
743 { 0x000080c4, 0x05dc01e0 },
744 { 0x000080c8, 0x1f402710 },
745 { 0x000080cc, 0x01f40000 },
746 { 0x000080d0, 0x00001e00 },
747 { 0x000080d4, 0x00000000 },
748 { 0x000080d8, 0x00400000 },
749 { 0x000080e0, 0xffffffff },
750 { 0x000080e4, 0x0000ffff },
751 { 0x000080e8, 0x003f3f3f },
752 { 0x000080ec, 0x00000000 },
753 { 0x000080f0, 0x00000000 },
754 { 0x000080f4, 0x00000000 },
755 { 0x000080f8, 0x00000000 },
756 { 0x000080fc, 0x00020000 },
757 { 0x00008100, 0x00020000 },
758 { 0x00008104, 0x00000001 },
759 { 0x00008108, 0x00000052 },
760 { 0x0000810c, 0x00000000 },
761 { 0x00008110, 0x00000168 },
762 { 0x00008118, 0x000100aa },
763 { 0x0000811c, 0x00003210 },
764 { 0x00008120, 0x08f04800 },
765 { 0x00008124, 0x00000000 },
766 { 0x00008128, 0x00000000 },
767 { 0x0000812c, 0x00000000 },
768 { 0x00008130, 0x00000000 },
769 { 0x00008134, 0x00000000 },
770 { 0x00008138, 0x00000000 },
771 { 0x0000813c, 0x00000000 },
772 { 0x00008144, 0xffffffff },
773 { 0x00008168, 0x00000000 },
774 { 0x0000816c, 0x00000000 },
775 { 0x00008170, 0x32143320 },
776 { 0x00008174, 0xfaa4fa50 },
777 { 0x00008178, 0x00000100 },
778 { 0x0000817c, 0x00000000 },
779 { 0x000081c4, 0x00000000 },
780 { 0x000081d0, 0x00003210 },
781 { 0x000081ec, 0x00000000 },
782 { 0x000081f0, 0x00000000 },
783 { 0x000081f4, 0x00000000 },
784 { 0x000081f8, 0x00000000 },
785 { 0x000081fc, 0x00000000 },
786 { 0x00008200, 0x00000000 },
787 { 0x00008204, 0x00000000 },
788 { 0x00008208, 0x00000000 },
789 { 0x0000820c, 0x00000000 },
790 { 0x00008210, 0x00000000 },
791 { 0x00008214, 0x00000000 },
792 { 0x00008218, 0x00000000 },
793 { 0x0000821c, 0x00000000 },
794 { 0x00008220, 0x00000000 },
795 { 0x00008224, 0x00000000 },
796 { 0x00008228, 0x00000000 },
797 { 0x0000822c, 0x00000000 },
798 { 0x00008230, 0x00000000 },
799 { 0x00008234, 0x00000000 },
800 { 0x00008238, 0x00000000 },
801 { 0x0000823c, 0x00000000 },
802 { 0x00008240, 0x00100000 },
803 { 0x00008244, 0x0010f400 },
804 { 0x00008248, 0x00000100 },
805 { 0x0000824c, 0x0001e800 },
806 { 0x00008250, 0x00000000 },
807 { 0x00008254, 0x00000000 },
808 { 0x00008258, 0x00000000 },
809 { 0x0000825c, 0x400000ff },
810 { 0x00008260, 0x00080922 },
811 { 0x00008270, 0x00000000 },
812 { 0x00008274, 0x40000000 },
813 { 0x00008278, 0x003e4180 },
814 { 0x0000827c, 0x00000000 },
815 { 0x00008284, 0x0000002c },
816 { 0x00008288, 0x0000002c },
817 { 0x0000828c, 0x00000000 },
818 { 0x00008294, 0x00000000 },
819 { 0x00008298, 0x00000000 },
820 { 0x00008300, 0x00000000 },
821 { 0x00008304, 0x00000000 },
822 { 0x00008308, 0x00000000 },
823 { 0x0000830c, 0x00000000 },
824 { 0x00008310, 0x00000000 },
825 { 0x00008314, 0x00000000 },
826 { 0x00008318, 0x00000000 },
827 { 0x00008328, 0x00000000 },
828 { 0x0000832c, 0x00000007 },
829 { 0x00008330, 0x00000302 },
830 { 0x00008334, 0x00000e00 },
831 { 0x00008338, 0x00ff0000 },
832 { 0x0000833c, 0x00000000 },
833 { 0x00008340, 0x000107ff },
834 { 0x00009808, 0x00000000 },
835 { 0x0000980c, 0xad848e19 },
836 { 0x00009810, 0x7d14e000 },
837 { 0x00009814, 0x9c0a9f6b },
838 { 0x0000981c, 0x00000000 },
839 { 0x0000982c, 0x0000a000 },
840 { 0x00009830, 0x00000000 },
841 { 0x0000983c, 0x00200400 },
842 { 0x00009840, 0x206a01ae },
843 { 0x0000984c, 0x1284233c },
844 { 0x00009854, 0x00000859 },
845 { 0x00009900, 0x00000000 },
846 { 0x00009904, 0x00000000 },
847 { 0x00009908, 0x00000000 },
848 { 0x0000990c, 0x00000000 },
849 { 0x0000991c, 0x10000fff },
850 { 0x00009920, 0x05100000 },
851 { 0x0000a920, 0x05100000 },
852 { 0x0000b920, 0x05100000 },
853 { 0x00009928, 0x00000001 },
854 { 0x0000992c, 0x00000004 },
855 { 0x00009934, 0x1e1f2022 },
856 { 0x00009938, 0x0a0b0c0d },
857 { 0x0000993c, 0x00000000 },
858 { 0x00009948, 0x9280b212 },
859 { 0x0000994c, 0x00020028 },
860 { 0x00009954, 0x5f3ca3de },
861 { 0x00009958, 0x2108ecff },
862 { 0x00009940, 0x00750604 },
863 { 0x0000c95c, 0x004b6a8e },
864 { 0x00009970, 0x190fb515 },
865 { 0x00009974, 0x00000000 },
866 { 0x00009978, 0x00000001 },
867 { 0x0000997c, 0x00000000 },
868 { 0x00009980, 0x00000000 },
869 { 0x00009984, 0x00000000 },
870 { 0x00009988, 0x00000000 },
871 { 0x0000998c, 0x00000000 },
872 { 0x00009990, 0x00000000 },
873 { 0x00009994, 0x00000000 },
874 { 0x00009998, 0x00000000 },
875 { 0x0000999c, 0x00000000 },
876 { 0x000099a0, 0x00000000 },
877 { 0x000099a4, 0x00000001 },
878 { 0x000099a8, 0x201fff00 },
879 { 0x000099ac, 0x006f0000 },
880 { 0x000099b0, 0x03051000 },
881 { 0x000099dc, 0x00000000 },
882 { 0x000099e0, 0x00000200 },
883 { 0x000099e4, 0xaaaaaaaa },
884 { 0x000099e8, 0x3c466478 },
885 { 0x000099ec, 0x0cc80caa },
886 { 0x000099fc, 0x00001042 },
887 { 0x00009b00, 0x00000000 },
888 { 0x00009b04, 0x00000001 },
889 { 0x00009b08, 0x00000002 },
890 { 0x00009b0c, 0x00000003 },
891 { 0x00009b10, 0x00000004 },
892 { 0x00009b14, 0x00000005 },
893 { 0x00009b18, 0x00000008 },
894 { 0x00009b1c, 0x00000009 },
895 { 0x00009b20, 0x0000000a },
896 { 0x00009b24, 0x0000000b },
897 { 0x00009b28, 0x0000000c },
898 { 0x00009b2c, 0x0000000d },
899 { 0x00009b30, 0x00000010 },
900 { 0x00009b34, 0x00000011 },
901 { 0x00009b38, 0x00000012 },
902 { 0x00009b3c, 0x00000013 },
903 { 0x00009b40, 0x00000014 },
904 { 0x00009b44, 0x00000015 },
905 { 0x00009b48, 0x00000018 },
906 { 0x00009b4c, 0x00000019 },
907 { 0x00009b50, 0x0000001a },
908 { 0x00009b54, 0x0000001b },
909 { 0x00009b58, 0x0000001c },
910 { 0x00009b5c, 0x0000001d },
911 { 0x00009b60, 0x00000020 },
912 { 0x00009b64, 0x00000021 },
913 { 0x00009b68, 0x00000022 },
914 { 0x00009b6c, 0x00000023 },
915 { 0x00009b70, 0x00000024 },
916 { 0x00009b74, 0x00000025 },
917 { 0x00009b78, 0x00000028 },
918 { 0x00009b7c, 0x00000029 },
919 { 0x00009b80, 0x0000002a },
920 { 0x00009b84, 0x0000002b },
921 { 0x00009b88, 0x0000002c },
922 { 0x00009b8c, 0x0000002d },
923 { 0x00009b90, 0x00000030 },
924 { 0x00009b94, 0x00000031 },
925 { 0x00009b98, 0x00000032 },
926 { 0x00009b9c, 0x00000033 },
927 { 0x00009ba0, 0x00000034 },
928 { 0x00009ba4, 0x00000035 },
929 { 0x00009ba8, 0x00000035 },
930 { 0x00009bac, 0x00000035 },
931 { 0x00009bb0, 0x00000035 },
932 { 0x00009bb4, 0x00000035 },
933 { 0x00009bb8, 0x00000035 },
934 { 0x00009bbc, 0x00000035 },
935 { 0x00009bc0, 0x00000035 },
936 { 0x00009bc4, 0x00000035 },
937 { 0x00009bc8, 0x00000035 },
938 { 0x00009bcc, 0x00000035 },
939 { 0x00009bd0, 0x00000035 },
940 { 0x00009bd4, 0x00000035 },
941 { 0x00009bd8, 0x00000035 },
942 { 0x00009bdc, 0x00000035 },
943 { 0x00009be0, 0x00000035 },
944 { 0x00009be4, 0x00000035 },
945 { 0x00009be8, 0x00000035 },
946 { 0x00009bec, 0x00000035 },
947 { 0x00009bf0, 0x00000035 },
948 { 0x00009bf4, 0x00000035 },
949 { 0x00009bf8, 0x00000010 },
950 { 0x00009bfc, 0x0000001a },
951 { 0x0000a210, 0x40806333 },
952 { 0x0000a214, 0x00106c10 },
953 { 0x0000a218, 0x009c4060 },
954 { 0x0000a220, 0x018830c6 },
955 { 0x0000a224, 0x00000400 },
956 { 0x0000a228, 0x001a0bb5 },
957 { 0x0000a22c, 0x00000000 },
958 { 0x0000a234, 0x20202020 },
959 { 0x0000a238, 0x20202020 },
960 { 0x0000a23c, 0x13c889af },
961 { 0x0000a240, 0x38490a20 },
962 { 0x0000a244, 0x00007bb6 },
963 { 0x0000a248, 0x0fff3ffc },
964 { 0x0000a24c, 0x00000001 },
965 { 0x0000a250, 0x0000e000 },
966 { 0x0000a254, 0x00000000 },
967 { 0x0000a258, 0x0cc75380 },
968 { 0x0000a25c, 0x0f0f0f01 },
969 { 0x0000a260, 0xdfa91f01 },
970 { 0x0000a268, 0x00000001 },
971 { 0x0000a26c, 0x0ebae9c6 },
972 { 0x0000b26c, 0x0ebae9c6 },
973 { 0x0000c26c, 0x0ebae9c6 },
974 { 0x0000d270, 0x00820820 },
975 { 0x0000a278, 0x1ce739ce },
976 { 0x0000a27c, 0x050701ce },
977 { 0x0000a338, 0x00000000 },
978 { 0x0000a33c, 0x00000000 },
979 { 0x0000a340, 0x00000000 },
980 { 0x0000a344, 0x00000000 },
981 { 0x0000a348, 0x3fffffff },
982 { 0x0000a34c, 0x3fffffff },
983 { 0x0000a350, 0x3fffffff },
984 { 0x0000a354, 0x0003ffff },
985 { 0x0000a358, 0x79bfaa03 },
986 { 0x0000d35c, 0x07ffffef },
987 { 0x0000d360, 0x0fffffe7 },
988 { 0x0000d364, 0x17ffffe5 },
989 { 0x0000d368, 0x1fffffe4 },
990 { 0x0000d36c, 0x37ffffe3 },
991 { 0x0000d370, 0x3fffffe3 },
992 { 0x0000d374, 0x57ffffe3 },
993 { 0x0000d378, 0x5fffffe2 },
994 { 0x0000d37c, 0x7fffffe2 },
995 { 0x0000d380, 0x7f3c7bba },
996 { 0x0000d384, 0xf3307ff0 },
997 { 0x0000a388, 0x0c000000 },
998 { 0x0000a38c, 0x20202020 },
999 { 0x0000a390, 0x20202020 },
1000 { 0x0000a394, 0x1ce739ce },
1001 { 0x0000a398, 0x000001ce },
1002 { 0x0000a39c, 0x00000001 },
1003 { 0x0000a3a0, 0x00000000 },
1004 { 0x0000a3a4, 0x00000000 },
1005 { 0x0000a3a8, 0x00000000 },
1006 { 0x0000a3ac, 0x00000000 },
1007 { 0x0000a3b0, 0x00000000 },
1008 { 0x0000a3b4, 0x00000000 },
1009 { 0x0000a3b8, 0x00000000 },
1010 { 0x0000a3bc, 0x00000000 },
1011 { 0x0000a3c0, 0x00000000 },
1012 { 0x0000a3c4, 0x00000000 },
1013 { 0x0000a3c8, 0x00000246 },
1014 { 0x0000a3cc, 0x20202020 },
1015 { 0x0000a3d0, 0x20202020 },
1016 { 0x0000a3d4, 0x20202020 },
1017 { 0x0000a3dc, 0x1ce739ce },
1018 { 0x0000a3e0, 0x000001ce },
1019};
1020
1021static const u32 ar5416Bank0_9160[][2] = {
1022 { 0x000098b0, 0x1e5795e5 },
1023 { 0x000098e0, 0x02008020 },
1024};
1025
1026static const u32 ar5416BB_RfGain_9160[][3] = {
1027 { 0x00009a00, 0x00000000, 0x00000000 },
1028 { 0x00009a04, 0x00000040, 0x00000040 },
1029 { 0x00009a08, 0x00000080, 0x00000080 },
1030 { 0x00009a0c, 0x000001a1, 0x00000141 },
1031 { 0x00009a10, 0x000001e1, 0x00000181 },
1032 { 0x00009a14, 0x00000021, 0x000001c1 },
1033 { 0x00009a18, 0x00000061, 0x00000001 },
1034 { 0x00009a1c, 0x00000168, 0x00000041 },
1035 { 0x00009a20, 0x000001a8, 0x000001a8 },
1036 { 0x00009a24, 0x000001e8, 0x000001e8 },
1037 { 0x00009a28, 0x00000028, 0x00000028 },
1038 { 0x00009a2c, 0x00000068, 0x00000068 },
1039 { 0x00009a30, 0x00000189, 0x000000a8 },
1040 { 0x00009a34, 0x000001c9, 0x00000169 },
1041 { 0x00009a38, 0x00000009, 0x000001a9 },
1042 { 0x00009a3c, 0x00000049, 0x000001e9 },
1043 { 0x00009a40, 0x00000089, 0x00000029 },
1044 { 0x00009a44, 0x00000170, 0x00000069 },
1045 { 0x00009a48, 0x000001b0, 0x00000190 },
1046 { 0x00009a4c, 0x000001f0, 0x000001d0 },
1047 { 0x00009a50, 0x00000030, 0x00000010 },
1048 { 0x00009a54, 0x00000070, 0x00000050 },
1049 { 0x00009a58, 0x00000191, 0x00000090 },
1050 { 0x00009a5c, 0x000001d1, 0x00000151 },
1051 { 0x00009a60, 0x00000011, 0x00000191 },
1052 { 0x00009a64, 0x00000051, 0x000001d1 },
1053 { 0x00009a68, 0x00000091, 0x00000011 },
1054 { 0x00009a6c, 0x000001b8, 0x00000051 },
1055 { 0x00009a70, 0x000001f8, 0x00000198 },
1056 { 0x00009a74, 0x00000038, 0x000001d8 },
1057 { 0x00009a78, 0x00000078, 0x00000018 },
1058 { 0x00009a7c, 0x00000199, 0x00000058 },
1059 { 0x00009a80, 0x000001d9, 0x00000098 },
1060 { 0x00009a84, 0x00000019, 0x00000159 },
1061 { 0x00009a88, 0x00000059, 0x00000199 },
1062 { 0x00009a8c, 0x00000099, 0x000001d9 },
1063 { 0x00009a90, 0x000000d9, 0x00000019 },
1064 { 0x00009a94, 0x000000f9, 0x00000059 },
1065 { 0x00009a98, 0x000000f9, 0x00000099 },
1066 { 0x00009a9c, 0x000000f9, 0x000000d9 },
1067 { 0x00009aa0, 0x000000f9, 0x000000f9 },
1068 { 0x00009aa4, 0x000000f9, 0x000000f9 },
1069 { 0x00009aa8, 0x000000f9, 0x000000f9 },
1070 { 0x00009aac, 0x000000f9, 0x000000f9 },
1071 { 0x00009ab0, 0x000000f9, 0x000000f9 },
1072 { 0x00009ab4, 0x000000f9, 0x000000f9 },
1073 { 0x00009ab8, 0x000000f9, 0x000000f9 },
1074 { 0x00009abc, 0x000000f9, 0x000000f9 },
1075 { 0x00009ac0, 0x000000f9, 0x000000f9 },
1076 { 0x00009ac4, 0x000000f9, 0x000000f9 },
1077 { 0x00009ac8, 0x000000f9, 0x000000f9 },
1078 { 0x00009acc, 0x000000f9, 0x000000f9 },
1079 { 0x00009ad0, 0x000000f9, 0x000000f9 },
1080 { 0x00009ad4, 0x000000f9, 0x000000f9 },
1081 { 0x00009ad8, 0x000000f9, 0x000000f9 },
1082 { 0x00009adc, 0x000000f9, 0x000000f9 },
1083 { 0x00009ae0, 0x000000f9, 0x000000f9 },
1084 { 0x00009ae4, 0x000000f9, 0x000000f9 },
1085 { 0x00009ae8, 0x000000f9, 0x000000f9 },
1086 { 0x00009aec, 0x000000f9, 0x000000f9 },
1087 { 0x00009af0, 0x000000f9, 0x000000f9 },
1088 { 0x00009af4, 0x000000f9, 0x000000f9 },
1089 { 0x00009af8, 0x000000f9, 0x000000f9 },
1090 { 0x00009afc, 0x000000f9, 0x000000f9 },
1091};
1092
1093static const u32 ar5416Bank1_9160[][2] = {
1094 { 0x000098b0, 0x02108421 },
1095 { 0x000098ec, 0x00000008 },
1096};
1097
1098static const u32 ar5416Bank2_9160[][2] = {
1099 { 0x000098b0, 0x0e73ff17 },
1100 { 0x000098e0, 0x00000420 },
1101};
1102
1103static const u32 ar5416Bank3_9160[][3] = {
1104 { 0x000098f0, 0x01400018, 0x01c00018 },
1105};
1106
1107static const u32 ar5416Bank6_9160[][3] = {
1108 { 0x0000989c, 0x00000000, 0x00000000 },
1109 { 0x0000989c, 0x00000000, 0x00000000 },
1110 { 0x0000989c, 0x00000000, 0x00000000 },
1111 { 0x0000989c, 0x00e00000, 0x00e00000 },
1112 { 0x0000989c, 0x005e0000, 0x005e0000 },
1113 { 0x0000989c, 0x00120000, 0x00120000 },
1114 { 0x0000989c, 0x00620000, 0x00620000 },
1115 { 0x0000989c, 0x00020000, 0x00020000 },
1116 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
1117 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
1118 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
1119 { 0x0000989c, 0x40ff0000, 0x40ff0000 },
1120 { 0x0000989c, 0x005f0000, 0x005f0000 },
1121 { 0x0000989c, 0x00870000, 0x00870000 },
1122 { 0x0000989c, 0x00f90000, 0x00f90000 },
1123 { 0x0000989c, 0x007b0000, 0x007b0000 },
1124 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
1125 { 0x0000989c, 0x00f50000, 0x00f50000 },
1126 { 0x0000989c, 0x00dc0000, 0x00dc0000 },
1127 { 0x0000989c, 0x00110000, 0x00110000 },
1128 { 0x0000989c, 0x006100a8, 0x006100a8 },
1129 { 0x0000989c, 0x004210a2, 0x004210a2 },
1130 { 0x0000989c, 0x0014008f, 0x0014008f },
1131 { 0x0000989c, 0x00c40003, 0x00c40003 },
1132 { 0x0000989c, 0x003000f2, 0x003000f2 },
1133 { 0x0000989c, 0x00440016, 0x00440016 },
1134 { 0x0000989c, 0x00410040, 0x00410040 },
1135 { 0x0000989c, 0x0001805e, 0x0001805e },
1136 { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
1137 { 0x0000989c, 0x000000f1, 0x000000f1 },
1138 { 0x0000989c, 0x00002081, 0x00002081 },
1139 { 0x0000989c, 0x000000d4, 0x000000d4 },
1140 { 0x000098d0, 0x0000000f, 0x0010000f },
1141};
1142
1143static const u32 ar5416Bank6TPC_9160[][3] = {
1144 { 0x0000989c, 0x00000000, 0x00000000 },
1145 { 0x0000989c, 0x00000000, 0x00000000 },
1146 { 0x0000989c, 0x00000000, 0x00000000 },
1147 { 0x0000989c, 0x00e00000, 0x00e00000 },
1148 { 0x0000989c, 0x005e0000, 0x005e0000 },
1149 { 0x0000989c, 0x00120000, 0x00120000 },
1150 { 0x0000989c, 0x00620000, 0x00620000 },
1151 { 0x0000989c, 0x00020000, 0x00020000 },
1152 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
1153 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
1154 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
1155 { 0x0000989c, 0x40ff0000, 0x40ff0000 },
1156 { 0x0000989c, 0x005f0000, 0x005f0000 },
1157 { 0x0000989c, 0x00870000, 0x00870000 },
1158 { 0x0000989c, 0x00f90000, 0x00f90000 },
1159 { 0x0000989c, 0x007b0000, 0x007b0000 },
1160 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
1161 { 0x0000989c, 0x00f50000, 0x00f50000 },
1162 { 0x0000989c, 0x00dc0000, 0x00dc0000 },
1163 { 0x0000989c, 0x00110000, 0x00110000 },
1164 { 0x0000989c, 0x006100a8, 0x006100a8 },
1165 { 0x0000989c, 0x00423022, 0x00423022 },
1166 { 0x0000989c, 0x2014008f, 0x2014008f },
1167 { 0x0000989c, 0x00c40002, 0x00c40002 },
1168 { 0x0000989c, 0x003000f2, 0x003000f2 },
1169 { 0x0000989c, 0x00440016, 0x00440016 },
1170 { 0x0000989c, 0x00410040, 0x00410040 },
1171 { 0x0000989c, 0x0001805e, 0x0001805e },
1172 { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
1173 { 0x0000989c, 0x000000e1, 0x000000e1 },
1174 { 0x0000989c, 0x00007080, 0x00007080 },
1175 { 0x0000989c, 0x000000d4, 0x000000d4 },
1176 { 0x000098d0, 0x0000000f, 0x0010000f },
1177};
1178
1179static const u32 ar5416Bank7_9160[][2] = {
1180 { 0x0000989c, 0x00000500 },
1181 { 0x0000989c, 0x00000800 },
1182 { 0x000098cc, 0x0000000e },
1183};
1184
1185static const u32 ar5416Addac_9160[][2] = {
1186 {0x0000989c, 0x00000000 },
1187 {0x0000989c, 0x00000000 },
1188 {0x0000989c, 0x00000000 },
1189 {0x0000989c, 0x00000000 },
1190 {0x0000989c, 0x00000000 },
1191 {0x0000989c, 0x00000000 },
1192 {0x0000989c, 0x000000c0 },
1193 {0x0000989c, 0x00000018 },
1194 {0x0000989c, 0x00000004 },
1195 {0x0000989c, 0x00000000 },
1196 {0x0000989c, 0x00000000 },
1197 {0x0000989c, 0x00000000 },
1198 {0x0000989c, 0x00000000 },
1199 {0x0000989c, 0x00000000 },
1200 {0x0000989c, 0x00000000 },
1201 {0x0000989c, 0x00000000 },
1202 {0x0000989c, 0x00000000 },
1203 {0x0000989c, 0x00000000 },
1204 {0x0000989c, 0x00000000 },
1205 {0x0000989c, 0x00000000 },
1206 {0x0000989c, 0x00000000 },
1207 {0x0000989c, 0x000000c0 },
1208 {0x0000989c, 0x00000019 },
1209 {0x0000989c, 0x00000004 },
1210 {0x0000989c, 0x00000000 },
1211 {0x0000989c, 0x00000000 },
1212 {0x0000989c, 0x00000000 },
1213 {0x0000989c, 0x00000004 },
1214 {0x0000989c, 0x00000003 },
1215 {0x0000989c, 0x00000008 },
1216 {0x0000989c, 0x00000000 },
1217 {0x000098cc, 0x00000000 },
1218};
1219
1220static const u32 ar5416Addac_91601_1[][2] = {
1221 {0x0000989c, 0x00000000 },
1222 {0x0000989c, 0x00000000 },
1223 {0x0000989c, 0x00000000 },
1224 {0x0000989c, 0x00000000 },
1225 {0x0000989c, 0x00000000 },
1226 {0x0000989c, 0x00000000 },
1227 {0x0000989c, 0x000000c0 },
1228 {0x0000989c, 0x00000018 },
1229 {0x0000989c, 0x00000004 },
1230 {0x0000989c, 0x00000000 },
1231 {0x0000989c, 0x00000000 },
1232 {0x0000989c, 0x00000000 },
1233 {0x0000989c, 0x00000000 },
1234 {0x0000989c, 0x00000000 },
1235 {0x0000989c, 0x00000000 },
1236 {0x0000989c, 0x00000000 },
1237 {0x0000989c, 0x00000000 },
1238 {0x0000989c, 0x00000000 },
1239 {0x0000989c, 0x00000000 },
1240 {0x0000989c, 0x00000000 },
1241 {0x0000989c, 0x00000000 },
1242 {0x0000989c, 0x000000c0 },
1243 {0x0000989c, 0x00000019 },
1244 {0x0000989c, 0x00000004 },
1245 {0x0000989c, 0x00000000 },
1246 {0x0000989c, 0x00000000 },
1247 {0x0000989c, 0x00000000 },
1248 {0x0000989c, 0x00000000 },
1249 {0x0000989c, 0x00000000 },
1250 {0x0000989c, 0x00000000 },
1251 {0x0000989c, 0x00000000 },
1252 {0x000098cc, 0x00000000 },
1253};
1254
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_calib.c b/drivers/net/wireless/ath/ath9k/ar9002_calib.c
new file mode 100644
index 000000000000..5fdbb53b47e0
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/ar9002_calib.c
@@ -0,0 +1,1000 @@
1/*
2 * Copyright (c) 2008-2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "hw.h"
18#include "hw-ops.h"
19#include "ar9002_phy.h"
20
21#define AR9285_CLCAL_REDO_THRESH 1
22
23static void ar9002_hw_setup_calibration(struct ath_hw *ah,
24 struct ath9k_cal_list *currCal)
25{
26 struct ath_common *common = ath9k_hw_common(ah);
27
28 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
29 AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
30 currCal->calData->calCountMax);
31
32 switch (currCal->calData->calType) {
33 case IQ_MISMATCH_CAL:
34 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
35 ath_print(common, ATH_DBG_CALIBRATE,
36 "starting IQ Mismatch Calibration\n");
37 break;
38 case ADC_GAIN_CAL:
39 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
40 ath_print(common, ATH_DBG_CALIBRATE,
41 "starting ADC Gain Calibration\n");
42 break;
43 case ADC_DC_CAL:
44 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
45 ath_print(common, ATH_DBG_CALIBRATE,
46 "starting ADC DC Calibration\n");
47 break;
48 case ADC_DC_INIT_CAL:
49 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
50 ath_print(common, ATH_DBG_CALIBRATE,
51 "starting Init ADC DC Calibration\n");
52 break;
53 case TEMP_COMP_CAL:
54 break; /* Not supported */
55 }
56
57 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
58 AR_PHY_TIMING_CTRL4_DO_CAL);
59}
60
61static bool ar9002_hw_per_calibration(struct ath_hw *ah,
62 struct ath9k_channel *ichan,
63 u8 rxchainmask,
64 struct ath9k_cal_list *currCal)
65{
66 bool iscaldone = false;
67
68 if (currCal->calState == CAL_RUNNING) {
69 if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &
70 AR_PHY_TIMING_CTRL4_DO_CAL)) {
71
72 currCal->calData->calCollect(ah);
73 ah->cal_samples++;
74
75 if (ah->cal_samples >=
76 currCal->calData->calNumSamples) {
77 int i, numChains = 0;
78 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
79 if (rxchainmask & (1 << i))
80 numChains++;
81 }
82
83 currCal->calData->calPostProc(ah, numChains);
84 ichan->CalValid |= currCal->calData->calType;
85 currCal->calState = CAL_DONE;
86 iscaldone = true;
87 } else {
88 ar9002_hw_setup_calibration(ah, currCal);
89 }
90 }
91 } else if (!(ichan->CalValid & currCal->calData->calType)) {
92 ath9k_hw_reset_calibration(ah, currCal);
93 }
94
95 return iscaldone;
96}
97
98/* Assumes you are talking about the currently configured channel */
99static bool ar9002_hw_iscal_supported(struct ath_hw *ah,
100 enum ath9k_cal_types calType)
101{
102 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
103
104 switch (calType & ah->supp_cals) {
105 case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */
106 return true;
107 case ADC_GAIN_CAL:
108 case ADC_DC_CAL:
109 if (!(conf->channel->band == IEEE80211_BAND_2GHZ &&
110 conf_is_ht20(conf)))
111 return true;
112 break;
113 }
114 return false;
115}
116
117static void ar9002_hw_iqcal_collect(struct ath_hw *ah)
118{
119 int i;
120
121 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
122 ah->totalPowerMeasI[i] +=
123 REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
124 ah->totalPowerMeasQ[i] +=
125 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
126 ah->totalIqCorrMeas[i] +=
127 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
128 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
129 "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
130 ah->cal_samples, i, ah->totalPowerMeasI[i],
131 ah->totalPowerMeasQ[i],
132 ah->totalIqCorrMeas[i]);
133 }
134}
135
136static void ar9002_hw_adc_gaincal_collect(struct ath_hw *ah)
137{
138 int i;
139
140 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
141 ah->totalAdcIOddPhase[i] +=
142 REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
143 ah->totalAdcIEvenPhase[i] +=
144 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
145 ah->totalAdcQOddPhase[i] +=
146 REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
147 ah->totalAdcQEvenPhase[i] +=
148 REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
149
150 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
151 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
152 "oddq=0x%08x; evenq=0x%08x;\n",
153 ah->cal_samples, i,
154 ah->totalAdcIOddPhase[i],
155 ah->totalAdcIEvenPhase[i],
156 ah->totalAdcQOddPhase[i],
157 ah->totalAdcQEvenPhase[i]);
158 }
159}
160
161static void ar9002_hw_adc_dccal_collect(struct ath_hw *ah)
162{
163 int i;
164
165 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
166 ah->totalAdcDcOffsetIOddPhase[i] +=
167 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
168 ah->totalAdcDcOffsetIEvenPhase[i] +=
169 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
170 ah->totalAdcDcOffsetQOddPhase[i] +=
171 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
172 ah->totalAdcDcOffsetQEvenPhase[i] +=
173 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
174
175 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
176 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
177 "oddq=0x%08x; evenq=0x%08x;\n",
178 ah->cal_samples, i,
179 ah->totalAdcDcOffsetIOddPhase[i],
180 ah->totalAdcDcOffsetIEvenPhase[i],
181 ah->totalAdcDcOffsetQOddPhase[i],
182 ah->totalAdcDcOffsetQEvenPhase[i]);
183 }
184}
185
186static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
187{
188 struct ath_common *common = ath9k_hw_common(ah);
189 u32 powerMeasQ, powerMeasI, iqCorrMeas;
190 u32 qCoffDenom, iCoffDenom;
191 int32_t qCoff, iCoff;
192 int iqCorrNeg, i;
193
194 for (i = 0; i < numChains; i++) {
195 powerMeasI = ah->totalPowerMeasI[i];
196 powerMeasQ = ah->totalPowerMeasQ[i];
197 iqCorrMeas = ah->totalIqCorrMeas[i];
198
199 ath_print(common, ATH_DBG_CALIBRATE,
200 "Starting IQ Cal and Correction for Chain %d\n",
201 i);
202
203 ath_print(common, ATH_DBG_CALIBRATE,
204 "Orignal: Chn %diq_corr_meas = 0x%08x\n",
205 i, ah->totalIqCorrMeas[i]);
206
207 iqCorrNeg = 0;
208
209 if (iqCorrMeas > 0x80000000) {
210 iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
211 iqCorrNeg = 1;
212 }
213
214 ath_print(common, ATH_DBG_CALIBRATE,
215 "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
216 ath_print(common, ATH_DBG_CALIBRATE,
217 "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
218 ath_print(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
219 iqCorrNeg);
220
221 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
222 qCoffDenom = powerMeasQ / 64;
223
224 if ((powerMeasQ != 0) && (iCoffDenom != 0) &&
225 (qCoffDenom != 0)) {
226 iCoff = iqCorrMeas / iCoffDenom;
227 qCoff = powerMeasI / qCoffDenom - 64;
228 ath_print(common, ATH_DBG_CALIBRATE,
229 "Chn %d iCoff = 0x%08x\n", i, iCoff);
230 ath_print(common, ATH_DBG_CALIBRATE,
231 "Chn %d qCoff = 0x%08x\n", i, qCoff);
232
233 iCoff = iCoff & 0x3f;
234 ath_print(common, ATH_DBG_CALIBRATE,
235 "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
236 if (iqCorrNeg == 0x0)
237 iCoff = 0x40 - iCoff;
238
239 if (qCoff > 15)
240 qCoff = 15;
241 else if (qCoff <= -16)
242 qCoff = 16;
243
244 ath_print(common, ATH_DBG_CALIBRATE,
245 "Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
246 i, iCoff, qCoff);
247
248 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
249 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
250 iCoff);
251 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
252 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
253 qCoff);
254 ath_print(common, ATH_DBG_CALIBRATE,
255 "IQ Cal and Correction done for Chain %d\n",
256 i);
257 }
258 }
259
260 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
261 AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);
262}
263
264static void ar9002_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
265{
266 struct ath_common *common = ath9k_hw_common(ah);
267 u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset, qEvenMeasOffset;
268 u32 qGainMismatch, iGainMismatch, val, i;
269
270 for (i = 0; i < numChains; i++) {
271 iOddMeasOffset = ah->totalAdcIOddPhase[i];
272 iEvenMeasOffset = ah->totalAdcIEvenPhase[i];
273 qOddMeasOffset = ah->totalAdcQOddPhase[i];
274 qEvenMeasOffset = ah->totalAdcQEvenPhase[i];
275
276 ath_print(common, ATH_DBG_CALIBRATE,
277 "Starting ADC Gain Cal for Chain %d\n", i);
278
279 ath_print(common, ATH_DBG_CALIBRATE,
280 "Chn %d pwr_meas_odd_i = 0x%08x\n", i,
281 iOddMeasOffset);
282 ath_print(common, ATH_DBG_CALIBRATE,
283 "Chn %d pwr_meas_even_i = 0x%08x\n", i,
284 iEvenMeasOffset);
285 ath_print(common, ATH_DBG_CALIBRATE,
286 "Chn %d pwr_meas_odd_q = 0x%08x\n", i,
287 qOddMeasOffset);
288 ath_print(common, ATH_DBG_CALIBRATE,
289 "Chn %d pwr_meas_even_q = 0x%08x\n", i,
290 qEvenMeasOffset);
291
292 if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) {
293 iGainMismatch =
294 ((iEvenMeasOffset * 32) /
295 iOddMeasOffset) & 0x3f;
296 qGainMismatch =
297 ((qOddMeasOffset * 32) /
298 qEvenMeasOffset) & 0x3f;
299
300 ath_print(common, ATH_DBG_CALIBRATE,
301 "Chn %d gain_mismatch_i = 0x%08x\n", i,
302 iGainMismatch);
303 ath_print(common, ATH_DBG_CALIBRATE,
304 "Chn %d gain_mismatch_q = 0x%08x\n", i,
305 qGainMismatch);
306
307 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
308 val &= 0xfffff000;
309 val |= (qGainMismatch) | (iGainMismatch << 6);
310 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
311
312 ath_print(common, ATH_DBG_CALIBRATE,
313 "ADC Gain Cal done for Chain %d\n", i);
314 }
315 }
316
317 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
318 REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
319 AR_PHY_NEW_ADC_GAIN_CORR_ENABLE);
320}
321
322static void ar9002_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
323{
324 struct ath_common *common = ath9k_hw_common(ah);
325 u32 iOddMeasOffset, iEvenMeasOffset, val, i;
326 int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch;
327 const struct ath9k_percal_data *calData =
328 ah->cal_list_curr->calData;
329 u32 numSamples =
330 (1 << (calData->calCountMax + 5)) * calData->calNumSamples;
331
332 for (i = 0; i < numChains; i++) {
333 iOddMeasOffset = ah->totalAdcDcOffsetIOddPhase[i];
334 iEvenMeasOffset = ah->totalAdcDcOffsetIEvenPhase[i];
335 qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i];
336 qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i];
337
338 ath_print(common, ATH_DBG_CALIBRATE,
339 "Starting ADC DC Offset Cal for Chain %d\n", i);
340
341 ath_print(common, ATH_DBG_CALIBRATE,
342 "Chn %d pwr_meas_odd_i = %d\n", i,
343 iOddMeasOffset);
344 ath_print(common, ATH_DBG_CALIBRATE,
345 "Chn %d pwr_meas_even_i = %d\n", i,
346 iEvenMeasOffset);
347 ath_print(common, ATH_DBG_CALIBRATE,
348 "Chn %d pwr_meas_odd_q = %d\n", i,
349 qOddMeasOffset);
350 ath_print(common, ATH_DBG_CALIBRATE,
351 "Chn %d pwr_meas_even_q = %d\n", i,
352 qEvenMeasOffset);
353
354 iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
355 numSamples) & 0x1ff;
356 qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
357 numSamples) & 0x1ff;
358
359 ath_print(common, ATH_DBG_CALIBRATE,
360 "Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
361 iDcMismatch);
362 ath_print(common, ATH_DBG_CALIBRATE,
363 "Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
364 qDcMismatch);
365
366 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
367 val &= 0xc0000fff;
368 val |= (qDcMismatch << 12) | (iDcMismatch << 21);
369 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
370
371 ath_print(common, ATH_DBG_CALIBRATE,
372 "ADC DC Offset Cal done for Chain %d\n", i);
373 }
374
375 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
376 REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
377 AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
378}
379
380static void ar9287_hw_olc_temp_compensation(struct ath_hw *ah)
381{
382 u32 rddata;
383 int32_t delta, currPDADC, slope;
384
385 rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
386 currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
387
388 if (ah->initPDADC == 0 || currPDADC == 0) {
389 /*
390 * Zero value indicates that no frames have been transmitted
391 * yet, can't do temperature compensation until frames are
392 * transmitted.
393 */
394 return;
395 } else {
396 slope = ah->eep_ops->get_eeprom(ah, EEP_TEMPSENSE_SLOPE);
397
398 if (slope == 0) { /* to avoid divide by zero case */
399 delta = 0;
400 } else {
401 delta = ((currPDADC - ah->initPDADC)*4) / slope;
402 }
403 REG_RMW_FIELD(ah, AR_PHY_CH0_TX_PWRCTRL11,
404 AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
405 REG_RMW_FIELD(ah, AR_PHY_CH1_TX_PWRCTRL11,
406 AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
407 }
408}
409
410static void ar9280_hw_olc_temp_compensation(struct ath_hw *ah)
411{
412 u32 rddata, i;
413 int delta, currPDADC, regval;
414
415 rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
416 currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
417
418 if (ah->initPDADC == 0 || currPDADC == 0)
419 return;
420
421 if (ah->eep_ops->get_eeprom(ah, EEP_DAC_HPWR_5G))
422 delta = (currPDADC - ah->initPDADC + 4) / 8;
423 else
424 delta = (currPDADC - ah->initPDADC + 5) / 10;
425
426 if (delta != ah->PDADCdelta) {
427 ah->PDADCdelta = delta;
428 for (i = 1; i < AR9280_TX_GAIN_TABLE_SIZE; i++) {
429 regval = ah->originalGain[i] - delta;
430 if (regval < 0)
431 regval = 0;
432
433 REG_RMW_FIELD(ah,
434 AR_PHY_TX_GAIN_TBL1 + i * 4,
435 AR_PHY_TX_GAIN, regval);
436 }
437 }
438}
439
440static void ar9271_hw_pa_cal(struct ath_hw *ah, bool is_reset)
441{
442 u32 regVal;
443 unsigned int i;
444 u32 regList[][2] = {
445 { 0x786c, 0 },
446 { 0x7854, 0 },
447 { 0x7820, 0 },
448 { 0x7824, 0 },
449 { 0x7868, 0 },
450 { 0x783c, 0 },
451 { 0x7838, 0 } ,
452 { 0x7828, 0 } ,
453 };
454
455 for (i = 0; i < ARRAY_SIZE(regList); i++)
456 regList[i][1] = REG_READ(ah, regList[i][0]);
457
458 regVal = REG_READ(ah, 0x7834);
459 regVal &= (~(0x1));
460 REG_WRITE(ah, 0x7834, regVal);
461 regVal = REG_READ(ah, 0x9808);
462 regVal |= (0x1 << 27);
463 REG_WRITE(ah, 0x9808, regVal);
464
465 /* 786c,b23,1, pwddac=1 */
466 REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
467 /* 7854, b5,1, pdrxtxbb=1 */
468 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
469 /* 7854, b7,1, pdv2i=1 */
470 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
471 /* 7854, b8,1, pddacinterface=1 */
472 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
473 /* 7824,b12,0, offcal=0 */
474 REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
475 /* 7838, b1,0, pwddb=0 */
476 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
477 /* 7820,b11,0, enpacal=0 */
478 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
479 /* 7820,b25,1, pdpadrv1=0 */
480 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
481 /* 7820,b24,0, pdpadrv2=0 */
482 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0);
483 /* 7820,b23,0, pdpaout=0 */
484 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
485 /* 783c,b14-16,7, padrvgn2tab_0=7 */
486 REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
487 /*
488 * 7838,b29-31,0, padrvgn1tab_0=0
489 * does not matter since we turn it off
490 */
491 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
492
493 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9271_AN_RF2G3_CCOMP, 0xfff);
494
495 /* Set:
496 * localmode=1,bmode=1,bmoderxtx=1,synthon=1,
497 * txon=1,paon=1,oscon=1,synthon_force=1
498 */
499 REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
500 udelay(30);
501 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9271_AN_RF2G6_OFFS, 0);
502
503 /* find off_6_1; */
504 for (i = 6; i > 0; i--) {
505 regVal = REG_READ(ah, 0x7834);
506 regVal |= (1 << (20 + i));
507 REG_WRITE(ah, 0x7834, regVal);
508 udelay(1);
509 /* regVal = REG_READ(ah, 0x7834); */
510 regVal &= (~(0x1 << (20 + i)));
511 regVal |= (MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9)
512 << (20 + i));
513 REG_WRITE(ah, 0x7834, regVal);
514 }
515
516 regVal = (regVal >> 20) & 0x7f;
517
518 /* Update PA cal info */
519 if ((!is_reset) && (ah->pacal_info.prev_offset == regVal)) {
520 if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
521 ah->pacal_info.max_skipcount =
522 2 * ah->pacal_info.max_skipcount;
523 ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
524 } else {
525 ah->pacal_info.max_skipcount = 1;
526 ah->pacal_info.skipcount = 0;
527 ah->pacal_info.prev_offset = regVal;
528 }
529
530 ENABLE_REGWRITE_BUFFER(ah);
531
532 regVal = REG_READ(ah, 0x7834);
533 regVal |= 0x1;
534 REG_WRITE(ah, 0x7834, regVal);
535 regVal = REG_READ(ah, 0x9808);
536 regVal &= (~(0x1 << 27));
537 REG_WRITE(ah, 0x9808, regVal);
538
539 for (i = 0; i < ARRAY_SIZE(regList); i++)
540 REG_WRITE(ah, regList[i][0], regList[i][1]);
541
542 REGWRITE_BUFFER_FLUSH(ah);
543 DISABLE_REGWRITE_BUFFER(ah);
544}
545
546static inline void ar9285_hw_pa_cal(struct ath_hw *ah, bool is_reset)
547{
548 struct ath_common *common = ath9k_hw_common(ah);
549 u32 regVal;
550 int i, offset, offs_6_1, offs_0;
551 u32 ccomp_org, reg_field;
552 u32 regList[][2] = {
553 { 0x786c, 0 },
554 { 0x7854, 0 },
555 { 0x7820, 0 },
556 { 0x7824, 0 },
557 { 0x7868, 0 },
558 { 0x783c, 0 },
559 { 0x7838, 0 },
560 };
561
562 ath_print(common, ATH_DBG_CALIBRATE, "Running PA Calibration\n");
563
564 /* PA CAL is not needed for high power solution */
565 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) ==
566 AR5416_EEP_TXGAIN_HIGH_POWER)
567 return;
568
569 if (AR_SREV_9285_11(ah)) {
570 REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
571 udelay(10);
572 }
573
574 for (i = 0; i < ARRAY_SIZE(regList); i++)
575 regList[i][1] = REG_READ(ah, regList[i][0]);
576
577 regVal = REG_READ(ah, 0x7834);
578 regVal &= (~(0x1));
579 REG_WRITE(ah, 0x7834, regVal);
580 regVal = REG_READ(ah, 0x9808);
581 regVal |= (0x1 << 27);
582 REG_WRITE(ah, 0x9808, regVal);
583
584 REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
585 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
586 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
587 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
588 REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
589 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
590 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
591 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
592 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0);
593 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
594 REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
595 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
596 ccomp_org = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP);
597 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, 0xf);
598
599 REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
600 udelay(30);
601 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, 0);
602 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 0);
603
604 for (i = 6; i > 0; i--) {
605 regVal = REG_READ(ah, 0x7834);
606 regVal |= (1 << (19 + i));
607 REG_WRITE(ah, 0x7834, regVal);
608 udelay(1);
609 regVal = REG_READ(ah, 0x7834);
610 regVal &= (~(0x1 << (19 + i)));
611 reg_field = MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9);
612 regVal |= (reg_field << (19 + i));
613 REG_WRITE(ah, 0x7834, regVal);
614 }
615
616 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 1);
617 udelay(1);
618 reg_field = MS(REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9);
619 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, reg_field);
620 offs_6_1 = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS);
621 offs_0 = MS(REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP);
622
623 offset = (offs_6_1<<1) | offs_0;
624 offset = offset - 0;
625 offs_6_1 = offset>>1;
626 offs_0 = offset & 1;
627
628 if ((!is_reset) && (ah->pacal_info.prev_offset == offset)) {
629 if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
630 ah->pacal_info.max_skipcount =
631 2 * ah->pacal_info.max_skipcount;
632 ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
633 } else {
634 ah->pacal_info.max_skipcount = 1;
635 ah->pacal_info.skipcount = 0;
636 ah->pacal_info.prev_offset = offset;
637 }
638
639 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1);
640 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0);
641
642 regVal = REG_READ(ah, 0x7834);
643 regVal |= 0x1;
644 REG_WRITE(ah, 0x7834, regVal);
645 regVal = REG_READ(ah, 0x9808);
646 regVal &= (~(0x1 << 27));
647 REG_WRITE(ah, 0x9808, regVal);
648
649 for (i = 0; i < ARRAY_SIZE(regList); i++)
650 REG_WRITE(ah, regList[i][0], regList[i][1]);
651
652 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, ccomp_org);
653
654 if (AR_SREV_9285_11(ah))
655 REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);
656
657}
658
659static void ar9002_hw_pa_cal(struct ath_hw *ah, bool is_reset)
660{
661 if (AR_SREV_9271(ah)) {
662 if (is_reset || !ah->pacal_info.skipcount)
663 ar9271_hw_pa_cal(ah, is_reset);
664 else
665 ah->pacal_info.skipcount--;
666 } else if (AR_SREV_9285_11_OR_LATER(ah)) {
667 if (is_reset || !ah->pacal_info.skipcount)
668 ar9285_hw_pa_cal(ah, is_reset);
669 else
670 ah->pacal_info.skipcount--;
671 }
672}
673
674static void ar9002_hw_olc_temp_compensation(struct ath_hw *ah)
675{
676 if (OLC_FOR_AR9287_10_LATER)
677 ar9287_hw_olc_temp_compensation(ah);
678 else if (OLC_FOR_AR9280_20_LATER)
679 ar9280_hw_olc_temp_compensation(ah);
680}
681
682static bool ar9002_hw_calibrate(struct ath_hw *ah,
683 struct ath9k_channel *chan,
684 u8 rxchainmask,
685 bool longcal)
686{
687 bool iscaldone = true;
688 struct ath9k_cal_list *currCal = ah->cal_list_curr;
689
690 if (currCal &&
691 (currCal->calState == CAL_RUNNING ||
692 currCal->calState == CAL_WAITING)) {
693 iscaldone = ar9002_hw_per_calibration(ah, chan,
694 rxchainmask, currCal);
695 if (iscaldone) {
696 ah->cal_list_curr = currCal = currCal->calNext;
697
698 if (currCal->calState == CAL_WAITING) {
699 iscaldone = false;
700 ath9k_hw_reset_calibration(ah, currCal);
701 }
702 }
703 }
704
705 /* Do NF cal only at longer intervals */
706 if (longcal) {
707 /* Do periodic PAOffset Cal */
708 ar9002_hw_pa_cal(ah, false);
709 ar9002_hw_olc_temp_compensation(ah);
710
711 /*
712 * Get the value from the previous NF cal and update
713 * history buffer.
714 */
715 ath9k_hw_getnf(ah, chan);
716
717 /*
718 * Load the NF from history buffer of the current channel.
719 * NF is slow time-variant, so it is OK to use a historical
720 * value.
721 */
722 ath9k_hw_loadnf(ah, ah->curchan);
723
724 ath9k_hw_start_nfcal(ah);
725 }
726
727 return iscaldone;
728}
729
730/* Carrier leakage Calibration fix */
731static bool ar9285_hw_cl_cal(struct ath_hw *ah, struct ath9k_channel *chan)
732{
733 struct ath_common *common = ath9k_hw_common(ah);
734
735 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
736 if (IS_CHAN_HT20(chan)) {
737 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
738 REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
739 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
740 AR_PHY_AGC_CONTROL_FLTR_CAL);
741 REG_CLR_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
742 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
743 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
744 AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) {
745 ath_print(common, ATH_DBG_CALIBRATE, "offset "
746 "calibration failed to complete in "
747 "1ms; noisy ??\n");
748 return false;
749 }
750 REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
751 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
752 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
753 }
754 REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
755 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
756 REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
757 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
758 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
759 0, AH_WAIT_TIMEOUT)) {
760 ath_print(common, ATH_DBG_CALIBRATE, "offset calibration "
761 "failed to complete in 1ms; noisy ??\n");
762 return false;
763 }
764
765 REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
766 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
767 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
768
769 return true;
770}
771
772static bool ar9285_hw_clc(struct ath_hw *ah, struct ath9k_channel *chan)
773{
774 int i;
775 u_int32_t txgain_max;
776 u_int32_t clc_gain, gain_mask = 0, clc_num = 0;
777 u_int32_t reg_clc_I0, reg_clc_Q0;
778 u_int32_t i0_num = 0;
779 u_int32_t q0_num = 0;
780 u_int32_t total_num = 0;
781 u_int32_t reg_rf2g5_org;
782 bool retv = true;
783
784 if (!(ar9285_hw_cl_cal(ah, chan)))
785 return false;
786
787 txgain_max = MS(REG_READ(ah, AR_PHY_TX_PWRCTRL7),
788 AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX);
789
790 for (i = 0; i < (txgain_max+1); i++) {
791 clc_gain = (REG_READ(ah, (AR_PHY_TX_GAIN_TBL1+(i<<2))) &
792 AR_PHY_TX_GAIN_CLC) >> AR_PHY_TX_GAIN_CLC_S;
793 if (!(gain_mask & (1 << clc_gain))) {
794 gain_mask |= (1 << clc_gain);
795 clc_num++;
796 }
797 }
798
799 for (i = 0; i < clc_num; i++) {
800 reg_clc_I0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))
801 & AR_PHY_CLC_I0) >> AR_PHY_CLC_I0_S;
802 reg_clc_Q0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))
803 & AR_PHY_CLC_Q0) >> AR_PHY_CLC_Q0_S;
804 if (reg_clc_I0 == 0)
805 i0_num++;
806
807 if (reg_clc_Q0 == 0)
808 q0_num++;
809 }
810 total_num = i0_num + q0_num;
811 if (total_num > AR9285_CLCAL_REDO_THRESH) {
812 reg_rf2g5_org = REG_READ(ah, AR9285_RF2G5);
813 if (AR_SREV_9285E_20(ah)) {
814 REG_WRITE(ah, AR9285_RF2G5,
815 (reg_rf2g5_org & AR9285_RF2G5_IC50TX) |
816 AR9285_RF2G5_IC50TX_XE_SET);
817 } else {
818 REG_WRITE(ah, AR9285_RF2G5,
819 (reg_rf2g5_org & AR9285_RF2G5_IC50TX) |
820 AR9285_RF2G5_IC50TX_SET);
821 }
822 retv = ar9285_hw_cl_cal(ah, chan);
823 REG_WRITE(ah, AR9285_RF2G5, reg_rf2g5_org);
824 }
825 return retv;
826}
827
828static bool ar9002_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
829{
830 struct ath_common *common = ath9k_hw_common(ah);
831
832 if (AR_SREV_9271(ah) || AR_SREV_9285_12_OR_LATER(ah)) {
833 if (!ar9285_hw_clc(ah, chan))
834 return false;
835 } else {
836 if (AR_SREV_9280_10_OR_LATER(ah)) {
837 if (!AR_SREV_9287_10_OR_LATER(ah))
838 REG_CLR_BIT(ah, AR_PHY_ADC_CTL,
839 AR_PHY_ADC_CTL_OFF_PWDADC);
840 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
841 AR_PHY_AGC_CONTROL_FLTR_CAL);
842 }
843
844 /* Calibrate the AGC */
845 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
846 REG_READ(ah, AR_PHY_AGC_CONTROL) |
847 AR_PHY_AGC_CONTROL_CAL);
848
849 /* Poll for offset calibration complete */
850 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
851 AR_PHY_AGC_CONTROL_CAL,
852 0, AH_WAIT_TIMEOUT)) {
853 ath_print(common, ATH_DBG_CALIBRATE,
854 "offset calibration failed to "
855 "complete in 1ms; noisy environment?\n");
856 return false;
857 }
858
859 if (AR_SREV_9280_10_OR_LATER(ah)) {
860 if (!AR_SREV_9287_10_OR_LATER(ah))
861 REG_SET_BIT(ah, AR_PHY_ADC_CTL,
862 AR_PHY_ADC_CTL_OFF_PWDADC);
863 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
864 AR_PHY_AGC_CONTROL_FLTR_CAL);
865 }
866 }
867
868 /* Do PA Calibration */
869 ar9002_hw_pa_cal(ah, true);
870
871 /* Do NF Calibration after DC offset and other calibrations */
872 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
873 REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_NF);
874
875 ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
876
877 /* Enable IQ, ADC Gain and ADC DC offset CALs */
878 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
879 if (ar9002_hw_iscal_supported(ah, ADC_GAIN_CAL)) {
880 INIT_CAL(&ah->adcgain_caldata);
881 INSERT_CAL(ah, &ah->adcgain_caldata);
882 ath_print(common, ATH_DBG_CALIBRATE,
883 "enabling ADC Gain Calibration.\n");
884 }
885 if (ar9002_hw_iscal_supported(ah, ADC_DC_CAL)) {
886 INIT_CAL(&ah->adcdc_caldata);
887 INSERT_CAL(ah, &ah->adcdc_caldata);
888 ath_print(common, ATH_DBG_CALIBRATE,
889 "enabling ADC DC Calibration.\n");
890 }
891 if (ar9002_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {
892 INIT_CAL(&ah->iq_caldata);
893 INSERT_CAL(ah, &ah->iq_caldata);
894 ath_print(common, ATH_DBG_CALIBRATE,
895 "enabling IQ Calibration.\n");
896 }
897
898 ah->cal_list_curr = ah->cal_list;
899
900 if (ah->cal_list_curr)
901 ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
902 }
903
904 chan->CalValid = 0;
905
906 return true;
907}
908
909static const struct ath9k_percal_data iq_cal_multi_sample = {
910 IQ_MISMATCH_CAL,
911 MAX_CAL_SAMPLES,
912 PER_MIN_LOG_COUNT,
913 ar9002_hw_iqcal_collect,
914 ar9002_hw_iqcalibrate
915};
916static const struct ath9k_percal_data iq_cal_single_sample = {
917 IQ_MISMATCH_CAL,
918 MIN_CAL_SAMPLES,
919 PER_MAX_LOG_COUNT,
920 ar9002_hw_iqcal_collect,
921 ar9002_hw_iqcalibrate
922};
923static const struct ath9k_percal_data adc_gain_cal_multi_sample = {
924 ADC_GAIN_CAL,
925 MAX_CAL_SAMPLES,
926 PER_MIN_LOG_COUNT,
927 ar9002_hw_adc_gaincal_collect,
928 ar9002_hw_adc_gaincal_calibrate
929};
930static const struct ath9k_percal_data adc_gain_cal_single_sample = {
931 ADC_GAIN_CAL,
932 MIN_CAL_SAMPLES,
933 PER_MAX_LOG_COUNT,
934 ar9002_hw_adc_gaincal_collect,
935 ar9002_hw_adc_gaincal_calibrate
936};
937static const struct ath9k_percal_data adc_dc_cal_multi_sample = {
938 ADC_DC_CAL,
939 MAX_CAL_SAMPLES,
940 PER_MIN_LOG_COUNT,
941 ar9002_hw_adc_dccal_collect,
942 ar9002_hw_adc_dccal_calibrate
943};
944static const struct ath9k_percal_data adc_dc_cal_single_sample = {
945 ADC_DC_CAL,
946 MIN_CAL_SAMPLES,
947 PER_MAX_LOG_COUNT,
948 ar9002_hw_adc_dccal_collect,
949 ar9002_hw_adc_dccal_calibrate
950};
951static const struct ath9k_percal_data adc_init_dc_cal = {
952 ADC_DC_INIT_CAL,
953 MIN_CAL_SAMPLES,
954 INIT_LOG_COUNT,
955 ar9002_hw_adc_dccal_collect,
956 ar9002_hw_adc_dccal_calibrate
957};
958
959static void ar9002_hw_init_cal_settings(struct ath_hw *ah)
960{
961 if (AR_SREV_9100(ah)) {
962 ah->iq_caldata.calData = &iq_cal_multi_sample;
963 ah->supp_cals = IQ_MISMATCH_CAL;
964 return;
965 }
966
967 if (AR_SREV_9160_10_OR_LATER(ah)) {
968 if (AR_SREV_9280_10_OR_LATER(ah)) {
969 ah->iq_caldata.calData = &iq_cal_single_sample;
970 ah->adcgain_caldata.calData =
971 &adc_gain_cal_single_sample;
972 ah->adcdc_caldata.calData =
973 &adc_dc_cal_single_sample;
974 ah->adcdc_calinitdata.calData =
975 &adc_init_dc_cal;
976 } else {
977 ah->iq_caldata.calData = &iq_cal_multi_sample;
978 ah->adcgain_caldata.calData =
979 &adc_gain_cal_multi_sample;
980 ah->adcdc_caldata.calData =
981 &adc_dc_cal_multi_sample;
982 ah->adcdc_calinitdata.calData =
983 &adc_init_dc_cal;
984 }
985 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
986 }
987}
988
989void ar9002_hw_attach_calib_ops(struct ath_hw *ah)
990{
991 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
992 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
993
994 priv_ops->init_cal_settings = ar9002_hw_init_cal_settings;
995 priv_ops->init_cal = ar9002_hw_init_cal;
996 priv_ops->setup_calibration = ar9002_hw_setup_calibration;
997 priv_ops->iscal_supported = ar9002_hw_iscal_supported;
998
999 ops->calibrate = ar9002_hw_calibrate;
1000}
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_hw.c b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
new file mode 100644
index 000000000000..a8a8cdc04afa
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
@@ -0,0 +1,598 @@
1/*
2 * Copyright (c) 2008-2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "hw.h"
18#include "ar5008_initvals.h"
19#include "ar9001_initvals.h"
20#include "ar9002_initvals.h"
21
22/* General hardware code for the A5008/AR9001/AR9002 hadware families */
23
24static bool ar9002_hw_macversion_supported(u32 macversion)
25{
26 switch (macversion) {
27 case AR_SREV_VERSION_5416_PCI:
28 case AR_SREV_VERSION_5416_PCIE:
29 case AR_SREV_VERSION_9160:
30 case AR_SREV_VERSION_9100:
31 case AR_SREV_VERSION_9280:
32 case AR_SREV_VERSION_9285:
33 case AR_SREV_VERSION_9287:
34 case AR_SREV_VERSION_9271:
35 return true;
36 default:
37 break;
38 }
39 return false;
40}
41
42static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
43{
44 if (AR_SREV_9271(ah)) {
45 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
46 ARRAY_SIZE(ar9271Modes_9271), 6);
47 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
48 ARRAY_SIZE(ar9271Common_9271), 2);
49 INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271,
50 ar9271Common_normal_cck_fir_coeff_9271,
51 ARRAY_SIZE(ar9271Common_normal_cck_fir_coeff_9271), 2);
52 INIT_INI_ARRAY(&ah->iniCommon_japan_2484_cck_fir_coeff_9271,
53 ar9271Common_japan_2484_cck_fir_coeff_9271,
54 ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271), 2);
55 INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
56 ar9271Modes_9271_1_0_only,
57 ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
58 INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg,
59 ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 6);
60 INIT_INI_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
61 ar9271Modes_high_power_tx_gain_9271,
62 ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 6);
63 INIT_INI_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
64 ar9271Modes_normal_power_tx_gain_9271,
65 ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 6);
66 return;
67 }
68
69 if (AR_SREV_9287_11_OR_LATER(ah)) {
70 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
71 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
72 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
73 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
74 if (ah->config.pcie_clock_req)
75 INIT_INI_ARRAY(&ah->iniPcieSerdes,
76 ar9287PciePhy_clkreq_off_L1_9287_1_1,
77 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
78 else
79 INIT_INI_ARRAY(&ah->iniPcieSerdes,
80 ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
81 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
82 2);
83 } else if (AR_SREV_9287_10_OR_LATER(ah)) {
84 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
85 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
86 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
87 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
88
89 if (ah->config.pcie_clock_req)
90 INIT_INI_ARRAY(&ah->iniPcieSerdes,
91 ar9287PciePhy_clkreq_off_L1_9287_1_0,
92 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
93 else
94 INIT_INI_ARRAY(&ah->iniPcieSerdes,
95 ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
96 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
97 2);
98 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
99
100
101 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
102 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
103 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
104 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
105
106 if (ah->config.pcie_clock_req) {
107 INIT_INI_ARRAY(&ah->iniPcieSerdes,
108 ar9285PciePhy_clkreq_off_L1_9285_1_2,
109 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
110 } else {
111 INIT_INI_ARRAY(&ah->iniPcieSerdes,
112 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
113 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
114 2);
115 }
116 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
117 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
118 ARRAY_SIZE(ar9285Modes_9285), 6);
119 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
120 ARRAY_SIZE(ar9285Common_9285), 2);
121
122 if (ah->config.pcie_clock_req) {
123 INIT_INI_ARRAY(&ah->iniPcieSerdes,
124 ar9285PciePhy_clkreq_off_L1_9285,
125 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
126 } else {
127 INIT_INI_ARRAY(&ah->iniPcieSerdes,
128 ar9285PciePhy_clkreq_always_on_L1_9285,
129 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
130 }
131 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
132 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
133 ARRAY_SIZE(ar9280Modes_9280_2), 6);
134 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
135 ARRAY_SIZE(ar9280Common_9280_2), 2);
136
137 if (ah->config.pcie_clock_req) {
138 INIT_INI_ARRAY(&ah->iniPcieSerdes,
139 ar9280PciePhy_clkreq_off_L1_9280,
140 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280), 2);
141 } else {
142 INIT_INI_ARRAY(&ah->iniPcieSerdes,
143 ar9280PciePhy_clkreq_always_on_L1_9280,
144 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
145 }
146 INIT_INI_ARRAY(&ah->iniModesAdditional,
147 ar9280Modes_fast_clock_9280_2,
148 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
149 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
150 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
151 ARRAY_SIZE(ar9280Modes_9280), 6);
152 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
153 ARRAY_SIZE(ar9280Common_9280), 2);
154 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
155 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
156 ARRAY_SIZE(ar5416Modes_9160), 6);
157 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
158 ARRAY_SIZE(ar5416Common_9160), 2);
159 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
160 ARRAY_SIZE(ar5416Bank0_9160), 2);
161 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
162 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
163 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
164 ARRAY_SIZE(ar5416Bank1_9160), 2);
165 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
166 ARRAY_SIZE(ar5416Bank2_9160), 2);
167 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
168 ARRAY_SIZE(ar5416Bank3_9160), 3);
169 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
170 ARRAY_SIZE(ar5416Bank6_9160), 3);
171 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
172 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
173 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
174 ARRAY_SIZE(ar5416Bank7_9160), 2);
175 if (AR_SREV_9160_11(ah)) {
176 INIT_INI_ARRAY(&ah->iniAddac,
177 ar5416Addac_91601_1,
178 ARRAY_SIZE(ar5416Addac_91601_1), 2);
179 } else {
180 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
181 ARRAY_SIZE(ar5416Addac_9160), 2);
182 }
183 } else if (AR_SREV_9100_OR_LATER(ah)) {
184 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
185 ARRAY_SIZE(ar5416Modes_9100), 6);
186 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
187 ARRAY_SIZE(ar5416Common_9100), 2);
188 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
189 ARRAY_SIZE(ar5416Bank0_9100), 2);
190 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
191 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
192 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
193 ARRAY_SIZE(ar5416Bank1_9100), 2);
194 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
195 ARRAY_SIZE(ar5416Bank2_9100), 2);
196 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
197 ARRAY_SIZE(ar5416Bank3_9100), 3);
198 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
199 ARRAY_SIZE(ar5416Bank6_9100), 3);
200 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
201 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
202 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
203 ARRAY_SIZE(ar5416Bank7_9100), 2);
204 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
205 ARRAY_SIZE(ar5416Addac_9100), 2);
206 } else {
207 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
208 ARRAY_SIZE(ar5416Modes), 6);
209 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
210 ARRAY_SIZE(ar5416Common), 2);
211 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
212 ARRAY_SIZE(ar5416Bank0), 2);
213 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
214 ARRAY_SIZE(ar5416BB_RfGain), 3);
215 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
216 ARRAY_SIZE(ar5416Bank1), 2);
217 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
218 ARRAY_SIZE(ar5416Bank2), 2);
219 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
220 ARRAY_SIZE(ar5416Bank3), 3);
221 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
222 ARRAY_SIZE(ar5416Bank6), 3);
223 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
224 ARRAY_SIZE(ar5416Bank6TPC), 3);
225 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
226 ARRAY_SIZE(ar5416Bank7), 2);
227 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
228 ARRAY_SIZE(ar5416Addac), 2);
229 }
230}
231
232/* Support for Japan ch.14 (2484) spread */
233void ar9002_hw_cck_chan14_spread(struct ath_hw *ah)
234{
235 if (AR_SREV_9287_11_OR_LATER(ah)) {
236 INIT_INI_ARRAY(&ah->iniCckfirNormal,
237 ar9287Common_normal_cck_fir_coeff_92871_1,
238 ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1),
239 2);
240 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
241 ar9287Common_japan_2484_cck_fir_coeff_92871_1,
242 ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1),
243 2);
244 }
245}
246
247static void ar9280_20_hw_init_rxgain_ini(struct ath_hw *ah)
248{
249 u32 rxgain_type;
250
251 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >=
252 AR5416_EEP_MINOR_VER_17) {
253 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
254
255 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
256 INIT_INI_ARRAY(&ah->iniModesRxGain,
257 ar9280Modes_backoff_13db_rxgain_9280_2,
258 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
259 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
260 INIT_INI_ARRAY(&ah->iniModesRxGain,
261 ar9280Modes_backoff_23db_rxgain_9280_2,
262 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
263 else
264 INIT_INI_ARRAY(&ah->iniModesRxGain,
265 ar9280Modes_original_rxgain_9280_2,
266 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
267 } else {
268 INIT_INI_ARRAY(&ah->iniModesRxGain,
269 ar9280Modes_original_rxgain_9280_2,
270 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
271 }
272}
273
274static void ar9280_20_hw_init_txgain_ini(struct ath_hw *ah)
275{
276 u32 txgain_type;
277
278 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >=
279 AR5416_EEP_MINOR_VER_19) {
280 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
281
282 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
283 INIT_INI_ARRAY(&ah->iniModesTxGain,
284 ar9280Modes_high_power_tx_gain_9280_2,
285 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
286 else
287 INIT_INI_ARRAY(&ah->iniModesTxGain,
288 ar9280Modes_original_tx_gain_9280_2,
289 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
290 } else {
291 INIT_INI_ARRAY(&ah->iniModesTxGain,
292 ar9280Modes_original_tx_gain_9280_2,
293 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
294 }
295}
296
297static void ar9002_hw_init_mode_gain_regs(struct ath_hw *ah)
298{
299 if (AR_SREV_9287_11_OR_LATER(ah))
300 INIT_INI_ARRAY(&ah->iniModesRxGain,
301 ar9287Modes_rx_gain_9287_1_1,
302 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
303 else if (AR_SREV_9287_10(ah))
304 INIT_INI_ARRAY(&ah->iniModesRxGain,
305 ar9287Modes_rx_gain_9287_1_0,
306 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
307 else if (AR_SREV_9280_20(ah))
308 ar9280_20_hw_init_rxgain_ini(ah);
309
310 if (AR_SREV_9287_11_OR_LATER(ah)) {
311 INIT_INI_ARRAY(&ah->iniModesTxGain,
312 ar9287Modes_tx_gain_9287_1_1,
313 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
314 } else if (AR_SREV_9287_10(ah)) {
315 INIT_INI_ARRAY(&ah->iniModesTxGain,
316 ar9287Modes_tx_gain_9287_1_0,
317 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
318 } else if (AR_SREV_9280_20(ah)) {
319 ar9280_20_hw_init_txgain_ini(ah);
320 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
321 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
322
323 /* txgain table */
324 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
325 if (AR_SREV_9285E_20(ah)) {
326 INIT_INI_ARRAY(&ah->iniModesTxGain,
327 ar9285Modes_XE2_0_high_power,
328 ARRAY_SIZE(
329 ar9285Modes_XE2_0_high_power), 6);
330 } else {
331 INIT_INI_ARRAY(&ah->iniModesTxGain,
332 ar9285Modes_high_power_tx_gain_9285_1_2,
333 ARRAY_SIZE(
334 ar9285Modes_high_power_tx_gain_9285_1_2), 6);
335 }
336 } else {
337 if (AR_SREV_9285E_20(ah)) {
338 INIT_INI_ARRAY(&ah->iniModesTxGain,
339 ar9285Modes_XE2_0_normal_power,
340 ARRAY_SIZE(
341 ar9285Modes_XE2_0_normal_power), 6);
342 } else {
343 INIT_INI_ARRAY(&ah->iniModesTxGain,
344 ar9285Modes_original_tx_gain_9285_1_2,
345 ARRAY_SIZE(
346 ar9285Modes_original_tx_gain_9285_1_2), 6);
347 }
348 }
349 }
350}
351
352/*
353 * Helper for ASPM support.
354 *
355 * Disable PLL when in L0s as well as receiver clock when in L1.
356 * This power saving option must be enabled through the SerDes.
357 *
358 * Programming the SerDes must go through the same 288 bit serial shift
359 * register as the other analog registers. Hence the 9 writes.
360 */
361static void ar9002_hw_configpcipowersave(struct ath_hw *ah,
362 int restore,
363 int power_off)
364{
365 u8 i;
366 u32 val;
367
368 if (ah->is_pciexpress != true)
369 return;
370
371 /* Do not touch SerDes registers */
372 if (ah->config.pcie_powersave_enable == 2)
373 return;
374
375 /* Nothing to do on restore for 11N */
376 if (!restore) {
377 if (AR_SREV_9280_20_OR_LATER(ah)) {
378 /*
379 * AR9280 2.0 or later chips use SerDes values from the
380 * initvals.h initialized depending on chipset during
381 * __ath9k_hw_init()
382 */
383 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
384 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
385 INI_RA(&ah->iniPcieSerdes, i, 1));
386 }
387 } else if (AR_SREV_9280(ah) &&
388 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
389 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
390 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
391
392 /* RX shut off when elecidle is asserted */
393 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
394 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
395 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
396
397 /* Shut off CLKREQ active in L1 */
398 if (ah->config.pcie_clock_req)
399 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
400 else
401 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
402
403 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
404 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
405 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
406
407 /* Load the new settings */
408 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
409
410 } else {
411 ENABLE_REGWRITE_BUFFER(ah);
412
413 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
414 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
415
416 /* RX shut off when elecidle is asserted */
417 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
418 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
419 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
420
421 /*
422 * Ignore ah->ah_config.pcie_clock_req setting for
423 * pre-AR9280 11n
424 */
425 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
426
427 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
428 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
429 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
430
431 /* Load the new settings */
432 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
433
434 REGWRITE_BUFFER_FLUSH(ah);
435 DISABLE_REGWRITE_BUFFER(ah);
436 }
437
438 udelay(1000);
439
440 /* set bit 19 to allow forcing of pcie core into L1 state */
441 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
442
443 /* Several PCIe massages to ensure proper behaviour */
444 if (ah->config.pcie_waen) {
445 val = ah->config.pcie_waen;
446 if (!power_off)
447 val &= (~AR_WA_D3_L1_DISABLE);
448 } else {
449 if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
450 AR_SREV_9287(ah)) {
451 val = AR9285_WA_DEFAULT;
452 if (!power_off)
453 val &= (~AR_WA_D3_L1_DISABLE);
454 } else if (AR_SREV_9280(ah)) {
455 /*
456 * On AR9280 chips bit 22 of 0x4004 needs to be
457 * set otherwise card may disappear.
458 */
459 val = AR9280_WA_DEFAULT;
460 if (!power_off)
461 val &= (~AR_WA_D3_L1_DISABLE);
462 } else
463 val = AR_WA_DEFAULT;
464 }
465
466 REG_WRITE(ah, AR_WA, val);
467 }
468
469 if (power_off) {
470 /*
471 * Set PCIe workaround bits
472 * bit 14 in WA register (disable L1) should only
473 * be set when device enters D3 and be cleared
474 * when device comes back to D0.
475 */
476 if (ah->config.pcie_waen) {
477 if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
478 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
479 } else {
480 if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
481 AR_SREV_9287(ah)) &&
482 (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
483 (AR_SREV_9280(ah) &&
484 (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
485 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
486 }
487 }
488 }
489}
490
491static int ar9002_hw_get_radiorev(struct ath_hw *ah)
492{
493 u32 val;
494 int i;
495
496 ENABLE_REGWRITE_BUFFER(ah);
497
498 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
499 for (i = 0; i < 8; i++)
500 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
501
502 REGWRITE_BUFFER_FLUSH(ah);
503 DISABLE_REGWRITE_BUFFER(ah);
504
505 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
506 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
507
508 return ath9k_hw_reverse_bits(val, 8);
509}
510
511int ar9002_hw_rf_claim(struct ath_hw *ah)
512{
513 u32 val;
514
515 REG_WRITE(ah, AR_PHY(0), 0x00000007);
516
517 val = ar9002_hw_get_radiorev(ah);
518 switch (val & AR_RADIO_SREV_MAJOR) {
519 case 0:
520 val = AR_RAD5133_SREV_MAJOR;
521 break;
522 case AR_RAD5133_SREV_MAJOR:
523 case AR_RAD5122_SREV_MAJOR:
524 case AR_RAD2133_SREV_MAJOR:
525 case AR_RAD2122_SREV_MAJOR:
526 break;
527 default:
528 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
529 "Radio Chip Rev 0x%02X not supported\n",
530 val & AR_RADIO_SREV_MAJOR);
531 return -EOPNOTSUPP;
532 }
533
534 ah->hw_version.analog5GhzRev = val;
535
536 return 0;
537}
538
539/*
540 * Enable ASYNC FIFO
541 *
542 * If Async FIFO is enabled, the following counters change as MAC now runs
543 * at 117 Mhz instead of 88/44MHz when async FIFO is disabled.
544 *
545 * The values below tested for ht40 2 chain.
546 * Overwrite the delay/timeouts initialized in process ini.
547 */
548void ar9002_hw_enable_async_fifo(struct ath_hw *ah)
549{
550 if (AR_SREV_9287_12_OR_LATER(ah)) {
551 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
552 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
553 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
554 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
555 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
556 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
557
558 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
559 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
560
561 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
562 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
563 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
564 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
565 }
566}
567
568/*
569 * We don't enable WEP aggregation on mac80211 but we keep this
570 * around for HAL unification purposes.
571 */
572void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah)
573{
574 if (AR_SREV_9287_12_OR_LATER(ah)) {
575 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
576 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
577 }
578}
579
580/* Sets up the AR5008/AR9001/AR9002 hardware familiy callbacks */
581void ar9002_hw_attach_ops(struct ath_hw *ah)
582{
583 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
584 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
585
586 priv_ops->init_mode_regs = ar9002_hw_init_mode_regs;
587 priv_ops->init_mode_gain_regs = ar9002_hw_init_mode_gain_regs;
588 priv_ops->macversion_supported = ar9002_hw_macversion_supported;
589
590 ops->config_pci_powersave = ar9002_hw_configpcipowersave;
591
592 ar5008_hw_attach_phy_ops(ah);
593 if (AR_SREV_9280_10_OR_LATER(ah))
594 ar9002_hw_attach_phy_ops(ah);
595
596 ar9002_hw_attach_calib_ops(ah);
597 ar9002_hw_attach_mac_ops(ah);
598}
diff --git a/drivers/net/wireless/ath/ath9k/initvals.h b/drivers/net/wireless/ath/ath9k/ar9002_initvals.h
index 455e9d3b3f13..dae7f3304eb8 100644
--- a/drivers/net/wireless/ath/ath9k/initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9002_initvals.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2008-2009 Atheros Communications Inc. 2 * Copyright (c) 2010 Atheros Communications Inc.
3 * 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any 4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above 5 * purpose with or without fee is hereby granted, provided that the above
@@ -14,1982 +14,9 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17static const u32 ar5416Modes[][6] = { 17#ifndef INITVALS_9002_10_H
18 { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 }, 18#define INITVALS_9002_10_H
19 { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
20 { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
21 { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },
22 { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
23 { 0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf },
24 { 0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810, 0x08f04810 },
25 { 0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a, 0x0000320a },
26 { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
27 { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
28 { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
29 { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
30 { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
31 { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
32 { 0x00009844, 0x1372161e, 0x1372161e, 0x137216a0, 0x137216a0, 0x137216a0 },
33 { 0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
34 { 0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
35 { 0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
36 { 0x00009850, 0x6c48b4e0, 0x6d48b4e0, 0x6d48b0de, 0x6c48b0de, 0x6c48b0de },
37 { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e },
38 { 0x0000985c, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e, 0x31395d5e },
39 { 0x00009860, 0x00049d18, 0x00049d18, 0x00049d18, 0x00049d18, 0x00049d18 },
40 { 0x00009864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
41 { 0x00009868, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190 },
42 { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 },
43 { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
44 { 0x00009918, 0x000001b8, 0x00000370, 0x00000268, 0x00000134, 0x00000134 },
45 { 0x00009924, 0xd0058a0b, 0xd0058a0b, 0xd0058a0b, 0xd0058a0b, 0xd0058a0b },
46 { 0x00009944, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020 },
47 { 0x00009960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80, 0x00012d80 },
48 { 0x0000a960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80, 0x00012d80 },
49 { 0x0000b960, 0x00000900, 0x00000900, 0x00012d80, 0x00012d80, 0x00012d80 },
50 { 0x00009964, 0x00000000, 0x00000000, 0x00001120, 0x00001120, 0x00001120 },
51 { 0x000099bc, 0x001a0a00, 0x001a0a00, 0x001a0a00, 0x001a0a00, 0x001a0a00 },
52 { 0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, 0x038919be },
53 { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
54 { 0x000099c8, 0x6af6532c, 0x6af6532c, 0x6af6532c, 0x6af6532c, 0x6af6532c },
55 { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
56 { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
57 { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
58 { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
59 { 0x0000a204, 0x00000880, 0x00000880, 0x00000880, 0x00000880, 0x00000880 },
60 { 0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788, 0xd03e4788 },
61 { 0x0000a20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 },
62 { 0x0000b20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 },
63 { 0x0000c20c, 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 },
64 { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
65 { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
66 { 0x0000a274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa, 0x0a1a7caa },
67 { 0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 },
68 { 0x0000a304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402, 0x2e032402 },
69 { 0x0000a308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06, 0x4a0a3c06 },
70 { 0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b, 0x621a540b },
71 { 0x0000a310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b, 0x764f6c1b },
72 { 0x0000a314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a, 0x845b7a5a },
73 { 0x0000a318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf, 0x950f8ccf },
74 { 0x0000a31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f, 0xa5cf9b4f },
75 { 0x0000a320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f, 0xbddfaf1f },
76 { 0x0000a324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f, 0xd1ffc93f },
77 { 0x0000a328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000, 0x00000000 },
78 { 0x0000a32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
79 { 0x0000a330, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
80 { 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
81};
82
83static const u32 ar5416Common[][2] = {
84 { 0x0000000c, 0x00000000 },
85 { 0x00000030, 0x00020015 },
86 { 0x00000034, 0x00000005 },
87 { 0x00000040, 0x00000000 },
88 { 0x00000044, 0x00000008 },
89 { 0x00000048, 0x00000008 },
90 { 0x0000004c, 0x00000010 },
91 { 0x00000050, 0x00000000 },
92 { 0x00000054, 0x0000001f },
93 { 0x00000800, 0x00000000 },
94 { 0x00000804, 0x00000000 },
95 { 0x00000808, 0x00000000 },
96 { 0x0000080c, 0x00000000 },
97 { 0x00000810, 0x00000000 },
98 { 0x00000814, 0x00000000 },
99 { 0x00000818, 0x00000000 },
100 { 0x0000081c, 0x00000000 },
101 { 0x00000820, 0x00000000 },
102 { 0x00000824, 0x00000000 },
103 { 0x00001040, 0x002ffc0f },
104 { 0x00001044, 0x002ffc0f },
105 { 0x00001048, 0x002ffc0f },
106 { 0x0000104c, 0x002ffc0f },
107 { 0x00001050, 0x002ffc0f },
108 { 0x00001054, 0x002ffc0f },
109 { 0x00001058, 0x002ffc0f },
110 { 0x0000105c, 0x002ffc0f },
111 { 0x00001060, 0x002ffc0f },
112 { 0x00001064, 0x002ffc0f },
113 { 0x00001230, 0x00000000 },
114 { 0x00001270, 0x00000000 },
115 { 0x00001038, 0x00000000 },
116 { 0x00001078, 0x00000000 },
117 { 0x000010b8, 0x00000000 },
118 { 0x000010f8, 0x00000000 },
119 { 0x00001138, 0x00000000 },
120 { 0x00001178, 0x00000000 },
121 { 0x000011b8, 0x00000000 },
122 { 0x000011f8, 0x00000000 },
123 { 0x00001238, 0x00000000 },
124 { 0x00001278, 0x00000000 },
125 { 0x000012b8, 0x00000000 },
126 { 0x000012f8, 0x00000000 },
127 { 0x00001338, 0x00000000 },
128 { 0x00001378, 0x00000000 },
129 { 0x000013b8, 0x00000000 },
130 { 0x000013f8, 0x00000000 },
131 { 0x00001438, 0x00000000 },
132 { 0x00001478, 0x00000000 },
133 { 0x000014b8, 0x00000000 },
134 { 0x000014f8, 0x00000000 },
135 { 0x00001538, 0x00000000 },
136 { 0x00001578, 0x00000000 },
137 { 0x000015b8, 0x00000000 },
138 { 0x000015f8, 0x00000000 },
139 { 0x00001638, 0x00000000 },
140 { 0x00001678, 0x00000000 },
141 { 0x000016b8, 0x00000000 },
142 { 0x000016f8, 0x00000000 },
143 { 0x00001738, 0x00000000 },
144 { 0x00001778, 0x00000000 },
145 { 0x000017b8, 0x00000000 },
146 { 0x000017f8, 0x00000000 },
147 { 0x0000103c, 0x00000000 },
148 { 0x0000107c, 0x00000000 },
149 { 0x000010bc, 0x00000000 },
150 { 0x000010fc, 0x00000000 },
151 { 0x0000113c, 0x00000000 },
152 { 0x0000117c, 0x00000000 },
153 { 0x000011bc, 0x00000000 },
154 { 0x000011fc, 0x00000000 },
155 { 0x0000123c, 0x00000000 },
156 { 0x0000127c, 0x00000000 },
157 { 0x000012bc, 0x00000000 },
158 { 0x000012fc, 0x00000000 },
159 { 0x0000133c, 0x00000000 },
160 { 0x0000137c, 0x00000000 },
161 { 0x000013bc, 0x00000000 },
162 { 0x000013fc, 0x00000000 },
163 { 0x0000143c, 0x00000000 },
164 { 0x0000147c, 0x00000000 },
165 { 0x00004030, 0x00000002 },
166 { 0x0000403c, 0x00000002 },
167 { 0x00007010, 0x00000000 },
168 { 0x00007038, 0x000004c2 },
169 { 0x00008004, 0x00000000 },
170 { 0x00008008, 0x00000000 },
171 { 0x0000800c, 0x00000000 },
172 { 0x00008018, 0x00000700 },
173 { 0x00008020, 0x00000000 },
174 { 0x00008038, 0x00000000 },
175 { 0x0000803c, 0x00000000 },
176 { 0x00008048, 0x40000000 },
177 { 0x00008054, 0x00000000 },
178 { 0x00008058, 0x00000000 },
179 { 0x0000805c, 0x000fc78f },
180 { 0x00008060, 0x0000000f },
181 { 0x00008064, 0x00000000 },
182 { 0x000080c0, 0x2a82301a },
183 { 0x000080c4, 0x05dc01e0 },
184 { 0x000080c8, 0x1f402710 },
185 { 0x000080cc, 0x01f40000 },
186 { 0x000080d0, 0x00001e00 },
187 { 0x000080d4, 0x00000000 },
188 { 0x000080d8, 0x00400000 },
189 { 0x000080e0, 0xffffffff },
190 { 0x000080e4, 0x0000ffff },
191 { 0x000080e8, 0x003f3f3f },
192 { 0x000080ec, 0x00000000 },
193 { 0x000080f0, 0x00000000 },
194 { 0x000080f4, 0x00000000 },
195 { 0x000080f8, 0x00000000 },
196 { 0x000080fc, 0x00020000 },
197 { 0x00008100, 0x00020000 },
198 { 0x00008104, 0x00000001 },
199 { 0x00008108, 0x00000052 },
200 { 0x0000810c, 0x00000000 },
201 { 0x00008110, 0x00000168 },
202 { 0x00008118, 0x000100aa },
203 { 0x0000811c, 0x00003210 },
204 { 0x00008124, 0x00000000 },
205 { 0x00008128, 0x00000000 },
206 { 0x0000812c, 0x00000000 },
207 { 0x00008130, 0x00000000 },
208 { 0x00008134, 0x00000000 },
209 { 0x00008138, 0x00000000 },
210 { 0x0000813c, 0x00000000 },
211 { 0x00008144, 0xffffffff },
212 { 0x00008168, 0x00000000 },
213 { 0x0000816c, 0x00000000 },
214 { 0x00008170, 0x32143320 },
215 { 0x00008174, 0xfaa4fa50 },
216 { 0x00008178, 0x00000100 },
217 { 0x0000817c, 0x00000000 },
218 { 0x000081c4, 0x00000000 },
219 { 0x000081ec, 0x00000000 },
220 { 0x000081f0, 0x00000000 },
221 { 0x000081f4, 0x00000000 },
222 { 0x000081f8, 0x00000000 },
223 { 0x000081fc, 0x00000000 },
224 { 0x00008200, 0x00000000 },
225 { 0x00008204, 0x00000000 },
226 { 0x00008208, 0x00000000 },
227 { 0x0000820c, 0x00000000 },
228 { 0x00008210, 0x00000000 },
229 { 0x00008214, 0x00000000 },
230 { 0x00008218, 0x00000000 },
231 { 0x0000821c, 0x00000000 },
232 { 0x00008220, 0x00000000 },
233 { 0x00008224, 0x00000000 },
234 { 0x00008228, 0x00000000 },
235 { 0x0000822c, 0x00000000 },
236 { 0x00008230, 0x00000000 },
237 { 0x00008234, 0x00000000 },
238 { 0x00008238, 0x00000000 },
239 { 0x0000823c, 0x00000000 },
240 { 0x00008240, 0x00100000 },
241 { 0x00008244, 0x0010f400 },
242 { 0x00008248, 0x00000100 },
243 { 0x0000824c, 0x0001e800 },
244 { 0x00008250, 0x00000000 },
245 { 0x00008254, 0x00000000 },
246 { 0x00008258, 0x00000000 },
247 { 0x0000825c, 0x400000ff },
248 { 0x00008260, 0x00080922 },
249 { 0x00008264, 0xa8000010 },
250 { 0x00008270, 0x00000000 },
251 { 0x00008274, 0x40000000 },
252 { 0x00008278, 0x003e4180 },
253 { 0x0000827c, 0x00000000 },
254 { 0x00008284, 0x0000002c },
255 { 0x00008288, 0x0000002c },
256 { 0x0000828c, 0x00000000 },
257 { 0x00008294, 0x00000000 },
258 { 0x00008298, 0x00000000 },
259 { 0x00008300, 0x00000000 },
260 { 0x00008304, 0x00000000 },
261 { 0x00008308, 0x00000000 },
262 { 0x0000830c, 0x00000000 },
263 { 0x00008310, 0x00000000 },
264 { 0x00008314, 0x00000000 },
265 { 0x00008318, 0x00000000 },
266 { 0x00008328, 0x00000000 },
267 { 0x0000832c, 0x00000007 },
268 { 0x00008330, 0x00000302 },
269 { 0x00008334, 0x00000e00 },
270 { 0x00008338, 0x00070000 },
271 { 0x0000833c, 0x00000000 },
272 { 0x00008340, 0x000107ff },
273 { 0x00009808, 0x00000000 },
274 { 0x0000980c, 0xad848e19 },
275 { 0x00009810, 0x7d14e000 },
276 { 0x00009814, 0x9c0a9f6b },
277 { 0x0000981c, 0x00000000 },
278 { 0x0000982c, 0x0000a000 },
279 { 0x00009830, 0x00000000 },
280 { 0x0000983c, 0x00200400 },
281 { 0x00009840, 0x206a002e },
282 { 0x0000984c, 0x1284233c },
283 { 0x00009854, 0x00000859 },
284 { 0x00009900, 0x00000000 },
285 { 0x00009904, 0x00000000 },
286 { 0x00009908, 0x00000000 },
287 { 0x0000990c, 0x00000000 },
288 { 0x0000991c, 0x10000fff },
289 { 0x00009920, 0x05100000 },
290 { 0x0000a920, 0x05100000 },
291 { 0x0000b920, 0x05100000 },
292 { 0x00009928, 0x00000001 },
293 { 0x0000992c, 0x00000004 },
294 { 0x00009934, 0x1e1f2022 },
295 { 0x00009938, 0x0a0b0c0d },
296 { 0x0000993c, 0x00000000 },
297 { 0x00009948, 0x9280b212 },
298 { 0x0000994c, 0x00020028 },
299 { 0x00009954, 0x5d50e188 },
300 { 0x00009958, 0x00081fff },
301 { 0x0000c95c, 0x004b6a8e },
302 { 0x0000c968, 0x000003ce },
303 { 0x00009970, 0x190fb515 },
304 { 0x00009974, 0x00000000 },
305 { 0x00009978, 0x00000001 },
306 { 0x0000997c, 0x00000000 },
307 { 0x00009980, 0x00000000 },
308 { 0x00009984, 0x00000000 },
309 { 0x00009988, 0x00000000 },
310 { 0x0000998c, 0x00000000 },
311 { 0x00009990, 0x00000000 },
312 { 0x00009994, 0x00000000 },
313 { 0x00009998, 0x00000000 },
314 { 0x0000999c, 0x00000000 },
315 { 0x000099a0, 0x00000000 },
316 { 0x000099a4, 0x00000001 },
317 { 0x000099a8, 0x001fff00 },
318 { 0x000099ac, 0x00000000 },
319 { 0x000099b0, 0x03051000 },
320 { 0x000099dc, 0x00000000 },
321 { 0x000099e0, 0x00000200 },
322 { 0x000099e4, 0xaaaaaaaa },
323 { 0x000099e8, 0x3c466478 },
324 { 0x000099ec, 0x000000aa },
325 { 0x000099fc, 0x00001042 },
326 { 0x00009b00, 0x00000000 },
327 { 0x00009b04, 0x00000001 },
328 { 0x00009b08, 0x00000002 },
329 { 0x00009b0c, 0x00000003 },
330 { 0x00009b10, 0x00000004 },
331 { 0x00009b14, 0x00000005 },
332 { 0x00009b18, 0x00000008 },
333 { 0x00009b1c, 0x00000009 },
334 { 0x00009b20, 0x0000000a },
335 { 0x00009b24, 0x0000000b },
336 { 0x00009b28, 0x0000000c },
337 { 0x00009b2c, 0x0000000d },
338 { 0x00009b30, 0x00000010 },
339 { 0x00009b34, 0x00000011 },
340 { 0x00009b38, 0x00000012 },
341 { 0x00009b3c, 0x00000013 },
342 { 0x00009b40, 0x00000014 },
343 { 0x00009b44, 0x00000015 },
344 { 0x00009b48, 0x00000018 },
345 { 0x00009b4c, 0x00000019 },
346 { 0x00009b50, 0x0000001a },
347 { 0x00009b54, 0x0000001b },
348 { 0x00009b58, 0x0000001c },
349 { 0x00009b5c, 0x0000001d },
350 { 0x00009b60, 0x00000020 },
351 { 0x00009b64, 0x00000021 },
352 { 0x00009b68, 0x00000022 },
353 { 0x00009b6c, 0x00000023 },
354 { 0x00009b70, 0x00000024 },
355 { 0x00009b74, 0x00000025 },
356 { 0x00009b78, 0x00000028 },
357 { 0x00009b7c, 0x00000029 },
358 { 0x00009b80, 0x0000002a },
359 { 0x00009b84, 0x0000002b },
360 { 0x00009b88, 0x0000002c },
361 { 0x00009b8c, 0x0000002d },
362 { 0x00009b90, 0x00000030 },
363 { 0x00009b94, 0x00000031 },
364 { 0x00009b98, 0x00000032 },
365 { 0x00009b9c, 0x00000033 },
366 { 0x00009ba0, 0x00000034 },
367 { 0x00009ba4, 0x00000035 },
368 { 0x00009ba8, 0x00000035 },
369 { 0x00009bac, 0x00000035 },
370 { 0x00009bb0, 0x00000035 },
371 { 0x00009bb4, 0x00000035 },
372 { 0x00009bb8, 0x00000035 },
373 { 0x00009bbc, 0x00000035 },
374 { 0x00009bc0, 0x00000035 },
375 { 0x00009bc4, 0x00000035 },
376 { 0x00009bc8, 0x00000035 },
377 { 0x00009bcc, 0x00000035 },
378 { 0x00009bd0, 0x00000035 },
379 { 0x00009bd4, 0x00000035 },
380 { 0x00009bd8, 0x00000035 },
381 { 0x00009bdc, 0x00000035 },
382 { 0x00009be0, 0x00000035 },
383 { 0x00009be4, 0x00000035 },
384 { 0x00009be8, 0x00000035 },
385 { 0x00009bec, 0x00000035 },
386 { 0x00009bf0, 0x00000035 },
387 { 0x00009bf4, 0x00000035 },
388 { 0x00009bf8, 0x00000010 },
389 { 0x00009bfc, 0x0000001a },
390 { 0x0000a210, 0x40806333 },
391 { 0x0000a214, 0x00106c10 },
392 { 0x0000a218, 0x009c4060 },
393 { 0x0000a220, 0x018830c6 },
394 { 0x0000a224, 0x00000400 },
395 { 0x0000a228, 0x00000bb5 },
396 { 0x0000a22c, 0x00000011 },
397 { 0x0000a234, 0x20202020 },
398 { 0x0000a238, 0x20202020 },
399 { 0x0000a23c, 0x13c889af },
400 { 0x0000a240, 0x38490a20 },
401 { 0x0000a244, 0x00007bb6 },
402 { 0x0000a248, 0x0fff3ffc },
403 { 0x0000a24c, 0x00000001 },
404 { 0x0000a250, 0x0000a000 },
405 { 0x0000a254, 0x00000000 },
406 { 0x0000a258, 0x0cc75380 },
407 { 0x0000a25c, 0x0f0f0f01 },
408 { 0x0000a260, 0xdfa91f01 },
409 { 0x0000a268, 0x00000000 },
410 { 0x0000a26c, 0x0e79e5c6 },
411 { 0x0000b26c, 0x0e79e5c6 },
412 { 0x0000c26c, 0x0e79e5c6 },
413 { 0x0000d270, 0x00820820 },
414 { 0x0000a278, 0x1ce739ce },
415 { 0x0000a27c, 0x051701ce },
416 { 0x0000a338, 0x00000000 },
417 { 0x0000a33c, 0x00000000 },
418 { 0x0000a340, 0x00000000 },
419 { 0x0000a344, 0x00000000 },
420 { 0x0000a348, 0x3fffffff },
421 { 0x0000a34c, 0x3fffffff },
422 { 0x0000a350, 0x3fffffff },
423 { 0x0000a354, 0x0003ffff },
424 { 0x0000a358, 0x79a8aa1f },
425 { 0x0000d35c, 0x07ffffef },
426 { 0x0000d360, 0x0fffffe7 },
427 { 0x0000d364, 0x17ffffe5 },
428 { 0x0000d368, 0x1fffffe4 },
429 { 0x0000d36c, 0x37ffffe3 },
430 { 0x0000d370, 0x3fffffe3 },
431 { 0x0000d374, 0x57ffffe3 },
432 { 0x0000d378, 0x5fffffe2 },
433 { 0x0000d37c, 0x7fffffe2 },
434 { 0x0000d380, 0x7f3c7bba },
435 { 0x0000d384, 0xf3307ff0 },
436 { 0x0000a388, 0x08000000 },
437 { 0x0000a38c, 0x20202020 },
438 { 0x0000a390, 0x20202020 },
439 { 0x0000a394, 0x1ce739ce },
440 { 0x0000a398, 0x000001ce },
441 { 0x0000a39c, 0x00000001 },
442 { 0x0000a3a0, 0x00000000 },
443 { 0x0000a3a4, 0x00000000 },
444 { 0x0000a3a8, 0x00000000 },
445 { 0x0000a3ac, 0x00000000 },
446 { 0x0000a3b0, 0x00000000 },
447 { 0x0000a3b4, 0x00000000 },
448 { 0x0000a3b8, 0x00000000 },
449 { 0x0000a3bc, 0x00000000 },
450 { 0x0000a3c0, 0x00000000 },
451 { 0x0000a3c4, 0x00000000 },
452 { 0x0000a3c8, 0x00000246 },
453 { 0x0000a3cc, 0x20202020 },
454 { 0x0000a3d0, 0x20202020 },
455 { 0x0000a3d4, 0x20202020 },
456 { 0x0000a3dc, 0x1ce739ce },
457 { 0x0000a3e0, 0x000001ce },
458};
459
460static const u32 ar5416Bank0[][2] = {
461 { 0x000098b0, 0x1e5795e5 },
462 { 0x000098e0, 0x02008020 },
463};
464
465static const u32 ar5416BB_RfGain[][3] = {
466 { 0x00009a00, 0x00000000, 0x00000000 },
467 { 0x00009a04, 0x00000040, 0x00000040 },
468 { 0x00009a08, 0x00000080, 0x00000080 },
469 { 0x00009a0c, 0x000001a1, 0x00000141 },
470 { 0x00009a10, 0x000001e1, 0x00000181 },
471 { 0x00009a14, 0x00000021, 0x000001c1 },
472 { 0x00009a18, 0x00000061, 0x00000001 },
473 { 0x00009a1c, 0x00000168, 0x00000041 },
474 { 0x00009a20, 0x000001a8, 0x000001a8 },
475 { 0x00009a24, 0x000001e8, 0x000001e8 },
476 { 0x00009a28, 0x00000028, 0x00000028 },
477 { 0x00009a2c, 0x00000068, 0x00000068 },
478 { 0x00009a30, 0x00000189, 0x000000a8 },
479 { 0x00009a34, 0x000001c9, 0x00000169 },
480 { 0x00009a38, 0x00000009, 0x000001a9 },
481 { 0x00009a3c, 0x00000049, 0x000001e9 },
482 { 0x00009a40, 0x00000089, 0x00000029 },
483 { 0x00009a44, 0x00000170, 0x00000069 },
484 { 0x00009a48, 0x000001b0, 0x00000190 },
485 { 0x00009a4c, 0x000001f0, 0x000001d0 },
486 { 0x00009a50, 0x00000030, 0x00000010 },
487 { 0x00009a54, 0x00000070, 0x00000050 },
488 { 0x00009a58, 0x00000191, 0x00000090 },
489 { 0x00009a5c, 0x000001d1, 0x00000151 },
490 { 0x00009a60, 0x00000011, 0x00000191 },
491 { 0x00009a64, 0x00000051, 0x000001d1 },
492 { 0x00009a68, 0x00000091, 0x00000011 },
493 { 0x00009a6c, 0x000001b8, 0x00000051 },
494 { 0x00009a70, 0x000001f8, 0x00000198 },
495 { 0x00009a74, 0x00000038, 0x000001d8 },
496 { 0x00009a78, 0x00000078, 0x00000018 },
497 { 0x00009a7c, 0x00000199, 0x00000058 },
498 { 0x00009a80, 0x000001d9, 0x00000098 },
499 { 0x00009a84, 0x00000019, 0x00000159 },
500 { 0x00009a88, 0x00000059, 0x00000199 },
501 { 0x00009a8c, 0x00000099, 0x000001d9 },
502 { 0x00009a90, 0x000000d9, 0x00000019 },
503 { 0x00009a94, 0x000000f9, 0x00000059 },
504 { 0x00009a98, 0x000000f9, 0x00000099 },
505 { 0x00009a9c, 0x000000f9, 0x000000d9 },
506 { 0x00009aa0, 0x000000f9, 0x000000f9 },
507 { 0x00009aa4, 0x000000f9, 0x000000f9 },
508 { 0x00009aa8, 0x000000f9, 0x000000f9 },
509 { 0x00009aac, 0x000000f9, 0x000000f9 },
510 { 0x00009ab0, 0x000000f9, 0x000000f9 },
511 { 0x00009ab4, 0x000000f9, 0x000000f9 },
512 { 0x00009ab8, 0x000000f9, 0x000000f9 },
513 { 0x00009abc, 0x000000f9, 0x000000f9 },
514 { 0x00009ac0, 0x000000f9, 0x000000f9 },
515 { 0x00009ac4, 0x000000f9, 0x000000f9 },
516 { 0x00009ac8, 0x000000f9, 0x000000f9 },
517 { 0x00009acc, 0x000000f9, 0x000000f9 },
518 { 0x00009ad0, 0x000000f9, 0x000000f9 },
519 { 0x00009ad4, 0x000000f9, 0x000000f9 },
520 { 0x00009ad8, 0x000000f9, 0x000000f9 },
521 { 0x00009adc, 0x000000f9, 0x000000f9 },
522 { 0x00009ae0, 0x000000f9, 0x000000f9 },
523 { 0x00009ae4, 0x000000f9, 0x000000f9 },
524 { 0x00009ae8, 0x000000f9, 0x000000f9 },
525 { 0x00009aec, 0x000000f9, 0x000000f9 },
526 { 0x00009af0, 0x000000f9, 0x000000f9 },
527 { 0x00009af4, 0x000000f9, 0x000000f9 },
528 { 0x00009af8, 0x000000f9, 0x000000f9 },
529 { 0x00009afc, 0x000000f9, 0x000000f9 },
530};
531
532static const u32 ar5416Bank1[][2] = {
533 { 0x000098b0, 0x02108421 },
534 { 0x000098ec, 0x00000008 },
535};
536
537static const u32 ar5416Bank2[][2] = {
538 { 0x000098b0, 0x0e73ff17 },
539 { 0x000098e0, 0x00000420 },
540};
541
542static const u32 ar5416Bank3[][3] = {
543 { 0x000098f0, 0x01400018, 0x01c00018 },
544};
545
546static const u32 ar5416Bank6[][3] = {
547
548 { 0x0000989c, 0x00000000, 0x00000000 },
549 { 0x0000989c, 0x00000000, 0x00000000 },
550 { 0x0000989c, 0x00000000, 0x00000000 },
551 { 0x0000989c, 0x00e00000, 0x00e00000 },
552 { 0x0000989c, 0x005e0000, 0x005e0000 },
553 { 0x0000989c, 0x00120000, 0x00120000 },
554 { 0x0000989c, 0x00620000, 0x00620000 },
555 { 0x0000989c, 0x00020000, 0x00020000 },
556 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
557 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
558 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
559 { 0x0000989c, 0x40ff0000, 0x40ff0000 },
560 { 0x0000989c, 0x005f0000, 0x005f0000 },
561 { 0x0000989c, 0x00870000, 0x00870000 },
562 { 0x0000989c, 0x00f90000, 0x00f90000 },
563 { 0x0000989c, 0x007b0000, 0x007b0000 },
564 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
565 { 0x0000989c, 0x00f50000, 0x00f50000 },
566 { 0x0000989c, 0x00dc0000, 0x00dc0000 },
567 { 0x0000989c, 0x00110000, 0x00110000 },
568 { 0x0000989c, 0x006100a8, 0x006100a8 },
569 { 0x0000989c, 0x004210a2, 0x004210a2 },
570 { 0x0000989c, 0x0014008f, 0x0014008f },
571 { 0x0000989c, 0x00c40003, 0x00c40003 },
572 { 0x0000989c, 0x003000f2, 0x003000f2 },
573 { 0x0000989c, 0x00440016, 0x00440016 },
574 { 0x0000989c, 0x00410040, 0x00410040 },
575 { 0x0000989c, 0x0001805e, 0x0001805e },
576 { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
577 { 0x0000989c, 0x000000f1, 0x000000f1 },
578 { 0x0000989c, 0x00002081, 0x00002081 },
579 { 0x0000989c, 0x000000d4, 0x000000d4 },
580 { 0x000098d0, 0x0000000f, 0x0010000f },
581};
582
583static const u32 ar5416Bank6TPC[][3] = {
584 { 0x0000989c, 0x00000000, 0x00000000 },
585 { 0x0000989c, 0x00000000, 0x00000000 },
586 { 0x0000989c, 0x00000000, 0x00000000 },
587 { 0x0000989c, 0x00e00000, 0x00e00000 },
588 { 0x0000989c, 0x005e0000, 0x005e0000 },
589 { 0x0000989c, 0x00120000, 0x00120000 },
590 { 0x0000989c, 0x00620000, 0x00620000 },
591 { 0x0000989c, 0x00020000, 0x00020000 },
592 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
593 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
594 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
595 { 0x0000989c, 0x40ff0000, 0x40ff0000 },
596 { 0x0000989c, 0x005f0000, 0x005f0000 },
597 { 0x0000989c, 0x00870000, 0x00870000 },
598 { 0x0000989c, 0x00f90000, 0x00f90000 },
599 { 0x0000989c, 0x007b0000, 0x007b0000 },
600 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
601 { 0x0000989c, 0x00f50000, 0x00f50000 },
602 { 0x0000989c, 0x00dc0000, 0x00dc0000 },
603 { 0x0000989c, 0x00110000, 0x00110000 },
604 { 0x0000989c, 0x006100a8, 0x006100a8 },
605 { 0x0000989c, 0x00423022, 0x00423022 },
606 { 0x0000989c, 0x201400df, 0x201400df },
607 { 0x0000989c, 0x00c40002, 0x00c40002 },
608 { 0x0000989c, 0x003000f2, 0x003000f2 },
609 { 0x0000989c, 0x00440016, 0x00440016 },
610 { 0x0000989c, 0x00410040, 0x00410040 },
611 { 0x0000989c, 0x0001805e, 0x0001805e },
612 { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
613 { 0x0000989c, 0x000000e1, 0x000000e1 },
614 { 0x0000989c, 0x00007081, 0x00007081 },
615 { 0x0000989c, 0x000000d4, 0x000000d4 },
616 { 0x000098d0, 0x0000000f, 0x0010000f },
617};
618
619static const u32 ar5416Bank7[][2] = {
620 { 0x0000989c, 0x00000500 },
621 { 0x0000989c, 0x00000800 },
622 { 0x000098cc, 0x0000000e },
623};
624
625static const u32 ar5416Addac[][2] = {
626 {0x0000989c, 0x00000000 },
627 {0x0000989c, 0x00000003 },
628 {0x0000989c, 0x00000000 },
629 {0x0000989c, 0x0000000c },
630 {0x0000989c, 0x00000000 },
631 {0x0000989c, 0x00000030 },
632 {0x0000989c, 0x00000000 },
633 {0x0000989c, 0x00000000 },
634 {0x0000989c, 0x00000000 },
635 {0x0000989c, 0x00000000 },
636 {0x0000989c, 0x00000000 },
637 {0x0000989c, 0x00000000 },
638 {0x0000989c, 0x00000000 },
639 {0x0000989c, 0x00000000 },
640 {0x0000989c, 0x00000000 },
641 {0x0000989c, 0x00000000 },
642 {0x0000989c, 0x00000000 },
643 {0x0000989c, 0x00000000 },
644 {0x0000989c, 0x00000060 },
645 {0x0000989c, 0x00000000 },
646 {0x0000989c, 0x00000000 },
647 {0x0000989c, 0x00000000 },
648 {0x0000989c, 0x00000000 },
649 {0x0000989c, 0x00000000 },
650 {0x0000989c, 0x00000000 },
651 {0x0000989c, 0x00000000 },
652 {0x0000989c, 0x00000000 },
653 {0x0000989c, 0x00000000 },
654 {0x0000989c, 0x00000000 },
655 {0x0000989c, 0x00000000 },
656 {0x0000989c, 0x00000000 },
657 {0x0000989c, 0x00000058 },
658 {0x0000989c, 0x00000000 },
659 {0x0000989c, 0x00000000 },
660 {0x0000989c, 0x00000000 },
661 {0x0000989c, 0x00000000 },
662 {0x000098cc, 0x00000000 },
663};
664
665static const u32 ar5416Modes_9100[][6] = {
666 { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
667 { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
668 { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
669 { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },
670 { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
671 { 0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf },
672 { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
673 { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
674 { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
675 { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
676 { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
677 { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
678 { 0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0, 0x037216a0 },
679 { 0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
680 { 0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
681 { 0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
682 { 0x00009850, 0x6d48b4e2, 0x6d48b4e2, 0x6d48b0e2, 0x6d48b0e2, 0x6d48b0e2 },
683 { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec86d2e, 0x7ec84d2e, 0x7ec82d2e },
684 { 0x0000985c, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e },
685 { 0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20, 0x00048d18 },
686 { 0x0000c864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
687 { 0x00009868, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0 },
688 { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 },
689 { 0x00009914, 0x000007d0, 0x000007d0, 0x00000898, 0x00000898, 0x000007d0 },
690 { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
691 { 0x00009924, 0xd00a8a07, 0xd00a8a07, 0xd00a8a11, 0xd00a8a0d, 0xd00a8a0d },
692 { 0x00009940, 0x00754604, 0x00754604, 0xfff81204, 0xfff81204, 0xfff81204 },
693 { 0x00009944, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020 },
694 { 0x00009954, 0x5f3ca3de, 0x5f3ca3de, 0xe250a51e, 0xe250a51e, 0xe250a51e },
695 { 0x00009958, 0x2108ecff, 0x2108ecff, 0x3388ffff, 0x3388ffff, 0x3388ffff },
696#ifdef TB243
697 { 0x00009960, 0x00000900, 0x00000900, 0x00009b40, 0x00009b40, 0x00012d80 },
698 { 0x0000a960, 0x00000900, 0x00000900, 0x00009b40, 0x00009b40, 0x00012d80 },
699 { 0x0000b960, 0x00000900, 0x00000900, 0x00009b40, 0x00009b40, 0x00012d80 },
700 { 0x00009964, 0x00000000, 0x00000000, 0x00002210, 0x00002210, 0x00001120 },
701#else
702 { 0x00009960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0 },
703 { 0x0000a960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0 },
704 { 0x0000b960, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0, 0x0001bfc0 },
705 { 0x00009964, 0x00001120, 0x00001120, 0x00001120, 0x00001120, 0x00001120 },
706#endif
707 { 0x0000c9bc, 0x001a0600, 0x001a0600, 0x001a1000, 0x001a0c00, 0x001a0c00 },
708 { 0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, 0x038919be },
709 { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
710 { 0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329 },
711 { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
712 { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
713 { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
714 { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
715 { 0x0000a204, 0x00000880, 0x00000880, 0x00000880, 0x00000880, 0x00000880 },
716 { 0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788, 0xd03e4788 },
717 { 0x0000a20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
718 { 0x0000b20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
719 { 0x0000c20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
720 { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
721 { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
722 { 0x0000a274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa, 0x0a1a7caa },
723 { 0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 },
724 { 0x0000a304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402, 0x2e032402 },
725 { 0x0000a308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06, 0x4a0a3c06 },
726 { 0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b, 0x621a540b },
727 { 0x0000a310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b, 0x764f6c1b },
728 { 0x0000a314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a, 0x845b7a5a },
729 { 0x0000a318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf, 0x950f8ccf },
730 { 0x0000a31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f, 0xa5cf9b4f },
731 { 0x0000a320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f, 0xbddfaf1f },
732 { 0x0000a324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f, 0xd1ffc93f },
733 { 0x0000a328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000, 0x00000000 },
734 { 0x0000a32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
735 { 0x0000a330, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
736 { 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
737};
738
739static const u32 ar5416Common_9100[][2] = {
740 { 0x0000000c, 0x00000000 },
741 { 0x00000030, 0x00020015 },
742 { 0x00000034, 0x00000005 },
743 { 0x00000040, 0x00000000 },
744 { 0x00000044, 0x00000008 },
745 { 0x00000048, 0x00000008 },
746 { 0x0000004c, 0x00000010 },
747 { 0x00000050, 0x00000000 },
748 { 0x00000054, 0x0000001f },
749 { 0x00000800, 0x00000000 },
750 { 0x00000804, 0x00000000 },
751 { 0x00000808, 0x00000000 },
752 { 0x0000080c, 0x00000000 },
753 { 0x00000810, 0x00000000 },
754 { 0x00000814, 0x00000000 },
755 { 0x00000818, 0x00000000 },
756 { 0x0000081c, 0x00000000 },
757 { 0x00000820, 0x00000000 },
758 { 0x00000824, 0x00000000 },
759 { 0x00001040, 0x002ffc0f },
760 { 0x00001044, 0x002ffc0f },
761 { 0x00001048, 0x002ffc0f },
762 { 0x0000104c, 0x002ffc0f },
763 { 0x00001050, 0x002ffc0f },
764 { 0x00001054, 0x002ffc0f },
765 { 0x00001058, 0x002ffc0f },
766 { 0x0000105c, 0x002ffc0f },
767 { 0x00001060, 0x002ffc0f },
768 { 0x00001064, 0x002ffc0f },
769 { 0x00001230, 0x00000000 },
770 { 0x00001270, 0x00000000 },
771 { 0x00001038, 0x00000000 },
772 { 0x00001078, 0x00000000 },
773 { 0x000010b8, 0x00000000 },
774 { 0x000010f8, 0x00000000 },
775 { 0x00001138, 0x00000000 },
776 { 0x00001178, 0x00000000 },
777 { 0x000011b8, 0x00000000 },
778 { 0x000011f8, 0x00000000 },
779 { 0x00001238, 0x00000000 },
780 { 0x00001278, 0x00000000 },
781 { 0x000012b8, 0x00000000 },
782 { 0x000012f8, 0x00000000 },
783 { 0x00001338, 0x00000000 },
784 { 0x00001378, 0x00000000 },
785 { 0x000013b8, 0x00000000 },
786 { 0x000013f8, 0x00000000 },
787 { 0x00001438, 0x00000000 },
788 { 0x00001478, 0x00000000 },
789 { 0x000014b8, 0x00000000 },
790 { 0x000014f8, 0x00000000 },
791 { 0x00001538, 0x00000000 },
792 { 0x00001578, 0x00000000 },
793 { 0x000015b8, 0x00000000 },
794 { 0x000015f8, 0x00000000 },
795 { 0x00001638, 0x00000000 },
796 { 0x00001678, 0x00000000 },
797 { 0x000016b8, 0x00000000 },
798 { 0x000016f8, 0x00000000 },
799 { 0x00001738, 0x00000000 },
800 { 0x00001778, 0x00000000 },
801 { 0x000017b8, 0x00000000 },
802 { 0x000017f8, 0x00000000 },
803 { 0x0000103c, 0x00000000 },
804 { 0x0000107c, 0x00000000 },
805 { 0x000010bc, 0x00000000 },
806 { 0x000010fc, 0x00000000 },
807 { 0x0000113c, 0x00000000 },
808 { 0x0000117c, 0x00000000 },
809 { 0x000011bc, 0x00000000 },
810 { 0x000011fc, 0x00000000 },
811 { 0x0000123c, 0x00000000 },
812 { 0x0000127c, 0x00000000 },
813 { 0x000012bc, 0x00000000 },
814 { 0x000012fc, 0x00000000 },
815 { 0x0000133c, 0x00000000 },
816 { 0x0000137c, 0x00000000 },
817 { 0x000013bc, 0x00000000 },
818 { 0x000013fc, 0x00000000 },
819 { 0x0000143c, 0x00000000 },
820 { 0x0000147c, 0x00000000 },
821 { 0x00020010, 0x00000003 },
822 { 0x00020038, 0x000004c2 },
823 { 0x00008004, 0x00000000 },
824 { 0x00008008, 0x00000000 },
825 { 0x0000800c, 0x00000000 },
826 { 0x00008018, 0x00000700 },
827 { 0x00008020, 0x00000000 },
828 { 0x00008038, 0x00000000 },
829 { 0x0000803c, 0x00000000 },
830 { 0x00008048, 0x40000000 },
831 { 0x00008054, 0x00004000 },
832 { 0x00008058, 0x00000000 },
833 { 0x0000805c, 0x000fc78f },
834 { 0x00008060, 0x0000000f },
835 { 0x00008064, 0x00000000 },
836 { 0x000080c0, 0x2a82301a },
837 { 0x000080c4, 0x05dc01e0 },
838 { 0x000080c8, 0x1f402710 },
839 { 0x000080cc, 0x01f40000 },
840 { 0x000080d0, 0x00001e00 },
841 { 0x000080d4, 0x00000000 },
842 { 0x000080d8, 0x00400000 },
843 { 0x000080e0, 0xffffffff },
844 { 0x000080e4, 0x0000ffff },
845 { 0x000080e8, 0x003f3f3f },
846 { 0x000080ec, 0x00000000 },
847 { 0x000080f0, 0x00000000 },
848 { 0x000080f4, 0x00000000 },
849 { 0x000080f8, 0x00000000 },
850 { 0x000080fc, 0x00020000 },
851 { 0x00008100, 0x00020000 },
852 { 0x00008104, 0x00000001 },
853 { 0x00008108, 0x00000052 },
854 { 0x0000810c, 0x00000000 },
855 { 0x00008110, 0x00000168 },
856 { 0x00008118, 0x000100aa },
857 { 0x0000811c, 0x00003210 },
858 { 0x00008120, 0x08f04800 },
859 { 0x00008124, 0x00000000 },
860 { 0x00008128, 0x00000000 },
861 { 0x0000812c, 0x00000000 },
862 { 0x00008130, 0x00000000 },
863 { 0x00008134, 0x00000000 },
864 { 0x00008138, 0x00000000 },
865 { 0x0000813c, 0x00000000 },
866 { 0x00008144, 0x00000000 },
867 { 0x00008168, 0x00000000 },
868 { 0x0000816c, 0x00000000 },
869 { 0x00008170, 0x32143320 },
870 { 0x00008174, 0xfaa4fa50 },
871 { 0x00008178, 0x00000100 },
872 { 0x0000817c, 0x00000000 },
873 { 0x000081c4, 0x00000000 },
874 { 0x000081d0, 0x00003210 },
875 { 0x000081ec, 0x00000000 },
876 { 0x000081f0, 0x00000000 },
877 { 0x000081f4, 0x00000000 },
878 { 0x000081f8, 0x00000000 },
879 { 0x000081fc, 0x00000000 },
880 { 0x00008200, 0x00000000 },
881 { 0x00008204, 0x00000000 },
882 { 0x00008208, 0x00000000 },
883 { 0x0000820c, 0x00000000 },
884 { 0x00008210, 0x00000000 },
885 { 0x00008214, 0x00000000 },
886 { 0x00008218, 0x00000000 },
887 { 0x0000821c, 0x00000000 },
888 { 0x00008220, 0x00000000 },
889 { 0x00008224, 0x00000000 },
890 { 0x00008228, 0x00000000 },
891 { 0x0000822c, 0x00000000 },
892 { 0x00008230, 0x00000000 },
893 { 0x00008234, 0x00000000 },
894 { 0x00008238, 0x00000000 },
895 { 0x0000823c, 0x00000000 },
896 { 0x00008240, 0x00100000 },
897 { 0x00008244, 0x0010f400 },
898 { 0x00008248, 0x00000100 },
899 { 0x0000824c, 0x0001e800 },
900 { 0x00008250, 0x00000000 },
901 { 0x00008254, 0x00000000 },
902 { 0x00008258, 0x00000000 },
903 { 0x0000825c, 0x400000ff },
904 { 0x00008260, 0x00080922 },
905 { 0x00008270, 0x00000000 },
906 { 0x00008274, 0x40000000 },
907 { 0x00008278, 0x003e4180 },
908 { 0x0000827c, 0x00000000 },
909 { 0x00008284, 0x0000002c },
910 { 0x00008288, 0x0000002c },
911 { 0x0000828c, 0x00000000 },
912 { 0x00008294, 0x00000000 },
913 { 0x00008298, 0x00000000 },
914 { 0x00008300, 0x00000000 },
915 { 0x00008304, 0x00000000 },
916 { 0x00008308, 0x00000000 },
917 { 0x0000830c, 0x00000000 },
918 { 0x00008310, 0x00000000 },
919 { 0x00008314, 0x00000000 },
920 { 0x00008318, 0x00000000 },
921 { 0x00008328, 0x00000000 },
922 { 0x0000832c, 0x00000007 },
923 { 0x00008330, 0x00000302 },
924 { 0x00008334, 0x00000e00 },
925 { 0x00008338, 0x00000000 },
926 { 0x0000833c, 0x00000000 },
927 { 0x00008340, 0x000107ff },
928 { 0x00009808, 0x00000000 },
929 { 0x0000980c, 0xad848e19 },
930 { 0x00009810, 0x7d14e000 },
931 { 0x00009814, 0x9c0a9f6b },
932 { 0x0000981c, 0x00000000 },
933 { 0x0000982c, 0x0000a000 },
934 { 0x00009830, 0x00000000 },
935 { 0x0000983c, 0x00200400 },
936 { 0x00009840, 0x206a01ae },
937 { 0x0000984c, 0x1284233c },
938 { 0x00009854, 0x00000859 },
939 { 0x00009900, 0x00000000 },
940 { 0x00009904, 0x00000000 },
941 { 0x00009908, 0x00000000 },
942 { 0x0000990c, 0x00000000 },
943 { 0x0000991c, 0x10000fff },
944 { 0x00009920, 0x05100000 },
945 { 0x0000a920, 0x05100000 },
946 { 0x0000b920, 0x05100000 },
947 { 0x00009928, 0x00000001 },
948 { 0x0000992c, 0x00000004 },
949 { 0x00009934, 0x1e1f2022 },
950 { 0x00009938, 0x0a0b0c0d },
951 { 0x0000993c, 0x00000000 },
952 { 0x00009948, 0x9280b212 },
953 { 0x0000994c, 0x00020028 },
954 { 0x0000c95c, 0x004b6a8e },
955 { 0x0000c968, 0x000003ce },
956 { 0x00009970, 0x190fb515 },
957 { 0x00009974, 0x00000000 },
958 { 0x00009978, 0x00000001 },
959 { 0x0000997c, 0x00000000 },
960 { 0x00009980, 0x00000000 },
961 { 0x00009984, 0x00000000 },
962 { 0x00009988, 0x00000000 },
963 { 0x0000998c, 0x00000000 },
964 { 0x00009990, 0x00000000 },
965 { 0x00009994, 0x00000000 },
966 { 0x00009998, 0x00000000 },
967 { 0x0000999c, 0x00000000 },
968 { 0x000099a0, 0x00000000 },
969 { 0x000099a4, 0x00000001 },
970 { 0x000099a8, 0x201fff00 },
971 { 0x000099ac, 0x006f0000 },
972 { 0x000099b0, 0x03051000 },
973 { 0x000099dc, 0x00000000 },
974 { 0x000099e0, 0x00000200 },
975 { 0x000099e4, 0xaaaaaaaa },
976 { 0x000099e8, 0x3c466478 },
977 { 0x000099ec, 0x0cc80caa },
978 { 0x000099fc, 0x00001042 },
979 { 0x00009b00, 0x00000000 },
980 { 0x00009b04, 0x00000001 },
981 { 0x00009b08, 0x00000002 },
982 { 0x00009b0c, 0x00000003 },
983 { 0x00009b10, 0x00000004 },
984 { 0x00009b14, 0x00000005 },
985 { 0x00009b18, 0x00000008 },
986 { 0x00009b1c, 0x00000009 },
987 { 0x00009b20, 0x0000000a },
988 { 0x00009b24, 0x0000000b },
989 { 0x00009b28, 0x0000000c },
990 { 0x00009b2c, 0x0000000d },
991 { 0x00009b30, 0x00000010 },
992 { 0x00009b34, 0x00000011 },
993 { 0x00009b38, 0x00000012 },
994 { 0x00009b3c, 0x00000013 },
995 { 0x00009b40, 0x00000014 },
996 { 0x00009b44, 0x00000015 },
997 { 0x00009b48, 0x00000018 },
998 { 0x00009b4c, 0x00000019 },
999 { 0x00009b50, 0x0000001a },
1000 { 0x00009b54, 0x0000001b },
1001 { 0x00009b58, 0x0000001c },
1002 { 0x00009b5c, 0x0000001d },
1003 { 0x00009b60, 0x00000020 },
1004 { 0x00009b64, 0x00000021 },
1005 { 0x00009b68, 0x00000022 },
1006 { 0x00009b6c, 0x00000023 },
1007 { 0x00009b70, 0x00000024 },
1008 { 0x00009b74, 0x00000025 },
1009 { 0x00009b78, 0x00000028 },
1010 { 0x00009b7c, 0x00000029 },
1011 { 0x00009b80, 0x0000002a },
1012 { 0x00009b84, 0x0000002b },
1013 { 0x00009b88, 0x0000002c },
1014 { 0x00009b8c, 0x0000002d },
1015 { 0x00009b90, 0x00000030 },
1016 { 0x00009b94, 0x00000031 },
1017 { 0x00009b98, 0x00000032 },
1018 { 0x00009b9c, 0x00000033 },
1019 { 0x00009ba0, 0x00000034 },
1020 { 0x00009ba4, 0x00000035 },
1021 { 0x00009ba8, 0x00000035 },
1022 { 0x00009bac, 0x00000035 },
1023 { 0x00009bb0, 0x00000035 },
1024 { 0x00009bb4, 0x00000035 },
1025 { 0x00009bb8, 0x00000035 },
1026 { 0x00009bbc, 0x00000035 },
1027 { 0x00009bc0, 0x00000035 },
1028 { 0x00009bc4, 0x00000035 },
1029 { 0x00009bc8, 0x00000035 },
1030 { 0x00009bcc, 0x00000035 },
1031 { 0x00009bd0, 0x00000035 },
1032 { 0x00009bd4, 0x00000035 },
1033 { 0x00009bd8, 0x00000035 },
1034 { 0x00009bdc, 0x00000035 },
1035 { 0x00009be0, 0x00000035 },
1036 { 0x00009be4, 0x00000035 },
1037 { 0x00009be8, 0x00000035 },
1038 { 0x00009bec, 0x00000035 },
1039 { 0x00009bf0, 0x00000035 },
1040 { 0x00009bf4, 0x00000035 },
1041 { 0x00009bf8, 0x00000010 },
1042 { 0x00009bfc, 0x0000001a },
1043 { 0x0000a210, 0x40806333 },
1044 { 0x0000a214, 0x00106c10 },
1045 { 0x0000a218, 0x009c4060 },
1046 { 0x0000a220, 0x018830c6 },
1047 { 0x0000a224, 0x00000400 },
1048 { 0x0000a228, 0x001a0bb5 },
1049 { 0x0000a22c, 0x00000000 },
1050 { 0x0000a234, 0x20202020 },
1051 { 0x0000a238, 0x20202020 },
1052 { 0x0000a23c, 0x13c889ae },
1053 { 0x0000a240, 0x38490a20 },
1054 { 0x0000a244, 0x00007bb6 },
1055 { 0x0000a248, 0x0fff3ffc },
1056 { 0x0000a24c, 0x00000001 },
1057 { 0x0000a250, 0x0000a000 },
1058 { 0x0000a254, 0x00000000 },
1059 { 0x0000a258, 0x0cc75380 },
1060 { 0x0000a25c, 0x0f0f0f01 },
1061 { 0x0000a260, 0xdfa91f01 },
1062 { 0x0000a268, 0x00000001 },
1063 { 0x0000a26c, 0x0ebae9c6 },
1064 { 0x0000b26c, 0x0ebae9c6 },
1065 { 0x0000c26c, 0x0ebae9c6 },
1066 { 0x0000d270, 0x00820820 },
1067 { 0x0000a278, 0x1ce739ce },
1068 { 0x0000a27c, 0x050701ce },
1069 { 0x0000a338, 0x00000000 },
1070 { 0x0000a33c, 0x00000000 },
1071 { 0x0000a340, 0x00000000 },
1072 { 0x0000a344, 0x00000000 },
1073 { 0x0000a348, 0x3fffffff },
1074 { 0x0000a34c, 0x3fffffff },
1075 { 0x0000a350, 0x3fffffff },
1076 { 0x0000a354, 0x0003ffff },
1077 { 0x0000a358, 0x79a8aa33 },
1078 { 0x0000d35c, 0x07ffffef },
1079 { 0x0000d360, 0x0fffffe7 },
1080 { 0x0000d364, 0x17ffffe5 },
1081 { 0x0000d368, 0x1fffffe4 },
1082 { 0x0000d36c, 0x37ffffe3 },
1083 { 0x0000d370, 0x3fffffe3 },
1084 { 0x0000d374, 0x57ffffe3 },
1085 { 0x0000d378, 0x5fffffe2 },
1086 { 0x0000d37c, 0x7fffffe2 },
1087 { 0x0000d380, 0x7f3c7bba },
1088 { 0x0000d384, 0xf3307ff0 },
1089 { 0x0000a388, 0x0c000000 },
1090 { 0x0000a38c, 0x20202020 },
1091 { 0x0000a390, 0x20202020 },
1092 { 0x0000a394, 0x1ce739ce },
1093 { 0x0000a398, 0x000001ce },
1094 { 0x0000a39c, 0x00000001 },
1095 { 0x0000a3a0, 0x00000000 },
1096 { 0x0000a3a4, 0x00000000 },
1097 { 0x0000a3a8, 0x00000000 },
1098 { 0x0000a3ac, 0x00000000 },
1099 { 0x0000a3b0, 0x00000000 },
1100 { 0x0000a3b4, 0x00000000 },
1101 { 0x0000a3b8, 0x00000000 },
1102 { 0x0000a3bc, 0x00000000 },
1103 { 0x0000a3c0, 0x00000000 },
1104 { 0x0000a3c4, 0x00000000 },
1105 { 0x0000a3c8, 0x00000246 },
1106 { 0x0000a3cc, 0x20202020 },
1107 { 0x0000a3d0, 0x20202020 },
1108 { 0x0000a3d4, 0x20202020 },
1109 { 0x0000a3dc, 0x1ce739ce },
1110 { 0x0000a3e0, 0x000001ce },
1111};
1112
1113static const u32 ar5416Bank0_9100[][2] = {
1114 { 0x000098b0, 0x1e5795e5 },
1115 { 0x000098e0, 0x02008020 },
1116};
1117
1118static const u32 ar5416BB_RfGain_9100[][3] = {
1119 { 0x00009a00, 0x00000000, 0x00000000 },
1120 { 0x00009a04, 0x00000040, 0x00000040 },
1121 { 0x00009a08, 0x00000080, 0x00000080 },
1122 { 0x00009a0c, 0x000001a1, 0x00000141 },
1123 { 0x00009a10, 0x000001e1, 0x00000181 },
1124 { 0x00009a14, 0x00000021, 0x000001c1 },
1125 { 0x00009a18, 0x00000061, 0x00000001 },
1126 { 0x00009a1c, 0x00000168, 0x00000041 },
1127 { 0x00009a20, 0x000001a8, 0x000001a8 },
1128 { 0x00009a24, 0x000001e8, 0x000001e8 },
1129 { 0x00009a28, 0x00000028, 0x00000028 },
1130 { 0x00009a2c, 0x00000068, 0x00000068 },
1131 { 0x00009a30, 0x00000189, 0x000000a8 },
1132 { 0x00009a34, 0x000001c9, 0x00000169 },
1133 { 0x00009a38, 0x00000009, 0x000001a9 },
1134 { 0x00009a3c, 0x00000049, 0x000001e9 },
1135 { 0x00009a40, 0x00000089, 0x00000029 },
1136 { 0x00009a44, 0x00000170, 0x00000069 },
1137 { 0x00009a48, 0x000001b0, 0x00000190 },
1138 { 0x00009a4c, 0x000001f0, 0x000001d0 },
1139 { 0x00009a50, 0x00000030, 0x00000010 },
1140 { 0x00009a54, 0x00000070, 0x00000050 },
1141 { 0x00009a58, 0x00000191, 0x00000090 },
1142 { 0x00009a5c, 0x000001d1, 0x00000151 },
1143 { 0x00009a60, 0x00000011, 0x00000191 },
1144 { 0x00009a64, 0x00000051, 0x000001d1 },
1145 { 0x00009a68, 0x00000091, 0x00000011 },
1146 { 0x00009a6c, 0x000001b8, 0x00000051 },
1147 { 0x00009a70, 0x000001f8, 0x00000198 },
1148 { 0x00009a74, 0x00000038, 0x000001d8 },
1149 { 0x00009a78, 0x00000078, 0x00000018 },
1150 { 0x00009a7c, 0x00000199, 0x00000058 },
1151 { 0x00009a80, 0x000001d9, 0x00000098 },
1152 { 0x00009a84, 0x00000019, 0x00000159 },
1153 { 0x00009a88, 0x00000059, 0x00000199 },
1154 { 0x00009a8c, 0x00000099, 0x000001d9 },
1155 { 0x00009a90, 0x000000d9, 0x00000019 },
1156 { 0x00009a94, 0x000000f9, 0x00000059 },
1157 { 0x00009a98, 0x000000f9, 0x00000099 },
1158 { 0x00009a9c, 0x000000f9, 0x000000d9 },
1159 { 0x00009aa0, 0x000000f9, 0x000000f9 },
1160 { 0x00009aa4, 0x000000f9, 0x000000f9 },
1161 { 0x00009aa8, 0x000000f9, 0x000000f9 },
1162 { 0x00009aac, 0x000000f9, 0x000000f9 },
1163 { 0x00009ab0, 0x000000f9, 0x000000f9 },
1164 { 0x00009ab4, 0x000000f9, 0x000000f9 },
1165 { 0x00009ab8, 0x000000f9, 0x000000f9 },
1166 { 0x00009abc, 0x000000f9, 0x000000f9 },
1167 { 0x00009ac0, 0x000000f9, 0x000000f9 },
1168 { 0x00009ac4, 0x000000f9, 0x000000f9 },
1169 { 0x00009ac8, 0x000000f9, 0x000000f9 },
1170 { 0x00009acc, 0x000000f9, 0x000000f9 },
1171 { 0x00009ad0, 0x000000f9, 0x000000f9 },
1172 { 0x00009ad4, 0x000000f9, 0x000000f9 },
1173 { 0x00009ad8, 0x000000f9, 0x000000f9 },
1174 { 0x00009adc, 0x000000f9, 0x000000f9 },
1175 { 0x00009ae0, 0x000000f9, 0x000000f9 },
1176 { 0x00009ae4, 0x000000f9, 0x000000f9 },
1177 { 0x00009ae8, 0x000000f9, 0x000000f9 },
1178 { 0x00009aec, 0x000000f9, 0x000000f9 },
1179 { 0x00009af0, 0x000000f9, 0x000000f9 },
1180 { 0x00009af4, 0x000000f9, 0x000000f9 },
1181 { 0x00009af8, 0x000000f9, 0x000000f9 },
1182 { 0x00009afc, 0x000000f9, 0x000000f9 },
1183};
1184
1185static const u32 ar5416Bank1_9100[][2] = {
1186 { 0x000098b0, 0x02108421},
1187 { 0x000098ec, 0x00000008},
1188};
1189
1190static const u32 ar5416Bank2_9100[][2] = {
1191 { 0x000098b0, 0x0e73ff17},
1192 { 0x000098e0, 0x00000420},
1193};
1194
1195static const u32 ar5416Bank3_9100[][3] = {
1196 { 0x000098f0, 0x01400018, 0x01c00018 },
1197};
1198
1199static const u32 ar5416Bank6_9100[][3] = {
1200
1201 { 0x0000989c, 0x00000000, 0x00000000 },
1202 { 0x0000989c, 0x00000000, 0x00000000 },
1203 { 0x0000989c, 0x00000000, 0x00000000 },
1204 { 0x0000989c, 0x00e00000, 0x00e00000 },
1205 { 0x0000989c, 0x005e0000, 0x005e0000 },
1206 { 0x0000989c, 0x00120000, 0x00120000 },
1207 { 0x0000989c, 0x00620000, 0x00620000 },
1208 { 0x0000989c, 0x00020000, 0x00020000 },
1209 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
1210 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
1211 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
1212 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
1213 { 0x0000989c, 0x005f0000, 0x005f0000 },
1214 { 0x0000989c, 0x00870000, 0x00870000 },
1215 { 0x0000989c, 0x00f90000, 0x00f90000 },
1216 { 0x0000989c, 0x007b0000, 0x007b0000 },
1217 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
1218 { 0x0000989c, 0x00f50000, 0x00f50000 },
1219 { 0x0000989c, 0x00dc0000, 0x00dc0000 },
1220 { 0x0000989c, 0x00110000, 0x00110000 },
1221 { 0x0000989c, 0x006100a8, 0x006100a8 },
1222 { 0x0000989c, 0x004210a2, 0x004210a2 },
1223 { 0x0000989c, 0x0014000f, 0x0014000f },
1224 { 0x0000989c, 0x00c40002, 0x00c40002 },
1225 { 0x0000989c, 0x003000f2, 0x003000f2 },
1226 { 0x0000989c, 0x00440016, 0x00440016 },
1227 { 0x0000989c, 0x00410040, 0x00410040 },
1228 { 0x0000989c, 0x000180d6, 0x000180d6 },
1229 { 0x0000989c, 0x0000c0aa, 0x0000c0aa },
1230 { 0x0000989c, 0x000000b1, 0x000000b1 },
1231 { 0x0000989c, 0x00002000, 0x00002000 },
1232 { 0x0000989c, 0x000000d4, 0x000000d4 },
1233 { 0x000098d0, 0x0000000f, 0x0010000f },
1234};
1235
1236
1237static const u32 ar5416Bank6TPC_9100[][3] = {
1238
1239 { 0x0000989c, 0x00000000, 0x00000000 },
1240 { 0x0000989c, 0x00000000, 0x00000000 },
1241 { 0x0000989c, 0x00000000, 0x00000000 },
1242 { 0x0000989c, 0x00e00000, 0x00e00000 },
1243 { 0x0000989c, 0x005e0000, 0x005e0000 },
1244 { 0x0000989c, 0x00120000, 0x00120000 },
1245 { 0x0000989c, 0x00620000, 0x00620000 },
1246 { 0x0000989c, 0x00020000, 0x00020000 },
1247 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
1248 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
1249 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
1250 { 0x0000989c, 0x40ff0000, 0x40ff0000 },
1251 { 0x0000989c, 0x005f0000, 0x005f0000 },
1252 { 0x0000989c, 0x00870000, 0x00870000 },
1253 { 0x0000989c, 0x00f90000, 0x00f90000 },
1254 { 0x0000989c, 0x007b0000, 0x007b0000 },
1255 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
1256 { 0x0000989c, 0x00f50000, 0x00f50000 },
1257 { 0x0000989c, 0x00dc0000, 0x00dc0000 },
1258 { 0x0000989c, 0x00110000, 0x00110000 },
1259 { 0x0000989c, 0x006100a8, 0x006100a8 },
1260 { 0x0000989c, 0x00423022, 0x00423022 },
1261 { 0x0000989c, 0x2014008f, 0x2014008f },
1262 { 0x0000989c, 0x00c40002, 0x00c40002 },
1263 { 0x0000989c, 0x003000f2, 0x003000f2 },
1264 { 0x0000989c, 0x00440016, 0x00440016 },
1265 { 0x0000989c, 0x00410040, 0x00410040 },
1266 { 0x0000989c, 0x0001805e, 0x0001805e },
1267 { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
1268 { 0x0000989c, 0x000000e1, 0x000000e1 },
1269 { 0x0000989c, 0x00007080, 0x00007080 },
1270 { 0x0000989c, 0x000000d4, 0x000000d4 },
1271 { 0x000098d0, 0x0000000f, 0x0010000f },
1272};
1273
1274static const u32 ar5416Bank7_9100[][2] = {
1275 { 0x0000989c, 0x00000500 },
1276 { 0x0000989c, 0x00000800 },
1277 { 0x000098cc, 0x0000000e },
1278};
1279
1280static const u32 ar5416Addac_9100[][2] = {
1281 {0x0000989c, 0x00000000 },
1282 {0x0000989c, 0x00000000 },
1283 {0x0000989c, 0x00000000 },
1284 {0x0000989c, 0x00000000 },
1285 {0x0000989c, 0x00000000 },
1286 {0x0000989c, 0x00000000 },
1287 {0x0000989c, 0x00000000 },
1288 {0x0000989c, 0x00000010 },
1289 {0x0000989c, 0x00000000 },
1290 {0x0000989c, 0x00000000 },
1291 {0x0000989c, 0x00000000 },
1292 {0x0000989c, 0x00000000 },
1293 {0x0000989c, 0x00000000 },
1294 {0x0000989c, 0x00000000 },
1295 {0x0000989c, 0x00000000 },
1296 {0x0000989c, 0x00000000 },
1297 {0x0000989c, 0x00000000 },
1298 {0x0000989c, 0x00000000 },
1299 {0x0000989c, 0x00000000 },
1300 {0x0000989c, 0x00000000 },
1301 {0x0000989c, 0x00000000 },
1302 {0x0000989c, 0x000000c0 },
1303 {0x0000989c, 0x00000015 },
1304 {0x0000989c, 0x00000000 },
1305 {0x0000989c, 0x00000000 },
1306 {0x0000989c, 0x00000000 },
1307 {0x0000989c, 0x00000000 },
1308 {0x0000989c, 0x00000000 },
1309 {0x0000989c, 0x00000000 },
1310 {0x0000989c, 0x00000000 },
1311 {0x0000989c, 0x00000000 },
1312 {0x000098cc, 0x00000000 },
1313};
1314
1315static const u32 ar5416Modes_9160[][6] = {
1316 { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
1317 { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
1318 { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
1319 { 0x000010f0, 0x0000a000, 0x00014000, 0x00016000, 0x0000b000, 0x00014008 },
1320 { 0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00, 0x06e006e0 },
1321 { 0x0000801c, 0x128d93a7, 0x128d93cf, 0x12e013d7, 0x12e013ab, 0x098813cf },
1322 { 0x00009804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, 0x00000303 },
1323 { 0x00009820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, 0x02020200 },
1324 { 0x00009824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
1325 { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
1326 { 0x00009834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e },
1327 { 0x00009838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 },
1328 { 0x00009844, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0, 0x037216a0 },
1329 { 0x00009848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
1330 { 0x0000a848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
1331 { 0x0000b848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, 0x00197a68 },
1332 { 0x00009850, 0x6c48b4e2, 0x6c48b4e2, 0x6c48b0e2, 0x6c48b0e2, 0x6c48b0e2 },
1333 { 0x00009858, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e, 0x7ec82d2e },
1334 { 0x0000985c, 0x31395d5e, 0x31395d5e, 0x31395d5e, 0x31395d5e, 0x31395d5e },
1335 { 0x00009860, 0x00048d18, 0x00048d18, 0x00048d20, 0x00048d20, 0x00048d18 },
1336 { 0x0000c864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 },
1337 { 0x00009868, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0, 0x409a40d0 },
1338 { 0x0000986c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 },
1339 { 0x00009914, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898, 0x000007d0 },
1340 { 0x00009918, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b, 0x00000016 },
1341 { 0x00009924, 0xd00a8a07, 0xd00a8a07, 0xd00a8a0d, 0xd00a8a0d, 0xd00a8a0d },
1342 { 0x00009944, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020, 0xffb81020 },
1343 { 0x00009960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40 },
1344 { 0x0000a960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40 },
1345 { 0x0000b960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40 },
1346 { 0x00009964, 0x00001120, 0x00001120, 0x00001120, 0x00001120, 0x00001120 },
1347 { 0x0000c968, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce, 0x000003ce },
1348 { 0x0000c9bc, 0x001a0600, 0x001a0600, 0x001a0c00, 0x001a0c00, 0x001a0c00 },
1349 { 0x000099c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, 0x038919be },
1350 { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 },
1351 { 0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329 },
1352 { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 },
1353 { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 },
1354 { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
1355 { 0x000099d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
1356 { 0x0000a204, 0x00000880, 0x00000880, 0x00000880, 0x00000880, 0x00000880 },
1357 { 0x0000a208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788, 0xd03e4788 },
1358 { 0x0000a20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
1359 { 0x0000b20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
1360 { 0x0000c20c, 0x002fc160, 0x002fc160, 0x002ac120, 0x002ac120, 0x002ac120 },
1361 { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a },
1362 { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 },
1363 { 0x0000a274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa, 0x0a1a7caa },
1364 { 0x0000a300, 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 },
1365 { 0x0000a304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402, 0x2e032402 },
1366 { 0x0000a308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06, 0x4a0a3c06 },
1367 { 0x0000a30c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b, 0x621a540b },
1368 { 0x0000a310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b, 0x764f6c1b },
1369 { 0x0000a314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a, 0x845b7a5a },
1370 { 0x0000a318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf, 0x950f8ccf },
1371 { 0x0000a31c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f, 0xa5cf9b4f },
1372 { 0x0000a320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f, 0xbddfaf1f },
1373 { 0x0000a324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f, 0xd1ffc93f },
1374 { 0x0000a328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000, 0x00000000 },
1375 { 0x0000a32c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
1376 { 0x0000a330, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
1377 { 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
1378};
1379 19
1380static const u32 ar5416Common_9160[][2] = {
1381 { 0x0000000c, 0x00000000 },
1382 { 0x00000030, 0x00020015 },
1383 { 0x00000034, 0x00000005 },
1384 { 0x00000040, 0x00000000 },
1385 { 0x00000044, 0x00000008 },
1386 { 0x00000048, 0x00000008 },
1387 { 0x0000004c, 0x00000010 },
1388 { 0x00000050, 0x00000000 },
1389 { 0x00000054, 0x0000001f },
1390 { 0x00000800, 0x00000000 },
1391 { 0x00000804, 0x00000000 },
1392 { 0x00000808, 0x00000000 },
1393 { 0x0000080c, 0x00000000 },
1394 { 0x00000810, 0x00000000 },
1395 { 0x00000814, 0x00000000 },
1396 { 0x00000818, 0x00000000 },
1397 { 0x0000081c, 0x00000000 },
1398 { 0x00000820, 0x00000000 },
1399 { 0x00000824, 0x00000000 },
1400 { 0x00001040, 0x002ffc0f },
1401 { 0x00001044, 0x002ffc0f },
1402 { 0x00001048, 0x002ffc0f },
1403 { 0x0000104c, 0x002ffc0f },
1404 { 0x00001050, 0x002ffc0f },
1405 { 0x00001054, 0x002ffc0f },
1406 { 0x00001058, 0x002ffc0f },
1407 { 0x0000105c, 0x002ffc0f },
1408 { 0x00001060, 0x002ffc0f },
1409 { 0x00001064, 0x002ffc0f },
1410 { 0x00001230, 0x00000000 },
1411 { 0x00001270, 0x00000000 },
1412 { 0x00001038, 0x00000000 },
1413 { 0x00001078, 0x00000000 },
1414 { 0x000010b8, 0x00000000 },
1415 { 0x000010f8, 0x00000000 },
1416 { 0x00001138, 0x00000000 },
1417 { 0x00001178, 0x00000000 },
1418 { 0x000011b8, 0x00000000 },
1419 { 0x000011f8, 0x00000000 },
1420 { 0x00001238, 0x00000000 },
1421 { 0x00001278, 0x00000000 },
1422 { 0x000012b8, 0x00000000 },
1423 { 0x000012f8, 0x00000000 },
1424 { 0x00001338, 0x00000000 },
1425 { 0x00001378, 0x00000000 },
1426 { 0x000013b8, 0x00000000 },
1427 { 0x000013f8, 0x00000000 },
1428 { 0x00001438, 0x00000000 },
1429 { 0x00001478, 0x00000000 },
1430 { 0x000014b8, 0x00000000 },
1431 { 0x000014f8, 0x00000000 },
1432 { 0x00001538, 0x00000000 },
1433 { 0x00001578, 0x00000000 },
1434 { 0x000015b8, 0x00000000 },
1435 { 0x000015f8, 0x00000000 },
1436 { 0x00001638, 0x00000000 },
1437 { 0x00001678, 0x00000000 },
1438 { 0x000016b8, 0x00000000 },
1439 { 0x000016f8, 0x00000000 },
1440 { 0x00001738, 0x00000000 },
1441 { 0x00001778, 0x00000000 },
1442 { 0x000017b8, 0x00000000 },
1443 { 0x000017f8, 0x00000000 },
1444 { 0x0000103c, 0x00000000 },
1445 { 0x0000107c, 0x00000000 },
1446 { 0x000010bc, 0x00000000 },
1447 { 0x000010fc, 0x00000000 },
1448 { 0x0000113c, 0x00000000 },
1449 { 0x0000117c, 0x00000000 },
1450 { 0x000011bc, 0x00000000 },
1451 { 0x000011fc, 0x00000000 },
1452 { 0x0000123c, 0x00000000 },
1453 { 0x0000127c, 0x00000000 },
1454 { 0x000012bc, 0x00000000 },
1455 { 0x000012fc, 0x00000000 },
1456 { 0x0000133c, 0x00000000 },
1457 { 0x0000137c, 0x00000000 },
1458 { 0x000013bc, 0x00000000 },
1459 { 0x000013fc, 0x00000000 },
1460 { 0x0000143c, 0x00000000 },
1461 { 0x0000147c, 0x00000000 },
1462 { 0x00004030, 0x00000002 },
1463 { 0x0000403c, 0x00000002 },
1464 { 0x00007010, 0x00000020 },
1465 { 0x00007038, 0x000004c2 },
1466 { 0x00008004, 0x00000000 },
1467 { 0x00008008, 0x00000000 },
1468 { 0x0000800c, 0x00000000 },
1469 { 0x00008018, 0x00000700 },
1470 { 0x00008020, 0x00000000 },
1471 { 0x00008038, 0x00000000 },
1472 { 0x0000803c, 0x00000000 },
1473 { 0x00008048, 0x40000000 },
1474 { 0x00008054, 0x00000000 },
1475 { 0x00008058, 0x00000000 },
1476 { 0x0000805c, 0x000fc78f },
1477 { 0x00008060, 0x0000000f },
1478 { 0x00008064, 0x00000000 },
1479 { 0x000080c0, 0x2a82301a },
1480 { 0x000080c4, 0x05dc01e0 },
1481 { 0x000080c8, 0x1f402710 },
1482 { 0x000080cc, 0x01f40000 },
1483 { 0x000080d0, 0x00001e00 },
1484 { 0x000080d4, 0x00000000 },
1485 { 0x000080d8, 0x00400000 },
1486 { 0x000080e0, 0xffffffff },
1487 { 0x000080e4, 0x0000ffff },
1488 { 0x000080e8, 0x003f3f3f },
1489 { 0x000080ec, 0x00000000 },
1490 { 0x000080f0, 0x00000000 },
1491 { 0x000080f4, 0x00000000 },
1492 { 0x000080f8, 0x00000000 },
1493 { 0x000080fc, 0x00020000 },
1494 { 0x00008100, 0x00020000 },
1495 { 0x00008104, 0x00000001 },
1496 { 0x00008108, 0x00000052 },
1497 { 0x0000810c, 0x00000000 },
1498 { 0x00008110, 0x00000168 },
1499 { 0x00008118, 0x000100aa },
1500 { 0x0000811c, 0x00003210 },
1501 { 0x00008120, 0x08f04800 },
1502 { 0x00008124, 0x00000000 },
1503 { 0x00008128, 0x00000000 },
1504 { 0x0000812c, 0x00000000 },
1505 { 0x00008130, 0x00000000 },
1506 { 0x00008134, 0x00000000 },
1507 { 0x00008138, 0x00000000 },
1508 { 0x0000813c, 0x00000000 },
1509 { 0x00008144, 0xffffffff },
1510 { 0x00008168, 0x00000000 },
1511 { 0x0000816c, 0x00000000 },
1512 { 0x00008170, 0x32143320 },
1513 { 0x00008174, 0xfaa4fa50 },
1514 { 0x00008178, 0x00000100 },
1515 { 0x0000817c, 0x00000000 },
1516 { 0x000081c4, 0x00000000 },
1517 { 0x000081d0, 0x00003210 },
1518 { 0x000081ec, 0x00000000 },
1519 { 0x000081f0, 0x00000000 },
1520 { 0x000081f4, 0x00000000 },
1521 { 0x000081f8, 0x00000000 },
1522 { 0x000081fc, 0x00000000 },
1523 { 0x00008200, 0x00000000 },
1524 { 0x00008204, 0x00000000 },
1525 { 0x00008208, 0x00000000 },
1526 { 0x0000820c, 0x00000000 },
1527 { 0x00008210, 0x00000000 },
1528 { 0x00008214, 0x00000000 },
1529 { 0x00008218, 0x00000000 },
1530 { 0x0000821c, 0x00000000 },
1531 { 0x00008220, 0x00000000 },
1532 { 0x00008224, 0x00000000 },
1533 { 0x00008228, 0x00000000 },
1534 { 0x0000822c, 0x00000000 },
1535 { 0x00008230, 0x00000000 },
1536 { 0x00008234, 0x00000000 },
1537 { 0x00008238, 0x00000000 },
1538 { 0x0000823c, 0x00000000 },
1539 { 0x00008240, 0x00100000 },
1540 { 0x00008244, 0x0010f400 },
1541 { 0x00008248, 0x00000100 },
1542 { 0x0000824c, 0x0001e800 },
1543 { 0x00008250, 0x00000000 },
1544 { 0x00008254, 0x00000000 },
1545 { 0x00008258, 0x00000000 },
1546 { 0x0000825c, 0x400000ff },
1547 { 0x00008260, 0x00080922 },
1548 { 0x00008270, 0x00000000 },
1549 { 0x00008274, 0x40000000 },
1550 { 0x00008278, 0x003e4180 },
1551 { 0x0000827c, 0x00000000 },
1552 { 0x00008284, 0x0000002c },
1553 { 0x00008288, 0x0000002c },
1554 { 0x0000828c, 0x00000000 },
1555 { 0x00008294, 0x00000000 },
1556 { 0x00008298, 0x00000000 },
1557 { 0x00008300, 0x00000000 },
1558 { 0x00008304, 0x00000000 },
1559 { 0x00008308, 0x00000000 },
1560 { 0x0000830c, 0x00000000 },
1561 { 0x00008310, 0x00000000 },
1562 { 0x00008314, 0x00000000 },
1563 { 0x00008318, 0x00000000 },
1564 { 0x00008328, 0x00000000 },
1565 { 0x0000832c, 0x00000007 },
1566 { 0x00008330, 0x00000302 },
1567 { 0x00008334, 0x00000e00 },
1568 { 0x00008338, 0x00ff0000 },
1569 { 0x0000833c, 0x00000000 },
1570 { 0x00008340, 0x000107ff },
1571 { 0x00009808, 0x00000000 },
1572 { 0x0000980c, 0xad848e19 },
1573 { 0x00009810, 0x7d14e000 },
1574 { 0x00009814, 0x9c0a9f6b },
1575 { 0x0000981c, 0x00000000 },
1576 { 0x0000982c, 0x0000a000 },
1577 { 0x00009830, 0x00000000 },
1578 { 0x0000983c, 0x00200400 },
1579 { 0x00009840, 0x206a01ae },
1580 { 0x0000984c, 0x1284233c },
1581 { 0x00009854, 0x00000859 },
1582 { 0x00009900, 0x00000000 },
1583 { 0x00009904, 0x00000000 },
1584 { 0x00009908, 0x00000000 },
1585 { 0x0000990c, 0x00000000 },
1586 { 0x0000991c, 0x10000fff },
1587 { 0x00009920, 0x05100000 },
1588 { 0x0000a920, 0x05100000 },
1589 { 0x0000b920, 0x05100000 },
1590 { 0x00009928, 0x00000001 },
1591 { 0x0000992c, 0x00000004 },
1592 { 0x00009934, 0x1e1f2022 },
1593 { 0x00009938, 0x0a0b0c0d },
1594 { 0x0000993c, 0x00000000 },
1595 { 0x00009948, 0x9280b212 },
1596 { 0x0000994c, 0x00020028 },
1597 { 0x00009954, 0x5f3ca3de },
1598 { 0x00009958, 0x2108ecff },
1599 { 0x00009940, 0x00750604 },
1600 { 0x0000c95c, 0x004b6a8e },
1601 { 0x00009970, 0x190fb515 },
1602 { 0x00009974, 0x00000000 },
1603 { 0x00009978, 0x00000001 },
1604 { 0x0000997c, 0x00000000 },
1605 { 0x00009980, 0x00000000 },
1606 { 0x00009984, 0x00000000 },
1607 { 0x00009988, 0x00000000 },
1608 { 0x0000998c, 0x00000000 },
1609 { 0x00009990, 0x00000000 },
1610 { 0x00009994, 0x00000000 },
1611 { 0x00009998, 0x00000000 },
1612 { 0x0000999c, 0x00000000 },
1613 { 0x000099a0, 0x00000000 },
1614 { 0x000099a4, 0x00000001 },
1615 { 0x000099a8, 0x201fff00 },
1616 { 0x000099ac, 0x006f0000 },
1617 { 0x000099b0, 0x03051000 },
1618 { 0x000099dc, 0x00000000 },
1619 { 0x000099e0, 0x00000200 },
1620 { 0x000099e4, 0xaaaaaaaa },
1621 { 0x000099e8, 0x3c466478 },
1622 { 0x000099ec, 0x0cc80caa },
1623 { 0x000099fc, 0x00001042 },
1624 { 0x00009b00, 0x00000000 },
1625 { 0x00009b04, 0x00000001 },
1626 { 0x00009b08, 0x00000002 },
1627 { 0x00009b0c, 0x00000003 },
1628 { 0x00009b10, 0x00000004 },
1629 { 0x00009b14, 0x00000005 },
1630 { 0x00009b18, 0x00000008 },
1631 { 0x00009b1c, 0x00000009 },
1632 { 0x00009b20, 0x0000000a },
1633 { 0x00009b24, 0x0000000b },
1634 { 0x00009b28, 0x0000000c },
1635 { 0x00009b2c, 0x0000000d },
1636 { 0x00009b30, 0x00000010 },
1637 { 0x00009b34, 0x00000011 },
1638 { 0x00009b38, 0x00000012 },
1639 { 0x00009b3c, 0x00000013 },
1640 { 0x00009b40, 0x00000014 },
1641 { 0x00009b44, 0x00000015 },
1642 { 0x00009b48, 0x00000018 },
1643 { 0x00009b4c, 0x00000019 },
1644 { 0x00009b50, 0x0000001a },
1645 { 0x00009b54, 0x0000001b },
1646 { 0x00009b58, 0x0000001c },
1647 { 0x00009b5c, 0x0000001d },
1648 { 0x00009b60, 0x00000020 },
1649 { 0x00009b64, 0x00000021 },
1650 { 0x00009b68, 0x00000022 },
1651 { 0x00009b6c, 0x00000023 },
1652 { 0x00009b70, 0x00000024 },
1653 { 0x00009b74, 0x00000025 },
1654 { 0x00009b78, 0x00000028 },
1655 { 0x00009b7c, 0x00000029 },
1656 { 0x00009b80, 0x0000002a },
1657 { 0x00009b84, 0x0000002b },
1658 { 0x00009b88, 0x0000002c },
1659 { 0x00009b8c, 0x0000002d },
1660 { 0x00009b90, 0x00000030 },
1661 { 0x00009b94, 0x00000031 },
1662 { 0x00009b98, 0x00000032 },
1663 { 0x00009b9c, 0x00000033 },
1664 { 0x00009ba0, 0x00000034 },
1665 { 0x00009ba4, 0x00000035 },
1666 { 0x00009ba8, 0x00000035 },
1667 { 0x00009bac, 0x00000035 },
1668 { 0x00009bb0, 0x00000035 },
1669 { 0x00009bb4, 0x00000035 },
1670 { 0x00009bb8, 0x00000035 },
1671 { 0x00009bbc, 0x00000035 },
1672 { 0x00009bc0, 0x00000035 },
1673 { 0x00009bc4, 0x00000035 },
1674 { 0x00009bc8, 0x00000035 },
1675 { 0x00009bcc, 0x00000035 },
1676 { 0x00009bd0, 0x00000035 },
1677 { 0x00009bd4, 0x00000035 },
1678 { 0x00009bd8, 0x00000035 },
1679 { 0x00009bdc, 0x00000035 },
1680 { 0x00009be0, 0x00000035 },
1681 { 0x00009be4, 0x00000035 },
1682 { 0x00009be8, 0x00000035 },
1683 { 0x00009bec, 0x00000035 },
1684 { 0x00009bf0, 0x00000035 },
1685 { 0x00009bf4, 0x00000035 },
1686 { 0x00009bf8, 0x00000010 },
1687 { 0x00009bfc, 0x0000001a },
1688 { 0x0000a210, 0x40806333 },
1689 { 0x0000a214, 0x00106c10 },
1690 { 0x0000a218, 0x009c4060 },
1691 { 0x0000a220, 0x018830c6 },
1692 { 0x0000a224, 0x00000400 },
1693 { 0x0000a228, 0x001a0bb5 },
1694 { 0x0000a22c, 0x00000000 },
1695 { 0x0000a234, 0x20202020 },
1696 { 0x0000a238, 0x20202020 },
1697 { 0x0000a23c, 0x13c889af },
1698 { 0x0000a240, 0x38490a20 },
1699 { 0x0000a244, 0x00007bb6 },
1700 { 0x0000a248, 0x0fff3ffc },
1701 { 0x0000a24c, 0x00000001 },
1702 { 0x0000a250, 0x0000e000 },
1703 { 0x0000a254, 0x00000000 },
1704 { 0x0000a258, 0x0cc75380 },
1705 { 0x0000a25c, 0x0f0f0f01 },
1706 { 0x0000a260, 0xdfa91f01 },
1707 { 0x0000a268, 0x00000001 },
1708 { 0x0000a26c, 0x0ebae9c6 },
1709 { 0x0000b26c, 0x0ebae9c6 },
1710 { 0x0000c26c, 0x0ebae9c6 },
1711 { 0x0000d270, 0x00820820 },
1712 { 0x0000a278, 0x1ce739ce },
1713 { 0x0000a27c, 0x050701ce },
1714 { 0x0000a338, 0x00000000 },
1715 { 0x0000a33c, 0x00000000 },
1716 { 0x0000a340, 0x00000000 },
1717 { 0x0000a344, 0x00000000 },
1718 { 0x0000a348, 0x3fffffff },
1719 { 0x0000a34c, 0x3fffffff },
1720 { 0x0000a350, 0x3fffffff },
1721 { 0x0000a354, 0x0003ffff },
1722 { 0x0000a358, 0x79bfaa03 },
1723 { 0x0000d35c, 0x07ffffef },
1724 { 0x0000d360, 0x0fffffe7 },
1725 { 0x0000d364, 0x17ffffe5 },
1726 { 0x0000d368, 0x1fffffe4 },
1727 { 0x0000d36c, 0x37ffffe3 },
1728 { 0x0000d370, 0x3fffffe3 },
1729 { 0x0000d374, 0x57ffffe3 },
1730 { 0x0000d378, 0x5fffffe2 },
1731 { 0x0000d37c, 0x7fffffe2 },
1732 { 0x0000d380, 0x7f3c7bba },
1733 { 0x0000d384, 0xf3307ff0 },
1734 { 0x0000a388, 0x0c000000 },
1735 { 0x0000a38c, 0x20202020 },
1736 { 0x0000a390, 0x20202020 },
1737 { 0x0000a394, 0x1ce739ce },
1738 { 0x0000a398, 0x000001ce },
1739 { 0x0000a39c, 0x00000001 },
1740 { 0x0000a3a0, 0x00000000 },
1741 { 0x0000a3a4, 0x00000000 },
1742 { 0x0000a3a8, 0x00000000 },
1743 { 0x0000a3ac, 0x00000000 },
1744 { 0x0000a3b0, 0x00000000 },
1745 { 0x0000a3b4, 0x00000000 },
1746 { 0x0000a3b8, 0x00000000 },
1747 { 0x0000a3bc, 0x00000000 },
1748 { 0x0000a3c0, 0x00000000 },
1749 { 0x0000a3c4, 0x00000000 },
1750 { 0x0000a3c8, 0x00000246 },
1751 { 0x0000a3cc, 0x20202020 },
1752 { 0x0000a3d0, 0x20202020 },
1753 { 0x0000a3d4, 0x20202020 },
1754 { 0x0000a3dc, 0x1ce739ce },
1755 { 0x0000a3e0, 0x000001ce },
1756};
1757
1758static const u32 ar5416Bank0_9160[][2] = {
1759 { 0x000098b0, 0x1e5795e5 },
1760 { 0x000098e0, 0x02008020 },
1761};
1762
1763static const u32 ar5416BB_RfGain_9160[][3] = {
1764 { 0x00009a00, 0x00000000, 0x00000000 },
1765 { 0x00009a04, 0x00000040, 0x00000040 },
1766 { 0x00009a08, 0x00000080, 0x00000080 },
1767 { 0x00009a0c, 0x000001a1, 0x00000141 },
1768 { 0x00009a10, 0x000001e1, 0x00000181 },
1769 { 0x00009a14, 0x00000021, 0x000001c1 },
1770 { 0x00009a18, 0x00000061, 0x00000001 },
1771 { 0x00009a1c, 0x00000168, 0x00000041 },
1772 { 0x00009a20, 0x000001a8, 0x000001a8 },
1773 { 0x00009a24, 0x000001e8, 0x000001e8 },
1774 { 0x00009a28, 0x00000028, 0x00000028 },
1775 { 0x00009a2c, 0x00000068, 0x00000068 },
1776 { 0x00009a30, 0x00000189, 0x000000a8 },
1777 { 0x00009a34, 0x000001c9, 0x00000169 },
1778 { 0x00009a38, 0x00000009, 0x000001a9 },
1779 { 0x00009a3c, 0x00000049, 0x000001e9 },
1780 { 0x00009a40, 0x00000089, 0x00000029 },
1781 { 0x00009a44, 0x00000170, 0x00000069 },
1782 { 0x00009a48, 0x000001b0, 0x00000190 },
1783 { 0x00009a4c, 0x000001f0, 0x000001d0 },
1784 { 0x00009a50, 0x00000030, 0x00000010 },
1785 { 0x00009a54, 0x00000070, 0x00000050 },
1786 { 0x00009a58, 0x00000191, 0x00000090 },
1787 { 0x00009a5c, 0x000001d1, 0x00000151 },
1788 { 0x00009a60, 0x00000011, 0x00000191 },
1789 { 0x00009a64, 0x00000051, 0x000001d1 },
1790 { 0x00009a68, 0x00000091, 0x00000011 },
1791 { 0x00009a6c, 0x000001b8, 0x00000051 },
1792 { 0x00009a70, 0x000001f8, 0x00000198 },
1793 { 0x00009a74, 0x00000038, 0x000001d8 },
1794 { 0x00009a78, 0x00000078, 0x00000018 },
1795 { 0x00009a7c, 0x00000199, 0x00000058 },
1796 { 0x00009a80, 0x000001d9, 0x00000098 },
1797 { 0x00009a84, 0x00000019, 0x00000159 },
1798 { 0x00009a88, 0x00000059, 0x00000199 },
1799 { 0x00009a8c, 0x00000099, 0x000001d9 },
1800 { 0x00009a90, 0x000000d9, 0x00000019 },
1801 { 0x00009a94, 0x000000f9, 0x00000059 },
1802 { 0x00009a98, 0x000000f9, 0x00000099 },
1803 { 0x00009a9c, 0x000000f9, 0x000000d9 },
1804 { 0x00009aa0, 0x000000f9, 0x000000f9 },
1805 { 0x00009aa4, 0x000000f9, 0x000000f9 },
1806 { 0x00009aa8, 0x000000f9, 0x000000f9 },
1807 { 0x00009aac, 0x000000f9, 0x000000f9 },
1808 { 0x00009ab0, 0x000000f9, 0x000000f9 },
1809 { 0x00009ab4, 0x000000f9, 0x000000f9 },
1810 { 0x00009ab8, 0x000000f9, 0x000000f9 },
1811 { 0x00009abc, 0x000000f9, 0x000000f9 },
1812 { 0x00009ac0, 0x000000f9, 0x000000f9 },
1813 { 0x00009ac4, 0x000000f9, 0x000000f9 },
1814 { 0x00009ac8, 0x000000f9, 0x000000f9 },
1815 { 0x00009acc, 0x000000f9, 0x000000f9 },
1816 { 0x00009ad0, 0x000000f9, 0x000000f9 },
1817 { 0x00009ad4, 0x000000f9, 0x000000f9 },
1818 { 0x00009ad8, 0x000000f9, 0x000000f9 },
1819 { 0x00009adc, 0x000000f9, 0x000000f9 },
1820 { 0x00009ae0, 0x000000f9, 0x000000f9 },
1821 { 0x00009ae4, 0x000000f9, 0x000000f9 },
1822 { 0x00009ae8, 0x000000f9, 0x000000f9 },
1823 { 0x00009aec, 0x000000f9, 0x000000f9 },
1824 { 0x00009af0, 0x000000f9, 0x000000f9 },
1825 { 0x00009af4, 0x000000f9, 0x000000f9 },
1826 { 0x00009af8, 0x000000f9, 0x000000f9 },
1827 { 0x00009afc, 0x000000f9, 0x000000f9 },
1828};
1829
1830static const u32 ar5416Bank1_9160[][2] = {
1831 { 0x000098b0, 0x02108421 },
1832 { 0x000098ec, 0x00000008 },
1833};
1834
1835static const u32 ar5416Bank2_9160[][2] = {
1836 { 0x000098b0, 0x0e73ff17 },
1837 { 0x000098e0, 0x00000420 },
1838};
1839
1840static const u32 ar5416Bank3_9160[][3] = {
1841 { 0x000098f0, 0x01400018, 0x01c00018 },
1842};
1843
1844static const u32 ar5416Bank6_9160[][3] = {
1845 { 0x0000989c, 0x00000000, 0x00000000 },
1846 { 0x0000989c, 0x00000000, 0x00000000 },
1847 { 0x0000989c, 0x00000000, 0x00000000 },
1848 { 0x0000989c, 0x00e00000, 0x00e00000 },
1849 { 0x0000989c, 0x005e0000, 0x005e0000 },
1850 { 0x0000989c, 0x00120000, 0x00120000 },
1851 { 0x0000989c, 0x00620000, 0x00620000 },
1852 { 0x0000989c, 0x00020000, 0x00020000 },
1853 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
1854 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
1855 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
1856 { 0x0000989c, 0x40ff0000, 0x40ff0000 },
1857 { 0x0000989c, 0x005f0000, 0x005f0000 },
1858 { 0x0000989c, 0x00870000, 0x00870000 },
1859 { 0x0000989c, 0x00f90000, 0x00f90000 },
1860 { 0x0000989c, 0x007b0000, 0x007b0000 },
1861 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
1862 { 0x0000989c, 0x00f50000, 0x00f50000 },
1863 { 0x0000989c, 0x00dc0000, 0x00dc0000 },
1864 { 0x0000989c, 0x00110000, 0x00110000 },
1865 { 0x0000989c, 0x006100a8, 0x006100a8 },
1866 { 0x0000989c, 0x004210a2, 0x004210a2 },
1867 { 0x0000989c, 0x0014008f, 0x0014008f },
1868 { 0x0000989c, 0x00c40003, 0x00c40003 },
1869 { 0x0000989c, 0x003000f2, 0x003000f2 },
1870 { 0x0000989c, 0x00440016, 0x00440016 },
1871 { 0x0000989c, 0x00410040, 0x00410040 },
1872 { 0x0000989c, 0x0001805e, 0x0001805e },
1873 { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
1874 { 0x0000989c, 0x000000f1, 0x000000f1 },
1875 { 0x0000989c, 0x00002081, 0x00002081 },
1876 { 0x0000989c, 0x000000d4, 0x000000d4 },
1877 { 0x000098d0, 0x0000000f, 0x0010000f },
1878};
1879
1880static const u32 ar5416Bank6TPC_9160[][3] = {
1881 { 0x0000989c, 0x00000000, 0x00000000 },
1882 { 0x0000989c, 0x00000000, 0x00000000 },
1883 { 0x0000989c, 0x00000000, 0x00000000 },
1884 { 0x0000989c, 0x00e00000, 0x00e00000 },
1885 { 0x0000989c, 0x005e0000, 0x005e0000 },
1886 { 0x0000989c, 0x00120000, 0x00120000 },
1887 { 0x0000989c, 0x00620000, 0x00620000 },
1888 { 0x0000989c, 0x00020000, 0x00020000 },
1889 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
1890 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
1891 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
1892 { 0x0000989c, 0x40ff0000, 0x40ff0000 },
1893 { 0x0000989c, 0x005f0000, 0x005f0000 },
1894 { 0x0000989c, 0x00870000, 0x00870000 },
1895 { 0x0000989c, 0x00f90000, 0x00f90000 },
1896 { 0x0000989c, 0x007b0000, 0x007b0000 },
1897 { 0x0000989c, 0x00ff0000, 0x00ff0000 },
1898 { 0x0000989c, 0x00f50000, 0x00f50000 },
1899 { 0x0000989c, 0x00dc0000, 0x00dc0000 },
1900 { 0x0000989c, 0x00110000, 0x00110000 },
1901 { 0x0000989c, 0x006100a8, 0x006100a8 },
1902 { 0x0000989c, 0x00423022, 0x00423022 },
1903 { 0x0000989c, 0x2014008f, 0x2014008f },
1904 { 0x0000989c, 0x00c40002, 0x00c40002 },
1905 { 0x0000989c, 0x003000f2, 0x003000f2 },
1906 { 0x0000989c, 0x00440016, 0x00440016 },
1907 { 0x0000989c, 0x00410040, 0x00410040 },
1908 { 0x0000989c, 0x0001805e, 0x0001805e },
1909 { 0x0000989c, 0x0000c0ab, 0x0000c0ab },
1910 { 0x0000989c, 0x000000e1, 0x000000e1 },
1911 { 0x0000989c, 0x00007080, 0x00007080 },
1912 { 0x0000989c, 0x000000d4, 0x000000d4 },
1913 { 0x000098d0, 0x0000000f, 0x0010000f },
1914};
1915
1916static const u32 ar5416Bank7_9160[][2] = {
1917 { 0x0000989c, 0x00000500 },
1918 { 0x0000989c, 0x00000800 },
1919 { 0x000098cc, 0x0000000e },
1920};
1921
1922static u32 ar5416Addac_9160[][2] = {
1923 {0x0000989c, 0x00000000 },
1924 {0x0000989c, 0x00000000 },
1925 {0x0000989c, 0x00000000 },
1926 {0x0000989c, 0x00000000 },
1927 {0x0000989c, 0x00000000 },
1928 {0x0000989c, 0x00000000 },
1929 {0x0000989c, 0x000000c0 },
1930 {0x0000989c, 0x00000018 },
1931 {0x0000989c, 0x00000004 },
1932 {0x0000989c, 0x00000000 },
1933 {0x0000989c, 0x00000000 },
1934 {0x0000989c, 0x00000000 },
1935 {0x0000989c, 0x00000000 },
1936 {0x0000989c, 0x00000000 },
1937 {0x0000989c, 0x00000000 },
1938 {0x0000989c, 0x00000000 },
1939 {0x0000989c, 0x00000000 },
1940 {0x0000989c, 0x00000000 },
1941 {0x0000989c, 0x00000000 },
1942 {0x0000989c, 0x00000000 },
1943 {0x0000989c, 0x00000000 },
1944 {0x0000989c, 0x000000c0 },
1945 {0x0000989c, 0x00000019 },
1946 {0x0000989c, 0x00000004 },
1947 {0x0000989c, 0x00000000 },
1948 {0x0000989c, 0x00000000 },
1949 {0x0000989c, 0x00000000 },
1950 {0x0000989c, 0x00000004 },
1951 {0x0000989c, 0x00000003 },
1952 {0x0000989c, 0x00000008 },
1953 {0x0000989c, 0x00000000 },
1954 {0x000098cc, 0x00000000 },
1955};
1956
1957static u32 ar5416Addac_91601_1[][2] = {
1958 {0x0000989c, 0x00000000 },
1959 {0x0000989c, 0x00000000 },
1960 {0x0000989c, 0x00000000 },
1961 {0x0000989c, 0x00000000 },
1962 {0x0000989c, 0x00000000 },
1963 {0x0000989c, 0x00000000 },
1964 {0x0000989c, 0x000000c0 },
1965 {0x0000989c, 0x00000018 },
1966 {0x0000989c, 0x00000004 },
1967 {0x0000989c, 0x00000000 },
1968 {0x0000989c, 0x00000000 },
1969 {0x0000989c, 0x00000000 },
1970 {0x0000989c, 0x00000000 },
1971 {0x0000989c, 0x00000000 },
1972 {0x0000989c, 0x00000000 },
1973 {0x0000989c, 0x00000000 },
1974 {0x0000989c, 0x00000000 },
1975 {0x0000989c, 0x00000000 },
1976 {0x0000989c, 0x00000000 },
1977 {0x0000989c, 0x00000000 },
1978 {0x0000989c, 0x00000000 },
1979 {0x0000989c, 0x000000c0 },
1980 {0x0000989c, 0x00000019 },
1981 {0x0000989c, 0x00000004 },
1982 {0x0000989c, 0x00000000 },
1983 {0x0000989c, 0x00000000 },
1984 {0x0000989c, 0x00000000 },
1985 {0x0000989c, 0x00000000 },
1986 {0x0000989c, 0x00000000 },
1987 {0x0000989c, 0x00000000 },
1988 {0x0000989c, 0x00000000 },
1989 {0x000098cc, 0x00000000 },
1990};
1991
1992/* XXX 9280 1 */
1993static const u32 ar9280Modes_9280[][6] = { 20static const u32 ar9280Modes_9280[][6] = {
1994 { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 }, 21 { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
1995 { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 }, 22 { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
@@ -2766,7 +793,7 @@ static const u32 ar9280Common_9280_2[][2] = {
2766 { 0x00008258, 0x00000000 }, 793 { 0x00008258, 0x00000000 },
2767 { 0x0000825c, 0x400000ff }, 794 { 0x0000825c, 0x400000ff },
2768 { 0x00008260, 0x00080922 }, 795 { 0x00008260, 0x00080922 },
2769 { 0x00008264, 0xa8a00010 }, 796 { 0x00008264, 0x88a00010 },
2770 { 0x00008270, 0x00000000 }, 797 { 0x00008270, 0x00000000 },
2771 { 0x00008274, 0x40000000 }, 798 { 0x00008274, 0x40000000 },
2772 { 0x00008278, 0x003e4180 }, 799 { 0x00008278, 0x003e4180 },
@@ -3441,7 +1468,7 @@ static const u32 ar9280PciePhy_clkreq_always_on_L1_9280[][2] = {
3441}; 1468};
3442 1469
3443/* AR9285 Revsion 10*/ 1470/* AR9285 Revsion 10*/
3444static const u_int32_t ar9285Modes_9285[][6] = { 1471static const u32 ar9285Modes_9285[][6] = {
3445 { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 }, 1472 { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
3446 { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 }, 1473 { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
3447 { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 }, 1474 { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
@@ -3763,7 +1790,7 @@ static const u_int32_t ar9285Modes_9285[][6] = {
3763 { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e }, 1790 { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
3764}; 1791};
3765 1792
3766static const u_int32_t ar9285Common_9285[][2] = { 1793static const u32 ar9285Common_9285[][2] = {
3767 { 0x0000000c, 0x00000000 }, 1794 { 0x0000000c, 0x00000000 },
3768 { 0x00000030, 0x00020045 }, 1795 { 0x00000030, 0x00020045 },
3769 { 0x00000034, 0x00000005 }, 1796 { 0x00000034, 0x00000005 },
@@ -3936,7 +1963,7 @@ static const u_int32_t ar9285Common_9285[][2] = {
3936 { 0x00008258, 0x00000000 }, 1963 { 0x00008258, 0x00000000 },
3937 { 0x0000825c, 0x400000ff }, 1964 { 0x0000825c, 0x400000ff },
3938 { 0x00008260, 0x00080922 }, 1965 { 0x00008260, 0x00080922 },
3939 { 0x00008264, 0xa8a00010 }, 1966 { 0x00008264, 0x88a00010 },
3940 { 0x00008270, 0x00000000 }, 1967 { 0x00008270, 0x00000000 },
3941 { 0x00008274, 0x40000000 }, 1968 { 0x00008274, 0x40000000 },
3942 { 0x00008278, 0x003e4180 }, 1969 { 0x00008278, 0x003e4180 },
@@ -4096,7 +2123,7 @@ static const u_int32_t ar9285Common_9285[][2] = {
4096 { 0x00007870, 0x10142c00 }, 2123 { 0x00007870, 0x10142c00 },
4097}; 2124};
4098 2125
4099static const u_int32_t ar9285PciePhy_clkreq_always_on_L1_9285[][2] = { 2126static const u32 ar9285PciePhy_clkreq_always_on_L1_9285[][2] = {
4100 {0x00004040, 0x9248fd00 }, 2127 {0x00004040, 0x9248fd00 },
4101 {0x00004040, 0x24924924 }, 2128 {0x00004040, 0x24924924 },
4102 {0x00004040, 0xa8000019 }, 2129 {0x00004040, 0xa8000019 },
@@ -4109,7 +2136,7 @@ static const u_int32_t ar9285PciePhy_clkreq_always_on_L1_9285[][2] = {
4109 {0x00004044, 0x00000000 }, 2136 {0x00004044, 0x00000000 },
4110}; 2137};
4111 2138
4112static const u_int32_t ar9285PciePhy_clkreq_off_L1_9285[][2] = { 2139static const u32 ar9285PciePhy_clkreq_off_L1_9285[][2] = {
4113 {0x00004040, 0x9248fd00 }, 2140 {0x00004040, 0x9248fd00 },
4114 {0x00004040, 0x24924924 }, 2141 {0x00004040, 0x24924924 },
4115 {0x00004040, 0xa8000019 }, 2142 {0x00004040, 0xa8000019 },
@@ -4123,7 +2150,7 @@ static const u_int32_t ar9285PciePhy_clkreq_off_L1_9285[][2] = {
4123}; 2150};
4124 2151
4125/* AR9285 v1_2 PCI Register Writes. Created: 04/13/09 */ 2152/* AR9285 v1_2 PCI Register Writes. Created: 04/13/09 */
4126static const u_int32_t ar9285Modes_9285_1_2[][6] = { 2153static const u32 ar9285Modes_9285_1_2[][6] = {
4127 /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */ 2154 /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
4128 { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 }, 2155 { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
4129 { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 }, 2156 { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
@@ -4429,7 +2456,7 @@ static const u_int32_t ar9285Modes_9285_1_2[][6] = {
4429 { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e }, 2456 { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
4430}; 2457};
4431 2458
4432static const u_int32_t ar9285Common_9285_1_2[][2] = { 2459static const u32 ar9285Common_9285_1_2[][2] = {
4433 { 0x0000000c, 0x00000000 }, 2460 { 0x0000000c, 0x00000000 },
4434 { 0x00000030, 0x00020045 }, 2461 { 0x00000030, 0x00020045 },
4435 { 0x00000034, 0x00000005 }, 2462 { 0x00000034, 0x00000005 },
@@ -4748,7 +2775,7 @@ static const u_int32_t ar9285Common_9285_1_2[][2] = {
4748 { 0x00007870, 0x10142c00 }, 2775 { 0x00007870, 0x10142c00 },
4749}; 2776};
4750 2777
4751static const u_int32_t ar9285Modes_high_power_tx_gain_9285_1_2[][6] = { 2778static const u32 ar9285Modes_high_power_tx_gain_9285_1_2[][6] = {
4752 /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */ 2779 /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
4753 { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, 2780 { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
4754 { 0x0000a304, 0x00000000, 0x00000000, 0x00006200, 0x00006200, 0x00000000 }, 2781 { 0x0000a304, 0x00000000, 0x00000000, 0x00006200, 0x00006200, 0x00000000 },
@@ -4789,7 +2816,7 @@ static const u_int32_t ar9285Modes_high_power_tx_gain_9285_1_2[][6] = {
4789 { 0x0000a3e0, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7 }, 2816 { 0x0000a3e0, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7 },
4790}; 2817};
4791 2818
4792static const u_int32_t ar9285Modes_original_tx_gain_9285_1_2[][6] = { 2819static const u32 ar9285Modes_original_tx_gain_9285_1_2[][6] = {
4793 /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */ 2820 /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
4794 { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, 2821 { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
4795 { 0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200, 0x00000000 }, 2822 { 0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200, 0x00000000 },
@@ -4830,7 +2857,7 @@ static const u_int32_t ar9285Modes_original_tx_gain_9285_1_2[][6] = {
4830 { 0x0000a3e0, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c }, 2857 { 0x0000a3e0, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c },
4831}; 2858};
4832 2859
4833static const u_int32_t ar9285Modes_XE2_0_normal_power[][6] = { 2860static const u32 ar9285Modes_XE2_0_normal_power[][6] = {
4834 { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, 2861 { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
4835 { 0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200, 0x00000000 }, 2862 { 0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200, 0x00000000 },
4836 { 0x0000a308, 0x00000000, 0x00000000, 0x00010208, 0x00010208, 0x00000000 }, 2863 { 0x0000a308, 0x00000000, 0x00000000, 0x00010208, 0x00010208, 0x00000000 },
@@ -4870,7 +2897,7 @@ static const u_int32_t ar9285Modes_XE2_0_normal_power[][6] = {
4870 { 0x0000a3e0, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c }, 2897 { 0x0000a3e0, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c },
4871}; 2898};
4872 2899
4873static const u_int32_t ar9285Modes_XE2_0_high_power[][6] = { 2900static const u32 ar9285Modes_XE2_0_high_power[][6] = {
4874 { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, 2901 { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
4875 { 0x0000a304, 0x00000000, 0x00000000, 0x00006200, 0x00006200, 0x00000000 }, 2902 { 0x0000a304, 0x00000000, 0x00000000, 0x00006200, 0x00006200, 0x00000000 },
4876 { 0x0000a308, 0x00000000, 0x00000000, 0x00008201, 0x00008201, 0x00000000 }, 2903 { 0x0000a308, 0x00000000, 0x00000000, 0x00008201, 0x00008201, 0x00000000 },
@@ -4910,7 +2937,7 @@ static const u_int32_t ar9285Modes_XE2_0_high_power[][6] = {
4910 { 0x0000a3e0, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7 }, 2937 { 0x0000a3e0, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7 },
4911}; 2938};
4912 2939
4913static const u_int32_t ar9285PciePhy_clkreq_always_on_L1_9285_1_2[][2] = { 2940static const u32 ar9285PciePhy_clkreq_always_on_L1_9285_1_2[][2] = {
4914 {0x00004040, 0x9248fd00 }, 2941 {0x00004040, 0x9248fd00 },
4915 {0x00004040, 0x24924924 }, 2942 {0x00004040, 0x24924924 },
4916 {0x00004040, 0xa8000019 }, 2943 {0x00004040, 0xa8000019 },
@@ -4923,7 +2950,7 @@ static const u_int32_t ar9285PciePhy_clkreq_always_on_L1_9285_1_2[][2] = {
4923 {0x00004044, 0x00000000 }, 2950 {0x00004044, 0x00000000 },
4924}; 2951};
4925 2952
4926static const u_int32_t ar9285PciePhy_clkreq_off_L1_9285_1_2[][2] = { 2953static const u32 ar9285PciePhy_clkreq_off_L1_9285_1_2[][2] = {
4927 {0x00004040, 0x9248fd00 }, 2954 {0x00004040, 0x9248fd00 },
4928 {0x00004040, 0x24924924 }, 2955 {0x00004040, 0x24924924 },
4929 {0x00004040, 0xa8000019 }, 2956 {0x00004040, 0xa8000019 },
@@ -4937,7 +2964,7 @@ static const u_int32_t ar9285PciePhy_clkreq_off_L1_9285_1_2[][2] = {
4937}; 2964};
4938 2965
4939/* AR9287 Revision 10 */ 2966/* AR9287 Revision 10 */
4940static const u_int32_t ar9287Modes_9287_1_0[][6] = { 2967static const u32 ar9287Modes_9287_1_0[][6] = {
4941 /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */ 2968 /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
4942 { 0x00001030, 0x00000000, 0x00000000, 0x000002c0, 0x00000160, 0x000001e0 }, 2969 { 0x00001030, 0x00000000, 0x00000000, 0x000002c0, 0x00000160, 0x000001e0 },
4943 { 0x00001070, 0x00000000, 0x00000000, 0x00000318, 0x0000018c, 0x000001e0 }, 2970 { 0x00001070, 0x00000000, 0x00000000, 0x00000318, 0x0000018c, 0x000001e0 },
@@ -4984,7 +3011,7 @@ static const u_int32_t ar9287Modes_9287_1_0[][6] = {
4984 { 0x0000a3d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, 3011 { 0x0000a3d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
4985}; 3012};
4986 3013
4987static const u_int32_t ar9287Common_9287_1_0[][2] = { 3014static const u32 ar9287Common_9287_1_0[][2] = {
4988 { 0x0000000c, 0x00000000 }, 3015 { 0x0000000c, 0x00000000 },
4989 { 0x00000030, 0x00020015 }, 3016 { 0x00000030, 0x00020015 },
4990 { 0x00000034, 0x00000005 }, 3017 { 0x00000034, 0x00000005 },
@@ -5158,7 +3185,7 @@ static const u_int32_t ar9287Common_9287_1_0[][2] = {
5158 { 0x00008258, 0x00000000 }, 3185 { 0x00008258, 0x00000000 },
5159 { 0x0000825c, 0x400000ff }, 3186 { 0x0000825c, 0x400000ff },
5160 { 0x00008260, 0x00080922 }, 3187 { 0x00008260, 0x00080922 },
5161 { 0x00008264, 0xa8a00010 }, 3188 { 0x00008264, 0x88a00010 },
5162 { 0x00008270, 0x00000000 }, 3189 { 0x00008270, 0x00000000 },
5163 { 0x00008274, 0x40000000 }, 3190 { 0x00008274, 0x40000000 },
5164 { 0x00008278, 0x003e4180 }, 3191 { 0x00008278, 0x003e4180 },
@@ -5355,7 +3382,7 @@ static const u_int32_t ar9287Common_9287_1_0[][2] = {
5355 { 0x000078b8, 0x2a850160 }, 3382 { 0x000078b8, 0x2a850160 },
5356}; 3383};
5357 3384
5358static const u_int32_t ar9287Modes_tx_gain_9287_1_0[][6] = { 3385static const u32 ar9287Modes_tx_gain_9287_1_0[][6] = {
5359 /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */ 3386 /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
5360 { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, 3387 { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
5361 { 0x0000a304, 0x00000000, 0x00000000, 0x00004002, 0x00004002, 0x00004002 }, 3388 { 0x0000a304, 0x00000000, 0x00000000, 0x00004002, 0x00004002, 0x00004002 },
@@ -5405,7 +3432,7 @@ static const u_int32_t ar9287Modes_tx_gain_9287_1_0[][6] = {
5405}; 3432};
5406 3433
5407 3434
5408static const u_int32_t ar9287Modes_rx_gain_9287_1_0[][6] = { 3435static const u32 ar9287Modes_rx_gain_9287_1_0[][6] = {
5409 /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */ 3436 /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
5410 { 0x00009a00, 0x00000000, 0x00000000, 0x0000a120, 0x0000a120, 0x0000a120 }, 3437 { 0x00009a00, 0x00000000, 0x00000000, 0x0000a120, 0x0000a120, 0x0000a120 },
5411 { 0x00009a04, 0x00000000, 0x00000000, 0x0000a124, 0x0000a124, 0x0000a124 }, 3438 { 0x00009a04, 0x00000000, 0x00000000, 0x0000a124, 0x0000a124, 0x0000a124 },
@@ -5667,7 +3694,7 @@ static const u_int32_t ar9287Modes_rx_gain_9287_1_0[][6] = {
5667 { 0x0000a848, 0x00000000, 0x00000000, 0x00001067, 0x00001067, 0x00001067 }, 3694 { 0x0000a848, 0x00000000, 0x00000000, 0x00001067, 0x00001067, 0x00001067 },
5668}; 3695};
5669 3696
5670static const u_int32_t ar9287PciePhy_clkreq_always_on_L1_9287_1_0[][2] = { 3697static const u32 ar9287PciePhy_clkreq_always_on_L1_9287_1_0[][2] = {
5671 {0x00004040, 0x9248fd00 }, 3698 {0x00004040, 0x9248fd00 },
5672 {0x00004040, 0x24924924 }, 3699 {0x00004040, 0x24924924 },
5673 {0x00004040, 0xa8000019 }, 3700 {0x00004040, 0xa8000019 },
@@ -5680,7 +3707,7 @@ static const u_int32_t ar9287PciePhy_clkreq_always_on_L1_9287_1_0[][2] = {
5680 {0x00004044, 0x00000000 }, 3707 {0x00004044, 0x00000000 },
5681}; 3708};
5682 3709
5683static const u_int32_t ar9287PciePhy_clkreq_off_L1_9287_1_0[][2] = { 3710static const u32 ar9287PciePhy_clkreq_off_L1_9287_1_0[][2] = {
5684 {0x00004040, 0x9248fd00 }, 3711 {0x00004040, 0x9248fd00 },
5685 {0x00004040, 0x24924924 }, 3712 {0x00004040, 0x24924924 },
5686 {0x00004040, 0xa8000019 }, 3713 {0x00004040, 0xa8000019 },
@@ -5695,7 +3722,7 @@ static const u_int32_t ar9287PciePhy_clkreq_off_L1_9287_1_0[][2] = {
5695 3722
5696/* AR9287 Revision 11 */ 3723/* AR9287 Revision 11 */
5697 3724
5698static const u_int32_t ar9287Modes_9287_1_1[][6] = { 3725static const u32 ar9287Modes_9287_1_1[][6] = {
5699 /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */ 3726 /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
5700 { 0x00001030, 0x00000000, 0x00000000, 0x000002c0, 0x00000160, 0x000001e0 }, 3727 { 0x00001030, 0x00000000, 0x00000000, 0x000002c0, 0x00000160, 0x000001e0 },
5701 { 0x00001070, 0x00000000, 0x00000000, 0x00000318, 0x0000018c, 0x000001e0 }, 3728 { 0x00001070, 0x00000000, 0x00000000, 0x00000318, 0x0000018c, 0x000001e0 },
@@ -5742,7 +3769,7 @@ static const u_int32_t ar9287Modes_9287_1_1[][6] = {
5742 { 0x0000a3d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, 3769 { 0x0000a3d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
5743}; 3770};
5744 3771
5745static const u_int32_t ar9287Common_9287_1_1[][2] = { 3772static const u32 ar9287Common_9287_1_1[][2] = {
5746 { 0x0000000c, 0x00000000 }, 3773 { 0x0000000c, 0x00000000 },
5747 { 0x00000030, 0x00020015 }, 3774 { 0x00000030, 0x00020015 },
5748 { 0x00000034, 0x00000005 }, 3775 { 0x00000034, 0x00000005 },
@@ -6112,21 +4139,22 @@ static const u_int32_t ar9287Common_9287_1_1[][2] = {
6112 4139
6113/* 4140/*
6114 * For Japanese regulatory requirements, 2484 MHz requires the following three 4141 * For Japanese regulatory requirements, 2484 MHz requires the following three
6115 * registers be programmed differently from the channel between 2412 and 2472 MHz. 4142 * registers be programmed differently from the channel between 2412 and
4143 * 2472 MHz.
6116 */ 4144 */
6117static const u_int32_t ar9287Common_normal_cck_fir_coeff_92871_1[][2] = { 4145static const u32 ar9287Common_normal_cck_fir_coeff_92871_1[][2] = {
6118 { 0x0000a1f4, 0x00fffeff }, 4146 { 0x0000a1f4, 0x00fffeff },
6119 { 0x0000a1f8, 0x00f5f9ff }, 4147 { 0x0000a1f8, 0x00f5f9ff },
6120 { 0x0000a1fc, 0xb79f6427 }, 4148 { 0x0000a1fc, 0xb79f6427 },
6121}; 4149};
6122 4150
6123static const u_int32_t ar9287Common_japan_2484_cck_fir_coeff_92871_1[][2] = { 4151static const u32 ar9287Common_japan_2484_cck_fir_coeff_92871_1[][2] = {
6124 { 0x0000a1f4, 0x00000000 }, 4152 { 0x0000a1f4, 0x00000000 },
6125 { 0x0000a1f8, 0xefff0301 }, 4153 { 0x0000a1f8, 0xefff0301 },
6126 { 0x0000a1fc, 0xca9228ee }, 4154 { 0x0000a1fc, 0xca9228ee },
6127}; 4155};
6128 4156
6129static const u_int32_t ar9287Modes_tx_gain_9287_1_1[][6] = { 4157static const u32 ar9287Modes_tx_gain_9287_1_1[][6] = {
6130 /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */ 4158 /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
6131 { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, 4159 { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
6132 { 0x0000a304, 0x00000000, 0x00000000, 0x00004002, 0x00004002, 0x00004002 }, 4160 { 0x0000a304, 0x00000000, 0x00000000, 0x00004002, 0x00004002, 0x00004002 },
@@ -6175,7 +4203,7 @@ static const u_int32_t ar9287Modes_tx_gain_9287_1_1[][6] = {
6175 { 0x0000a274, 0x0a180000, 0x0a180000, 0x0a1aa000, 0x0a1aa000, 0x0a1aa000 }, 4203 { 0x0000a274, 0x0a180000, 0x0a180000, 0x0a1aa000, 0x0a1aa000, 0x0a1aa000 },
6176}; 4204};
6177 4205
6178static const u_int32_t ar9287Modes_rx_gain_9287_1_1[][6] = { 4206static const u32 ar9287Modes_rx_gain_9287_1_1[][6] = {
6179 /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */ 4207 /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */
6180 { 0x00009a00, 0x00000000, 0x00000000, 0x0000a120, 0x0000a120, 0x0000a120 }, 4208 { 0x00009a00, 0x00000000, 0x00000000, 0x0000a120, 0x0000a120, 0x0000a120 },
6181 { 0x00009a04, 0x00000000, 0x00000000, 0x0000a124, 0x0000a124, 0x0000a124 }, 4209 { 0x00009a04, 0x00000000, 0x00000000, 0x0000a124, 0x0000a124, 0x0000a124 },
@@ -6437,7 +4465,7 @@ static const u_int32_t ar9287Modes_rx_gain_9287_1_1[][6] = {
6437 { 0x0000a848, 0x00000000, 0x00000000, 0x00001067, 0x00001067, 0x00001067 }, 4465 { 0x0000a848, 0x00000000, 0x00000000, 0x00001067, 0x00001067, 0x00001067 },
6438}; 4466};
6439 4467
6440static const u_int32_t ar9287PciePhy_clkreq_always_on_L1_9287_1_1[][2] = { 4468static const u32 ar9287PciePhy_clkreq_always_on_L1_9287_1_1[][2] = {
6441 {0x00004040, 0x9248fd00 }, 4469 {0x00004040, 0x9248fd00 },
6442 {0x00004040, 0x24924924 }, 4470 {0x00004040, 0x24924924 },
6443 {0x00004040, 0xa8000019 }, 4471 {0x00004040, 0xa8000019 },
@@ -6450,7 +4478,7 @@ static const u_int32_t ar9287PciePhy_clkreq_always_on_L1_9287_1_1[][2] = {
6450 {0x00004044, 0x00000000 }, 4478 {0x00004044, 0x00000000 },
6451}; 4479};
6452 4480
6453static const u_int32_t ar9287PciePhy_clkreq_off_L1_9287_1_1[][2] = { 4481static const u32 ar9287PciePhy_clkreq_off_L1_9287_1_1[][2] = {
6454 {0x00004040, 0x9248fd00 }, 4482 {0x00004040, 0x9248fd00 },
6455 {0x00004040, 0x24924924 }, 4483 {0x00004040, 0x24924924 },
6456 {0x00004040, 0xa8000019 }, 4484 {0x00004040, 0xa8000019 },
@@ -6465,7 +4493,7 @@ static const u_int32_t ar9287PciePhy_clkreq_off_L1_9287_1_1[][2] = {
6465 4493
6466 4494
6467/* AR9271 initialization values automaticaly created: 06/04/09 */ 4495/* AR9271 initialization values automaticaly created: 06/04/09 */
6468static const u_int32_t ar9271Modes_9271[][6] = { 4496static const u32 ar9271Modes_9271[][6] = {
6469 { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 }, 4497 { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 },
6470 { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 }, 4498 { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 },
6471 { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 }, 4499 { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 },
@@ -6771,7 +4799,7 @@ static const u_int32_t ar9271Modes_9271[][6] = {
6771 { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e }, 4799 { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e },
6772}; 4800};
6773 4801
6774static const u_int32_t ar9271Common_9271[][2] = { 4802static const u32 ar9271Common_9271[][2] = {
6775 { 0x0000000c, 0x00000000 }, 4803 { 0x0000000c, 0x00000000 },
6776 { 0x00000030, 0x00020045 }, 4804 { 0x00000030, 0x00020045 },
6777 { 0x00000034, 0x00000005 }, 4805 { 0x00000034, 0x00000005 },
@@ -6945,7 +4973,7 @@ static const u_int32_t ar9271Common_9271[][2] = {
6945 { 0x00008258, 0x00000000 }, 4973 { 0x00008258, 0x00000000 },
6946 { 0x0000825c, 0x400000ff }, 4974 { 0x0000825c, 0x400000ff },
6947 { 0x00008260, 0x00080922 }, 4975 { 0x00008260, 0x00080922 },
6948 { 0x00008264, 0xa8a00010 }, 4976 { 0x00008264, 0x88a00010 },
6949 { 0x00008270, 0x00000000 }, 4977 { 0x00008270, 0x00000000 },
6950 { 0x00008274, 0x40000000 }, 4978 { 0x00008274, 0x40000000 },
6951 { 0x00008278, 0x003e4180 }, 4979 { 0x00008278, 0x003e4180 },
@@ -7099,24 +5127,24 @@ static const u_int32_t ar9271Common_9271[][2] = {
7099 { 0x0000d384, 0xf3307ff0 }, 5127 { 0x0000d384, 0xf3307ff0 },
7100}; 5128};
7101 5129
7102static const u_int32_t ar9271Common_normal_cck_fir_coeff_9271[][2] = { 5130static const u32 ar9271Common_normal_cck_fir_coeff_9271[][2] = {
7103 { 0x0000a1f4, 0x00fffeff }, 5131 { 0x0000a1f4, 0x00fffeff },
7104 { 0x0000a1f8, 0x00f5f9ff }, 5132 { 0x0000a1f8, 0x00f5f9ff },
7105 { 0x0000a1fc, 0xb79f6427 }, 5133 { 0x0000a1fc, 0xb79f6427 },
7106}; 5134};
7107 5135
7108static const u_int32_t ar9271Common_japan_2484_cck_fir_coeff_9271[][2] = { 5136static const u32 ar9271Common_japan_2484_cck_fir_coeff_9271[][2] = {
7109 { 0x0000a1f4, 0x00000000 }, 5137 { 0x0000a1f4, 0x00000000 },
7110 { 0x0000a1f8, 0xefff0301 }, 5138 { 0x0000a1f8, 0xefff0301 },
7111 { 0x0000a1fc, 0xca9228ee }, 5139 { 0x0000a1fc, 0xca9228ee },
7112}; 5140};
7113 5141
7114static const u_int32_t ar9271Modes_9271_1_0_only[][6] = { 5142static const u32 ar9271Modes_9271_1_0_only[][6] = {
7115 { 0x00009910, 0x30002311, 0x30002311, 0x30002311, 0x30002311, 0x30002311 }, 5143 { 0x00009910, 0x30002311, 0x30002311, 0x30002311, 0x30002311, 0x30002311 },
7116 { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 }, 5144 { 0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001 },
7117}; 5145};
7118 5146
7119static const u_int32_t ar9271Modes_9271_ANI_reg[][6] = { 5147static const u32 ar9271Modes_9271_ANI_reg[][6] = {
7120 { 0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2 }, 5148 { 0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2 },
7121 { 0x0000985c, 0x3139605e, 0x3139605e, 0x3137605e, 0x3137605e, 0x3139605e }, 5149 { 0x0000985c, 0x3139605e, 0x3139605e, 0x3137605e, 0x3137605e, 0x3139605e },
7122 { 0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e }, 5150 { 0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e },
@@ -7127,7 +5155,7 @@ static const u_int32_t ar9271Modes_9271_ANI_reg[][6] = {
7127 { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 }, 5155 { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 },
7128}; 5156};
7129 5157
7130static const u_int32_t ar9271Modes_normal_power_tx_gain_9271[][6] = { 5158static const u32 ar9271Modes_normal_power_tx_gain_9271[][6] = {
7131 { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, 5159 { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
7132 { 0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200, 0x00000000 }, 5160 { 0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200, 0x00000000 },
7133 { 0x0000a308, 0x00000000, 0x00000000, 0x00010208, 0x00010208, 0x00000000 }, 5161 { 0x0000a308, 0x00000000, 0x00000000, 0x00010208, 0x00010208, 0x00000000 },
@@ -7163,7 +5191,7 @@ static const u_int32_t ar9271Modes_normal_power_tx_gain_9271[][6] = {
7163 { 0x0000a3e0, 0x000003bd, 0x000003bd, 0x000003bd, 0x000003bd, 0x000003bd }, 5191 { 0x0000a3e0, 0x000003bd, 0x000003bd, 0x000003bd, 0x000003bd, 0x000003bd },
7164}; 5192};
7165 5193
7166static const u_int32_t ar9271Modes_high_power_tx_gain_9271[][6] = { 5194static const u32 ar9271Modes_high_power_tx_gain_9271[][6] = {
7167 { 0x0000a300, 0x00000000, 0x00000000, 0x00010000, 0x00010000, 0x00000000 }, 5195 { 0x0000a300, 0x00000000, 0x00000000, 0x00010000, 0x00010000, 0x00000000 },
7168 { 0x0000a304, 0x00000000, 0x00000000, 0x00016200, 0x00016200, 0x00000000 }, 5196 { 0x0000a304, 0x00000000, 0x00000000, 0x00016200, 0x00016200, 0x00000000 },
7169 { 0x0000a308, 0x00000000, 0x00000000, 0x00018201, 0x00018201, 0x00000000 }, 5197 { 0x0000a308, 0x00000000, 0x00000000, 0x00018201, 0x00018201, 0x00000000 },
@@ -7198,3 +5226,5 @@ static const u_int32_t ar9271Modes_high_power_tx_gain_9271[][6] = {
7198 { 0x0000a3dc, 0x06318c63, 0x06318c63, 0x06318c63, 0x06318c63, 0x06318c63 }, 5226 { 0x0000a3dc, 0x06318c63, 0x06318c63, 0x06318c63, 0x06318c63, 0x06318c63 },
7199 { 0x0000a3e0, 0x00000063, 0x00000063, 0x00000063, 0x00000063, 0x00000063 }, 5227 { 0x0000a3e0, 0x00000063, 0x00000063, 0x00000063, 0x00000063, 0x00000063 },
7200}; 5228};
5229
5230#endif /* INITVALS_9002_10_H */
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_mac.c b/drivers/net/wireless/ath/ath9k/ar9002_mac.c
new file mode 100644
index 000000000000..2be20d2070c4
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/ar9002_mac.c
@@ -0,0 +1,480 @@
1/*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "hw.h"
18
19#define AR_BufLen 0x00000fff
20
21static void ar9002_hw_rx_enable(struct ath_hw *ah)
22{
23 REG_WRITE(ah, AR_CR, AR_CR_RXE);
24}
25
26static void ar9002_hw_set_desc_link(void *ds, u32 ds_link)
27{
28 ((struct ath_desc*) ds)->ds_link = ds_link;
29}
30
31static void ar9002_hw_get_desc_link(void *ds, u32 **ds_link)
32{
33 *ds_link = &((struct ath_desc *)ds)->ds_link;
34}
35
36static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
37{
38 u32 isr = 0;
39 u32 mask2 = 0;
40 struct ath9k_hw_capabilities *pCap = &ah->caps;
41 u32 sync_cause = 0;
42 bool fatal_int = false;
43 struct ath_common *common = ath9k_hw_common(ah);
44
45 if (!AR_SREV_9100(ah)) {
46 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
47 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
48 == AR_RTC_STATUS_ON) {
49 isr = REG_READ(ah, AR_ISR);
50 }
51 }
52
53 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
54 AR_INTR_SYNC_DEFAULT;
55
56 *masked = 0;
57
58 if (!isr && !sync_cause)
59 return false;
60 } else {
61 *masked = 0;
62 isr = REG_READ(ah, AR_ISR);
63 }
64
65 if (isr) {
66 if (isr & AR_ISR_BCNMISC) {
67 u32 isr2;
68 isr2 = REG_READ(ah, AR_ISR_S2);
69 if (isr2 & AR_ISR_S2_TIM)
70 mask2 |= ATH9K_INT_TIM;
71 if (isr2 & AR_ISR_S2_DTIM)
72 mask2 |= ATH9K_INT_DTIM;
73 if (isr2 & AR_ISR_S2_DTIMSYNC)
74 mask2 |= ATH9K_INT_DTIMSYNC;
75 if (isr2 & (AR_ISR_S2_CABEND))
76 mask2 |= ATH9K_INT_CABEND;
77 if (isr2 & AR_ISR_S2_GTT)
78 mask2 |= ATH9K_INT_GTT;
79 if (isr2 & AR_ISR_S2_CST)
80 mask2 |= ATH9K_INT_CST;
81 if (isr2 & AR_ISR_S2_TSFOOR)
82 mask2 |= ATH9K_INT_TSFOOR;
83 }
84
85 isr = REG_READ(ah, AR_ISR_RAC);
86 if (isr == 0xffffffff) {
87 *masked = 0;
88 return false;
89 }
90
91 *masked = isr & ATH9K_INT_COMMON;
92
93 if (ah->config.rx_intr_mitigation) {
94 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
95 *masked |= ATH9K_INT_RX;
96 }
97
98 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
99 *masked |= ATH9K_INT_RX;
100 if (isr &
101 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
102 AR_ISR_TXEOL)) {
103 u32 s0_s, s1_s;
104
105 *masked |= ATH9K_INT_TX;
106
107 s0_s = REG_READ(ah, AR_ISR_S0_S);
108 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
109 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
110
111 s1_s = REG_READ(ah, AR_ISR_S1_S);
112 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
113 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
114 }
115
116 if (isr & AR_ISR_RXORN) {
117 ath_print(common, ATH_DBG_INTERRUPT,
118 "receive FIFO overrun interrupt\n");
119 }
120
121 if (!AR_SREV_9100(ah)) {
122 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
123 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
124 if (isr5 & AR_ISR_S5_TIM_TIMER)
125 *masked |= ATH9K_INT_TIM_TIMER;
126 }
127 }
128
129 *masked |= mask2;
130 }
131
132 if (AR_SREV_9100(ah))
133 return true;
134
135 if (isr & AR_ISR_GENTMR) {
136 u32 s5_s;
137
138 s5_s = REG_READ(ah, AR_ISR_S5_S);
139 if (isr & AR_ISR_GENTMR) {
140 ah->intr_gen_timer_trigger =
141 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
142
143 ah->intr_gen_timer_thresh =
144 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
145
146 if (ah->intr_gen_timer_trigger)
147 *masked |= ATH9K_INT_GENTIMER;
148
149 }
150 }
151
152 if (sync_cause) {
153 fatal_int =
154 (sync_cause &
155 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
156 ? true : false;
157
158 if (fatal_int) {
159 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
160 ath_print(common, ATH_DBG_ANY,
161 "received PCI FATAL interrupt\n");
162 }
163 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
164 ath_print(common, ATH_DBG_ANY,
165 "received PCI PERR interrupt\n");
166 }
167 *masked |= ATH9K_INT_FATAL;
168 }
169 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
170 ath_print(common, ATH_DBG_INTERRUPT,
171 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
172 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
173 REG_WRITE(ah, AR_RC, 0);
174 *masked |= ATH9K_INT_FATAL;
175 }
176 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
177 ath_print(common, ATH_DBG_INTERRUPT,
178 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
179 }
180
181 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
182 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
183 }
184
185 return true;
186}
187
188static void ar9002_hw_fill_txdesc(struct ath_hw *ah, void *ds, u32 seglen,
189 bool is_firstseg, bool is_lastseg,
190 const void *ds0, dma_addr_t buf_addr,
191 unsigned int qcu)
192{
193 struct ar5416_desc *ads = AR5416DESC(ds);
194
195 ads->ds_data = buf_addr;
196
197 if (is_firstseg) {
198 ads->ds_ctl1 |= seglen | (is_lastseg ? 0 : AR_TxMore);
199 } else if (is_lastseg) {
200 ads->ds_ctl0 = 0;
201 ads->ds_ctl1 = seglen;
202 ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
203 ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
204 } else {
205 ads->ds_ctl0 = 0;
206 ads->ds_ctl1 = seglen | AR_TxMore;
207 ads->ds_ctl2 = 0;
208 ads->ds_ctl3 = 0;
209 }
210 ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
211 ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
212 ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
213 ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
214 ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
215}
216
217static int ar9002_hw_proc_txdesc(struct ath_hw *ah, void *ds,
218 struct ath_tx_status *ts)
219{
220 struct ar5416_desc *ads = AR5416DESC(ds);
221
222 if ((ads->ds_txstatus9 & AR_TxDone) == 0)
223 return -EINPROGRESS;
224
225 ts->ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
226 ts->ts_tstamp = ads->AR_SendTimestamp;
227 ts->ts_status = 0;
228 ts->ts_flags = 0;
229
230 if (ads->ds_txstatus1 & AR_FrmXmitOK)
231 ts->ts_status |= ATH9K_TX_ACKED;
232 if (ads->ds_txstatus1 & AR_ExcessiveRetries)
233 ts->ts_status |= ATH9K_TXERR_XRETRY;
234 if (ads->ds_txstatus1 & AR_Filtered)
235 ts->ts_status |= ATH9K_TXERR_FILT;
236 if (ads->ds_txstatus1 & AR_FIFOUnderrun) {
237 ts->ts_status |= ATH9K_TXERR_FIFO;
238 ath9k_hw_updatetxtriglevel(ah, true);
239 }
240 if (ads->ds_txstatus9 & AR_TxOpExceeded)
241 ts->ts_status |= ATH9K_TXERR_XTXOP;
242 if (ads->ds_txstatus1 & AR_TxTimerExpired)
243 ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
244
245 if (ads->ds_txstatus1 & AR_DescCfgErr)
246 ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
247 if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
248 ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
249 ath9k_hw_updatetxtriglevel(ah, true);
250 }
251 if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
252 ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
253 ath9k_hw_updatetxtriglevel(ah, true);
254 }
255 if (ads->ds_txstatus0 & AR_TxBaStatus) {
256 ts->ts_flags |= ATH9K_TX_BA;
257 ts->ba_low = ads->AR_BaBitmapLow;
258 ts->ba_high = ads->AR_BaBitmapHigh;
259 }
260
261 ts->ts_rateindex = MS(ads->ds_txstatus9, AR_FinalTxIdx);
262 switch (ts->ts_rateindex) {
263 case 0:
264 ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate0);
265 break;
266 case 1:
267 ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate1);
268 break;
269 case 2:
270 ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate2);
271 break;
272 case 3:
273 ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate3);
274 break;
275 }
276
277 ts->ts_rssi = MS(ads->ds_txstatus5, AR_TxRSSICombined);
278 ts->ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
279 ts->ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
280 ts->ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
281 ts->ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
282 ts->ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
283 ts->ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
284 ts->evm0 = ads->AR_TxEVM0;
285 ts->evm1 = ads->AR_TxEVM1;
286 ts->evm2 = ads->AR_TxEVM2;
287 ts->ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
288 ts->ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
289 ts->ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
290 ts->ts_antenna = 0;
291
292 return 0;
293}
294
295static void ar9002_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
296 u32 pktLen, enum ath9k_pkt_type type,
297 u32 txPower, u32 keyIx,
298 enum ath9k_key_type keyType, u32 flags)
299{
300 struct ar5416_desc *ads = AR5416DESC(ds);
301
302 txPower += ah->txpower_indexoffset;
303 if (txPower > 63)
304 txPower = 63;
305
306 ads->ds_ctl0 = (pktLen & AR_FrameLen)
307 | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
308 | SM(txPower, AR_XmitPower)
309 | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
310 | (flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
311 | (flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0)
312 | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0);
313
314 ads->ds_ctl1 =
315 (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
316 | SM(type, AR_FrameType)
317 | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
318 | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
319 | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
320
321 ads->ds_ctl6 = SM(keyType, AR_EncrType);
322
323 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) {
324 ads->ds_ctl8 = 0;
325 ads->ds_ctl9 = 0;
326 ads->ds_ctl10 = 0;
327 ads->ds_ctl11 = 0;
328 }
329}
330
331static void ar9002_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
332 void *lastds,
333 u32 durUpdateEn, u32 rtsctsRate,
334 u32 rtsctsDuration,
335 struct ath9k_11n_rate_series series[],
336 u32 nseries, u32 flags)
337{
338 struct ar5416_desc *ads = AR5416DESC(ds);
339 struct ar5416_desc *last_ads = AR5416DESC(lastds);
340 u32 ds_ctl0;
341
342 if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
343 ds_ctl0 = ads->ds_ctl0;
344
345 if (flags & ATH9K_TXDESC_RTSENA) {
346 ds_ctl0 &= ~AR_CTSEnable;
347 ds_ctl0 |= AR_RTSEnable;
348 } else {
349 ds_ctl0 &= ~AR_RTSEnable;
350 ds_ctl0 |= AR_CTSEnable;
351 }
352
353 ads->ds_ctl0 = ds_ctl0;
354 } else {
355 ads->ds_ctl0 =
356 (ads->ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
357 }
358
359 ads->ds_ctl2 = set11nTries(series, 0)
360 | set11nTries(series, 1)
361 | set11nTries(series, 2)
362 | set11nTries(series, 3)
363 | (durUpdateEn ? AR_DurUpdateEna : 0)
364 | SM(0, AR_BurstDur);
365
366 ads->ds_ctl3 = set11nRate(series, 0)
367 | set11nRate(series, 1)
368 | set11nRate(series, 2)
369 | set11nRate(series, 3);
370
371 ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
372 | set11nPktDurRTSCTS(series, 1);
373
374 ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
375 | set11nPktDurRTSCTS(series, 3);
376
377 ads->ds_ctl7 = set11nRateFlags(series, 0)
378 | set11nRateFlags(series, 1)
379 | set11nRateFlags(series, 2)
380 | set11nRateFlags(series, 3)
381 | SM(rtsctsRate, AR_RTSCTSRate);
382 last_ads->ds_ctl2 = ads->ds_ctl2;
383 last_ads->ds_ctl3 = ads->ds_ctl3;
384}
385
386static void ar9002_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
387 u32 aggrLen)
388{
389 struct ar5416_desc *ads = AR5416DESC(ds);
390
391 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
392 ads->ds_ctl6 &= ~AR_AggrLen;
393 ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen);
394}
395
396static void ar9002_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
397 u32 numDelims)
398{
399 struct ar5416_desc *ads = AR5416DESC(ds);
400 unsigned int ctl6;
401
402 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
403
404 ctl6 = ads->ds_ctl6;
405 ctl6 &= ~AR_PadDelim;
406 ctl6 |= SM(numDelims, AR_PadDelim);
407 ads->ds_ctl6 = ctl6;
408}
409
410static void ar9002_hw_set11n_aggr_last(struct ath_hw *ah, void *ds)
411{
412 struct ar5416_desc *ads = AR5416DESC(ds);
413
414 ads->ds_ctl1 |= AR_IsAggr;
415 ads->ds_ctl1 &= ~AR_MoreAggr;
416 ads->ds_ctl6 &= ~AR_PadDelim;
417}
418
419static void ar9002_hw_clr11n_aggr(struct ath_hw *ah, void *ds)
420{
421 struct ar5416_desc *ads = AR5416DESC(ds);
422
423 ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
424}
425
426static void ar9002_hw_set11n_burstduration(struct ath_hw *ah, void *ds,
427 u32 burstDuration)
428{
429 struct ar5416_desc *ads = AR5416DESC(ds);
430
431 ads->ds_ctl2 &= ~AR_BurstDur;
432 ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
433}
434
435static void ar9002_hw_set11n_virtualmorefrag(struct ath_hw *ah, void *ds,
436 u32 vmf)
437{
438 struct ar5416_desc *ads = AR5416DESC(ds);
439
440 if (vmf)
441 ads->ds_ctl0 |= AR_VirtMoreFrag;
442 else
443 ads->ds_ctl0 &= ~AR_VirtMoreFrag;
444}
445
446void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
447 u32 size, u32 flags)
448{
449 struct ar5416_desc *ads = AR5416DESC(ds);
450 struct ath9k_hw_capabilities *pCap = &ah->caps;
451
452 ads->ds_ctl1 = size & AR_BufLen;
453 if (flags & ATH9K_RXDESC_INTREQ)
454 ads->ds_ctl1 |= AR_RxIntrReq;
455
456 ads->ds_rxstatus8 &= ~AR_RxDone;
457 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
458 memset(&(ads->u), 0, sizeof(ads->u));
459}
460EXPORT_SYMBOL(ath9k_hw_setuprxdesc);
461
462void ar9002_hw_attach_mac_ops(struct ath_hw *ah)
463{
464 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
465
466 ops->rx_enable = ar9002_hw_rx_enable;
467 ops->set_desc_link = ar9002_hw_set_desc_link;
468 ops->get_desc_link = ar9002_hw_get_desc_link;
469 ops->get_isr = ar9002_hw_get_isr;
470 ops->fill_txdesc = ar9002_hw_fill_txdesc;
471 ops->proc_txdesc = ar9002_hw_proc_txdesc;
472 ops->set11n_txdesc = ar9002_hw_set11n_txdesc;
473 ops->set11n_ratescenario = ar9002_hw_set11n_ratescenario;
474 ops->set11n_aggr_first = ar9002_hw_set11n_aggr_first;
475 ops->set11n_aggr_middle = ar9002_hw_set11n_aggr_middle;
476 ops->set11n_aggr_last = ar9002_hw_set11n_aggr_last;
477 ops->clr11n_aggr = ar9002_hw_clr11n_aggr;
478 ops->set11n_burstduration = ar9002_hw_set11n_burstduration;
479 ops->set11n_virtualmorefrag = ar9002_hw_set11n_virtualmorefrag;
480}
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_phy.c b/drivers/net/wireless/ath/ath9k/ar9002_phy.c
new file mode 100644
index 000000000000..ed314e89bfe1
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/ar9002_phy.c
@@ -0,0 +1,535 @@
1/*
2 * Copyright (c) 2008-2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17/**
18 * DOC: Programming Atheros 802.11n analog front end radios
19 *
20 * AR5416 MAC based PCI devices and AR518 MAC based PCI-Express
21 * devices have either an external AR2133 analog front end radio for single
22 * band 2.4 GHz communication or an AR5133 analog front end radio for dual
23 * band 2.4 GHz / 5 GHz communication.
24 *
25 * All devices after the AR5416 and AR5418 family starting with the AR9280
26 * have their analog front radios, MAC/BB and host PCIe/USB interface embedded
27 * into a single-chip and require less programming.
28 *
29 * The following single-chips exist with a respective embedded radio:
30 *
31 * AR9280 - 11n dual-band 2x2 MIMO for PCIe
32 * AR9281 - 11n single-band 1x2 MIMO for PCIe
33 * AR9285 - 11n single-band 1x1 for PCIe
34 * AR9287 - 11n single-band 2x2 MIMO for PCIe
35 *
36 * AR9220 - 11n dual-band 2x2 MIMO for PCI
37 * AR9223 - 11n single-band 2x2 MIMO for PCI
38 *
39 * AR9287 - 11n single-band 1x1 MIMO for USB
40 */
41
42#include "hw.h"
43#include "ar9002_phy.h"
44
45/**
46 * ar9002_hw_set_channel - set channel on single-chip device
47 * @ah: atheros hardware structure
48 * @chan:
49 *
50 * This is the function to change channel on single-chip devices, that is
51 * all devices after ar9280.
52 *
53 * This function takes the channel value in MHz and sets
54 * hardware channel value. Assumes writes have been enabled to analog bus.
55 *
56 * Actual Expression,
57 *
58 * For 2GHz channel,
59 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
60 * (freq_ref = 40MHz)
61 *
62 * For 5GHz channel,
63 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
64 * (freq_ref = 40MHz/(24>>amodeRefSel))
65 */
66static int ar9002_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
67{
68 u16 bMode, fracMode, aModeRefSel = 0;
69 u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
70 struct chan_centers centers;
71 u32 refDivA = 24;
72
73 ath9k_hw_get_channel_centers(ah, chan, &centers);
74 freq = centers.synth_center;
75
76 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL);
77 reg32 &= 0xc0000000;
78
79 if (freq < 4800) { /* 2 GHz, fractional mode */
80 u32 txctl;
81 int regWrites = 0;
82
83 bMode = 1;
84 fracMode = 1;
85 aModeRefSel = 0;
86 channelSel = CHANSEL_2G(freq);
87
88 if (AR_SREV_9287_11_OR_LATER(ah)) {
89 if (freq == 2484) {
90 /* Enable channel spreading for channel 14 */
91 REG_WRITE_ARRAY(&ah->iniCckfirJapan2484,
92 1, regWrites);
93 } else {
94 REG_WRITE_ARRAY(&ah->iniCckfirNormal,
95 1, regWrites);
96 }
97 } else {
98 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
99 if (freq == 2484) {
100 /* Enable channel spreading for channel 14 */
101 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
102 txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
103 } else {
104 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
105 txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
106 }
107 }
108 } else {
109 bMode = 0;
110 fracMode = 0;
111
112 switch (ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) {
113 case 0:
114 if ((freq % 20) == 0)
115 aModeRefSel = 3;
116 else if ((freq % 10) == 0)
117 aModeRefSel = 2;
118 if (aModeRefSel)
119 break;
120 case 1:
121 default:
122 aModeRefSel = 0;
123 /*
124 * Enable 2G (fractional) mode for channels
125 * which are 5MHz spaced.
126 */
127 fracMode = 1;
128 refDivA = 1;
129 channelSel = CHANSEL_5G(freq);
130
131 /* RefDivA setting */
132 REG_RMW_FIELD(ah, AR_AN_SYNTH9,
133 AR_AN_SYNTH9_REFDIVA, refDivA);
134
135 }
136
137 if (!fracMode) {
138 ndiv = (freq * (refDivA >> aModeRefSel)) / 60;
139 channelSel = ndiv & 0x1ff;
140 channelFrac = (ndiv & 0xfffffe00) * 2;
141 channelSel = (channelSel << 17) | channelFrac;
142 }
143 }
144
145 reg32 = reg32 |
146 (bMode << 29) |
147 (fracMode << 28) | (aModeRefSel << 26) | (channelSel);
148
149 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
150
151 ah->curchan = chan;
152 ah->curchan_rad_index = -1;
153
154 return 0;
155}
156
157/**
158 * ar9002_hw_spur_mitigate - convert baseband spur frequency
159 * @ah: atheros hardware structure
160 * @chan:
161 *
162 * For single-chip solutions. Converts to baseband spur frequency given the
163 * input channel frequency and compute register settings below.
164 */
165static void ar9002_hw_spur_mitigate(struct ath_hw *ah,
166 struct ath9k_channel *chan)
167{
168 int bb_spur = AR_NO_SPUR;
169 int freq;
170 int bin, cur_bin;
171 int bb_spur_off, spur_subchannel_sd;
172 int spur_freq_sd;
173 int spur_delta_phase;
174 int denominator;
175 int upper, lower, cur_vit_mask;
176 int tmp, newVal;
177 int i;
178 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
179 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
180 };
181 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
182 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
183 };
184 int inc[4] = { 0, 100, 0, 0 };
185 struct chan_centers centers;
186
187 int8_t mask_m[123];
188 int8_t mask_p[123];
189 int8_t mask_amt;
190 int tmp_mask;
191 int cur_bb_spur;
192 bool is2GHz = IS_CHAN_2GHZ(chan);
193
194 memset(&mask_m, 0, sizeof(int8_t) * 123);
195 memset(&mask_p, 0, sizeof(int8_t) * 123);
196
197 ath9k_hw_get_channel_centers(ah, chan, &centers);
198 freq = centers.synth_center;
199
200 ah->config.spurmode = SPUR_ENABLE_EEPROM;
201 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
202 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
203
204 if (is2GHz)
205 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
206 else
207 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
208
209 if (AR_NO_SPUR == cur_bb_spur)
210 break;
211 cur_bb_spur = cur_bb_spur - freq;
212
213 if (IS_CHAN_HT40(chan)) {
214 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
215 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
216 bb_spur = cur_bb_spur;
217 break;
218 }
219 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
220 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
221 bb_spur = cur_bb_spur;
222 break;
223 }
224 }
225
226 if (AR_NO_SPUR == bb_spur) {
227 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
228 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
229 return;
230 } else {
231 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
232 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
233 }
234
235 bin = bb_spur * 320;
236
237 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
238
239 ENABLE_REGWRITE_BUFFER(ah);
240
241 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
242 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
243 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
244 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
245 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
246
247 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
248 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
249 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
250 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
251 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
252 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
253
254 if (IS_CHAN_HT40(chan)) {
255 if (bb_spur < 0) {
256 spur_subchannel_sd = 1;
257 bb_spur_off = bb_spur + 10;
258 } else {
259 spur_subchannel_sd = 0;
260 bb_spur_off = bb_spur - 10;
261 }
262 } else {
263 spur_subchannel_sd = 0;
264 bb_spur_off = bb_spur;
265 }
266
267 if (IS_CHAN_HT40(chan))
268 spur_delta_phase =
269 ((bb_spur * 262144) /
270 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
271 else
272 spur_delta_phase =
273 ((bb_spur * 524288) /
274 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
275
276 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
277 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
278
279 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
280 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
281 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
282 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
283
284 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
285 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
286
287 cur_bin = -6000;
288 upper = bin + 100;
289 lower = bin - 100;
290
291 for (i = 0; i < 4; i++) {
292 int pilot_mask = 0;
293 int chan_mask = 0;
294 int bp = 0;
295 for (bp = 0; bp < 30; bp++) {
296 if ((cur_bin > lower) && (cur_bin < upper)) {
297 pilot_mask = pilot_mask | 0x1 << bp;
298 chan_mask = chan_mask | 0x1 << bp;
299 }
300 cur_bin += 100;
301 }
302 cur_bin += inc[i];
303 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
304 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
305 }
306
307 cur_vit_mask = 6100;
308 upper = bin + 120;
309 lower = bin - 120;
310
311 for (i = 0; i < 123; i++) {
312 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
313
314 /* workaround for gcc bug #37014 */
315 volatile int tmp_v = abs(cur_vit_mask - bin);
316
317 if (tmp_v < 75)
318 mask_amt = 1;
319 else
320 mask_amt = 0;
321 if (cur_vit_mask < 0)
322 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
323 else
324 mask_p[cur_vit_mask / 100] = mask_amt;
325 }
326 cur_vit_mask -= 100;
327 }
328
329 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
330 | (mask_m[48] << 26) | (mask_m[49] << 24)
331 | (mask_m[50] << 22) | (mask_m[51] << 20)
332 | (mask_m[52] << 18) | (mask_m[53] << 16)
333 | (mask_m[54] << 14) | (mask_m[55] << 12)
334 | (mask_m[56] << 10) | (mask_m[57] << 8)
335 | (mask_m[58] << 6) | (mask_m[59] << 4)
336 | (mask_m[60] << 2) | (mask_m[61] << 0);
337 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
338 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
339
340 tmp_mask = (mask_m[31] << 28)
341 | (mask_m[32] << 26) | (mask_m[33] << 24)
342 | (mask_m[34] << 22) | (mask_m[35] << 20)
343 | (mask_m[36] << 18) | (mask_m[37] << 16)
344 | (mask_m[48] << 14) | (mask_m[39] << 12)
345 | (mask_m[40] << 10) | (mask_m[41] << 8)
346 | (mask_m[42] << 6) | (mask_m[43] << 4)
347 | (mask_m[44] << 2) | (mask_m[45] << 0);
348 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
349 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
350
351 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
352 | (mask_m[18] << 26) | (mask_m[18] << 24)
353 | (mask_m[20] << 22) | (mask_m[20] << 20)
354 | (mask_m[22] << 18) | (mask_m[22] << 16)
355 | (mask_m[24] << 14) | (mask_m[24] << 12)
356 | (mask_m[25] << 10) | (mask_m[26] << 8)
357 | (mask_m[27] << 6) | (mask_m[28] << 4)
358 | (mask_m[29] << 2) | (mask_m[30] << 0);
359 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
360 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
361
362 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
363 | (mask_m[2] << 26) | (mask_m[3] << 24)
364 | (mask_m[4] << 22) | (mask_m[5] << 20)
365 | (mask_m[6] << 18) | (mask_m[7] << 16)
366 | (mask_m[8] << 14) | (mask_m[9] << 12)
367 | (mask_m[10] << 10) | (mask_m[11] << 8)
368 | (mask_m[12] << 6) | (mask_m[13] << 4)
369 | (mask_m[14] << 2) | (mask_m[15] << 0);
370 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
371 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
372
373 tmp_mask = (mask_p[15] << 28)
374 | (mask_p[14] << 26) | (mask_p[13] << 24)
375 | (mask_p[12] << 22) | (mask_p[11] << 20)
376 | (mask_p[10] << 18) | (mask_p[9] << 16)
377 | (mask_p[8] << 14) | (mask_p[7] << 12)
378 | (mask_p[6] << 10) | (mask_p[5] << 8)
379 | (mask_p[4] << 6) | (mask_p[3] << 4)
380 | (mask_p[2] << 2) | (mask_p[1] << 0);
381 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
382 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
383
384 tmp_mask = (mask_p[30] << 28)
385 | (mask_p[29] << 26) | (mask_p[28] << 24)
386 | (mask_p[27] << 22) | (mask_p[26] << 20)
387 | (mask_p[25] << 18) | (mask_p[24] << 16)
388 | (mask_p[23] << 14) | (mask_p[22] << 12)
389 | (mask_p[21] << 10) | (mask_p[20] << 8)
390 | (mask_p[19] << 6) | (mask_p[18] << 4)
391 | (mask_p[17] << 2) | (mask_p[16] << 0);
392 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
393 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
394
395 tmp_mask = (mask_p[45] << 28)
396 | (mask_p[44] << 26) | (mask_p[43] << 24)
397 | (mask_p[42] << 22) | (mask_p[41] << 20)
398 | (mask_p[40] << 18) | (mask_p[39] << 16)
399 | (mask_p[38] << 14) | (mask_p[37] << 12)
400 | (mask_p[36] << 10) | (mask_p[35] << 8)
401 | (mask_p[34] << 6) | (mask_p[33] << 4)
402 | (mask_p[32] << 2) | (mask_p[31] << 0);
403 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
404 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
405
406 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
407 | (mask_p[59] << 26) | (mask_p[58] << 24)
408 | (mask_p[57] << 22) | (mask_p[56] << 20)
409 | (mask_p[55] << 18) | (mask_p[54] << 16)
410 | (mask_p[53] << 14) | (mask_p[52] << 12)
411 | (mask_p[51] << 10) | (mask_p[50] << 8)
412 | (mask_p[49] << 6) | (mask_p[48] << 4)
413 | (mask_p[47] << 2) | (mask_p[46] << 0);
414 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
415 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
416
417 REGWRITE_BUFFER_FLUSH(ah);
418 DISABLE_REGWRITE_BUFFER(ah);
419}
420
421static void ar9002_olc_init(struct ath_hw *ah)
422{
423 u32 i;
424
425 if (!OLC_FOR_AR9280_20_LATER)
426 return;
427
428 if (OLC_FOR_AR9287_10_LATER) {
429 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
430 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
431 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
432 AR9287_AN_TXPC0_TXPCMODE,
433 AR9287_AN_TXPC0_TXPCMODE_S,
434 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
435 udelay(100);
436 } else {
437 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
438 ah->originalGain[i] =
439 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
440 AR_PHY_TX_GAIN);
441 ah->PDADCdelta = 0;
442 }
443}
444
445static u32 ar9002_hw_compute_pll_control(struct ath_hw *ah,
446 struct ath9k_channel *chan)
447{
448 u32 pll;
449
450 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
451
452 if (chan && IS_CHAN_HALF_RATE(chan))
453 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
454 else if (chan && IS_CHAN_QUARTER_RATE(chan))
455 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
456
457 if (chan && IS_CHAN_5GHZ(chan)) {
458 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
459 pll = 0x142c;
460 else if (AR_SREV_9280_20(ah))
461 pll = 0x2850;
462 else
463 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
464 } else {
465 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
466 }
467
468 return pll;
469}
470
471static void ar9002_hw_do_getnf(struct ath_hw *ah,
472 int16_t nfarray[NUM_NF_READINGS])
473{
474 struct ath_common *common = ath9k_hw_common(ah);
475 int16_t nf;
476
477 nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
478
479 if (nf & 0x100)
480 nf = 0 - ((nf ^ 0x1ff) + 1);
481 ath_print(common, ATH_DBG_CALIBRATE,
482 "NF calibrated [ctl] [chain 0] is %d\n", nf);
483
484 if (AR_SREV_9271(ah) && (nf >= -114))
485 nf = -116;
486
487 nfarray[0] = nf;
488
489 if (!AR_SREV_9285(ah) && !AR_SREV_9271(ah)) {
490 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
491 AR9280_PHY_CH1_MINCCA_PWR);
492
493 if (nf & 0x100)
494 nf = 0 - ((nf ^ 0x1ff) + 1);
495 ath_print(common, ATH_DBG_CALIBRATE,
496 "NF calibrated [ctl] [chain 1] is %d\n", nf);
497 nfarray[1] = nf;
498 }
499
500 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR);
501 if (nf & 0x100)
502 nf = 0 - ((nf ^ 0x1ff) + 1);
503 ath_print(common, ATH_DBG_CALIBRATE,
504 "NF calibrated [ext] [chain 0] is %d\n", nf);
505
506 if (AR_SREV_9271(ah) && (nf >= -114))
507 nf = -116;
508
509 nfarray[3] = nf;
510
511 if (!AR_SREV_9285(ah) && !AR_SREV_9271(ah)) {
512 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
513 AR9280_PHY_CH1_EXT_MINCCA_PWR);
514
515 if (nf & 0x100)
516 nf = 0 - ((nf ^ 0x1ff) + 1);
517 ath_print(common, ATH_DBG_CALIBRATE,
518 "NF calibrated [ext] [chain 1] is %d\n", nf);
519 nfarray[4] = nf;
520 }
521}
522
523void ar9002_hw_attach_phy_ops(struct ath_hw *ah)
524{
525 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
526
527 priv_ops->set_rf_regs = NULL;
528 priv_ops->rf_alloc_ext_banks = NULL;
529 priv_ops->rf_free_ext_banks = NULL;
530 priv_ops->rf_set_freq = ar9002_hw_set_channel;
531 priv_ops->spur_mitigate_freq = ar9002_hw_spur_mitigate;
532 priv_ops->olc_init = ar9002_olc_init;
533 priv_ops->compute_pll_control = ar9002_hw_compute_pll_control;
534 priv_ops->do_getnf = ar9002_hw_do_getnf;
535}
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_phy.h b/drivers/net/wireless/ath/ath9k/ar9002_phy.h
new file mode 100644
index 000000000000..81bf6e5840e1
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/ar9002_phy.h
@@ -0,0 +1,572 @@
1/*
2 * Copyright (c) 2008-2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16#ifndef AR9002_PHY_H
17#define AR9002_PHY_H
18
19#define AR_PHY_TEST 0x9800
20#define PHY_AGC_CLR 0x10000000
21#define RFSILENT_BB 0x00002000
22
23#define AR_PHY_TURBO 0x9804
24#define AR_PHY_FC_TURBO_MODE 0x00000001
25#define AR_PHY_FC_TURBO_SHORT 0x00000002
26#define AR_PHY_FC_DYN2040_EN 0x00000004
27#define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008
28#define AR_PHY_FC_DYN2040_PRI_CH 0x00000010
29/* For 25 MHz channel spacing -- not used but supported by hw */
30#define AR_PHY_FC_DYN2040_EXT_CH 0x00000020
31#define AR_PHY_FC_HT_EN 0x00000040
32#define AR_PHY_FC_SHORT_GI_40 0x00000080
33#define AR_PHY_FC_WALSH 0x00000100
34#define AR_PHY_FC_SINGLE_HT_LTF1 0x00000200
35#define AR_PHY_FC_ENABLE_DAC_FIFO 0x00000800
36
37#define AR_PHY_TEST2 0x9808
38
39#define AR_PHY_TIMING2 0x9810
40#define AR_PHY_TIMING3 0x9814
41#define AR_PHY_TIMING3_DSC_MAN 0xFFFE0000
42#define AR_PHY_TIMING3_DSC_MAN_S 17
43#define AR_PHY_TIMING3_DSC_EXP 0x0001E000
44#define AR_PHY_TIMING3_DSC_EXP_S 13
45
46#define AR_PHY_CHIP_ID_REV_0 0x80
47#define AR_PHY_CHIP_ID_REV_1 0x81
48#define AR_PHY_CHIP_ID_9160_REV_0 0xb0
49
50#define AR_PHY_ACTIVE 0x981C
51#define AR_PHY_ACTIVE_EN 0x00000001
52#define AR_PHY_ACTIVE_DIS 0x00000000
53
54#define AR_PHY_RF_CTL2 0x9824
55#define AR_PHY_TX_END_DATA_START 0x000000FF
56#define AR_PHY_TX_END_DATA_START_S 0
57#define AR_PHY_TX_END_PA_ON 0x0000FF00
58#define AR_PHY_TX_END_PA_ON_S 8
59
60#define AR_PHY_RF_CTL3 0x9828
61#define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000
62#define AR_PHY_TX_END_TO_A2_RX_ON_S 16
63
64#define AR_PHY_ADC_CTL 0x982C
65#define AR_PHY_ADC_CTL_OFF_INBUFGAIN 0x00000003
66#define AR_PHY_ADC_CTL_OFF_INBUFGAIN_S 0
67#define AR_PHY_ADC_CTL_OFF_PWDDAC 0x00002000
68#define AR_PHY_ADC_CTL_OFF_PWDBANDGAP 0x00004000
69#define AR_PHY_ADC_CTL_OFF_PWDADC 0x00008000
70#define AR_PHY_ADC_CTL_ON_INBUFGAIN 0x00030000
71#define AR_PHY_ADC_CTL_ON_INBUFGAIN_S 16
72
73#define AR_PHY_ADC_SERIAL_CTL 0x9830
74#define AR_PHY_SEL_INTERNAL_ADDAC 0x00000000
75#define AR_PHY_SEL_EXTERNAL_RADIO 0x00000001
76
77#define AR_PHY_RF_CTL4 0x9834
78#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF 0xFF000000
79#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_S 24
80#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF 0x00FF0000
81#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_S 16
82#define AR_PHY_RF_CTL4_FRAME_XPAB_ON 0x0000FF00
83#define AR_PHY_RF_CTL4_FRAME_XPAB_ON_S 8
84#define AR_PHY_RF_CTL4_FRAME_XPAA_ON 0x000000FF
85#define AR_PHY_RF_CTL4_FRAME_XPAA_ON_S 0
86
87#define AR_PHY_TSTDAC_CONST 0x983c
88
89#define AR_PHY_SETTLING 0x9844
90#define AR_PHY_SETTLING_SWITCH 0x00003F80
91#define AR_PHY_SETTLING_SWITCH_S 7
92
93#define AR_PHY_RXGAIN 0x9848
94#define AR_PHY_RXGAIN_TXRX_ATTEN 0x0003F000
95#define AR_PHY_RXGAIN_TXRX_ATTEN_S 12
96#define AR_PHY_RXGAIN_TXRX_RF_MAX 0x007C0000
97#define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18
98#define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80
99#define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7
100#define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000
101#define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14
102
103#define AR_PHY_DESIRED_SZ 0x9850
104#define AR_PHY_DESIRED_SZ_ADC 0x000000FF
105#define AR_PHY_DESIRED_SZ_ADC_S 0
106#define AR_PHY_DESIRED_SZ_PGA 0x0000FF00
107#define AR_PHY_DESIRED_SZ_PGA_S 8
108#define AR_PHY_DESIRED_SZ_TOT_DES 0x0FF00000
109#define AR_PHY_DESIRED_SZ_TOT_DES_S 20
110
111#define AR_PHY_FIND_SIG 0x9858
112#define AR_PHY_FIND_SIG_FIRSTEP 0x0003F000
113#define AR_PHY_FIND_SIG_FIRSTEP_S 12
114#define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000
115#define AR_PHY_FIND_SIG_FIRPWR_S 18
116
117#define AR_PHY_AGC_CTL1 0x985C
118#define AR_PHY_AGC_CTL1_COARSE_LOW 0x00007F80
119#define AR_PHY_AGC_CTL1_COARSE_LOW_S 7
120#define AR_PHY_AGC_CTL1_COARSE_HIGH 0x003F8000
121#define AR_PHY_AGC_CTL1_COARSE_HIGH_S 15
122
123#define AR_PHY_CCA 0x9864
124#define AR_PHY_MINCCA_PWR 0x0FF80000
125#define AR_PHY_MINCCA_PWR_S 19
126#define AR_PHY_CCA_THRESH62 0x0007F000
127#define AR_PHY_CCA_THRESH62_S 12
128#define AR9280_PHY_MINCCA_PWR 0x1FF00000
129#define AR9280_PHY_MINCCA_PWR_S 20
130#define AR9280_PHY_CCA_THRESH62 0x000FF000
131#define AR9280_PHY_CCA_THRESH62_S 12
132
133#define AR_PHY_SFCORR_LOW 0x986C
134#define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001
135#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003F00
136#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8
137#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001FC000
138#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14
139#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0FE00000
140#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21
141
142#define AR_PHY_SFCORR 0x9868
143#define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F
144#define AR_PHY_SFCORR_M2COUNT_THR_S 0
145#define AR_PHY_SFCORR_M1_THRESH 0x00FE0000
146#define AR_PHY_SFCORR_M1_THRESH_S 17
147#define AR_PHY_SFCORR_M2_THRESH 0x7F000000
148#define AR_PHY_SFCORR_M2_THRESH_S 24
149
150#define AR_PHY_SLEEP_CTR_CONTROL 0x9870
151#define AR_PHY_SLEEP_CTR_LIMIT 0x9874
152#define AR_PHY_SYNTH_CONTROL 0x9874
153#define AR_PHY_SLEEP_SCAL 0x9878
154
155#define AR_PHY_PLL_CTL 0x987c
156#define AR_PHY_PLL_CTL_40 0xaa
157#define AR_PHY_PLL_CTL_40_5413 0x04
158#define AR_PHY_PLL_CTL_44 0xab
159#define AR_PHY_PLL_CTL_44_2133 0xeb
160#define AR_PHY_PLL_CTL_40_2133 0xea
161
162#define AR_PHY_SPECTRAL_SCAN 0x9910 /* AR9280 spectral scan configuration register */
163#define AR_PHY_SPECTRAL_SCAN_ENABLE 0x1
164#define AR_PHY_SPECTRAL_SCAN_ENA 0x00000001 /* Enable spectral scan, reg 68, bit 0 */
165#define AR_PHY_SPECTRAL_SCAN_ENA_S 0 /* Enable spectral scan, reg 68, bit 0 */
166#define AR_PHY_SPECTRAL_SCAN_ACTIVE 0x00000002 /* Activate spectral scan reg 68, bit 1*/
167#define AR_PHY_SPECTRAL_SCAN_ACTIVE_S 1 /* Activate spectral scan reg 68, bit 1*/
168#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD 0x000000F0 /* Interval for FFT reports, reg 68, bits 4-7*/
169#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S 4
170#define AR_PHY_SPECTRAL_SCAN_PERIOD 0x0000FF00 /* Interval for FFT reports, reg 68, bits 8-15*/
171#define AR_PHY_SPECTRAL_SCAN_PERIOD_S 8
172#define AR_PHY_SPECTRAL_SCAN_COUNT 0x00FF0000 /* Number of reports, reg 68, bits 16-23*/
173#define AR_PHY_SPECTRAL_SCAN_COUNT_S 16
174#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x01000000 /* Short repeat, reg 68, bit 24*/
175#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 24 /* Short repeat, reg 68, bit 24*/
176
177#define AR_PHY_RX_DELAY 0x9914
178#define AR_PHY_SEARCH_START_DELAY 0x9918
179#define AR_PHY_RX_DELAY_DELAY 0x00003FFF
180
181#define AR_PHY_TIMING_CTRL4(_i) (0x9920 + ((_i) << 12))
182#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF 0x01F
183#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S 0
184#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF 0x7E0
185#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S 5
186#define AR_PHY_TIMING_CTRL4_IQCORR_ENABLE 0x800
187#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX 0xF000
188#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S 12
189#define AR_PHY_TIMING_CTRL4_DO_CAL 0x10000
190
191#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI 0x80000000
192#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER 0x40000000
193#define AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK 0x20000000
194#define AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK 0x10000000
195
196#define AR_PHY_TIMING5 0x9924
197#define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE
198#define AR_PHY_TIMING5_CYCPWR_THR1_S 1
199
200#define AR_PHY_POWER_TX_RATE1 0x9934
201#define AR_PHY_POWER_TX_RATE2 0x9938
202#define AR_PHY_POWER_TX_RATE_MAX 0x993c
203#define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040
204
205#define AR_PHY_FRAME_CTL 0x9944
206#define AR_PHY_FRAME_CTL_TX_CLIP 0x00000038
207#define AR_PHY_FRAME_CTL_TX_CLIP_S 3
208
209#define AR_PHY_TXPWRADJ 0x994C
210#define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA 0x00000FC0
211#define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA_S 6
212#define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX 0x00FC0000
213#define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX_S 18
214
215#define AR_PHY_RADAR_EXT 0x9940
216#define AR_PHY_RADAR_EXT_ENA 0x00004000
217
218#define AR_PHY_RADAR_0 0x9954
219#define AR_PHY_RADAR_0_ENA 0x00000001
220#define AR_PHY_RADAR_0_FFT_ENA 0x80000000
221#define AR_PHY_RADAR_0_INBAND 0x0000003e
222#define AR_PHY_RADAR_0_INBAND_S 1
223#define AR_PHY_RADAR_0_PRSSI 0x00000FC0
224#define AR_PHY_RADAR_0_PRSSI_S 6
225#define AR_PHY_RADAR_0_HEIGHT 0x0003F000
226#define AR_PHY_RADAR_0_HEIGHT_S 12
227#define AR_PHY_RADAR_0_RRSSI 0x00FC0000
228#define AR_PHY_RADAR_0_RRSSI_S 18
229#define AR_PHY_RADAR_0_FIRPWR 0x7F000000
230#define AR_PHY_RADAR_0_FIRPWR_S 24
231
232#define AR_PHY_RADAR_1 0x9958
233#define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000
234#define AR_PHY_RADAR_1_USE_FIR128 0x00400000
235#define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000
236#define AR_PHY_RADAR_1_RELPWR_THRESH_S 16
237#define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000
238#define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000
239#define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000
240#define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00
241#define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8
242#define AR_PHY_RADAR_1_MAXLEN 0x000000FF
243#define AR_PHY_RADAR_1_MAXLEN_S 0
244
245#define AR_PHY_SWITCH_CHAIN_0 0x9960
246#define AR_PHY_SWITCH_COM 0x9964
247
248#define AR_PHY_SIGMA_DELTA 0x996C
249#define AR_PHY_SIGMA_DELTA_ADC_SEL 0x00000003
250#define AR_PHY_SIGMA_DELTA_ADC_SEL_S 0
251#define AR_PHY_SIGMA_DELTA_FILT2 0x000000F8
252#define AR_PHY_SIGMA_DELTA_FILT2_S 3
253#define AR_PHY_SIGMA_DELTA_FILT1 0x00001F00
254#define AR_PHY_SIGMA_DELTA_FILT1_S 8
255#define AR_PHY_SIGMA_DELTA_ADC_CLIP 0x01FFE000
256#define AR_PHY_SIGMA_DELTA_ADC_CLIP_S 13
257
258#define AR_PHY_RESTART 0x9970
259#define AR_PHY_RESTART_DIV_GC 0x001C0000
260#define AR_PHY_RESTART_DIV_GC_S 18
261
262#define AR_PHY_RFBUS_REQ 0x997C
263#define AR_PHY_RFBUS_REQ_EN 0x00000001
264
265#define AR_PHY_TIMING7 0x9980
266#define AR_PHY_TIMING8 0x9984
267#define AR_PHY_TIMING8_PILOT_MASK_2 0x000FFFFF
268#define AR_PHY_TIMING8_PILOT_MASK_2_S 0
269
270#define AR_PHY_BIN_MASK2_1 0x9988
271#define AR_PHY_BIN_MASK2_2 0x998c
272#define AR_PHY_BIN_MASK2_3 0x9990
273#define AR_PHY_BIN_MASK2_4 0x9994
274
275#define AR_PHY_BIN_MASK_1 0x9900
276#define AR_PHY_BIN_MASK_2 0x9904
277#define AR_PHY_BIN_MASK_3 0x9908
278
279#define AR_PHY_MASK_CTL 0x990c
280
281#define AR_PHY_BIN_MASK2_4_MASK_4 0x00003FFF
282#define AR_PHY_BIN_MASK2_4_MASK_4_S 0
283
284#define AR_PHY_TIMING9 0x9998
285#define AR_PHY_TIMING10 0x999c
286#define AR_PHY_TIMING10_PILOT_MASK_2 0x000FFFFF
287#define AR_PHY_TIMING10_PILOT_MASK_2_S 0
288
289#define AR_PHY_TIMING11 0x99a0
290#define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF
291#define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
292#define AR_PHY_TIMING11_USE_SPUR_IN_AGC 0x40000000
293#define AR_PHY_TIMING11_USE_SPUR_IN_SELFCOR 0x80000000
294
295#define AR_PHY_RX_CHAINMASK 0x99a4
296#define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (0x99b4 + ((_i) << 12))
297#define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000
298#define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000
299
300#define AR_PHY_MULTICHAIN_GAIN_CTL 0x99ac
301#define AR_PHY_9285_ANT_DIV_CTL_ALL 0x7f000000
302#define AR_PHY_9285_ANT_DIV_CTL 0x01000000
303#define AR_PHY_9285_ANT_DIV_CTL_S 24
304#define AR_PHY_9285_ANT_DIV_ALT_LNACONF 0x06000000
305#define AR_PHY_9285_ANT_DIV_ALT_LNACONF_S 25
306#define AR_PHY_9285_ANT_DIV_MAIN_LNACONF 0x18000000
307#define AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S 27
308#define AR_PHY_9285_ANT_DIV_ALT_GAINTB 0x20000000
309#define AR_PHY_9285_ANT_DIV_ALT_GAINTB_S 29
310#define AR_PHY_9285_ANT_DIV_MAIN_GAINTB 0x40000000
311#define AR_PHY_9285_ANT_DIV_MAIN_GAINTB_S 30
312#define AR_PHY_9285_ANT_DIV_LNA1 2
313#define AR_PHY_9285_ANT_DIV_LNA2 1
314#define AR_PHY_9285_ANT_DIV_LNA1_PLUS_LNA2 3
315#define AR_PHY_9285_ANT_DIV_LNA1_MINUS_LNA2 0
316#define AR_PHY_9285_ANT_DIV_GAINTB_0 0
317#define AR_PHY_9285_ANT_DIV_GAINTB_1 1
318
319#define AR_PHY_EXT_CCA0 0x99b8
320#define AR_PHY_EXT_CCA0_THRESH62 0x000000FF
321#define AR_PHY_EXT_CCA0_THRESH62_S 0
322
323#define AR_PHY_EXT_CCA 0x99bc
324#define AR_PHY_EXT_CCA_CYCPWR_THR1 0x0000FE00
325#define AR_PHY_EXT_CCA_CYCPWR_THR1_S 9
326#define AR_PHY_EXT_CCA_THRESH62 0x007F0000
327#define AR_PHY_EXT_CCA_THRESH62_S 16
328#define AR_PHY_EXT_MINCCA_PWR 0xFF800000
329#define AR_PHY_EXT_MINCCA_PWR_S 23
330#define AR9280_PHY_EXT_MINCCA_PWR 0x01FF0000
331#define AR9280_PHY_EXT_MINCCA_PWR_S 16
332
333#define AR_PHY_SFCORR_EXT 0x99c0
334#define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F
335#define AR_PHY_SFCORR_EXT_M1_THRESH_S 0
336#define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80
337#define AR_PHY_SFCORR_EXT_M2_THRESH_S 7
338#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000
339#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14
340#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000
341#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21
342#define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28
343
344#define AR_PHY_HALFGI 0x99D0
345#define AR_PHY_HALFGI_DSC_MAN 0x0007FFF0
346#define AR_PHY_HALFGI_DSC_MAN_S 4
347#define AR_PHY_HALFGI_DSC_EXP 0x0000000F
348#define AR_PHY_HALFGI_DSC_EXP_S 0
349
350#define AR_PHY_CHAN_INFO_MEMORY 0x99DC
351#define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001
352
353#define AR_PHY_HEAVY_CLIP_ENABLE 0x99E0
354
355#define AR_PHY_HEAVY_CLIP_FACTOR_RIFS 0x99EC
356#define AR_PHY_RIFS_INIT_DELAY 0x03ff0000
357
358#define AR_PHY_M_SLEEP 0x99f0
359#define AR_PHY_REFCLKDLY 0x99f4
360#define AR_PHY_REFCLKPD 0x99f8
361
362#define AR_PHY_CALMODE 0x99f0
363
364#define AR_PHY_CALMODE_IQ 0x00000000
365#define AR_PHY_CALMODE_ADC_GAIN 0x00000001
366#define AR_PHY_CALMODE_ADC_DC_PER 0x00000002
367#define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003
368
369#define AR_PHY_CAL_MEAS_0(_i) (0x9c10 + ((_i) << 12))
370#define AR_PHY_CAL_MEAS_1(_i) (0x9c14 + ((_i) << 12))
371#define AR_PHY_CAL_MEAS_2(_i) (0x9c18 + ((_i) << 12))
372#define AR_PHY_CAL_MEAS_3(_i) (0x9c1c + ((_i) << 12))
373
374#define AR_PHY_CURRENT_RSSI 0x9c1c
375#define AR9280_PHY_CURRENT_RSSI 0x9c3c
376
377#define AR_PHY_RFBUS_GRANT 0x9C20
378#define AR_PHY_RFBUS_GRANT_EN 0x00000001
379
380#define AR_PHY_CHAN_INFO_GAIN_DIFF 0x9CF4
381#define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320
382
383#define AR_PHY_CHAN_INFO_GAIN 0x9CFC
384
385#define AR_PHY_MODE 0xA200
386#define AR_PHY_MODE_ASYNCFIFO 0x80
387#define AR_PHY_MODE_AR2133 0x08
388#define AR_PHY_MODE_AR5111 0x00
389#define AR_PHY_MODE_AR5112 0x08
390#define AR_PHY_MODE_DYNAMIC 0x04
391#define AR_PHY_MODE_RF2GHZ 0x02
392#define AR_PHY_MODE_RF5GHZ 0x00
393#define AR_PHY_MODE_CCK 0x01
394#define AR_PHY_MODE_OFDM 0x00
395#define AR_PHY_MODE_DYN_CCK_DISABLE 0x100
396
397#define AR_PHY_CCK_TX_CTRL 0xA204
398#define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010
399#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK 0x0000000C
400#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_S 2
401
402#define AR_PHY_CCK_DETECT 0xA208
403#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F
404#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0
405/* [12:6] settling time for antenna switch */
406#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0
407#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6
408#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000
409#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV_S 13
410
411#define AR_PHY_GAIN_2GHZ 0xA20C
412#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN 0x00FC0000
413#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN_S 18
414#define AR_PHY_GAIN_2GHZ_BSW_MARGIN 0x00003C00
415#define AR_PHY_GAIN_2GHZ_BSW_MARGIN_S 10
416#define AR_PHY_GAIN_2GHZ_BSW_ATTEN 0x0000001F
417#define AR_PHY_GAIN_2GHZ_BSW_ATTEN_S 0
418
419#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN 0x003E0000
420#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S 17
421#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN 0x0001F000
422#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S 12
423#define AR_PHY_GAIN_2GHZ_XATTEN2_DB 0x00000FC0
424#define AR_PHY_GAIN_2GHZ_XATTEN2_DB_S 6
425#define AR_PHY_GAIN_2GHZ_XATTEN1_DB 0x0000003F
426#define AR_PHY_GAIN_2GHZ_XATTEN1_DB_S 0
427
428#define AR_PHY_CCK_RXCTRL4 0xA21C
429#define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT 0x01F80000
430#define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_S 19
431
432#define AR_PHY_DAG_CTRLCCK 0xA228
433#define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200
434#define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00
435#define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10
436
437#define AR_PHY_FORCE_CLKEN_CCK 0xA22C
438#define AR_PHY_FORCE_CLKEN_CCK_MRC_MUX 0x00000040
439
440#define AR_PHY_POWER_TX_RATE3 0xA234
441#define AR_PHY_POWER_TX_RATE4 0xA238
442
443#define AR_PHY_SCRM_SEQ_XR 0xA23C
444#define AR_PHY_HEADER_DETECT_XR 0xA240
445#define AR_PHY_CHIRP_DETECTED_XR 0xA244
446#define AR_PHY_BLUETOOTH 0xA254
447
448#define AR_PHY_TPCRG1 0xA258
449#define AR_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000
450#define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14
451
452#define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000
453#define AR_PHY_TPCRG1_PD_GAIN_1_S 16
454#define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000
455#define AR_PHY_TPCRG1_PD_GAIN_2_S 18
456#define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000
457#define AR_PHY_TPCRG1_PD_GAIN_3_S 20
458
459#define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000
460#define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22
461
462#define AR_PHY_TX_PWRCTRL4 0xa264
463#define AR_PHY_TX_PWRCTRL_PD_AVG_VALID 0x00000001
464#define AR_PHY_TX_PWRCTRL_PD_AVG_VALID_S 0
465#define AR_PHY_TX_PWRCTRL_PD_AVG_OUT 0x000001FE
466#define AR_PHY_TX_PWRCTRL_PD_AVG_OUT_S 1
467
468#define AR_PHY_TX_PWRCTRL6_0 0xa270
469#define AR_PHY_TX_PWRCTRL6_1 0xb270
470#define AR_PHY_TX_PWRCTRL_ERR_EST_MODE 0x03000000
471#define AR_PHY_TX_PWRCTRL_ERR_EST_MODE_S 24
472
473#define AR_PHY_TX_PWRCTRL7 0xa274
474#define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN 0x01F80000
475#define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN_S 19
476
477#define AR_PHY_TX_PWRCTRL9 0xa27C
478#define AR_PHY_TX_DESIRED_SCALE_CCK 0x00007C00
479#define AR_PHY_TX_DESIRED_SCALE_CCK_S 10
480#define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL 0x80000000
481#define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL_S 31
482
483#define AR_PHY_TX_GAIN_TBL1 0xa300
484#define AR_PHY_TX_GAIN 0x0007F000
485#define AR_PHY_TX_GAIN_S 12
486
487#define AR_PHY_CH0_TX_PWRCTRL11 0xa398
488#define AR_PHY_CH1_TX_PWRCTRL11 0xb398
489#define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP 0x0000FC00
490#define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP_S 10
491
492#define AR_PHY_VIT_MASK2_M_46_61 0xa3a0
493#define AR_PHY_MASK2_M_31_45 0xa3a4
494#define AR_PHY_MASK2_M_16_30 0xa3a8
495#define AR_PHY_MASK2_M_00_15 0xa3ac
496#define AR_PHY_MASK2_P_15_01 0xa3b8
497#define AR_PHY_MASK2_P_30_16 0xa3bc
498#define AR_PHY_MASK2_P_45_31 0xa3c0
499#define AR_PHY_MASK2_P_61_45 0xa3c4
500#define AR_PHY_SPUR_REG 0x994c
501
502#define AR_PHY_SPUR_REG_MASK_RATE_CNTL (0xFF << 18)
503#define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18
504
505#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000
506#define AR_PHY_SPUR_REG_MASK_RATE_SELECT (0xFF << 9)
507#define AR_PHY_SPUR_REG_MASK_RATE_SELECT_S 9
508#define AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI 0x100
509#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x7F
510#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0
511
512#define AR_PHY_PILOT_MASK_01_30 0xa3b0
513#define AR_PHY_PILOT_MASK_31_60 0xa3b4
514
515#define AR_PHY_CHANNEL_MASK_01_30 0x99d4
516#define AR_PHY_CHANNEL_MASK_31_60 0x99d8
517
518#define AR_PHY_ANALOG_SWAP 0xa268
519#define AR_PHY_SWAP_ALT_CHAIN 0x00000040
520
521#define AR_PHY_TPCRG5 0xA26C
522#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000F
523#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0
524#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003F0
525#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4
526#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000FC00
527#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10
528#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003F0000
529#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16
530#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0FC00000
531#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22
532
533/* Carrier leak calibration control, do it after AGC calibration */
534#define AR_PHY_CL_CAL_CTL 0xA358
535#define AR_PHY_CL_CAL_ENABLE 0x00000002
536#define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001
537
538#define AR_PHY_POWER_TX_RATE5 0xA38C
539#define AR_PHY_POWER_TX_RATE6 0xA390
540
541#define AR_PHY_CAL_CHAINMASK 0xA39C
542
543#define AR_PHY_POWER_TX_SUB 0xA3C8
544#define AR_PHY_POWER_TX_RATE7 0xA3CC
545#define AR_PHY_POWER_TX_RATE8 0xA3D0
546#define AR_PHY_POWER_TX_RATE9 0xA3D4
547
548#define AR_PHY_XPA_CFG 0xA3D8
549#define AR_PHY_FORCE_XPA_CFG 0x000000001
550#define AR_PHY_FORCE_XPA_CFG_S 0
551
552#define AR_PHY_CH1_CCA 0xa864
553#define AR_PHY_CH1_MINCCA_PWR 0x0FF80000
554#define AR_PHY_CH1_MINCCA_PWR_S 19
555#define AR9280_PHY_CH1_MINCCA_PWR 0x1FF00000
556#define AR9280_PHY_CH1_MINCCA_PWR_S 20
557
558#define AR_PHY_CH2_CCA 0xb864
559#define AR_PHY_CH2_MINCCA_PWR 0x0FF80000
560#define AR_PHY_CH2_MINCCA_PWR_S 19
561
562#define AR_PHY_CH1_EXT_CCA 0xa9bc
563#define AR_PHY_CH1_EXT_MINCCA_PWR 0xFF800000
564#define AR_PHY_CH1_EXT_MINCCA_PWR_S 23
565#define AR9280_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000
566#define AR9280_PHY_CH1_EXT_MINCCA_PWR_S 16
567
568#define AR_PHY_CH2_EXT_CCA 0xb9bc
569#define AR_PHY_CH2_EXT_MINCCA_PWR 0xFF800000
570#define AR_PHY_CH2_EXT_MINCCA_PWR_S 23
571
572#endif
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_calib.c b/drivers/net/wireless/ath/ath9k/ar9003_calib.c
new file mode 100644
index 000000000000..5fcafb460877
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/ar9003_calib.c
@@ -0,0 +1,803 @@
1/*
2 * Copyright (c) 2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "hw.h"
18#include "hw-ops.h"
19#include "ar9003_phy.h"
20
21static void ar9003_hw_setup_calibration(struct ath_hw *ah,
22 struct ath9k_cal_list *currCal)
23{
24 struct ath_common *common = ath9k_hw_common(ah);
25
26 /* Select calibration to run */
27 switch (currCal->calData->calType) {
28 case IQ_MISMATCH_CAL:
29 /*
30 * Start calibration with
31 * 2^(INIT_IQCAL_LOG_COUNT_MAX+1) samples
32 */
33 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
34 AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX,
35 currCal->calData->calCountMax);
36 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
37
38 ath_print(common, ATH_DBG_CALIBRATE,
39 "starting IQ Mismatch Calibration\n");
40
41 /* Kick-off cal */
42 REG_SET_BIT(ah, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL);
43 break;
44 case TEMP_COMP_CAL:
45 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_THERM,
46 AR_PHY_65NM_CH0_THERM_LOCAL, 1);
47 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_THERM,
48 AR_PHY_65NM_CH0_THERM_START, 1);
49
50 ath_print(common, ATH_DBG_CALIBRATE,
51 "starting Temperature Compensation Calibration\n");
52 break;
53 case ADC_DC_INIT_CAL:
54 case ADC_GAIN_CAL:
55 case ADC_DC_CAL:
56 /* Not yet */
57 break;
58 }
59}
60
61/*
62 * Generic calibration routine.
63 * Recalibrate the lower PHY chips to account for temperature/environment
64 * changes.
65 */
66static bool ar9003_hw_per_calibration(struct ath_hw *ah,
67 struct ath9k_channel *ichan,
68 u8 rxchainmask,
69 struct ath9k_cal_list *currCal)
70{
71 /* Cal is assumed not done until explicitly set below */
72 bool iscaldone = false;
73
74 /* Calibration in progress. */
75 if (currCal->calState == CAL_RUNNING) {
76 /* Check to see if it has finished. */
77 if (!(REG_READ(ah, AR_PHY_TIMING4) & AR_PHY_TIMING4_DO_CAL)) {
78 /*
79 * Accumulate cal measures for active chains
80 */
81 currCal->calData->calCollect(ah);
82 ah->cal_samples++;
83
84 if (ah->cal_samples >=
85 currCal->calData->calNumSamples) {
86 unsigned int i, numChains = 0;
87 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
88 if (rxchainmask & (1 << i))
89 numChains++;
90 }
91
92 /*
93 * Process accumulated data
94 */
95 currCal->calData->calPostProc(ah, numChains);
96
97 /* Calibration has finished. */
98 ichan->CalValid |= currCal->calData->calType;
99 currCal->calState = CAL_DONE;
100 iscaldone = true;
101 } else {
102 /*
103 * Set-up collection of another sub-sample until we
104 * get desired number
105 */
106 ar9003_hw_setup_calibration(ah, currCal);
107 }
108 }
109 } else if (!(ichan->CalValid & currCal->calData->calType)) {
110 /* If current cal is marked invalid in channel, kick it off */
111 ath9k_hw_reset_calibration(ah, currCal);
112 }
113
114 return iscaldone;
115}
116
117static bool ar9003_hw_calibrate(struct ath_hw *ah,
118 struct ath9k_channel *chan,
119 u8 rxchainmask,
120 bool longcal)
121{
122 bool iscaldone = true;
123 struct ath9k_cal_list *currCal = ah->cal_list_curr;
124
125 /*
126 * For given calibration:
127 * 1. Call generic cal routine
128 * 2. When this cal is done (isCalDone) if we have more cals waiting
129 * (eg after reset), mask this to upper layers by not propagating
130 * isCalDone if it is set to TRUE.
131 * Instead, change isCalDone to FALSE and setup the waiting cal(s)
132 * to be run.
133 */
134 if (currCal &&
135 (currCal->calState == CAL_RUNNING ||
136 currCal->calState == CAL_WAITING)) {
137 iscaldone = ar9003_hw_per_calibration(ah, chan,
138 rxchainmask, currCal);
139 if (iscaldone) {
140 ah->cal_list_curr = currCal = currCal->calNext;
141
142 if (currCal->calState == CAL_WAITING) {
143 iscaldone = false;
144 ath9k_hw_reset_calibration(ah, currCal);
145 }
146 }
147 }
148
149 /* Do NF cal only at longer intervals */
150 if (longcal) {
151 /*
152 * Load the NF from history buffer of the current channel.
153 * NF is slow time-variant, so it is OK to use a historical
154 * value.
155 */
156 ath9k_hw_loadnf(ah, ah->curchan);
157
158 /* start NF calibration, without updating BB NF register */
159 ath9k_hw_start_nfcal(ah);
160 }
161
162 return iscaldone;
163}
164
165static void ar9003_hw_iqcal_collect(struct ath_hw *ah)
166{
167 int i;
168
169 /* Accumulate IQ cal measures for active chains */
170 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
171 ah->totalPowerMeasI[i] +=
172 REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
173 ah->totalPowerMeasQ[i] +=
174 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
175 ah->totalIqCorrMeas[i] +=
176 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
177 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
178 "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
179 ah->cal_samples, i, ah->totalPowerMeasI[i],
180 ah->totalPowerMeasQ[i],
181 ah->totalIqCorrMeas[i]);
182 }
183}
184
185static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
186{
187 struct ath_common *common = ath9k_hw_common(ah);
188 u32 powerMeasQ, powerMeasI, iqCorrMeas;
189 u32 qCoffDenom, iCoffDenom;
190 int32_t qCoff, iCoff;
191 int iqCorrNeg, i;
192 const u_int32_t offset_array[3] = {
193 AR_PHY_RX_IQCAL_CORR_B0,
194 AR_PHY_RX_IQCAL_CORR_B1,
195 AR_PHY_RX_IQCAL_CORR_B2,
196 };
197
198 for (i = 0; i < numChains; i++) {
199 powerMeasI = ah->totalPowerMeasI[i];
200 powerMeasQ = ah->totalPowerMeasQ[i];
201 iqCorrMeas = ah->totalIqCorrMeas[i];
202
203 ath_print(common, ATH_DBG_CALIBRATE,
204 "Starting IQ Cal and Correction for Chain %d\n",
205 i);
206
207 ath_print(common, ATH_DBG_CALIBRATE,
208 "Orignal: Chn %diq_corr_meas = 0x%08x\n",
209 i, ah->totalIqCorrMeas[i]);
210
211 iqCorrNeg = 0;
212
213 if (iqCorrMeas > 0x80000000) {
214 iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
215 iqCorrNeg = 1;
216 }
217
218 ath_print(common, ATH_DBG_CALIBRATE,
219 "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
220 ath_print(common, ATH_DBG_CALIBRATE,
221 "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
222 ath_print(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
223 iqCorrNeg);
224
225 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 256;
226 qCoffDenom = powerMeasQ / 64;
227
228 if ((iCoffDenom != 0) && (qCoffDenom != 0)) {
229 iCoff = iqCorrMeas / iCoffDenom;
230 qCoff = powerMeasI / qCoffDenom - 64;
231 ath_print(common, ATH_DBG_CALIBRATE,
232 "Chn %d iCoff = 0x%08x\n", i, iCoff);
233 ath_print(common, ATH_DBG_CALIBRATE,
234 "Chn %d qCoff = 0x%08x\n", i, qCoff);
235
236 /* Force bounds on iCoff */
237 if (iCoff >= 63)
238 iCoff = 63;
239 else if (iCoff <= -63)
240 iCoff = -63;
241
242 /* Negate iCoff if iqCorrNeg == 0 */
243 if (iqCorrNeg == 0x0)
244 iCoff = -iCoff;
245
246 /* Force bounds on qCoff */
247 if (qCoff >= 63)
248 qCoff = 63;
249 else if (qCoff <= -63)
250 qCoff = -63;
251
252 iCoff = iCoff & 0x7f;
253 qCoff = qCoff & 0x7f;
254
255 ath_print(common, ATH_DBG_CALIBRATE,
256 "Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
257 i, iCoff, qCoff);
258 ath_print(common, ATH_DBG_CALIBRATE,
259 "Register offset (0x%04x) "
260 "before update = 0x%x\n",
261 offset_array[i],
262 REG_READ(ah, offset_array[i]));
263
264 REG_RMW_FIELD(ah, offset_array[i],
265 AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF,
266 iCoff);
267 REG_RMW_FIELD(ah, offset_array[i],
268 AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF,
269 qCoff);
270 ath_print(common, ATH_DBG_CALIBRATE,
271 "Register offset (0x%04x) QI COFF "
272 "(bitfields 0x%08x) after update = 0x%x\n",
273 offset_array[i],
274 AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF,
275 REG_READ(ah, offset_array[i]));
276 ath_print(common, ATH_DBG_CALIBRATE,
277 "Register offset (0x%04x) QQ COFF "
278 "(bitfields 0x%08x) after update = 0x%x\n",
279 offset_array[i],
280 AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF,
281 REG_READ(ah, offset_array[i]));
282
283 ath_print(common, ATH_DBG_CALIBRATE,
284 "IQ Cal and Correction done for Chain %d\n",
285 i);
286 }
287 }
288
289 REG_SET_BIT(ah, AR_PHY_RX_IQCAL_CORR_B0,
290 AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE);
291 ath_print(common, ATH_DBG_CALIBRATE,
292 "IQ Cal and Correction (offset 0x%04x) enabled "
293 "(bit position 0x%08x). New Value 0x%08x\n",
294 (unsigned) (AR_PHY_RX_IQCAL_CORR_B0),
295 AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE,
296 REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B0));
297}
298
299static const struct ath9k_percal_data iq_cal_single_sample = {
300 IQ_MISMATCH_CAL,
301 MIN_CAL_SAMPLES,
302 PER_MAX_LOG_COUNT,
303 ar9003_hw_iqcal_collect,
304 ar9003_hw_iqcalibrate
305};
306
307static void ar9003_hw_init_cal_settings(struct ath_hw *ah)
308{
309 ah->iq_caldata.calData = &iq_cal_single_sample;
310 ah->supp_cals = IQ_MISMATCH_CAL;
311}
312
313static bool ar9003_hw_iscal_supported(struct ath_hw *ah,
314 enum ath9k_cal_types calType)
315{
316 switch (calType & ah->supp_cals) {
317 case IQ_MISMATCH_CAL:
318 /*
319 * XXX: Run IQ Mismatch for non-CCK only
320 * Note that CHANNEL_B is never set though.
321 */
322 return true;
323 case ADC_GAIN_CAL:
324 case ADC_DC_CAL:
325 return false;
326 case TEMP_COMP_CAL:
327 return true;
328 }
329
330 return false;
331}
332
333/*
334 * solve 4x4 linear equation used in loopback iq cal.
335 */
336static bool ar9003_hw_solve_iq_cal(struct ath_hw *ah,
337 s32 sin_2phi_1,
338 s32 cos_2phi_1,
339 s32 sin_2phi_2,
340 s32 cos_2phi_2,
341 s32 mag_a0_d0,
342 s32 phs_a0_d0,
343 s32 mag_a1_d0,
344 s32 phs_a1_d0,
345 s32 solved_eq[])
346{
347 s32 f1 = cos_2phi_1 - cos_2phi_2,
348 f3 = sin_2phi_1 - sin_2phi_2,
349 f2;
350 s32 mag_tx, phs_tx, mag_rx, phs_rx;
351 const s32 result_shift = 1 << 15;
352 struct ath_common *common = ath9k_hw_common(ah);
353
354 f2 = (f1 * f1 + f3 * f3) / result_shift;
355
356 if (!f2) {
357 ath_print(common, ATH_DBG_CALIBRATE, "Divide by 0\n");
358 return false;
359 }
360
361 /* mag mismatch, tx */
362 mag_tx = f1 * (mag_a0_d0 - mag_a1_d0) + f3 * (phs_a0_d0 - phs_a1_d0);
363 /* phs mismatch, tx */
364 phs_tx = f3 * (-mag_a0_d0 + mag_a1_d0) + f1 * (phs_a0_d0 - phs_a1_d0);
365
366 mag_tx = (mag_tx / f2);
367 phs_tx = (phs_tx / f2);
368
369 /* mag mismatch, rx */
370 mag_rx = mag_a0_d0 - (cos_2phi_1 * mag_tx + sin_2phi_1 * phs_tx) /
371 result_shift;
372 /* phs mismatch, rx */
373 phs_rx = phs_a0_d0 + (sin_2phi_1 * mag_tx - cos_2phi_1 * phs_tx) /
374 result_shift;
375
376 solved_eq[0] = mag_tx;
377 solved_eq[1] = phs_tx;
378 solved_eq[2] = mag_rx;
379 solved_eq[3] = phs_rx;
380
381 return true;
382}
383
384static s32 ar9003_hw_find_mag_approx(struct ath_hw *ah, s32 in_re, s32 in_im)
385{
386 s32 abs_i = abs(in_re),
387 abs_q = abs(in_im),
388 max_abs, min_abs;
389
390 if (abs_i > abs_q) {
391 max_abs = abs_i;
392 min_abs = abs_q;
393 } else {
394 max_abs = abs_q;
395 min_abs = abs_i;
396 }
397
398 return max_abs - (max_abs / 32) + (min_abs / 8) + (min_abs / 4);
399}
400
401#define DELPT 32
402
403static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
404 s32 chain_idx,
405 const s32 iq_res[],
406 s32 iqc_coeff[])
407{
408 s32 i2_m_q2_a0_d0, i2_p_q2_a0_d0, iq_corr_a0_d0,
409 i2_m_q2_a0_d1, i2_p_q2_a0_d1, iq_corr_a0_d1,
410 i2_m_q2_a1_d0, i2_p_q2_a1_d0, iq_corr_a1_d0,
411 i2_m_q2_a1_d1, i2_p_q2_a1_d1, iq_corr_a1_d1;
412 s32 mag_a0_d0, mag_a1_d0, mag_a0_d1, mag_a1_d1,
413 phs_a0_d0, phs_a1_d0, phs_a0_d1, phs_a1_d1,
414 sin_2phi_1, cos_2phi_1,
415 sin_2phi_2, cos_2phi_2;
416 s32 mag_tx, phs_tx, mag_rx, phs_rx;
417 s32 solved_eq[4], mag_corr_tx, phs_corr_tx, mag_corr_rx, phs_corr_rx,
418 q_q_coff, q_i_coff;
419 const s32 res_scale = 1 << 15;
420 const s32 delpt_shift = 1 << 8;
421 s32 mag1, mag2;
422 struct ath_common *common = ath9k_hw_common(ah);
423
424 i2_m_q2_a0_d0 = iq_res[0] & 0xfff;
425 i2_p_q2_a0_d0 = (iq_res[0] >> 12) & 0xfff;
426 iq_corr_a0_d0 = ((iq_res[0] >> 24) & 0xff) + ((iq_res[1] & 0xf) << 8);
427
428 if (i2_m_q2_a0_d0 > 0x800)
429 i2_m_q2_a0_d0 = -((0xfff - i2_m_q2_a0_d0) + 1);
430
431 if (i2_p_q2_a0_d0 > 0x800)
432 i2_p_q2_a0_d0 = -((0xfff - i2_p_q2_a0_d0) + 1);
433
434 if (iq_corr_a0_d0 > 0x800)
435 iq_corr_a0_d0 = -((0xfff - iq_corr_a0_d0) + 1);
436
437 i2_m_q2_a0_d1 = (iq_res[1] >> 4) & 0xfff;
438 i2_p_q2_a0_d1 = (iq_res[2] & 0xfff);
439 iq_corr_a0_d1 = (iq_res[2] >> 12) & 0xfff;
440
441 if (i2_m_q2_a0_d1 > 0x800)
442 i2_m_q2_a0_d1 = -((0xfff - i2_m_q2_a0_d1) + 1);
443
444 if (i2_p_q2_a0_d1 > 0x800)
445 i2_p_q2_a0_d1 = -((0xfff - i2_p_q2_a0_d1) + 1);
446
447 if (iq_corr_a0_d1 > 0x800)
448 iq_corr_a0_d1 = -((0xfff - iq_corr_a0_d1) + 1);
449
450 i2_m_q2_a1_d0 = ((iq_res[2] >> 24) & 0xff) + ((iq_res[3] & 0xf) << 8);
451 i2_p_q2_a1_d0 = (iq_res[3] >> 4) & 0xfff;
452 iq_corr_a1_d0 = iq_res[4] & 0xfff;
453
454 if (i2_m_q2_a1_d0 > 0x800)
455 i2_m_q2_a1_d0 = -((0xfff - i2_m_q2_a1_d0) + 1);
456
457 if (i2_p_q2_a1_d0 > 0x800)
458 i2_p_q2_a1_d0 = -((0xfff - i2_p_q2_a1_d0) + 1);
459
460 if (iq_corr_a1_d0 > 0x800)
461 iq_corr_a1_d0 = -((0xfff - iq_corr_a1_d0) + 1);
462
463 i2_m_q2_a1_d1 = (iq_res[4] >> 12) & 0xfff;
464 i2_p_q2_a1_d1 = ((iq_res[4] >> 24) & 0xff) + ((iq_res[5] & 0xf) << 8);
465 iq_corr_a1_d1 = (iq_res[5] >> 4) & 0xfff;
466
467 if (i2_m_q2_a1_d1 > 0x800)
468 i2_m_q2_a1_d1 = -((0xfff - i2_m_q2_a1_d1) + 1);
469
470 if (i2_p_q2_a1_d1 > 0x800)
471 i2_p_q2_a1_d1 = -((0xfff - i2_p_q2_a1_d1) + 1);
472
473 if (iq_corr_a1_d1 > 0x800)
474 iq_corr_a1_d1 = -((0xfff - iq_corr_a1_d1) + 1);
475
476 if ((i2_p_q2_a0_d0 == 0) || (i2_p_q2_a0_d1 == 0) ||
477 (i2_p_q2_a1_d0 == 0) || (i2_p_q2_a1_d1 == 0)) {
478 ath_print(common, ATH_DBG_CALIBRATE,
479 "Divide by 0:\na0_d0=%d\n"
480 "a0_d1=%d\na2_d0=%d\na1_d1=%d\n",
481 i2_p_q2_a0_d0, i2_p_q2_a0_d1,
482 i2_p_q2_a1_d0, i2_p_q2_a1_d1);
483 return false;
484 }
485
486 mag_a0_d0 = (i2_m_q2_a0_d0 * res_scale) / i2_p_q2_a0_d0;
487 phs_a0_d0 = (iq_corr_a0_d0 * res_scale) / i2_p_q2_a0_d0;
488
489 mag_a0_d1 = (i2_m_q2_a0_d1 * res_scale) / i2_p_q2_a0_d1;
490 phs_a0_d1 = (iq_corr_a0_d1 * res_scale) / i2_p_q2_a0_d1;
491
492 mag_a1_d0 = (i2_m_q2_a1_d0 * res_scale) / i2_p_q2_a1_d0;
493 phs_a1_d0 = (iq_corr_a1_d0 * res_scale) / i2_p_q2_a1_d0;
494
495 mag_a1_d1 = (i2_m_q2_a1_d1 * res_scale) / i2_p_q2_a1_d1;
496 phs_a1_d1 = (iq_corr_a1_d1 * res_scale) / i2_p_q2_a1_d1;
497
498 /* w/o analog phase shift */
499 sin_2phi_1 = (((mag_a0_d0 - mag_a0_d1) * delpt_shift) / DELPT);
500 /* w/o analog phase shift */
501 cos_2phi_1 = (((phs_a0_d1 - phs_a0_d0) * delpt_shift) / DELPT);
502 /* w/ analog phase shift */
503 sin_2phi_2 = (((mag_a1_d0 - mag_a1_d1) * delpt_shift) / DELPT);
504 /* w/ analog phase shift */
505 cos_2phi_2 = (((phs_a1_d1 - phs_a1_d0) * delpt_shift) / DELPT);
506
507 /*
508 * force sin^2 + cos^2 = 1;
509 * find magnitude by approximation
510 */
511 mag1 = ar9003_hw_find_mag_approx(ah, cos_2phi_1, sin_2phi_1);
512 mag2 = ar9003_hw_find_mag_approx(ah, cos_2phi_2, sin_2phi_2);
513
514 if ((mag1 == 0) || (mag2 == 0)) {
515 ath_print(common, ATH_DBG_CALIBRATE,
516 "Divide by 0: mag1=%d, mag2=%d\n",
517 mag1, mag2);
518 return false;
519 }
520
521 /* normalization sin and cos by mag */
522 sin_2phi_1 = (sin_2phi_1 * res_scale / mag1);
523 cos_2phi_1 = (cos_2phi_1 * res_scale / mag1);
524 sin_2phi_2 = (sin_2phi_2 * res_scale / mag2);
525 cos_2phi_2 = (cos_2phi_2 * res_scale / mag2);
526
527 /* calculate IQ mismatch */
528 if (!ar9003_hw_solve_iq_cal(ah,
529 sin_2phi_1, cos_2phi_1,
530 sin_2phi_2, cos_2phi_2,
531 mag_a0_d0, phs_a0_d0,
532 mag_a1_d0,
533 phs_a1_d0, solved_eq)) {
534 ath_print(common, ATH_DBG_CALIBRATE,
535 "Call to ar9003_hw_solve_iq_cal() failed.\n");
536 return false;
537 }
538
539 mag_tx = solved_eq[0];
540 phs_tx = solved_eq[1];
541 mag_rx = solved_eq[2];
542 phs_rx = solved_eq[3];
543
544 ath_print(common, ATH_DBG_CALIBRATE,
545 "chain %d: mag mismatch=%d phase mismatch=%d\n",
546 chain_idx, mag_tx/res_scale, phs_tx/res_scale);
547
548 if (res_scale == mag_tx) {
549 ath_print(common, ATH_DBG_CALIBRATE,
550 "Divide by 0: mag_tx=%d, res_scale=%d\n",
551 mag_tx, res_scale);
552 return false;
553 }
554
555 /* calculate and quantize Tx IQ correction factor */
556 mag_corr_tx = (mag_tx * res_scale) / (res_scale - mag_tx);
557 phs_corr_tx = -phs_tx;
558
559 q_q_coff = (mag_corr_tx * 128 / res_scale);
560 q_i_coff = (phs_corr_tx * 256 / res_scale);
561
562 ath_print(common, ATH_DBG_CALIBRATE,
563 "tx chain %d: mag corr=%d phase corr=%d\n",
564 chain_idx, q_q_coff, q_i_coff);
565
566 if (q_i_coff < -63)
567 q_i_coff = -63;
568 if (q_i_coff > 63)
569 q_i_coff = 63;
570 if (q_q_coff < -63)
571 q_q_coff = -63;
572 if (q_q_coff > 63)
573 q_q_coff = 63;
574
575 iqc_coeff[0] = (q_q_coff * 128) + q_i_coff;
576
577 ath_print(common, ATH_DBG_CALIBRATE,
578 "tx chain %d: iq corr coeff=%x\n",
579 chain_idx, iqc_coeff[0]);
580
581 if (-mag_rx == res_scale) {
582 ath_print(common, ATH_DBG_CALIBRATE,
583 "Divide by 0: mag_rx=%d, res_scale=%d\n",
584 mag_rx, res_scale);
585 return false;
586 }
587
588 /* calculate and quantize Rx IQ correction factors */
589 mag_corr_rx = (-mag_rx * res_scale) / (res_scale + mag_rx);
590 phs_corr_rx = -phs_rx;
591
592 q_q_coff = (mag_corr_rx * 128 / res_scale);
593 q_i_coff = (phs_corr_rx * 256 / res_scale);
594
595 ath_print(common, ATH_DBG_CALIBRATE,
596 "rx chain %d: mag corr=%d phase corr=%d\n",
597 chain_idx, q_q_coff, q_i_coff);
598
599 if (q_i_coff < -63)
600 q_i_coff = -63;
601 if (q_i_coff > 63)
602 q_i_coff = 63;
603 if (q_q_coff < -63)
604 q_q_coff = -63;
605 if (q_q_coff > 63)
606 q_q_coff = 63;
607
608 iqc_coeff[1] = (q_q_coff * 128) + q_i_coff;
609
610 ath_print(common, ATH_DBG_CALIBRATE,
611 "rx chain %d: iq corr coeff=%x\n",
612 chain_idx, iqc_coeff[1]);
613
614 return true;
615}
616
617static void ar9003_hw_tx_iq_cal(struct ath_hw *ah)
618{
619 struct ath_common *common = ath9k_hw_common(ah);
620 const u32 txiqcal_status[AR9300_MAX_CHAINS] = {
621 AR_PHY_TX_IQCAL_STATUS_B0,
622 AR_PHY_TX_IQCAL_STATUS_B1,
623 AR_PHY_TX_IQCAL_STATUS_B2,
624 };
625 const u32 tx_corr_coeff[AR9300_MAX_CHAINS] = {
626 AR_PHY_TX_IQCAL_CORR_COEFF_01_B0,
627 AR_PHY_TX_IQCAL_CORR_COEFF_01_B1,
628 AR_PHY_TX_IQCAL_CORR_COEFF_01_B2,
629 };
630 const u32 rx_corr[AR9300_MAX_CHAINS] = {
631 AR_PHY_RX_IQCAL_CORR_B0,
632 AR_PHY_RX_IQCAL_CORR_B1,
633 AR_PHY_RX_IQCAL_CORR_B2,
634 };
635 const u_int32_t chan_info_tab[] = {
636 AR_PHY_CHAN_INFO_TAB_0,
637 AR_PHY_CHAN_INFO_TAB_1,
638 AR_PHY_CHAN_INFO_TAB_2,
639 };
640 s32 iq_res[6];
641 s32 iqc_coeff[2];
642 s32 i, j;
643 u32 num_chains = 0;
644
645 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
646 if (ah->txchainmask & (1 << i))
647 num_chains++;
648 }
649
650 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1,
651 AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT,
652 DELPT);
653 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_START,
654 AR_PHY_TX_IQCAL_START_DO_CAL,
655 AR_PHY_TX_IQCAL_START_DO_CAL);
656
657 if (!ath9k_hw_wait(ah, AR_PHY_TX_IQCAL_START,
658 AR_PHY_TX_IQCAL_START_DO_CAL,
659 0, AH_WAIT_TIMEOUT)) {
660 ath_print(common, ATH_DBG_CALIBRATE,
661 "Tx IQ Cal not complete.\n");
662 goto TX_IQ_CAL_FAILED;
663 }
664
665 for (i = 0; i < num_chains; i++) {
666 ath_print(common, ATH_DBG_CALIBRATE,
667 "Doing Tx IQ Cal for chain %d.\n", i);
668
669 if (REG_READ(ah, txiqcal_status[i]) &
670 AR_PHY_TX_IQCAL_STATUS_FAILED) {
671 ath_print(common, ATH_DBG_CALIBRATE,
672 "Tx IQ Cal failed for chain %d.\n", i);
673 goto TX_IQ_CAL_FAILED;
674 }
675
676 for (j = 0; j < 3; j++) {
677 u_int8_t idx = 2 * j,
678 offset = 4 * j;
679
680 REG_RMW_FIELD(ah, AR_PHY_CHAN_INFO_MEMORY,
681 AR_PHY_CHAN_INFO_TAB_S2_READ, 0);
682
683 /* 32 bits */
684 iq_res[idx] = REG_READ(ah, chan_info_tab[i] + offset);
685
686 REG_RMW_FIELD(ah, AR_PHY_CHAN_INFO_MEMORY,
687 AR_PHY_CHAN_INFO_TAB_S2_READ, 1);
688
689 /* 16 bits */
690 iq_res[idx+1] = 0xffff & REG_READ(ah,
691 chan_info_tab[i] +
692 offset);
693
694 ath_print(common, ATH_DBG_CALIBRATE,
695 "IQ RES[%d]=0x%x IQ_RES[%d]=0x%x\n",
696 idx, iq_res[idx], idx+1, iq_res[idx+1]);
697 }
698
699 if (!ar9003_hw_calc_iq_corr(ah, i, iq_res, iqc_coeff)) {
700 ath_print(common, ATH_DBG_CALIBRATE,
701 "Failed in calculation of IQ correction.\n");
702 goto TX_IQ_CAL_FAILED;
703 }
704
705 ath_print(common, ATH_DBG_CALIBRATE,
706 "IQ_COEFF[0] = 0x%x IQ_COEFF[1] = 0x%x\n",
707 iqc_coeff[0], iqc_coeff[1]);
708
709 REG_RMW_FIELD(ah, tx_corr_coeff[i],
710 AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE,
711 iqc_coeff[0]);
712 REG_RMW_FIELD(ah, rx_corr[i],
713 AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF,
714 iqc_coeff[1] >> 7);
715 REG_RMW_FIELD(ah, rx_corr[i],
716 AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF,
717 iqc_coeff[1]);
718 }
719
720 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3,
721 AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN, 0x1);
722 REG_RMW_FIELD(ah, AR_PHY_RX_IQCAL_CORR_B0,
723 AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN, 0x1);
724
725 return;
726
727TX_IQ_CAL_FAILED:
728 ath_print(common, ATH_DBG_CALIBRATE, "Tx IQ Cal failed\n");
729 return;
730}
731
732static bool ar9003_hw_init_cal(struct ath_hw *ah,
733 struct ath9k_channel *chan)
734{
735 struct ath_common *common = ath9k_hw_common(ah);
736
737 /*
738 * 0x7 = 0b111 , AR9003 needs to be configured for 3-chain mode before
739 * running AGC/TxIQ cals
740 */
741 ar9003_hw_set_chain_masks(ah, 0x7, 0x7);
742
743 /* Calibrate the AGC */
744 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
745 REG_READ(ah, AR_PHY_AGC_CONTROL) |
746 AR_PHY_AGC_CONTROL_CAL);
747
748 /* Poll for offset calibration complete */
749 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
750 0, AH_WAIT_TIMEOUT)) {
751 ath_print(common, ATH_DBG_CALIBRATE,
752 "offset calibration failed to "
753 "complete in 1ms; noisy environment?\n");
754 return false;
755 }
756
757 /* Do Tx IQ Calibration */
758 if (ah->config.tx_iq_calibration)
759 ar9003_hw_tx_iq_cal(ah);
760
761 /* Revert chainmasks to their original values before NF cal */
762 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
763
764 /* Initialize list pointers */
765 ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
766
767 if (ar9003_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {
768 INIT_CAL(&ah->iq_caldata);
769 INSERT_CAL(ah, &ah->iq_caldata);
770 ath_print(common, ATH_DBG_CALIBRATE,
771 "enabling IQ Calibration.\n");
772 }
773
774 if (ar9003_hw_iscal_supported(ah, TEMP_COMP_CAL)) {
775 INIT_CAL(&ah->tempCompCalData);
776 INSERT_CAL(ah, &ah->tempCompCalData);
777 ath_print(common, ATH_DBG_CALIBRATE,
778 "enabling Temperature Compensation Calibration.\n");
779 }
780
781 /* Initialize current pointer to first element in list */
782 ah->cal_list_curr = ah->cal_list;
783
784 if (ah->cal_list_curr)
785 ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
786
787 chan->CalValid = 0;
788
789 return true;
790}
791
792void ar9003_hw_attach_calib_ops(struct ath_hw *ah)
793{
794 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
795 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
796
797 priv_ops->init_cal_settings = ar9003_hw_init_cal_settings;
798 priv_ops->init_cal = ar9003_hw_init_cal;
799 priv_ops->setup_calibration = ar9003_hw_setup_calibration;
800 priv_ops->iscal_supported = ar9003_hw_iscal_supported;
801
802 ops->calibrate = ar9003_hw_calibrate;
803}
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
new file mode 100644
index 000000000000..8a79550dff71
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
@@ -0,0 +1,1860 @@
1/*
2 * Copyright (c) 2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "hw.h"
18#include "ar9003_phy.h"
19#include "ar9003_eeprom.h"
20
21#define COMP_HDR_LEN 4
22#define COMP_CKSUM_LEN 2
23
24#define AR_CH0_TOP (0x00016288)
25#define AR_CH0_TOP_XPABIASLVL (0x3)
26#define AR_CH0_TOP_XPABIASLVL_S (8)
27
28#define AR_CH0_THERM (0x00016290)
29#define AR_CH0_THERM_SPARE (0x3f)
30#define AR_CH0_THERM_SPARE_S (0)
31
32#define AR_SWITCH_TABLE_COM_ALL (0xffff)
33#define AR_SWITCH_TABLE_COM_ALL_S (0)
34
35#define AR_SWITCH_TABLE_COM2_ALL (0xffffff)
36#define AR_SWITCH_TABLE_COM2_ALL_S (0)
37
38#define AR_SWITCH_TABLE_ALL (0xfff)
39#define AR_SWITCH_TABLE_ALL_S (0)
40
41static const struct ar9300_eeprom ar9300_default = {
42 .eepromVersion = 2,
43 .templateVersion = 2,
44 .macAddr = {1, 2, 3, 4, 5, 6},
45 .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
46 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
47 .baseEepHeader = {
48 .regDmn = {0, 0x1f},
49 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
50 .opCapFlags = {
51 .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
52 .eepMisc = 0,
53 },
54 .rfSilent = 0,
55 .blueToothOptions = 0,
56 .deviceCap = 0,
57 .deviceType = 5, /* takes lower byte in eeprom location */
58 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
59 .params_for_tuning_caps = {0, 0},
60 .featureEnable = 0x0c,
61 /*
62 * bit0 - enable tx temp comp - disabled
63 * bit1 - enable tx volt comp - disabled
64 * bit2 - enable fastClock - enabled
65 * bit3 - enable doubling - enabled
66 * bit4 - enable internal regulator - disabled
67 */
68 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
69 .eepromWriteEnableGpio = 3,
70 .wlanDisableGpio = 0,
71 .wlanLedGpio = 8,
72 .rxBandSelectGpio = 0xff,
73 .txrxgain = 0,
74 .swreg = 0,
75 },
76 .modalHeader2G = {
77 /* ar9300_modal_eep_header 2g */
78 /* 4 idle,t1,t2,b(4 bits per setting) */
79 .antCtrlCommon = 0x110,
80 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
81 .antCtrlCommon2 = 0x22222,
82
83 /*
84 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
85 * rx1, rx12, b (2 bits each)
86 */
87 .antCtrlChain = {0x150, 0x150, 0x150},
88
89 /*
90 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
91 * for ar9280 (0xa20c/b20c 5:0)
92 */
93 .xatten1DB = {0, 0, 0},
94
95 /*
96 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
97 * for ar9280 (0xa20c/b20c 16:12
98 */
99 .xatten1Margin = {0, 0, 0},
100 .tempSlope = 36,
101 .voltSlope = 0,
102
103 /*
104 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
105 * channels in usual fbin coding format
106 */
107 .spurChans = {0, 0, 0, 0, 0},
108
109 /*
110 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
111 * if the register is per chain
112 */
113 .noiseFloorThreshCh = {-1, 0, 0},
114 .ob = {1, 1, 1},/* 3 chain */
115 .db_stage2 = {1, 1, 1}, /* 3 chain */
116 .db_stage3 = {0, 0, 0},
117 .db_stage4 = {0, 0, 0},
118 .xpaBiasLvl = 0,
119 .txFrameToDataStart = 0x0e,
120 .txFrameToPaOn = 0x0e,
121 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
122 .antennaGain = 0,
123 .switchSettling = 0x2c,
124 .adcDesiredSize = -30,
125 .txEndToXpaOff = 0,
126 .txEndToRxOn = 0x2,
127 .txFrameToXpaOn = 0xe,
128 .thresh62 = 28,
129 .futureModal = { /* [32] */
130 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
131 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
132 },
133 },
134 .calFreqPier2G = {
135 FREQ2FBIN(2412, 1),
136 FREQ2FBIN(2437, 1),
137 FREQ2FBIN(2472, 1),
138 },
139 /* ar9300_cal_data_per_freq_op_loop 2g */
140 .calPierData2G = {
141 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
142 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
143 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
144 },
145 .calTarget_freqbin_Cck = {
146 FREQ2FBIN(2412, 1),
147 FREQ2FBIN(2484, 1),
148 },
149 .calTarget_freqbin_2G = {
150 FREQ2FBIN(2412, 1),
151 FREQ2FBIN(2437, 1),
152 FREQ2FBIN(2472, 1)
153 },
154 .calTarget_freqbin_2GHT20 = {
155 FREQ2FBIN(2412, 1),
156 FREQ2FBIN(2437, 1),
157 FREQ2FBIN(2472, 1)
158 },
159 .calTarget_freqbin_2GHT40 = {
160 FREQ2FBIN(2412, 1),
161 FREQ2FBIN(2437, 1),
162 FREQ2FBIN(2472, 1)
163 },
164 .calTargetPowerCck = {
165 /* 1L-5L,5S,11L,11S */
166 { {36, 36, 36, 36} },
167 { {36, 36, 36, 36} },
168 },
169 .calTargetPower2G = {
170 /* 6-24,36,48,54 */
171 { {32, 32, 28, 24} },
172 { {32, 32, 28, 24} },
173 { {32, 32, 28, 24} },
174 },
175 .calTargetPower2GHT20 = {
176 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
177 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
178 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
179 },
180 .calTargetPower2GHT40 = {
181 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
182 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
183 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
184 },
185 .ctlIndex_2G = {
186 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
187 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
188 },
189 .ctl_freqbin_2G = {
190 {
191 FREQ2FBIN(2412, 1),
192 FREQ2FBIN(2417, 1),
193 FREQ2FBIN(2457, 1),
194 FREQ2FBIN(2462, 1)
195 },
196 {
197 FREQ2FBIN(2412, 1),
198 FREQ2FBIN(2417, 1),
199 FREQ2FBIN(2462, 1),
200 0xFF,
201 },
202
203 {
204 FREQ2FBIN(2412, 1),
205 FREQ2FBIN(2417, 1),
206 FREQ2FBIN(2462, 1),
207 0xFF,
208 },
209 {
210 FREQ2FBIN(2422, 1),
211 FREQ2FBIN(2427, 1),
212 FREQ2FBIN(2447, 1),
213 FREQ2FBIN(2452, 1)
214 },
215
216 {
217 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
218 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
219 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
220 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
221 },
222
223 {
224 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
225 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
226 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
227 0,
228 },
229
230 {
231 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
232 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
233 FREQ2FBIN(2472, 1),
234 0,
235 },
236
237 {
238 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
239 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
240 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
241 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
242 },
243
244 {
245 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
246 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
247 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
248 },
249
250 {
251 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
252 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
253 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
254 0
255 },
256
257 {
258 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
259 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
260 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
261 0
262 },
263
264 {
265 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
266 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
267 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
268 /* Data[11].ctlEdges[3].bChannel */
269 FREQ2FBIN(2462, 1),
270 }
271 },
272 .ctlPowerData_2G = {
273 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
274 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
275 { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
276
277 { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
278 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
279 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
280
281 { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
282 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
283 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
284
285 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
286 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
287 },
288 .modalHeader5G = {
289 /* 4 idle,t1,t2,b (4 bits per setting) */
290 .antCtrlCommon = 0x110,
291 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
292 .antCtrlCommon2 = 0x22222,
293 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
294 .antCtrlChain = {
295 0x000, 0x000, 0x000,
296 },
297 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
298 .xatten1DB = {0, 0, 0},
299
300 /*
301 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
302 * for merlin (0xa20c/b20c 16:12
303 */
304 .xatten1Margin = {0, 0, 0},
305 .tempSlope = 68,
306 .voltSlope = 0,
307 /* spurChans spur channels in usual fbin coding format */
308 .spurChans = {0, 0, 0, 0, 0},
309 /* noiseFloorThreshCh Check if the register is per chain */
310 .noiseFloorThreshCh = {-1, 0, 0},
311 .ob = {3, 3, 3}, /* 3 chain */
312 .db_stage2 = {3, 3, 3}, /* 3 chain */
313 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
314 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
315 .xpaBiasLvl = 0,
316 .txFrameToDataStart = 0x0e,
317 .txFrameToPaOn = 0x0e,
318 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
319 .antennaGain = 0,
320 .switchSettling = 0x2d,
321 .adcDesiredSize = -30,
322 .txEndToXpaOff = 0,
323 .txEndToRxOn = 0x2,
324 .txFrameToXpaOn = 0xe,
325 .thresh62 = 28,
326 .futureModal = {
327 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
328 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
329 },
330 },
331 .calFreqPier5G = {
332 FREQ2FBIN(5180, 0),
333 FREQ2FBIN(5220, 0),
334 FREQ2FBIN(5320, 0),
335 FREQ2FBIN(5400, 0),
336 FREQ2FBIN(5500, 0),
337 FREQ2FBIN(5600, 0),
338 FREQ2FBIN(5725, 0),
339 FREQ2FBIN(5825, 0)
340 },
341 .calPierData5G = {
342 {
343 {0, 0, 0, 0, 0},
344 {0, 0, 0, 0, 0},
345 {0, 0, 0, 0, 0},
346 {0, 0, 0, 0, 0},
347 {0, 0, 0, 0, 0},
348 {0, 0, 0, 0, 0},
349 {0, 0, 0, 0, 0},
350 {0, 0, 0, 0, 0},
351 },
352 {
353 {0, 0, 0, 0, 0},
354 {0, 0, 0, 0, 0},
355 {0, 0, 0, 0, 0},
356 {0, 0, 0, 0, 0},
357 {0, 0, 0, 0, 0},
358 {0, 0, 0, 0, 0},
359 {0, 0, 0, 0, 0},
360 {0, 0, 0, 0, 0},
361 },
362 {
363 {0, 0, 0, 0, 0},
364 {0, 0, 0, 0, 0},
365 {0, 0, 0, 0, 0},
366 {0, 0, 0, 0, 0},
367 {0, 0, 0, 0, 0},
368 {0, 0, 0, 0, 0},
369 {0, 0, 0, 0, 0},
370 {0, 0, 0, 0, 0},
371 },
372
373 },
374 .calTarget_freqbin_5G = {
375 FREQ2FBIN(5180, 0),
376 FREQ2FBIN(5220, 0),
377 FREQ2FBIN(5320, 0),
378 FREQ2FBIN(5400, 0),
379 FREQ2FBIN(5500, 0),
380 FREQ2FBIN(5600, 0),
381 FREQ2FBIN(5725, 0),
382 FREQ2FBIN(5825, 0)
383 },
384 .calTarget_freqbin_5GHT20 = {
385 FREQ2FBIN(5180, 0),
386 FREQ2FBIN(5240, 0),
387 FREQ2FBIN(5320, 0),
388 FREQ2FBIN(5500, 0),
389 FREQ2FBIN(5700, 0),
390 FREQ2FBIN(5745, 0),
391 FREQ2FBIN(5725, 0),
392 FREQ2FBIN(5825, 0)
393 },
394 .calTarget_freqbin_5GHT40 = {
395 FREQ2FBIN(5180, 0),
396 FREQ2FBIN(5240, 0),
397 FREQ2FBIN(5320, 0),
398 FREQ2FBIN(5500, 0),
399 FREQ2FBIN(5700, 0),
400 FREQ2FBIN(5745, 0),
401 FREQ2FBIN(5725, 0),
402 FREQ2FBIN(5825, 0)
403 },
404 .calTargetPower5G = {
405 /* 6-24,36,48,54 */
406 { {20, 20, 20, 10} },
407 { {20, 20, 20, 10} },
408 { {20, 20, 20, 10} },
409 { {20, 20, 20, 10} },
410 { {20, 20, 20, 10} },
411 { {20, 20, 20, 10} },
412 { {20, 20, 20, 10} },
413 { {20, 20, 20, 10} },
414 },
415 .calTargetPower5GHT20 = {
416 /*
417 * 0_8_16,1-3_9-11_17-19,
418 * 4,5,6,7,12,13,14,15,20,21,22,23
419 */
420 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
421 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
422 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
423 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
424 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
425 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
426 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
427 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
428 },
429 .calTargetPower5GHT40 = {
430 /*
431 * 0_8_16,1-3_9-11_17-19,
432 * 4,5,6,7,12,13,14,15,20,21,22,23
433 */
434 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
435 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
436 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
437 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
438 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
439 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
440 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
441 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
442 },
443 .ctlIndex_5G = {
444 0x10, 0x16, 0x18, 0x40, 0x46,
445 0x48, 0x30, 0x36, 0x38
446 },
447 .ctl_freqbin_5G = {
448 {
449 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
450 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
451 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
452 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
453 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
454 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
455 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
456 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
457 },
458 {
459 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
460 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
461 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
462 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
463 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
464 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
465 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
466 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
467 },
468
469 {
470 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
471 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
472 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
473 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
474 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
475 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
476 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
477 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
478 },
479
480 {
481 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
482 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
483 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
484 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
485 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
486 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
487 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
488 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
489 },
490
491 {
492 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
493 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
494 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
495 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
496 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
497 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
498 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
499 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
500 },
501
502 {
503 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
504 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
505 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
506 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
507 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
508 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
509 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
510 /* Data[5].ctlEdges[7].bChannel */ 0xFF
511 },
512
513 {
514 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
515 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
516 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
517 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
518 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
519 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
520 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
521 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
522 },
523
524 {
525 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
526 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
527 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
528 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
529 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
530 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
531 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
532 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
533 },
534
535 {
536 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
537 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
538 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
539 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
540 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
541 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
542 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
543 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
544 }
545 },
546 .ctlPowerData_5G = {
547 {
548 {
549 {60, 1}, {60, 1}, {60, 1}, {60, 1},
550 {60, 1}, {60, 1}, {60, 1}, {60, 0},
551 }
552 },
553 {
554 {
555 {60, 1}, {60, 1}, {60, 1}, {60, 1},
556 {60, 1}, {60, 1}, {60, 1}, {60, 0},
557 }
558 },
559 {
560 {
561 {60, 0}, {60, 1}, {60, 0}, {60, 1},
562 {60, 1}, {60, 1}, {60, 1}, {60, 1},
563 }
564 },
565 {
566 {
567 {60, 0}, {60, 1}, {60, 1}, {60, 0},
568 {60, 1}, {60, 0}, {60, 0}, {60, 0},
569 }
570 },
571 {
572 {
573 {60, 1}, {60, 1}, {60, 1}, {60, 0},
574 {60, 0}, {60, 0}, {60, 0}, {60, 0},
575 }
576 },
577 {
578 {
579 {60, 1}, {60, 1}, {60, 1}, {60, 1},
580 {60, 1}, {60, 0}, {60, 0}, {60, 0},
581 }
582 },
583 {
584 {
585 {60, 1}, {60, 1}, {60, 1}, {60, 1},
586 {60, 1}, {60, 1}, {60, 1}, {60, 1},
587 }
588 },
589 {
590 {
591 {60, 1}, {60, 1}, {60, 0}, {60, 1},
592 {60, 1}, {60, 1}, {60, 1}, {60, 0},
593 }
594 },
595 {
596 {
597 {60, 1}, {60, 0}, {60, 1}, {60, 1},
598 {60, 1}, {60, 1}, {60, 0}, {60, 1},
599 }
600 },
601 }
602};
603
604static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah)
605{
606 return 0;
607}
608
609static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
610 enum eeprom_param param)
611{
612 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
613 struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
614
615 switch (param) {
616 case EEP_MAC_LSW:
617 return eep->macAddr[0] << 8 | eep->macAddr[1];
618 case EEP_MAC_MID:
619 return eep->macAddr[2] << 8 | eep->macAddr[3];
620 case EEP_MAC_MSW:
621 return eep->macAddr[4] << 8 | eep->macAddr[5];
622 case EEP_REG_0:
623 return pBase->regDmn[0];
624 case EEP_REG_1:
625 return pBase->regDmn[1];
626 case EEP_OP_CAP:
627 return pBase->deviceCap;
628 case EEP_OP_MODE:
629 return pBase->opCapFlags.opFlags;
630 case EEP_RF_SILENT:
631 return pBase->rfSilent;
632 case EEP_TX_MASK:
633 return (pBase->txrxMask >> 4) & 0xf;
634 case EEP_RX_MASK:
635 return pBase->txrxMask & 0xf;
636 case EEP_DRIVE_STRENGTH:
637#define AR9300_EEP_BASE_DRIV_STRENGTH 0x1
638 return pBase->miscConfiguration & AR9300_EEP_BASE_DRIV_STRENGTH;
639 case EEP_INTERNAL_REGULATOR:
640 /* Bit 4 is internal regulator flag */
641 return (pBase->featureEnable & 0x10) >> 4;
642 case EEP_SWREG:
643 return pBase->swreg;
644 default:
645 return 0;
646 }
647}
648
649#ifdef __BIG_ENDIAN
650static void ar9300_swap_eeprom(struct ar9300_eeprom *eep)
651{
652 u32 dword;
653 u16 word;
654 int i;
655
656 word = swab16(eep->baseEepHeader.regDmn[0]);
657 eep->baseEepHeader.regDmn[0] = word;
658
659 word = swab16(eep->baseEepHeader.regDmn[1]);
660 eep->baseEepHeader.regDmn[1] = word;
661
662 dword = swab32(eep->baseEepHeader.swreg);
663 eep->baseEepHeader.swreg = dword;
664
665 dword = swab32(eep->modalHeader2G.antCtrlCommon);
666 eep->modalHeader2G.antCtrlCommon = dword;
667
668 dword = swab32(eep->modalHeader2G.antCtrlCommon2);
669 eep->modalHeader2G.antCtrlCommon2 = dword;
670
671 dword = swab32(eep->modalHeader5G.antCtrlCommon);
672 eep->modalHeader5G.antCtrlCommon = dword;
673
674 dword = swab32(eep->modalHeader5G.antCtrlCommon2);
675 eep->modalHeader5G.antCtrlCommon2 = dword;
676
677 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
678 word = swab16(eep->modalHeader2G.antCtrlChain[i]);
679 eep->modalHeader2G.antCtrlChain[i] = word;
680
681 word = swab16(eep->modalHeader5G.antCtrlChain[i]);
682 eep->modalHeader5G.antCtrlChain[i] = word;
683 }
684}
685#endif
686
687static bool ar9300_hw_read_eeprom(struct ath_hw *ah,
688 long address, u8 *buffer, int many)
689{
690 int i;
691 u8 value[2];
692 unsigned long eepAddr;
693 unsigned long byteAddr;
694 u16 *svalue;
695 struct ath_common *common = ath9k_hw_common(ah);
696
697 if ((address < 0) || ((address + many) > AR9300_EEPROM_SIZE - 1)) {
698 ath_print(common, ATH_DBG_EEPROM,
699 "eeprom address not in range\n");
700 return false;
701 }
702
703 for (i = 0; i < many; i++) {
704 eepAddr = (u16) (address + i) / 2;
705 byteAddr = (u16) (address + i) % 2;
706 svalue = (u16 *) value;
707 if (!ath9k_hw_nvram_read(common, eepAddr, svalue)) {
708 ath_print(common, ATH_DBG_EEPROM,
709 "unable to read eeprom region\n");
710 return false;
711 }
712 *svalue = le16_to_cpu(*svalue);
713 buffer[i] = value[byteAddr];
714 }
715
716 return true;
717}
718
719static bool ar9300_read_eeprom(struct ath_hw *ah,
720 int address, u8 *buffer, int many)
721{
722 int it;
723
724 for (it = 0; it < many; it++)
725 if (!ar9300_hw_read_eeprom(ah,
726 (address - it),
727 (buffer + it), 1))
728 return false;
729 return true;
730}
731
732static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference,
733 int *length, int *major, int *minor)
734{
735 unsigned long value[4];
736
737 value[0] = best[0];
738 value[1] = best[1];
739 value[2] = best[2];
740 value[3] = best[3];
741 *code = ((value[0] >> 5) & 0x0007);
742 *reference = (value[0] & 0x001f) | ((value[1] >> 2) & 0x0020);
743 *length = ((value[1] << 4) & 0x07f0) | ((value[2] >> 4) & 0x000f);
744 *major = (value[2] & 0x000f);
745 *minor = (value[3] & 0x00ff);
746}
747
748static u16 ar9300_comp_cksum(u8 *data, int dsize)
749{
750 int it, checksum = 0;
751
752 for (it = 0; it < dsize; it++) {
753 checksum += data[it];
754 checksum &= 0xffff;
755 }
756
757 return checksum;
758}
759
760static bool ar9300_uncompress_block(struct ath_hw *ah,
761 u8 *mptr,
762 int mdataSize,
763 u8 *block,
764 int size)
765{
766 int it;
767 int spot;
768 int offset;
769 int length;
770 struct ath_common *common = ath9k_hw_common(ah);
771
772 spot = 0;
773
774 for (it = 0; it < size; it += (length+2)) {
775 offset = block[it];
776 offset &= 0xff;
777 spot += offset;
778 length = block[it+1];
779 length &= 0xff;
780
781 if (length > 0 && spot >= 0 && spot+length < mdataSize) {
782 ath_print(common, ATH_DBG_EEPROM,
783 "Restore at %d: spot=%d "
784 "offset=%d length=%d\n",
785 it, spot, offset, length);
786 memcpy(&mptr[spot], &block[it+2], length);
787 spot += length;
788 } else if (length > 0) {
789 ath_print(common, ATH_DBG_EEPROM,
790 "Bad restore at %d: spot=%d "
791 "offset=%d length=%d\n",
792 it, spot, offset, length);
793 return false;
794 }
795 }
796 return true;
797}
798
799static int ar9300_compress_decision(struct ath_hw *ah,
800 int it,
801 int code,
802 int reference,
803 u8 *mptr,
804 u8 *word, int length, int mdata_size)
805{
806 struct ath_common *common = ath9k_hw_common(ah);
807 u8 *dptr;
808
809 switch (code) {
810 case _CompressNone:
811 if (length != mdata_size) {
812 ath_print(common, ATH_DBG_EEPROM,
813 "EEPROM structure size mismatch"
814 "memory=%d eeprom=%d\n", mdata_size, length);
815 return -1;
816 }
817 memcpy(mptr, (u8 *) (word + COMP_HDR_LEN), length);
818 ath_print(common, ATH_DBG_EEPROM, "restored eeprom %d:"
819 " uncompressed, length %d\n", it, length);
820 break;
821 case _CompressBlock:
822 if (reference == 0) {
823 dptr = mptr;
824 } else {
825 if (reference != 2) {
826 ath_print(common, ATH_DBG_EEPROM,
827 "cant find reference eeprom"
828 "struct %d\n", reference);
829 return -1;
830 }
831 memcpy(mptr, &ar9300_default, mdata_size);
832 }
833 ath_print(common, ATH_DBG_EEPROM,
834 "restore eeprom %d: block, reference %d,"
835 " length %d\n", it, reference, length);
836 ar9300_uncompress_block(ah, mptr, mdata_size,
837 (u8 *) (word + COMP_HDR_LEN), length);
838 break;
839 default:
840 ath_print(common, ATH_DBG_EEPROM, "unknown compression"
841 " code %d\n", code);
842 return -1;
843 }
844 return 0;
845}
846
847/*
848 * Read the configuration data from the eeprom.
849 * The data can be put in any specified memory buffer.
850 *
851 * Returns -1 on error.
852 * Returns address of next memory location on success.
853 */
854static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
855 u8 *mptr, int mdata_size)
856{
857#define MDEFAULT 15
858#define MSTATE 100
859 int cptr;
860 u8 *word;
861 int code;
862 int reference, length, major, minor;
863 int osize;
864 int it;
865 u16 checksum, mchecksum;
866 struct ath_common *common = ath9k_hw_common(ah);
867
868 word = kzalloc(2048, GFP_KERNEL);
869 if (!word)
870 return -1;
871
872 memcpy(mptr, &ar9300_default, mdata_size);
873
874 cptr = AR9300_BASE_ADDR;
875 for (it = 0; it < MSTATE; it++) {
876 if (!ar9300_read_eeprom(ah, cptr, word, COMP_HDR_LEN))
877 goto fail;
878
879 if ((word[0] == 0 && word[1] == 0 && word[2] == 0 &&
880 word[3] == 0) || (word[0] == 0xff && word[1] == 0xff
881 && word[2] == 0xff && word[3] == 0xff))
882 break;
883
884 ar9300_comp_hdr_unpack(word, &code, &reference,
885 &length, &major, &minor);
886 ath_print(common, ATH_DBG_EEPROM,
887 "Found block at %x: code=%d ref=%d"
888 "length=%d major=%d minor=%d\n", cptr, code,
889 reference, length, major, minor);
890 if (length >= 1024) {
891 ath_print(common, ATH_DBG_EEPROM,
892 "Skipping bad header\n");
893 cptr -= COMP_HDR_LEN;
894 continue;
895 }
896
897 osize = length;
898 ar9300_read_eeprom(ah, cptr, word,
899 COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
900 checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length);
901 mchecksum = word[COMP_HDR_LEN + osize] |
902 (word[COMP_HDR_LEN + osize + 1] << 8);
903 ath_print(common, ATH_DBG_EEPROM,
904 "checksum %x %x\n", checksum, mchecksum);
905 if (checksum == mchecksum) {
906 ar9300_compress_decision(ah, it, code, reference, mptr,
907 word, length, mdata_size);
908 } else {
909 ath_print(common, ATH_DBG_EEPROM,
910 "skipping block with bad checksum\n");
911 }
912 cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
913 }
914
915 kfree(word);
916 return cptr;
917
918fail:
919 kfree(word);
920 return -1;
921}
922
923/*
924 * Restore the configuration structure by reading the eeprom.
925 * This function destroys any existing in-memory structure
926 * content.
927 */
928static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah)
929{
930 u8 *mptr = NULL;
931 int mdata_size;
932
933 mptr = (u8 *) &ah->eeprom.ar9300_eep;
934 mdata_size = sizeof(struct ar9300_eeprom);
935
936 if (mptr && mdata_size > 0) {
937 /* At this point, mptr points to the eeprom data structure
938 * in it's "default" state. If this is big endian, swap the
939 * data structures back to "little endian"
940 */
941 /* First swap, default to Little Endian */
942#ifdef __BIG_ENDIAN
943 ar9300_swap_eeprom((struct ar9300_eeprom *)mptr);
944#endif
945 if (ar9300_eeprom_restore_internal(ah, mptr, mdata_size) >= 0)
946 return true;
947
948 /* Second Swap, back to Big Endian */
949#ifdef __BIG_ENDIAN
950 ar9300_swap_eeprom((struct ar9300_eeprom *)mptr);
951#endif
952 }
953 return false;
954}
955
956/* XXX: review hardware docs */
957static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah)
958{
959 return ah->eeprom.ar9300_eep.eepromVersion;
960}
961
962/* XXX: could be read from the eepromVersion, not sure yet */
963static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah)
964{
965 return 0;
966}
967
968static u8 ath9k_hw_ar9300_get_num_ant_config(struct ath_hw *ah,
969 enum ieee80211_band freq_band)
970{
971 return 1;
972}
973
974static u16 ath9k_hw_ar9300_get_eeprom_antenna_cfg(struct ath_hw *ah,
975 struct ath9k_channel *chan)
976{
977 return -EINVAL;
978}
979
980static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, bool is2ghz)
981{
982 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
983
984 if (is2ghz)
985 return eep->modalHeader2G.xpaBiasLvl;
986 else
987 return eep->modalHeader5G.xpaBiasLvl;
988}
989
990static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
991{
992 int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
993 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, (bias & 0x3));
994 REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_SPARE,
995 ((bias >> 2) & 0x3));
996}
997
998static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
999{
1000 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
1001
1002 if (is2ghz)
1003 return eep->modalHeader2G.antCtrlCommon;
1004 else
1005 return eep->modalHeader5G.antCtrlCommon;
1006}
1007
1008static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz)
1009{
1010 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
1011
1012 if (is2ghz)
1013 return eep->modalHeader2G.antCtrlCommon2;
1014 else
1015 return eep->modalHeader5G.antCtrlCommon2;
1016}
1017
1018static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah,
1019 int chain,
1020 bool is2ghz)
1021{
1022 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
1023
1024 if (chain >= 0 && chain < AR9300_MAX_CHAINS) {
1025 if (is2ghz)
1026 return eep->modalHeader2G.antCtrlChain[chain];
1027 else
1028 return eep->modalHeader5G.antCtrlChain[chain];
1029 }
1030
1031 return 0;
1032}
1033
1034static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
1035{
1036 u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);
1037 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, AR_SWITCH_TABLE_COM_ALL, value);
1038
1039 value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz);
1040 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value);
1041
1042 value = ar9003_hw_ant_ctrl_chain_get(ah, 0, is2ghz);
1043 REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_0, AR_SWITCH_TABLE_ALL, value);
1044
1045 value = ar9003_hw_ant_ctrl_chain_get(ah, 1, is2ghz);
1046 REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_1, AR_SWITCH_TABLE_ALL, value);
1047
1048 value = ar9003_hw_ant_ctrl_chain_get(ah, 2, is2ghz);
1049 REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_2, AR_SWITCH_TABLE_ALL, value);
1050}
1051
1052static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
1053{
1054 int drive_strength;
1055 unsigned long reg;
1056
1057 drive_strength = ath9k_hw_ar9300_get_eeprom(ah, EEP_DRIVE_STRENGTH);
1058
1059 if (!drive_strength)
1060 return;
1061
1062 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1);
1063 reg &= ~0x00ffffc0;
1064 reg |= 0x5 << 21;
1065 reg |= 0x5 << 18;
1066 reg |= 0x5 << 15;
1067 reg |= 0x5 << 12;
1068 reg |= 0x5 << 9;
1069 reg |= 0x5 << 6;
1070 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg);
1071
1072 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2);
1073 reg &= ~0xffffffe0;
1074 reg |= 0x5 << 29;
1075 reg |= 0x5 << 26;
1076 reg |= 0x5 << 23;
1077 reg |= 0x5 << 20;
1078 reg |= 0x5 << 17;
1079 reg |= 0x5 << 14;
1080 reg |= 0x5 << 11;
1081 reg |= 0x5 << 8;
1082 reg |= 0x5 << 5;
1083 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg);
1084
1085 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4);
1086 reg &= ~0xff800000;
1087 reg |= 0x5 << 29;
1088 reg |= 0x5 << 26;
1089 reg |= 0x5 << 23;
1090 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg);
1091}
1092
1093static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
1094{
1095 int internal_regulator =
1096 ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR);
1097
1098 if (internal_regulator) {
1099 /* Internal regulator is ON. Write swreg register. */
1100 int swreg = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
1101 REG_WRITE(ah, AR_RTC_REG_CONTROL1,
1102 REG_READ(ah, AR_RTC_REG_CONTROL1) &
1103 (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
1104 REG_WRITE(ah, AR_RTC_REG_CONTROL0, swreg);
1105 /* Set REG_CONTROL1.SWREG_PROGRAM */
1106 REG_WRITE(ah, AR_RTC_REG_CONTROL1,
1107 REG_READ(ah,
1108 AR_RTC_REG_CONTROL1) |
1109 AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
1110 } else {
1111 REG_WRITE(ah, AR_RTC_SLEEP_CLK,
1112 (REG_READ(ah,
1113 AR_RTC_SLEEP_CLK) |
1114 AR_RTC_FORCE_SWREG_PRD));
1115 }
1116}
1117
1118static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
1119 struct ath9k_channel *chan)
1120{
1121 ar9003_hw_xpa_bias_level_apply(ah, IS_CHAN_2GHZ(chan));
1122 ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan));
1123 ar9003_hw_drive_strength_apply(ah);
1124 ar9003_hw_internal_regulator_apply(ah);
1125}
1126
1127static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah,
1128 struct ath9k_channel *chan)
1129{
1130}
1131
1132/*
1133 * Returns the interpolated y value corresponding to the specified x value
1134 * from the np ordered pairs of data (px,py).
1135 * The pairs do not have to be in any order.
1136 * If the specified x value is less than any of the px,
1137 * the returned y value is equal to the py for the lowest px.
1138 * If the specified x value is greater than any of the px,
1139 * the returned y value is equal to the py for the highest px.
1140 */
1141static int ar9003_hw_power_interpolate(int32_t x,
1142 int32_t *px, int32_t *py, u_int16_t np)
1143{
1144 int ip = 0;
1145 int lx = 0, ly = 0, lhave = 0;
1146 int hx = 0, hy = 0, hhave = 0;
1147 int dx = 0;
1148 int y = 0;
1149
1150 lhave = 0;
1151 hhave = 0;
1152
1153 /* identify best lower and higher x calibration measurement */
1154 for (ip = 0; ip < np; ip++) {
1155 dx = x - px[ip];
1156
1157 /* this measurement is higher than our desired x */
1158 if (dx <= 0) {
1159 if (!hhave || dx > (x - hx)) {
1160 /* new best higher x measurement */
1161 hx = px[ip];
1162 hy = py[ip];
1163 hhave = 1;
1164 }
1165 }
1166 /* this measurement is lower than our desired x */
1167 if (dx >= 0) {
1168 if (!lhave || dx < (x - lx)) {
1169 /* new best lower x measurement */
1170 lx = px[ip];
1171 ly = py[ip];
1172 lhave = 1;
1173 }
1174 }
1175 }
1176
1177 /* the low x is good */
1178 if (lhave) {
1179 /* so is the high x */
1180 if (hhave) {
1181 /* they're the same, so just pick one */
1182 if (hx == lx)
1183 y = ly;
1184 else /* interpolate */
1185 y = ly + (((x - lx) * (hy - ly)) / (hx - lx));
1186 } else /* only low is good, use it */
1187 y = ly;
1188 } else if (hhave) /* only high is good, use it */
1189 y = hy;
1190 else /* nothing is good,this should never happen unless np=0, ???? */
1191 y = -(1 << 30);
1192 return y;
1193}
1194
1195static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah,
1196 u16 rateIndex, u16 freq, bool is2GHz)
1197{
1198 u16 numPiers, i;
1199 s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
1200 s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
1201 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
1202 struct cal_tgt_pow_legacy *pEepromTargetPwr;
1203 u8 *pFreqBin;
1204
1205 if (is2GHz) {
1206 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
1207 pEepromTargetPwr = eep->calTargetPower2G;
1208 pFreqBin = eep->calTarget_freqbin_2G;
1209 } else {
1210 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
1211 pEepromTargetPwr = eep->calTargetPower5G;
1212 pFreqBin = eep->calTarget_freqbin_5G;
1213 }
1214
1215 /*
1216 * create array of channels and targetpower from
1217 * targetpower piers stored on eeprom
1218 */
1219 for (i = 0; i < numPiers; i++) {
1220 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
1221 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
1222 }
1223
1224 /* interpolate to get target power for given frequency */
1225 return (u8) ar9003_hw_power_interpolate((s32) freq,
1226 freqArray,
1227 targetPowerArray, numPiers);
1228}
1229
1230static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah,
1231 u16 rateIndex,
1232 u16 freq, bool is2GHz)
1233{
1234 u16 numPiers, i;
1235 s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
1236 s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
1237 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
1238 struct cal_tgt_pow_ht *pEepromTargetPwr;
1239 u8 *pFreqBin;
1240
1241 if (is2GHz) {
1242 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
1243 pEepromTargetPwr = eep->calTargetPower2GHT20;
1244 pFreqBin = eep->calTarget_freqbin_2GHT20;
1245 } else {
1246 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
1247 pEepromTargetPwr = eep->calTargetPower5GHT20;
1248 pFreqBin = eep->calTarget_freqbin_5GHT20;
1249 }
1250
1251 /*
1252 * create array of channels and targetpower
1253 * from targetpower piers stored on eeprom
1254 */
1255 for (i = 0; i < numPiers; i++) {
1256 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
1257 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
1258 }
1259
1260 /* interpolate to get target power for given frequency */
1261 return (u8) ar9003_hw_power_interpolate((s32) freq,
1262 freqArray,
1263 targetPowerArray, numPiers);
1264}
1265
1266static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah,
1267 u16 rateIndex,
1268 u16 freq, bool is2GHz)
1269{
1270 u16 numPiers, i;
1271 s32 targetPowerArray[AR9300_NUM_5G_40_TARGET_POWERS];
1272 s32 freqArray[AR9300_NUM_5G_40_TARGET_POWERS];
1273 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
1274 struct cal_tgt_pow_ht *pEepromTargetPwr;
1275 u8 *pFreqBin;
1276
1277 if (is2GHz) {
1278 numPiers = AR9300_NUM_2G_40_TARGET_POWERS;
1279 pEepromTargetPwr = eep->calTargetPower2GHT40;
1280 pFreqBin = eep->calTarget_freqbin_2GHT40;
1281 } else {
1282 numPiers = AR9300_NUM_5G_40_TARGET_POWERS;
1283 pEepromTargetPwr = eep->calTargetPower5GHT40;
1284 pFreqBin = eep->calTarget_freqbin_5GHT40;
1285 }
1286
1287 /*
1288 * create array of channels and targetpower from
1289 * targetpower piers stored on eeprom
1290 */
1291 for (i = 0; i < numPiers; i++) {
1292 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
1293 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
1294 }
1295
1296 /* interpolate to get target power for given frequency */
1297 return (u8) ar9003_hw_power_interpolate((s32) freq,
1298 freqArray,
1299 targetPowerArray, numPiers);
1300}
1301
1302static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah,
1303 u16 rateIndex, u16 freq)
1304{
1305 u16 numPiers = AR9300_NUM_2G_CCK_TARGET_POWERS, i;
1306 s32 targetPowerArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
1307 s32 freqArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
1308 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
1309 struct cal_tgt_pow_legacy *pEepromTargetPwr = eep->calTargetPowerCck;
1310 u8 *pFreqBin = eep->calTarget_freqbin_Cck;
1311
1312 /*
1313 * create array of channels and targetpower from
1314 * targetpower piers stored on eeprom
1315 */
1316 for (i = 0; i < numPiers; i++) {
1317 freqArray[i] = FBIN2FREQ(pFreqBin[i], 1);
1318 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
1319 }
1320
1321 /* interpolate to get target power for given frequency */
1322 return (u8) ar9003_hw_power_interpolate((s32) freq,
1323 freqArray,
1324 targetPowerArray, numPiers);
1325}
1326
1327/* Set tx power registers to array of values passed in */
1328static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
1329{
1330#define POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
1331 /* make sure forced gain is not set */
1332 REG_WRITE(ah, 0xa458, 0);
1333
1334 /* Write the OFDM power per rate set */
1335
1336 /* 6 (LSB), 9, 12, 18 (MSB) */
1337 REG_WRITE(ah, 0xa3c0,
1338 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
1339 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 16) |
1340 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
1341 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
1342
1343 /* 24 (LSB), 36, 48, 54 (MSB) */
1344 REG_WRITE(ah, 0xa3c4,
1345 POW_SM(pPwrArray[ALL_TARGET_LEGACY_54], 24) |
1346 POW_SM(pPwrArray[ALL_TARGET_LEGACY_48], 16) |
1347 POW_SM(pPwrArray[ALL_TARGET_LEGACY_36], 8) |
1348 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
1349
1350 /* Write the CCK power per rate set */
1351
1352 /* 1L (LSB), reserved, 2L, 2S (MSB) */
1353 REG_WRITE(ah, 0xa3c8,
1354 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24) |
1355 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
1356 /* POW_SM(txPowerTimes2, 8) | this is reserved for AR9003 */
1357 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0));
1358
1359 /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
1360 REG_WRITE(ah, 0xa3cc,
1361 POW_SM(pPwrArray[ALL_TARGET_LEGACY_11S], 24) |
1362 POW_SM(pPwrArray[ALL_TARGET_LEGACY_11L], 16) |
1363 POW_SM(pPwrArray[ALL_TARGET_LEGACY_5S], 8) |
1364 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
1365 );
1366
1367 /* Write the HT20 power per rate set */
1368
1369 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
1370 REG_WRITE(ah, 0xa3d0,
1371 POW_SM(pPwrArray[ALL_TARGET_HT20_5], 24) |
1372 POW_SM(pPwrArray[ALL_TARGET_HT20_4], 16) |
1373 POW_SM(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19], 8) |
1374 POW_SM(pPwrArray[ALL_TARGET_HT20_0_8_16], 0)
1375 );
1376
1377 /* 6 (LSB), 7, 12, 13 (MSB) */
1378 REG_WRITE(ah, 0xa3d4,
1379 POW_SM(pPwrArray[ALL_TARGET_HT20_13], 24) |
1380 POW_SM(pPwrArray[ALL_TARGET_HT20_12], 16) |
1381 POW_SM(pPwrArray[ALL_TARGET_HT20_7], 8) |
1382 POW_SM(pPwrArray[ALL_TARGET_HT20_6], 0)
1383 );
1384
1385 /* 14 (LSB), 15, 20, 21 */
1386 REG_WRITE(ah, 0xa3e4,
1387 POW_SM(pPwrArray[ALL_TARGET_HT20_21], 24) |
1388 POW_SM(pPwrArray[ALL_TARGET_HT20_20], 16) |
1389 POW_SM(pPwrArray[ALL_TARGET_HT20_15], 8) |
1390 POW_SM(pPwrArray[ALL_TARGET_HT20_14], 0)
1391 );
1392
1393 /* Mixed HT20 and HT40 rates */
1394
1395 /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
1396 REG_WRITE(ah, 0xa3e8,
1397 POW_SM(pPwrArray[ALL_TARGET_HT40_23], 24) |
1398 POW_SM(pPwrArray[ALL_TARGET_HT40_22], 16) |
1399 POW_SM(pPwrArray[ALL_TARGET_HT20_23], 8) |
1400 POW_SM(pPwrArray[ALL_TARGET_HT20_22], 0)
1401 );
1402
1403 /*
1404 * Write the HT40 power per rate set
1405 * correct PAR difference between HT40 and HT20/LEGACY
1406 * 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB)
1407 */
1408 REG_WRITE(ah, 0xa3d8,
1409 POW_SM(pPwrArray[ALL_TARGET_HT40_5], 24) |
1410 POW_SM(pPwrArray[ALL_TARGET_HT40_4], 16) |
1411 POW_SM(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
1412 POW_SM(pPwrArray[ALL_TARGET_HT40_0_8_16], 0)
1413 );
1414
1415 /* 6 (LSB), 7, 12, 13 (MSB) */
1416 REG_WRITE(ah, 0xa3dc,
1417 POW_SM(pPwrArray[ALL_TARGET_HT40_13], 24) |
1418 POW_SM(pPwrArray[ALL_TARGET_HT40_12], 16) |
1419 POW_SM(pPwrArray[ALL_TARGET_HT40_7], 8) |
1420 POW_SM(pPwrArray[ALL_TARGET_HT40_6], 0)
1421 );
1422
1423 /* 14 (LSB), 15, 20, 21 */
1424 REG_WRITE(ah, 0xa3ec,
1425 POW_SM(pPwrArray[ALL_TARGET_HT40_21], 24) |
1426 POW_SM(pPwrArray[ALL_TARGET_HT40_20], 16) |
1427 POW_SM(pPwrArray[ALL_TARGET_HT40_15], 8) |
1428 POW_SM(pPwrArray[ALL_TARGET_HT40_14], 0)
1429 );
1430
1431 return 0;
1432#undef POW_SM
1433}
1434
1435static void ar9003_hw_set_target_power_eeprom(struct ath_hw *ah, u16 freq)
1436{
1437 u8 targetPowerValT2[ar9300RateSize];
1438 /* XXX: hard code for now, need to get from eeprom struct */
1439 u8 ht40PowerIncForPdadc = 0;
1440 bool is2GHz = false;
1441 unsigned int i = 0;
1442 struct ath_common *common = ath9k_hw_common(ah);
1443
1444 if (freq < 4000)
1445 is2GHz = true;
1446
1447 targetPowerValT2[ALL_TARGET_LEGACY_6_24] =
1448 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_6_24, freq,
1449 is2GHz);
1450 targetPowerValT2[ALL_TARGET_LEGACY_36] =
1451 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_36, freq,
1452 is2GHz);
1453 targetPowerValT2[ALL_TARGET_LEGACY_48] =
1454 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_48, freq,
1455 is2GHz);
1456 targetPowerValT2[ALL_TARGET_LEGACY_54] =
1457 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_54, freq,
1458 is2GHz);
1459 targetPowerValT2[ALL_TARGET_LEGACY_1L_5L] =
1460 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_1L_5L,
1461 freq);
1462 targetPowerValT2[ALL_TARGET_LEGACY_5S] =
1463 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_5S, freq);
1464 targetPowerValT2[ALL_TARGET_LEGACY_11L] =
1465 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11L, freq);
1466 targetPowerValT2[ALL_TARGET_LEGACY_11S] =
1467 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11S, freq);
1468 targetPowerValT2[ALL_TARGET_HT20_0_8_16] =
1469 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
1470 is2GHz);
1471 targetPowerValT2[ALL_TARGET_HT20_1_3_9_11_17_19] =
1472 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
1473 freq, is2GHz);
1474 targetPowerValT2[ALL_TARGET_HT20_4] =
1475 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
1476 is2GHz);
1477 targetPowerValT2[ALL_TARGET_HT20_5] =
1478 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
1479 is2GHz);
1480 targetPowerValT2[ALL_TARGET_HT20_6] =
1481 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
1482 is2GHz);
1483 targetPowerValT2[ALL_TARGET_HT20_7] =
1484 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
1485 is2GHz);
1486 targetPowerValT2[ALL_TARGET_HT20_12] =
1487 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
1488 is2GHz);
1489 targetPowerValT2[ALL_TARGET_HT20_13] =
1490 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
1491 is2GHz);
1492 targetPowerValT2[ALL_TARGET_HT20_14] =
1493 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
1494 is2GHz);
1495 targetPowerValT2[ALL_TARGET_HT20_15] =
1496 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
1497 is2GHz);
1498 targetPowerValT2[ALL_TARGET_HT20_20] =
1499 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
1500 is2GHz);
1501 targetPowerValT2[ALL_TARGET_HT20_21] =
1502 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
1503 is2GHz);
1504 targetPowerValT2[ALL_TARGET_HT20_22] =
1505 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
1506 is2GHz);
1507 targetPowerValT2[ALL_TARGET_HT20_23] =
1508 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
1509 is2GHz);
1510 targetPowerValT2[ALL_TARGET_HT40_0_8_16] =
1511 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
1512 is2GHz) + ht40PowerIncForPdadc;
1513 targetPowerValT2[ALL_TARGET_HT40_1_3_9_11_17_19] =
1514 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
1515 freq,
1516 is2GHz) + ht40PowerIncForPdadc;
1517 targetPowerValT2[ALL_TARGET_HT40_4] =
1518 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
1519 is2GHz) + ht40PowerIncForPdadc;
1520 targetPowerValT2[ALL_TARGET_HT40_5] =
1521 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
1522 is2GHz) + ht40PowerIncForPdadc;
1523 targetPowerValT2[ALL_TARGET_HT40_6] =
1524 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
1525 is2GHz) + ht40PowerIncForPdadc;
1526 targetPowerValT2[ALL_TARGET_HT40_7] =
1527 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
1528 is2GHz) + ht40PowerIncForPdadc;
1529 targetPowerValT2[ALL_TARGET_HT40_12] =
1530 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
1531 is2GHz) + ht40PowerIncForPdadc;
1532 targetPowerValT2[ALL_TARGET_HT40_13] =
1533 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
1534 is2GHz) + ht40PowerIncForPdadc;
1535 targetPowerValT2[ALL_TARGET_HT40_14] =
1536 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
1537 is2GHz) + ht40PowerIncForPdadc;
1538 targetPowerValT2[ALL_TARGET_HT40_15] =
1539 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
1540 is2GHz) + ht40PowerIncForPdadc;
1541 targetPowerValT2[ALL_TARGET_HT40_20] =
1542 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
1543 is2GHz) + ht40PowerIncForPdadc;
1544 targetPowerValT2[ALL_TARGET_HT40_21] =
1545 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
1546 is2GHz) + ht40PowerIncForPdadc;
1547 targetPowerValT2[ALL_TARGET_HT40_22] =
1548 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
1549 is2GHz) + ht40PowerIncForPdadc;
1550 targetPowerValT2[ALL_TARGET_HT40_23] =
1551 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
1552 is2GHz) + ht40PowerIncForPdadc;
1553
1554 while (i < ar9300RateSize) {
1555 ath_print(common, ATH_DBG_EEPROM,
1556 "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
1557 i++;
1558
1559 ath_print(common, ATH_DBG_EEPROM,
1560 "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
1561 i++;
1562
1563 ath_print(common, ATH_DBG_EEPROM,
1564 "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
1565 i++;
1566
1567 ath_print(common, ATH_DBG_EEPROM,
1568 "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
1569 i++;
1570 }
1571
1572 /* Write target power array to registers */
1573 ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
1574}
1575
1576static int ar9003_hw_cal_pier_get(struct ath_hw *ah,
1577 int mode,
1578 int ipier,
1579 int ichain,
1580 int *pfrequency,
1581 int *pcorrection,
1582 int *ptemperature, int *pvoltage)
1583{
1584 u8 *pCalPier;
1585 struct ar9300_cal_data_per_freq_op_loop *pCalPierStruct;
1586 int is2GHz;
1587 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
1588 struct ath_common *common = ath9k_hw_common(ah);
1589
1590 if (ichain >= AR9300_MAX_CHAINS) {
1591 ath_print(common, ATH_DBG_EEPROM,
1592 "Invalid chain index, must be less than %d\n",
1593 AR9300_MAX_CHAINS);
1594 return -1;
1595 }
1596
1597 if (mode) { /* 5GHz */
1598 if (ipier >= AR9300_NUM_5G_CAL_PIERS) {
1599 ath_print(common, ATH_DBG_EEPROM,
1600 "Invalid 5GHz cal pier index, must "
1601 "be less than %d\n",
1602 AR9300_NUM_5G_CAL_PIERS);
1603 return -1;
1604 }
1605 pCalPier = &(eep->calFreqPier5G[ipier]);
1606 pCalPierStruct = &(eep->calPierData5G[ichain][ipier]);
1607 is2GHz = 0;
1608 } else {
1609 if (ipier >= AR9300_NUM_2G_CAL_PIERS) {
1610 ath_print(common, ATH_DBG_EEPROM,
1611 "Invalid 2GHz cal pier index, must "
1612 "be less than %d\n", AR9300_NUM_2G_CAL_PIERS);
1613 return -1;
1614 }
1615
1616 pCalPier = &(eep->calFreqPier2G[ipier]);
1617 pCalPierStruct = &(eep->calPierData2G[ichain][ipier]);
1618 is2GHz = 1;
1619 }
1620
1621 *pfrequency = FBIN2FREQ(*pCalPier, is2GHz);
1622 *pcorrection = pCalPierStruct->refPower;
1623 *ptemperature = pCalPierStruct->tempMeas;
1624 *pvoltage = pCalPierStruct->voltMeas;
1625
1626 return 0;
1627}
1628
1629static int ar9003_hw_power_control_override(struct ath_hw *ah,
1630 int frequency,
1631 int *correction,
1632 int *voltage, int *temperature)
1633{
1634 int tempSlope = 0;
1635 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
1636
1637 REG_RMW(ah, AR_PHY_TPC_11_B0,
1638 (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
1639 AR_PHY_TPC_OLPC_GAIN_DELTA);
1640 REG_RMW(ah, AR_PHY_TPC_11_B1,
1641 (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
1642 AR_PHY_TPC_OLPC_GAIN_DELTA);
1643 REG_RMW(ah, AR_PHY_TPC_11_B2,
1644 (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
1645 AR_PHY_TPC_OLPC_GAIN_DELTA);
1646
1647 /* enable open loop power control on chip */
1648 REG_RMW(ah, AR_PHY_TPC_6_B0,
1649 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
1650 AR_PHY_TPC_6_ERROR_EST_MODE);
1651 REG_RMW(ah, AR_PHY_TPC_6_B1,
1652 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
1653 AR_PHY_TPC_6_ERROR_EST_MODE);
1654 REG_RMW(ah, AR_PHY_TPC_6_B2,
1655 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
1656 AR_PHY_TPC_6_ERROR_EST_MODE);
1657
1658 /*
1659 * enable temperature compensation
1660 * Need to use register names
1661 */
1662 if (frequency < 4000)
1663 tempSlope = eep->modalHeader2G.tempSlope;
1664 else
1665 tempSlope = eep->modalHeader5G.tempSlope;
1666
1667 REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope);
1668 REG_RMW_FIELD(ah, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE,
1669 temperature[0]);
1670
1671 return 0;
1672}
1673
1674/* Apply the recorded correction values. */
1675static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
1676{
1677 int ichain, ipier, npier;
1678 int mode;
1679 int lfrequency[AR9300_MAX_CHAINS],
1680 lcorrection[AR9300_MAX_CHAINS],
1681 ltemperature[AR9300_MAX_CHAINS], lvoltage[AR9300_MAX_CHAINS];
1682 int hfrequency[AR9300_MAX_CHAINS],
1683 hcorrection[AR9300_MAX_CHAINS],
1684 htemperature[AR9300_MAX_CHAINS], hvoltage[AR9300_MAX_CHAINS];
1685 int fdiff;
1686 int correction[AR9300_MAX_CHAINS],
1687 voltage[AR9300_MAX_CHAINS], temperature[AR9300_MAX_CHAINS];
1688 int pfrequency, pcorrection, ptemperature, pvoltage;
1689 struct ath_common *common = ath9k_hw_common(ah);
1690
1691 mode = (frequency >= 4000);
1692 if (mode)
1693 npier = AR9300_NUM_5G_CAL_PIERS;
1694 else
1695 npier = AR9300_NUM_2G_CAL_PIERS;
1696
1697 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
1698 lfrequency[ichain] = 0;
1699 hfrequency[ichain] = 100000;
1700 }
1701 /* identify best lower and higher frequency calibration measurement */
1702 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
1703 for (ipier = 0; ipier < npier; ipier++) {
1704 if (!ar9003_hw_cal_pier_get(ah, mode, ipier, ichain,
1705 &pfrequency, &pcorrection,
1706 &ptemperature, &pvoltage)) {
1707 fdiff = frequency - pfrequency;
1708
1709 /*
1710 * this measurement is higher than
1711 * our desired frequency
1712 */
1713 if (fdiff <= 0) {
1714 if (hfrequency[ichain] <= 0 ||
1715 hfrequency[ichain] >= 100000 ||
1716 fdiff >
1717 (frequency - hfrequency[ichain])) {
1718 /*
1719 * new best higher
1720 * frequency measurement
1721 */
1722 hfrequency[ichain] = pfrequency;
1723 hcorrection[ichain] =
1724 pcorrection;
1725 htemperature[ichain] =
1726 ptemperature;
1727 hvoltage[ichain] = pvoltage;
1728 }
1729 }
1730 if (fdiff >= 0) {
1731 if (lfrequency[ichain] <= 0
1732 || fdiff <
1733 (frequency - lfrequency[ichain])) {
1734 /*
1735 * new best lower
1736 * frequency measurement
1737 */
1738 lfrequency[ichain] = pfrequency;
1739 lcorrection[ichain] =
1740 pcorrection;
1741 ltemperature[ichain] =
1742 ptemperature;
1743 lvoltage[ichain] = pvoltage;
1744 }
1745 }
1746 }
1747 }
1748 }
1749
1750 /* interpolate */
1751 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
1752 ath_print(common, ATH_DBG_EEPROM,
1753 "ch=%d f=%d low=%d %d h=%d %d\n",
1754 ichain, frequency, lfrequency[ichain],
1755 lcorrection[ichain], hfrequency[ichain],
1756 hcorrection[ichain]);
1757 /* they're the same, so just pick one */
1758 if (hfrequency[ichain] == lfrequency[ichain]) {
1759 correction[ichain] = lcorrection[ichain];
1760 voltage[ichain] = lvoltage[ichain];
1761 temperature[ichain] = ltemperature[ichain];
1762 }
1763 /* the low frequency is good */
1764 else if (frequency - lfrequency[ichain] < 1000) {
1765 /* so is the high frequency, interpolate */
1766 if (hfrequency[ichain] - frequency < 1000) {
1767
1768 correction[ichain] = lcorrection[ichain] +
1769 (((frequency - lfrequency[ichain]) *
1770 (hcorrection[ichain] -
1771 lcorrection[ichain])) /
1772 (hfrequency[ichain] - lfrequency[ichain]));
1773
1774 temperature[ichain] = ltemperature[ichain] +
1775 (((frequency - lfrequency[ichain]) *
1776 (htemperature[ichain] -
1777 ltemperature[ichain])) /
1778 (hfrequency[ichain] - lfrequency[ichain]));
1779
1780 voltage[ichain] =
1781 lvoltage[ichain] +
1782 (((frequency -
1783 lfrequency[ichain]) * (hvoltage[ichain] -
1784 lvoltage[ichain]))
1785 / (hfrequency[ichain] -
1786 lfrequency[ichain]));
1787 }
1788 /* only low is good, use it */
1789 else {
1790 correction[ichain] = lcorrection[ichain];
1791 temperature[ichain] = ltemperature[ichain];
1792 voltage[ichain] = lvoltage[ichain];
1793 }
1794 }
1795 /* only high is good, use it */
1796 else if (hfrequency[ichain] - frequency < 1000) {
1797 correction[ichain] = hcorrection[ichain];
1798 temperature[ichain] = htemperature[ichain];
1799 voltage[ichain] = hvoltage[ichain];
1800 } else { /* nothing is good, presume 0???? */
1801 correction[ichain] = 0;
1802 temperature[ichain] = 0;
1803 voltage[ichain] = 0;
1804 }
1805 }
1806
1807 ar9003_hw_power_control_override(ah, frequency, correction, voltage,
1808 temperature);
1809
1810 ath_print(common, ATH_DBG_EEPROM,
1811 "for frequency=%d, calibration correction = %d %d %d\n",
1812 frequency, correction[0], correction[1], correction[2]);
1813
1814 return 0;
1815}
1816
1817static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
1818 struct ath9k_channel *chan, u16 cfgCtl,
1819 u8 twiceAntennaReduction,
1820 u8 twiceMaxRegulatoryPower,
1821 u8 powerLimit)
1822{
1823 ah->txpower_limit = powerLimit;
1824 ar9003_hw_set_target_power_eeprom(ah, chan->channel);
1825 ar9003_hw_calibration_apply(ah, chan->channel);
1826}
1827
1828static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah,
1829 u16 i, bool is2GHz)
1830{
1831 return AR_NO_SPUR;
1832}
1833
1834s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah)
1835{
1836 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
1837
1838 return (eep->baseEepHeader.txrxgain >> 4) & 0xf; /* bits 7:4 */
1839}
1840
1841s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah)
1842{
1843 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
1844
1845 return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */
1846}
1847
1848const struct eeprom_ops eep_ar9300_ops = {
1849 .check_eeprom = ath9k_hw_ar9300_check_eeprom,
1850 .get_eeprom = ath9k_hw_ar9300_get_eeprom,
1851 .fill_eeprom = ath9k_hw_ar9300_fill_eeprom,
1852 .get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver,
1853 .get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev,
1854 .get_num_ant_config = ath9k_hw_ar9300_get_num_ant_config,
1855 .get_eeprom_antenna_cfg = ath9k_hw_ar9300_get_eeprom_antenna_cfg,
1856 .set_board_values = ath9k_hw_ar9300_set_board_values,
1857 .set_addac = ath9k_hw_ar9300_set_addac,
1858 .set_txpower = ath9k_hw_ar9300_set_txpower,
1859 .get_spur_channel = ath9k_hw_ar9300_get_spur_channel
1860};
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
new file mode 100644
index 000000000000..d8c0318f416f
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
@@ -0,0 +1,323 @@
1#ifndef AR9003_EEPROM_H
2#define AR9003_EEPROM_H
3
4#include <linux/types.h>
5
6#define AR9300_EEP_VER 0xD000
7#define AR9300_EEP_VER_MINOR_MASK 0xFFF
8#define AR9300_EEP_MINOR_VER_1 0x1
9#define AR9300_EEP_MINOR_VER AR9300_EEP_MINOR_VER_1
10
11/* 16-bit offset location start of calibration struct */
12#define AR9300_EEP_START_LOC 256
13#define AR9300_NUM_5G_CAL_PIERS 8
14#define AR9300_NUM_2G_CAL_PIERS 3
15#define AR9300_NUM_5G_20_TARGET_POWERS 8
16#define AR9300_NUM_5G_40_TARGET_POWERS 8
17#define AR9300_NUM_2G_CCK_TARGET_POWERS 2
18#define AR9300_NUM_2G_20_TARGET_POWERS 3
19#define AR9300_NUM_2G_40_TARGET_POWERS 3
20/* #define AR9300_NUM_CTLS 21 */
21#define AR9300_NUM_CTLS_5G 9
22#define AR9300_NUM_CTLS_2G 12
23#define AR9300_CTL_MODE_M 0xF
24#define AR9300_NUM_BAND_EDGES_5G 8
25#define AR9300_NUM_BAND_EDGES_2G 4
26#define AR9300_NUM_PD_GAINS 4
27#define AR9300_PD_GAINS_IN_MASK 4
28#define AR9300_PD_GAIN_ICEPTS 5
29#define AR9300_EEPROM_MODAL_SPURS 5
30#define AR9300_MAX_RATE_POWER 63
31#define AR9300_NUM_PDADC_VALUES 128
32#define AR9300_NUM_RATES 16
33#define AR9300_BCHAN_UNUSED 0xFF
34#define AR9300_MAX_PWR_RANGE_IN_HALF_DB 64
35#define AR9300_OPFLAGS_11A 0x01
36#define AR9300_OPFLAGS_11G 0x02
37#define AR9300_OPFLAGS_5G_HT40 0x04
38#define AR9300_OPFLAGS_2G_HT40 0x08
39#define AR9300_OPFLAGS_5G_HT20 0x10
40#define AR9300_OPFLAGS_2G_HT20 0x20
41#define AR9300_EEPMISC_BIG_ENDIAN 0x01
42#define AR9300_EEPMISC_WOW 0x02
43#define AR9300_CUSTOMER_DATA_SIZE 20
44
45#define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
46#define FBIN2FREQ(x, y) ((y) ? (2300 + x) : (4800 + 5 * x))
47#define AR9300_MAX_CHAINS 3
48#define AR9300_ANT_16S 25
49#define AR9300_FUTURE_MODAL_SZ 6
50
51#define AR9300_NUM_ANT_CHAIN_FIELDS 7
52#define AR9300_NUM_ANT_COMMON_FIELDS 4
53#define AR9300_SIZE_ANT_CHAIN_FIELD 3
54#define AR9300_SIZE_ANT_COMMON_FIELD 4
55#define AR9300_ANT_CHAIN_MASK 0x7
56#define AR9300_ANT_COMMON_MASK 0xf
57#define AR9300_CHAIN_0_IDX 0
58#define AR9300_CHAIN_1_IDX 1
59#define AR9300_CHAIN_2_IDX 2
60
61#define AR928X_NUM_ANT_CHAIN_FIELDS 6
62#define AR928X_SIZE_ANT_CHAIN_FIELD 2
63#define AR928X_ANT_CHAIN_MASK 0x3
64
65/* Delta from which to start power to pdadc table */
66/* This offset is used in both open loop and closed loop power control
67 * schemes. In open loop power control, it is not really needed, but for
68 * the "sake of consistency" it was kept. For certain AP designs, this
69 * value is overwritten by the value in the flag "pwrTableOffset" just
70 * before writing the pdadc vs pwr into the chip registers.
71 */
72#define AR9300_PWR_TABLE_OFFSET 0
73
74/* enable flags for voltage and temp compensation */
75#define ENABLE_TEMP_COMPENSATION 0x01
76#define ENABLE_VOLT_COMPENSATION 0x02
77/* byte addressable */
78#define AR9300_EEPROM_SIZE (16*1024)
79#define FIXED_CCA_THRESHOLD 15
80
81#define AR9300_BASE_ADDR 0x3ff
82
83enum targetPowerHTRates {
84 HT_TARGET_RATE_0_8_16,
85 HT_TARGET_RATE_1_3_9_11_17_19,
86 HT_TARGET_RATE_4,
87 HT_TARGET_RATE_5,
88 HT_TARGET_RATE_6,
89 HT_TARGET_RATE_7,
90 HT_TARGET_RATE_12,
91 HT_TARGET_RATE_13,
92 HT_TARGET_RATE_14,
93 HT_TARGET_RATE_15,
94 HT_TARGET_RATE_20,
95 HT_TARGET_RATE_21,
96 HT_TARGET_RATE_22,
97 HT_TARGET_RATE_23
98};
99
100enum targetPowerLegacyRates {
101 LEGACY_TARGET_RATE_6_24,
102 LEGACY_TARGET_RATE_36,
103 LEGACY_TARGET_RATE_48,
104 LEGACY_TARGET_RATE_54
105};
106
107enum targetPowerCckRates {
108 LEGACY_TARGET_RATE_1L_5L,
109 LEGACY_TARGET_RATE_5S,
110 LEGACY_TARGET_RATE_11L,
111 LEGACY_TARGET_RATE_11S
112};
113
114enum ar9300_Rates {
115 ALL_TARGET_LEGACY_6_24,
116 ALL_TARGET_LEGACY_36,
117 ALL_TARGET_LEGACY_48,
118 ALL_TARGET_LEGACY_54,
119 ALL_TARGET_LEGACY_1L_5L,
120 ALL_TARGET_LEGACY_5S,
121 ALL_TARGET_LEGACY_11L,
122 ALL_TARGET_LEGACY_11S,
123 ALL_TARGET_HT20_0_8_16,
124 ALL_TARGET_HT20_1_3_9_11_17_19,
125 ALL_TARGET_HT20_4,
126 ALL_TARGET_HT20_5,
127 ALL_TARGET_HT20_6,
128 ALL_TARGET_HT20_7,
129 ALL_TARGET_HT20_12,
130 ALL_TARGET_HT20_13,
131 ALL_TARGET_HT20_14,
132 ALL_TARGET_HT20_15,
133 ALL_TARGET_HT20_20,
134 ALL_TARGET_HT20_21,
135 ALL_TARGET_HT20_22,
136 ALL_TARGET_HT20_23,
137 ALL_TARGET_HT40_0_8_16,
138 ALL_TARGET_HT40_1_3_9_11_17_19,
139 ALL_TARGET_HT40_4,
140 ALL_TARGET_HT40_5,
141 ALL_TARGET_HT40_6,
142 ALL_TARGET_HT40_7,
143 ALL_TARGET_HT40_12,
144 ALL_TARGET_HT40_13,
145 ALL_TARGET_HT40_14,
146 ALL_TARGET_HT40_15,
147 ALL_TARGET_HT40_20,
148 ALL_TARGET_HT40_21,
149 ALL_TARGET_HT40_22,
150 ALL_TARGET_HT40_23,
151 ar9300RateSize,
152};
153
154
155struct eepFlags {
156 u8 opFlags;
157 u8 eepMisc;
158} __packed;
159
160enum CompressAlgorithm {
161 _CompressNone = 0,
162 _CompressLzma,
163 _CompressPairs,
164 _CompressBlock,
165 _Compress4,
166 _Compress5,
167 _Compress6,
168 _Compress7,
169};
170
171struct ar9300_base_eep_hdr {
172 u16 regDmn[2];
173 /* 4 bits tx and 4 bits rx */
174 u8 txrxMask;
175 struct eepFlags opCapFlags;
176 u8 rfSilent;
177 u8 blueToothOptions;
178 u8 deviceCap;
179 /* takes lower byte in eeprom location */
180 u8 deviceType;
181 /* offset in dB to be added to beginning
182 * of pdadc table in calibration
183 */
184 int8_t pwrTableOffset;
185 u8 params_for_tuning_caps[2];
186 /*
187 * bit0 - enable tx temp comp
188 * bit1 - enable tx volt comp
189 * bit2 - enable fastClock - default to 1
190 * bit3 - enable doubling - default to 1
191 * bit4 - enable internal regulator - default to 1
192 */
193 u8 featureEnable;
194 /* misc flags: bit0 - turn down drivestrength */
195 u8 miscConfiguration;
196 u8 eepromWriteEnableGpio;
197 u8 wlanDisableGpio;
198 u8 wlanLedGpio;
199 u8 rxBandSelectGpio;
200 u8 txrxgain;
201 /* SW controlled internal regulator fields */
202 u32 swreg;
203} __packed;
204
205struct ar9300_modal_eep_header {
206 /* 4 idle, t1, t2, b (4 bits per setting) */
207 u32 antCtrlCommon;
208 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
209 u32 antCtrlCommon2;
210 /* 6 idle, t, r, rx1, rx12, b (2 bits each) */
211 u16 antCtrlChain[AR9300_MAX_CHAINS];
212 /* 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
213 u8 xatten1DB[AR9300_MAX_CHAINS];
214 /* 3 xatten1_margin for merlin (0xa20c/b20c 16:12 */
215 u8 xatten1Margin[AR9300_MAX_CHAINS];
216 int8_t tempSlope;
217 int8_t voltSlope;
218 /* spur channels in usual fbin coding format */
219 u8 spurChans[AR9300_EEPROM_MODAL_SPURS];
220 /* 3 Check if the register is per chain */
221 int8_t noiseFloorThreshCh[AR9300_MAX_CHAINS];
222 u8 ob[AR9300_MAX_CHAINS];
223 u8 db_stage2[AR9300_MAX_CHAINS];
224 u8 db_stage3[AR9300_MAX_CHAINS];
225 u8 db_stage4[AR9300_MAX_CHAINS];
226 u8 xpaBiasLvl;
227 u8 txFrameToDataStart;
228 u8 txFrameToPaOn;
229 u8 txClip;
230 int8_t antennaGain;
231 u8 switchSettling;
232 int8_t adcDesiredSize;
233 u8 txEndToXpaOff;
234 u8 txEndToRxOn;
235 u8 txFrameToXpaOn;
236 u8 thresh62;
237 u8 futureModal[32];
238} __packed;
239
240struct ar9300_cal_data_per_freq_op_loop {
241 int8_t refPower;
242 /* pdadc voltage at power measurement */
243 u8 voltMeas;
244 /* pcdac used for power measurement */
245 u8 tempMeas;
246 /* range is -60 to -127 create a mapping equation 1db resolution */
247 int8_t rxNoisefloorCal;
248 /*range is same as noisefloor */
249 int8_t rxNoisefloorPower;
250 /* temp measured when noisefloor cal was performed */
251 u8 rxTempMeas;
252} __packed;
253
254struct cal_tgt_pow_legacy {
255 u8 tPow2x[4];
256} __packed;
257
258struct cal_tgt_pow_ht {
259 u8 tPow2x[14];
260} __packed;
261
262struct cal_ctl_edge_pwr {
263 u8 tPower:6,
264 flag:2;
265} __packed;
266
267struct cal_ctl_data_2g {
268 struct cal_ctl_edge_pwr ctlEdges[AR9300_NUM_BAND_EDGES_2G];
269} __packed;
270
271struct cal_ctl_data_5g {
272 struct cal_ctl_edge_pwr ctlEdges[AR9300_NUM_BAND_EDGES_5G];
273} __packed;
274
275struct ar9300_eeprom {
276 u8 eepromVersion;
277 u8 templateVersion;
278 u8 macAddr[6];
279 u8 custData[AR9300_CUSTOMER_DATA_SIZE];
280
281 struct ar9300_base_eep_hdr baseEepHeader;
282
283 struct ar9300_modal_eep_header modalHeader2G;
284 u8 calFreqPier2G[AR9300_NUM_2G_CAL_PIERS];
285 struct ar9300_cal_data_per_freq_op_loop
286 calPierData2G[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS];
287 u8 calTarget_freqbin_Cck[AR9300_NUM_2G_CCK_TARGET_POWERS];
288 u8 calTarget_freqbin_2G[AR9300_NUM_2G_20_TARGET_POWERS];
289 u8 calTarget_freqbin_2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
290 u8 calTarget_freqbin_2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
291 struct cal_tgt_pow_legacy
292 calTargetPowerCck[AR9300_NUM_2G_CCK_TARGET_POWERS];
293 struct cal_tgt_pow_legacy
294 calTargetPower2G[AR9300_NUM_2G_20_TARGET_POWERS];
295 struct cal_tgt_pow_ht
296 calTargetPower2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
297 struct cal_tgt_pow_ht
298 calTargetPower2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
299 u8 ctlIndex_2G[AR9300_NUM_CTLS_2G];
300 u8 ctl_freqbin_2G[AR9300_NUM_CTLS_2G][AR9300_NUM_BAND_EDGES_2G];
301 struct cal_ctl_data_2g ctlPowerData_2G[AR9300_NUM_CTLS_2G];
302 struct ar9300_modal_eep_header modalHeader5G;
303 u8 calFreqPier5G[AR9300_NUM_5G_CAL_PIERS];
304 struct ar9300_cal_data_per_freq_op_loop
305 calPierData5G[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS];
306 u8 calTarget_freqbin_5G[AR9300_NUM_5G_20_TARGET_POWERS];
307 u8 calTarget_freqbin_5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
308 u8 calTarget_freqbin_5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
309 struct cal_tgt_pow_legacy
310 calTargetPower5G[AR9300_NUM_5G_20_TARGET_POWERS];
311 struct cal_tgt_pow_ht
312 calTargetPower5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
313 struct cal_tgt_pow_ht
314 calTargetPower5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
315 u8 ctlIndex_5G[AR9300_NUM_CTLS_5G];
316 u8 ctl_freqbin_5G[AR9300_NUM_CTLS_5G][AR9300_NUM_BAND_EDGES_5G];
317 struct cal_ctl_data_5g ctlPowerData_5G[AR9300_NUM_CTLS_5G];
318} __packed;
319
320s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah);
321s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah);
322
323#endif
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_hw.c b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
new file mode 100644
index 000000000000..b15309caf1da
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
@@ -0,0 +1,205 @@
1/*
2 * Copyright (c) 2008-2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "hw.h"
18#include "ar9003_mac.h"
19#include "ar9003_initvals.h"
20
21/* General hardware code for the AR9003 hadware family */
22
23static bool ar9003_hw_macversion_supported(u32 macversion)
24{
25 switch (macversion) {
26 case AR_SREV_VERSION_9300:
27 return true;
28 default:
29 break;
30 }
31 return false;
32}
33
34/* AR9003 2.0 - new INI format (pre, core, post arrays per subsystem) */
35/*
36 * XXX: move TX/RX gain INI to its own init_mode_gain_regs after
37 * ensuring it does not affect hardware bring up
38 */
39static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
40{
41 /* mac */
42 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
43 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
44 ar9300_2p0_mac_core,
45 ARRAY_SIZE(ar9300_2p0_mac_core), 2);
46 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
47 ar9300_2p0_mac_postamble,
48 ARRAY_SIZE(ar9300_2p0_mac_postamble), 5);
49
50 /* bb */
51 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
52 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
53 ar9300_2p0_baseband_core,
54 ARRAY_SIZE(ar9300_2p0_baseband_core), 2);
55 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
56 ar9300_2p0_baseband_postamble,
57 ARRAY_SIZE(ar9300_2p0_baseband_postamble), 5);
58
59 /* radio */
60 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
61 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
62 ar9300_2p0_radio_core,
63 ARRAY_SIZE(ar9300_2p0_radio_core), 2);
64 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
65 ar9300_2p0_radio_postamble,
66 ARRAY_SIZE(ar9300_2p0_radio_postamble), 5);
67
68 /* soc */
69 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
70 ar9300_2p0_soc_preamble,
71 ARRAY_SIZE(ar9300_2p0_soc_preamble), 2);
72 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
73 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
74 ar9300_2p0_soc_postamble,
75 ARRAY_SIZE(ar9300_2p0_soc_postamble), 5);
76
77 /* rx/tx gain */
78 INIT_INI_ARRAY(&ah->iniModesRxGain,
79 ar9300Common_rx_gain_table_2p0,
80 ARRAY_SIZE(ar9300Common_rx_gain_table_2p0), 2);
81 INIT_INI_ARRAY(&ah->iniModesTxGain,
82 ar9300Modes_lowest_ob_db_tx_gain_table_2p0,
83 ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p0),
84 5);
85
86 /* Load PCIE SERDES settings from INI */
87
88 /* Awake Setting */
89
90 INIT_INI_ARRAY(&ah->iniPcieSerdes,
91 ar9300PciePhy_pll_on_clkreq_disable_L1_2p0,
92 ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p0),
93 2);
94
95 /* Sleep Setting */
96
97 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
98 ar9300PciePhy_clkreq_enable_L1_2p0,
99 ARRAY_SIZE(ar9300PciePhy_clkreq_enable_L1_2p0),
100 2);
101
102 /* Fast clock modal settings */
103 INIT_INI_ARRAY(&ah->iniModesAdditional,
104 ar9300Modes_fast_clock_2p0,
105 ARRAY_SIZE(ar9300Modes_fast_clock_2p0),
106 3);
107}
108
109static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
110{
111 switch (ar9003_hw_get_tx_gain_idx(ah)) {
112 case 0:
113 default:
114 INIT_INI_ARRAY(&ah->iniModesTxGain,
115 ar9300Modes_lowest_ob_db_tx_gain_table_2p0,
116 ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p0),
117 5);
118 break;
119 case 1:
120 INIT_INI_ARRAY(&ah->iniModesTxGain,
121 ar9300Modes_high_ob_db_tx_gain_table_2p0,
122 ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p0),
123 5);
124 break;
125 case 2:
126 INIT_INI_ARRAY(&ah->iniModesTxGain,
127 ar9300Modes_low_ob_db_tx_gain_table_2p0,
128 ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p0),
129 5);
130 break;
131 }
132}
133
134static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
135{
136 switch (ar9003_hw_get_rx_gain_idx(ah)) {
137 case 0:
138 default:
139 INIT_INI_ARRAY(&ah->iniModesRxGain, ar9300Common_rx_gain_table_2p0,
140 ARRAY_SIZE(ar9300Common_rx_gain_table_2p0),
141 2);
142 break;
143 case 1:
144 INIT_INI_ARRAY(&ah->iniModesRxGain,
145 ar9300Common_wo_xlna_rx_gain_table_2p0,
146 ARRAY_SIZE(ar9300Common_wo_xlna_rx_gain_table_2p0),
147 2);
148 break;
149 }
150}
151
152/* set gain table pointers according to values read from the eeprom */
153static void ar9003_hw_init_mode_gain_regs(struct ath_hw *ah)
154{
155 ar9003_tx_gain_table_apply(ah);
156 ar9003_rx_gain_table_apply(ah);
157}
158
159/*
160 * Helper for ASPM support.
161 *
162 * Disable PLL when in L0s as well as receiver clock when in L1.
163 * This power saving option must be enabled through the SerDes.
164 *
165 * Programming the SerDes must go through the same 288 bit serial shift
166 * register as the other analog registers. Hence the 9 writes.
167 */
168static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
169 int restore,
170 int power_off)
171{
172 if (ah->is_pciexpress != true)
173 return;
174
175 /* Do not touch SerDes registers */
176 if (ah->config.pcie_powersave_enable == 2)
177 return;
178
179 /* Nothing to do on restore for 11N */
180 if (!restore) {
181 /* set bit 19 to allow forcing of pcie core into L1 state */
182 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
183
184 /* Several PCIe massages to ensure proper behaviour */
185 if (ah->config.pcie_waen)
186 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
187 }
188}
189
190/* Sets up the AR9003 hardware familiy callbacks */
191void ar9003_hw_attach_ops(struct ath_hw *ah)
192{
193 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
194 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
195
196 priv_ops->init_mode_regs = ar9003_hw_init_mode_regs;
197 priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs;
198 priv_ops->macversion_supported = ar9003_hw_macversion_supported;
199
200 ops->config_pci_powersave = ar9003_hw_configpcipowersave;
201
202 ar9003_hw_attach_phy_ops(ah);
203 ar9003_hw_attach_calib_ops(ah);
204 ar9003_hw_attach_mac_ops(ah);
205}
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_initvals.h b/drivers/net/wireless/ath/ath9k/ar9003_initvals.h
new file mode 100644
index 000000000000..a131cd10ef29
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/ar9003_initvals.h
@@ -0,0 +1,1784 @@
1/*
2 * Copyright (c) 2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef INITVALS_9003_H
18#define INITVALS_9003_H
19
20/* AR9003 2.0 */
21
22static const u32 ar9300_2p0_radio_postamble[][5] = {
23 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
24 {0x0001609c, 0x0dd08f29, 0x0dd08f29, 0x0b283f31, 0x0b283f31},
25 {0x000160ac, 0xa4653c00, 0xa4653c00, 0x24652800, 0x24652800},
26 {0x000160b0, 0x03284f3e, 0x03284f3e, 0x05d08f20, 0x05d08f20},
27 {0x0001610c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
28 {0x0001650c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
29 {0x0001690c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
30};
31
32static const u32 ar9300Modes_lowest_ob_db_tx_gain_table_2p0[][5] = {
33 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
34 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
35 {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
36 {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
37 {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
38 {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
39 {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
40 {0x0000a514, 0x1c000223, 0x1c000223, 0x12000400, 0x12000400},
41 {0x0000a518, 0x21020220, 0x21020220, 0x16000402, 0x16000402},
42 {0x0000a51c, 0x27020223, 0x27020223, 0x19000404, 0x19000404},
43 {0x0000a520, 0x2b022220, 0x2b022220, 0x1c000603, 0x1c000603},
44 {0x0000a524, 0x2f022222, 0x2f022222, 0x21000a02, 0x21000a02},
45 {0x0000a528, 0x34022225, 0x34022225, 0x25000a04, 0x25000a04},
46 {0x0000a52c, 0x3a02222a, 0x3a02222a, 0x28000a20, 0x28000a20},
47 {0x0000a530, 0x3e02222c, 0x3e02222c, 0x2c000e20, 0x2c000e20},
48 {0x0000a534, 0x4202242a, 0x4202242a, 0x30000e22, 0x30000e22},
49 {0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24},
50 {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640},
51 {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660},
52 {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861},
53 {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81},
54 {0x0000a54c, 0x5c04286b, 0x5c04286b, 0x47001a83, 0x47001a83},
55 {0x0000a550, 0x61042a6c, 0x61042a6c, 0x4a001c84, 0x4a001c84},
56 {0x0000a554, 0x66062a6c, 0x66062a6c, 0x4e001ce3, 0x4e001ce3},
57 {0x0000a558, 0x6b062e6c, 0x6b062e6c, 0x52001ce5, 0x52001ce5},
58 {0x0000a55c, 0x7006308c, 0x7006308c, 0x56001ce9, 0x56001ce9},
59 {0x0000a560, 0x730a308a, 0x730a308a, 0x5a001ceb, 0x5a001ceb},
60 {0x0000a564, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
61 {0x0000a568, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
62 {0x0000a56c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
63 {0x0000a570, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
64 {0x0000a574, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
65 {0x0000a578, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
66 {0x0000a57c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
67 {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
68 {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002},
69 {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004},
70 {0x0000a58c, 0x10800023, 0x10800023, 0x0b800200, 0x0b800200},
71 {0x0000a590, 0x16800220, 0x16800220, 0x0f800202, 0x0f800202},
72 {0x0000a594, 0x1c800223, 0x1c800223, 0x12800400, 0x12800400},
73 {0x0000a598, 0x21820220, 0x21820220, 0x16800402, 0x16800402},
74 {0x0000a59c, 0x27820223, 0x27820223, 0x19800404, 0x19800404},
75 {0x0000a5a0, 0x2b822220, 0x2b822220, 0x1c800603, 0x1c800603},
76 {0x0000a5a4, 0x2f822222, 0x2f822222, 0x21800a02, 0x21800a02},
77 {0x0000a5a8, 0x34822225, 0x34822225, 0x25800a04, 0x25800a04},
78 {0x0000a5ac, 0x3a82222a, 0x3a82222a, 0x28800a20, 0x28800a20},
79 {0x0000a5b0, 0x3e82222c, 0x3e82222c, 0x2c800e20, 0x2c800e20},
80 {0x0000a5b4, 0x4282242a, 0x4282242a, 0x30800e22, 0x30800e22},
81 {0x0000a5b8, 0x4782244a, 0x4782244a, 0x34800e24, 0x34800e24},
82 {0x0000a5bc, 0x4b82244c, 0x4b82244c, 0x38801640, 0x38801640},
83 {0x0000a5c0, 0x4e82246c, 0x4e82246c, 0x3c801660, 0x3c801660},
84 {0x0000a5c4, 0x5382266c, 0x5382266c, 0x3f801861, 0x3f801861},
85 {0x0000a5c8, 0x5782286c, 0x5782286c, 0x43801a81, 0x43801a81},
86 {0x0000a5cc, 0x5c84286b, 0x5c84286b, 0x47801a83, 0x47801a83},
87 {0x0000a5d0, 0x61842a6c, 0x61842a6c, 0x4a801c84, 0x4a801c84},
88 {0x0000a5d4, 0x66862a6c, 0x66862a6c, 0x4e801ce3, 0x4e801ce3},
89 {0x0000a5d8, 0x6b862e6c, 0x6b862e6c, 0x52801ce5, 0x52801ce5},
90 {0x0000a5dc, 0x7086308c, 0x7086308c, 0x56801ce9, 0x56801ce9},
91 {0x0000a5e0, 0x738a308a, 0x738a308a, 0x5a801ceb, 0x5a801ceb},
92 {0x0000a5e4, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
93 {0x0000a5e8, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
94 {0x0000a5ec, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
95 {0x0000a5f0, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
96 {0x0000a5f4, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
97 {0x0000a5f8, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
98 {0x0000a5fc, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
99 {0x00016044, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
100 {0x00016048, 0x60001a61, 0x60001a61, 0x60001a61, 0x60001a61},
101 {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
102 {0x00016444, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
103 {0x00016448, 0x60001a61, 0x60001a61, 0x60001a61, 0x60001a61},
104 {0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
105 {0x00016844, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
106 {0x00016848, 0x60001a61, 0x60001a61, 0x60001a61, 0x60001a61},
107 {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
108};
109
110static const u32 ar9300Modes_fast_clock_2p0[][3] = {
111 /* Addr 5G_HT20 5G_HT40 */
112 {0x00001030, 0x00000268, 0x000004d0},
113 {0x00001070, 0x0000018c, 0x00000318},
114 {0x000010b0, 0x00000fd0, 0x00001fa0},
115 {0x00008014, 0x044c044c, 0x08980898},
116 {0x0000801c, 0x148ec02b, 0x148ec057},
117 {0x00008318, 0x000044c0, 0x00008980},
118 {0x00009e00, 0x03721821, 0x03721821},
119 {0x0000a230, 0x0000000b, 0x00000016},
120 {0x0000a254, 0x00000898, 0x00001130},
121};
122
123static const u32 ar9300_2p0_radio_core[][2] = {
124 /* Addr allmodes */
125 {0x00016000, 0x36db6db6},
126 {0x00016004, 0x6db6db40},
127 {0x00016008, 0x73f00000},
128 {0x0001600c, 0x00000000},
129 {0x00016040, 0x7f80fff8},
130 {0x0001604c, 0x76d005b5},
131 {0x00016050, 0x556cf031},
132 {0x00016054, 0x43449440},
133 {0x00016058, 0x0c51c92c},
134 {0x0001605c, 0x3db7fffc},
135 {0x00016060, 0xfffffffc},
136 {0x00016064, 0x000f0278},
137 {0x0001606c, 0x6db60000},
138 {0x00016080, 0x00000000},
139 {0x00016084, 0x0e48048c},
140 {0x00016088, 0x54214514},
141 {0x0001608c, 0x119f481e},
142 {0x00016090, 0x24926490},
143 {0x00016098, 0xd2888888},
144 {0x000160a0, 0x0a108ffe},
145 {0x000160a4, 0x812fc370},
146 {0x000160a8, 0x423c8000},
147 {0x000160b4, 0x92480080},
148 {0x000160c0, 0x00adb6d0},
149 {0x000160c4, 0x6db6db60},
150 {0x000160c8, 0x6db6db6c},
151 {0x000160cc, 0x01e6c000},
152 {0x00016100, 0x3fffbe01},
153 {0x00016104, 0xfff80000},
154 {0x00016108, 0x00080010},
155 {0x00016140, 0x10804008},
156 {0x00016144, 0x02084080},
157 {0x00016148, 0x00000000},
158 {0x00016280, 0x058a0001},
159 {0x00016284, 0x3d840208},
160 {0x00016288, 0x01a20408},
161 {0x0001628c, 0x00038c07},
162 {0x00016290, 0x40000004},
163 {0x00016294, 0x458aa14f},
164 {0x00016380, 0x00000000},
165 {0x00016384, 0x00000000},
166 {0x00016388, 0x00800700},
167 {0x0001638c, 0x00800700},
168 {0x00016390, 0x00800700},
169 {0x00016394, 0x00000000},
170 {0x00016398, 0x00000000},
171 {0x0001639c, 0x00000000},
172 {0x000163a0, 0x00000001},
173 {0x000163a4, 0x00000001},
174 {0x000163a8, 0x00000000},
175 {0x000163ac, 0x00000000},
176 {0x000163b0, 0x00000000},
177 {0x000163b4, 0x00000000},
178 {0x000163b8, 0x00000000},
179 {0x000163bc, 0x00000000},
180 {0x000163c0, 0x000000a0},
181 {0x000163c4, 0x000c0000},
182 {0x000163c8, 0x14021402},
183 {0x000163cc, 0x00001402},
184 {0x000163d0, 0x00000000},
185 {0x000163d4, 0x00000000},
186 {0x00016400, 0x36db6db6},
187 {0x00016404, 0x6db6db40},
188 {0x00016408, 0x73f00000},
189 {0x0001640c, 0x00000000},
190 {0x00016440, 0x7f80fff8},
191 {0x0001644c, 0x76d005b5},
192 {0x00016450, 0x556cf031},
193 {0x00016454, 0x43449440},
194 {0x00016458, 0x0c51c92c},
195 {0x0001645c, 0x3db7fffc},
196 {0x00016460, 0xfffffffc},
197 {0x00016464, 0x000f0278},
198 {0x0001646c, 0x6db60000},
199 {0x00016500, 0x3fffbe01},
200 {0x00016504, 0xfff80000},
201 {0x00016508, 0x00080010},
202 {0x00016540, 0x10804008},
203 {0x00016544, 0x02084080},
204 {0x00016548, 0x00000000},
205 {0x00016780, 0x00000000},
206 {0x00016784, 0x00000000},
207 {0x00016788, 0x00800700},
208 {0x0001678c, 0x00800700},
209 {0x00016790, 0x00800700},
210 {0x00016794, 0x00000000},
211 {0x00016798, 0x00000000},
212 {0x0001679c, 0x00000000},
213 {0x000167a0, 0x00000001},
214 {0x000167a4, 0x00000001},
215 {0x000167a8, 0x00000000},
216 {0x000167ac, 0x00000000},
217 {0x000167b0, 0x00000000},
218 {0x000167b4, 0x00000000},
219 {0x000167b8, 0x00000000},
220 {0x000167bc, 0x00000000},
221 {0x000167c0, 0x000000a0},
222 {0x000167c4, 0x000c0000},
223 {0x000167c8, 0x14021402},
224 {0x000167cc, 0x00001402},
225 {0x000167d0, 0x00000000},
226 {0x000167d4, 0x00000000},
227 {0x00016800, 0x36db6db6},
228 {0x00016804, 0x6db6db40},
229 {0x00016808, 0x73f00000},
230 {0x0001680c, 0x00000000},
231 {0x00016840, 0x7f80fff8},
232 {0x0001684c, 0x76d005b5},
233 {0x00016850, 0x556cf031},
234 {0x00016854, 0x43449440},
235 {0x00016858, 0x0c51c92c},
236 {0x0001685c, 0x3db7fffc},
237 {0x00016860, 0xfffffffc},
238 {0x00016864, 0x000f0278},
239 {0x0001686c, 0x6db60000},
240 {0x00016900, 0x3fffbe01},
241 {0x00016904, 0xfff80000},
242 {0x00016908, 0x00080010},
243 {0x00016940, 0x10804008},
244 {0x00016944, 0x02084080},
245 {0x00016948, 0x00000000},
246 {0x00016b80, 0x00000000},
247 {0x00016b84, 0x00000000},
248 {0x00016b88, 0x00800700},
249 {0x00016b8c, 0x00800700},
250 {0x00016b90, 0x00800700},
251 {0x00016b94, 0x00000000},
252 {0x00016b98, 0x00000000},
253 {0x00016b9c, 0x00000000},
254 {0x00016ba0, 0x00000001},
255 {0x00016ba4, 0x00000001},
256 {0x00016ba8, 0x00000000},
257 {0x00016bac, 0x00000000},
258 {0x00016bb0, 0x00000000},
259 {0x00016bb4, 0x00000000},
260 {0x00016bb8, 0x00000000},
261 {0x00016bbc, 0x00000000},
262 {0x00016bc0, 0x000000a0},
263 {0x00016bc4, 0x000c0000},
264 {0x00016bc8, 0x14021402},
265 {0x00016bcc, 0x00001402},
266 {0x00016bd0, 0x00000000},
267 {0x00016bd4, 0x00000000},
268};
269
270static const u32 ar9300Common_rx_gain_table_merlin_2p0[][2] = {
271 /* Addr allmodes */
272 {0x0000a000, 0x02000101},
273 {0x0000a004, 0x02000102},
274 {0x0000a008, 0x02000103},
275 {0x0000a00c, 0x02000104},
276 {0x0000a010, 0x02000200},
277 {0x0000a014, 0x02000201},
278 {0x0000a018, 0x02000202},
279 {0x0000a01c, 0x02000203},
280 {0x0000a020, 0x02000204},
281 {0x0000a024, 0x02000205},
282 {0x0000a028, 0x02000208},
283 {0x0000a02c, 0x02000302},
284 {0x0000a030, 0x02000303},
285 {0x0000a034, 0x02000304},
286 {0x0000a038, 0x02000400},
287 {0x0000a03c, 0x02010300},
288 {0x0000a040, 0x02010301},
289 {0x0000a044, 0x02010302},
290 {0x0000a048, 0x02000500},
291 {0x0000a04c, 0x02010400},
292 {0x0000a050, 0x02020300},
293 {0x0000a054, 0x02020301},
294 {0x0000a058, 0x02020302},
295 {0x0000a05c, 0x02020303},
296 {0x0000a060, 0x02020400},
297 {0x0000a064, 0x02030300},
298 {0x0000a068, 0x02030301},
299 {0x0000a06c, 0x02030302},
300 {0x0000a070, 0x02030303},
301 {0x0000a074, 0x02030400},
302 {0x0000a078, 0x02040300},
303 {0x0000a07c, 0x02040301},
304 {0x0000a080, 0x02040302},
305 {0x0000a084, 0x02040303},
306 {0x0000a088, 0x02030500},
307 {0x0000a08c, 0x02040400},
308 {0x0000a090, 0x02050203},
309 {0x0000a094, 0x02050204},
310 {0x0000a098, 0x02050205},
311 {0x0000a09c, 0x02040500},
312 {0x0000a0a0, 0x02050301},
313 {0x0000a0a4, 0x02050302},
314 {0x0000a0a8, 0x02050303},
315 {0x0000a0ac, 0x02050400},
316 {0x0000a0b0, 0x02050401},
317 {0x0000a0b4, 0x02050402},
318 {0x0000a0b8, 0x02050403},
319 {0x0000a0bc, 0x02050500},
320 {0x0000a0c0, 0x02050501},
321 {0x0000a0c4, 0x02050502},
322 {0x0000a0c8, 0x02050503},
323 {0x0000a0cc, 0x02050504},
324 {0x0000a0d0, 0x02050600},
325 {0x0000a0d4, 0x02050601},
326 {0x0000a0d8, 0x02050602},
327 {0x0000a0dc, 0x02050603},
328 {0x0000a0e0, 0x02050604},
329 {0x0000a0e4, 0x02050700},
330 {0x0000a0e8, 0x02050701},
331 {0x0000a0ec, 0x02050702},
332 {0x0000a0f0, 0x02050703},
333 {0x0000a0f4, 0x02050704},
334 {0x0000a0f8, 0x02050705},
335 {0x0000a0fc, 0x02050708},
336 {0x0000a100, 0x02050709},
337 {0x0000a104, 0x0205070a},
338 {0x0000a108, 0x0205070b},
339 {0x0000a10c, 0x0205070c},
340 {0x0000a110, 0x0205070d},
341 {0x0000a114, 0x02050710},
342 {0x0000a118, 0x02050711},
343 {0x0000a11c, 0x02050712},
344 {0x0000a120, 0x02050713},
345 {0x0000a124, 0x02050714},
346 {0x0000a128, 0x02050715},
347 {0x0000a12c, 0x02050730},
348 {0x0000a130, 0x02050731},
349 {0x0000a134, 0x02050732},
350 {0x0000a138, 0x02050733},
351 {0x0000a13c, 0x02050734},
352 {0x0000a140, 0x02050735},
353 {0x0000a144, 0x02050750},
354 {0x0000a148, 0x02050751},
355 {0x0000a14c, 0x02050752},
356 {0x0000a150, 0x02050753},
357 {0x0000a154, 0x02050754},
358 {0x0000a158, 0x02050755},
359 {0x0000a15c, 0x02050770},
360 {0x0000a160, 0x02050771},
361 {0x0000a164, 0x02050772},
362 {0x0000a168, 0x02050773},
363 {0x0000a16c, 0x02050774},
364 {0x0000a170, 0x02050775},
365 {0x0000a174, 0x00000776},
366 {0x0000a178, 0x00000776},
367 {0x0000a17c, 0x00000776},
368 {0x0000a180, 0x00000776},
369 {0x0000a184, 0x00000776},
370 {0x0000a188, 0x00000776},
371 {0x0000a18c, 0x00000776},
372 {0x0000a190, 0x00000776},
373 {0x0000a194, 0x00000776},
374 {0x0000a198, 0x00000776},
375 {0x0000a19c, 0x00000776},
376 {0x0000a1a0, 0x00000776},
377 {0x0000a1a4, 0x00000776},
378 {0x0000a1a8, 0x00000776},
379 {0x0000a1ac, 0x00000776},
380 {0x0000a1b0, 0x00000776},
381 {0x0000a1b4, 0x00000776},
382 {0x0000a1b8, 0x00000776},
383 {0x0000a1bc, 0x00000776},
384 {0x0000a1c0, 0x00000776},
385 {0x0000a1c4, 0x00000776},
386 {0x0000a1c8, 0x00000776},
387 {0x0000a1cc, 0x00000776},
388 {0x0000a1d0, 0x00000776},
389 {0x0000a1d4, 0x00000776},
390 {0x0000a1d8, 0x00000776},
391 {0x0000a1dc, 0x00000776},
392 {0x0000a1e0, 0x00000776},
393 {0x0000a1e4, 0x00000776},
394 {0x0000a1e8, 0x00000776},
395 {0x0000a1ec, 0x00000776},
396 {0x0000a1f0, 0x00000776},
397 {0x0000a1f4, 0x00000776},
398 {0x0000a1f8, 0x00000776},
399 {0x0000a1fc, 0x00000776},
400 {0x0000b000, 0x02000101},
401 {0x0000b004, 0x02000102},
402 {0x0000b008, 0x02000103},
403 {0x0000b00c, 0x02000104},
404 {0x0000b010, 0x02000200},
405 {0x0000b014, 0x02000201},
406 {0x0000b018, 0x02000202},
407 {0x0000b01c, 0x02000203},
408 {0x0000b020, 0x02000204},
409 {0x0000b024, 0x02000205},
410 {0x0000b028, 0x02000208},
411 {0x0000b02c, 0x02000302},
412 {0x0000b030, 0x02000303},
413 {0x0000b034, 0x02000304},
414 {0x0000b038, 0x02000400},
415 {0x0000b03c, 0x02010300},
416 {0x0000b040, 0x02010301},
417 {0x0000b044, 0x02010302},
418 {0x0000b048, 0x02000500},
419 {0x0000b04c, 0x02010400},
420 {0x0000b050, 0x02020300},
421 {0x0000b054, 0x02020301},
422 {0x0000b058, 0x02020302},
423 {0x0000b05c, 0x02020303},
424 {0x0000b060, 0x02020400},
425 {0x0000b064, 0x02030300},
426 {0x0000b068, 0x02030301},
427 {0x0000b06c, 0x02030302},
428 {0x0000b070, 0x02030303},
429 {0x0000b074, 0x02030400},
430 {0x0000b078, 0x02040300},
431 {0x0000b07c, 0x02040301},
432 {0x0000b080, 0x02040302},
433 {0x0000b084, 0x02040303},
434 {0x0000b088, 0x02030500},
435 {0x0000b08c, 0x02040400},
436 {0x0000b090, 0x02050203},
437 {0x0000b094, 0x02050204},
438 {0x0000b098, 0x02050205},
439 {0x0000b09c, 0x02040500},
440 {0x0000b0a0, 0x02050301},
441 {0x0000b0a4, 0x02050302},
442 {0x0000b0a8, 0x02050303},
443 {0x0000b0ac, 0x02050400},
444 {0x0000b0b0, 0x02050401},
445 {0x0000b0b4, 0x02050402},
446 {0x0000b0b8, 0x02050403},
447 {0x0000b0bc, 0x02050500},
448 {0x0000b0c0, 0x02050501},
449 {0x0000b0c4, 0x02050502},
450 {0x0000b0c8, 0x02050503},
451 {0x0000b0cc, 0x02050504},
452 {0x0000b0d0, 0x02050600},
453 {0x0000b0d4, 0x02050601},
454 {0x0000b0d8, 0x02050602},
455 {0x0000b0dc, 0x02050603},
456 {0x0000b0e0, 0x02050604},
457 {0x0000b0e4, 0x02050700},
458 {0x0000b0e8, 0x02050701},
459 {0x0000b0ec, 0x02050702},
460 {0x0000b0f0, 0x02050703},
461 {0x0000b0f4, 0x02050704},
462 {0x0000b0f8, 0x02050705},
463 {0x0000b0fc, 0x02050708},
464 {0x0000b100, 0x02050709},
465 {0x0000b104, 0x0205070a},
466 {0x0000b108, 0x0205070b},
467 {0x0000b10c, 0x0205070c},
468 {0x0000b110, 0x0205070d},
469 {0x0000b114, 0x02050710},
470 {0x0000b118, 0x02050711},
471 {0x0000b11c, 0x02050712},
472 {0x0000b120, 0x02050713},
473 {0x0000b124, 0x02050714},
474 {0x0000b128, 0x02050715},
475 {0x0000b12c, 0x02050730},
476 {0x0000b130, 0x02050731},
477 {0x0000b134, 0x02050732},
478 {0x0000b138, 0x02050733},
479 {0x0000b13c, 0x02050734},
480 {0x0000b140, 0x02050735},
481 {0x0000b144, 0x02050750},
482 {0x0000b148, 0x02050751},
483 {0x0000b14c, 0x02050752},
484 {0x0000b150, 0x02050753},
485 {0x0000b154, 0x02050754},
486 {0x0000b158, 0x02050755},
487 {0x0000b15c, 0x02050770},
488 {0x0000b160, 0x02050771},
489 {0x0000b164, 0x02050772},
490 {0x0000b168, 0x02050773},
491 {0x0000b16c, 0x02050774},
492 {0x0000b170, 0x02050775},
493 {0x0000b174, 0x00000776},
494 {0x0000b178, 0x00000776},
495 {0x0000b17c, 0x00000776},
496 {0x0000b180, 0x00000776},
497 {0x0000b184, 0x00000776},
498 {0x0000b188, 0x00000776},
499 {0x0000b18c, 0x00000776},
500 {0x0000b190, 0x00000776},
501 {0x0000b194, 0x00000776},
502 {0x0000b198, 0x00000776},
503 {0x0000b19c, 0x00000776},
504 {0x0000b1a0, 0x00000776},
505 {0x0000b1a4, 0x00000776},
506 {0x0000b1a8, 0x00000776},
507 {0x0000b1ac, 0x00000776},
508 {0x0000b1b0, 0x00000776},
509 {0x0000b1b4, 0x00000776},
510 {0x0000b1b8, 0x00000776},
511 {0x0000b1bc, 0x00000776},
512 {0x0000b1c0, 0x00000776},
513 {0x0000b1c4, 0x00000776},
514 {0x0000b1c8, 0x00000776},
515 {0x0000b1cc, 0x00000776},
516 {0x0000b1d0, 0x00000776},
517 {0x0000b1d4, 0x00000776},
518 {0x0000b1d8, 0x00000776},
519 {0x0000b1dc, 0x00000776},
520 {0x0000b1e0, 0x00000776},
521 {0x0000b1e4, 0x00000776},
522 {0x0000b1e8, 0x00000776},
523 {0x0000b1ec, 0x00000776},
524 {0x0000b1f0, 0x00000776},
525 {0x0000b1f4, 0x00000776},
526 {0x0000b1f8, 0x00000776},
527 {0x0000b1fc, 0x00000776},
528};
529
530static const u32 ar9300_2p0_mac_postamble[][5] = {
531 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
532 {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
533 {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
534 {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
535 {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
536 {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
537 {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
538 {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
539 {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
540};
541
542static const u32 ar9300_2p0_soc_postamble[][5] = {
543 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
544 {0x00007010, 0x00000023, 0x00000023, 0x00000022, 0x00000022},
545};
546
547static const u32 ar9200_merlin_2p0_radio_core[][2] = {
548 /* Addr allmodes */
549 {0x00007800, 0x00040000},
550 {0x00007804, 0xdb005012},
551 {0x00007808, 0x04924914},
552 {0x0000780c, 0x21084210},
553 {0x00007810, 0x6d801300},
554 {0x00007814, 0x0019beff},
555 {0x00007818, 0x07e41000},
556 {0x0000781c, 0x00392000},
557 {0x00007820, 0x92592480},
558 {0x00007824, 0x00040000},
559 {0x00007828, 0xdb005012},
560 {0x0000782c, 0x04924914},
561 {0x00007830, 0x21084210},
562 {0x00007834, 0x6d801300},
563 {0x00007838, 0x0019beff},
564 {0x0000783c, 0x07e40000},
565 {0x00007840, 0x00392000},
566 {0x00007844, 0x92592480},
567 {0x00007848, 0x00100000},
568 {0x0000784c, 0x773f0567},
569 {0x00007850, 0x54214514},
570 {0x00007854, 0x12035828},
571 {0x00007858, 0x92592692},
572 {0x0000785c, 0x00000000},
573 {0x00007860, 0x56400000},
574 {0x00007864, 0x0a8e370e},
575 {0x00007868, 0xc0102850},
576 {0x0000786c, 0x812d4000},
577 {0x00007870, 0x807ec400},
578 {0x00007874, 0x001b6db0},
579 {0x00007878, 0x00376b63},
580 {0x0000787c, 0x06db6db6},
581 {0x00007880, 0x006d8000},
582 {0x00007884, 0xffeffffe},
583 {0x00007888, 0xffeffffe},
584 {0x0000788c, 0x00010000},
585 {0x00007890, 0x02060aeb},
586 {0x00007894, 0x5a108000},
587};
588
589static const u32 ar9300_2p0_baseband_postamble[][5] = {
590 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
591 {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005},
592 {0x00009820, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e},
593 {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
594 {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
595 {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
596 {0x00009830, 0x0000059c, 0x0000059c, 0x0000059c, 0x0000059c},
597 {0x00009c00, 0x00000044, 0x000000c4, 0x000000c4, 0x00000044},
598 {0x00009e00, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0},
599 {0x00009e04, 0x00802020, 0x00802020, 0x00802020, 0x00802020},
600 {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
601 {0x00009e10, 0x7ec88d2e, 0x7ec88d2e, 0x7ec84d2e, 0x7ec84d2e},
602 {0x00009e14, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e},
603 {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
604 {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
605 {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
606 {0x00009e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021},
607 {0x00009e44, 0x02321e27, 0x02321e27, 0x02282324, 0x02282324},
608 {0x00009e48, 0x5030201a, 0x5030201a, 0x50302010, 0x50302010},
609 {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
610 {0x0000a204, 0x000037c0, 0x000037c4, 0x000037c4, 0x000037c0},
611 {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004},
612 {0x0000a230, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b},
613 {0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018},
614 {0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108},
615 {0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898},
616 {0x0000a258, 0x02020002, 0x02020002, 0x02020002, 0x02020002},
617 {0x0000a25c, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e},
618 {0x0000a260, 0x0a021501, 0x0a021501, 0x3a021501, 0x3a021501},
619 {0x0000a264, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e},
620 {0x0000a280, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b},
621 {0x0000a284, 0x00000000, 0x00000000, 0x00000150, 0x00000150},
622 {0x0000a288, 0x00000110, 0x00000110, 0x00000110, 0x00000110},
623 {0x0000a28c, 0x00022222, 0x00022222, 0x00022222, 0x00022222},
624 {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
625 {0x0000a2d0, 0x00071981, 0x00071981, 0x00071981, 0x00071982},
626 {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0xf999a83a, 0xf999a83a},
627 {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
628 {0x0000a830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
629 {0x0000ae04, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
630 {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
631 {0x0000ae1c, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
632 {0x0000ae20, 0x000001b5, 0x000001b5, 0x000001ce, 0x000001ce},
633 {0x0000b284, 0x00000000, 0x00000000, 0x00000150, 0x00000150},
634 {0x0000b830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
635 {0x0000be04, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
636 {0x0000be18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
637 {0x0000be1c, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
638 {0x0000be20, 0x000001b5, 0x000001b5, 0x000001ce, 0x000001ce},
639 {0x0000c284, 0x00000000, 0x00000000, 0x00000150, 0x00000150},
640};
641
642static const u32 ar9300_2p0_baseband_core[][2] = {
643 /* Addr allmodes */
644 {0x00009800, 0xafe68e30},
645 {0x00009804, 0xfd14e000},
646 {0x00009808, 0x9c0a9f6b},
647 {0x0000980c, 0x04900000},
648 {0x00009814, 0x9280c00a},
649 {0x00009818, 0x00000000},
650 {0x0000981c, 0x00020028},
651 {0x00009834, 0x5f3ca3de},
652 {0x00009838, 0x0108ecff},
653 {0x0000983c, 0x14750600},
654 {0x00009880, 0x201fff00},
655 {0x00009884, 0x00001042},
656 {0x000098a4, 0x00200400},
657 {0x000098b0, 0x52440bbe},
658 {0x000098d0, 0x004b6a8e},
659 {0x000098d4, 0x00000820},
660 {0x000098dc, 0x00000000},
661 {0x000098f0, 0x00000000},
662 {0x000098f4, 0x00000000},
663 {0x00009c04, 0xff55ff55},
664 {0x00009c08, 0x0320ff55},
665 {0x00009c0c, 0x00000000},
666 {0x00009c10, 0x00000000},
667 {0x00009c14, 0x00046384},
668 {0x00009c18, 0x05b6b440},
669 {0x00009c1c, 0x00b6b440},
670 {0x00009d00, 0xc080a333},
671 {0x00009d04, 0x40206c10},
672 {0x00009d08, 0x009c4060},
673 {0x00009d0c, 0x9883800a},
674 {0x00009d10, 0x01834061},
675 {0x00009d14, 0x00c0040b},
676 {0x00009d18, 0x00000000},
677 {0x00009e08, 0x0038233c},
678 {0x00009e24, 0x990bb515},
679 {0x00009e28, 0x0c6f0000},
680 {0x00009e30, 0x06336f77},
681 {0x00009e34, 0x6af6532f},
682 {0x00009e38, 0x0cc80c00},
683 {0x00009e3c, 0xcf946222},
684 {0x00009e40, 0x0d261820},
685 {0x00009e4c, 0x00001004},
686 {0x00009e50, 0x00ff03f1},
687 {0x00009e54, 0x00000000},
688 {0x00009fc0, 0x803e4788},
689 {0x00009fc4, 0x0001efb5},
690 {0x00009fcc, 0x40000014},
691 {0x00009fd0, 0x01193b93},
692 {0x0000a20c, 0x00000000},
693 {0x0000a220, 0x00000000},
694 {0x0000a224, 0x00000000},
695 {0x0000a228, 0x10002310},
696 {0x0000a22c, 0x01036a1e},
697 {0x0000a234, 0x10000fff},
698 {0x0000a23c, 0x00000000},
699 {0x0000a244, 0x0c000000},
700 {0x0000a2a0, 0x00000001},
701 {0x0000a2c0, 0x00000001},
702 {0x0000a2c8, 0x00000000},
703 {0x0000a2cc, 0x18c43433},
704 {0x0000a2d4, 0x00000000},
705 {0x0000a2dc, 0x00000000},
706 {0x0000a2e0, 0x00000000},
707 {0x0000a2e4, 0x00000000},
708 {0x0000a2e8, 0x00000000},
709 {0x0000a2ec, 0x00000000},
710 {0x0000a2f0, 0x00000000},
711 {0x0000a2f4, 0x00000000},
712 {0x0000a2f8, 0x00000000},
713 {0x0000a344, 0x00000000},
714 {0x0000a34c, 0x00000000},
715 {0x0000a350, 0x0000a000},
716 {0x0000a364, 0x00000000},
717 {0x0000a370, 0x00000000},
718 {0x0000a390, 0x00000001},
719 {0x0000a394, 0x00000444},
720 {0x0000a398, 0x001f0e0f},
721 {0x0000a39c, 0x0075393f},
722 {0x0000a3a0, 0xb79f6427},
723 {0x0000a3a4, 0x00000000},
724 {0x0000a3a8, 0xaaaaaaaa},
725 {0x0000a3ac, 0x3c466478},
726 {0x0000a3c0, 0x20202020},
727 {0x0000a3c4, 0x22222220},
728 {0x0000a3c8, 0x20200020},
729 {0x0000a3cc, 0x20202020},
730 {0x0000a3d0, 0x20202020},
731 {0x0000a3d4, 0x20202020},
732 {0x0000a3d8, 0x20202020},
733 {0x0000a3dc, 0x20202020},
734 {0x0000a3e0, 0x20202020},
735 {0x0000a3e4, 0x20202020},
736 {0x0000a3e8, 0x20202020},
737 {0x0000a3ec, 0x20202020},
738 {0x0000a3f0, 0x00000000},
739 {0x0000a3f4, 0x00000246},
740 {0x0000a3f8, 0x0cdbd380},
741 {0x0000a3fc, 0x000f0f01},
742 {0x0000a400, 0x8fa91f01},
743 {0x0000a404, 0x00000000},
744 {0x0000a408, 0x0e79e5c6},
745 {0x0000a40c, 0x00820820},
746 {0x0000a414, 0x1ce739ce},
747 {0x0000a418, 0x7d001dce},
748 {0x0000a41c, 0x1ce739ce},
749 {0x0000a420, 0x000001ce},
750 {0x0000a424, 0x1ce739ce},
751 {0x0000a428, 0x000001ce},
752 {0x0000a42c, 0x1ce739ce},
753 {0x0000a430, 0x1ce739ce},
754 {0x0000a434, 0x00000000},
755 {0x0000a438, 0x00001801},
756 {0x0000a43c, 0x00000000},
757 {0x0000a440, 0x00000000},
758 {0x0000a444, 0x00000000},
759 {0x0000a448, 0x07000080},
760 {0x0000a44c, 0x00000001},
761 {0x0000a450, 0x00010000},
762 {0x0000a458, 0x00000000},
763 {0x0000a600, 0x00000000},
764 {0x0000a604, 0x00000000},
765 {0x0000a608, 0x00000000},
766 {0x0000a60c, 0x00000000},
767 {0x0000a610, 0x00000000},
768 {0x0000a614, 0x00000000},
769 {0x0000a618, 0x00000000},
770 {0x0000a61c, 0x00000000},
771 {0x0000a620, 0x00000000},
772 {0x0000a624, 0x00000000},
773 {0x0000a628, 0x00000000},
774 {0x0000a62c, 0x00000000},
775 {0x0000a630, 0x00000000},
776 {0x0000a634, 0x00000000},
777 {0x0000a638, 0x00000000},
778 {0x0000a63c, 0x00000000},
779 {0x0000a640, 0x00000000},
780 {0x0000a644, 0x3ffd9d74},
781 {0x0000a648, 0x0048060a},
782 {0x0000a64c, 0x00000637},
783 {0x0000a670, 0x03020100},
784 {0x0000a674, 0x09080504},
785 {0x0000a678, 0x0d0c0b0a},
786 {0x0000a67c, 0x13121110},
787 {0x0000a680, 0x31301514},
788 {0x0000a684, 0x35343332},
789 {0x0000a688, 0x00000036},
790 {0x0000a690, 0x00000838},
791 {0x0000a7c0, 0x00000000},
792 {0x0000a7c4, 0xfffffffc},
793 {0x0000a7c8, 0x00000000},
794 {0x0000a7cc, 0x00000000},
795 {0x0000a7d0, 0x00000000},
796 {0x0000a7d4, 0x00000004},
797 {0x0000a7dc, 0x00000001},
798 {0x0000a8d0, 0x004b6a8e},
799 {0x0000a8d4, 0x00000820},
800 {0x0000a8dc, 0x00000000},
801 {0x0000a8f0, 0x00000000},
802 {0x0000a8f4, 0x00000000},
803 {0x0000b2d0, 0x00000080},
804 {0x0000b2d4, 0x00000000},
805 {0x0000b2dc, 0x00000000},
806 {0x0000b2e0, 0x00000000},
807 {0x0000b2e4, 0x00000000},
808 {0x0000b2e8, 0x00000000},
809 {0x0000b2ec, 0x00000000},
810 {0x0000b2f0, 0x00000000},
811 {0x0000b2f4, 0x00000000},
812 {0x0000b2f8, 0x00000000},
813 {0x0000b408, 0x0e79e5c0},
814 {0x0000b40c, 0x00820820},
815 {0x0000b420, 0x00000000},
816 {0x0000b8d0, 0x004b6a8e},
817 {0x0000b8d4, 0x00000820},
818 {0x0000b8dc, 0x00000000},
819 {0x0000b8f0, 0x00000000},
820 {0x0000b8f4, 0x00000000},
821 {0x0000c2d0, 0x00000080},
822 {0x0000c2d4, 0x00000000},
823 {0x0000c2dc, 0x00000000},
824 {0x0000c2e0, 0x00000000},
825 {0x0000c2e4, 0x00000000},
826 {0x0000c2e8, 0x00000000},
827 {0x0000c2ec, 0x00000000},
828 {0x0000c2f0, 0x00000000},
829 {0x0000c2f4, 0x00000000},
830 {0x0000c2f8, 0x00000000},
831 {0x0000c408, 0x0e79e5c0},
832 {0x0000c40c, 0x00820820},
833 {0x0000c420, 0x00000000},
834};
835
836static const u32 ar9300Modes_high_power_tx_gain_table_2p0[][5] = {
837 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
838 {0x0000a410, 0x000050db, 0x000050db, 0x000050d9, 0x000050d9},
839 {0x0000a500, 0x00020220, 0x00020220, 0x00000000, 0x00000000},
840 {0x0000a504, 0x06020223, 0x06020223, 0x04000002, 0x04000002},
841 {0x0000a508, 0x0a022220, 0x0a022220, 0x08000004, 0x08000004},
842 {0x0000a50c, 0x0f022223, 0x0f022223, 0x0b000200, 0x0b000200},
843 {0x0000a510, 0x14022620, 0x14022620, 0x0f000202, 0x0f000202},
844 {0x0000a514, 0x18022622, 0x18022622, 0x11000400, 0x11000400},
845 {0x0000a518, 0x1b022822, 0x1b022822, 0x15000402, 0x15000402},
846 {0x0000a51c, 0x20022842, 0x20022842, 0x19000404, 0x19000404},
847 {0x0000a520, 0x22022c41, 0x22022c41, 0x1b000603, 0x1b000603},
848 {0x0000a524, 0x28023042, 0x28023042, 0x1f000a02, 0x1f000a02},
849 {0x0000a528, 0x2c023044, 0x2c023044, 0x23000a04, 0x23000a04},
850 {0x0000a52c, 0x2f023644, 0x2f023644, 0x26000a20, 0x26000a20},
851 {0x0000a530, 0x34043643, 0x34043643, 0x2a000e20, 0x2a000e20},
852 {0x0000a534, 0x38043a44, 0x38043a44, 0x2e000e22, 0x2e000e22},
853 {0x0000a538, 0x3b043e45, 0x3b043e45, 0x31000e24, 0x31000e24},
854 {0x0000a53c, 0x40063e46, 0x40063e46, 0x34001640, 0x34001640},
855 {0x0000a540, 0x44083e46, 0x44083e46, 0x38001660, 0x38001660},
856 {0x0000a544, 0x46083e66, 0x46083e66, 0x3b001861, 0x3b001861},
857 {0x0000a548, 0x4b0a3e69, 0x4b0a3e69, 0x3e001a81, 0x3e001a81},
858 {0x0000a54c, 0x4f0a5e66, 0x4f0a5e66, 0x42001a83, 0x42001a83},
859 {0x0000a550, 0x540a7e66, 0x540a7e66, 0x44001c84, 0x44001c84},
860 {0x0000a554, 0x570a7e89, 0x570a7e89, 0x48001ce3, 0x48001ce3},
861 {0x0000a558, 0x5c0e7e8a, 0x5c0e7e8a, 0x4c001ce5, 0x4c001ce5},
862 {0x0000a55c, 0x60127e8b, 0x60127e8b, 0x50001ce9, 0x50001ce9},
863 {0x0000a560, 0x65127ecc, 0x65127ecc, 0x54001ceb, 0x54001ceb},
864 {0x0000a564, 0x6b169ecd, 0x6b169ecd, 0x56001eec, 0x56001eec},
865 {0x0000a568, 0x70169f0e, 0x70169f0e, 0x56001eec, 0x56001eec},
866 {0x0000a56c, 0x75169f4f, 0x75169f4f, 0x56001eec, 0x56001eec},
867 {0x0000a570, 0x75169f4f, 0x75169f4f, 0x56001eec, 0x56001eec},
868 {0x0000a574, 0x75169f4f, 0x75169f4f, 0x56001eec, 0x56001eec},
869 {0x0000a578, 0x75169f4f, 0x75169f4f, 0x56001eec, 0x56001eec},
870 {0x0000a57c, 0x75169f4f, 0x75169f4f, 0x56001eec, 0x56001eec},
871 {0x0000a580, 0x00820220, 0x00820220, 0x00800000, 0x00800000},
872 {0x0000a584, 0x06820223, 0x06820223, 0x04800002, 0x04800002},
873 {0x0000a588, 0x0a822220, 0x0a822220, 0x08800004, 0x08800004},
874 {0x0000a58c, 0x0f822223, 0x0f822223, 0x0b800200, 0x0b800200},
875 {0x0000a590, 0x14822620, 0x14822620, 0x0f800202, 0x0f800202},
876 {0x0000a594, 0x18822622, 0x18822622, 0x11800400, 0x11800400},
877 {0x0000a598, 0x1b822822, 0x1b822822, 0x15800402, 0x15800402},
878 {0x0000a59c, 0x20822842, 0x20822842, 0x19800404, 0x19800404},
879 {0x0000a5a0, 0x22822c41, 0x22822c41, 0x1b800603, 0x1b800603},
880 {0x0000a5a4, 0x28823042, 0x28823042, 0x1f800a02, 0x1f800a02},
881 {0x0000a5a8, 0x2c823044, 0x2c823044, 0x23800a04, 0x23800a04},
882 {0x0000a5ac, 0x2f823644, 0x2f823644, 0x26800a20, 0x26800a20},
883 {0x0000a5b0, 0x34843643, 0x34843643, 0x2a800e20, 0x2a800e20},
884 {0x0000a5b4, 0x38843a44, 0x38843a44, 0x2e800e22, 0x2e800e22},
885 {0x0000a5b8, 0x3b843e45, 0x3b843e45, 0x31800e24, 0x31800e24},
886 {0x0000a5bc, 0x40863e46, 0x40863e46, 0x34801640, 0x34801640},
887 {0x0000a5c0, 0x4c8a3065, 0x44883e46, 0x44883e46, 0x38801660},
888 {0x0000a5c4, 0x46883e66, 0x46883e66, 0x3b801861, 0x3b801861},
889 {0x0000a5c8, 0x4b8a3e69, 0x4b8a3e69, 0x3e801a81, 0x3e801a81},
890 {0x0000a5cc, 0x4f8a5e66, 0x4f8a5e66, 0x42801a83, 0x42801a83},
891 {0x0000a5d0, 0x548a7e66, 0x548a7e66, 0x44801c84, 0x44801c84},
892 {0x0000a5d4, 0x578a7e89, 0x578a7e89, 0x48801ce3, 0x48801ce3},
893 {0x0000a5d8, 0x5c8e7e8a, 0x5c8e7e8a, 0x4c801ce5, 0x4c801ce5},
894 {0x0000a5dc, 0x60927e8b, 0x60927e8b, 0x50801ce9, 0x50801ce9},
895 {0x0000a5e0, 0x65927ecc, 0x65927ecc, 0x54801ceb, 0x54801ceb},
896 {0x0000a5e4, 0x6b969ecd, 0x6b969ecd, 0x56801eec, 0x56801eec},
897 {0x0000a5e8, 0x70969f0e, 0x70969f0e, 0x56801eec, 0x56801eec},
898 {0x0000a5ec, 0x75969f4f, 0x75969f4f, 0x56801eec, 0x56801eec},
899 {0x0000a5f0, 0x75969f4f, 0x75969f4f, 0x56801eec, 0x56801eec},
900 {0x0000a5f4, 0x75969f4f, 0x75969f4f, 0x56801eec, 0x56801eec},
901 {0x0000a5f8, 0x75969f4f, 0x75969f4f, 0x56801eec, 0x56801eec},
902 {0x0000a5fc, 0x75969f4f, 0x75969f4f, 0x56801eec, 0x56801eec},
903 {0x00016044, 0x056db2e6, 0x056db2e6, 0x056db2e6, 0x056db2e6},
904 {0x00016048, 0xad241a61, 0xad241a61, 0xad241a61, 0xad241a61},
905 {0x00016068, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c},
906 {0x00016444, 0x056db2e6, 0x056db2e6, 0x056db2e6, 0x056db2e6},
907 {0x00016448, 0xad241a61, 0xad241a61, 0xad241a61, 0xad241a61},
908 {0x00016468, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c},
909 {0x00016844, 0x056db2e6, 0x056db2e6, 0x056db2e6, 0x056db2e6},
910 {0x00016848, 0xad241a61, 0xad241a61, 0xad241a61, 0xad241a61},
911 {0x00016868, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c},
912};
913
914static const u32 ar9300Modes_high_ob_db_tx_gain_table_2p0[][5] = {
915 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
916 {0x0000a410, 0x000050db, 0x000050db, 0x000050d9, 0x000050d9},
917 {0x0000a500, 0x00020220, 0x00020220, 0x00000000, 0x00000000},
918 {0x0000a504, 0x06020223, 0x06020223, 0x04000002, 0x04000002},
919 {0x0000a508, 0x0a022220, 0x0a022220, 0x08000004, 0x08000004},
920 {0x0000a50c, 0x0f022223, 0x0f022223, 0x0b000200, 0x0b000200},
921 {0x0000a510, 0x14022620, 0x14022620, 0x0f000202, 0x0f000202},
922 {0x0000a514, 0x18022622, 0x18022622, 0x11000400, 0x11000400},
923 {0x0000a518, 0x1b022822, 0x1b022822, 0x15000402, 0x15000402},
924 {0x0000a51c, 0x20022842, 0x20022842, 0x19000404, 0x19000404},
925 {0x0000a520, 0x22022c41, 0x22022c41, 0x1b000603, 0x1b000603},
926 {0x0000a524, 0x28023042, 0x28023042, 0x1f000a02, 0x1f000a02},
927 {0x0000a528, 0x2c023044, 0x2c023044, 0x23000a04, 0x23000a04},
928 {0x0000a52c, 0x2f023644, 0x2f023644, 0x26000a20, 0x26000a20},
929 {0x0000a530, 0x34043643, 0x34043643, 0x2a000e20, 0x2a000e20},
930 {0x0000a534, 0x38043a44, 0x38043a44, 0x2e000e22, 0x2e000e22},
931 {0x0000a538, 0x3b043e45, 0x3b043e45, 0x31000e24, 0x31000e24},
932 {0x0000a53c, 0x40063e46, 0x40063e46, 0x34001640, 0x34001640},
933 {0x0000a540, 0x44083e46, 0x44083e46, 0x38001660, 0x38001660},
934 {0x0000a544, 0x46083e66, 0x46083e66, 0x3b001861, 0x3b001861},
935 {0x0000a548, 0x4b0a3e69, 0x4b0a3e69, 0x3e001a81, 0x3e001a81},
936 {0x0000a54c, 0x4f0a5e66, 0x4f0a5e66, 0x42001a83, 0x42001a83},
937 {0x0000a550, 0x540a7e66, 0x540a7e66, 0x44001c84, 0x44001c84},
938 {0x0000a554, 0x570a7e89, 0x570a7e89, 0x48001ce3, 0x48001ce3},
939 {0x0000a558, 0x5c0e7e8a, 0x5c0e7e8a, 0x4c001ce5, 0x4c001ce5},
940 {0x0000a55c, 0x60127e8b, 0x60127e8b, 0x50001ce9, 0x50001ce9},
941 {0x0000a560, 0x65127ecc, 0x65127ecc, 0x54001ceb, 0x54001ceb},
942 {0x0000a564, 0x6b169ecd, 0x6b169ecd, 0x56001eec, 0x56001eec},
943 {0x0000a568, 0x70169f0e, 0x70169f0e, 0x56001eec, 0x56001eec},
944 {0x0000a56c, 0x75169f4f, 0x75169f4f, 0x56001eec, 0x56001eec},
945 {0x0000a570, 0x75169f4f, 0x75169f4f, 0x56001eec, 0x56001eec},
946 {0x0000a574, 0x75169f4f, 0x75169f4f, 0x56001eec, 0x56001eec},
947 {0x0000a578, 0x75169f4f, 0x75169f4f, 0x56001eec, 0x56001eec},
948 {0x0000a57c, 0x75169f4f, 0x75169f4f, 0x56001eec, 0x56001eec},
949 {0x0000a580, 0x00820220, 0x00820220, 0x00800000, 0x00800000},
950 {0x0000a584, 0x06820223, 0x06820223, 0x04800002, 0x04800002},
951 {0x0000a588, 0x0a822220, 0x0a822220, 0x08800004, 0x08800004},
952 {0x0000a58c, 0x0f822223, 0x0f822223, 0x0b800200, 0x0b800200},
953 {0x0000a590, 0x14822620, 0x14822620, 0x0f800202, 0x0f800202},
954 {0x0000a594, 0x18822622, 0x18822622, 0x11800400, 0x11800400},
955 {0x0000a598, 0x1b822822, 0x1b822822, 0x15800402, 0x15800402},
956 {0x0000a59c, 0x20822842, 0x20822842, 0x19800404, 0x19800404},
957 {0x0000a5a0, 0x22822c41, 0x22822c41, 0x1b800603, 0x1b800603},
958 {0x0000a5a4, 0x28823042, 0x28823042, 0x1f800a02, 0x1f800a02},
959 {0x0000a5a8, 0x2c823044, 0x2c823044, 0x23800a04, 0x23800a04},
960 {0x0000a5ac, 0x2f823644, 0x2f823644, 0x26800a20, 0x26800a20},
961 {0x0000a5b0, 0x34843643, 0x34843643, 0x2a800e20, 0x2a800e20},
962 {0x0000a5b4, 0x38843a44, 0x38843a44, 0x2e800e22, 0x2e800e22},
963 {0x0000a5b8, 0x3b843e45, 0x3b843e45, 0x31800e24, 0x31800e24},
964 {0x0000a5bc, 0x40863e46, 0x40863e46, 0x34801640, 0x34801640},
965 {0x0000a5c0, 0x44883e46, 0x44883e46, 0x38801660, 0x38801660},
966 {0x0000a5c4, 0x46883e66, 0x46883e66, 0x3b801861, 0x3b801861},
967 {0x0000a5c8, 0x4b8a3e69, 0x4b8a3e69, 0x3e801a81, 0x3e801a81},
968 {0x0000a5cc, 0x4f8a5e66, 0x4f8a5e66, 0x42801a83, 0x42801a83},
969 {0x0000a5d0, 0x548a7e66, 0x548a7e66, 0x44801c84, 0x44801c84},
970 {0x0000a5d4, 0x578a7e89, 0x578a7e89, 0x48801ce3, 0x48801ce3},
971 {0x0000a5d8, 0x5c8e7e8a, 0x5c8e7e8a, 0x4c801ce5, 0x4c801ce5},
972 {0x0000a5dc, 0x60927e8b, 0x60927e8b, 0x50801ce9, 0x50801ce9},
973 {0x0000a5e0, 0x65927ecc, 0x65927ecc, 0x54801ceb, 0x54801ceb},
974 {0x0000a5e4, 0x6b969ecd, 0x6b969ecd, 0x56801eec, 0x56801eec},
975 {0x0000a5e8, 0x70969f0e, 0x70969f0e, 0x56801eec, 0x56801eec},
976 {0x0000a5ec, 0x75969f4f, 0x75969f4f, 0x56801eec, 0x56801eec},
977 {0x0000a5f0, 0x75969f4f, 0x75969f4f, 0x56801eec, 0x56801eec},
978 {0x0000a5f4, 0x75969f4f, 0x75969f4f, 0x56801eec, 0x56801eec},
979 {0x0000a5f8, 0x75969f4f, 0x75969f4f, 0x56801eec, 0x56801eec},
980 {0x0000a5fc, 0x75969f4f, 0x75969f4f, 0x56801eec, 0x56801eec},
981 {0x00016044, 0x056db2e4, 0x056db2e4, 0x056db2e4, 0x056db2e4},
982 {0x00016048, 0x8c001a61, 0x8c001a61, 0x8c001a61, 0x8c001a61},
983 {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
984 {0x00016444, 0x056db2e4, 0x056db2e4, 0x056db2e4, 0x056db2e4},
985 {0x00016448, 0x8c001a61, 0x8c001a61, 0x8c001a61, 0x8c001a61},
986 {0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
987 {0x00016844, 0x056db2e4, 0x056db2e4, 0x056db2e4, 0x056db2e4},
988 {0x00016848, 0x8c001a61, 0x8c001a61, 0x8c001a61, 0x8c001a61},
989 {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
990};
991
992static const u32 ar9300Common_rx_gain_table_2p0[][2] = {
993 /* Addr allmodes */
994 {0x0000a000, 0x00010000},
995 {0x0000a004, 0x00030002},
996 {0x0000a008, 0x00050004},
997 {0x0000a00c, 0x00810080},
998 {0x0000a010, 0x01800082},
999 {0x0000a014, 0x01820181},
1000 {0x0000a018, 0x01840183},
1001 {0x0000a01c, 0x01880185},
1002 {0x0000a020, 0x018a0189},
1003 {0x0000a024, 0x02850284},
1004 {0x0000a028, 0x02890288},
1005 {0x0000a02c, 0x028b028a},
1006 {0x0000a030, 0x028d028c},
1007 {0x0000a034, 0x02910290},
1008 {0x0000a038, 0x02930292},
1009 {0x0000a03c, 0x03910390},
1010 {0x0000a040, 0x03930392},
1011 {0x0000a044, 0x03950394},
1012 {0x0000a048, 0x00000396},
1013 {0x0000a04c, 0x00000000},
1014 {0x0000a050, 0x00000000},
1015 {0x0000a054, 0x00000000},
1016 {0x0000a058, 0x00000000},
1017 {0x0000a05c, 0x00000000},
1018 {0x0000a060, 0x00000000},
1019 {0x0000a064, 0x00000000},
1020 {0x0000a068, 0x00000000},
1021 {0x0000a06c, 0x00000000},
1022 {0x0000a070, 0x00000000},
1023 {0x0000a074, 0x00000000},
1024 {0x0000a078, 0x00000000},
1025 {0x0000a07c, 0x00000000},
1026 {0x0000a080, 0x28282828},
1027 {0x0000a084, 0x21212128},
1028 {0x0000a088, 0x21212121},
1029 {0x0000a08c, 0x1c1c1c21},
1030 {0x0000a090, 0x1c1c1c1c},
1031 {0x0000a094, 0x17171c1c},
1032 {0x0000a098, 0x02020212},
1033 {0x0000a09c, 0x02020202},
1034 {0x0000a0a0, 0x00000000},
1035 {0x0000a0a4, 0x00000000},
1036 {0x0000a0a8, 0x00000000},
1037 {0x0000a0ac, 0x00000000},
1038 {0x0000a0b0, 0x00000000},
1039 {0x0000a0b4, 0x00000000},
1040 {0x0000a0b8, 0x00000000},
1041 {0x0000a0bc, 0x00000000},
1042 {0x0000a0c0, 0x001f0000},
1043 {0x0000a0c4, 0x011f0100},
1044 {0x0000a0c8, 0x011d011e},
1045 {0x0000a0cc, 0x011b011c},
1046 {0x0000a0d0, 0x02030204},
1047 {0x0000a0d4, 0x02010202},
1048 {0x0000a0d8, 0x021f0200},
1049 {0x0000a0dc, 0x021d021e},
1050 {0x0000a0e0, 0x03010302},
1051 {0x0000a0e4, 0x031f0300},
1052 {0x0000a0e8, 0x0402031e},
1053 {0x0000a0ec, 0x04000401},
1054 {0x0000a0f0, 0x041e041f},
1055 {0x0000a0f4, 0x05010502},
1056 {0x0000a0f8, 0x051f0500},
1057 {0x0000a0fc, 0x0602051e},
1058 {0x0000a100, 0x06000601},
1059 {0x0000a104, 0x061e061f},
1060 {0x0000a108, 0x0703061d},
1061 {0x0000a10c, 0x07010702},
1062 {0x0000a110, 0x00000700},
1063 {0x0000a114, 0x00000000},
1064 {0x0000a118, 0x00000000},
1065 {0x0000a11c, 0x00000000},
1066 {0x0000a120, 0x00000000},
1067 {0x0000a124, 0x00000000},
1068 {0x0000a128, 0x00000000},
1069 {0x0000a12c, 0x00000000},
1070 {0x0000a130, 0x00000000},
1071 {0x0000a134, 0x00000000},
1072 {0x0000a138, 0x00000000},
1073 {0x0000a13c, 0x00000000},
1074 {0x0000a140, 0x001f0000},
1075 {0x0000a144, 0x011f0100},
1076 {0x0000a148, 0x011d011e},
1077 {0x0000a14c, 0x011b011c},
1078 {0x0000a150, 0x02030204},
1079 {0x0000a154, 0x02010202},
1080 {0x0000a158, 0x021f0200},
1081 {0x0000a15c, 0x021d021e},
1082 {0x0000a160, 0x03010302},
1083 {0x0000a164, 0x031f0300},
1084 {0x0000a168, 0x0402031e},
1085 {0x0000a16c, 0x04000401},
1086 {0x0000a170, 0x041e041f},
1087 {0x0000a174, 0x05010502},
1088 {0x0000a178, 0x051f0500},
1089 {0x0000a17c, 0x0602051e},
1090 {0x0000a180, 0x06000601},
1091 {0x0000a184, 0x061e061f},
1092 {0x0000a188, 0x0703061d},
1093 {0x0000a18c, 0x07010702},
1094 {0x0000a190, 0x00000700},
1095 {0x0000a194, 0x00000000},
1096 {0x0000a198, 0x00000000},
1097 {0x0000a19c, 0x00000000},
1098 {0x0000a1a0, 0x00000000},
1099 {0x0000a1a4, 0x00000000},
1100 {0x0000a1a8, 0x00000000},
1101 {0x0000a1ac, 0x00000000},
1102 {0x0000a1b0, 0x00000000},
1103 {0x0000a1b4, 0x00000000},
1104 {0x0000a1b8, 0x00000000},
1105 {0x0000a1bc, 0x00000000},
1106 {0x0000a1c0, 0x00000000},
1107 {0x0000a1c4, 0x00000000},
1108 {0x0000a1c8, 0x00000000},
1109 {0x0000a1cc, 0x00000000},
1110 {0x0000a1d0, 0x00000000},
1111 {0x0000a1d4, 0x00000000},
1112 {0x0000a1d8, 0x00000000},
1113 {0x0000a1dc, 0x00000000},
1114 {0x0000a1e0, 0x00000000},
1115 {0x0000a1e4, 0x00000000},
1116 {0x0000a1e8, 0x00000000},
1117 {0x0000a1ec, 0x00000000},
1118 {0x0000a1f0, 0x00000396},
1119 {0x0000a1f4, 0x00000396},
1120 {0x0000a1f8, 0x00000396},
1121 {0x0000a1fc, 0x00000196},
1122 {0x0000b000, 0x00010000},
1123 {0x0000b004, 0x00030002},
1124 {0x0000b008, 0x00050004},
1125 {0x0000b00c, 0x00810080},
1126 {0x0000b010, 0x00830082},
1127 {0x0000b014, 0x01810180},
1128 {0x0000b018, 0x01830182},
1129 {0x0000b01c, 0x01850184},
1130 {0x0000b020, 0x02810280},
1131 {0x0000b024, 0x02830282},
1132 {0x0000b028, 0x02850284},
1133 {0x0000b02c, 0x02890288},
1134 {0x0000b030, 0x028b028a},
1135 {0x0000b034, 0x0388028c},
1136 {0x0000b038, 0x038a0389},
1137 {0x0000b03c, 0x038c038b},
1138 {0x0000b040, 0x0390038d},
1139 {0x0000b044, 0x03920391},
1140 {0x0000b048, 0x03940393},
1141 {0x0000b04c, 0x03960395},
1142 {0x0000b050, 0x00000000},
1143 {0x0000b054, 0x00000000},
1144 {0x0000b058, 0x00000000},
1145 {0x0000b05c, 0x00000000},
1146 {0x0000b060, 0x00000000},
1147 {0x0000b064, 0x00000000},
1148 {0x0000b068, 0x00000000},
1149 {0x0000b06c, 0x00000000},
1150 {0x0000b070, 0x00000000},
1151 {0x0000b074, 0x00000000},
1152 {0x0000b078, 0x00000000},
1153 {0x0000b07c, 0x00000000},
1154 {0x0000b080, 0x32323232},
1155 {0x0000b084, 0x2f2f3232},
1156 {0x0000b088, 0x23282a2d},
1157 {0x0000b08c, 0x1c1e2123},
1158 {0x0000b090, 0x14171919},
1159 {0x0000b094, 0x0e0e1214},
1160 {0x0000b098, 0x03050707},
1161 {0x0000b09c, 0x00030303},
1162 {0x0000b0a0, 0x00000000},
1163 {0x0000b0a4, 0x00000000},
1164 {0x0000b0a8, 0x00000000},
1165 {0x0000b0ac, 0x00000000},
1166 {0x0000b0b0, 0x00000000},
1167 {0x0000b0b4, 0x00000000},
1168 {0x0000b0b8, 0x00000000},
1169 {0x0000b0bc, 0x00000000},
1170 {0x0000b0c0, 0x003f0020},
1171 {0x0000b0c4, 0x00400041},
1172 {0x0000b0c8, 0x0140005f},
1173 {0x0000b0cc, 0x0160015f},
1174 {0x0000b0d0, 0x017e017f},
1175 {0x0000b0d4, 0x02410242},
1176 {0x0000b0d8, 0x025f0240},
1177 {0x0000b0dc, 0x027f0260},
1178 {0x0000b0e0, 0x0341027e},
1179 {0x0000b0e4, 0x035f0340},
1180 {0x0000b0e8, 0x037f0360},
1181 {0x0000b0ec, 0x04400441},
1182 {0x0000b0f0, 0x0460045f},
1183 {0x0000b0f4, 0x0541047f},
1184 {0x0000b0f8, 0x055f0540},
1185 {0x0000b0fc, 0x057f0560},
1186 {0x0000b100, 0x06400641},
1187 {0x0000b104, 0x0660065f},
1188 {0x0000b108, 0x067e067f},
1189 {0x0000b10c, 0x07410742},
1190 {0x0000b110, 0x075f0740},
1191 {0x0000b114, 0x077f0760},
1192 {0x0000b118, 0x07800781},
1193 {0x0000b11c, 0x07a0079f},
1194 {0x0000b120, 0x07c107bf},
1195 {0x0000b124, 0x000007c0},
1196 {0x0000b128, 0x00000000},
1197 {0x0000b12c, 0x00000000},
1198 {0x0000b130, 0x00000000},
1199 {0x0000b134, 0x00000000},
1200 {0x0000b138, 0x00000000},
1201 {0x0000b13c, 0x00000000},
1202 {0x0000b140, 0x003f0020},
1203 {0x0000b144, 0x00400041},
1204 {0x0000b148, 0x0140005f},
1205 {0x0000b14c, 0x0160015f},
1206 {0x0000b150, 0x017e017f},
1207 {0x0000b154, 0x02410242},
1208 {0x0000b158, 0x025f0240},
1209 {0x0000b15c, 0x027f0260},
1210 {0x0000b160, 0x0341027e},
1211 {0x0000b164, 0x035f0340},
1212 {0x0000b168, 0x037f0360},
1213 {0x0000b16c, 0x04400441},
1214 {0x0000b170, 0x0460045f},
1215 {0x0000b174, 0x0541047f},
1216 {0x0000b178, 0x055f0540},
1217 {0x0000b17c, 0x057f0560},
1218 {0x0000b180, 0x06400641},
1219 {0x0000b184, 0x0660065f},
1220 {0x0000b188, 0x067e067f},
1221 {0x0000b18c, 0x07410742},
1222 {0x0000b190, 0x075f0740},
1223 {0x0000b194, 0x077f0760},
1224 {0x0000b198, 0x07800781},
1225 {0x0000b19c, 0x07a0079f},
1226 {0x0000b1a0, 0x07c107bf},
1227 {0x0000b1a4, 0x000007c0},
1228 {0x0000b1a8, 0x00000000},
1229 {0x0000b1ac, 0x00000000},
1230 {0x0000b1b0, 0x00000000},
1231 {0x0000b1b4, 0x00000000},
1232 {0x0000b1b8, 0x00000000},
1233 {0x0000b1bc, 0x00000000},
1234 {0x0000b1c0, 0x00000000},
1235 {0x0000b1c4, 0x00000000},
1236 {0x0000b1c8, 0x00000000},
1237 {0x0000b1cc, 0x00000000},
1238 {0x0000b1d0, 0x00000000},
1239 {0x0000b1d4, 0x00000000},
1240 {0x0000b1d8, 0x00000000},
1241 {0x0000b1dc, 0x00000000},
1242 {0x0000b1e0, 0x00000000},
1243 {0x0000b1e4, 0x00000000},
1244 {0x0000b1e8, 0x00000000},
1245 {0x0000b1ec, 0x00000000},
1246 {0x0000b1f0, 0x00000396},
1247 {0x0000b1f4, 0x00000396},
1248 {0x0000b1f8, 0x00000396},
1249 {0x0000b1fc, 0x00000196},
1250};
1251
1252static const u32 ar9300Modes_low_ob_db_tx_gain_table_2p0[][5] = {
1253 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
1254 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
1255 {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1256 {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
1257 {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
1258 {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
1259 {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
1260 {0x0000a514, 0x1c000223, 0x1c000223, 0x12000400, 0x12000400},
1261 {0x0000a518, 0x21020220, 0x21020220, 0x16000402, 0x16000402},
1262 {0x0000a51c, 0x27020223, 0x27020223, 0x19000404, 0x19000404},
1263 {0x0000a520, 0x2b022220, 0x2b022220, 0x1c000603, 0x1c000603},
1264 {0x0000a524, 0x2f022222, 0x2f022222, 0x21000a02, 0x21000a02},
1265 {0x0000a528, 0x34022225, 0x34022225, 0x25000a04, 0x25000a04},
1266 {0x0000a52c, 0x3a02222a, 0x3a02222a, 0x28000a20, 0x28000a20},
1267 {0x0000a530, 0x3e02222c, 0x3e02222c, 0x2c000e20, 0x2c000e20},
1268 {0x0000a534, 0x4202242a, 0x4202242a, 0x30000e22, 0x30000e22},
1269 {0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24},
1270 {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640},
1271 {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660},
1272 {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861},
1273 {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81},
1274 {0x0000a54c, 0x5c04286b, 0x5c04286b, 0x47001a83, 0x47001a83},
1275 {0x0000a550, 0x61042a6c, 0x61042a6c, 0x4a001c84, 0x4a001c84},
1276 {0x0000a554, 0x66062a6c, 0x66062a6c, 0x4e001ce3, 0x4e001ce3},
1277 {0x0000a558, 0x6b062e6c, 0x6b062e6c, 0x52001ce5, 0x52001ce5},
1278 {0x0000a55c, 0x7006308c, 0x7006308c, 0x56001ce9, 0x56001ce9},
1279 {0x0000a560, 0x730a308a, 0x730a308a, 0x5a001ceb, 0x5a001ceb},
1280 {0x0000a564, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
1281 {0x0000a568, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
1282 {0x0000a56c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
1283 {0x0000a570, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
1284 {0x0000a574, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
1285 {0x0000a578, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
1286 {0x0000a57c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
1287 {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
1288 {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002},
1289 {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004},
1290 {0x0000a58c, 0x10800023, 0x10800023, 0x0b800200, 0x0b800200},
1291 {0x0000a590, 0x16800220, 0x16800220, 0x0f800202, 0x0f800202},
1292 {0x0000a594, 0x1c800223, 0x1c800223, 0x12800400, 0x12800400},
1293 {0x0000a598, 0x21820220, 0x21820220, 0x16800402, 0x16800402},
1294 {0x0000a59c, 0x27820223, 0x27820223, 0x19800404, 0x19800404},
1295 {0x0000a5a0, 0x2b822220, 0x2b822220, 0x1c800603, 0x1c800603},
1296 {0x0000a5a4, 0x2f822222, 0x2f822222, 0x21800a02, 0x21800a02},
1297 {0x0000a5a8, 0x34822225, 0x34822225, 0x25800a04, 0x25800a04},
1298 {0x0000a5ac, 0x3a82222a, 0x3a82222a, 0x28800a20, 0x28800a20},
1299 {0x0000a5b0, 0x3e82222c, 0x3e82222c, 0x2c800e20, 0x2c800e20},
1300 {0x0000a5b4, 0x4282242a, 0x4282242a, 0x30800e22, 0x30800e22},
1301 {0x0000a5b8, 0x4782244a, 0x4782244a, 0x34800e24, 0x34800e24},
1302 {0x0000a5bc, 0x4b82244c, 0x4b82244c, 0x38801640, 0x38801640},
1303 {0x0000a5c0, 0x4e82246c, 0x4e82246c, 0x3c801660, 0x3c801660},
1304 {0x0000a5c4, 0x5382266c, 0x5382266c, 0x3f801861, 0x3f801861},
1305 {0x0000a5c8, 0x5782286c, 0x5782286c, 0x43801a81, 0x43801a81},
1306 {0x0000a5cc, 0x5c84286b, 0x5c84286b, 0x47801a83, 0x47801a83},
1307 {0x0000a5d0, 0x61842a6c, 0x61842a6c, 0x4a801c84, 0x4a801c84},
1308 {0x0000a5d4, 0x66862a6c, 0x66862a6c, 0x4e801ce3, 0x4e801ce3},
1309 {0x0000a5d8, 0x6b862e6c, 0x6b862e6c, 0x52801ce5, 0x52801ce5},
1310 {0x0000a5dc, 0x7086308c, 0x7086308c, 0x56801ce9, 0x56801ce9},
1311 {0x0000a5e0, 0x738a308a, 0x738a308a, 0x5a801ceb, 0x5a801ceb},
1312 {0x0000a5e4, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
1313 {0x0000a5e8, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
1314 {0x0000a5ec, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
1315 {0x0000a5f0, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
1316 {0x0000a5f4, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
1317 {0x0000a5f8, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
1318 {0x0000a5fc, 0x778a308c, 0x778a308c, 0x5d801eec, 0x5d801eec},
1319 {0x00016044, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
1320 {0x00016048, 0x64001a61, 0x64001a61, 0x64001a61, 0x64001a61},
1321 {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
1322 {0x00016444, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
1323 {0x00016448, 0x64001a61, 0x64001a61, 0x64001a61, 0x64001a61},
1324 {0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
1325 {0x00016844, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
1326 {0x00016848, 0x64001a61, 0x64001a61, 0x64001a61, 0x64001a61},
1327 {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
1328};
1329
1330static const u32 ar9300_2p0_mac_core[][2] = {
1331 /* Addr allmodes */
1332 {0x00000008, 0x00000000},
1333 {0x00000030, 0x00020085},
1334 {0x00000034, 0x00000005},
1335 {0x00000040, 0x00000000},
1336 {0x00000044, 0x00000000},
1337 {0x00000048, 0x00000008},
1338 {0x0000004c, 0x00000010},
1339 {0x00000050, 0x00000000},
1340 {0x00001040, 0x002ffc0f},
1341 {0x00001044, 0x002ffc0f},
1342 {0x00001048, 0x002ffc0f},
1343 {0x0000104c, 0x002ffc0f},
1344 {0x00001050, 0x002ffc0f},
1345 {0x00001054, 0x002ffc0f},
1346 {0x00001058, 0x002ffc0f},
1347 {0x0000105c, 0x002ffc0f},
1348 {0x00001060, 0x002ffc0f},
1349 {0x00001064, 0x002ffc0f},
1350 {0x000010f0, 0x00000100},
1351 {0x00001270, 0x00000000},
1352 {0x000012b0, 0x00000000},
1353 {0x000012f0, 0x00000000},
1354 {0x0000143c, 0x00000000},
1355 {0x0000147c, 0x00000000},
1356 {0x00008000, 0x00000000},
1357 {0x00008004, 0x00000000},
1358 {0x00008008, 0x00000000},
1359 {0x0000800c, 0x00000000},
1360 {0x00008018, 0x00000000},
1361 {0x00008020, 0x00000000},
1362 {0x00008038, 0x00000000},
1363 {0x0000803c, 0x00000000},
1364 {0x00008040, 0x00000000},
1365 {0x00008044, 0x00000000},
1366 {0x00008048, 0x00000000},
1367 {0x0000804c, 0xffffffff},
1368 {0x00008054, 0x00000000},
1369 {0x00008058, 0x00000000},
1370 {0x0000805c, 0x000fc78f},
1371 {0x00008060, 0x0000000f},
1372 {0x00008064, 0x00000000},
1373 {0x00008070, 0x00000310},
1374 {0x00008074, 0x00000020},
1375 {0x00008078, 0x00000000},
1376 {0x0000809c, 0x0000000f},
1377 {0x000080a0, 0x00000000},
1378 {0x000080a4, 0x02ff0000},
1379 {0x000080a8, 0x0e070605},
1380 {0x000080ac, 0x0000000d},
1381 {0x000080b0, 0x00000000},
1382 {0x000080b4, 0x00000000},
1383 {0x000080b8, 0x00000000},
1384 {0x000080bc, 0x00000000},
1385 {0x000080c0, 0x2a800000},
1386 {0x000080c4, 0x06900168},
1387 {0x000080c8, 0x13881c20},
1388 {0x000080cc, 0x01f40000},
1389 {0x000080d0, 0x00252500},
1390 {0x000080d4, 0x00a00000},
1391 {0x000080d8, 0x00400000},
1392 {0x000080dc, 0x00000000},
1393 {0x000080e0, 0xffffffff},
1394 {0x000080e4, 0x0000ffff},
1395 {0x000080e8, 0x3f3f3f3f},
1396 {0x000080ec, 0x00000000},
1397 {0x000080f0, 0x00000000},
1398 {0x000080f4, 0x00000000},
1399 {0x000080fc, 0x00020000},
1400 {0x00008100, 0x00000000},
1401 {0x00008108, 0x00000052},
1402 {0x0000810c, 0x00000000},
1403 {0x00008110, 0x00000000},
1404 {0x00008114, 0x000007ff},
1405 {0x00008118, 0x000000aa},
1406 {0x0000811c, 0x00003210},
1407 {0x00008124, 0x00000000},
1408 {0x00008128, 0x00000000},
1409 {0x0000812c, 0x00000000},
1410 {0x00008130, 0x00000000},
1411 {0x00008134, 0x00000000},
1412 {0x00008138, 0x00000000},
1413 {0x0000813c, 0x0000ffff},
1414 {0x00008144, 0xffffffff},
1415 {0x00008168, 0x00000000},
1416 {0x0000816c, 0x00000000},
1417 {0x00008170, 0x18486200},
1418 {0x00008174, 0x33332210},
1419 {0x00008178, 0x00000000},
1420 {0x0000817c, 0x00020000},
1421 {0x000081c0, 0x00000000},
1422 {0x000081c4, 0x33332210},
1423 {0x000081c8, 0x00000000},
1424 {0x000081cc, 0x00000000},
1425 {0x000081d4, 0x00000000},
1426 {0x000081ec, 0x00000000},
1427 {0x000081f0, 0x00000000},
1428 {0x000081f4, 0x00000000},
1429 {0x000081f8, 0x00000000},
1430 {0x000081fc, 0x00000000},
1431 {0x00008240, 0x00100000},
1432 {0x00008244, 0x0010f424},
1433 {0x00008248, 0x00000800},
1434 {0x0000824c, 0x0001e848},
1435 {0x00008250, 0x00000000},
1436 {0x00008254, 0x00000000},
1437 {0x00008258, 0x00000000},
1438 {0x0000825c, 0x40000000},
1439 {0x00008260, 0x00080922},
1440 {0x00008264, 0x98a00010},
1441 {0x00008268, 0xffffffff},
1442 {0x0000826c, 0x0000ffff},
1443 {0x00008270, 0x00000000},
1444 {0x00008274, 0x40000000},
1445 {0x00008278, 0x003e4180},
1446 {0x0000827c, 0x00000004},
1447 {0x00008284, 0x0000002c},
1448 {0x00008288, 0x0000002c},
1449 {0x0000828c, 0x000000ff},
1450 {0x00008294, 0x00000000},
1451 {0x00008298, 0x00000000},
1452 {0x0000829c, 0x00000000},
1453 {0x00008300, 0x00000140},
1454 {0x00008314, 0x00000000},
1455 {0x0000831c, 0x0000010d},
1456 {0x00008328, 0x00000000},
1457 {0x0000832c, 0x00000007},
1458 {0x00008330, 0x00000302},
1459 {0x00008334, 0x00000700},
1460 {0x00008338, 0x00ff0000},
1461 {0x0000833c, 0x02400000},
1462 {0x00008340, 0x000107ff},
1463 {0x00008344, 0xaa48105b},
1464 {0x00008348, 0x008f0000},
1465 {0x0000835c, 0x00000000},
1466 {0x00008360, 0xffffffff},
1467 {0x00008364, 0xffffffff},
1468 {0x00008368, 0x00000000},
1469 {0x00008370, 0x00000000},
1470 {0x00008374, 0x000000ff},
1471 {0x00008378, 0x00000000},
1472 {0x0000837c, 0x00000000},
1473 {0x00008380, 0xffffffff},
1474 {0x00008384, 0xffffffff},
1475 {0x00008390, 0xffffffff},
1476 {0x00008394, 0xffffffff},
1477 {0x00008398, 0x00000000},
1478 {0x0000839c, 0x00000000},
1479 {0x000083a0, 0x00000000},
1480 {0x000083a4, 0x0000fa14},
1481 {0x000083a8, 0x000f0c00},
1482 {0x000083ac, 0x33332210},
1483 {0x000083b0, 0x33332210},
1484 {0x000083b4, 0x33332210},
1485 {0x000083b8, 0x33332210},
1486 {0x000083bc, 0x00000000},
1487 {0x000083c0, 0x00000000},
1488 {0x000083c4, 0x00000000},
1489 {0x000083c8, 0x00000000},
1490 {0x000083cc, 0x00000200},
1491 {0x000083d0, 0x000301ff},
1492};
1493
1494static const u32 ar9300Common_wo_xlna_rx_gain_table_2p0[][2] = {
1495 /* Addr allmodes */
1496 {0x0000a000, 0x00010000},
1497 {0x0000a004, 0x00030002},
1498 {0x0000a008, 0x00050004},
1499 {0x0000a00c, 0x00810080},
1500 {0x0000a010, 0x01800082},
1501 {0x0000a014, 0x01820181},
1502 {0x0000a018, 0x01840183},
1503 {0x0000a01c, 0x01880185},
1504 {0x0000a020, 0x018a0189},
1505 {0x0000a024, 0x02850284},
1506 {0x0000a028, 0x02890288},
1507 {0x0000a02c, 0x03850384},
1508 {0x0000a030, 0x03890388},
1509 {0x0000a034, 0x038b038a},
1510 {0x0000a038, 0x038d038c},
1511 {0x0000a03c, 0x03910390},
1512 {0x0000a040, 0x03930392},
1513 {0x0000a044, 0x03950394},
1514 {0x0000a048, 0x00000396},
1515 {0x0000a04c, 0x00000000},
1516 {0x0000a050, 0x00000000},
1517 {0x0000a054, 0x00000000},
1518 {0x0000a058, 0x00000000},
1519 {0x0000a05c, 0x00000000},
1520 {0x0000a060, 0x00000000},
1521 {0x0000a064, 0x00000000},
1522 {0x0000a068, 0x00000000},
1523 {0x0000a06c, 0x00000000},
1524 {0x0000a070, 0x00000000},
1525 {0x0000a074, 0x00000000},
1526 {0x0000a078, 0x00000000},
1527 {0x0000a07c, 0x00000000},
1528 {0x0000a080, 0x28282828},
1529 {0x0000a084, 0x28282828},
1530 {0x0000a088, 0x28282828},
1531 {0x0000a08c, 0x28282828},
1532 {0x0000a090, 0x28282828},
1533 {0x0000a094, 0x21212128},
1534 {0x0000a098, 0x171c1c1c},
1535 {0x0000a09c, 0x02020212},
1536 {0x0000a0a0, 0x00000202},
1537 {0x0000a0a4, 0x00000000},
1538 {0x0000a0a8, 0x00000000},
1539 {0x0000a0ac, 0x00000000},
1540 {0x0000a0b0, 0x00000000},
1541 {0x0000a0b4, 0x00000000},
1542 {0x0000a0b8, 0x00000000},
1543 {0x0000a0bc, 0x00000000},
1544 {0x0000a0c0, 0x001f0000},
1545 {0x0000a0c4, 0x011f0100},
1546 {0x0000a0c8, 0x011d011e},
1547 {0x0000a0cc, 0x011b011c},
1548 {0x0000a0d0, 0x02030204},
1549 {0x0000a0d4, 0x02010202},
1550 {0x0000a0d8, 0x021f0200},
1551 {0x0000a0dc, 0x021d021e},
1552 {0x0000a0e0, 0x03010302},
1553 {0x0000a0e4, 0x031f0300},
1554 {0x0000a0e8, 0x0402031e},
1555 {0x0000a0ec, 0x04000401},
1556 {0x0000a0f0, 0x041e041f},
1557 {0x0000a0f4, 0x05010502},
1558 {0x0000a0f8, 0x051f0500},
1559 {0x0000a0fc, 0x0602051e},
1560 {0x0000a100, 0x06000601},
1561 {0x0000a104, 0x061e061f},
1562 {0x0000a108, 0x0703061d},
1563 {0x0000a10c, 0x07010702},
1564 {0x0000a110, 0x00000700},
1565 {0x0000a114, 0x00000000},
1566 {0x0000a118, 0x00000000},
1567 {0x0000a11c, 0x00000000},
1568 {0x0000a120, 0x00000000},
1569 {0x0000a124, 0x00000000},
1570 {0x0000a128, 0x00000000},
1571 {0x0000a12c, 0x00000000},
1572 {0x0000a130, 0x00000000},
1573 {0x0000a134, 0x00000000},
1574 {0x0000a138, 0x00000000},
1575 {0x0000a13c, 0x00000000},
1576 {0x0000a140, 0x001f0000},
1577 {0x0000a144, 0x011f0100},
1578 {0x0000a148, 0x011d011e},
1579 {0x0000a14c, 0x011b011c},
1580 {0x0000a150, 0x02030204},
1581 {0x0000a154, 0x02010202},
1582 {0x0000a158, 0x021f0200},
1583 {0x0000a15c, 0x021d021e},
1584 {0x0000a160, 0x03010302},
1585 {0x0000a164, 0x031f0300},
1586 {0x0000a168, 0x0402031e},
1587 {0x0000a16c, 0x04000401},
1588 {0x0000a170, 0x041e041f},
1589 {0x0000a174, 0x05010502},
1590 {0x0000a178, 0x051f0500},
1591 {0x0000a17c, 0x0602051e},
1592 {0x0000a180, 0x06000601},
1593 {0x0000a184, 0x061e061f},
1594 {0x0000a188, 0x0703061d},
1595 {0x0000a18c, 0x07010702},
1596 {0x0000a190, 0x00000700},
1597 {0x0000a194, 0x00000000},
1598 {0x0000a198, 0x00000000},
1599 {0x0000a19c, 0x00000000},
1600 {0x0000a1a0, 0x00000000},
1601 {0x0000a1a4, 0x00000000},
1602 {0x0000a1a8, 0x00000000},
1603 {0x0000a1ac, 0x00000000},
1604 {0x0000a1b0, 0x00000000},
1605 {0x0000a1b4, 0x00000000},
1606 {0x0000a1b8, 0x00000000},
1607 {0x0000a1bc, 0x00000000},
1608 {0x0000a1c0, 0x00000000},
1609 {0x0000a1c4, 0x00000000},
1610 {0x0000a1c8, 0x00000000},
1611 {0x0000a1cc, 0x00000000},
1612 {0x0000a1d0, 0x00000000},
1613 {0x0000a1d4, 0x00000000},
1614 {0x0000a1d8, 0x00000000},
1615 {0x0000a1dc, 0x00000000},
1616 {0x0000a1e0, 0x00000000},
1617 {0x0000a1e4, 0x00000000},
1618 {0x0000a1e8, 0x00000000},
1619 {0x0000a1ec, 0x00000000},
1620 {0x0000a1f0, 0x00000396},
1621 {0x0000a1f4, 0x00000396},
1622 {0x0000a1f8, 0x00000396},
1623 {0x0000a1fc, 0x00000296},
1624 {0x0000b000, 0x00010000},
1625 {0x0000b004, 0x00030002},
1626 {0x0000b008, 0x00050004},
1627 {0x0000b00c, 0x00810080},
1628 {0x0000b010, 0x00830082},
1629 {0x0000b014, 0x01810180},
1630 {0x0000b018, 0x01830182},
1631 {0x0000b01c, 0x01850184},
1632 {0x0000b020, 0x02810280},
1633 {0x0000b024, 0x02830282},
1634 {0x0000b028, 0x02850284},
1635 {0x0000b02c, 0x02890288},
1636 {0x0000b030, 0x028b028a},
1637 {0x0000b034, 0x0388028c},
1638 {0x0000b038, 0x038a0389},
1639 {0x0000b03c, 0x038c038b},
1640 {0x0000b040, 0x0390038d},
1641 {0x0000b044, 0x03920391},
1642 {0x0000b048, 0x03940393},
1643 {0x0000b04c, 0x03960395},
1644 {0x0000b050, 0x00000000},
1645 {0x0000b054, 0x00000000},
1646 {0x0000b058, 0x00000000},
1647 {0x0000b05c, 0x00000000},
1648 {0x0000b060, 0x00000000},
1649 {0x0000b064, 0x00000000},
1650 {0x0000b068, 0x00000000},
1651 {0x0000b06c, 0x00000000},
1652 {0x0000b070, 0x00000000},
1653 {0x0000b074, 0x00000000},
1654 {0x0000b078, 0x00000000},
1655 {0x0000b07c, 0x00000000},
1656 {0x0000b080, 0x32323232},
1657 {0x0000b084, 0x2f2f3232},
1658 {0x0000b088, 0x23282a2d},
1659 {0x0000b08c, 0x1c1e2123},
1660 {0x0000b090, 0x14171919},
1661 {0x0000b094, 0x0e0e1214},
1662 {0x0000b098, 0x03050707},
1663 {0x0000b09c, 0x00030303},
1664 {0x0000b0a0, 0x00000000},
1665 {0x0000b0a4, 0x00000000},
1666 {0x0000b0a8, 0x00000000},
1667 {0x0000b0ac, 0x00000000},
1668 {0x0000b0b0, 0x00000000},
1669 {0x0000b0b4, 0x00000000},
1670 {0x0000b0b8, 0x00000000},
1671 {0x0000b0bc, 0x00000000},
1672 {0x0000b0c0, 0x003f0020},
1673 {0x0000b0c4, 0x00400041},
1674 {0x0000b0c8, 0x0140005f},
1675 {0x0000b0cc, 0x0160015f},
1676 {0x0000b0d0, 0x017e017f},
1677 {0x0000b0d4, 0x02410242},
1678 {0x0000b0d8, 0x025f0240},
1679 {0x0000b0dc, 0x027f0260},
1680 {0x0000b0e0, 0x0341027e},
1681 {0x0000b0e4, 0x035f0340},
1682 {0x0000b0e8, 0x037f0360},
1683 {0x0000b0ec, 0x04400441},
1684 {0x0000b0f0, 0x0460045f},
1685 {0x0000b0f4, 0x0541047f},
1686 {0x0000b0f8, 0x055f0540},
1687 {0x0000b0fc, 0x057f0560},
1688 {0x0000b100, 0x06400641},
1689 {0x0000b104, 0x0660065f},
1690 {0x0000b108, 0x067e067f},
1691 {0x0000b10c, 0x07410742},
1692 {0x0000b110, 0x075f0740},
1693 {0x0000b114, 0x077f0760},
1694 {0x0000b118, 0x07800781},
1695 {0x0000b11c, 0x07a0079f},
1696 {0x0000b120, 0x07c107bf},
1697 {0x0000b124, 0x000007c0},
1698 {0x0000b128, 0x00000000},
1699 {0x0000b12c, 0x00000000},
1700 {0x0000b130, 0x00000000},
1701 {0x0000b134, 0x00000000},
1702 {0x0000b138, 0x00000000},
1703 {0x0000b13c, 0x00000000},
1704 {0x0000b140, 0x003f0020},
1705 {0x0000b144, 0x00400041},
1706 {0x0000b148, 0x0140005f},
1707 {0x0000b14c, 0x0160015f},
1708 {0x0000b150, 0x017e017f},
1709 {0x0000b154, 0x02410242},
1710 {0x0000b158, 0x025f0240},
1711 {0x0000b15c, 0x027f0260},
1712 {0x0000b160, 0x0341027e},
1713 {0x0000b164, 0x035f0340},
1714 {0x0000b168, 0x037f0360},
1715 {0x0000b16c, 0x04400441},
1716 {0x0000b170, 0x0460045f},
1717 {0x0000b174, 0x0541047f},
1718 {0x0000b178, 0x055f0540},
1719 {0x0000b17c, 0x057f0560},
1720 {0x0000b180, 0x06400641},
1721 {0x0000b184, 0x0660065f},
1722 {0x0000b188, 0x067e067f},
1723 {0x0000b18c, 0x07410742},
1724 {0x0000b190, 0x075f0740},
1725 {0x0000b194, 0x077f0760},
1726 {0x0000b198, 0x07800781},
1727 {0x0000b19c, 0x07a0079f},
1728 {0x0000b1a0, 0x07c107bf},
1729 {0x0000b1a4, 0x000007c0},
1730 {0x0000b1a8, 0x00000000},
1731 {0x0000b1ac, 0x00000000},
1732 {0x0000b1b0, 0x00000000},
1733 {0x0000b1b4, 0x00000000},
1734 {0x0000b1b8, 0x00000000},
1735 {0x0000b1bc, 0x00000000},
1736 {0x0000b1c0, 0x00000000},
1737 {0x0000b1c4, 0x00000000},
1738 {0x0000b1c8, 0x00000000},
1739 {0x0000b1cc, 0x00000000},
1740 {0x0000b1d0, 0x00000000},
1741 {0x0000b1d4, 0x00000000},
1742 {0x0000b1d8, 0x00000000},
1743 {0x0000b1dc, 0x00000000},
1744 {0x0000b1e0, 0x00000000},
1745 {0x0000b1e4, 0x00000000},
1746 {0x0000b1e8, 0x00000000},
1747 {0x0000b1ec, 0x00000000},
1748 {0x0000b1f0, 0x00000396},
1749 {0x0000b1f4, 0x00000396},
1750 {0x0000b1f8, 0x00000396},
1751 {0x0000b1fc, 0x00000196},
1752};
1753
1754static const u32 ar9300_2p0_soc_preamble[][2] = {
1755 /* Addr allmodes */
1756 {0x000040a4, 0x00a0c1c9},
1757 {0x00007008, 0x00000000},
1758 {0x00007020, 0x00000000},
1759 {0x00007034, 0x00000002},
1760 {0x00007038, 0x000004c2},
1761};
1762
1763static const u32 ar9300PciePhy_pll_on_clkreq_disable_L1_2p0[][2] = {
1764 /* Addr allmodes */
1765 {0x00004040, 0x08212e5e},
1766 {0x00004040, 0x0008003b},
1767 {0x00004044, 0x00000000},
1768};
1769
1770static const u32 ar9300PciePhy_clkreq_enable_L1_2p0[][2] = {
1771 /* Addr allmodes */
1772 {0x00004040, 0x08253e5e},
1773 {0x00004040, 0x0008003b},
1774 {0x00004044, 0x00000000},
1775};
1776
1777static const u32 ar9300PciePhy_clkreq_disable_L1_2p0[][2] = {
1778 /* Addr allmodes */
1779 {0x00004040, 0x08213e5e},
1780 {0x00004040, 0x0008003b},
1781 {0x00004044, 0x00000000},
1782};
1783
1784#endif /* INITVALS_9003_H */
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_mac.c b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
new file mode 100644
index 000000000000..37ba37481a47
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
@@ -0,0 +1,614 @@
1/*
2 * Copyright (c) 2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16#include "hw.h"
17#include "ar9003_mac.h"
18
19static void ar9003_hw_rx_enable(struct ath_hw *hw)
20{
21 REG_WRITE(hw, AR_CR, 0);
22}
23
24static u16 ar9003_calc_ptr_chksum(struct ar9003_txc *ads)
25{
26 int checksum;
27
28 checksum = ads->info + ads->link
29 + ads->data0 + ads->ctl3
30 + ads->data1 + ads->ctl5
31 + ads->data2 + ads->ctl7
32 + ads->data3 + ads->ctl9;
33
34 return ((checksum & 0xffff) + (checksum >> 16)) & AR_TxPtrChkSum;
35}
36
37static void ar9003_hw_set_desc_link(void *ds, u32 ds_link)
38{
39 struct ar9003_txc *ads = ds;
40
41 ads->link = ds_link;
42 ads->ctl10 &= ~AR_TxPtrChkSum;
43 ads->ctl10 |= ar9003_calc_ptr_chksum(ads);
44}
45
46static void ar9003_hw_get_desc_link(void *ds, u32 **ds_link)
47{
48 struct ar9003_txc *ads = ds;
49
50 *ds_link = &ads->link;
51}
52
53static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
54{
55 u32 isr = 0;
56 u32 mask2 = 0;
57 struct ath9k_hw_capabilities *pCap = &ah->caps;
58 u32 sync_cause = 0;
59 struct ath_common *common = ath9k_hw_common(ah);
60
61 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
62 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
63 == AR_RTC_STATUS_ON)
64 isr = REG_READ(ah, AR_ISR);
65 }
66
67 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & AR_INTR_SYNC_DEFAULT;
68
69 *masked = 0;
70
71 if (!isr && !sync_cause)
72 return false;
73
74 if (isr) {
75 if (isr & AR_ISR_BCNMISC) {
76 u32 isr2;
77 isr2 = REG_READ(ah, AR_ISR_S2);
78
79 mask2 |= ((isr2 & AR_ISR_S2_TIM) >>
80 MAP_ISR_S2_TIM);
81 mask2 |= ((isr2 & AR_ISR_S2_DTIM) >>
82 MAP_ISR_S2_DTIM);
83 mask2 |= ((isr2 & AR_ISR_S2_DTIMSYNC) >>
84 MAP_ISR_S2_DTIMSYNC);
85 mask2 |= ((isr2 & AR_ISR_S2_CABEND) >>
86 MAP_ISR_S2_CABEND);
87 mask2 |= ((isr2 & AR_ISR_S2_GTT) <<
88 MAP_ISR_S2_GTT);
89 mask2 |= ((isr2 & AR_ISR_S2_CST) <<
90 MAP_ISR_S2_CST);
91 mask2 |= ((isr2 & AR_ISR_S2_TSFOOR) >>
92 MAP_ISR_S2_TSFOOR);
93
94 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
95 REG_WRITE(ah, AR_ISR_S2, isr2);
96 isr &= ~AR_ISR_BCNMISC;
97 }
98 }
99
100 if ((pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED))
101 isr = REG_READ(ah, AR_ISR_RAC);
102
103 if (isr == 0xffffffff) {
104 *masked = 0;
105 return false;
106 }
107
108 *masked = isr & ATH9K_INT_COMMON;
109
110 if (ah->config.rx_intr_mitigation)
111 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
112 *masked |= ATH9K_INT_RXLP;
113
114 if (ah->config.tx_intr_mitigation)
115 if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM))
116 *masked |= ATH9K_INT_TX;
117
118 if (isr & (AR_ISR_LP_RXOK | AR_ISR_RXERR))
119 *masked |= ATH9K_INT_RXLP;
120
121 if (isr & AR_ISR_HP_RXOK)
122 *masked |= ATH9K_INT_RXHP;
123
124 if (isr & (AR_ISR_TXOK | AR_ISR_TXERR | AR_ISR_TXEOL)) {
125 *masked |= ATH9K_INT_TX;
126
127 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
128 u32 s0, s1;
129 s0 = REG_READ(ah, AR_ISR_S0);
130 REG_WRITE(ah, AR_ISR_S0, s0);
131 s1 = REG_READ(ah, AR_ISR_S1);
132 REG_WRITE(ah, AR_ISR_S1, s1);
133
134 isr &= ~(AR_ISR_TXOK | AR_ISR_TXERR |
135 AR_ISR_TXEOL);
136 }
137 }
138
139 if (isr & AR_ISR_GENTMR) {
140 u32 s5;
141
142 if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)
143 s5 = REG_READ(ah, AR_ISR_S5_S);
144 else
145 s5 = REG_READ(ah, AR_ISR_S5);
146
147 ah->intr_gen_timer_trigger =
148 MS(s5, AR_ISR_S5_GENTIMER_TRIG);
149
150 ah->intr_gen_timer_thresh =
151 MS(s5, AR_ISR_S5_GENTIMER_THRESH);
152
153 if (ah->intr_gen_timer_trigger)
154 *masked |= ATH9K_INT_GENTIMER;
155
156 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
157 REG_WRITE(ah, AR_ISR_S5, s5);
158 isr &= ~AR_ISR_GENTMR;
159 }
160
161 }
162
163 *masked |= mask2;
164
165 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
166 REG_WRITE(ah, AR_ISR, isr);
167
168 (void) REG_READ(ah, AR_ISR);
169 }
170 }
171
172 if (sync_cause) {
173 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
174 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
175 REG_WRITE(ah, AR_RC, 0);
176 *masked |= ATH9K_INT_FATAL;
177 }
178
179 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT)
180 ath_print(common, ATH_DBG_INTERRUPT,
181 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
182
183 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
184 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
185
186 }
187 return true;
188}
189
190static void ar9003_hw_fill_txdesc(struct ath_hw *ah, void *ds, u32 seglen,
191 bool is_firstseg, bool is_lastseg,
192 const void *ds0, dma_addr_t buf_addr,
193 unsigned int qcu)
194{
195 struct ar9003_txc *ads = (struct ar9003_txc *) ds;
196 unsigned int descid = 0;
197
198 ads->info = (ATHEROS_VENDOR_ID << AR_DescId_S) |
199 (1 << AR_TxRxDesc_S) |
200 (1 << AR_CtrlStat_S) |
201 (qcu << AR_TxQcuNum_S) | 0x17;
202
203 ads->data0 = buf_addr;
204 ads->data1 = 0;
205 ads->data2 = 0;
206 ads->data3 = 0;
207
208 ads->ctl3 = (seglen << AR_BufLen_S);
209 ads->ctl3 &= AR_BufLen;
210
211 /* Fill in pointer checksum and descriptor id */
212 ads->ctl10 = ar9003_calc_ptr_chksum(ads);
213 ads->ctl10 |= (descid << AR_TxDescId_S);
214
215 if (is_firstseg) {
216 ads->ctl12 |= (is_lastseg ? 0 : AR_TxMore);
217 } else if (is_lastseg) {
218 ads->ctl11 = 0;
219 ads->ctl12 = 0;
220 ads->ctl13 = AR9003TXC_CONST(ds0)->ctl13;
221 ads->ctl14 = AR9003TXC_CONST(ds0)->ctl14;
222 } else {
223 /* XXX Intermediate descriptor in a multi-descriptor frame.*/
224 ads->ctl11 = 0;
225 ads->ctl12 = AR_TxMore;
226 ads->ctl13 = 0;
227 ads->ctl14 = 0;
228 }
229}
230
231static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds,
232 struct ath_tx_status *ts)
233{
234 struct ar9003_txs *ads;
235
236 ads = &ah->ts_ring[ah->ts_tail];
237
238 if ((ads->status8 & AR_TxDone) == 0)
239 return -EINPROGRESS;
240
241 ah->ts_tail = (ah->ts_tail + 1) % ah->ts_size;
242
243 if ((MS(ads->ds_info, AR_DescId) != ATHEROS_VENDOR_ID) ||
244 (MS(ads->ds_info, AR_TxRxDesc) != 1)) {
245 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
246 "Tx Descriptor error %x\n", ads->ds_info);
247 memset(ads, 0, sizeof(*ads));
248 return -EIO;
249 }
250
251 ts->qid = MS(ads->ds_info, AR_TxQcuNum);
252 ts->desc_id = MS(ads->status1, AR_TxDescId);
253 ts->ts_seqnum = MS(ads->status8, AR_SeqNum);
254 ts->ts_tstamp = ads->status4;
255 ts->ts_status = 0;
256 ts->ts_flags = 0;
257
258 if (ads->status3 & AR_ExcessiveRetries)
259 ts->ts_status |= ATH9K_TXERR_XRETRY;
260 if (ads->status3 & AR_Filtered)
261 ts->ts_status |= ATH9K_TXERR_FILT;
262 if (ads->status3 & AR_FIFOUnderrun) {
263 ts->ts_status |= ATH9K_TXERR_FIFO;
264 ath9k_hw_updatetxtriglevel(ah, true);
265 }
266 if (ads->status8 & AR_TxOpExceeded)
267 ts->ts_status |= ATH9K_TXERR_XTXOP;
268 if (ads->status3 & AR_TxTimerExpired)
269 ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
270
271 if (ads->status3 & AR_DescCfgErr)
272 ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
273 if (ads->status3 & AR_TxDataUnderrun) {
274 ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
275 ath9k_hw_updatetxtriglevel(ah, true);
276 }
277 if (ads->status3 & AR_TxDelimUnderrun) {
278 ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
279 ath9k_hw_updatetxtriglevel(ah, true);
280 }
281 if (ads->status2 & AR_TxBaStatus) {
282 ts->ts_flags |= ATH9K_TX_BA;
283 ts->ba_low = ads->status5;
284 ts->ba_high = ads->status6;
285 }
286
287 ts->ts_rateindex = MS(ads->status8, AR_FinalTxIdx);
288
289 ts->ts_rssi = MS(ads->status7, AR_TxRSSICombined);
290 ts->ts_rssi_ctl0 = MS(ads->status2, AR_TxRSSIAnt00);
291 ts->ts_rssi_ctl1 = MS(ads->status2, AR_TxRSSIAnt01);
292 ts->ts_rssi_ctl2 = MS(ads->status2, AR_TxRSSIAnt02);
293 ts->ts_rssi_ext0 = MS(ads->status7, AR_TxRSSIAnt10);
294 ts->ts_rssi_ext1 = MS(ads->status7, AR_TxRSSIAnt11);
295 ts->ts_rssi_ext2 = MS(ads->status7, AR_TxRSSIAnt12);
296 ts->ts_shortretry = MS(ads->status3, AR_RTSFailCnt);
297 ts->ts_longretry = MS(ads->status3, AR_DataFailCnt);
298 ts->ts_virtcol = MS(ads->status3, AR_VirtRetryCnt);
299 ts->ts_antenna = 0;
300
301 ts->tid = MS(ads->status8, AR_TxTid);
302
303 memset(ads, 0, sizeof(*ads));
304
305 return 0;
306}
307
308static void ar9003_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
309 u32 pktlen, enum ath9k_pkt_type type, u32 txpower,
310 u32 keyIx, enum ath9k_key_type keyType, u32 flags)
311{
312 struct ar9003_txc *ads = (struct ar9003_txc *) ds;
313
314 if (txpower > ah->txpower_limit)
315 txpower = ah->txpower_limit;
316
317 txpower += ah->txpower_indexoffset;
318 if (txpower > 63)
319 txpower = 63;
320
321 ads->ctl11 = (pktlen & AR_FrameLen)
322 | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
323 | SM(txpower, AR_XmitPower)
324 | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
325 | (flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
326 | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0)
327 | (flags & ATH9K_TXDESC_LOWRXCHAIN ? AR_LowRxChain : 0);
328
329 ads->ctl12 =
330 (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
331 | SM(type, AR_FrameType)
332 | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
333 | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
334 | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
335
336 ads->ctl17 = SM(keyType, AR_EncrType) |
337 (flags & ATH9K_TXDESC_LDPC ? AR_LDPC : 0);
338 ads->ctl18 = 0;
339 ads->ctl19 = AR_Not_Sounding;
340
341 ads->ctl20 = 0;
342 ads->ctl21 = 0;
343 ads->ctl22 = 0;
344}
345
346static void ar9003_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
347 void *lastds,
348 u32 durUpdateEn, u32 rtsctsRate,
349 u32 rtsctsDuration,
350 struct ath9k_11n_rate_series series[],
351 u32 nseries, u32 flags)
352{
353 struct ar9003_txc *ads = (struct ar9003_txc *) ds;
354 struct ar9003_txc *last_ads = (struct ar9003_txc *) lastds;
355 u_int32_t ctl11;
356
357 if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
358 ctl11 = ads->ctl11;
359
360 if (flags & ATH9K_TXDESC_RTSENA) {
361 ctl11 &= ~AR_CTSEnable;
362 ctl11 |= AR_RTSEnable;
363 } else {
364 ctl11 &= ~AR_RTSEnable;
365 ctl11 |= AR_CTSEnable;
366 }
367
368 ads->ctl11 = ctl11;
369 } else {
370 ads->ctl11 = (ads->ctl11 & ~(AR_RTSEnable | AR_CTSEnable));
371 }
372
373 ads->ctl13 = set11nTries(series, 0)
374 | set11nTries(series, 1)
375 | set11nTries(series, 2)
376 | set11nTries(series, 3)
377 | (durUpdateEn ? AR_DurUpdateEna : 0)
378 | SM(0, AR_BurstDur);
379
380 ads->ctl14 = set11nRate(series, 0)
381 | set11nRate(series, 1)
382 | set11nRate(series, 2)
383 | set11nRate(series, 3);
384
385 ads->ctl15 = set11nPktDurRTSCTS(series, 0)
386 | set11nPktDurRTSCTS(series, 1);
387
388 ads->ctl16 = set11nPktDurRTSCTS(series, 2)
389 | set11nPktDurRTSCTS(series, 3);
390
391 ads->ctl18 = set11nRateFlags(series, 0)
392 | set11nRateFlags(series, 1)
393 | set11nRateFlags(series, 2)
394 | set11nRateFlags(series, 3)
395 | SM(rtsctsRate, AR_RTSCTSRate);
396 ads->ctl19 = AR_Not_Sounding;
397
398 last_ads->ctl13 = ads->ctl13;
399 last_ads->ctl14 = ads->ctl14;
400}
401
402static void ar9003_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
403 u32 aggrLen)
404{
405 struct ar9003_txc *ads = (struct ar9003_txc *) ds;
406
407 ads->ctl12 |= (AR_IsAggr | AR_MoreAggr);
408
409 ads->ctl17 &= ~AR_AggrLen;
410 ads->ctl17 |= SM(aggrLen, AR_AggrLen);
411}
412
413static void ar9003_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
414 u32 numDelims)
415{
416 struct ar9003_txc *ads = (struct ar9003_txc *) ds;
417 unsigned int ctl17;
418
419 ads->ctl12 |= (AR_IsAggr | AR_MoreAggr);
420
421 /*
422 * We use a stack variable to manipulate ctl6 to reduce uncached
423 * read modify, modfiy, write.
424 */
425 ctl17 = ads->ctl17;
426 ctl17 &= ~AR_PadDelim;
427 ctl17 |= SM(numDelims, AR_PadDelim);
428 ads->ctl17 = ctl17;
429}
430
431static void ar9003_hw_set11n_aggr_last(struct ath_hw *ah, void *ds)
432{
433 struct ar9003_txc *ads = (struct ar9003_txc *) ds;
434
435 ads->ctl12 |= AR_IsAggr;
436 ads->ctl12 &= ~AR_MoreAggr;
437 ads->ctl17 &= ~AR_PadDelim;
438}
439
440static void ar9003_hw_clr11n_aggr(struct ath_hw *ah, void *ds)
441{
442 struct ar9003_txc *ads = (struct ar9003_txc *) ds;
443
444 ads->ctl12 &= (~AR_IsAggr & ~AR_MoreAggr);
445}
446
447static void ar9003_hw_set11n_burstduration(struct ath_hw *ah, void *ds,
448 u32 burstDuration)
449{
450 struct ar9003_txc *ads = (struct ar9003_txc *) ds;
451
452 ads->ctl13 &= ~AR_BurstDur;
453 ads->ctl13 |= SM(burstDuration, AR_BurstDur);
454
455}
456
457static void ar9003_hw_set11n_virtualmorefrag(struct ath_hw *ah, void *ds,
458 u32 vmf)
459{
460 struct ar9003_txc *ads = (struct ar9003_txc *) ds;
461
462 if (vmf)
463 ads->ctl11 |= AR_VirtMoreFrag;
464 else
465 ads->ctl11 &= ~AR_VirtMoreFrag;
466}
467
468void ar9003_hw_attach_mac_ops(struct ath_hw *hw)
469{
470 struct ath_hw_ops *ops = ath9k_hw_ops(hw);
471
472 ops->rx_enable = ar9003_hw_rx_enable;
473 ops->set_desc_link = ar9003_hw_set_desc_link;
474 ops->get_desc_link = ar9003_hw_get_desc_link;
475 ops->get_isr = ar9003_hw_get_isr;
476 ops->fill_txdesc = ar9003_hw_fill_txdesc;
477 ops->proc_txdesc = ar9003_hw_proc_txdesc;
478 ops->set11n_txdesc = ar9003_hw_set11n_txdesc;
479 ops->set11n_ratescenario = ar9003_hw_set11n_ratescenario;
480 ops->set11n_aggr_first = ar9003_hw_set11n_aggr_first;
481 ops->set11n_aggr_middle = ar9003_hw_set11n_aggr_middle;
482 ops->set11n_aggr_last = ar9003_hw_set11n_aggr_last;
483 ops->clr11n_aggr = ar9003_hw_clr11n_aggr;
484 ops->set11n_burstduration = ar9003_hw_set11n_burstduration;
485 ops->set11n_virtualmorefrag = ar9003_hw_set11n_virtualmorefrag;
486}
487
488void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size)
489{
490 REG_WRITE(ah, AR_DATABUF_SIZE, buf_size & AR_DATABUF_SIZE_MASK);
491}
492EXPORT_SYMBOL(ath9k_hw_set_rx_bufsize);
493
494void ath9k_hw_addrxbuf_edma(struct ath_hw *ah, u32 rxdp,
495 enum ath9k_rx_qtype qtype)
496{
497 if (qtype == ATH9K_RX_QUEUE_HP)
498 REG_WRITE(ah, AR_HP_RXDP, rxdp);
499 else
500 REG_WRITE(ah, AR_LP_RXDP, rxdp);
501}
502EXPORT_SYMBOL(ath9k_hw_addrxbuf_edma);
503
504int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah, struct ath_rx_status *rxs,
505 void *buf_addr)
506{
507 struct ar9003_rxs *rxsp = (struct ar9003_rxs *) buf_addr;
508 unsigned int phyerr;
509
510 /* TODO: byte swap on big endian for ar9300_10 */
511
512 if ((rxsp->status11 & AR_RxDone) == 0)
513 return -EINPROGRESS;
514
515 if (MS(rxsp->ds_info, AR_DescId) != 0x168c)
516 return -EINVAL;
517
518 if ((rxsp->ds_info & (AR_TxRxDesc | AR_CtrlStat)) != 0)
519 return -EINPROGRESS;
520
521 if (!rxs)
522 return 0;
523
524 rxs->rs_status = 0;
525 rxs->rs_flags = 0;
526
527 rxs->rs_datalen = rxsp->status2 & AR_DataLen;
528 rxs->rs_tstamp = rxsp->status3;
529
530 /* XXX: Keycache */
531 rxs->rs_rssi = MS(rxsp->status5, AR_RxRSSICombined);
532 rxs->rs_rssi_ctl0 = MS(rxsp->status1, AR_RxRSSIAnt00);
533 rxs->rs_rssi_ctl1 = MS(rxsp->status1, AR_RxRSSIAnt01);
534 rxs->rs_rssi_ctl2 = MS(rxsp->status1, AR_RxRSSIAnt02);
535 rxs->rs_rssi_ext0 = MS(rxsp->status5, AR_RxRSSIAnt10);
536 rxs->rs_rssi_ext1 = MS(rxsp->status5, AR_RxRSSIAnt11);
537 rxs->rs_rssi_ext2 = MS(rxsp->status5, AR_RxRSSIAnt12);
538
539 if (rxsp->status11 & AR_RxKeyIdxValid)
540 rxs->rs_keyix = MS(rxsp->status11, AR_KeyIdx);
541 else
542 rxs->rs_keyix = ATH9K_RXKEYIX_INVALID;
543
544 rxs->rs_rate = MS(rxsp->status1, AR_RxRate);
545 rxs->rs_more = (rxsp->status2 & AR_RxMore) ? 1 : 0;
546
547 rxs->rs_isaggr = (rxsp->status11 & AR_RxAggr) ? 1 : 0;
548 rxs->rs_moreaggr = (rxsp->status11 & AR_RxMoreAggr) ? 1 : 0;
549 rxs->rs_antenna = (MS(rxsp->status4, AR_RxAntenna) & 0x7);
550 rxs->rs_flags = (rxsp->status4 & AR_GI) ? ATH9K_RX_GI : 0;
551 rxs->rs_flags |= (rxsp->status4 & AR_2040) ? ATH9K_RX_2040 : 0;
552
553 rxs->evm0 = rxsp->status6;
554 rxs->evm1 = rxsp->status7;
555 rxs->evm2 = rxsp->status8;
556 rxs->evm3 = rxsp->status9;
557 rxs->evm4 = (rxsp->status10 & 0xffff);
558
559 if (rxsp->status11 & AR_PreDelimCRCErr)
560 rxs->rs_flags |= ATH9K_RX_DELIM_CRC_PRE;
561
562 if (rxsp->status11 & AR_PostDelimCRCErr)
563 rxs->rs_flags |= ATH9K_RX_DELIM_CRC_POST;
564
565 if (rxsp->status11 & AR_DecryptBusyErr)
566 rxs->rs_flags |= ATH9K_RX_DECRYPT_BUSY;
567
568 if ((rxsp->status11 & AR_RxFrameOK) == 0) {
569 if (rxsp->status11 & AR_CRCErr) {
570 rxs->rs_status |= ATH9K_RXERR_CRC;
571 } else if (rxsp->status11 & AR_PHYErr) {
572 rxs->rs_status |= ATH9K_RXERR_PHY;
573 phyerr = MS(rxsp->status11, AR_PHYErrCode);
574 rxs->rs_phyerr = phyerr;
575 } else if (rxsp->status11 & AR_DecryptCRCErr) {
576 rxs->rs_status |= ATH9K_RXERR_DECRYPT;
577 } else if (rxsp->status11 & AR_MichaelErr) {
578 rxs->rs_status |= ATH9K_RXERR_MIC;
579 }
580 }
581
582 return 0;
583}
584EXPORT_SYMBOL(ath9k_hw_process_rxdesc_edma);
585
586void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah)
587{
588 ah->ts_tail = 0;
589
590 memset((void *) ah->ts_ring, 0,
591 ah->ts_size * sizeof(struct ar9003_txs));
592
593 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
594 "TS Start 0x%x End 0x%x Virt %p, Size %d\n",
595 ah->ts_paddr_start, ah->ts_paddr_end,
596 ah->ts_ring, ah->ts_size);
597
598 REG_WRITE(ah, AR_Q_STATUS_RING_START, ah->ts_paddr_start);
599 REG_WRITE(ah, AR_Q_STATUS_RING_END, ah->ts_paddr_end);
600}
601
602void ath9k_hw_setup_statusring(struct ath_hw *ah, void *ts_start,
603 u32 ts_paddr_start,
604 u8 size)
605{
606
607 ah->ts_paddr_start = ts_paddr_start;
608 ah->ts_paddr_end = ts_paddr_start + (size * sizeof(struct ar9003_txs));
609 ah->ts_size = size;
610 ah->ts_ring = (struct ar9003_txs *) ts_start;
611
612 ath9k_hw_reset_txstatus_ring(ah);
613}
614EXPORT_SYMBOL(ath9k_hw_setup_statusring);
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_mac.h b/drivers/net/wireless/ath/ath9k/ar9003_mac.h
new file mode 100644
index 000000000000..f17558b14539
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.h
@@ -0,0 +1,120 @@
1/*
2 * Copyright (c) 2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef AR9003_MAC_H
18#define AR9003_MAC_H
19
20#define AR_DescId 0xffff0000
21#define AR_DescId_S 16
22#define AR_CtrlStat 0x00004000
23#define AR_CtrlStat_S 14
24#define AR_TxRxDesc 0x00008000
25#define AR_TxRxDesc_S 15
26#define AR_TxQcuNum 0x00000f00
27#define AR_TxQcuNum_S 8
28
29#define AR_BufLen 0x0fff0000
30#define AR_BufLen_S 16
31
32#define AR_TxDescId 0xffff0000
33#define AR_TxDescId_S 16
34#define AR_TxPtrChkSum 0x0000ffff
35
36#define AR_TxTid 0xf0000000
37#define AR_TxTid_S 28
38
39#define AR_LowRxChain 0x00004000
40
41#define AR_Not_Sounding 0x20000000
42
43#define MAP_ISR_S2_CST 6
44#define MAP_ISR_S2_GTT 6
45#define MAP_ISR_S2_TIM 3
46#define MAP_ISR_S2_CABEND 0
47#define MAP_ISR_S2_DTIMSYNC 7
48#define MAP_ISR_S2_DTIM 7
49#define MAP_ISR_S2_TSFOOR 4
50
51#define AR9003TXC_CONST(_ds) ((const struct ar9003_txc *) _ds)
52
53struct ar9003_rxs {
54 u32 ds_info;
55 u32 status1;
56 u32 status2;
57 u32 status3;
58 u32 status4;
59 u32 status5;
60 u32 status6;
61 u32 status7;
62 u32 status8;
63 u32 status9;
64 u32 status10;
65 u32 status11;
66} __packed;
67
68/* Transmit Control Descriptor */
69struct ar9003_txc {
70 u32 info; /* descriptor information */
71 u32 link; /* link pointer */
72 u32 data0; /* data pointer to 1st buffer */
73 u32 ctl3; /* DMA control 3 */
74 u32 data1; /* data pointer to 2nd buffer */
75 u32 ctl5; /* DMA control 5 */
76 u32 data2; /* data pointer to 3rd buffer */
77 u32 ctl7; /* DMA control 7 */
78 u32 data3; /* data pointer to 4th buffer */
79 u32 ctl9; /* DMA control 9 */
80 u32 ctl10; /* DMA control 10 */
81 u32 ctl11; /* DMA control 11 */
82 u32 ctl12; /* DMA control 12 */
83 u32 ctl13; /* DMA control 13 */
84 u32 ctl14; /* DMA control 14 */
85 u32 ctl15; /* DMA control 15 */
86 u32 ctl16; /* DMA control 16 */
87 u32 ctl17; /* DMA control 17 */
88 u32 ctl18; /* DMA control 18 */
89 u32 ctl19; /* DMA control 19 */
90 u32 ctl20; /* DMA control 20 */
91 u32 ctl21; /* DMA control 21 */
92 u32 ctl22; /* DMA control 22 */
93 u32 pad[9]; /* pad to cache line (128 bytes/32 dwords) */
94} __packed;
95
96struct ar9003_txs {
97 u32 ds_info;
98 u32 status1;
99 u32 status2;
100 u32 status3;
101 u32 status4;
102 u32 status5;
103 u32 status6;
104 u32 status7;
105 u32 status8;
106} __packed;
107
108void ar9003_hw_attach_mac_ops(struct ath_hw *hw);
109void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size);
110void ath9k_hw_addrxbuf_edma(struct ath_hw *ah, u32 rxdp,
111 enum ath9k_rx_qtype qtype);
112
113int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah,
114 struct ath_rx_status *rxs,
115 void *buf_addr);
116void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah);
117void ath9k_hw_setup_statusring(struct ath_hw *ah, void *ts_start,
118 u32 ts_paddr_start,
119 u8 size);
120#endif
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
new file mode 100644
index 000000000000..80431a2f6dc1
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
@@ -0,0 +1,1134 @@
1/*
2 * Copyright (c) 2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "hw.h"
18#include "ar9003_phy.h"
19
20/**
21 * ar9003_hw_set_channel - set channel on single-chip device
22 * @ah: atheros hardware structure
23 * @chan:
24 *
25 * This is the function to change channel on single-chip devices, that is
26 * all devices after ar9280.
27 *
28 * This function takes the channel value in MHz and sets
29 * hardware channel value. Assumes writes have been enabled to analog bus.
30 *
31 * Actual Expression,
32 *
33 * For 2GHz channel,
34 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
35 * (freq_ref = 40MHz)
36 *
37 * For 5GHz channel,
38 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
39 * (freq_ref = 40MHz/(24>>amodeRefSel))
40 *
41 * For 5GHz channels which are 5MHz spaced,
42 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
43 * (freq_ref = 40MHz)
44 */
45static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
46{
47 u16 bMode, fracMode = 0, aModeRefSel = 0;
48 u32 freq, channelSel = 0, reg32 = 0;
49 struct chan_centers centers;
50 int loadSynthChannel;
51
52 ath9k_hw_get_channel_centers(ah, chan, &centers);
53 freq = centers.synth_center;
54
55 if (freq < 4800) { /* 2 GHz, fractional mode */
56 channelSel = CHANSEL_2G(freq);
57 /* Set to 2G mode */
58 bMode = 1;
59 } else {
60 channelSel = CHANSEL_5G(freq);
61 /* Doubler is ON, so, divide channelSel by 2. */
62 channelSel >>= 1;
63 /* Set to 5G mode */
64 bMode = 0;
65 }
66
67 /* Enable fractional mode for all channels */
68 fracMode = 1;
69 aModeRefSel = 0;
70 loadSynthChannel = 0;
71
72 reg32 = (bMode << 29);
73 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
74
75 /* Enable Long shift Select for Synthesizer */
76 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
77 AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
78
79 /* Program Synth. setting */
80 reg32 = (channelSel << 2) | (fracMode << 30) |
81 (aModeRefSel << 28) | (loadSynthChannel << 31);
82 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
83
84 /* Toggle Load Synth channel bit */
85 loadSynthChannel = 1;
86 reg32 = (channelSel << 2) | (fracMode << 30) |
87 (aModeRefSel << 28) | (loadSynthChannel << 31);
88 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
89
90 ah->curchan = chan;
91 ah->curchan_rad_index = -1;
92
93 return 0;
94}
95
96/**
97 * ar9003_hw_spur_mitigate - convert baseband spur frequency
98 * @ah: atheros hardware structure
99 * @chan:
100 *
101 * For single-chip solutions. Converts to baseband spur frequency given the
102 * input channel frequency and compute register settings below.
103 *
104 * Spur mitigation for MRC CCK
105 */
106static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
107 struct ath9k_channel *chan)
108{
109 u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
110 int cur_bb_spur, negative = 0, cck_spur_freq;
111 int i;
112
113 /*
114 * Need to verify range +/- 10 MHz in control channel, otherwise spur
115 * is out-of-band and can be ignored.
116 */
117
118 for (i = 0; i < 4; i++) {
119 negative = 0;
120 cur_bb_spur = spur_freq[i] - chan->channel;
121
122 if (cur_bb_spur < 0) {
123 negative = 1;
124 cur_bb_spur = -cur_bb_spur;
125 }
126 if (cur_bb_spur < 10) {
127 cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
128
129 if (negative == 1)
130 cck_spur_freq = -cck_spur_freq;
131
132 cck_spur_freq = cck_spur_freq & 0xfffff;
133
134 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
135 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
136 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
137 AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
138 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
139 AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
140 0x2);
141 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
142 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
143 0x1);
144 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
145 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
146 cck_spur_freq);
147
148 return;
149 }
150 }
151
152 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
153 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
154 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
155 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
156 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
157 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
158}
159
160/* Clean all spur register fields */
161static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
162{
163 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
164 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
165 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
166 AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
167 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
168 AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
169 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
170 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
171 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
172 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
173 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
174 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
175 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
176 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
177 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
178 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
179 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
180 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
181
182 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
183 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
184 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
185 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
186 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
187 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
188 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
189 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
190 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
191 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
192 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
193 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
194 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
195 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
196 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
197 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
198 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
199 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
200 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
201 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
202}
203
204static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
205 int freq_offset,
206 int spur_freq_sd,
207 int spur_delta_phase,
208 int spur_subchannel_sd)
209{
210 int mask_index = 0;
211
212 /* OFDM Spur mitigation */
213 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
214 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
215 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
216 AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
217 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
218 AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
219 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
220 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
221 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
222 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
223 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
224 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
225 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
226 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
227 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
228 AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
229 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
230 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
231
232 if (REG_READ_FIELD(ah, AR_PHY_MODE,
233 AR_PHY_MODE_DYNAMIC) == 0x1)
234 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
235 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
236
237 mask_index = (freq_offset << 4) / 5;
238 if (mask_index < 0)
239 mask_index = mask_index - 1;
240
241 mask_index = mask_index & 0x7f;
242
243 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
244 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
245 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
246 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
247 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
248 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
249 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
250 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
251 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
252 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
253 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
254 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
255 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
256 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
257 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
258 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
259 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
260 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
261 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
262 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
263}
264
265static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
266 struct ath9k_channel *chan,
267 int freq_offset)
268{
269 int spur_freq_sd = 0;
270 int spur_subchannel_sd = 0;
271 int spur_delta_phase = 0;
272
273 if (IS_CHAN_HT40(chan)) {
274 if (freq_offset < 0) {
275 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
276 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
277 spur_subchannel_sd = 1;
278 else
279 spur_subchannel_sd = 0;
280
281 spur_freq_sd = ((freq_offset + 10) << 9) / 11;
282
283 } else {
284 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
285 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
286 spur_subchannel_sd = 0;
287 else
288 spur_subchannel_sd = 1;
289
290 spur_freq_sd = ((freq_offset - 10) << 9) / 11;
291
292 }
293
294 spur_delta_phase = (freq_offset << 17) / 5;
295
296 } else {
297 spur_subchannel_sd = 0;
298 spur_freq_sd = (freq_offset << 9) /11;
299 spur_delta_phase = (freq_offset << 18) / 5;
300 }
301
302 spur_freq_sd = spur_freq_sd & 0x3ff;
303 spur_delta_phase = spur_delta_phase & 0xfffff;
304
305 ar9003_hw_spur_ofdm(ah,
306 freq_offset,
307 spur_freq_sd,
308 spur_delta_phase,
309 spur_subchannel_sd);
310}
311
312/* Spur mitigation for OFDM */
313static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
314 struct ath9k_channel *chan)
315{
316 int synth_freq;
317 int range = 10;
318 int freq_offset = 0;
319 int mode;
320 u8* spurChansPtr;
321 unsigned int i;
322 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
323
324 if (IS_CHAN_5GHZ(chan)) {
325 spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
326 mode = 0;
327 }
328 else {
329 spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
330 mode = 1;
331 }
332
333 if (spurChansPtr[0] == 0)
334 return; /* No spur in the mode */
335
336 if (IS_CHAN_HT40(chan)) {
337 range = 19;
338 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
339 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
340 synth_freq = chan->channel - 10;
341 else
342 synth_freq = chan->channel + 10;
343 } else {
344 range = 10;
345 synth_freq = chan->channel;
346 }
347
348 ar9003_hw_spur_ofdm_clear(ah);
349
350 for (i = 0; spurChansPtr[i] && i < 5; i++) {
351 freq_offset = FBIN2FREQ(spurChansPtr[i], mode) - synth_freq;
352 if (abs(freq_offset) < range) {
353 ar9003_hw_spur_ofdm_work(ah, chan, freq_offset);
354 break;
355 }
356 }
357}
358
359static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
360 struct ath9k_channel *chan)
361{
362 ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
363 ar9003_hw_spur_mitigate_ofdm(ah, chan);
364}
365
366static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
367 struct ath9k_channel *chan)
368{
369 u32 pll;
370
371 pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
372
373 if (chan && IS_CHAN_HALF_RATE(chan))
374 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
375 else if (chan && IS_CHAN_QUARTER_RATE(chan))
376 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
377
378 pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
379
380 return pll;
381}
382
383static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
384 struct ath9k_channel *chan)
385{
386 u32 phymode;
387 u32 enableDacFifo = 0;
388
389 enableDacFifo =
390 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
391
392 /* Enable 11n HT, 20 MHz */
393 phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 | AR_PHY_GC_WALSH |
394 AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
395
396 /* Configure baseband for dynamic 20/40 operation */
397 if (IS_CHAN_HT40(chan)) {
398 phymode |= AR_PHY_GC_DYN2040_EN;
399 /* Configure control (primary) channel at +-10MHz */
400 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
401 (chan->chanmode == CHANNEL_G_HT40PLUS))
402 phymode |= AR_PHY_GC_DYN2040_PRI_CH;
403
404 }
405
406 /* make sure we preserve INI settings */
407 phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
408 /* turn off Green Field detection for STA for now */
409 phymode &= ~AR_PHY_GC_GF_DETECT_EN;
410
411 REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
412
413 /* Configure MAC for 20/40 operation */
414 ath9k_hw_set11nmac2040(ah);
415
416 /* global transmit timeout (25 TUs default)*/
417 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
418 /* carrier sense timeout */
419 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
420}
421
422static void ar9003_hw_init_bb(struct ath_hw *ah,
423 struct ath9k_channel *chan)
424{
425 u32 synthDelay;
426
427 /*
428 * Wait for the frequency synth to settle (synth goes on
429 * via AR_PHY_ACTIVE_EN). Read the phy active delay register.
430 * Value is in 100ns increments.
431 */
432 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
433 if (IS_CHAN_B(chan))
434 synthDelay = (4 * synthDelay) / 22;
435 else
436 synthDelay /= 10;
437
438 /* Activate the PHY (includes baseband activate + synthesizer on) */
439 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
440
441 /*
442 * There is an issue if the AP starts the calibration before
443 * the base band timeout completes. This could result in the
444 * rx_clear false triggering. As a workaround we add delay an
445 * extra BASE_ACTIVATE_DELAY usecs to ensure this condition
446 * does not happen.
447 */
448 udelay(synthDelay + BASE_ACTIVATE_DELAY);
449}
450
451void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
452{
453 switch (rx) {
454 case 0x5:
455 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
456 AR_PHY_SWAP_ALT_CHAIN);
457 case 0x3:
458 case 0x1:
459 case 0x2:
460 case 0x7:
461 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
462 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
463 break;
464 default:
465 break;
466 }
467
468 REG_WRITE(ah, AR_SELFGEN_MASK, tx);
469 if (tx == 0x5) {
470 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
471 AR_PHY_SWAP_ALT_CHAIN);
472 }
473}
474
475/*
476 * Override INI values with chip specific configuration.
477 */
478static void ar9003_hw_override_ini(struct ath_hw *ah)
479{
480 u32 val;
481
482 /*
483 * Set the RX_ABORT and RX_DIS and clear it only after
484 * RXE is set for MAC. This prevents frames with
485 * corrupted descriptor status.
486 */
487 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
488
489 /*
490 * For AR9280 and above, there is a new feature that allows
491 * Multicast search based on both MAC Address and Key ID. By default,
492 * this feature is enabled. But since the driver is not using this
493 * feature, we switch it off; otherwise multicast search based on
494 * MAC addr only will fail.
495 */
496 val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
497 REG_WRITE(ah, AR_PCU_MISC_MODE2,
498 val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE);
499}
500
501static void ar9003_hw_prog_ini(struct ath_hw *ah,
502 struct ar5416IniArray *iniArr,
503 int column)
504{
505 unsigned int i, regWrites = 0;
506
507 /* New INI format: Array may be undefined (pre, core, post arrays) */
508 if (!iniArr->ia_array)
509 return;
510
511 /*
512 * New INI format: Pre, core, and post arrays for a given subsystem
513 * may be modal (> 2 columns) or non-modal (2 columns). Determine if
514 * the array is non-modal and force the column to 1.
515 */
516 if (column >= iniArr->ia_columns)
517 column = 1;
518
519 for (i = 0; i < iniArr->ia_rows; i++) {
520 u32 reg = INI_RA(iniArr, i, 0);
521 u32 val = INI_RA(iniArr, i, column);
522
523 REG_WRITE(ah, reg, val);
524
525 /*
526 * Determine if this is a shift register value, and insert the
527 * configured delay if so.
528 */
529 if (reg >= 0x16000 && reg < 0x17000
530 && ah->config.analog_shiftreg)
531 udelay(100);
532
533 DO_DELAY(regWrites);
534 }
535}
536
537static int ar9003_hw_process_ini(struct ath_hw *ah,
538 struct ath9k_channel *chan)
539{
540 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
541 unsigned int regWrites = 0, i;
542 struct ieee80211_channel *channel = chan->chan;
543 u32 modesIndex, freqIndex;
544
545 switch (chan->chanmode) {
546 case CHANNEL_A:
547 case CHANNEL_A_HT20:
548 modesIndex = 1;
549 freqIndex = 1;
550 break;
551 case CHANNEL_A_HT40PLUS:
552 case CHANNEL_A_HT40MINUS:
553 modesIndex = 2;
554 freqIndex = 1;
555 break;
556 case CHANNEL_G:
557 case CHANNEL_G_HT20:
558 case CHANNEL_B:
559 modesIndex = 4;
560 freqIndex = 2;
561 break;
562 case CHANNEL_G_HT40PLUS:
563 case CHANNEL_G_HT40MINUS:
564 modesIndex = 3;
565 freqIndex = 2;
566 break;
567
568 default:
569 return -EINVAL;
570 }
571
572 for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
573 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
574 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
575 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
576 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
577 }
578
579 REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
580 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
581
582 /*
583 * For 5GHz channels requiring Fast Clock, apply
584 * different modal values.
585 */
586 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
587 REG_WRITE_ARRAY(&ah->iniModesAdditional,
588 modesIndex, regWrites);
589
590 ar9003_hw_override_ini(ah);
591 ar9003_hw_set_channel_regs(ah, chan);
592 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
593
594 /* Set TX power */
595 ah->eep_ops->set_txpower(ah, chan,
596 ath9k_regd_get_ctl(regulatory, chan),
597 channel->max_antenna_gain * 2,
598 channel->max_power * 2,
599 min((u32) MAX_RATE_POWER,
600 (u32) regulatory->power_limit));
601
602 return 0;
603}
604
605static void ar9003_hw_set_rfmode(struct ath_hw *ah,
606 struct ath9k_channel *chan)
607{
608 u32 rfMode = 0;
609
610 if (chan == NULL)
611 return;
612
613 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
614 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
615
616 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
617 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
618
619 REG_WRITE(ah, AR_PHY_MODE, rfMode);
620}
621
622static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
623{
624 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
625}
626
627static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
628 struct ath9k_channel *chan)
629{
630 u32 coef_scaled, ds_coef_exp, ds_coef_man;
631 u32 clockMhzScaled = 0x64000000;
632 struct chan_centers centers;
633
634 /*
635 * half and quarter rate can divide the scaled clock by 2 or 4
636 * scale for selected channel bandwidth
637 */
638 if (IS_CHAN_HALF_RATE(chan))
639 clockMhzScaled = clockMhzScaled >> 1;
640 else if (IS_CHAN_QUARTER_RATE(chan))
641 clockMhzScaled = clockMhzScaled >> 2;
642
643 /*
644 * ALGO -> coef = 1e8/fcarrier*fclock/40;
645 * scaled coef to provide precision for this floating calculation
646 */
647 ath9k_hw_get_channel_centers(ah, chan, &centers);
648 coef_scaled = clockMhzScaled / centers.synth_center;
649
650 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
651 &ds_coef_exp);
652
653 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
654 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
655 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
656 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
657
658 /*
659 * For Short GI,
660 * scaled coeff is 9/10 that of normal coeff
661 */
662 coef_scaled = (9 * coef_scaled) / 10;
663
664 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
665 &ds_coef_exp);
666
667 /* for short gi */
668 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
669 AR_PHY_SGI_DSC_MAN, ds_coef_man);
670 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
671 AR_PHY_SGI_DSC_EXP, ds_coef_exp);
672}
673
674static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
675{
676 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
677 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
678 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
679}
680
681/*
682 * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
683 * Read the phy active delay register. Value is in 100ns increments.
684 */
685static void ar9003_hw_rfbus_done(struct ath_hw *ah)
686{
687 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
688 if (IS_CHAN_B(ah->curchan))
689 synthDelay = (4 * synthDelay) / 22;
690 else
691 synthDelay /= 10;
692
693 udelay(synthDelay + BASE_ACTIVATE_DELAY);
694
695 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
696}
697
698/*
699 * Set the interrupt and GPIO values so the ISR can disable RF
700 * on a switch signal. Assumes GPIO port and interrupt polarity
701 * are set prior to call.
702 */
703static void ar9003_hw_enable_rfkill(struct ath_hw *ah)
704{
705 /* Connect rfsilent_bb_l to baseband */
706 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
707 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
708 /* Set input mux for rfsilent_bb_l to GPIO #0 */
709 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
710 AR_GPIO_INPUT_MUX2_RFSILENT);
711
712 /*
713 * Configure the desired GPIO port for input and
714 * enable baseband rf silence.
715 */
716 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
717 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
718}
719
720static void ar9003_hw_set_diversity(struct ath_hw *ah, bool value)
721{
722 u32 v = REG_READ(ah, AR_PHY_CCK_DETECT);
723 if (value)
724 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
725 else
726 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
727 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
728}
729
730static bool ar9003_hw_ani_control(struct ath_hw *ah,
731 enum ath9k_ani_cmd cmd, int param)
732{
733 struct ar5416AniState *aniState = ah->curani;
734 struct ath_common *common = ath9k_hw_common(ah);
735
736 switch (cmd & ah->ani_function) {
737 case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
738 u32 level = param;
739
740 if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
741 ath_print(common, ATH_DBG_ANI,
742 "level out of range (%u > %u)\n",
743 level,
744 (unsigned)ARRAY_SIZE(ah->totalSizeDesired));
745 return false;
746 }
747
748 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
749 AR_PHY_DESIRED_SZ_TOT_DES,
750 ah->totalSizeDesired[level]);
751 REG_RMW_FIELD(ah, AR_PHY_AGC,
752 AR_PHY_AGC_COARSE_LOW,
753 ah->coarse_low[level]);
754 REG_RMW_FIELD(ah, AR_PHY_AGC,
755 AR_PHY_AGC_COARSE_HIGH,
756 ah->coarse_high[level]);
757 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
758 AR_PHY_FIND_SIG_FIRPWR, ah->firpwr[level]);
759
760 if (level > aniState->noiseImmunityLevel)
761 ah->stats.ast_ani_niup++;
762 else if (level < aniState->noiseImmunityLevel)
763 ah->stats.ast_ani_nidown++;
764 aniState->noiseImmunityLevel = level;
765 break;
766 }
767 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
768 const int m1ThreshLow[] = { 127, 50 };
769 const int m2ThreshLow[] = { 127, 40 };
770 const int m1Thresh[] = { 127, 0x4d };
771 const int m2Thresh[] = { 127, 0x40 };
772 const int m2CountThr[] = { 31, 16 };
773 const int m2CountThrLow[] = { 63, 48 };
774 u32 on = param ? 1 : 0;
775
776 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
777 AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
778 m1ThreshLow[on]);
779 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
780 AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
781 m2ThreshLow[on]);
782 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
783 AR_PHY_SFCORR_M1_THRESH, m1Thresh[on]);
784 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
785 AR_PHY_SFCORR_M2_THRESH, m2Thresh[on]);
786 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
787 AR_PHY_SFCORR_M2COUNT_THR, m2CountThr[on]);
788 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
789 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
790 m2CountThrLow[on]);
791
792 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
793 AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLow[on]);
794 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
795 AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLow[on]);
796 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
797 AR_PHY_SFCORR_EXT_M1_THRESH, m1Thresh[on]);
798 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
799 AR_PHY_SFCORR_EXT_M2_THRESH, m2Thresh[on]);
800
801 if (on)
802 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
803 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
804 else
805 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
806 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
807
808 if (!on != aniState->ofdmWeakSigDetectOff) {
809 if (on)
810 ah->stats.ast_ani_ofdmon++;
811 else
812 ah->stats.ast_ani_ofdmoff++;
813 aniState->ofdmWeakSigDetectOff = !on;
814 }
815 break;
816 }
817 case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
818 const int weakSigThrCck[] = { 8, 6 };
819 u32 high = param ? 1 : 0;
820
821 REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
822 AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
823 weakSigThrCck[high]);
824 if (high != aniState->cckWeakSigThreshold) {
825 if (high)
826 ah->stats.ast_ani_cckhigh++;
827 else
828 ah->stats.ast_ani_ccklow++;
829 aniState->cckWeakSigThreshold = high;
830 }
831 break;
832 }
833 case ATH9K_ANI_FIRSTEP_LEVEL:{
834 const int firstep[] = { 0, 4, 8 };
835 u32 level = param;
836
837 if (level >= ARRAY_SIZE(firstep)) {
838 ath_print(common, ATH_DBG_ANI,
839 "level out of range (%u > %u)\n",
840 level,
841 (unsigned) ARRAY_SIZE(firstep));
842 return false;
843 }
844 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
845 AR_PHY_FIND_SIG_FIRSTEP,
846 firstep[level]);
847 if (level > aniState->firstepLevel)
848 ah->stats.ast_ani_stepup++;
849 else if (level < aniState->firstepLevel)
850 ah->stats.ast_ani_stepdown++;
851 aniState->firstepLevel = level;
852 break;
853 }
854 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
855 const int cycpwrThr1[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
856 u32 level = param;
857
858 if (level >= ARRAY_SIZE(cycpwrThr1)) {
859 ath_print(common, ATH_DBG_ANI,
860 "level out of range (%u > %u)\n",
861 level,
862 (unsigned) ARRAY_SIZE(cycpwrThr1));
863 return false;
864 }
865 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
866 AR_PHY_TIMING5_CYCPWR_THR1,
867 cycpwrThr1[level]);
868 if (level > aniState->spurImmunityLevel)
869 ah->stats.ast_ani_spurup++;
870 else if (level < aniState->spurImmunityLevel)
871 ah->stats.ast_ani_spurdown++;
872 aniState->spurImmunityLevel = level;
873 break;
874 }
875 case ATH9K_ANI_PRESENT:
876 break;
877 default:
878 ath_print(common, ATH_DBG_ANI,
879 "invalid cmd %u\n", cmd);
880 return false;
881 }
882
883 ath_print(common, ATH_DBG_ANI, "ANI parameters:\n");
884 ath_print(common, ATH_DBG_ANI,
885 "noiseImmunityLevel=%d, spurImmunityLevel=%d, "
886 "ofdmWeakSigDetectOff=%d\n",
887 aniState->noiseImmunityLevel,
888 aniState->spurImmunityLevel,
889 !aniState->ofdmWeakSigDetectOff);
890 ath_print(common, ATH_DBG_ANI,
891 "cckWeakSigThreshold=%d, "
892 "firstepLevel=%d, listenTime=%d\n",
893 aniState->cckWeakSigThreshold,
894 aniState->firstepLevel,
895 aniState->listenTime);
896 ath_print(common, ATH_DBG_ANI,
897 "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
898 aniState->cycleCount,
899 aniState->ofdmPhyErrCount,
900 aniState->cckPhyErrCount);
901
902 return true;
903}
904
905static void ar9003_hw_nf_sanitize_2g(struct ath_hw *ah, s16 *nf)
906{
907 struct ath_common *common = ath9k_hw_common(ah);
908
909 if (*nf > ah->nf_2g_max) {
910 ath_print(common, ATH_DBG_CALIBRATE,
911 "2 GHz NF (%d) > MAX (%d), "
912 "correcting to MAX",
913 *nf, ah->nf_2g_max);
914 *nf = ah->nf_2g_max;
915 } else if (*nf < ah->nf_2g_min) {
916 ath_print(common, ATH_DBG_CALIBRATE,
917 "2 GHz NF (%d) < MIN (%d), "
918 "correcting to MIN",
919 *nf, ah->nf_2g_min);
920 *nf = ah->nf_2g_min;
921 }
922}
923
924static void ar9003_hw_nf_sanitize_5g(struct ath_hw *ah, s16 *nf)
925{
926 struct ath_common *common = ath9k_hw_common(ah);
927
928 if (*nf > ah->nf_5g_max) {
929 ath_print(common, ATH_DBG_CALIBRATE,
930 "5 GHz NF (%d) > MAX (%d), "
931 "correcting to MAX",
932 *nf, ah->nf_5g_max);
933 *nf = ah->nf_5g_max;
934 } else if (*nf < ah->nf_5g_min) {
935 ath_print(common, ATH_DBG_CALIBRATE,
936 "5 GHz NF (%d) < MIN (%d), "
937 "correcting to MIN",
938 *nf, ah->nf_5g_min);
939 *nf = ah->nf_5g_min;
940 }
941}
942
943static void ar9003_hw_nf_sanitize(struct ath_hw *ah, s16 *nf)
944{
945 if (IS_CHAN_2GHZ(ah->curchan))
946 ar9003_hw_nf_sanitize_2g(ah, nf);
947 else
948 ar9003_hw_nf_sanitize_5g(ah, nf);
949}
950
951static void ar9003_hw_do_getnf(struct ath_hw *ah,
952 int16_t nfarray[NUM_NF_READINGS])
953{
954 struct ath_common *common = ath9k_hw_common(ah);
955 int16_t nf;
956
957 nf = MS(REG_READ(ah, AR_PHY_CCA_0), AR_PHY_MINCCA_PWR);
958 if (nf & 0x100)
959 nf = 0 - ((nf ^ 0x1ff) + 1);
960 ar9003_hw_nf_sanitize(ah, &nf);
961 ath_print(common, ATH_DBG_CALIBRATE,
962 "NF calibrated [ctl] [chain 0] is %d\n", nf);
963 nfarray[0] = nf;
964
965 nf = MS(REG_READ(ah, AR_PHY_CCA_1), AR_PHY_CH1_MINCCA_PWR);
966 if (nf & 0x100)
967 nf = 0 - ((nf ^ 0x1ff) + 1);
968 ar9003_hw_nf_sanitize(ah, &nf);
969 ath_print(common, ATH_DBG_CALIBRATE,
970 "NF calibrated [ctl] [chain 1] is %d\n", nf);
971 nfarray[1] = nf;
972
973 nf = MS(REG_READ(ah, AR_PHY_CCA_2), AR_PHY_CH2_MINCCA_PWR);
974 if (nf & 0x100)
975 nf = 0 - ((nf ^ 0x1ff) + 1);
976 ar9003_hw_nf_sanitize(ah, &nf);
977 ath_print(common, ATH_DBG_CALIBRATE,
978 "NF calibrated [ctl] [chain 2] is %d\n", nf);
979 nfarray[2] = nf;
980
981 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
982 if (nf & 0x100)
983 nf = 0 - ((nf ^ 0x1ff) + 1);
984 ar9003_hw_nf_sanitize(ah, &nf);
985 ath_print(common, ATH_DBG_CALIBRATE,
986 "NF calibrated [ext] [chain 0] is %d\n", nf);
987 nfarray[3] = nf;
988
989 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA_1), AR_PHY_CH1_EXT_MINCCA_PWR);
990 if (nf & 0x100)
991 nf = 0 - ((nf ^ 0x1ff) + 1);
992 ar9003_hw_nf_sanitize(ah, &nf);
993 ath_print(common, ATH_DBG_CALIBRATE,
994 "NF calibrated [ext] [chain 1] is %d\n", nf);
995 nfarray[4] = nf;
996
997 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA_2), AR_PHY_CH2_EXT_MINCCA_PWR);
998 if (nf & 0x100)
999 nf = 0 - ((nf ^ 0x1ff) + 1);
1000 ar9003_hw_nf_sanitize(ah, &nf);
1001 ath_print(common, ATH_DBG_CALIBRATE,
1002 "NF calibrated [ext] [chain 2] is %d\n", nf);
1003 nfarray[5] = nf;
1004}
1005
1006void ar9003_hw_set_nf_limits(struct ath_hw *ah)
1007{
1008 ah->nf_2g_max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
1009 ah->nf_2g_min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
1010 ah->nf_5g_max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
1011 ah->nf_5g_min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
1012}
1013
1014/*
1015 * Find out which of the RX chains are enabled
1016 */
1017static u32 ar9003_hw_get_rx_chainmask(struct ath_hw *ah)
1018{
1019 u32 chain = REG_READ(ah, AR_PHY_RX_CHAINMASK);
1020 /*
1021 * The bits [2:0] indicate the rx chain mask and are to be
1022 * interpreted as follows:
1023 * 00x => Only chain 0 is enabled
1024 * 01x => Chain 1 and 0 enabled
1025 * 1xx => Chain 2,1 and 0 enabled
1026 */
1027 return chain & 0x7;
1028}
1029
1030static void ar9003_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
1031{
1032 struct ath9k_nfcal_hist *h;
1033 unsigned i, j;
1034 int32_t val;
1035 const u32 ar9300_cca_regs[6] = {
1036 AR_PHY_CCA_0,
1037 AR_PHY_CCA_1,
1038 AR_PHY_CCA_2,
1039 AR_PHY_EXT_CCA,
1040 AR_PHY_EXT_CCA_1,
1041 AR_PHY_EXT_CCA_2,
1042 };
1043 u8 chainmask, rx_chain_status;
1044 struct ath_common *common = ath9k_hw_common(ah);
1045
1046 rx_chain_status = ar9003_hw_get_rx_chainmask(ah);
1047
1048 chainmask = 0x3F;
1049 h = ah->nfCalHist;
1050
1051 for (i = 0; i < NUM_NF_READINGS; i++) {
1052 if (chainmask & (1 << i)) {
1053 val = REG_READ(ah, ar9300_cca_regs[i]);
1054 val &= 0xFFFFFE00;
1055 val |= (((u32) (h[i].privNF) << 1) & 0x1ff);
1056 REG_WRITE(ah, ar9300_cca_regs[i], val);
1057 }
1058 }
1059
1060 /*
1061 * Load software filtered NF value into baseband internal minCCApwr
1062 * variable.
1063 */
1064 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
1065 AR_PHY_AGC_CONTROL_ENABLE_NF);
1066 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
1067 AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
1068 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
1069
1070 /*
1071 * Wait for load to complete, should be fast, a few 10s of us.
1072 * The max delay was changed from an original 250us to 10000us
1073 * since 250us often results in NF load timeout and causes deaf
1074 * condition during stress testing 12/12/2009
1075 */
1076 for (j = 0; j < 1000; j++) {
1077 if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
1078 AR_PHY_AGC_CONTROL_NF) == 0)
1079 break;
1080 udelay(10);
1081 }
1082
1083 /*
1084 * We timed out waiting for the noisefloor to load, probably due to an
1085 * in-progress rx. Simply return here and allow the load plenty of time
1086 * to complete before the next calibration interval. We need to avoid
1087 * trying to load -50 (which happens below) while the previous load is
1088 * still in progress as this can cause rx deafness. Instead by returning
1089 * here, the baseband nf cal will just be capped by our present
1090 * noisefloor until the next calibration timer.
1091 */
1092 if (j == 1000) {
1093 ath_print(common, ATH_DBG_ANY, "Timeout while waiting for nf "
1094 "to load: AR_PHY_AGC_CONTROL=0x%x\n",
1095 REG_READ(ah, AR_PHY_AGC_CONTROL));
1096 return;
1097 }
1098
1099 /*
1100 * Restore maxCCAPower register parameter again so that we're not capped
1101 * by the median we just loaded. This will be initial (and max) value
1102 * of next noise floor calibration the baseband does.
1103 */
1104 for (i = 0; i < NUM_NF_READINGS; i++) {
1105 if (chainmask & (1 << i)) {
1106 val = REG_READ(ah, ar9300_cca_regs[i]);
1107 val &= 0xFFFFFE00;
1108 val |= (((u32) (-50) << 1) & 0x1ff);
1109 REG_WRITE(ah, ar9300_cca_regs[i], val);
1110 }
1111 }
1112}
1113
1114void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1115{
1116 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1117
1118 priv_ops->rf_set_freq = ar9003_hw_set_channel;
1119 priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
1120 priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
1121 priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
1122 priv_ops->init_bb = ar9003_hw_init_bb;
1123 priv_ops->process_ini = ar9003_hw_process_ini;
1124 priv_ops->set_rfmode = ar9003_hw_set_rfmode;
1125 priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
1126 priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
1127 priv_ops->rfbus_req = ar9003_hw_rfbus_req;
1128 priv_ops->rfbus_done = ar9003_hw_rfbus_done;
1129 priv_ops->enable_rfkill = ar9003_hw_enable_rfkill;
1130 priv_ops->set_diversity = ar9003_hw_set_diversity;
1131 priv_ops->ani_control = ar9003_hw_ani_control;
1132 priv_ops->do_getnf = ar9003_hw_do_getnf;
1133 priv_ops->loadnf = ar9003_hw_loadnf;
1134}
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.h b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
new file mode 100644
index 000000000000..f08cc8bda005
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
@@ -0,0 +1,847 @@
1/*
2 * Copyright (c) 2002-2010 Atheros Communications, Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef AR9003_PHY_H
18#define AR9003_PHY_H
19
20/*
21 * Channel Register Map
22 */
23#define AR_CHAN_BASE 0x9800
24
25#define AR_PHY_TIMING1 (AR_CHAN_BASE + 0x0)
26#define AR_PHY_TIMING2 (AR_CHAN_BASE + 0x4)
27#define AR_PHY_TIMING3 (AR_CHAN_BASE + 0x8)
28#define AR_PHY_TIMING4 (AR_CHAN_BASE + 0xc)
29#define AR_PHY_TIMING5 (AR_CHAN_BASE + 0x10)
30#define AR_PHY_TIMING6 (AR_CHAN_BASE + 0x14)
31#define AR_PHY_TIMING11 (AR_CHAN_BASE + 0x18)
32#define AR_PHY_SPUR_REG (AR_CHAN_BASE + 0x1c)
33#define AR_PHY_RX_IQCAL_CORR_B0 (AR_CHAN_BASE + 0xdc)
34#define AR_PHY_TX_IQCAL_CONTROL_3 (AR_CHAN_BASE + 0xb0)
35
36#define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000
37#define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20
38
39#define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF
40#define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
41
42#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC 0x40000000
43#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC_S 30
44
45#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR 0x80000000
46#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR_S 31
47
48#define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT 0x4000000
49#define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT_S 26
50
51#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 /* bins move with freq offset */
52#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM_S 17
53#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x000000FF
54#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0
55#define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI 0x00000100
56#define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI_S 8
57#define AR_PHY_SPUR_REG_MASK_RATE_CNTL 0x03FC0000
58#define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18
59
60#define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN 0x20000000
61#define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN_S 29
62
63#define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN 0x80000000
64#define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN_S 31
65
66#define AR_PHY_FIND_SIG_LOW (AR_CHAN_BASE + 0x20)
67
68#define AR_PHY_SFCORR (AR_CHAN_BASE + 0x24)
69#define AR_PHY_SFCORR_LOW (AR_CHAN_BASE + 0x28)
70#define AR_PHY_SFCORR_EXT (AR_CHAN_BASE + 0x2c)
71
72#define AR_PHY_EXT_CCA (AR_CHAN_BASE + 0x30)
73#define AR_PHY_RADAR_0 (AR_CHAN_BASE + 0x34)
74#define AR_PHY_RADAR_1 (AR_CHAN_BASE + 0x38)
75#define AR_PHY_RADAR_EXT (AR_CHAN_BASE + 0x3c)
76#define AR_PHY_MULTICHAIN_CTRL (AR_CHAN_BASE + 0x80)
77#define AR_PHY_PERCHAIN_CSD (AR_CHAN_BASE + 0x84)
78
79#define AR_PHY_TX_PHASE_RAMP_0 (AR_CHAN_BASE + 0xd0)
80#define AR_PHY_ADC_GAIN_DC_CORR_0 (AR_CHAN_BASE + 0xd4)
81#define AR_PHY_IQ_ADC_MEAS_0_B0 (AR_CHAN_BASE + 0xc0)
82#define AR_PHY_IQ_ADC_MEAS_1_B0 (AR_CHAN_BASE + 0xc4)
83#define AR_PHY_IQ_ADC_MEAS_2_B0 (AR_CHAN_BASE + 0xc8)
84#define AR_PHY_IQ_ADC_MEAS_3_B0 (AR_CHAN_BASE + 0xcc)
85
86/* The following registers changed position from AR9300 1.0 to AR9300 2.0 */
87#define AR_PHY_TX_PHASE_RAMP_0_9300_10 (AR_CHAN_BASE + 0xd0 - 0x10)
88#define AR_PHY_ADC_GAIN_DC_CORR_0_9300_10 (AR_CHAN_BASE + 0xd4 - 0x10)
89#define AR_PHY_IQ_ADC_MEAS_0_B0_9300_10 (AR_CHAN_BASE + 0xc0 + 0x8)
90#define AR_PHY_IQ_ADC_MEAS_1_B0_9300_10 (AR_CHAN_BASE + 0xc4 + 0x8)
91#define AR_PHY_IQ_ADC_MEAS_2_B0_9300_10 (AR_CHAN_BASE + 0xc8 + 0x8)
92#define AR_PHY_IQ_ADC_MEAS_3_B0_9300_10 (AR_CHAN_BASE + 0xcc + 0x8)
93
94#define AR_PHY_TX_CRC (AR_CHAN_BASE + 0xa0)
95#define AR_PHY_TST_DAC_CONST (AR_CHAN_BASE + 0xa4)
96#define AR_PHY_SPUR_REPORT_0 (AR_CHAN_BASE + 0xa8)
97#define AR_PHY_CHAN_INFO_TAB_0 (AR_CHAN_BASE + 0x300)
98
99/*
100 * Channel Field Definitions
101 */
102#define AR_PHY_TIMING2_USE_FORCE_PPM 0x00001000
103#define AR_PHY_TIMING2_FORCE_PPM_VAL 0x00000fff
104#define AR_PHY_TIMING3_DSC_MAN 0xFFFE0000
105#define AR_PHY_TIMING3_DSC_MAN_S 17
106#define AR_PHY_TIMING3_DSC_EXP 0x0001E000
107#define AR_PHY_TIMING3_DSC_EXP_S 13
108#define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX 0xF000
109#define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX_S 12
110#define AR_PHY_TIMING4_DO_CAL 0x10000
111
112#define AR_PHY_TIMING4_ENABLE_PILOT_MASK 0x10000000
113#define AR_PHY_TIMING4_ENABLE_PILOT_MASK_S 28
114#define AR_PHY_TIMING4_ENABLE_CHAN_MASK 0x20000000
115#define AR_PHY_TIMING4_ENABLE_CHAN_MASK_S 29
116
117#define AR_PHY_TIMING4_ENABLE_SPUR_FILTER 0x40000000
118#define AR_PHY_TIMING4_ENABLE_SPUR_FILTER_S 30
119#define AR_PHY_TIMING4_ENABLE_SPUR_RSSI 0x80000000
120#define AR_PHY_TIMING4_ENABLE_SPUR_RSSI_S 31
121
122#define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000
123#define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000
124#define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001
125#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003F00
126#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8
127#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001FC000
128#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14
129#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0FE00000
130#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21
131#define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F
132#define AR_PHY_SFCORR_M2COUNT_THR_S 0
133#define AR_PHY_SFCORR_M1_THRESH 0x00FE0000
134#define AR_PHY_SFCORR_M1_THRESH_S 17
135#define AR_PHY_SFCORR_M2_THRESH 0x7F000000
136#define AR_PHY_SFCORR_M2_THRESH_S 24
137#define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F
138#define AR_PHY_SFCORR_EXT_M1_THRESH_S 0
139#define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80
140#define AR_PHY_SFCORR_EXT_M2_THRESH_S 7
141#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000
142#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14
143#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000
144#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21
145#define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD 0x10000000
146#define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD_S 28
147#define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28
148#define AR_PHY_EXT_CCA_THRESH62 0x007F0000
149#define AR_PHY_EXT_CCA_THRESH62_S 16
150#define AR_PHY_EXT_MINCCA_PWR 0x01FF0000
151#define AR_PHY_EXT_MINCCA_PWR_S 16
152#define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE
153#define AR_PHY_TIMING5_CYCPWR_THR1_S 1
154#define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE 0x00000001
155#define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE_S 0
156#define AR_PHY_TIMING5_CYCPWR_THR1A 0x007F0000
157#define AR_PHY_TIMING5_CYCPWR_THR1A_S 16
158#define AR_PHY_TIMING5_RSSI_THR1A (0x7F << 16)
159#define AR_PHY_TIMING5_RSSI_THR1A_S 16
160#define AR_PHY_TIMING5_RSSI_THR1A_ENA (0x1 << 15)
161#define AR_PHY_RADAR_0_ENA 0x00000001
162#define AR_PHY_RADAR_0_FFT_ENA 0x80000000
163#define AR_PHY_RADAR_0_INBAND 0x0000003e
164#define AR_PHY_RADAR_0_INBAND_S 1
165#define AR_PHY_RADAR_0_PRSSI 0x00000FC0
166#define AR_PHY_RADAR_0_PRSSI_S 6
167#define AR_PHY_RADAR_0_HEIGHT 0x0003F000
168#define AR_PHY_RADAR_0_HEIGHT_S 12
169#define AR_PHY_RADAR_0_RRSSI 0x00FC0000
170#define AR_PHY_RADAR_0_RRSSI_S 18
171#define AR_PHY_RADAR_0_FIRPWR 0x7F000000
172#define AR_PHY_RADAR_0_FIRPWR_S 24
173#define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000
174#define AR_PHY_RADAR_1_USE_FIR128 0x00400000
175#define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000
176#define AR_PHY_RADAR_1_RELPWR_THRESH_S 16
177#define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000
178#define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000
179#define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000
180#define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00
181#define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8
182#define AR_PHY_RADAR_1_MAXLEN 0x000000FF
183#define AR_PHY_RADAR_1_MAXLEN_S 0
184#define AR_PHY_RADAR_EXT_ENA 0x00004000
185#define AR_PHY_RADAR_DC_PWR_THRESH 0x007f8000
186#define AR_PHY_RADAR_DC_PWR_THRESH_S 15
187#define AR_PHY_RADAR_LB_DC_CAP 0x7f800000
188#define AR_PHY_RADAR_LB_DC_CAP_S 23
189#define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW (0x3f << 6)
190#define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW_S 6
191#define AR_PHY_FIND_SIG_LOW_FIRPWR (0x7f << 12)
192#define AR_PHY_FIND_SIG_LOW_FIRPWR_S 12
193#define AR_PHY_FIND_SIG_LOW_FIRPWR_SIGN_BIT 19
194#define AR_PHY_FIND_SIG_LOW_RELSTEP 0x1f
195#define AR_PHY_FIND_SIG_LOW_RELSTEP_S 0
196#define AR_PHY_FIND_SIG_LOW_RELSTEP_SIGN_BIT 5
197#define AR_PHY_CHAN_INFO_TAB_S2_READ 0x00000008
198#define AR_PHY_CHAN_INFO_TAB_S2_READ_S 3
199#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF 0x0000007F
200#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF_S 0
201#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF 0x00003F80
202#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF_S 7
203#define AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE 0x00004000
204#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF 0x003f8000
205#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF_S 15
206#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF 0x1fc00000
207#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF_S 22
208
209/*
210 * MRC Register Map
211 */
212#define AR_MRC_BASE 0x9c00
213
214#define AR_PHY_TIMING_3A (AR_MRC_BASE + 0x0)
215#define AR_PHY_LDPC_CNTL1 (AR_MRC_BASE + 0x4)
216#define AR_PHY_LDPC_CNTL2 (AR_MRC_BASE + 0x8)
217#define AR_PHY_PILOT_SPUR_MASK (AR_MRC_BASE + 0xc)
218#define AR_PHY_CHAN_SPUR_MASK (AR_MRC_BASE + 0x10)
219#define AR_PHY_SGI_DELTA (AR_MRC_BASE + 0x14)
220#define AR_PHY_ML_CNTL_1 (AR_MRC_BASE + 0x18)
221#define AR_PHY_ML_CNTL_2 (AR_MRC_BASE + 0x1c)
222#define AR_PHY_TST_ADC (AR_MRC_BASE + 0x20)
223
224#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A 0x00000FE0
225#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_S 5
226#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A 0x1F
227#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A_S 0
228
229#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A 0x00000FE0
230#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_S 5
231#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A 0x1F
232#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A_S 0
233
234/*
235 * MRC Feild Definitions
236 */
237#define AR_PHY_SGI_DSC_MAN 0x0007FFF0
238#define AR_PHY_SGI_DSC_MAN_S 4
239#define AR_PHY_SGI_DSC_EXP 0x0000000F
240#define AR_PHY_SGI_DSC_EXP_S 0
241/*
242 * BBB Register Map
243 */
244#define AR_BBB_BASE 0x9d00
245
246/*
247 * AGC Register Map
248 */
249#define AR_AGC_BASE 0x9e00
250
251#define AR_PHY_SETTLING (AR_AGC_BASE + 0x0)
252#define AR_PHY_FORCEMAX_GAINS_0 (AR_AGC_BASE + 0x4)
253#define AR_PHY_GAINS_MINOFF0 (AR_AGC_BASE + 0x8)
254#define AR_PHY_DESIRED_SZ (AR_AGC_BASE + 0xc)
255#define AR_PHY_FIND_SIG (AR_AGC_BASE + 0x10)
256#define AR_PHY_AGC (AR_AGC_BASE + 0x14)
257#define AR_PHY_EXT_ATTEN_CTL_0 (AR_AGC_BASE + 0x18)
258#define AR_PHY_CCA_0 (AR_AGC_BASE + 0x1c)
259#define AR_PHY_EXT_CCA0 (AR_AGC_BASE + 0x20)
260#define AR_PHY_RESTART (AR_AGC_BASE + 0x24)
261#define AR_PHY_MC_GAIN_CTRL (AR_AGC_BASE + 0x28)
262#define AR_PHY_EXTCHN_PWRTHR1 (AR_AGC_BASE + 0x2c)
263#define AR_PHY_EXT_CHN_WIN (AR_AGC_BASE + 0x30)
264#define AR_PHY_20_40_DET_THR (AR_AGC_BASE + 0x34)
265#define AR_PHY_RIFS_SRCH (AR_AGC_BASE + 0x38)
266#define AR_PHY_PEAK_DET_CTRL_1 (AR_AGC_BASE + 0x3c)
267#define AR_PHY_PEAK_DET_CTRL_2 (AR_AGC_BASE + 0x40)
268#define AR_PHY_RX_GAIN_BOUNDS_1 (AR_AGC_BASE + 0x44)
269#define AR_PHY_RX_GAIN_BOUNDS_2 (AR_AGC_BASE + 0x48)
270#define AR_PHY_RSSI_0 (AR_AGC_BASE + 0x180)
271#define AR_PHY_SPUR_CCK_REP0 (AR_AGC_BASE + 0x184)
272#define AR_PHY_CCK_DETECT (AR_AGC_BASE + 0x1c0)
273#define AR_PHY_DAG_CTRLCCK (AR_AGC_BASE + 0x1c4)
274#define AR_PHY_IQCORR_CTRL_CCK (AR_AGC_BASE + 0x1c8)
275
276#define AR_PHY_CCK_SPUR_MIT (AR_AGC_BASE + 0x1cc)
277#define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR 0x000001fe
278#define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR_S 1
279#define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE 0x60000000
280#define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE_S 29
281#define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT 0x00000001
282#define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_S 0
283#define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ 0x1ffffe00
284#define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ_S 9
285
286#define AR_PHY_RX_OCGAIN (AR_AGC_BASE + 0x200)
287
288#define AR_PHY_CCA_NOM_VAL_9300_2GHZ -110
289#define AR_PHY_CCA_NOM_VAL_9300_5GHZ -115
290#define AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ -125
291#define AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ -125
292#define AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ -95
293#define AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ -100
294
295/*
296 * AGC Field Definitions
297 */
298#define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN 0x00FC0000
299#define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN_S 18
300#define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN 0x00003C00
301#define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN_S 10
302#define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN 0x0000001F
303#define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN_S 0
304#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN 0x003E0000
305#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN_S 17
306#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN 0x0001F000
307#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN_S 12
308#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB 0x00000FC0
309#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB_S 6
310#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB 0x0000003F
311#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB_S 0
312#define AR_PHY_RXGAIN_TXRX_ATTEN 0x0003F000
313#define AR_PHY_RXGAIN_TXRX_ATTEN_S 12
314#define AR_PHY_RXGAIN_TXRX_RF_MAX 0x007C0000
315#define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18
316#define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80
317#define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7
318#define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000
319#define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14
320#define AR_PHY_SETTLING_SWITCH 0x00003F80
321#define AR_PHY_SETTLING_SWITCH_S 7
322#define AR_PHY_DESIRED_SZ_ADC 0x000000FF
323#define AR_PHY_DESIRED_SZ_ADC_S 0
324#define AR_PHY_DESIRED_SZ_PGA 0x0000FF00
325#define AR_PHY_DESIRED_SZ_PGA_S 8
326#define AR_PHY_DESIRED_SZ_TOT_DES 0x0FF00000
327#define AR_PHY_DESIRED_SZ_TOT_DES_S 20
328#define AR_PHY_MINCCA_PWR 0x1FF00000
329#define AR_PHY_MINCCA_PWR_S 20
330#define AR_PHY_CCA_THRESH62 0x0007F000
331#define AR_PHY_CCA_THRESH62_S 12
332#define AR9280_PHY_MINCCA_PWR 0x1FF00000
333#define AR9280_PHY_MINCCA_PWR_S 20
334#define AR9280_PHY_CCA_THRESH62 0x000FF000
335#define AR9280_PHY_CCA_THRESH62_S 12
336#define AR_PHY_EXT_CCA0_THRESH62 0x000000FF
337#define AR_PHY_EXT_CCA0_THRESH62_S 0
338#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F
339#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0
340#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0
341#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6
342#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000
343
344#define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200
345#define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR_S 9
346#define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00
347#define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10
348
349#define AR_PHY_RIFS_INIT_DELAY 0x3ff0000
350#define AR_PHY_AGC_COARSE_LOW 0x00007F80
351#define AR_PHY_AGC_COARSE_LOW_S 7
352#define AR_PHY_AGC_COARSE_HIGH 0x003F8000
353#define AR_PHY_AGC_COARSE_HIGH_S 15
354#define AR_PHY_AGC_COARSE_PWR_CONST 0x0000007F
355#define AR_PHY_AGC_COARSE_PWR_CONST_S 0
356#define AR_PHY_FIND_SIG_FIRSTEP 0x0003F000
357#define AR_PHY_FIND_SIG_FIRSTEP_S 12
358#define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000
359#define AR_PHY_FIND_SIG_FIRPWR_S 18
360#define AR_PHY_FIND_SIG_FIRPWR_SIGN_BIT 25
361#define AR_PHY_FIND_SIG_RELPWR (0x1f << 6)
362#define AR_PHY_FIND_SIG_RELPWR_S 6
363#define AR_PHY_FIND_SIG_RELPWR_SIGN_BIT 11
364#define AR_PHY_FIND_SIG_RELSTEP 0x1f
365#define AR_PHY_FIND_SIG_RELSTEP_S 0
366#define AR_PHY_FIND_SIG_RELSTEP_SIGN_BIT 5
367#define AR_PHY_RESTART_DIV_GC 0x001C0000
368#define AR_PHY_RESTART_DIV_GC_S 18
369#define AR_PHY_RESTART_ENA 0x01
370#define AR_PHY_DC_RESTART_DIS 0x40000000
371
372#define AR_PHY_TPC_OLPC_GAIN_DELTA_PAL_ON 0xFF000000
373#define AR_PHY_TPC_OLPC_GAIN_DELTA_PAL_ON_S 24
374#define AR_PHY_TPC_OLPC_GAIN_DELTA 0x00FF0000
375#define AR_PHY_TPC_OLPC_GAIN_DELTA_S 16
376
377#define AR_PHY_TPC_6_ERROR_EST_MODE 0x03000000
378#define AR_PHY_TPC_6_ERROR_EST_MODE_S 24
379
380/*
381 * SM Register Map
382 */
383#define AR_SM_BASE 0xa200
384
385#define AR_PHY_D2_CHIP_ID (AR_SM_BASE + 0x0)
386#define AR_PHY_GEN_CTRL (AR_SM_BASE + 0x4)
387#define AR_PHY_MODE (AR_SM_BASE + 0x8)
388#define AR_PHY_ACTIVE (AR_SM_BASE + 0xc)
389#define AR_PHY_SPUR_MASK_A (AR_SM_BASE + 0x20)
390#define AR_PHY_SPUR_MASK_B (AR_SM_BASE + 0x24)
391#define AR_PHY_SPECTRAL_SCAN (AR_SM_BASE + 0x28)
392#define AR_PHY_RADAR_BW_FILTER (AR_SM_BASE + 0x2c)
393#define AR_PHY_SEARCH_START_DELAY (AR_SM_BASE + 0x30)
394#define AR_PHY_MAX_RX_LEN (AR_SM_BASE + 0x34)
395#define AR_PHY_FRAME_CTL (AR_SM_BASE + 0x38)
396#define AR_PHY_RFBUS_REQ (AR_SM_BASE + 0x3c)
397#define AR_PHY_RFBUS_GRANT (AR_SM_BASE + 0x40)
398#define AR_PHY_RIFS (AR_SM_BASE + 0x44)
399#define AR_PHY_RX_CLR_DELAY (AR_SM_BASE + 0x50)
400#define AR_PHY_RX_DELAY (AR_SM_BASE + 0x54)
401
402#define AR_PHY_XPA_TIMING_CTL (AR_SM_BASE + 0x64)
403#define AR_PHY_MISC_PA_CTL (AR_SM_BASE + 0x80)
404#define AR_PHY_SWITCH_CHAIN_0 (AR_SM_BASE + 0x84)
405#define AR_PHY_SWITCH_COM (AR_SM_BASE + 0x88)
406#define AR_PHY_SWITCH_COM_2 (AR_SM_BASE + 0x8c)
407#define AR_PHY_RX_CHAINMASK (AR_SM_BASE + 0xa0)
408#define AR_PHY_CAL_CHAINMASK (AR_SM_BASE + 0xc0)
409#define AR_PHY_CALMODE (AR_SM_BASE + 0xc8)
410#define AR_PHY_FCAL_1 (AR_SM_BASE + 0xcc)
411#define AR_PHY_FCAL_2_0 (AR_SM_BASE + 0xd0)
412#define AR_PHY_DFT_TONE_CTL_0 (AR_SM_BASE + 0xd4)
413#define AR_PHY_CL_CAL_CTL (AR_SM_BASE + 0xd8)
414#define AR_PHY_CL_TAB_0 (AR_SM_BASE + 0x100)
415#define AR_PHY_SYNTH_CONTROL (AR_SM_BASE + 0x140)
416#define AR_PHY_ADDAC_CLK_SEL (AR_SM_BASE + 0x144)
417#define AR_PHY_PLL_CTL (AR_SM_BASE + 0x148)
418#define AR_PHY_ANALOG_SWAP (AR_SM_BASE + 0x14c)
419#define AR_PHY_ADDAC_PARA_CTL (AR_SM_BASE + 0x150)
420#define AR_PHY_XPA_CFG (AR_SM_BASE + 0x158)
421
422#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A 0x0001FC00
423#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_S 10
424#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A 0x3FF
425#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A_S 0
426
427#define AR_PHY_TEST (AR_SM_BASE + 0x160)
428
429#define AR_PHY_TEST_BBB_OBS_SEL 0x780000
430#define AR_PHY_TEST_BBB_OBS_SEL_S 19
431
432#define AR_PHY_TEST_RX_OBS_SEL_BIT5_S 23
433#define AR_PHY_TEST_RX_OBS_SEL_BIT5 (1 << AR_PHY_TEST_RX_OBS_SEL_BIT5_S)
434
435#define AR_PHY_TEST_CHAIN_SEL 0xC0000000
436#define AR_PHY_TEST_CHAIN_SEL_S 30
437
438#define AR_PHY_TEST_CTL_STATUS (AR_SM_BASE + 0x164)
439#define AR_PHY_TEST_CTL_TSTDAC_EN 0x1
440#define AR_PHY_TEST_CTL_TSTDAC_EN_S 0
441#define AR_PHY_TEST_CTL_TX_OBS_SEL 0x1C
442#define AR_PHY_TEST_CTL_TX_OBS_SEL_S 2
443#define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL 0x60
444#define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL_S 5
445#define AR_PHY_TEST_CTL_TSTADC_EN 0x100
446#define AR_PHY_TEST_CTL_TSTADC_EN_S 8
447#define AR_PHY_TEST_CTL_RX_OBS_SEL 0x3C00
448#define AR_PHY_TEST_CTL_RX_OBS_SEL_S 10
449
450
451#define AR_PHY_TSTDAC (AR_SM_BASE + 0x168)
452
453#define AR_PHY_CHAN_STATUS (AR_SM_BASE + 0x16c)
454#define AR_PHY_CHAN_INFO_MEMORY (AR_SM_BASE + 0x170)
455#define AR_PHY_CHNINFO_NOISEPWR (AR_SM_BASE + 0x174)
456#define AR_PHY_CHNINFO_GAINDIFF (AR_SM_BASE + 0x178)
457#define AR_PHY_CHNINFO_FINETIM (AR_SM_BASE + 0x17c)
458#define AR_PHY_CHAN_INFO_GAIN_0 (AR_SM_BASE + 0x180)
459#define AR_PHY_SCRAMBLER_SEED (AR_SM_BASE + 0x190)
460#define AR_PHY_CCK_TX_CTRL (AR_SM_BASE + 0x194)
461
462#define AR_PHY_HEAVYCLIP_CTL (AR_SM_BASE + 0x1a4)
463#define AR_PHY_HEAVYCLIP_20 (AR_SM_BASE + 0x1a8)
464#define AR_PHY_HEAVYCLIP_40 (AR_SM_BASE + 0x1ac)
465#define AR_PHY_ILLEGAL_TXRATE (AR_SM_BASE + 0x1b0)
466
467#define AR_PHY_PWRTX_MAX (AR_SM_BASE + 0x1f0)
468#define AR_PHY_POWER_TX_SUB (AR_SM_BASE + 0x1f4)
469
470#define AR_PHY_TPC_4_B0 (AR_SM_BASE + 0x204)
471#define AR_PHY_TPC_5_B0 (AR_SM_BASE + 0x208)
472#define AR_PHY_TPC_6_B0 (AR_SM_BASE + 0x20c)
473#define AR_PHY_TPC_11_B0 (AR_SM_BASE + 0x220)
474#define AR_PHY_TPC_18 (AR_SM_BASE + 0x23c)
475#define AR_PHY_TPC_19 (AR_SM_BASE + 0x240)
476
477#define AR_PHY_TX_FORCED_GAIN (AR_SM_BASE + 0x258)
478
479#define AR_PHY_PDADC_TAB_0 (AR_SM_BASE + 0x280)
480
481#define AR_PHY_TX_IQCAL_CONTROL_1 (AR_SM_BASE + 0x448)
482#define AR_PHY_TX_IQCAL_START (AR_SM_BASE + 0x440)
483#define AR_PHY_TX_IQCAL_STATUS_B0 (AR_SM_BASE + 0x48c)
484#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B0 (AR_SM_BASE + 0x450)
485
486#define AR_PHY_PANIC_WD_STATUS (AR_SM_BASE + 0x5c0)
487#define AR_PHY_PANIC_WD_CTL_1 (AR_SM_BASE + 0x5c4)
488#define AR_PHY_PANIC_WD_CTL_2 (AR_SM_BASE + 0x5c8)
489#define AR_PHY_BT_CTL (AR_SM_BASE + 0x5cc)
490#define AR_PHY_ONLY_WARMRESET (AR_SM_BASE + 0x5d0)
491#define AR_PHY_ONLY_CTL (AR_SM_BASE + 0x5d4)
492#define AR_PHY_ECO_CTRL (AR_SM_BASE + 0x5dc)
493#define AR_PHY_BB_THERM_ADC_1 (AR_SM_BASE + 0x248)
494
495#define AR_PHY_65NM_CH0_SYNTH4 0x1608c
496#define AR_PHY_SYNTH4_LONG_SHIFT_SELECT 0x00000002
497#define AR_PHY_SYNTH4_LONG_SHIFT_SELECT_S 1
498#define AR_PHY_65NM_CH0_SYNTH7 0x16098
499#define AR_PHY_65NM_CH0_BIAS1 0x160c0
500#define AR_PHY_65NM_CH0_BIAS2 0x160c4
501#define AR_PHY_65NM_CH0_BIAS4 0x160cc
502#define AR_PHY_65NM_CH0_RXTX4 0x1610c
503#define AR_PHY_65NM_CH0_THERM 0x16290
504
505#define AR_PHY_65NM_CH0_THERM_LOCAL 0x80000000
506#define AR_PHY_65NM_CH0_THERM_LOCAL_S 31
507#define AR_PHY_65NM_CH0_THERM_START 0x20000000
508#define AR_PHY_65NM_CH0_THERM_START_S 29
509#define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT 0x0000ff00
510#define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT_S 8
511
512#define AR_PHY_65NM_CH0_RXTX1 0x16100
513#define AR_PHY_65NM_CH0_RXTX2 0x16104
514#define AR_PHY_65NM_CH1_RXTX1 0x16500
515#define AR_PHY_65NM_CH1_RXTX2 0x16504
516#define AR_PHY_65NM_CH2_RXTX1 0x16900
517#define AR_PHY_65NM_CH2_RXTX2 0x16904
518
519#define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT 0x00380000
520#define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT_S 19
521#define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT 0x00c00000
522#define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT_S 22
523#define AR_PHY_LNAGAIN_LONG_SHIFT 0xe0000000
524#define AR_PHY_LNAGAIN_LONG_SHIFT_S 29
525#define AR_PHY_MXRGAIN_LONG_SHIFT 0x03000000
526#define AR_PHY_MXRGAIN_LONG_SHIFT_S 24
527#define AR_PHY_VGAGAIN_LONG_SHIFT 0x1c000000
528#define AR_PHY_VGAGAIN_LONG_SHIFT_S 26
529#define AR_PHY_SCFIR_GAIN_LONG_SHIFT 0x00000001
530#define AR_PHY_SCFIR_GAIN_LONG_SHIFT_S 0
531#define AR_PHY_MANRXGAIN_LONG_SHIFT 0x00000002
532#define AR_PHY_MANRXGAIN_LONG_SHIFT_S 1
533
534/*
535 * SM Field Definitions
536 */
537#define AR_PHY_CL_CAL_ENABLE 0x00000002
538#define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001
539#define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000
540#define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22
541
542#define AR_PHY_ADDAC_PARACTL_OFF_PWDADC 0x00008000
543
544#define AR_PHY_FCAL20_CAP_STATUS_0 0x01f00000
545#define AR_PHY_FCAL20_CAP_STATUS_0_S 20
546
547#define AR_PHY_RFBUS_REQ_EN 0x00000001 /* request for RF bus */
548#define AR_PHY_RFBUS_GRANT_EN 0x00000001 /* RF bus granted */
549#define AR_PHY_GC_TURBO_MODE 0x00000001 /* set turbo mode bits */
550#define AR_PHY_GC_TURBO_SHORT 0x00000002 /* set short symbols to turbo mode setting */
551#define AR_PHY_GC_DYN2040_EN 0x00000004 /* enable dyn 20/40 mode */
552#define AR_PHY_GC_DYN2040_PRI_ONLY 0x00000008 /* dyn 20/40 - primary only */
553#define AR_PHY_GC_DYN2040_PRI_CH 0x00000010 /* dyn 20/40 - primary ch offset (0=+10MHz, 1=-10MHz)*/
554#define AR_PHY_GC_DYN2040_PRI_CH_S 4
555#define AR_PHY_GC_DYN2040_EXT_CH 0x00000020 /* dyn 20/40 - ext ch spacing (0=20MHz/ 1=25MHz) */
556#define AR_PHY_GC_HT_EN 0x00000040 /* ht enable */
557#define AR_PHY_GC_SHORT_GI_40 0x00000080 /* allow short GI for HT 40 */
558#define AR_PHY_GC_WALSH 0x00000100 /* walsh spatial spreading for 2 chains,2 streams TX */
559#define AR_PHY_GC_SINGLE_HT_LTF1 0x00000200 /* single length (4us) 1st HT long training symbol */
560#define AR_PHY_GC_GF_DETECT_EN 0x00000400 /* enable Green Field detection. Only affects rx, not tx */
561#define AR_PHY_GC_ENABLE_DAC_FIFO 0x00000800 /* fifo between bb and dac */
562#define AR_PHY_RX_DELAY_DELAY 0x00003FFF /* delay from wakeup to rx ena */
563
564#define AR_PHY_CALMODE_IQ 0x00000000
565#define AR_PHY_CALMODE_ADC_GAIN 0x00000001
566#define AR_PHY_CALMODE_ADC_DC_PER 0x00000002
567#define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003
568#define AR_PHY_SWAP_ALT_CHAIN 0x00000040
569#define AR_PHY_MODE_OFDM 0x00000000
570#define AR_PHY_MODE_CCK 0x00000001
571#define AR_PHY_MODE_DYNAMIC 0x00000004
572#define AR_PHY_MODE_DYNAMIC_S 2
573#define AR_PHY_MODE_HALF 0x00000020
574#define AR_PHY_MODE_QUARTER 0x00000040
575#define AR_PHY_MAC_CLK_MODE 0x00000080
576#define AR_PHY_MODE_DYN_CCK_DISABLE 0x00000100
577#define AR_PHY_MODE_SVD_HALF 0x00000200
578#define AR_PHY_ACTIVE_EN 0x00000001
579#define AR_PHY_ACTIVE_DIS 0x00000000
580#define AR_PHY_FORCE_XPA_CFG 0x000000001
581#define AR_PHY_FORCE_XPA_CFG_S 0
582#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF 0xFF000000
583#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF_S 24
584#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF 0x00FF0000
585#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF_S 16
586#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON 0x0000FF00
587#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON_S 8
588#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON 0x000000FF
589#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON_S 0
590#define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000
591#define AR_PHY_TX_END_TO_A2_RX_ON_S 16
592#define AR_PHY_TX_END_DATA_START 0x000000FF
593#define AR_PHY_TX_END_DATA_START_S 0
594#define AR_PHY_TX_END_PA_ON 0x0000FF00
595#define AR_PHY_TX_END_PA_ON_S 8
596#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000F
597#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0
598#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003F0
599#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4
600#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000FC00
601#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10
602#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003F0000
603#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16
604#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0FC00000
605#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22
606#define AR_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000
607#define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14
608#define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000
609#define AR_PHY_TPCRG1_PD_GAIN_1_S 16
610#define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000
611#define AR_PHY_TPCRG1_PD_GAIN_2_S 18
612#define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000
613#define AR_PHY_TPCRG1_PD_GAIN_3_S 20
614#define AR_PHY_TPCGR1_FORCED_DAC_GAIN 0x0000003e
615#define AR_PHY_TPCGR1_FORCED_DAC_GAIN_S 1
616#define AR_PHY_TPCGR1_FORCE_DAC_GAIN 0x00000001
617#define AR_PHY_TXGAIN_FORCE 0x00000001
618#define AR_PHY_TXGAIN_FORCED_PADVGNRA 0x00003c00
619#define AR_PHY_TXGAIN_FORCED_PADVGNRA_S 10
620#define AR_PHY_TXGAIN_FORCED_PADVGNRB 0x0003c000
621#define AR_PHY_TXGAIN_FORCED_PADVGNRB_S 14
622#define AR_PHY_TXGAIN_FORCED_PADVGNRD 0x00c00000
623#define AR_PHY_TXGAIN_FORCED_PADVGNRD_S 22
624#define AR_PHY_TXGAIN_FORCED_TXMXRGAIN 0x000003c0
625#define AR_PHY_TXGAIN_FORCED_TXMXRGAIN_S 6
626#define AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN 0x0000000e
627#define AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN_S 1
628
629#define AR_PHY_POWER_TX_RATE1 0x9934
630#define AR_PHY_POWER_TX_RATE2 0x9938
631#define AR_PHY_POWER_TX_RATE_MAX 0x993c
632#define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040
633#define PHY_AGC_CLR 0x10000000
634#define RFSILENT_BB 0x00002000
635#define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK 0xFFF
636#define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_SIGNED_BIT 0x800
637#define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320
638#define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001
639#define AR_PHY_RX_DELAY_DELAY 0x00003FFF
640#define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010
641#define AR_PHY_SPECTRAL_SCAN_ENABLE 0x00000001
642#define AR_PHY_SPECTRAL_SCAN_ENABLE_S 0
643#define AR_PHY_SPECTRAL_SCAN_ACTIVE 0x00000002
644#define AR_PHY_SPECTRAL_SCAN_ACTIVE_S 1
645#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD 0x000000F0
646#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S 4
647#define AR_PHY_SPECTRAL_SCAN_PERIOD 0x0000FF00
648#define AR_PHY_SPECTRAL_SCAN_PERIOD_S 8
649#define AR_PHY_SPECTRAL_SCAN_COUNT 0x00FF0000
650#define AR_PHY_SPECTRAL_SCAN_COUNT_S 16
651#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x01000000
652#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 24
653#define AR_PHY_CHANNEL_STATUS_RX_CLEAR 0x00000004
654#define AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT 0x01fc0000
655#define AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_S 18
656#define AR_PHY_TX_IQCAL_START_DO_CAL 0x00000001
657#define AR_PHY_TX_IQCAL_START_DO_CAL_S 0
658
659#define AR_PHY_TX_IQCAL_STATUS_FAILED 0x00000001
660#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE 0x00003fff
661#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_S 0
662
663#define AR_PHY_TPC_18_THERM_CAL_VALUE 0xff
664#define AR_PHY_TPC_18_THERM_CAL_VALUE_S 0
665#define AR_PHY_TPC_19_ALPHA_THERM 0xff
666#define AR_PHY_TPC_19_ALPHA_THERM_S 0
667
668#define AR_PHY_65NM_CH0_RXTX4_THERM_ON 0x10000000
669#define AR_PHY_65NM_CH0_RXTX4_THERM_ON_S 28
670
671#define AR_PHY_BB_THERM_ADC_1_INIT_THERM 0x000000ff
672#define AR_PHY_BB_THERM_ADC_1_INIT_THERM_S 0
673
674/*
675 * Channel 1 Register Map
676 */
677#define AR_CHAN1_BASE 0xa800
678
679#define AR_PHY_EXT_CCA_1 (AR_CHAN1_BASE + 0x30)
680#define AR_PHY_TX_PHASE_RAMP_1 (AR_CHAN1_BASE + 0xd0)
681#define AR_PHY_ADC_GAIN_DC_CORR_1 (AR_CHAN1_BASE + 0xd4)
682
683#define AR_PHY_SPUR_REPORT_1 (AR_CHAN1_BASE + 0xa8)
684#define AR_PHY_CHAN_INFO_TAB_1 (AR_CHAN1_BASE + 0x300)
685#define AR_PHY_RX_IQCAL_CORR_B1 (AR_CHAN1_BASE + 0xdc)
686
687/*
688 * Channel 1 Field Definitions
689 */
690#define AR_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000
691#define AR_PHY_CH1_EXT_MINCCA_PWR_S 16
692
693/*
694 * AGC 1 Register Map
695 */
696#define AR_AGC1_BASE 0xae00
697
698#define AR_PHY_FORCEMAX_GAINS_1 (AR_AGC1_BASE + 0x4)
699#define AR_PHY_EXT_ATTEN_CTL_1 (AR_AGC1_BASE + 0x18)
700#define AR_PHY_CCA_1 (AR_AGC1_BASE + 0x1c)
701#define AR_PHY_CCA_CTRL_1 (AR_AGC1_BASE + 0x20)
702#define AR_PHY_RSSI_1 (AR_AGC1_BASE + 0x180)
703#define AR_PHY_SPUR_CCK_REP_1 (AR_AGC1_BASE + 0x184)
704#define AR_PHY_RX_OCGAIN_2 (AR_AGC1_BASE + 0x200)
705
706/*
707 * AGC 1 Field Definitions
708 */
709#define AR_PHY_CH1_MINCCA_PWR 0x1FF00000
710#define AR_PHY_CH1_MINCCA_PWR_S 20
711
712/*
713 * SM 1 Register Map
714 */
715#define AR_SM1_BASE 0xb200
716
717#define AR_PHY_SWITCH_CHAIN_1 (AR_SM1_BASE + 0x84)
718#define AR_PHY_FCAL_2_1 (AR_SM1_BASE + 0xd0)
719#define AR_PHY_DFT_TONE_CTL_1 (AR_SM1_BASE + 0xd4)
720#define AR_PHY_CL_TAB_1 (AR_SM1_BASE + 0x100)
721#define AR_PHY_CHAN_INFO_GAIN_1 (AR_SM1_BASE + 0x180)
722#define AR_PHY_TPC_4_B1 (AR_SM1_BASE + 0x204)
723#define AR_PHY_TPC_5_B1 (AR_SM1_BASE + 0x208)
724#define AR_PHY_TPC_6_B1 (AR_SM1_BASE + 0x20c)
725#define AR_PHY_TPC_11_B1 (AR_SM1_BASE + 0x220)
726#define AR_PHY_PDADC_TAB_1 (AR_SM1_BASE + 0x240)
727#define AR_PHY_TX_IQCAL_STATUS_B1 (AR_SM1_BASE + 0x48c)
728#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B1 (AR_SM1_BASE + 0x450)
729
730/*
731 * Channel 2 Register Map
732 */
733#define AR_CHAN2_BASE 0xb800
734
735#define AR_PHY_EXT_CCA_2 (AR_CHAN2_BASE + 0x30)
736#define AR_PHY_TX_PHASE_RAMP_2 (AR_CHAN2_BASE + 0xd0)
737#define AR_PHY_ADC_GAIN_DC_CORR_2 (AR_CHAN2_BASE + 0xd4)
738
739#define AR_PHY_SPUR_REPORT_2 (AR_CHAN2_BASE + 0xa8)
740#define AR_PHY_CHAN_INFO_TAB_2 (AR_CHAN2_BASE + 0x300)
741#define AR_PHY_RX_IQCAL_CORR_B2 (AR_CHAN2_BASE + 0xdc)
742
743/*
744 * Channel 2 Field Definitions
745 */
746#define AR_PHY_CH2_EXT_MINCCA_PWR 0x01FF0000
747#define AR_PHY_CH2_EXT_MINCCA_PWR_S 16
748/*
749 * AGC 2 Register Map
750 */
751#define AR_AGC2_BASE 0xbe00
752
753#define AR_PHY_FORCEMAX_GAINS_2 (AR_AGC2_BASE + 0x4)
754#define AR_PHY_EXT_ATTEN_CTL_2 (AR_AGC2_BASE + 0x18)
755#define AR_PHY_CCA_2 (AR_AGC2_BASE + 0x1c)
756#define AR_PHY_CCA_CTRL_2 (AR_AGC2_BASE + 0x20)
757#define AR_PHY_RSSI_2 (AR_AGC2_BASE + 0x180)
758
759/*
760 * AGC 2 Field Definitions
761 */
762#define AR_PHY_CH2_MINCCA_PWR 0x1FF00000
763#define AR_PHY_CH2_MINCCA_PWR_S 20
764
765/*
766 * SM 2 Register Map
767 */
768#define AR_SM2_BASE 0xc200
769
770#define AR_PHY_SWITCH_CHAIN_2 (AR_SM2_BASE + 0x84)
771#define AR_PHY_FCAL_2_2 (AR_SM2_BASE + 0xd0)
772#define AR_PHY_DFT_TONE_CTL_2 (AR_SM2_BASE + 0xd4)
773#define AR_PHY_CL_TAB_2 (AR_SM2_BASE + 0x100)
774#define AR_PHY_CHAN_INFO_GAIN_2 (AR_SM2_BASE + 0x180)
775#define AR_PHY_TPC_4_B2 (AR_SM2_BASE + 0x204)
776#define AR_PHY_TPC_5_B2 (AR_SM2_BASE + 0x208)
777#define AR_PHY_TPC_6_B2 (AR_SM2_BASE + 0x20c)
778#define AR_PHY_TPC_11_B2 (AR_SM2_BASE + 0x220)
779#define AR_PHY_PDADC_TAB_2 (AR_SM2_BASE + 0x240)
780#define AR_PHY_TX_IQCAL_STATUS_B2 (AR_SM2_BASE + 0x48c)
781#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B2 (AR_SM2_BASE + 0x450)
782
783#define AR_PHY_TX_IQCAL_STATUS_B2_FAILED 0x00000001
784
785/*
786 * AGC 3 Register Map
787 */
788#define AR_AGC3_BASE 0xce00
789
790#define AR_PHY_RSSI_3 (AR_AGC3_BASE + 0x180)
791
792/*
793 * Misc helper defines
794 */
795#define AR_PHY_CHAIN_OFFSET (AR_CHAN1_BASE - AR_CHAN_BASE)
796
797#define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (AR_PHY_ADC_GAIN_DC_CORR_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
798#define AR_PHY_NEW_ADC_DC_GAIN_CORR_9300_10(_i) (AR_PHY_ADC_GAIN_DC_CORR_0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
799#define AR_PHY_SWITCH_CHAIN(_i) (AR_PHY_SWITCH_CHAIN_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
800#define AR_PHY_EXT_ATTEN_CTL(_i) (AR_PHY_EXT_ATTEN_CTL_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
801
802#define AR_PHY_RXGAIN(_i) (AR_PHY_FORCEMAX_GAINS_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
803#define AR_PHY_TPCRG5(_i) (AR_PHY_TPC_5_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
804#define AR_PHY_PDADC_TAB(_i) (AR_PHY_PDADC_TAB_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
805
806#define AR_PHY_CAL_MEAS_0(_i) (AR_PHY_IQ_ADC_MEAS_0_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
807#define AR_PHY_CAL_MEAS_1(_i) (AR_PHY_IQ_ADC_MEAS_1_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
808#define AR_PHY_CAL_MEAS_2(_i) (AR_PHY_IQ_ADC_MEAS_2_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
809#define AR_PHY_CAL_MEAS_3(_i) (AR_PHY_IQ_ADC_MEAS_3_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
810#define AR_PHY_CAL_MEAS_0_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_0_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
811#define AR_PHY_CAL_MEAS_1_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_1_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
812#define AR_PHY_CAL_MEAS_2_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_2_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
813#define AR_PHY_CAL_MEAS_3_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_3_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
814
815#define AR_PHY_BB_PANIC_NON_IDLE_ENABLE 0x00000001
816#define AR_PHY_BB_PANIC_IDLE_ENABLE 0x00000002
817#define AR_PHY_BB_PANIC_IDLE_MASK 0xFFFF0000
818#define AR_PHY_BB_PANIC_NON_IDLE_MASK 0x0000FFFC
819
820#define AR_PHY_BB_PANIC_RST_ENABLE 0x00000002
821#define AR_PHY_BB_PANIC_IRQ_ENABLE 0x00000004
822#define AR_PHY_BB_PANIC_CNTL2_MASK 0xFFFFFFF9
823
824#define AR_PHY_BB_WD_STATUS 0x00000007
825#define AR_PHY_BB_WD_STATUS_S 0
826#define AR_PHY_BB_WD_DET_HANG 0x00000008
827#define AR_PHY_BB_WD_DET_HANG_S 3
828#define AR_PHY_BB_WD_RADAR_SM 0x000000F0
829#define AR_PHY_BB_WD_RADAR_SM_S 4
830#define AR_PHY_BB_WD_RX_OFDM_SM 0x00000F00
831#define AR_PHY_BB_WD_RX_OFDM_SM_S 8
832#define AR_PHY_BB_WD_RX_CCK_SM 0x0000F000
833#define AR_PHY_BB_WD_RX_CCK_SM_S 12
834#define AR_PHY_BB_WD_TX_OFDM_SM 0x000F0000
835#define AR_PHY_BB_WD_TX_OFDM_SM_S 16
836#define AR_PHY_BB_WD_TX_CCK_SM 0x00F00000
837#define AR_PHY_BB_WD_TX_CCK_SM_S 20
838#define AR_PHY_BB_WD_AGC_SM 0x0F000000
839#define AR_PHY_BB_WD_AGC_SM_S 24
840#define AR_PHY_BB_WD_SRCH_SM 0xF0000000
841#define AR_PHY_BB_WD_SRCH_SM_S 28
842
843#define AR_PHY_BB_WD_STATUS_CLR 0x00000008
844
845void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx);
846
847#endif /* AR9003_PHY_H */
diff --git a/drivers/net/wireless/ath/ath9k/ath9k.h b/drivers/net/wireless/ath/ath9k/ath9k.h
index bdcd257ca7a4..fbb7dec6ddeb 100644
--- a/drivers/net/wireless/ath/ath9k/ath9k.h
+++ b/drivers/net/wireless/ath/ath9k/ath9k.h
@@ -114,8 +114,10 @@ enum buffer_type {
114#define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY) 114#define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY)
115#define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY) 115#define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY)
116 116
117#define ATH_TXSTATUS_RING_SIZE 64
118
117struct ath_descdma { 119struct ath_descdma {
118 struct ath_desc *dd_desc; 120 void *dd_desc;
119 dma_addr_t dd_desc_paddr; 121 dma_addr_t dd_desc_paddr;
120 u32 dd_desc_len; 122 u32 dd_desc_len;
121 struct ath_buf *dd_bufptr; 123 struct ath_buf *dd_bufptr;
@@ -123,7 +125,7 @@ struct ath_descdma {
123 125
124int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, 126int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
125 struct list_head *head, const char *name, 127 struct list_head *head, const char *name,
126 int nbuf, int ndesc); 128 int nbuf, int ndesc, bool is_tx);
127void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd, 129void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
128 struct list_head *head); 130 struct list_head *head);
129 131
@@ -188,6 +190,7 @@ enum ATH_AGGR_STATUS {
188 ATH_AGGR_LIMITED, 190 ATH_AGGR_LIMITED,
189}; 191};
190 192
193#define ATH_TXFIFO_DEPTH 8
191struct ath_txq { 194struct ath_txq {
192 u32 axq_qnum; 195 u32 axq_qnum;
193 u32 *axq_link; 196 u32 *axq_link;
@@ -197,6 +200,10 @@ struct ath_txq {
197 bool stopped; 200 bool stopped;
198 bool axq_tx_inprogress; 201 bool axq_tx_inprogress;
199 struct list_head axq_acq; 202 struct list_head axq_acq;
203 struct list_head txq_fifo[ATH_TXFIFO_DEPTH];
204 struct list_head txq_fifo_pending;
205 u8 txq_headidx;
206 u8 txq_tailidx;
200}; 207};
201 208
202#define AGGR_CLEANUP BIT(1) 209#define AGGR_CLEANUP BIT(1)
@@ -223,6 +230,12 @@ struct ath_tx {
223 struct ath_descdma txdma; 230 struct ath_descdma txdma;
224}; 231};
225 232
233struct ath_rx_edma {
234 struct sk_buff_head rx_fifo;
235 struct sk_buff_head rx_buffers;
236 u32 rx_fifo_hwsize;
237};
238
226struct ath_rx { 239struct ath_rx {
227 u8 defant; 240 u8 defant;
228 u8 rxotherant; 241 u8 rxotherant;
@@ -232,6 +245,8 @@ struct ath_rx {
232 spinlock_t rxbuflock; 245 spinlock_t rxbuflock;
233 struct list_head rxbuf; 246 struct list_head rxbuf;
234 struct ath_descdma rxdma; 247 struct ath_descdma rxdma;
248 struct ath_buf *rx_bufptr;
249 struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX];
235}; 250};
236 251
237int ath_startrecv(struct ath_softc *sc); 252int ath_startrecv(struct ath_softc *sc);
@@ -240,7 +255,7 @@ void ath_flushrecv(struct ath_softc *sc);
240u32 ath_calcrxfilter(struct ath_softc *sc); 255u32 ath_calcrxfilter(struct ath_softc *sc);
241int ath_rx_init(struct ath_softc *sc, int nbufs); 256int ath_rx_init(struct ath_softc *sc, int nbufs);
242void ath_rx_cleanup(struct ath_softc *sc); 257void ath_rx_cleanup(struct ath_softc *sc);
243int ath_rx_tasklet(struct ath_softc *sc, int flush); 258int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp);
244struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype); 259struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
245void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq); 260void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
246int ath_tx_setup(struct ath_softc *sc, int haltype); 261int ath_tx_setup(struct ath_softc *sc, int haltype);
@@ -258,6 +273,7 @@ int ath_txq_update(struct ath_softc *sc, int qnum,
258int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, 273int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
259 struct ath_tx_control *txctl); 274 struct ath_tx_control *txctl);
260void ath_tx_tasklet(struct ath_softc *sc); 275void ath_tx_tasklet(struct ath_softc *sc);
276void ath_tx_edma_tasklet(struct ath_softc *sc);
261void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb); 277void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb);
262bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno); 278bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno);
263void ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, 279void ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
@@ -507,6 +523,8 @@ struct ath_softc {
507 struct ath_beacon_config cur_beacon_conf; 523 struct ath_beacon_config cur_beacon_conf;
508 struct delayed_work tx_complete_work; 524 struct delayed_work tx_complete_work;
509 struct ath_btcoex btcoex; 525 struct ath_btcoex btcoex;
526
527 struct ath_descdma txsdma;
510}; 528};
511 529
512struct ath_wiphy { 530struct ath_wiphy {
diff --git a/drivers/net/wireless/ath/ath9k/beacon.c b/drivers/net/wireless/ath/ath9k/beacon.c
index 22375a754718..c8a4558f79ba 100644
--- a/drivers/net/wireless/ath/ath9k/beacon.c
+++ b/drivers/net/wireless/ath/ath9k/beacon.c
@@ -93,8 +93,6 @@ static void ath_beacon_setup(struct ath_softc *sc, struct ath_vif *avp,
93 antenna = ((sc->beacon.ast_be_xmit / sc->nbcnvifs) & 1 ? 2 : 1); 93 antenna = ((sc->beacon.ast_be_xmit / sc->nbcnvifs) & 1 ? 2 : 1);
94 } 94 }
95 95
96 ds->ds_data = bf->bf_buf_addr;
97
98 sband = &sc->sbands[common->hw->conf.channel->band]; 96 sband = &sc->sbands[common->hw->conf.channel->band];
99 rate = sband->bitrates[rateidx].hw_value; 97 rate = sband->bitrates[rateidx].hw_value;
100 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT) 98 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
@@ -109,7 +107,8 @@ static void ath_beacon_setup(struct ath_softc *sc, struct ath_vif *avp,
109 107
110 /* NB: beacon's BufLen must be a multiple of 4 bytes */ 108 /* NB: beacon's BufLen must be a multiple of 4 bytes */
111 ath9k_hw_filltxdesc(ah, ds, roundup(skb->len, 4), 109 ath9k_hw_filltxdesc(ah, ds, roundup(skb->len, 4),
112 true, true, ds); 110 true, true, ds, bf->bf_buf_addr,
111 sc->beacon.beaconq);
113 112
114 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4); 113 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
115 series[0].Tries = 1; 114 series[0].Tries = 1;
diff --git a/drivers/net/wireless/ath/ath9k/calib.c b/drivers/net/wireless/ath/ath9k/calib.c
index 064f5b51dfcd..6982577043b8 100644
--- a/drivers/net/wireless/ath/ath9k/calib.c
+++ b/drivers/net/wireless/ath/ath9k/calib.c
@@ -15,10 +15,12 @@
15 */ 15 */
16 16
17#include "hw.h" 17#include "hw.h"
18#include "hw-ops.h"
19
20/* Common calibration code */
18 21
19/* We can tune this as we go by monitoring really low values */ 22/* We can tune this as we go by monitoring really low values */
20#define ATH9K_NF_TOO_LOW -60 23#define ATH9K_NF_TOO_LOW -60
21#define AR9285_CLCAL_REDO_THRESH 1
22 24
23/* AR5416 may return very high value (like -31 dBm), in those cases the nf 25/* AR5416 may return very high value (like -31 dBm), in those cases the nf
24 * is incorrect and we should use the static NF value. Later we can try to 26 * is incorrect and we should use the static NF value. Later we can try to
@@ -87,98 +89,9 @@ static void ath9k_hw_update_nfcal_hist_buffer(struct ath9k_nfcal_hist *h,
87 return; 89 return;
88} 90}
89 91
90static void ath9k_hw_do_getnf(struct ath_hw *ah, 92static bool ath9k_hw_get_nf_thresh(struct ath_hw *ah,
91 int16_t nfarray[NUM_NF_READINGS]) 93 enum ieee80211_band band,
92{ 94 int16_t *nft)
93 struct ath_common *common = ath9k_hw_common(ah);
94 int16_t nf;
95
96 if (AR_SREV_9280_10_OR_LATER(ah))
97 nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
98 else
99 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
100
101 if (nf & 0x100)
102 nf = 0 - ((nf ^ 0x1ff) + 1);
103 ath_print(common, ATH_DBG_CALIBRATE,
104 "NF calibrated [ctl] [chain 0] is %d\n", nf);
105
106 if (AR_SREV_9271(ah) && (nf >= -114))
107 nf = -116;
108
109 nfarray[0] = nf;
110
111 if (!AR_SREV_9285(ah) && !AR_SREV_9271(ah)) {
112 if (AR_SREV_9280_10_OR_LATER(ah))
113 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
114 AR9280_PHY_CH1_MINCCA_PWR);
115 else
116 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
117 AR_PHY_CH1_MINCCA_PWR);
118
119 if (nf & 0x100)
120 nf = 0 - ((nf ^ 0x1ff) + 1);
121 ath_print(common, ATH_DBG_CALIBRATE,
122 "NF calibrated [ctl] [chain 1] is %d\n", nf);
123 nfarray[1] = nf;
124
125 if (!AR_SREV_9280(ah) && !AR_SREV_9287(ah)) {
126 nf = MS(REG_READ(ah, AR_PHY_CH2_CCA),
127 AR_PHY_CH2_MINCCA_PWR);
128 if (nf & 0x100)
129 nf = 0 - ((nf ^ 0x1ff) + 1);
130 ath_print(common, ATH_DBG_CALIBRATE,
131 "NF calibrated [ctl] [chain 2] is %d\n", nf);
132 nfarray[2] = nf;
133 }
134 }
135
136 if (AR_SREV_9280_10_OR_LATER(ah))
137 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),
138 AR9280_PHY_EXT_MINCCA_PWR);
139 else
140 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),
141 AR_PHY_EXT_MINCCA_PWR);
142
143 if (nf & 0x100)
144 nf = 0 - ((nf ^ 0x1ff) + 1);
145 ath_print(common, ATH_DBG_CALIBRATE,
146 "NF calibrated [ext] [chain 0] is %d\n", nf);
147
148 if (AR_SREV_9271(ah) && (nf >= -114))
149 nf = -116;
150
151 nfarray[3] = nf;
152
153 if (!AR_SREV_9285(ah) && !AR_SREV_9271(ah)) {
154 if (AR_SREV_9280_10_OR_LATER(ah))
155 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
156 AR9280_PHY_CH1_EXT_MINCCA_PWR);
157 else
158 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
159 AR_PHY_CH1_EXT_MINCCA_PWR);
160
161 if (nf & 0x100)
162 nf = 0 - ((nf ^ 0x1ff) + 1);
163 ath_print(common, ATH_DBG_CALIBRATE,
164 "NF calibrated [ext] [chain 1] is %d\n", nf);
165 nfarray[4] = nf;
166
167 if (!AR_SREV_9280(ah) && !AR_SREV_9287(ah)) {
168 nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA),
169 AR_PHY_CH2_EXT_MINCCA_PWR);
170 if (nf & 0x100)
171 nf = 0 - ((nf ^ 0x1ff) + 1);
172 ath_print(common, ATH_DBG_CALIBRATE,
173 "NF calibrated [ext] [chain 2] is %d\n", nf);
174 nfarray[5] = nf;
175 }
176 }
177}
178
179static bool getNoiseFloorThresh(struct ath_hw *ah,
180 enum ieee80211_band band,
181 int16_t *nft)
182{ 95{
183 switch (band) { 96 switch (band) {
184 case IEEE80211_BAND_5GHZ: 97 case IEEE80211_BAND_5GHZ:
@@ -195,44 +108,8 @@ static bool getNoiseFloorThresh(struct ath_hw *ah,
195 return true; 108 return true;
196} 109}
197 110
198static void ath9k_hw_setup_calibration(struct ath_hw *ah, 111void ath9k_hw_reset_calibration(struct ath_hw *ah,
199 struct ath9k_cal_list *currCal) 112 struct ath9k_cal_list *currCal)
200{
201 struct ath_common *common = ath9k_hw_common(ah);
202
203 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
204 AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
205 currCal->calData->calCountMax);
206
207 switch (currCal->calData->calType) {
208 case IQ_MISMATCH_CAL:
209 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
210 ath_print(common, ATH_DBG_CALIBRATE,
211 "starting IQ Mismatch Calibration\n");
212 break;
213 case ADC_GAIN_CAL:
214 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
215 ath_print(common, ATH_DBG_CALIBRATE,
216 "starting ADC Gain Calibration\n");
217 break;
218 case ADC_DC_CAL:
219 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
220 ath_print(common, ATH_DBG_CALIBRATE,
221 "starting ADC DC Calibration\n");
222 break;
223 case ADC_DC_INIT_CAL:
224 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
225 ath_print(common, ATH_DBG_CALIBRATE,
226 "starting Init ADC DC Calibration\n");
227 break;
228 }
229
230 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
231 AR_PHY_TIMING_CTRL4_DO_CAL);
232}
233
234static void ath9k_hw_reset_calibration(struct ath_hw *ah,
235 struct ath9k_cal_list *currCal)
236{ 113{
237 int i; 114 int i;
238 115
@@ -250,324 +127,6 @@ static void ath9k_hw_reset_calibration(struct ath_hw *ah,
250 ah->cal_samples = 0; 127 ah->cal_samples = 0;
251} 128}
252 129
253static bool ath9k_hw_per_calibration(struct ath_hw *ah,
254 struct ath9k_channel *ichan,
255 u8 rxchainmask,
256 struct ath9k_cal_list *currCal)
257{
258 bool iscaldone = false;
259
260 if (currCal->calState == CAL_RUNNING) {
261 if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &
262 AR_PHY_TIMING_CTRL4_DO_CAL)) {
263
264 currCal->calData->calCollect(ah);
265 ah->cal_samples++;
266
267 if (ah->cal_samples >= currCal->calData->calNumSamples) {
268 int i, numChains = 0;
269 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
270 if (rxchainmask & (1 << i))
271 numChains++;
272 }
273
274 currCal->calData->calPostProc(ah, numChains);
275 ichan->CalValid |= currCal->calData->calType;
276 currCal->calState = CAL_DONE;
277 iscaldone = true;
278 } else {
279 ath9k_hw_setup_calibration(ah, currCal);
280 }
281 }
282 } else if (!(ichan->CalValid & currCal->calData->calType)) {
283 ath9k_hw_reset_calibration(ah, currCal);
284 }
285
286 return iscaldone;
287}
288
289/* Assumes you are talking about the currently configured channel */
290static bool ath9k_hw_iscal_supported(struct ath_hw *ah,
291 enum ath9k_cal_types calType)
292{
293 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
294
295 switch (calType & ah->supp_cals) {
296 case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */
297 return true;
298 case ADC_GAIN_CAL:
299 case ADC_DC_CAL:
300 if (!(conf->channel->band == IEEE80211_BAND_2GHZ &&
301 conf_is_ht20(conf)))
302 return true;
303 break;
304 }
305 return false;
306}
307
308static void ath9k_hw_iqcal_collect(struct ath_hw *ah)
309{
310 int i;
311
312 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
313 ah->totalPowerMeasI[i] +=
314 REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
315 ah->totalPowerMeasQ[i] +=
316 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
317 ah->totalIqCorrMeas[i] +=
318 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
319 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
320 "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
321 ah->cal_samples, i, ah->totalPowerMeasI[i],
322 ah->totalPowerMeasQ[i],
323 ah->totalIqCorrMeas[i]);
324 }
325}
326
327static void ath9k_hw_adc_gaincal_collect(struct ath_hw *ah)
328{
329 int i;
330
331 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
332 ah->totalAdcIOddPhase[i] +=
333 REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
334 ah->totalAdcIEvenPhase[i] +=
335 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
336 ah->totalAdcQOddPhase[i] +=
337 REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
338 ah->totalAdcQEvenPhase[i] +=
339 REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
340
341 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
342 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
343 "oddq=0x%08x; evenq=0x%08x;\n",
344 ah->cal_samples, i,
345 ah->totalAdcIOddPhase[i],
346 ah->totalAdcIEvenPhase[i],
347 ah->totalAdcQOddPhase[i],
348 ah->totalAdcQEvenPhase[i]);
349 }
350}
351
352static void ath9k_hw_adc_dccal_collect(struct ath_hw *ah)
353{
354 int i;
355
356 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
357 ah->totalAdcDcOffsetIOddPhase[i] +=
358 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
359 ah->totalAdcDcOffsetIEvenPhase[i] +=
360 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
361 ah->totalAdcDcOffsetQOddPhase[i] +=
362 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
363 ah->totalAdcDcOffsetQEvenPhase[i] +=
364 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
365
366 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
367 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
368 "oddq=0x%08x; evenq=0x%08x;\n",
369 ah->cal_samples, i,
370 ah->totalAdcDcOffsetIOddPhase[i],
371 ah->totalAdcDcOffsetIEvenPhase[i],
372 ah->totalAdcDcOffsetQOddPhase[i],
373 ah->totalAdcDcOffsetQEvenPhase[i]);
374 }
375}
376
377static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
378{
379 struct ath_common *common = ath9k_hw_common(ah);
380 u32 powerMeasQ, powerMeasI, iqCorrMeas;
381 u32 qCoffDenom, iCoffDenom;
382 int32_t qCoff, iCoff;
383 int iqCorrNeg, i;
384
385 for (i = 0; i < numChains; i++) {
386 powerMeasI = ah->totalPowerMeasI[i];
387 powerMeasQ = ah->totalPowerMeasQ[i];
388 iqCorrMeas = ah->totalIqCorrMeas[i];
389
390 ath_print(common, ATH_DBG_CALIBRATE,
391 "Starting IQ Cal and Correction for Chain %d\n",
392 i);
393
394 ath_print(common, ATH_DBG_CALIBRATE,
395 "Orignal: Chn %diq_corr_meas = 0x%08x\n",
396 i, ah->totalIqCorrMeas[i]);
397
398 iqCorrNeg = 0;
399
400 if (iqCorrMeas > 0x80000000) {
401 iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
402 iqCorrNeg = 1;
403 }
404
405 ath_print(common, ATH_DBG_CALIBRATE,
406 "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
407 ath_print(common, ATH_DBG_CALIBRATE,
408 "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
409 ath_print(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
410 iqCorrNeg);
411
412 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
413 qCoffDenom = powerMeasQ / 64;
414
415 if ((powerMeasQ != 0) && (iCoffDenom != 0) &&
416 (qCoffDenom != 0)) {
417 iCoff = iqCorrMeas / iCoffDenom;
418 qCoff = powerMeasI / qCoffDenom - 64;
419 ath_print(common, ATH_DBG_CALIBRATE,
420 "Chn %d iCoff = 0x%08x\n", i, iCoff);
421 ath_print(common, ATH_DBG_CALIBRATE,
422 "Chn %d qCoff = 0x%08x\n", i, qCoff);
423
424 iCoff = iCoff & 0x3f;
425 ath_print(common, ATH_DBG_CALIBRATE,
426 "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
427 if (iqCorrNeg == 0x0)
428 iCoff = 0x40 - iCoff;
429
430 if (qCoff > 15)
431 qCoff = 15;
432 else if (qCoff <= -16)
433 qCoff = 16;
434
435 ath_print(common, ATH_DBG_CALIBRATE,
436 "Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
437 i, iCoff, qCoff);
438
439 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
440 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
441 iCoff);
442 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
443 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
444 qCoff);
445 ath_print(common, ATH_DBG_CALIBRATE,
446 "IQ Cal and Correction done for Chain %d\n",
447 i);
448 }
449 }
450
451 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
452 AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);
453}
454
455static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
456{
457 struct ath_common *common = ath9k_hw_common(ah);
458 u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset, qEvenMeasOffset;
459 u32 qGainMismatch, iGainMismatch, val, i;
460
461 for (i = 0; i < numChains; i++) {
462 iOddMeasOffset = ah->totalAdcIOddPhase[i];
463 iEvenMeasOffset = ah->totalAdcIEvenPhase[i];
464 qOddMeasOffset = ah->totalAdcQOddPhase[i];
465 qEvenMeasOffset = ah->totalAdcQEvenPhase[i];
466
467 ath_print(common, ATH_DBG_CALIBRATE,
468 "Starting ADC Gain Cal for Chain %d\n", i);
469
470 ath_print(common, ATH_DBG_CALIBRATE,
471 "Chn %d pwr_meas_odd_i = 0x%08x\n", i,
472 iOddMeasOffset);
473 ath_print(common, ATH_DBG_CALIBRATE,
474 "Chn %d pwr_meas_even_i = 0x%08x\n", i,
475 iEvenMeasOffset);
476 ath_print(common, ATH_DBG_CALIBRATE,
477 "Chn %d pwr_meas_odd_q = 0x%08x\n", i,
478 qOddMeasOffset);
479 ath_print(common, ATH_DBG_CALIBRATE,
480 "Chn %d pwr_meas_even_q = 0x%08x\n", i,
481 qEvenMeasOffset);
482
483 if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) {
484 iGainMismatch =
485 ((iEvenMeasOffset * 32) /
486 iOddMeasOffset) & 0x3f;
487 qGainMismatch =
488 ((qOddMeasOffset * 32) /
489 qEvenMeasOffset) & 0x3f;
490
491 ath_print(common, ATH_DBG_CALIBRATE,
492 "Chn %d gain_mismatch_i = 0x%08x\n", i,
493 iGainMismatch);
494 ath_print(common, ATH_DBG_CALIBRATE,
495 "Chn %d gain_mismatch_q = 0x%08x\n", i,
496 qGainMismatch);
497
498 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
499 val &= 0xfffff000;
500 val |= (qGainMismatch) | (iGainMismatch << 6);
501 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
502
503 ath_print(common, ATH_DBG_CALIBRATE,
504 "ADC Gain Cal done for Chain %d\n", i);
505 }
506 }
507
508 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
509 REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
510 AR_PHY_NEW_ADC_GAIN_CORR_ENABLE);
511}
512
513static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
514{
515 struct ath_common *common = ath9k_hw_common(ah);
516 u32 iOddMeasOffset, iEvenMeasOffset, val, i;
517 int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch;
518 const struct ath9k_percal_data *calData =
519 ah->cal_list_curr->calData;
520 u32 numSamples =
521 (1 << (calData->calCountMax + 5)) * calData->calNumSamples;
522
523 for (i = 0; i < numChains; i++) {
524 iOddMeasOffset = ah->totalAdcDcOffsetIOddPhase[i];
525 iEvenMeasOffset = ah->totalAdcDcOffsetIEvenPhase[i];
526 qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i];
527 qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i];
528
529 ath_print(common, ATH_DBG_CALIBRATE,
530 "Starting ADC DC Offset Cal for Chain %d\n", i);
531
532 ath_print(common, ATH_DBG_CALIBRATE,
533 "Chn %d pwr_meas_odd_i = %d\n", i,
534 iOddMeasOffset);
535 ath_print(common, ATH_DBG_CALIBRATE,
536 "Chn %d pwr_meas_even_i = %d\n", i,
537 iEvenMeasOffset);
538 ath_print(common, ATH_DBG_CALIBRATE,
539 "Chn %d pwr_meas_odd_q = %d\n", i,
540 qOddMeasOffset);
541 ath_print(common, ATH_DBG_CALIBRATE,
542 "Chn %d pwr_meas_even_q = %d\n", i,
543 qEvenMeasOffset);
544
545 iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
546 numSamples) & 0x1ff;
547 qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
548 numSamples) & 0x1ff;
549
550 ath_print(common, ATH_DBG_CALIBRATE,
551 "Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
552 iDcMismatch);
553 ath_print(common, ATH_DBG_CALIBRATE,
554 "Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
555 qDcMismatch);
556
557 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
558 val &= 0xc0000fff;
559 val |= (qDcMismatch << 12) | (iDcMismatch << 21);
560 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
561
562 ath_print(common, ATH_DBG_CALIBRATE,
563 "ADC DC Offset Cal done for Chain %d\n", i);
564 }
565
566 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
567 REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
568 AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
569}
570
571/* This is done for the currently configured channel */ 130/* This is done for the currently configured channel */
572bool ath9k_hw_reset_calvalid(struct ath_hw *ah) 131bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
573{ 132{
@@ -614,72 +173,6 @@ void ath9k_hw_start_nfcal(struct ath_hw *ah)
614 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); 173 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
615} 174}
616 175
617void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
618{
619 struct ath9k_nfcal_hist *h;
620 int i, j;
621 int32_t val;
622 const u32 ar5416_cca_regs[6] = {
623 AR_PHY_CCA,
624 AR_PHY_CH1_CCA,
625 AR_PHY_CH2_CCA,
626 AR_PHY_EXT_CCA,
627 AR_PHY_CH1_EXT_CCA,
628 AR_PHY_CH2_EXT_CCA
629 };
630 u8 chainmask, rx_chain_status;
631
632 rx_chain_status = REG_READ(ah, AR_PHY_RX_CHAINMASK);
633 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
634 chainmask = 0x9;
635 else if (AR_SREV_9280(ah) || AR_SREV_9287(ah)) {
636 if ((rx_chain_status & 0x2) || (rx_chain_status & 0x4))
637 chainmask = 0x1B;
638 else
639 chainmask = 0x09;
640 } else {
641 if (rx_chain_status & 0x4)
642 chainmask = 0x3F;
643 else if (rx_chain_status & 0x2)
644 chainmask = 0x1B;
645 else
646 chainmask = 0x09;
647 }
648
649 h = ah->nfCalHist;
650
651 for (i = 0; i < NUM_NF_READINGS; i++) {
652 if (chainmask & (1 << i)) {
653 val = REG_READ(ah, ar5416_cca_regs[i]);
654 val &= 0xFFFFFE00;
655 val |= (((u32) (h[i].privNF) << 1) & 0x1ff);
656 REG_WRITE(ah, ar5416_cca_regs[i], val);
657 }
658 }
659
660 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
661 AR_PHY_AGC_CONTROL_ENABLE_NF);
662 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
663 AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
664 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
665
666 for (j = 0; j < 5; j++) {
667 if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
668 AR_PHY_AGC_CONTROL_NF) == 0)
669 break;
670 udelay(50);
671 }
672
673 for (i = 0; i < NUM_NF_READINGS; i++) {
674 if (chainmask & (1 << i)) {
675 val = REG_READ(ah, ar5416_cca_regs[i]);
676 val &= 0xFFFFFE00;
677 val |= (((u32) (-50) << 1) & 0x1ff);
678 REG_WRITE(ah, ar5416_cca_regs[i], val);
679 }
680 }
681}
682
683int16_t ath9k_hw_getnf(struct ath_hw *ah, 176int16_t ath9k_hw_getnf(struct ath_hw *ah,
684 struct ath9k_channel *chan) 177 struct ath9k_channel *chan)
685{ 178{
@@ -699,7 +192,7 @@ int16_t ath9k_hw_getnf(struct ath_hw *ah,
699 } else { 192 } else {
700 ath9k_hw_do_getnf(ah, nfarray); 193 ath9k_hw_do_getnf(ah, nfarray);
701 nf = nfarray[0]; 194 nf = nfarray[0];
702 if (getNoiseFloorThresh(ah, c->band, &nfThresh) 195 if (ath9k_hw_get_nf_thresh(ah, c->band, &nfThresh)
703 && nf > nfThresh) { 196 && nf > nfThresh) {
704 ath_print(common, ATH_DBG_CALIBRATE, 197 ath_print(common, ATH_DBG_CALIBRATE,
705 "noise floor failed detected; " 198 "noise floor failed detected; "
@@ -757,567 +250,3 @@ s16 ath9k_hw_getchan_noise(struct ath_hw *ah, struct ath9k_channel *chan)
757 return nf; 250 return nf;
758} 251}
759EXPORT_SYMBOL(ath9k_hw_getchan_noise); 252EXPORT_SYMBOL(ath9k_hw_getchan_noise);
760
761static void ath9k_olc_temp_compensation_9287(struct ath_hw *ah)
762{
763 u32 rddata;
764 int32_t delta, currPDADC, slope;
765
766 rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
767 currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
768
769 if (ah->initPDADC == 0 || currPDADC == 0) {
770 /*
771 * Zero value indicates that no frames have been transmitted yet,
772 * can't do temperature compensation until frames are transmitted.
773 */
774 return;
775 } else {
776 slope = ah->eep_ops->get_eeprom(ah, EEP_TEMPSENSE_SLOPE);
777
778 if (slope == 0) { /* to avoid divide by zero case */
779 delta = 0;
780 } else {
781 delta = ((currPDADC - ah->initPDADC)*4) / slope;
782 }
783 REG_RMW_FIELD(ah, AR_PHY_CH0_TX_PWRCTRL11,
784 AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
785 REG_RMW_FIELD(ah, AR_PHY_CH1_TX_PWRCTRL11,
786 AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
787 }
788}
789
790static void ath9k_olc_temp_compensation(struct ath_hw *ah)
791{
792 u32 rddata, i;
793 int delta, currPDADC, regval;
794
795 if (OLC_FOR_AR9287_10_LATER) {
796 ath9k_olc_temp_compensation_9287(ah);
797 } else {
798 rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
799 currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
800
801 if (ah->initPDADC == 0 || currPDADC == 0) {
802 return;
803 } else {
804 if (ah->eep_ops->get_eeprom(ah, EEP_DAC_HPWR_5G))
805 delta = (currPDADC - ah->initPDADC + 4) / 8;
806 else
807 delta = (currPDADC - ah->initPDADC + 5) / 10;
808
809 if (delta != ah->PDADCdelta) {
810 ah->PDADCdelta = delta;
811 for (i = 1; i < AR9280_TX_GAIN_TABLE_SIZE; i++) {
812 regval = ah->originalGain[i] - delta;
813 if (regval < 0)
814 regval = 0;
815
816 REG_RMW_FIELD(ah,
817 AR_PHY_TX_GAIN_TBL1 + i * 4,
818 AR_PHY_TX_GAIN, regval);
819 }
820 }
821 }
822 }
823}
824
825static void ath9k_hw_9271_pa_cal(struct ath_hw *ah, bool is_reset)
826{
827 u32 regVal;
828 unsigned int i;
829 u32 regList [][2] = {
830 { 0x786c, 0 },
831 { 0x7854, 0 },
832 { 0x7820, 0 },
833 { 0x7824, 0 },
834 { 0x7868, 0 },
835 { 0x783c, 0 },
836 { 0x7838, 0 } ,
837 { 0x7828, 0 } ,
838 };
839
840 for (i = 0; i < ARRAY_SIZE(regList); i++)
841 regList[i][1] = REG_READ(ah, regList[i][0]);
842
843 regVal = REG_READ(ah, 0x7834);
844 regVal &= (~(0x1));
845 REG_WRITE(ah, 0x7834, regVal);
846 regVal = REG_READ(ah, 0x9808);
847 regVal |= (0x1 << 27);
848 REG_WRITE(ah, 0x9808, regVal);
849
850 /* 786c,b23,1, pwddac=1 */
851 REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
852 /* 7854, b5,1, pdrxtxbb=1 */
853 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
854 /* 7854, b7,1, pdv2i=1 */
855 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
856 /* 7854, b8,1, pddacinterface=1 */
857 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
858 /* 7824,b12,0, offcal=0 */
859 REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
860 /* 7838, b1,0, pwddb=0 */
861 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
862 /* 7820,b11,0, enpacal=0 */
863 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
864 /* 7820,b25,1, pdpadrv1=0 */
865 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
866 /* 7820,b24,0, pdpadrv2=0 */
867 REG_RMW_FIELD(ah, AR9285_AN_RF2G1,AR9285_AN_RF2G1_PDPADRV2,0);
868 /* 7820,b23,0, pdpaout=0 */
869 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
870 /* 783c,b14-16,7, padrvgn2tab_0=7 */
871 REG_RMW_FIELD(ah, AR9285_AN_RF2G8,AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
872 /*
873 * 7838,b29-31,0, padrvgn1tab_0=0
874 * does not matter since we turn it off
875 */
876 REG_RMW_FIELD(ah, AR9285_AN_RF2G7,AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
877
878 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9271_AN_RF2G3_CCOMP, 0xfff);
879
880 /* Set:
881 * localmode=1,bmode=1,bmoderxtx=1,synthon=1,
882 * txon=1,paon=1,oscon=1,synthon_force=1
883 */
884 REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
885 udelay(30);
886 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9271_AN_RF2G6_OFFS, 0);
887
888 /* find off_6_1; */
889 for (i = 6; i > 0; i--) {
890 regVal = REG_READ(ah, 0x7834);
891 regVal |= (1 << (20 + i));
892 REG_WRITE(ah, 0x7834, regVal);
893 udelay(1);
894 //regVal = REG_READ(ah, 0x7834);
895 regVal &= (~(0x1 << (20 + i)));
896 regVal |= (MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9)
897 << (20 + i));
898 REG_WRITE(ah, 0x7834, regVal);
899 }
900
901 regVal = (regVal >>20) & 0x7f;
902
903 /* Update PA cal info */
904 if ((!is_reset) && (ah->pacal_info.prev_offset == regVal)) {
905 if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
906 ah->pacal_info.max_skipcount =
907 2 * ah->pacal_info.max_skipcount;
908 ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
909 } else {
910 ah->pacal_info.max_skipcount = 1;
911 ah->pacal_info.skipcount = 0;
912 ah->pacal_info.prev_offset = regVal;
913 }
914
915 regVal = REG_READ(ah, 0x7834);
916 regVal |= 0x1;
917 REG_WRITE(ah, 0x7834, regVal);
918 regVal = REG_READ(ah, 0x9808);
919 regVal &= (~(0x1 << 27));
920 REG_WRITE(ah, 0x9808, regVal);
921
922 for (i = 0; i < ARRAY_SIZE(regList); i++)
923 REG_WRITE(ah, regList[i][0], regList[i][1]);
924}
925
926static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah, bool is_reset)
927{
928 struct ath_common *common = ath9k_hw_common(ah);
929 u32 regVal;
930 int i, offset, offs_6_1, offs_0;
931 u32 ccomp_org, reg_field;
932 u32 regList[][2] = {
933 { 0x786c, 0 },
934 { 0x7854, 0 },
935 { 0x7820, 0 },
936 { 0x7824, 0 },
937 { 0x7868, 0 },
938 { 0x783c, 0 },
939 { 0x7838, 0 },
940 };
941
942 ath_print(common, ATH_DBG_CALIBRATE, "Running PA Calibration\n");
943
944 /* PA CAL is not needed for high power solution */
945 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) ==
946 AR5416_EEP_TXGAIN_HIGH_POWER)
947 return;
948
949 if (AR_SREV_9285_11(ah)) {
950 REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
951 udelay(10);
952 }
953
954 for (i = 0; i < ARRAY_SIZE(regList); i++)
955 regList[i][1] = REG_READ(ah, regList[i][0]);
956
957 regVal = REG_READ(ah, 0x7834);
958 regVal &= (~(0x1));
959 REG_WRITE(ah, 0x7834, regVal);
960 regVal = REG_READ(ah, 0x9808);
961 regVal |= (0x1 << 27);
962 REG_WRITE(ah, 0x9808, regVal);
963
964 REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
965 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
966 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
967 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
968 REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
969 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
970 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
971 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
972 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0);
973 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
974 REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
975 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
976 ccomp_org = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP);
977 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, 0xf);
978
979 REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
980 udelay(30);
981 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, 0);
982 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 0);
983
984 for (i = 6; i > 0; i--) {
985 regVal = REG_READ(ah, 0x7834);
986 regVal |= (1 << (19 + i));
987 REG_WRITE(ah, 0x7834, regVal);
988 udelay(1);
989 regVal = REG_READ(ah, 0x7834);
990 regVal &= (~(0x1 << (19 + i)));
991 reg_field = MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9);
992 regVal |= (reg_field << (19 + i));
993 REG_WRITE(ah, 0x7834, regVal);
994 }
995
996 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 1);
997 udelay(1);
998 reg_field = MS(REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9);
999 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, reg_field);
1000 offs_6_1 = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS);
1001 offs_0 = MS(REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP);
1002
1003 offset = (offs_6_1<<1) | offs_0;
1004 offset = offset - 0;
1005 offs_6_1 = offset>>1;
1006 offs_0 = offset & 1;
1007
1008 if ((!is_reset) && (ah->pacal_info.prev_offset == offset)) {
1009 if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
1010 ah->pacal_info.max_skipcount =
1011 2 * ah->pacal_info.max_skipcount;
1012 ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
1013 } else {
1014 ah->pacal_info.max_skipcount = 1;
1015 ah->pacal_info.skipcount = 0;
1016 ah->pacal_info.prev_offset = offset;
1017 }
1018
1019 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1);
1020 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0);
1021
1022 regVal = REG_READ(ah, 0x7834);
1023 regVal |= 0x1;
1024 REG_WRITE(ah, 0x7834, regVal);
1025 regVal = REG_READ(ah, 0x9808);
1026 regVal &= (~(0x1 << 27));
1027 REG_WRITE(ah, 0x9808, regVal);
1028
1029 for (i = 0; i < ARRAY_SIZE(regList); i++)
1030 REG_WRITE(ah, regList[i][0], regList[i][1]);
1031
1032 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, ccomp_org);
1033
1034 if (AR_SREV_9285_11(ah))
1035 REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);
1036
1037}
1038
1039bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
1040 u8 rxchainmask, bool longcal)
1041{
1042 bool iscaldone = true;
1043 struct ath9k_cal_list *currCal = ah->cal_list_curr;
1044
1045 if (currCal &&
1046 (currCal->calState == CAL_RUNNING ||
1047 currCal->calState == CAL_WAITING)) {
1048 iscaldone = ath9k_hw_per_calibration(ah, chan,
1049 rxchainmask, currCal);
1050 if (iscaldone) {
1051 ah->cal_list_curr = currCal = currCal->calNext;
1052
1053 if (currCal->calState == CAL_WAITING) {
1054 iscaldone = false;
1055 ath9k_hw_reset_calibration(ah, currCal);
1056 }
1057 }
1058 }
1059
1060 /* Do NF cal only at longer intervals */
1061 if (longcal) {
1062 /* Do periodic PAOffset Cal */
1063 if (AR_SREV_9271(ah)) {
1064 if (!ah->pacal_info.skipcount)
1065 ath9k_hw_9271_pa_cal(ah, false);
1066 else
1067 ah->pacal_info.skipcount--;
1068 } else if (AR_SREV_9285_11_OR_LATER(ah)) {
1069 if (!ah->pacal_info.skipcount)
1070 ath9k_hw_9285_pa_cal(ah, false);
1071 else
1072 ah->pacal_info.skipcount--;
1073 }
1074
1075 if (OLC_FOR_AR9280_20_LATER || OLC_FOR_AR9287_10_LATER)
1076 ath9k_olc_temp_compensation(ah);
1077
1078 /* Get the value from the previous NF cal and update history buffer */
1079 ath9k_hw_getnf(ah, chan);
1080
1081 /*
1082 * Load the NF from history buffer of the current channel.
1083 * NF is slow time-variant, so it is OK to use a historical value.
1084 */
1085 ath9k_hw_loadnf(ah, ah->curchan);
1086
1087 ath9k_hw_start_nfcal(ah);
1088 }
1089
1090 return iscaldone;
1091}
1092EXPORT_SYMBOL(ath9k_hw_calibrate);
1093
1094/* Carrier leakage Calibration fix */
1095static bool ar9285_cl_cal(struct ath_hw *ah, struct ath9k_channel *chan)
1096{
1097 struct ath_common *common = ath9k_hw_common(ah);
1098
1099 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
1100 if (IS_CHAN_HT20(chan)) {
1101 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
1102 REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
1103 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
1104 AR_PHY_AGC_CONTROL_FLTR_CAL);
1105 REG_CLR_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
1106 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
1107 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
1108 AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) {
1109 ath_print(common, ATH_DBG_CALIBRATE, "offset "
1110 "calibration failed to complete in "
1111 "1ms; noisy ??\n");
1112 return false;
1113 }
1114 REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
1115 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
1116 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
1117 }
1118 REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
1119 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
1120 REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
1121 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
1122 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
1123 0, AH_WAIT_TIMEOUT)) {
1124 ath_print(common, ATH_DBG_CALIBRATE, "offset calibration "
1125 "failed to complete in 1ms; noisy ??\n");
1126 return false;
1127 }
1128
1129 REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
1130 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
1131 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
1132
1133 return true;
1134}
1135
1136static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan)
1137{
1138 int i;
1139 u_int32_t txgain_max;
1140 u_int32_t clc_gain, gain_mask = 0, clc_num = 0;
1141 u_int32_t reg_clc_I0, reg_clc_Q0;
1142 u_int32_t i0_num = 0;
1143 u_int32_t q0_num = 0;
1144 u_int32_t total_num = 0;
1145 u_int32_t reg_rf2g5_org;
1146 bool retv = true;
1147
1148 if (!(ar9285_cl_cal(ah, chan)))
1149 return false;
1150
1151 txgain_max = MS(REG_READ(ah, AR_PHY_TX_PWRCTRL7),
1152 AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX);
1153
1154 for (i = 0; i < (txgain_max+1); i++) {
1155 clc_gain = (REG_READ(ah, (AR_PHY_TX_GAIN_TBL1+(i<<2))) &
1156 AR_PHY_TX_GAIN_CLC) >> AR_PHY_TX_GAIN_CLC_S;
1157 if (!(gain_mask & (1 << clc_gain))) {
1158 gain_mask |= (1 << clc_gain);
1159 clc_num++;
1160 }
1161 }
1162
1163 for (i = 0; i < clc_num; i++) {
1164 reg_clc_I0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))
1165 & AR_PHY_CLC_I0) >> AR_PHY_CLC_I0_S;
1166 reg_clc_Q0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))
1167 & AR_PHY_CLC_Q0) >> AR_PHY_CLC_Q0_S;
1168 if (reg_clc_I0 == 0)
1169 i0_num++;
1170
1171 if (reg_clc_Q0 == 0)
1172 q0_num++;
1173 }
1174 total_num = i0_num + q0_num;
1175 if (total_num > AR9285_CLCAL_REDO_THRESH) {
1176 reg_rf2g5_org = REG_READ(ah, AR9285_RF2G5);
1177 if (AR_SREV_9285E_20(ah)) {
1178 REG_WRITE(ah, AR9285_RF2G5,
1179 (reg_rf2g5_org & AR9285_RF2G5_IC50TX) |
1180 AR9285_RF2G5_IC50TX_XE_SET);
1181 } else {
1182 REG_WRITE(ah, AR9285_RF2G5,
1183 (reg_rf2g5_org & AR9285_RF2G5_IC50TX) |
1184 AR9285_RF2G5_IC50TX_SET);
1185 }
1186 retv = ar9285_cl_cal(ah, chan);
1187 REG_WRITE(ah, AR9285_RF2G5, reg_rf2g5_org);
1188 }
1189 return retv;
1190}
1191
1192bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
1193{
1194 struct ath_common *common = ath9k_hw_common(ah);
1195
1196 if (AR_SREV_9271(ah) || AR_SREV_9285_12_OR_LATER(ah)) {
1197 if (!ar9285_clc(ah, chan))
1198 return false;
1199 } else {
1200 if (AR_SREV_9280_10_OR_LATER(ah)) {
1201 if (!AR_SREV_9287_10_OR_LATER(ah))
1202 REG_CLR_BIT(ah, AR_PHY_ADC_CTL,
1203 AR_PHY_ADC_CTL_OFF_PWDADC);
1204 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
1205 AR_PHY_AGC_CONTROL_FLTR_CAL);
1206 }
1207
1208 /* Calibrate the AGC */
1209 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
1210 REG_READ(ah, AR_PHY_AGC_CONTROL) |
1211 AR_PHY_AGC_CONTROL_CAL);
1212
1213 /* Poll for offset calibration complete */
1214 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
1215 0, AH_WAIT_TIMEOUT)) {
1216 ath_print(common, ATH_DBG_CALIBRATE,
1217 "offset calibration failed to "
1218 "complete in 1ms; noisy environment?\n");
1219 return false;
1220 }
1221
1222 if (AR_SREV_9280_10_OR_LATER(ah)) {
1223 if (!AR_SREV_9287_10_OR_LATER(ah))
1224 REG_SET_BIT(ah, AR_PHY_ADC_CTL,
1225 AR_PHY_ADC_CTL_OFF_PWDADC);
1226 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
1227 AR_PHY_AGC_CONTROL_FLTR_CAL);
1228 }
1229 }
1230
1231 /* Do PA Calibration */
1232 if (AR_SREV_9271(ah))
1233 ath9k_hw_9271_pa_cal(ah, true);
1234 else if (AR_SREV_9285_11_OR_LATER(ah))
1235 ath9k_hw_9285_pa_cal(ah, true);
1236
1237 /* Do NF Calibration after DC offset and other calibrations */
1238 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
1239 REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_NF);
1240
1241 ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
1242
1243 /* Enable IQ, ADC Gain and ADC DC offset CALs */
1244 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
1245 if (ath9k_hw_iscal_supported(ah, ADC_GAIN_CAL)) {
1246 INIT_CAL(&ah->adcgain_caldata);
1247 INSERT_CAL(ah, &ah->adcgain_caldata);
1248 ath_print(common, ATH_DBG_CALIBRATE,
1249 "enabling ADC Gain Calibration.\n");
1250 }
1251 if (ath9k_hw_iscal_supported(ah, ADC_DC_CAL)) {
1252 INIT_CAL(&ah->adcdc_caldata);
1253 INSERT_CAL(ah, &ah->adcdc_caldata);
1254 ath_print(common, ATH_DBG_CALIBRATE,
1255 "enabling ADC DC Calibration.\n");
1256 }
1257 if (ath9k_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {
1258 INIT_CAL(&ah->iq_caldata);
1259 INSERT_CAL(ah, &ah->iq_caldata);
1260 ath_print(common, ATH_DBG_CALIBRATE,
1261 "enabling IQ Calibration.\n");
1262 }
1263
1264 ah->cal_list_curr = ah->cal_list;
1265
1266 if (ah->cal_list_curr)
1267 ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
1268 }
1269
1270 chan->CalValid = 0;
1271
1272 return true;
1273}
1274
1275const struct ath9k_percal_data iq_cal_multi_sample = {
1276 IQ_MISMATCH_CAL,
1277 MAX_CAL_SAMPLES,
1278 PER_MIN_LOG_COUNT,
1279 ath9k_hw_iqcal_collect,
1280 ath9k_hw_iqcalibrate
1281};
1282const struct ath9k_percal_data iq_cal_single_sample = {
1283 IQ_MISMATCH_CAL,
1284 MIN_CAL_SAMPLES,
1285 PER_MAX_LOG_COUNT,
1286 ath9k_hw_iqcal_collect,
1287 ath9k_hw_iqcalibrate
1288};
1289const struct ath9k_percal_data adc_gain_cal_multi_sample = {
1290 ADC_GAIN_CAL,
1291 MAX_CAL_SAMPLES,
1292 PER_MIN_LOG_COUNT,
1293 ath9k_hw_adc_gaincal_collect,
1294 ath9k_hw_adc_gaincal_calibrate
1295};
1296const struct ath9k_percal_data adc_gain_cal_single_sample = {
1297 ADC_GAIN_CAL,
1298 MIN_CAL_SAMPLES,
1299 PER_MAX_LOG_COUNT,
1300 ath9k_hw_adc_gaincal_collect,
1301 ath9k_hw_adc_gaincal_calibrate
1302};
1303const struct ath9k_percal_data adc_dc_cal_multi_sample = {
1304 ADC_DC_CAL,
1305 MAX_CAL_SAMPLES,
1306 PER_MIN_LOG_COUNT,
1307 ath9k_hw_adc_dccal_collect,
1308 ath9k_hw_adc_dccal_calibrate
1309};
1310const struct ath9k_percal_data adc_dc_cal_single_sample = {
1311 ADC_DC_CAL,
1312 MIN_CAL_SAMPLES,
1313 PER_MAX_LOG_COUNT,
1314 ath9k_hw_adc_dccal_collect,
1315 ath9k_hw_adc_dccal_calibrate
1316};
1317const struct ath9k_percal_data adc_init_dc_cal = {
1318 ADC_DC_INIT_CAL,
1319 MIN_CAL_SAMPLES,
1320 INIT_LOG_COUNT,
1321 ath9k_hw_adc_dccal_collect,
1322 ath9k_hw_adc_dccal_calibrate
1323};
diff --git a/drivers/net/wireless/ath/ath9k/calib.h b/drivers/net/wireless/ath/ath9k/calib.h
index b2c873e97485..24538bdb9126 100644
--- a/drivers/net/wireless/ath/ath9k/calib.h
+++ b/drivers/net/wireless/ath/ath9k/calib.h
@@ -19,14 +19,6 @@
19 19
20#include "hw.h" 20#include "hw.h"
21 21
22extern const struct ath9k_percal_data iq_cal_multi_sample;
23extern const struct ath9k_percal_data iq_cal_single_sample;
24extern const struct ath9k_percal_data adc_gain_cal_multi_sample;
25extern const struct ath9k_percal_data adc_gain_cal_single_sample;
26extern const struct ath9k_percal_data adc_dc_cal_multi_sample;
27extern const struct ath9k_percal_data adc_dc_cal_single_sample;
28extern const struct ath9k_percal_data adc_init_dc_cal;
29
30#define AR_PHY_CCA_MAX_AR5416_GOOD_VALUE -85 22#define AR_PHY_CCA_MAX_AR5416_GOOD_VALUE -85
31#define AR_PHY_CCA_MAX_AR9280_GOOD_VALUE -112 23#define AR_PHY_CCA_MAX_AR9280_GOOD_VALUE -112
32#define AR_PHY_CCA_MAX_AR9285_GOOD_VALUE -118 24#define AR_PHY_CCA_MAX_AR9285_GOOD_VALUE -118
@@ -76,7 +68,8 @@ enum ath9k_cal_types {
76 ADC_DC_INIT_CAL = 0x1, 68 ADC_DC_INIT_CAL = 0x1,
77 ADC_GAIN_CAL = 0x2, 69 ADC_GAIN_CAL = 0x2,
78 ADC_DC_CAL = 0x4, 70 ADC_DC_CAL = 0x4,
79 IQ_MISMATCH_CAL = 0x8 71 IQ_MISMATCH_CAL = 0x8,
72 TEMP_COMP_CAL = 0x10,
80}; 73};
81 74
82enum ath9k_cal_state { 75enum ath9k_cal_state {
@@ -122,14 +115,12 @@ struct ath9k_pacal_info{
122 115
123bool ath9k_hw_reset_calvalid(struct ath_hw *ah); 116bool ath9k_hw_reset_calvalid(struct ath_hw *ah);
124void ath9k_hw_start_nfcal(struct ath_hw *ah); 117void ath9k_hw_start_nfcal(struct ath_hw *ah);
125void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan);
126int16_t ath9k_hw_getnf(struct ath_hw *ah, 118int16_t ath9k_hw_getnf(struct ath_hw *ah,
127 struct ath9k_channel *chan); 119 struct ath9k_channel *chan);
128void ath9k_init_nfcal_hist_buffer(struct ath_hw *ah); 120void ath9k_init_nfcal_hist_buffer(struct ath_hw *ah);
129s16 ath9k_hw_getchan_noise(struct ath_hw *ah, struct ath9k_channel *chan); 121s16 ath9k_hw_getchan_noise(struct ath_hw *ah, struct ath9k_channel *chan);
130bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan, 122void ath9k_hw_reset_calibration(struct ath_hw *ah,
131 u8 rxchainmask, bool longcal); 123 struct ath9k_cal_list *currCal);
132bool ath9k_hw_init_cal(struct ath_hw *ah, 124
133 struct ath9k_channel *chan);
134 125
135#endif /* CALIB_H */ 126#endif /* CALIB_H */
diff --git a/drivers/net/wireless/ath/ath9k/common.c b/drivers/net/wireless/ath/ath9k/common.c
index 09effdedc8c0..b4424a623cf5 100644
--- a/drivers/net/wireless/ath/ath9k/common.c
+++ b/drivers/net/wireless/ath/ath9k/common.c
@@ -212,7 +212,6 @@ int ath9k_cmn_rx_skb_preprocess(struct ath_common *common,
212 rx_status->mactime = ath9k_hw_extend_tsf(ah, rx_stats->rs_tstamp); 212 rx_status->mactime = ath9k_hw_extend_tsf(ah, rx_stats->rs_tstamp);
213 rx_status->band = hw->conf.channel->band; 213 rx_status->band = hw->conf.channel->band;
214 rx_status->freq = hw->conf.channel->center_freq; 214 rx_status->freq = hw->conf.channel->center_freq;
215 rx_status->noise = common->ani.noise_floor;
216 rx_status->signal = ATH_DEFAULT_NOISE_FLOOR + rx_stats->rs_rssi; 215 rx_status->signal = ATH_DEFAULT_NOISE_FLOOR + rx_stats->rs_rssi;
217 rx_status->antenna = rx_stats->rs_antenna; 216 rx_status->antenna = rx_stats->rs_antenna;
218 rx_status->flag |= RX_FLAG_TSFT; 217 rx_status->flag |= RX_FLAG_TSFT;
diff --git a/drivers/net/wireless/ath/ath9k/common.h b/drivers/net/wireless/ath/ath9k/common.h
index 72a835d9e97f..e08f7e5a26e0 100644
--- a/drivers/net/wireless/ath/ath9k/common.h
+++ b/drivers/net/wireless/ath/ath9k/common.h
@@ -20,6 +20,7 @@
20#include "../debug.h" 20#include "../debug.h"
21 21
22#include "hw.h" 22#include "hw.h"
23#include "hw-ops.h"
23 24
24/* Common header for Atheros 802.11n base driver cores */ 25/* Common header for Atheros 802.11n base driver cores */
25 26
@@ -76,11 +77,12 @@ struct ath_buf {
76 an aggregate) */ 77 an aggregate) */
77 struct ath_buf *bf_next; /* next subframe in the aggregate */ 78 struct ath_buf *bf_next; /* next subframe in the aggregate */
78 struct sk_buff *bf_mpdu; /* enclosing frame structure */ 79 struct sk_buff *bf_mpdu; /* enclosing frame structure */
79 struct ath_desc *bf_desc; /* virtual addr of desc */ 80 void *bf_desc; /* virtual addr of desc */
80 dma_addr_t bf_daddr; /* physical addr of desc */ 81 dma_addr_t bf_daddr; /* physical addr of desc */
81 dma_addr_t bf_buf_addr; /* physical addr of data buffer */ 82 dma_addr_t bf_buf_addr; /* physical addr of data buffer */
82 bool bf_stale; 83 bool bf_stale;
83 bool bf_isnullfunc; 84 bool bf_isnullfunc;
85 bool bf_tx_aborted;
84 u16 bf_flags; 86 u16 bf_flags;
85 struct ath_buf_state bf_state; 87 struct ath_buf_state bf_state;
86 dma_addr_t bf_dmacontext; 88 dma_addr_t bf_dmacontext;
diff --git a/drivers/net/wireless/ath/ath9k/debug.c b/drivers/net/wireless/ath/ath9k/debug.c
index 9a8e419398f9..64e30cd45d05 100644
--- a/drivers/net/wireless/ath/ath9k/debug.c
+++ b/drivers/net/wireless/ath/ath9k/debug.c
@@ -180,8 +180,15 @@ void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status)
180{ 180{
181 if (status) 181 if (status)
182 sc->debug.stats.istats.total++; 182 sc->debug.stats.istats.total++;
183 if (status & ATH9K_INT_RX) 183 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
184 sc->debug.stats.istats.rxok++; 184 if (status & ATH9K_INT_RXLP)
185 sc->debug.stats.istats.rxlp++;
186 if (status & ATH9K_INT_RXHP)
187 sc->debug.stats.istats.rxhp++;
188 } else {
189 if (status & ATH9K_INT_RX)
190 sc->debug.stats.istats.rxok++;
191 }
185 if (status & ATH9K_INT_RXEOL) 192 if (status & ATH9K_INT_RXEOL)
186 sc->debug.stats.istats.rxeol++; 193 sc->debug.stats.istats.rxeol++;
187 if (status & ATH9K_INT_RXORN) 194 if (status & ATH9K_INT_RXORN)
@@ -223,8 +230,15 @@ static ssize_t read_file_interrupt(struct file *file, char __user *user_buf,
223 char buf[512]; 230 char buf[512];
224 unsigned int len = 0; 231 unsigned int len = 0;
225 232
226 len += snprintf(buf + len, sizeof(buf) - len, 233 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
227 "%8s: %10u\n", "RX", sc->debug.stats.istats.rxok); 234 len += snprintf(buf + len, sizeof(buf) - len,
235 "%8s: %10u\n", "RXLP", sc->debug.stats.istats.rxlp);
236 len += snprintf(buf + len, sizeof(buf) - len,
237 "%8s: %10u\n", "RXHP", sc->debug.stats.istats.rxhp);
238 } else {
239 len += snprintf(buf + len, sizeof(buf) - len,
240 "%8s: %10u\n", "RX", sc->debug.stats.istats.rxok);
241 }
228 len += snprintf(buf + len, sizeof(buf) - len, 242 len += snprintf(buf + len, sizeof(buf) - len,
229 "%8s: %10u\n", "RXEOL", sc->debug.stats.istats.rxeol); 243 "%8s: %10u\n", "RXEOL", sc->debug.stats.istats.rxeol);
230 len += snprintf(buf + len, sizeof(buf) - len, 244 len += snprintf(buf + len, sizeof(buf) - len,
diff --git a/drivers/net/wireless/ath/ath9k/debug.h b/drivers/net/wireless/ath/ath9k/debug.h
index b2af9de755e6..c545960e7ec5 100644
--- a/drivers/net/wireless/ath/ath9k/debug.h
+++ b/drivers/net/wireless/ath/ath9k/debug.h
@@ -35,6 +35,8 @@ struct ath_buf;
35 * struct ath_interrupt_stats - Contains statistics about interrupts 35 * struct ath_interrupt_stats - Contains statistics about interrupts
36 * @total: Total no. of interrupts generated so far 36 * @total: Total no. of interrupts generated so far
37 * @rxok: RX with no errors 37 * @rxok: RX with no errors
38 * @rxlp: RX with low priority RX
39 * @rxhp: RX with high priority, uapsd only
38 * @rxeol: RX with no more RXDESC available 40 * @rxeol: RX with no more RXDESC available
39 * @rxorn: RX FIFO overrun 41 * @rxorn: RX FIFO overrun
40 * @txok: TX completed at the requested rate 42 * @txok: TX completed at the requested rate
@@ -55,6 +57,8 @@ struct ath_buf;
55struct ath_interrupt_stats { 57struct ath_interrupt_stats {
56 u32 total; 58 u32 total;
57 u32 rxok; 59 u32 rxok;
60 u32 rxlp;
61 u32 rxhp;
58 u32 rxeol; 62 u32 rxeol;
59 u32 rxorn; 63 u32 rxorn;
60 u32 txok; 64 u32 txok;
diff --git a/drivers/net/wireless/ath/ath9k/eeprom.c b/drivers/net/wireless/ath/ath9k/eeprom.c
index dacaae934148..bd9dff3293dc 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom.c
@@ -256,14 +256,13 @@ int ath9k_hw_eeprom_init(struct ath_hw *ah)
256{ 256{
257 int status; 257 int status;
258 258
259 if (AR_SREV_9287(ah)) { 259 if (AR_SREV_9300_20_OR_LATER(ah))
260 ah->eep_map = EEP_MAP_AR9287; 260 ah->eep_ops = &eep_ar9300_ops;
261 ah->eep_ops = &eep_AR9287_ops; 261 else if (AR_SREV_9287(ah)) {
262 ah->eep_ops = &eep_ar9287_ops;
262 } else if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) { 263 } else if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) {
263 ah->eep_map = EEP_MAP_4KBITS;
264 ah->eep_ops = &eep_4k_ops; 264 ah->eep_ops = &eep_4k_ops;
265 } else { 265 } else {
266 ah->eep_map = EEP_MAP_DEFAULT;
267 ah->eep_ops = &eep_def_ops; 266 ah->eep_ops = &eep_def_ops;
268 } 267 }
269 268
diff --git a/drivers/net/wireless/ath/ath9k/eeprom.h b/drivers/net/wireless/ath/ath9k/eeprom.h
index 2f2993b50e2f..21354c15a9a9 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom.h
+++ b/drivers/net/wireless/ath/ath9k/eeprom.h
@@ -19,6 +19,7 @@
19 19
20#include "../ath.h" 20#include "../ath.h"
21#include <net/cfg80211.h> 21#include <net/cfg80211.h>
22#include "ar9003_eeprom.h"
22 23
23#define AH_USE_EEPROM 0x1 24#define AH_USE_EEPROM 0x1
24 25
@@ -93,7 +94,6 @@
93 */ 94 */
94#define AR9285_RDEXT_DEFAULT 0x1F 95#define AR9285_RDEXT_DEFAULT 0x1F
95 96
96#define AR_EEPROM_MAC(i) (0x1d+(i))
97#define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s)) 97#define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
98#define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5)) 98#define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
99#define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM)) 99#define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM))
@@ -155,6 +155,7 @@
155#define AR5416_BCHAN_UNUSED 0xFF 155#define AR5416_BCHAN_UNUSED 0xFF
156#define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64 156#define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
157#define AR5416_MAX_CHAINS 3 157#define AR5416_MAX_CHAINS 3
158#define AR9300_MAX_CHAINS 3
158#define AR5416_PWR_TABLE_OFFSET_DB -5 159#define AR5416_PWR_TABLE_OFFSET_DB -5
159 160
160/* Rx gain type values */ 161/* Rx gain type values */
@@ -249,16 +250,20 @@ enum eeprom_param {
249 EEP_MINOR_REV, 250 EEP_MINOR_REV,
250 EEP_TX_MASK, 251 EEP_TX_MASK,
251 EEP_RX_MASK, 252 EEP_RX_MASK,
253 EEP_FSTCLK_5G,
252 EEP_RXGAIN_TYPE, 254 EEP_RXGAIN_TYPE,
253 EEP_TXGAIN_TYPE,
254 EEP_OL_PWRCTRL, 255 EEP_OL_PWRCTRL,
256 EEP_TXGAIN_TYPE,
255 EEP_RC_CHAIN_MASK, 257 EEP_RC_CHAIN_MASK,
256 EEP_DAC_HPWR_5G, 258 EEP_DAC_HPWR_5G,
257 EEP_FRAC_N_5G, 259 EEP_FRAC_N_5G,
258 EEP_DEV_TYPE, 260 EEP_DEV_TYPE,
259 EEP_TEMPSENSE_SLOPE, 261 EEP_TEMPSENSE_SLOPE,
260 EEP_TEMPSENSE_SLOPE_PAL_ON, 262 EEP_TEMPSENSE_SLOPE_PAL_ON,
261 EEP_PWR_TABLE_OFFSET 263 EEP_PWR_TABLE_OFFSET,
264 EEP_DRIVE_STRENGTH,
265 EEP_INTERNAL_REGULATOR,
266 EEP_SWREG
262}; 267};
263 268
264enum ar5416_rates { 269enum ar5416_rates {
@@ -295,7 +300,8 @@ struct base_eep_header {
295 u32 binBuildNumber; 300 u32 binBuildNumber;
296 u8 deviceType; 301 u8 deviceType;
297 u8 pwdclkind; 302 u8 pwdclkind;
298 u8 futureBase_1[2]; 303 u8 fastClk5g;
304 u8 divChain;
299 u8 rxGainType; 305 u8 rxGainType;
300 u8 dacHiPwrMode_5G; 306 u8 dacHiPwrMode_5G;
301 u8 openLoopPwrCntl; 307 u8 openLoopPwrCntl;
@@ -656,13 +662,6 @@ struct ath9k_country_entry {
656 u8 iso[3]; 662 u8 iso[3];
657}; 663};
658 664
659enum ath9k_eep_map {
660 EEP_MAP_DEFAULT = 0x0,
661 EEP_MAP_4KBITS,
662 EEP_MAP_AR9287,
663 EEP_MAP_MAX
664};
665
666struct eeprom_ops { 665struct eeprom_ops {
667 int (*check_eeprom)(struct ath_hw *hw); 666 int (*check_eeprom)(struct ath_hw *hw);
668 u32 (*get_eeprom)(struct ath_hw *hw, enum eeprom_param param); 667 u32 (*get_eeprom)(struct ath_hw *hw, enum eeprom_param param);
@@ -713,6 +712,8 @@ int ath9k_hw_eeprom_init(struct ath_hw *ah);
713 712
714extern const struct eeprom_ops eep_def_ops; 713extern const struct eeprom_ops eep_def_ops;
715extern const struct eeprom_ops eep_4k_ops; 714extern const struct eeprom_ops eep_4k_ops;
716extern const struct eeprom_ops eep_AR9287_ops; 715extern const struct eeprom_ops eep_ar9287_ops;
716extern const struct eeprom_ops eep_ar9287_ops;
717extern const struct eeprom_ops eep_ar9300_ops;
717 718
718#endif /* EEPROM_H */ 719#endif /* EEPROM_H */
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_4k.c b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
index 0354fe50f8e0..41a77d1bd439 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_4k.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
@@ -15,6 +15,7 @@
15 */ 15 */
16 16
17#include "hw.h" 17#include "hw.h"
18#include "ar9002_phy.h"
18 19
19static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah) 20static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah)
20{ 21{
@@ -182,11 +183,11 @@ static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
182 switch (param) { 183 switch (param) {
183 case EEP_NFTHRESH_2: 184 case EEP_NFTHRESH_2:
184 return pModal->noiseFloorThreshCh[0]; 185 return pModal->noiseFloorThreshCh[0];
185 case AR_EEPROM_MAC(0): 186 case EEP_MAC_LSW:
186 return pBase->macAddr[0] << 8 | pBase->macAddr[1]; 187 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
187 case AR_EEPROM_MAC(1): 188 case EEP_MAC_MID:
188 return pBase->macAddr[2] << 8 | pBase->macAddr[3]; 189 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
189 case AR_EEPROM_MAC(2): 190 case EEP_MAC_MSW:
190 return pBase->macAddr[4] << 8 | pBase->macAddr[5]; 191 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
191 case EEP_REG_0: 192 case EEP_REG_0:
192 return pBase->regDmn[0]; 193 return pBase->regDmn[0];
@@ -453,6 +454,8 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
453 &tMinCalPower, gainBoundaries, 454 &tMinCalPower, gainBoundaries,
454 pdadcValues, numXpdGain); 455 pdadcValues, numXpdGain);
455 456
457 ENABLE_REGWRITE_BUFFER(ah);
458
456 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) { 459 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
457 REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset, 460 REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,
458 SM(pdGainOverlap_t2, 461 SM(pdGainOverlap_t2,
@@ -493,6 +496,9 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
493 496
494 regOffset += 4; 497 regOffset += 4;
495 } 498 }
499
500 REGWRITE_BUFFER_FLUSH(ah);
501 DISABLE_REGWRITE_BUFFER(ah);
496 } 502 }
497 } 503 }
498 504
@@ -758,6 +764,8 @@ static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
758 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2; 764 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2;
759 } 765 }
760 766
767 ENABLE_REGWRITE_BUFFER(ah);
768
761 /* OFDM power per rate */ 769 /* OFDM power per rate */
762 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, 770 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
763 ATH9K_POW_SM(ratesArray[rate18mb], 24) 771 ATH9K_POW_SM(ratesArray[rate18mb], 24)
@@ -820,6 +828,9 @@ static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
820 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8) 828 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
821 | ATH9K_POW_SM(ratesArray[rateDupCck], 0)); 829 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
822 } 830 }
831
832 REGWRITE_BUFFER_FLUSH(ah);
833 DISABLE_REGWRITE_BUFFER(ah);
823} 834}
824 835
825static void ath9k_hw_4k_set_addac(struct ath_hw *ah, 836static void ath9k_hw_4k_set_addac(struct ath_hw *ah,
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_9287.c b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
index d8ca94c3fa0c..b471db5fb82d 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_9287.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
@@ -15,6 +15,7 @@
15 */ 15 */
16 16
17#include "hw.h" 17#include "hw.h"
18#include "ar9002_phy.h"
18 19
19static int ath9k_hw_AR9287_get_eeprom_ver(struct ath_hw *ah) 20static int ath9k_hw_AR9287_get_eeprom_ver(struct ath_hw *ah)
20{ 21{
@@ -172,11 +173,11 @@ static u32 ath9k_hw_AR9287_get_eeprom(struct ath_hw *ah,
172 switch (param) { 173 switch (param) {
173 case EEP_NFTHRESH_2: 174 case EEP_NFTHRESH_2:
174 return pModal->noiseFloorThreshCh[0]; 175 return pModal->noiseFloorThreshCh[0];
175 case AR_EEPROM_MAC(0): 176 case EEP_MAC_LSW:
176 return pBase->macAddr[0] << 8 | pBase->macAddr[1]; 177 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
177 case AR_EEPROM_MAC(1): 178 case EEP_MAC_MID:
178 return pBase->macAddr[2] << 8 | pBase->macAddr[3]; 179 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
179 case AR_EEPROM_MAC(2): 180 case EEP_MAC_MSW:
180 return pBase->macAddr[4] << 8 | pBase->macAddr[5]; 181 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
181 case EEP_REG_0: 182 case EEP_REG_0:
182 return pBase->regDmn[0]; 183 return pBase->regDmn[0];
@@ -1169,7 +1170,7 @@ static u16 ath9k_hw_AR9287_get_spur_channel(struct ath_hw *ah,
1169#undef EEP_MAP9287_SPURCHAN 1170#undef EEP_MAP9287_SPURCHAN
1170} 1171}
1171 1172
1172const struct eeprom_ops eep_AR9287_ops = { 1173const struct eeprom_ops eep_ar9287_ops = {
1173 .check_eeprom = ath9k_hw_AR9287_check_eeprom, 1174 .check_eeprom = ath9k_hw_AR9287_check_eeprom,
1174 .get_eeprom = ath9k_hw_AR9287_get_eeprom, 1175 .get_eeprom = ath9k_hw_AR9287_get_eeprom,
1175 .fill_eeprom = ath9k_hw_AR9287_fill_eeprom, 1176 .fill_eeprom = ath9k_hw_AR9287_fill_eeprom,
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_def.c b/drivers/net/wireless/ath/ath9k/eeprom_def.c
index 404a0341242c..e591ad6016e5 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_def.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_def.c
@@ -15,6 +15,7 @@
15 */ 15 */
16 16
17#include "hw.h" 17#include "hw.h"
18#include "ar9002_phy.h"
18 19
19static void ath9k_get_txgain_index(struct ath_hw *ah, 20static void ath9k_get_txgain_index(struct ath_hw *ah,
20 struct ath9k_channel *chan, 21 struct ath9k_channel *chan,
@@ -222,6 +223,12 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
222 return -EINVAL; 223 return -EINVAL;
223 } 224 }
224 225
226 /* Enable fixup for AR_AN_TOP2 if necessary */
227 if (AR_SREV_9280_10_OR_LATER(ah) &&
228 (eep->baseEepHeader.version & 0xff) > 0x0a &&
229 eep->baseEepHeader.pwdclkind == 0)
230 ah->need_an_top2_fixup = 1;
231
225 return 0; 232 return 0;
226} 233}
227 234
@@ -237,11 +244,11 @@ static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
237 return pModal[0].noiseFloorThreshCh[0]; 244 return pModal[0].noiseFloorThreshCh[0];
238 case EEP_NFTHRESH_2: 245 case EEP_NFTHRESH_2:
239 return pModal[1].noiseFloorThreshCh[0]; 246 return pModal[1].noiseFloorThreshCh[0];
240 case AR_EEPROM_MAC(0): 247 case EEP_MAC_LSW:
241 return pBase->macAddr[0] << 8 | pBase->macAddr[1]; 248 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
242 case AR_EEPROM_MAC(1): 249 case EEP_MAC_MID:
243 return pBase->macAddr[2] << 8 | pBase->macAddr[3]; 250 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
244 case AR_EEPROM_MAC(2): 251 case EEP_MAC_MSW:
245 return pBase->macAddr[4] << 8 | pBase->macAddr[5]; 252 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
246 case EEP_REG_0: 253 case EEP_REG_0:
247 return pBase->regDmn[0]; 254 return pBase->regDmn[0];
@@ -267,6 +274,8 @@ static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
267 return pBase->txMask; 274 return pBase->txMask;
268 case EEP_RX_MASK: 275 case EEP_RX_MASK:
269 return pBase->rxMask; 276 return pBase->rxMask;
277 case EEP_FSTCLK_5G:
278 return pBase->fastClk5g;
270 case EEP_RXGAIN_TYPE: 279 case EEP_RXGAIN_TYPE:
271 return pBase->rxGainType; 280 return pBase->rxGainType;
272 case EEP_TXGAIN_TYPE: 281 case EEP_TXGAIN_TYPE:
diff --git a/drivers/net/wireless/ath/ath9k/hif_usb.c b/drivers/net/wireless/ath/ath9k/hif_usb.c
index fe994e229898..74872ca76f9a 100644
--- a/drivers/net/wireless/ath/ath9k/hif_usb.c
+++ b/drivers/net/wireless/ath/ath9k/hif_usb.c
@@ -93,14 +93,24 @@ static int hif_usb_send_regout(struct hif_device_usb *hif_dev,
93 return ret; 93 return ret;
94} 94}
95 95
96static inline void ath9k_skb_queue_purge(struct hif_device_usb *hif_dev,
97 struct sk_buff_head *list)
98{
99 struct sk_buff *skb;
100
101 while ((skb = __skb_dequeue(list)) != NULL) {
102 dev_kfree_skb_any(skb);
103 TX_STAT_INC(skb_dropped);
104 }
105}
106
96static void hif_usb_tx_cb(struct urb *urb) 107static void hif_usb_tx_cb(struct urb *urb)
97{ 108{
98 struct tx_buf *tx_buf = (struct tx_buf *) urb->context; 109 struct tx_buf *tx_buf = (struct tx_buf *) urb->context;
99 struct hif_device_usb *hif_dev = tx_buf->hif_dev; 110 struct hif_device_usb *hif_dev = tx_buf->hif_dev;
100 struct sk_buff *skb; 111 struct sk_buff *skb;
101 bool drop, flush;
102 112
103 if (!hif_dev) 113 if (!hif_dev || !tx_buf)
104 return; 114 return;
105 115
106 switch (urb->status) { 116 switch (urb->status) {
@@ -108,52 +118,47 @@ static void hif_usb_tx_cb(struct urb *urb)
108 break; 118 break;
109 case -ENOENT: 119 case -ENOENT:
110 case -ECONNRESET: 120 case -ECONNRESET:
111 break;
112 case -ENODEV: 121 case -ENODEV:
113 case -ESHUTDOWN: 122 case -ESHUTDOWN:
123 /*
124 * The URB has been killed, free the SKBs
125 * and return.
126 */
127 ath9k_skb_queue_purge(hif_dev, &tx_buf->skb_queue);
114 return; 128 return;
115 default: 129 default:
116 break; 130 break;
117 } 131 }
118 132
119 if (tx_buf) { 133 /* Check if TX has been stopped */
120 spin_lock(&hif_dev->tx.tx_lock); 134 spin_lock(&hif_dev->tx.tx_lock);
121 drop = !!(hif_dev->tx.flags & HIF_USB_TX_STOP); 135 if (hif_dev->tx.flags & HIF_USB_TX_STOP) {
122 flush = !!(hif_dev->tx.flags & HIF_USB_TX_FLUSH);
123 spin_unlock(&hif_dev->tx.tx_lock);
124
125 while ((skb = __skb_dequeue(&tx_buf->skb_queue)) != NULL) {
126 if (!drop && !flush) {
127 ath9k_htc_txcompletion_cb(hif_dev->htc_handle,
128 skb, 1);
129 TX_STAT_INC(skb_completed);
130 } else {
131 dev_kfree_skb_any(skb);
132 }
133 }
134
135 if (flush)
136 return;
137
138 tx_buf->len = tx_buf->offset = 0;
139 __skb_queue_head_init(&tx_buf->skb_queue);
140
141 spin_lock(&hif_dev->tx.tx_lock);
142 list_del(&tx_buf->list);
143 list_add_tail(&tx_buf->list, &hif_dev->tx.tx_buf);
144 hif_dev->tx.tx_buf_cnt++;
145 if (!drop)
146 __hif_usb_tx(hif_dev); /* Check for pending SKBs */
147 TX_STAT_INC(buf_completed);
148 spin_unlock(&hif_dev->tx.tx_lock); 136 spin_unlock(&hif_dev->tx.tx_lock);
149 } 137 ath9k_skb_queue_purge(hif_dev, &tx_buf->skb_queue);
150} 138 goto add_free;
151 139 }
152static inline void ath9k_skb_queue_purge(struct sk_buff_head *list) 140 spin_unlock(&hif_dev->tx.tx_lock);
153{ 141
154 struct sk_buff *skb; 142 /* Complete the queued SKBs. */
155 while ((skb = __skb_dequeue(list)) != NULL) 143 while ((skb = __skb_dequeue(&tx_buf->skb_queue)) != NULL) {
156 dev_kfree_skb_any(skb); 144 ath9k_htc_txcompletion_cb(hif_dev->htc_handle,
145 skb, 1);
146 TX_STAT_INC(skb_completed);
147 }
148
149add_free:
150 /* Re-initialize the SKB queue */
151 tx_buf->len = tx_buf->offset = 0;
152 __skb_queue_head_init(&tx_buf->skb_queue);
153
154 /* Add this TX buffer to the free list */
155 spin_lock(&hif_dev->tx.tx_lock);
156 list_move_tail(&tx_buf->list, &hif_dev->tx.tx_buf);
157 hif_dev->tx.tx_buf_cnt++;
158 if (!(hif_dev->tx.flags & HIF_USB_TX_STOP))
159 __hif_usb_tx(hif_dev); /* Check for pending SKBs */
160 TX_STAT_INC(buf_completed);
161 spin_unlock(&hif_dev->tx.tx_lock);
157} 162}
158 163
159/* TX lock has to be taken */ 164/* TX lock has to be taken */
@@ -173,8 +178,7 @@ static int __hif_usb_tx(struct hif_device_usb *hif_dev)
173 return 0; 178 return 0;
174 179
175 tx_buf = list_first_entry(&hif_dev->tx.tx_buf, struct tx_buf, list); 180 tx_buf = list_first_entry(&hif_dev->tx.tx_buf, struct tx_buf, list);
176 list_del(&tx_buf->list); 181 list_move_tail(&tx_buf->list, &hif_dev->tx.tx_pending);
177 list_add_tail(&tx_buf->list, &hif_dev->tx.tx_pending);
178 hif_dev->tx.tx_buf_cnt--; 182 hif_dev->tx.tx_buf_cnt--;
179 183
180 tx_skb_cnt = min_t(u16, hif_dev->tx.tx_skb_cnt, MAX_TX_AGGR_NUM); 184 tx_skb_cnt = min_t(u16, hif_dev->tx.tx_skb_cnt, MAX_TX_AGGR_NUM);
@@ -214,7 +218,7 @@ static int __hif_usb_tx(struct hif_device_usb *hif_dev)
214 ret = usb_submit_urb(tx_buf->urb, GFP_ATOMIC); 218 ret = usb_submit_urb(tx_buf->urb, GFP_ATOMIC);
215 if (ret) { 219 if (ret) {
216 tx_buf->len = tx_buf->offset = 0; 220 tx_buf->len = tx_buf->offset = 0;
217 ath9k_skb_queue_purge(&tx_buf->skb_queue); 221 ath9k_skb_queue_purge(hif_dev, &tx_buf->skb_queue);
218 __skb_queue_head_init(&tx_buf->skb_queue); 222 __skb_queue_head_init(&tx_buf->skb_queue);
219 list_move_tail(&tx_buf->list, &hif_dev->tx.tx_buf); 223 list_move_tail(&tx_buf->list, &hif_dev->tx.tx_buf);
220 hif_dev->tx.tx_buf_cnt++; 224 hif_dev->tx.tx_buf_cnt++;
@@ -281,7 +285,7 @@ static void hif_usb_stop(void *hif_handle, u8 pipe_id)
281 unsigned long flags; 285 unsigned long flags;
282 286
283 spin_lock_irqsave(&hif_dev->tx.tx_lock, flags); 287 spin_lock_irqsave(&hif_dev->tx.tx_lock, flags);
284 ath9k_skb_queue_purge(&hif_dev->tx.tx_skb_queue); 288 ath9k_skb_queue_purge(hif_dev, &hif_dev->tx.tx_skb_queue);
285 hif_dev->tx.tx_skb_cnt = 0; 289 hif_dev->tx.tx_skb_cnt = 0;
286 hif_dev->tx.flags |= HIF_USB_TX_STOP; 290 hif_dev->tx.flags |= HIF_USB_TX_STOP;
287 spin_unlock_irqrestore(&hif_dev->tx.tx_lock, flags); 291 spin_unlock_irqrestore(&hif_dev->tx.tx_lock, flags);
@@ -506,9 +510,18 @@ static void ath9k_hif_usb_reg_in_cb(struct urb *urb)
506 if (likely(urb->actual_length != 0)) { 510 if (likely(urb->actual_length != 0)) {
507 skb_put(skb, urb->actual_length); 511 skb_put(skb, urb->actual_length);
508 512
513 /* Process the command first */
514 ath9k_htc_rx_msg(hif_dev->htc_handle, skb,
515 skb->len, USB_REG_IN_PIPE);
516
517
509 nskb = alloc_skb(MAX_REG_IN_BUF_SIZE, GFP_ATOMIC); 518 nskb = alloc_skb(MAX_REG_IN_BUF_SIZE, GFP_ATOMIC);
510 if (!nskb) 519 if (!nskb) {
511 goto resubmit; 520 dev_err(&hif_dev->udev->dev,
521 "ath9k_htc: REG_IN memory allocation failure\n");
522 urb->context = NULL;
523 return;
524 }
512 525
513 usb_fill_int_urb(urb, hif_dev->udev, 526 usb_fill_int_urb(urb, hif_dev->udev,
514 usb_rcvintpipe(hif_dev->udev, USB_REG_IN_PIPE), 527 usb_rcvintpipe(hif_dev->udev, USB_REG_IN_PIPE),
@@ -518,12 +531,9 @@ static void ath9k_hif_usb_reg_in_cb(struct urb *urb)
518 ret = usb_submit_urb(urb, GFP_ATOMIC); 531 ret = usb_submit_urb(urb, GFP_ATOMIC);
519 if (ret) { 532 if (ret) {
520 kfree_skb(nskb); 533 kfree_skb(nskb);
521 goto free; 534 urb->context = NULL;
522 } 535 }
523 536
524 ath9k_htc_rx_msg(hif_dev->htc_handle, skb,
525 skb->len, USB_REG_IN_PIPE);
526
527 return; 537 return;
528 } 538 }
529 539
@@ -543,20 +553,17 @@ free:
543 553
544static void ath9k_hif_usb_dealloc_tx_urbs(struct hif_device_usb *hif_dev) 554static void ath9k_hif_usb_dealloc_tx_urbs(struct hif_device_usb *hif_dev)
545{ 555{
546 unsigned long flags;
547 struct tx_buf *tx_buf = NULL, *tx_buf_tmp = NULL; 556 struct tx_buf *tx_buf = NULL, *tx_buf_tmp = NULL;
548 557
549 list_for_each_entry_safe(tx_buf, tx_buf_tmp, &hif_dev->tx.tx_buf, list) { 558 list_for_each_entry_safe(tx_buf, tx_buf_tmp,
559 &hif_dev->tx.tx_buf, list) {
560 usb_kill_urb(tx_buf->urb);
550 list_del(&tx_buf->list); 561 list_del(&tx_buf->list);
551 usb_free_urb(tx_buf->urb); 562 usb_free_urb(tx_buf->urb);
552 kfree(tx_buf->buf); 563 kfree(tx_buf->buf);
553 kfree(tx_buf); 564 kfree(tx_buf);
554 } 565 }
555 566
556 spin_lock_irqsave(&hif_dev->tx.tx_lock, flags);
557 hif_dev->tx.flags |= HIF_USB_TX_FLUSH;
558 spin_unlock_irqrestore(&hif_dev->tx.tx_lock, flags);
559
560 list_for_each_entry_safe(tx_buf, tx_buf_tmp, 567 list_for_each_entry_safe(tx_buf, tx_buf_tmp,
561 &hif_dev->tx.tx_pending, list) { 568 &hif_dev->tx.tx_pending, list) {
562 usb_kill_urb(tx_buf->urb); 569 usb_kill_urb(tx_buf->urb);
@@ -565,10 +572,6 @@ static void ath9k_hif_usb_dealloc_tx_urbs(struct hif_device_usb *hif_dev)
565 kfree(tx_buf->buf); 572 kfree(tx_buf->buf);
566 kfree(tx_buf); 573 kfree(tx_buf);
567 } 574 }
568
569 spin_lock_irqsave(&hif_dev->tx.tx_lock, flags);
570 hif_dev->tx.flags &= ~HIF_USB_TX_FLUSH;
571 spin_unlock_irqrestore(&hif_dev->tx.tx_lock, flags);
572} 575}
573 576
574static int ath9k_hif_usb_alloc_tx_urbs(struct hif_device_usb *hif_dev) 577static int ath9k_hif_usb_alloc_tx_urbs(struct hif_device_usb *hif_dev)
@@ -892,6 +895,26 @@ err_alloc:
892 return ret; 895 return ret;
893} 896}
894 897
898static void ath9k_hif_usb_reboot(struct usb_device *udev)
899{
900 u32 reboot_cmd = 0xffffffff;
901 void *buf;
902 int ret;
903
904 buf = kmalloc(4, GFP_KERNEL);
905 if (!buf)
906 return;
907
908 memcpy(buf, &reboot_cmd, 4);
909
910 ret = usb_bulk_msg(udev, usb_sndbulkpipe(udev, USB_REG_OUT_PIPE),
911 buf, 4, NULL, HZ);
912 if (ret)
913 dev_err(&udev->dev, "ath9k_htc: USB reboot failed\n");
914
915 kfree(buf);
916}
917
895static void ath9k_hif_usb_disconnect(struct usb_interface *interface) 918static void ath9k_hif_usb_disconnect(struct usb_interface *interface)
896{ 919{
897 struct usb_device *udev = interface_to_usbdev(interface); 920 struct usb_device *udev = interface_to_usbdev(interface);
@@ -899,14 +922,15 @@ static void ath9k_hif_usb_disconnect(struct usb_interface *interface)
899 (struct hif_device_usb *) usb_get_intfdata(interface); 922 (struct hif_device_usb *) usb_get_intfdata(interface);
900 923
901 if (hif_dev) { 924 if (hif_dev) {
902 ath9k_htc_hw_deinit(hif_dev->htc_handle, true); 925 ath9k_htc_hw_deinit(hif_dev->htc_handle,
926 (udev->state == USB_STATE_NOTATTACHED) ? true : false);
903 ath9k_htc_hw_free(hif_dev->htc_handle); 927 ath9k_htc_hw_free(hif_dev->htc_handle);
904 ath9k_hif_usb_dev_deinit(hif_dev); 928 ath9k_hif_usb_dev_deinit(hif_dev);
905 usb_set_intfdata(interface, NULL); 929 usb_set_intfdata(interface, NULL);
906 } 930 }
907 931
908 if (hif_dev->flags & HIF_USB_START) 932 if (hif_dev->flags & HIF_USB_START)
909 usb_reset_device(udev); 933 ath9k_hif_usb_reboot(udev);
910 934
911 kfree(hif_dev); 935 kfree(hif_dev);
912 dev_info(&udev->dev, "ath9k_htc: USB layer deinitialized\n"); 936 dev_info(&udev->dev, "ath9k_htc: USB layer deinitialized\n");
diff --git a/drivers/net/wireless/ath/ath9k/hif_usb.h b/drivers/net/wireless/ath/ath9k/hif_usb.h
index 7d49a8af420e..0aca49b6fcb6 100644
--- a/drivers/net/wireless/ath/ath9k/hif_usb.h
+++ b/drivers/net/wireless/ath/ath9k/hif_usb.h
@@ -61,7 +61,6 @@ struct tx_buf {
61}; 61};
62 62
63#define HIF_USB_TX_STOP BIT(0) 63#define HIF_USB_TX_STOP BIT(0)
64#define HIF_USB_TX_FLUSH BIT(1)
65 64
66struct hif_usb_tx { 65struct hif_usb_tx {
67 u8 flags; 66 u8 flags;
diff --git a/drivers/net/wireless/ath/ath9k/htc.h b/drivers/net/wireless/ath/ath9k/htc.h
index 78213fc71b09..1ae18bbc4d9e 100644
--- a/drivers/net/wireless/ath/ath9k/htc.h
+++ b/drivers/net/wireless/ath/ath9k/htc.h
@@ -124,13 +124,13 @@ struct ath9k_htc_cap_target {
124struct ath9k_htc_target_vif { 124struct ath9k_htc_target_vif {
125 u8 index; 125 u8 index;
126 u8 des_bssid[ETH_ALEN]; 126 u8 des_bssid[ETH_ALEN];
127 enum htc_opmode opmode; 127 __be32 opmode;
128 u8 myaddr[ETH_ALEN]; 128 u8 myaddr[ETH_ALEN];
129 u8 bssid[ETH_ALEN]; 129 u8 bssid[ETH_ALEN];
130 u32 flags; 130 u32 flags;
131 u32 flags_ext; 131 u32 flags_ext;
132 u16 ps_sta; 132 u16 ps_sta;
133 u16 rtsthreshold; 133 __be16 rtsthreshold;
134 u8 ath_cap; 134 u8 ath_cap;
135 u8 node; 135 u8 node;
136 s8 mcast_rate; 136 s8 mcast_rate;
@@ -151,7 +151,7 @@ struct ath9k_htc_target_sta {
151 u8 sta_index; 151 u8 sta_index;
152 u8 vif_index; 152 u8 vif_index;
153 u8 vif_sta; 153 u8 vif_sta;
154 u16 flags; /* ATH_HTC_STA_* */ 154 __be16 flags; /* ATH_HTC_STA_* */
155 u16 htcap; 155 u16 htcap;
156 u8 valid; 156 u8 valid;
157 u16 capinfo; 157 u16 capinfo;
@@ -191,16 +191,16 @@ struct ath9k_htc_rate {
191struct ath9k_htc_target_rate { 191struct ath9k_htc_target_rate {
192 u8 sta_index; 192 u8 sta_index;
193 u8 isnew; 193 u8 isnew;
194 u32 capflags; 194 __be32 capflags;
195 struct ath9k_htc_rate rates; 195 struct ath9k_htc_rate rates;
196}; 196};
197 197
198struct ath9k_htc_target_stats { 198struct ath9k_htc_target_stats {
199 u32 tx_shortretry; 199 __be32 tx_shortretry;
200 u32 tx_longretry; 200 __be32 tx_longretry;
201 u32 tx_xretries; 201 __be32 tx_xretries;
202 u32 ht_txunaggr_xretry; 202 __be32 ht_txunaggr_xretry;
203 u32 ht_tx_xretries; 203 __be32 ht_tx_xretries;
204} __packed; 204} __packed;
205 205
206struct ath9k_htc_vif { 206struct ath9k_htc_vif {
@@ -261,6 +261,7 @@ struct ath_tx_stats {
261 u32 buf_completed; 261 u32 buf_completed;
262 u32 skb_queued; 262 u32 skb_queued;
263 u32 skb_completed; 263 u32 skb_completed;
264 u32 skb_dropped;
264}; 265};
265 266
266struct ath_rx_stats { 267struct ath_rx_stats {
@@ -328,6 +329,7 @@ struct htc_beacon_config {
328#define OP_ASSOCIATED BIT(8) 329#define OP_ASSOCIATED BIT(8)
329#define OP_ENABLE_BEACON BIT(9) 330#define OP_ENABLE_BEACON BIT(9)
330#define OP_LED_DEINIT BIT(10) 331#define OP_LED_DEINIT BIT(10)
332#define OP_UNPLUGGED BIT(11)
331 333
332struct ath9k_htc_priv { 334struct ath9k_htc_priv {
333 struct device *dev; 335 struct device *dev;
@@ -377,6 +379,7 @@ struct ath9k_htc_priv {
377 struct mutex htc_pm_lock; 379 struct mutex htc_pm_lock;
378 unsigned long ps_usecount; 380 unsigned long ps_usecount;
379 bool ps_enabled; 381 bool ps_enabled;
382 bool ps_idle;
380 383
381 struct ath_led radio_led; 384 struct ath_led radio_led;
382 struct ath_led assoc_led; 385 struct ath_led assoc_led;
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c b/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c
index 5e21f4d92ff5..7cb55f5b071c 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c
@@ -26,7 +26,8 @@ static void ath9k_htc_beacon_config_sta(struct ath9k_htc_priv *priv,
26 enum ath9k_int imask = 0; 26 enum ath9k_int imask = 0;
27 int dtimperiod, dtimcount, sleepduration; 27 int dtimperiod, dtimcount, sleepduration;
28 int cfpperiod, cfpcount, bmiss_timeout; 28 int cfpperiod, cfpcount, bmiss_timeout;
29 u32 nexttbtt = 0, intval, tsftu, htc_imask = 0; 29 u32 nexttbtt = 0, intval, tsftu;
30 __be32 htc_imask = 0;
30 u64 tsf; 31 u64 tsf;
31 int num_beacons, offset, dtim_dec_count, cfp_dec_count; 32 int num_beacons, offset, dtim_dec_count, cfp_dec_count;
32 int ret; 33 int ret;
@@ -142,7 +143,8 @@ static void ath9k_htc_beacon_config_adhoc(struct ath9k_htc_priv *priv,
142{ 143{
143 struct ath_common *common = ath9k_hw_common(priv->ah); 144 struct ath_common *common = ath9k_hw_common(priv->ah);
144 enum ath9k_int imask = 0; 145 enum ath9k_int imask = 0;
145 u32 nexttbtt, intval, htc_imask = 0; 146 u32 nexttbtt, intval;
147 __be32 htc_imask = 0;
146 int ret; 148 int ret;
147 u8 cmd_rsp; 149 u8 cmd_rsp;
148 150
@@ -244,25 +246,20 @@ void ath9k_htc_beacon_config(struct ath9k_htc_priv *priv,
244 struct ieee80211_vif *vif) 246 struct ieee80211_vif *vif)
245{ 247{
246 struct ath_common *common = ath9k_hw_common(priv->ah); 248 struct ath_common *common = ath9k_hw_common(priv->ah);
247 enum nl80211_iftype iftype;
248 struct htc_beacon_config *cur_conf = &priv->cur_beacon_conf; 249 struct htc_beacon_config *cur_conf = &priv->cur_beacon_conf;
250 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
249 251
250 if (vif) { 252 cur_conf->beacon_interval = bss_conf->beacon_int;
251 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
252 iftype = vif->type;
253 cur_conf->beacon_interval = bss_conf->beacon_int;
254 cur_conf->dtim_period = bss_conf->dtim_period;
255 cur_conf->listen_interval = 1;
256 cur_conf->dtim_count = 1;
257 cur_conf->bmiss_timeout =
258 ATH_DEFAULT_BMISS_LIMIT * cur_conf->beacon_interval;
259 } else
260 iftype = priv->ah->opmode;
261
262 if (cur_conf->beacon_interval == 0) 253 if (cur_conf->beacon_interval == 0)
263 cur_conf->beacon_interval = 100; 254 cur_conf->beacon_interval = 100;
264 255
265 switch (iftype) { 256 cur_conf->dtim_period = bss_conf->dtim_period;
257 cur_conf->listen_interval = 1;
258 cur_conf->dtim_count = 1;
259 cur_conf->bmiss_timeout =
260 ATH_DEFAULT_BMISS_LIMIT * cur_conf->beacon_interval;
261
262 switch (vif->type) {
266 case NL80211_IFTYPE_STATION: 263 case NL80211_IFTYPE_STATION:
267 ath9k_htc_beacon_config_sta(priv, cur_conf); 264 ath9k_htc_beacon_config_sta(priv, cur_conf);
268 break; 265 break;
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_init.c b/drivers/net/wireless/ath/ath9k/htc_drv_init.c
index aed53573c547..701f2ef5a440 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_init.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_init.c
@@ -213,7 +213,7 @@ static int ath9k_reg_notifier(struct wiphy *wiphy,
213 ath9k_hw_regulatory(priv->ah)); 213 ath9k_hw_regulatory(priv->ah));
214} 214}
215 215
216static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset) 216static unsigned int ath9k_regread(void *hw_priv, u32 reg_offset)
217{ 217{
218 struct ath_hw *ah = (struct ath_hw *) hw_priv; 218 struct ath_hw *ah = (struct ath_hw *) hw_priv;
219 struct ath_common *common = ath9k_hw_common(ah); 219 struct ath_common *common = ath9k_hw_common(ah);
@@ -235,7 +235,7 @@ static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
235 return be32_to_cpu(val); 235 return be32_to_cpu(val);
236} 236}
237 237
238static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) 238static void ath9k_regwrite_single(void *hw_priv, u32 val, u32 reg_offset)
239{ 239{
240 struct ath_hw *ah = (struct ath_hw *) hw_priv; 240 struct ath_hw *ah = (struct ath_hw *) hw_priv;
241 struct ath_common *common = ath9k_hw_common(ah); 241 struct ath_common *common = ath9k_hw_common(ah);
@@ -257,9 +257,105 @@ static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
257 } 257 }
258} 258}
259 259
260static void ath9k_regwrite_buffer(void *hw_priv, u32 val, u32 reg_offset)
261{
262 struct ath_hw *ah = (struct ath_hw *) hw_priv;
263 struct ath_common *common = ath9k_hw_common(ah);
264 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
265 u32 rsp_status;
266 int r;
267
268 mutex_lock(&priv->wmi->multi_write_mutex);
269
270 /* Store the register/value */
271 priv->wmi->multi_write[priv->wmi->multi_write_idx].reg =
272 cpu_to_be32(reg_offset);
273 priv->wmi->multi_write[priv->wmi->multi_write_idx].val =
274 cpu_to_be32(val);
275
276 priv->wmi->multi_write_idx++;
277
278 /* If the buffer is full, send it out. */
279 if (priv->wmi->multi_write_idx == MAX_CMD_NUMBER) {
280 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
281 (u8 *) &priv->wmi->multi_write,
282 sizeof(struct register_write) * priv->wmi->multi_write_idx,
283 (u8 *) &rsp_status, sizeof(rsp_status),
284 100);
285 if (unlikely(r)) {
286 ath_print(common, ATH_DBG_WMI,
287 "REGISTER WRITE FAILED, multi len: %d\n",
288 priv->wmi->multi_write_idx);
289 }
290 priv->wmi->multi_write_idx = 0;
291 }
292
293 mutex_unlock(&priv->wmi->multi_write_mutex);
294}
295
296static void ath9k_regwrite(void *hw_priv, u32 val, u32 reg_offset)
297{
298 struct ath_hw *ah = (struct ath_hw *) hw_priv;
299 struct ath_common *common = ath9k_hw_common(ah);
300 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
301
302 if (atomic_read(&priv->wmi->mwrite_cnt))
303 ath9k_regwrite_buffer(hw_priv, val, reg_offset);
304 else
305 ath9k_regwrite_single(hw_priv, val, reg_offset);
306}
307
308static void ath9k_enable_regwrite_buffer(void *hw_priv)
309{
310 struct ath_hw *ah = (struct ath_hw *) hw_priv;
311 struct ath_common *common = ath9k_hw_common(ah);
312 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
313
314 atomic_inc(&priv->wmi->mwrite_cnt);
315}
316
317static void ath9k_disable_regwrite_buffer(void *hw_priv)
318{
319 struct ath_hw *ah = (struct ath_hw *) hw_priv;
320 struct ath_common *common = ath9k_hw_common(ah);
321 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
322
323 atomic_dec(&priv->wmi->mwrite_cnt);
324}
325
326static void ath9k_regwrite_flush(void *hw_priv)
327{
328 struct ath_hw *ah = (struct ath_hw *) hw_priv;
329 struct ath_common *common = ath9k_hw_common(ah);
330 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
331 u32 rsp_status;
332 int r;
333
334 mutex_lock(&priv->wmi->multi_write_mutex);
335
336 if (priv->wmi->multi_write_idx) {
337 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
338 (u8 *) &priv->wmi->multi_write,
339 sizeof(struct register_write) * priv->wmi->multi_write_idx,
340 (u8 *) &rsp_status, sizeof(rsp_status),
341 100);
342 if (unlikely(r)) {
343 ath_print(common, ATH_DBG_WMI,
344 "REGISTER WRITE FAILED, multi len: %d\n",
345 priv->wmi->multi_write_idx);
346 }
347 priv->wmi->multi_write_idx = 0;
348 }
349
350 mutex_unlock(&priv->wmi->multi_write_mutex);
351}
352
260static const struct ath_ops ath9k_common_ops = { 353static const struct ath_ops ath9k_common_ops = {
261 .read = ath9k_ioread32, 354 .read = ath9k_regread,
262 .write = ath9k_iowrite32, 355 .write = ath9k_regwrite,
356 .enable_write_buffer = ath9k_enable_regwrite_buffer,
357 .disable_write_buffer = ath9k_disable_regwrite_buffer,
358 .write_flush = ath9k_regwrite_flush,
263}; 359};
264 360
265static void ath_usb_read_cachesize(struct ath_common *common, int *csz) 361static void ath_usb_read_cachesize(struct ath_common *common, int *csz)
@@ -648,6 +744,9 @@ int ath9k_htc_probe_device(struct htc_target *htc_handle, struct device *dev,
648 if (ret) 744 if (ret)
649 goto err_init; 745 goto err_init;
650 746
747 /* The device may have been unplugged earlier. */
748 priv->op_flags &= ~OP_UNPLUGGED;
749
651 ret = ath9k_init_device(priv, devid); 750 ret = ath9k_init_device(priv, devid);
652 if (ret) 751 if (ret)
653 goto err_init; 752 goto err_init;
@@ -664,6 +763,11 @@ err_free:
664void ath9k_htc_disconnect_device(struct htc_target *htc_handle, bool hotunplug) 763void ath9k_htc_disconnect_device(struct htc_target *htc_handle, bool hotunplug)
665{ 764{
666 if (htc_handle->drv_priv) { 765 if (htc_handle->drv_priv) {
766
767 /* Check if the device has been yanked out. */
768 if (hotunplug)
769 htc_handle->drv_priv->op_flags |= OP_UNPLUGGED;
770
667 ath9k_deinit_device(htc_handle->drv_priv); 771 ath9k_deinit_device(htc_handle->drv_priv);
668 ath9k_deinit_wmi(htc_handle->drv_priv); 772 ath9k_deinit_wmi(htc_handle->drv_priv);
669 ieee80211_free_hw(htc_handle->drv_priv->hw); 773 ieee80211_free_hw(htc_handle->drv_priv->hw);
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_main.c b/drivers/net/wireless/ath/ath9k/htc_drv_main.c
index eb7722b2cfcc..ca7f3a78eb11 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_main.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_main.c
@@ -94,8 +94,11 @@ void ath9k_htc_ps_restore(struct ath9k_htc_priv *priv)
94 if (--priv->ps_usecount != 0) 94 if (--priv->ps_usecount != 0)
95 goto unlock; 95 goto unlock;
96 96
97 if (priv->ps_enabled) 97 if (priv->ps_idle)
98 ath9k_hw_setpower(priv->ah, ATH9K_PM_FULL_SLEEP);
99 else if (priv->ps_enabled)
98 ath9k_hw_setpower(priv->ah, ATH9K_PM_NETWORK_SLEEP); 100 ath9k_hw_setpower(priv->ah, ATH9K_PM_NETWORK_SLEEP);
101
99unlock: 102unlock:
100 mutex_unlock(&priv->htc_pm_lock); 103 mutex_unlock(&priv->htc_pm_lock);
101} 104}
@@ -125,7 +128,7 @@ static int ath9k_htc_set_channel(struct ath9k_htc_priv *priv,
125 bool fastcc = true; 128 bool fastcc = true;
126 struct ieee80211_channel *channel = hw->conf.channel; 129 struct ieee80211_channel *channel = hw->conf.channel;
127 enum htc_phymode mode; 130 enum htc_phymode mode;
128 u16 htc_mode; 131 __be16 htc_mode;
129 u8 cmd_rsp; 132 u8 cmd_rsp;
130 int ret; 133 int ret;
131 134
@@ -153,7 +156,6 @@ static int ath9k_htc_set_channel(struct ath9k_htc_priv *priv,
153 ath_print(common, ATH_DBG_FATAL, 156 ath_print(common, ATH_DBG_FATAL,
154 "Unable to reset channel (%u Mhz) " 157 "Unable to reset channel (%u Mhz) "
155 "reset status %d\n", channel->center_freq, ret); 158 "reset status %d\n", channel->center_freq, ret);
156 ath9k_htc_ps_restore(priv);
157 goto err; 159 goto err;
158 } 160 }
159 161
@@ -378,7 +380,7 @@ static int ath9k_htc_init_rate(struct ath9k_htc_priv *priv,
378 priv->tgt_rate.sta_index = ista->index; 380 priv->tgt_rate.sta_index = ista->index;
379 priv->tgt_rate.isnew = 1; 381 priv->tgt_rate.isnew = 1;
380 trate = priv->tgt_rate; 382 trate = priv->tgt_rate;
381 priv->tgt_rate.capflags = caps; 383 priv->tgt_rate.capflags = cpu_to_be32(caps);
382 trate.capflags = cpu_to_be32(caps); 384 trate.capflags = cpu_to_be32(caps);
383 385
384 WMI_CMD_BUF(WMI_RC_RATE_UPDATE_CMDID, &trate); 386 WMI_CMD_BUF(WMI_RC_RATE_UPDATE_CMDID, &trate);
@@ -426,6 +428,7 @@ static void ath9k_htc_rc_update(struct ath9k_htc_priv *priv, bool is_cw40)
426 struct ath9k_htc_target_rate trate; 428 struct ath9k_htc_target_rate trate;
427 struct ath_common *common = ath9k_hw_common(priv->ah); 429 struct ath_common *common = ath9k_hw_common(priv->ah);
428 int ret; 430 int ret;
431 u32 caps = be32_to_cpu(priv->tgt_rate.capflags);
429 u8 cmd_rsp; 432 u8 cmd_rsp;
430 433
431 memset(&trate, 0, sizeof(trate)); 434 memset(&trate, 0, sizeof(trate));
@@ -433,11 +436,12 @@ static void ath9k_htc_rc_update(struct ath9k_htc_priv *priv, bool is_cw40)
433 trate = priv->tgt_rate; 436 trate = priv->tgt_rate;
434 437
435 if (is_cw40) 438 if (is_cw40)
436 priv->tgt_rate.capflags |= WLAN_RC_40_FLAG; 439 caps |= WLAN_RC_40_FLAG;
437 else 440 else
438 priv->tgt_rate.capflags &= ~WLAN_RC_40_FLAG; 441 caps &= ~WLAN_RC_40_FLAG;
439 442
440 trate.capflags = cpu_to_be32(priv->tgt_rate.capflags); 443 priv->tgt_rate.capflags = cpu_to_be32(caps);
444 trate.capflags = cpu_to_be32(caps);
441 445
442 WMI_CMD_BUF(WMI_RC_RATE_UPDATE_CMDID, &trate); 446 WMI_CMD_BUF(WMI_RC_RATE_UPDATE_CMDID, &trate);
443 if (ret) { 447 if (ret) {
@@ -609,6 +613,9 @@ static ssize_t read_file_xmit(struct file *file, char __user *user_buf,
609 len += snprintf(buf + len, sizeof(buf) - len, 613 len += snprintf(buf + len, sizeof(buf) - len,
610 "%20s : %10u\n", "SKBs completed", 614 "%20s : %10u\n", "SKBs completed",
611 priv->debug.tx_stats.skb_completed); 615 priv->debug.tx_stats.skb_completed);
616 len += snprintf(buf + len, sizeof(buf) - len,
617 "%20s : %10u\n", "SKBs dropped",
618 priv->debug.tx_stats.skb_dropped);
612 619
613 return simple_read_from_buffer(user_buf, count, ppos, buf, len); 620 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
614} 621}
@@ -960,7 +967,6 @@ void ath9k_deinit_leds(struct ath9k_htc_priv *priv)
960 ath9k_unregister_led(&priv->tx_led); 967 ath9k_unregister_led(&priv->tx_led);
961 ath9k_unregister_led(&priv->rx_led); 968 ath9k_unregister_led(&priv->rx_led);
962 ath9k_unregister_led(&priv->radio_led); 969 ath9k_unregister_led(&priv->radio_led);
963 ath9k_hw_set_gpio(priv->ah, priv->ah->led_pin, 1);
964} 970}
965 971
966void ath9k_init_leds(struct ath9k_htc_priv *priv) 972void ath9k_init_leds(struct ath9k_htc_priv *priv)
@@ -1093,7 +1099,7 @@ fail_tx:
1093 return 0; 1099 return 0;
1094} 1100}
1095 1101
1096static int ath9k_htc_start(struct ieee80211_hw *hw) 1102static int ath9k_htc_radio_enable(struct ieee80211_hw *hw)
1097{ 1103{
1098 struct ath9k_htc_priv *priv = hw->priv; 1104 struct ath9k_htc_priv *priv = hw->priv;
1099 struct ath_hw *ah = priv->ah; 1105 struct ath_hw *ah = priv->ah;
@@ -1102,15 +1108,13 @@ static int ath9k_htc_start(struct ieee80211_hw *hw)
1102 struct ath9k_channel *init_channel; 1108 struct ath9k_channel *init_channel;
1103 int ret = 0; 1109 int ret = 0;
1104 enum htc_phymode mode; 1110 enum htc_phymode mode;
1105 u16 htc_mode; 1111 __be16 htc_mode;
1106 u8 cmd_rsp; 1112 u8 cmd_rsp;
1107 1113
1108 ath_print(common, ATH_DBG_CONFIG, 1114 ath_print(common, ATH_DBG_CONFIG,
1109 "Starting driver with initial channel: %d MHz\n", 1115 "Starting driver with initial channel: %d MHz\n",
1110 curchan->center_freq); 1116 curchan->center_freq);
1111 1117
1112 mutex_lock(&priv->mutex);
1113
1114 /* setup initial channel */ 1118 /* setup initial channel */
1115 init_channel = ath9k_cmn_get_curchannel(hw, ah); 1119 init_channel = ath9k_cmn_get_curchannel(hw, ah);
1116 1120
@@ -1123,7 +1127,7 @@ static int ath9k_htc_start(struct ieee80211_hw *hw)
1123 ath_print(common, ATH_DBG_FATAL, 1127 ath_print(common, ATH_DBG_FATAL,
1124 "Unable to reset hardware; reset status %d " 1128 "Unable to reset hardware; reset status %d "
1125 "(freq %u MHz)\n", ret, curchan->center_freq); 1129 "(freq %u MHz)\n", ret, curchan->center_freq);
1126 goto mutex_unlock; 1130 return ret;
1127 } 1131 }
1128 1132
1129 ath_update_txpow(priv); 1133 ath_update_txpow(priv);
@@ -1131,16 +1135,8 @@ static int ath9k_htc_start(struct ieee80211_hw *hw)
1131 mode = ath9k_htc_get_curmode(priv, init_channel); 1135 mode = ath9k_htc_get_curmode(priv, init_channel);
1132 htc_mode = cpu_to_be16(mode); 1136 htc_mode = cpu_to_be16(mode);
1133 WMI_CMD_BUF(WMI_SET_MODE_CMDID, &htc_mode); 1137 WMI_CMD_BUF(WMI_SET_MODE_CMDID, &htc_mode);
1134 if (ret)
1135 goto mutex_unlock;
1136
1137 WMI_CMD(WMI_ATH_INIT_CMDID); 1138 WMI_CMD(WMI_ATH_INIT_CMDID);
1138 if (ret)
1139 goto mutex_unlock;
1140
1141 WMI_CMD(WMI_START_RECV_CMDID); 1139 WMI_CMD(WMI_START_RECV_CMDID);
1142 if (ret)
1143 goto mutex_unlock;
1144 1140
1145 ath9k_host_rx_init(priv); 1141 ath9k_host_rx_init(priv);
1146 1142
@@ -1153,12 +1149,22 @@ static int ath9k_htc_start(struct ieee80211_hw *hw)
1153 1149
1154 ieee80211_wake_queues(hw); 1150 ieee80211_wake_queues(hw);
1155 1151
1156mutex_unlock: 1152 return ret;
1153}
1154
1155static int ath9k_htc_start(struct ieee80211_hw *hw)
1156{
1157 struct ath9k_htc_priv *priv = hw->priv;
1158 int ret = 0;
1159
1160 mutex_lock(&priv->mutex);
1161 ret = ath9k_htc_radio_enable(hw);
1157 mutex_unlock(&priv->mutex); 1162 mutex_unlock(&priv->mutex);
1163
1158 return ret; 1164 return ret;
1159} 1165}
1160 1166
1161static void ath9k_htc_stop(struct ieee80211_hw *hw) 1167static void ath9k_htc_radio_disable(struct ieee80211_hw *hw)
1162{ 1168{
1163 struct ath9k_htc_priv *priv = hw->priv; 1169 struct ath9k_htc_priv *priv = hw->priv;
1164 struct ath_hw *ah = priv->ah; 1170 struct ath_hw *ah = priv->ah;
@@ -1166,14 +1172,18 @@ static void ath9k_htc_stop(struct ieee80211_hw *hw)
1166 int ret = 0; 1172 int ret = 0;
1167 u8 cmd_rsp; 1173 u8 cmd_rsp;
1168 1174
1169 mutex_lock(&priv->mutex);
1170
1171 if (priv->op_flags & OP_INVALID) { 1175 if (priv->op_flags & OP_INVALID) {
1172 ath_print(common, ATH_DBG_ANY, "Device not present\n"); 1176 ath_print(common, ATH_DBG_ANY, "Device not present\n");
1173 mutex_unlock(&priv->mutex);
1174 return; 1177 return;
1175 } 1178 }
1176 1179
1180 /* Cancel all the running timers/work .. */
1181 cancel_work_sync(&priv->ps_work);
1182 cancel_delayed_work_sync(&priv->ath9k_ani_work);
1183 cancel_delayed_work_sync(&priv->ath9k_aggr_work);
1184 cancel_delayed_work_sync(&priv->ath9k_led_blink_work);
1185 ath9k_led_stop_brightness(priv);
1186
1177 ath9k_htc_ps_wakeup(priv); 1187 ath9k_htc_ps_wakeup(priv);
1178 htc_stop(priv->htc); 1188 htc_stop(priv->htc);
1179 WMI_CMD(WMI_DISABLE_INTR_CMDID); 1189 WMI_CMD(WMI_DISABLE_INTR_CMDID);
@@ -1185,11 +1195,6 @@ static void ath9k_htc_stop(struct ieee80211_hw *hw)
1185 ath9k_htc_ps_restore(priv); 1195 ath9k_htc_ps_restore(priv);
1186 ath9k_htc_setpower(priv, ATH9K_PM_FULL_SLEEP); 1196 ath9k_htc_setpower(priv, ATH9K_PM_FULL_SLEEP);
1187 1197
1188 cancel_work_sync(&priv->ps_work);
1189 cancel_delayed_work_sync(&priv->ath9k_ani_work);
1190 cancel_delayed_work_sync(&priv->ath9k_aggr_work);
1191 cancel_delayed_work_sync(&priv->ath9k_led_blink_work);
1192 ath9k_led_stop_brightness(priv);
1193 skb_queue_purge(&priv->tx_queue); 1198 skb_queue_purge(&priv->tx_queue);
1194 1199
1195 /* Remove monitor interface here */ 1200 /* Remove monitor interface here */
@@ -1203,11 +1208,20 @@ static void ath9k_htc_stop(struct ieee80211_hw *hw)
1203 } 1208 }
1204 1209
1205 priv->op_flags |= OP_INVALID; 1210 priv->op_flags |= OP_INVALID;
1206 mutex_unlock(&priv->mutex);
1207 1211
1208 ath_print(common, ATH_DBG_CONFIG, "Driver halt\n"); 1212 ath_print(common, ATH_DBG_CONFIG, "Driver halt\n");
1209} 1213}
1210 1214
1215static void ath9k_htc_stop(struct ieee80211_hw *hw)
1216{
1217 struct ath9k_htc_priv *priv = hw->priv;
1218
1219 mutex_lock(&priv->mutex);
1220 ath9k_htc_radio_disable(hw);
1221 mutex_unlock(&priv->mutex);
1222}
1223
1224
1211static int ath9k_htc_add_interface(struct ieee80211_hw *hw, 1225static int ath9k_htc_add_interface(struct ieee80211_hw *hw,
1212 struct ieee80211_vif *vif) 1226 struct ieee80211_vif *vif)
1213{ 1227{
@@ -1321,6 +1335,23 @@ static int ath9k_htc_config(struct ieee80211_hw *hw, u32 changed)
1321 1335
1322 mutex_lock(&priv->mutex); 1336 mutex_lock(&priv->mutex);
1323 1337
1338 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
1339 bool enable_radio = false;
1340 bool idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1341
1342 if (!idle && priv->ps_idle)
1343 enable_radio = true;
1344
1345 priv->ps_idle = idle;
1346
1347 if (enable_radio) {
1348 ath9k_htc_setpower(priv, ATH9K_PM_AWAKE);
1349 ath9k_htc_radio_enable(hw);
1350 ath_print(common, ATH_DBG_CONFIG,
1351 "not-idle: enabling radio\n");
1352 }
1353 }
1354
1324 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { 1355 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
1325 struct ieee80211_channel *curchan = hw->conf.channel; 1356 struct ieee80211_channel *curchan = hw->conf.channel;
1326 int pos = curchan->hw_value; 1357 int pos = curchan->hw_value;
@@ -1364,6 +1395,13 @@ static int ath9k_htc_config(struct ieee80211_hw *hw, u32 changed)
1364 } 1395 }
1365 } 1396 }
1366 1397
1398 if (priv->ps_idle) {
1399 ath_print(common, ATH_DBG_CONFIG,
1400 "idle: disabling radio\n");
1401 ath9k_htc_radio_disable(hw);
1402 }
1403
1404
1367 mutex_unlock(&priv->mutex); 1405 mutex_unlock(&priv->mutex);
1368 1406
1369 return 0; 1407 return 0;
@@ -1687,7 +1725,7 @@ static void ath9k_htc_sw_scan_complete(struct ieee80211_hw *hw)
1687 spin_unlock_bh(&priv->beacon_lock); 1725 spin_unlock_bh(&priv->beacon_lock);
1688 priv->op_flags |= OP_FULL_RESET; 1726 priv->op_flags |= OP_FULL_RESET;
1689 if (priv->op_flags & OP_ASSOCIATED) 1727 if (priv->op_flags & OP_ASSOCIATED)
1690 ath9k_htc_beacon_config(priv, NULL); 1728 ath9k_htc_beacon_config(priv, priv->vif);
1691 ath_start_ani(priv); 1729 ath_start_ani(priv);
1692 mutex_unlock(&priv->mutex); 1730 mutex_unlock(&priv->mutex);
1693 ath9k_htc_ps_restore(priv); 1731 ath9k_htc_ps_restore(priv);
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c b/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c
index 0a7cb30af5b4..28abc7d5e909 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c
@@ -244,16 +244,25 @@ void ath9k_htc_txep(void *drv_priv, struct sk_buff *skb,
244 enum htc_endpoint_id ep_id, bool txok) 244 enum htc_endpoint_id ep_id, bool txok)
245{ 245{
246 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) drv_priv; 246 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) drv_priv;
247 struct ath_common *common = ath9k_hw_common(priv->ah);
247 struct ieee80211_tx_info *tx_info; 248 struct ieee80211_tx_info *tx_info;
248 249
249 if (!skb) 250 if (!skb)
250 return; 251 return;
251 252
252 if (ep_id == priv->mgmt_ep) 253 if (ep_id == priv->mgmt_ep) {
253 skb_pull(skb, sizeof(struct tx_mgmt_hdr)); 254 skb_pull(skb, sizeof(struct tx_mgmt_hdr));
254 else 255 } else if ((ep_id == priv->data_bk_ep) ||
255 /* TODO: Check for cab/uapsd/data */ 256 (ep_id == priv->data_be_ep) ||
257 (ep_id == priv->data_vi_ep) ||
258 (ep_id == priv->data_vo_ep)) {
256 skb_pull(skb, sizeof(struct tx_frame_hdr)); 259 skb_pull(skb, sizeof(struct tx_frame_hdr));
260 } else {
261 ath_print(common, ATH_DBG_FATAL,
262 "Unsupported TX EPID: %d\n", ep_id);
263 dev_kfree_skb_any(skb);
264 return;
265 }
257 266
258 tx_info = IEEE80211_SKB_CB(skb); 267 tx_info = IEEE80211_SKB_CB(skb);
259 268
@@ -439,10 +448,32 @@ static bool ath9k_rx_prepare(struct ath9k_htc_priv *priv,
439 struct ieee80211_hw *hw = priv->hw; 448 struct ieee80211_hw *hw = priv->hw;
440 struct sk_buff *skb = rxbuf->skb; 449 struct sk_buff *skb = rxbuf->skb;
441 struct ath_common *common = ath9k_hw_common(priv->ah); 450 struct ath_common *common = ath9k_hw_common(priv->ah);
451 struct ath_htc_rx_status *rxstatus;
442 int hdrlen, padpos, padsize; 452 int hdrlen, padpos, padsize;
443 int last_rssi = ATH_RSSI_DUMMY_MARKER; 453 int last_rssi = ATH_RSSI_DUMMY_MARKER;
444 __le16 fc; 454 __le16 fc;
445 455
456 if (skb->len <= HTC_RX_FRAME_HEADER_SIZE) {
457 ath_print(common, ATH_DBG_FATAL,
458 "Corrupted RX frame, dropping\n");
459 goto rx_next;
460 }
461
462 rxstatus = (struct ath_htc_rx_status *)skb->data;
463
464 if (be16_to_cpu(rxstatus->rs_datalen) -
465 (skb->len - HTC_RX_FRAME_HEADER_SIZE) != 0) {
466 ath_print(common, ATH_DBG_FATAL,
467 "Corrupted RX data len, dropping "
468 "(dlen: %d, skblen: %d)\n",
469 rxstatus->rs_datalen, skb->len);
470 goto rx_next;
471 }
472
473 /* Get the RX status information */
474 memcpy(&rxbuf->rxstatus, rxstatus, HTC_RX_FRAME_HEADER_SIZE);
475 skb_pull(skb, HTC_RX_FRAME_HEADER_SIZE);
476
446 hdr = (struct ieee80211_hdr *)skb->data; 477 hdr = (struct ieee80211_hdr *)skb->data;
447 fc = hdr->frame_control; 478 fc = hdr->frame_control;
448 hdrlen = ieee80211_get_hdrlen_from_skb(skb); 479 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
@@ -530,7 +561,7 @@ static bool ath9k_rx_prepare(struct ath9k_htc_priv *priv,
530 priv->ah->stats.avgbrssi = rxbuf->rxstatus.rs_rssi; 561 priv->ah->stats.avgbrssi = rxbuf->rxstatus.rs_rssi;
531 } 562 }
532 563
533 rx_status->mactime = rxbuf->rxstatus.rs_tstamp; 564 rx_status->mactime = be64_to_cpu(rxbuf->rxstatus.rs_tstamp);
534 rx_status->band = hw->conf.channel->band; 565 rx_status->band = hw->conf.channel->band;
535 rx_status->freq = hw->conf.channel->center_freq; 566 rx_status->freq = hw->conf.channel->center_freq;
536 rx_status->signal = rxbuf->rxstatus.rs_rssi + ATH_DEFAULT_NOISE_FLOOR; 567 rx_status->signal = rxbuf->rxstatus.rs_rssi + ATH_DEFAULT_NOISE_FLOOR;
@@ -607,8 +638,6 @@ void ath9k_htc_rxep(void *drv_priv, struct sk_buff *skb,
607 struct ath_hw *ah = priv->ah; 638 struct ath_hw *ah = priv->ah;
608 struct ath_common *common = ath9k_hw_common(ah); 639 struct ath_common *common = ath9k_hw_common(ah);
609 struct ath9k_htc_rxbuf *rxbuf = NULL, *tmp_buf = NULL; 640 struct ath9k_htc_rxbuf *rxbuf = NULL, *tmp_buf = NULL;
610 struct ath_htc_rx_status *rxstatus;
611 u32 len = 0;
612 641
613 spin_lock(&priv->rx.rxbuflock); 642 spin_lock(&priv->rx.rxbuflock);
614 list_for_each_entry(tmp_buf, &priv->rx.rxbuf, list) { 643 list_for_each_entry(tmp_buf, &priv->rx.rxbuf, list) {
@@ -625,32 +654,7 @@ void ath9k_htc_rxep(void *drv_priv, struct sk_buff *skb,
625 goto err; 654 goto err;
626 } 655 }
627 656
628 len = skb->len;
629 if (len <= HTC_RX_FRAME_HEADER_SIZE) {
630 ath_print(common, ATH_DBG_FATAL,
631 "Corrupted RX frame, dropping\n");
632 goto err;
633 }
634
635 rxstatus = (struct ath_htc_rx_status *)skb->data;
636
637 rxstatus->rs_tstamp = be64_to_cpu(rxstatus->rs_tstamp);
638 rxstatus->rs_datalen = be16_to_cpu(rxstatus->rs_datalen);
639 rxstatus->evm0 = be32_to_cpu(rxstatus->evm0);
640 rxstatus->evm1 = be32_to_cpu(rxstatus->evm1);
641 rxstatus->evm2 = be32_to_cpu(rxstatus->evm2);
642
643 if (rxstatus->rs_datalen - (len - HTC_RX_FRAME_HEADER_SIZE) != 0) {
644 ath_print(common, ATH_DBG_FATAL,
645 "Corrupted RX data len, dropping "
646 "(epid: %d, dlen: %d, skblen: %d)\n",
647 ep_id, rxstatus->rs_datalen, len);
648 goto err;
649 }
650
651 spin_lock(&priv->rx.rxbuflock); 657 spin_lock(&priv->rx.rxbuflock);
652 memcpy(&rxbuf->rxstatus, rxstatus, HTC_RX_FRAME_HEADER_SIZE);
653 skb_pull(skb, HTC_RX_FRAME_HEADER_SIZE);
654 rxbuf->skb = skb; 658 rxbuf->skb = skb;
655 rxbuf->in_process = true; 659 rxbuf->in_process = true;
656 spin_unlock(&priv->rx.rxbuflock); 660 spin_unlock(&priv->rx.rxbuflock);
diff --git a/drivers/net/wireless/ath/ath9k/htc_hst.c b/drivers/net/wireless/ath/ath9k/htc_hst.c
index 587d98ed0989..7bf6ce1e7e2e 100644
--- a/drivers/net/wireless/ath/ath9k/htc_hst.c
+++ b/drivers/net/wireless/ath/ath9k/htc_hst.c
@@ -341,8 +341,9 @@ void ath9k_htc_txcompletion_cb(struct htc_target *htc_handle,
341 skb_pull(skb, sizeof(struct htc_frame_hdr)); 341 skb_pull(skb, sizeof(struct htc_frame_hdr));
342 342
343 if (endpoint->ep_callbacks.tx) { 343 if (endpoint->ep_callbacks.tx) {
344 endpoint->ep_callbacks.tx(htc_handle->drv_priv, skb, 344 endpoint->ep_callbacks.tx(endpoint->ep_callbacks.priv,
345 htc_hdr->endpoint_id, txok); 345 skb, htc_hdr->endpoint_id,
346 txok);
346 } 347 }
347 } 348 }
348 349
@@ -368,7 +369,7 @@ void ath9k_htc_rx_msg(struct htc_target *htc_handle,
368 struct htc_frame_hdr *htc_hdr; 369 struct htc_frame_hdr *htc_hdr;
369 enum htc_endpoint_id epid; 370 enum htc_endpoint_id epid;
370 struct htc_endpoint *endpoint; 371 struct htc_endpoint *endpoint;
371 u16 *msg_id; 372 __be16 *msg_id;
372 373
373 if (!htc_handle || !skb) 374 if (!htc_handle || !skb)
374 return; 375 return;
@@ -388,14 +389,14 @@ void ath9k_htc_rx_msg(struct htc_target *htc_handle,
388 389
389 /* Handle trailer */ 390 /* Handle trailer */
390 if (htc_hdr->flags & HTC_FLAGS_RECV_TRAILER) { 391 if (htc_hdr->flags & HTC_FLAGS_RECV_TRAILER) {
391 if (be32_to_cpu(*(u32 *) skb->data) == 0x00C60000) 392 if (be32_to_cpu(*(__be32 *) skb->data) == 0x00C60000)
392 /* Move past the Watchdog pattern */ 393 /* Move past the Watchdog pattern */
393 htc_hdr = (struct htc_frame_hdr *)(skb->data + 4); 394 htc_hdr = (struct htc_frame_hdr *)(skb->data + 4);
394 } 395 }
395 396
396 /* Get the message ID */ 397 /* Get the message ID */
397 msg_id = (u16 *) ((void *) htc_hdr + 398 msg_id = (__be16 *) ((void *) htc_hdr +
398 sizeof(struct htc_frame_hdr)); 399 sizeof(struct htc_frame_hdr));
399 400
400 /* Now process HTC messages */ 401 /* Now process HTC messages */
401 switch (be16_to_cpu(*msg_id)) { 402 switch (be16_to_cpu(*msg_id)) {
diff --git a/drivers/net/wireless/ath/ath9k/htc_hst.h b/drivers/net/wireless/ath/ath9k/htc_hst.h
index cd7048ffd239..ea50ab032d20 100644
--- a/drivers/net/wireless/ath/ath9k/htc_hst.h
+++ b/drivers/net/wireless/ath/ath9k/htc_hst.h
@@ -59,20 +59,20 @@ enum htc_endpoint_id {
59struct htc_frame_hdr { 59struct htc_frame_hdr {
60 u8 endpoint_id; 60 u8 endpoint_id;
61 u8 flags; 61 u8 flags;
62 u16 payload_len; 62 __be16 payload_len;
63 u8 control[4]; 63 u8 control[4];
64} __packed; 64} __packed;
65 65
66struct htc_ready_msg { 66struct htc_ready_msg {
67 u16 message_id; 67 __be16 message_id;
68 u16 credits; 68 __be16 credits;
69 u16 credit_size; 69 __be16 credit_size;
70 u8 max_endpoints; 70 u8 max_endpoints;
71 u8 pad; 71 u8 pad;
72} __packed; 72} __packed;
73 73
74struct htc_config_pipe_msg { 74struct htc_config_pipe_msg {
75 u16 message_id; 75 __be16 message_id;
76 u8 pipe_id; 76 u8 pipe_id;
77 u8 credits; 77 u8 credits;
78} __packed; 78} __packed;
@@ -192,9 +192,9 @@ enum htc_service_group_ids{
192#define WMI_DATA_BK_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP, 8) 192#define WMI_DATA_BK_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP, 8)
193 193
194struct htc_conn_svc_msg { 194struct htc_conn_svc_msg {
195 u16 msg_id; 195 __be16 msg_id;
196 u16 service_id; 196 __be16 service_id;
197 u16 con_flags; 197 __be16 con_flags;
198 u8 dl_pipeid; 198 u8 dl_pipeid;
199 u8 ul_pipeid; 199 u8 ul_pipeid;
200 u8 svc_meta_len; 200 u8 svc_meta_len;
@@ -209,17 +209,17 @@ struct htc_conn_svc_msg {
209#define HTC_SERVICE_NO_MORE_EP 4 209#define HTC_SERVICE_NO_MORE_EP 4
210 210
211struct htc_conn_svc_rspmsg { 211struct htc_conn_svc_rspmsg {
212 u16 msg_id; 212 __be16 msg_id;
213 u16 service_id; 213 __be16 service_id;
214 u8 status; 214 u8 status;
215 u8 endpoint_id; 215 u8 endpoint_id;
216 u16 max_msg_len; 216 __be16 max_msg_len;
217 u8 svc_meta_len; 217 u8 svc_meta_len;
218 u8 pad; 218 u8 pad;
219} __packed; 219} __packed;
220 220
221struct htc_comp_msg { 221struct htc_comp_msg {
222 u16 msg_id; 222 __be16 msg_id;
223} __packed; 223} __packed;
224 224
225int htc_init(struct htc_target *target); 225int htc_init(struct htc_target *target);
diff --git a/drivers/net/wireless/ath/ath9k/hw-ops.h b/drivers/net/wireless/ath/ath9k/hw-ops.h
new file mode 100644
index 000000000000..624422a8169e
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/hw-ops.h
@@ -0,0 +1,280 @@
1/*
2 * Copyright (c) 2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef ATH9K_HW_OPS_H
18#define ATH9K_HW_OPS_H
19
20#include "hw.h"
21
22/* Hardware core and driver accessible callbacks */
23
24static inline void ath9k_hw_configpcipowersave(struct ath_hw *ah,
25 int restore,
26 int power_off)
27{
28 ath9k_hw_ops(ah)->config_pci_powersave(ah, restore, power_off);
29}
30
31static inline void ath9k_hw_rxena(struct ath_hw *ah)
32{
33 ath9k_hw_ops(ah)->rx_enable(ah);
34}
35
36static inline void ath9k_hw_set_desc_link(struct ath_hw *ah, void *ds,
37 u32 link)
38{
39 ath9k_hw_ops(ah)->set_desc_link(ds, link);
40}
41
42static inline void ath9k_hw_get_desc_link(struct ath_hw *ah, void *ds,
43 u32 **link)
44{
45 ath9k_hw_ops(ah)->get_desc_link(ds, link);
46}
47static inline bool ath9k_hw_calibrate(struct ath_hw *ah,
48 struct ath9k_channel *chan,
49 u8 rxchainmask,
50 bool longcal)
51{
52 return ath9k_hw_ops(ah)->calibrate(ah, chan, rxchainmask, longcal);
53}
54
55static inline bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
56{
57 return ath9k_hw_ops(ah)->get_isr(ah, masked);
58}
59
60static inline void ath9k_hw_filltxdesc(struct ath_hw *ah, void *ds, u32 seglen,
61 bool is_firstseg, bool is_lastseg,
62 const void *ds0, dma_addr_t buf_addr,
63 unsigned int qcu)
64{
65 ath9k_hw_ops(ah)->fill_txdesc(ah, ds, seglen, is_firstseg, is_lastseg,
66 ds0, buf_addr, qcu);
67}
68
69static inline int ath9k_hw_txprocdesc(struct ath_hw *ah, void *ds,
70 struct ath_tx_status *ts)
71{
72 return ath9k_hw_ops(ah)->proc_txdesc(ah, ds, ts);
73}
74
75static inline void ath9k_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
76 u32 pktLen, enum ath9k_pkt_type type,
77 u32 txPower, u32 keyIx,
78 enum ath9k_key_type keyType,
79 u32 flags)
80{
81 ath9k_hw_ops(ah)->set11n_txdesc(ah, ds, pktLen, type, txPower, keyIx,
82 keyType, flags);
83}
84
85static inline void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
86 void *lastds,
87 u32 durUpdateEn, u32 rtsctsRate,
88 u32 rtsctsDuration,
89 struct ath9k_11n_rate_series series[],
90 u32 nseries, u32 flags)
91{
92 ath9k_hw_ops(ah)->set11n_ratescenario(ah, ds, lastds, durUpdateEn,
93 rtsctsRate, rtsctsDuration, series,
94 nseries, flags);
95}
96
97static inline void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
98 u32 aggrLen)
99{
100 ath9k_hw_ops(ah)->set11n_aggr_first(ah, ds, aggrLen);
101}
102
103static inline void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
104 u32 numDelims)
105{
106 ath9k_hw_ops(ah)->set11n_aggr_middle(ah, ds, numDelims);
107}
108
109static inline void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, void *ds)
110{
111 ath9k_hw_ops(ah)->set11n_aggr_last(ah, ds);
112}
113
114static inline void ath9k_hw_clr11n_aggr(struct ath_hw *ah, void *ds)
115{
116 ath9k_hw_ops(ah)->clr11n_aggr(ah, ds);
117}
118
119static inline void ath9k_hw_set11n_burstduration(struct ath_hw *ah, void *ds,
120 u32 burstDuration)
121{
122 ath9k_hw_ops(ah)->set11n_burstduration(ah, ds, burstDuration);
123}
124
125static inline void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, void *ds,
126 u32 vmf)
127{
128 ath9k_hw_ops(ah)->set11n_virtualmorefrag(ah, ds, vmf);
129}
130
131/* Private hardware call ops */
132
133/* PHY ops */
134
135static inline int ath9k_hw_rf_set_freq(struct ath_hw *ah,
136 struct ath9k_channel *chan)
137{
138 return ath9k_hw_private_ops(ah)->rf_set_freq(ah, chan);
139}
140
141static inline void ath9k_hw_spur_mitigate_freq(struct ath_hw *ah,
142 struct ath9k_channel *chan)
143{
144 ath9k_hw_private_ops(ah)->spur_mitigate_freq(ah, chan);
145}
146
147static inline int ath9k_hw_rf_alloc_ext_banks(struct ath_hw *ah)
148{
149 if (!ath9k_hw_private_ops(ah)->rf_alloc_ext_banks)
150 return 0;
151
152 return ath9k_hw_private_ops(ah)->rf_alloc_ext_banks(ah);
153}
154
155static inline void ath9k_hw_rf_free_ext_banks(struct ath_hw *ah)
156{
157 if (!ath9k_hw_private_ops(ah)->rf_free_ext_banks)
158 return;
159
160 ath9k_hw_private_ops(ah)->rf_free_ext_banks(ah);
161}
162
163static inline bool ath9k_hw_set_rf_regs(struct ath_hw *ah,
164 struct ath9k_channel *chan,
165 u16 modesIndex)
166{
167 if (!ath9k_hw_private_ops(ah)->set_rf_regs)
168 return true;
169
170 return ath9k_hw_private_ops(ah)->set_rf_regs(ah, chan, modesIndex);
171}
172
173static inline void ath9k_hw_init_bb(struct ath_hw *ah,
174 struct ath9k_channel *chan)
175{
176 return ath9k_hw_private_ops(ah)->init_bb(ah, chan);
177}
178
179static inline void ath9k_hw_set_channel_regs(struct ath_hw *ah,
180 struct ath9k_channel *chan)
181{
182 return ath9k_hw_private_ops(ah)->set_channel_regs(ah, chan);
183}
184
185static inline int ath9k_hw_process_ini(struct ath_hw *ah,
186 struct ath9k_channel *chan)
187{
188 return ath9k_hw_private_ops(ah)->process_ini(ah, chan);
189}
190
191static inline void ath9k_olc_init(struct ath_hw *ah)
192{
193 if (!ath9k_hw_private_ops(ah)->olc_init)
194 return;
195
196 return ath9k_hw_private_ops(ah)->olc_init(ah);
197}
198
199static inline void ath9k_hw_set_rfmode(struct ath_hw *ah,
200 struct ath9k_channel *chan)
201{
202 return ath9k_hw_private_ops(ah)->set_rfmode(ah, chan);
203}
204
205static inline void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
206{
207 return ath9k_hw_private_ops(ah)->mark_phy_inactive(ah);
208}
209
210static inline void ath9k_hw_set_delta_slope(struct ath_hw *ah,
211 struct ath9k_channel *chan)
212{
213 return ath9k_hw_private_ops(ah)->set_delta_slope(ah, chan);
214}
215
216static inline bool ath9k_hw_rfbus_req(struct ath_hw *ah)
217{
218 return ath9k_hw_private_ops(ah)->rfbus_req(ah);
219}
220
221static inline void ath9k_hw_rfbus_done(struct ath_hw *ah)
222{
223 return ath9k_hw_private_ops(ah)->rfbus_done(ah);
224}
225
226static inline void ath9k_enable_rfkill(struct ath_hw *ah)
227{
228 return ath9k_hw_private_ops(ah)->enable_rfkill(ah);
229}
230
231static inline void ath9k_hw_restore_chainmask(struct ath_hw *ah)
232{
233 if (!ath9k_hw_private_ops(ah)->restore_chainmask)
234 return;
235
236 return ath9k_hw_private_ops(ah)->restore_chainmask(ah);
237}
238
239static inline void ath9k_hw_set_diversity(struct ath_hw *ah, bool value)
240{
241 return ath9k_hw_private_ops(ah)->set_diversity(ah, value);
242}
243
244static inline bool ath9k_hw_ani_control(struct ath_hw *ah,
245 enum ath9k_ani_cmd cmd, int param)
246{
247 return ath9k_hw_private_ops(ah)->ani_control(ah, cmd, param);
248}
249
250static inline void ath9k_hw_do_getnf(struct ath_hw *ah,
251 int16_t nfarray[NUM_NF_READINGS])
252{
253 ath9k_hw_private_ops(ah)->do_getnf(ah, nfarray);
254}
255
256static inline void ath9k_hw_loadnf(struct ath_hw *ah,
257 struct ath9k_channel *chan)
258{
259 ath9k_hw_private_ops(ah)->loadnf(ah, chan);
260}
261
262static inline bool ath9k_hw_init_cal(struct ath_hw *ah,
263 struct ath9k_channel *chan)
264{
265 return ath9k_hw_private_ops(ah)->init_cal(ah, chan);
266}
267
268static inline void ath9k_hw_setup_calibration(struct ath_hw *ah,
269 struct ath9k_cal_list *currCal)
270{
271 ath9k_hw_private_ops(ah)->setup_calibration(ah, currCal);
272}
273
274static inline bool ath9k_hw_iscal_supported(struct ath_hw *ah,
275 enum ath9k_cal_types calType)
276{
277 return ath9k_hw_private_ops(ah)->iscal_supported(ah, calType);
278}
279
280#endif /* ATH9K_HW_OPS_H */
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index af730c7d50e6..559019262d30 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2008-2009 Atheros Communications Inc. 2 * Copyright (c) 2008-2010 Atheros Communications Inc.
3 * 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any 4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above 5 * purpose with or without fee is hereby granted, provided that the above
@@ -19,15 +19,16 @@
19#include <asm/unaligned.h> 19#include <asm/unaligned.h>
20 20
21#include "hw.h" 21#include "hw.h"
22#include "hw-ops.h"
22#include "rc.h" 23#include "rc.h"
23#include "initvals.h" 24#include "ar9003_mac.h"
24 25
25#define ATH9K_CLOCK_RATE_CCK 22 26#define ATH9K_CLOCK_RATE_CCK 22
26#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40 27#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
27#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44 28#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
29#define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44
28 30
29static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); 31static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
30static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
31 32
32MODULE_AUTHOR("Atheros Communications"); 33MODULE_AUTHOR("Atheros Communications");
33MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 34MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
@@ -46,6 +47,39 @@ static void __exit ath9k_exit(void)
46} 47}
47module_exit(ath9k_exit); 48module_exit(ath9k_exit);
48 49
50/* Private hardware callbacks */
51
52static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
53{
54 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
55}
56
57static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
58{
59 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
60}
61
62static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
63{
64 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
65
66 return priv_ops->macversion_supported(ah->hw_version.macVersion);
67}
68
69static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
70 struct ath9k_channel *chan)
71{
72 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
73}
74
75static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
76{
77 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
78 return;
79
80 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
81}
82
49/********************/ 83/********************/
50/* Helper Functions */ 84/* Helper Functions */
51/********************/ 85/********************/
@@ -58,7 +92,11 @@ static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
58 return usecs *ATH9K_CLOCK_RATE_CCK; 92 return usecs *ATH9K_CLOCK_RATE_CCK;
59 if (conf->channel->band == IEEE80211_BAND_2GHZ) 93 if (conf->channel->band == IEEE80211_BAND_2GHZ)
60 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM; 94 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
61 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM; 95
96 if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
97 return usecs * ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
98 else
99 return usecs * ATH9K_CLOCK_RATE_5GHZ_OFDM;
62} 100}
63 101
64static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) 102static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
@@ -233,21 +271,6 @@ static void ath9k_hw_read_revisions(struct ath_hw *ah)
233 } 271 }
234} 272}
235 273
236static int ath9k_hw_get_radiorev(struct ath_hw *ah)
237{
238 u32 val;
239 int i;
240
241 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
242
243 for (i = 0; i < 8; i++)
244 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
245 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
246 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
247
248 return ath9k_hw_reverse_bits(val, 8);
249}
250
251/************************************/ 274/************************************/
252/* HW Attach, Detach, Init Routines */ 275/* HW Attach, Detach, Init Routines */
253/************************************/ 276/************************************/
@@ -257,6 +280,8 @@ static void ath9k_hw_disablepcie(struct ath_hw *ah)
257 if (AR_SREV_9100(ah)) 280 if (AR_SREV_9100(ah))
258 return; 281 return;
259 282
283 ENABLE_REGWRITE_BUFFER(ah);
284
260 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 285 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
261 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 286 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
262 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 287 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
@@ -268,20 +293,30 @@ static void ath9k_hw_disablepcie(struct ath_hw *ah)
268 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 293 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
269 294
270 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 295 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
296
297 REGWRITE_BUFFER_FLUSH(ah);
298 DISABLE_REGWRITE_BUFFER(ah);
271} 299}
272 300
301/* This should work for all families including legacy */
273static bool ath9k_hw_chip_test(struct ath_hw *ah) 302static bool ath9k_hw_chip_test(struct ath_hw *ah)
274{ 303{
275 struct ath_common *common = ath9k_hw_common(ah); 304 struct ath_common *common = ath9k_hw_common(ah);
276 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) }; 305 u32 regAddr[2] = { AR_STA_ID0 };
277 u32 regHold[2]; 306 u32 regHold[2];
278 u32 patternData[4] = { 0x55555555, 307 u32 patternData[4] = { 0x55555555,
279 0xaaaaaaaa, 308 0xaaaaaaaa,
280 0x66666666, 309 0x66666666,
281 0x99999999 }; 310 0x99999999 };
282 int i, j; 311 int i, j, loop_max;
283 312
284 for (i = 0; i < 2; i++) { 313 if (!AR_SREV_9300_20_OR_LATER(ah)) {
314 loop_max = 2;
315 regAddr[1] = AR_PHY_BASE + (8 << 2);
316 } else
317 loop_max = 1;
318
319 for (i = 0; i < loop_max; i++) {
285 u32 addr = regAddr[i]; 320 u32 addr = regAddr[i];
286 u32 wrData, rdData; 321 u32 wrData, rdData;
287 322
@@ -336,7 +371,13 @@ static void ath9k_hw_init_config(struct ath_hw *ah)
336 ah->config.ofdm_trig_high = 500; 371 ah->config.ofdm_trig_high = 500;
337 ah->config.cck_trig_high = 200; 372 ah->config.cck_trig_high = 200;
338 ah->config.cck_trig_low = 100; 373 ah->config.cck_trig_low = 100;
339 ah->config.enable_ani = 1; 374
375 /*
376 * For now ANI is disabled for AR9003, it is still
377 * being tested.
378 */
379 if (!AR_SREV_9300_20_OR_LATER(ah))
380 ah->config.enable_ani = 1;
340 381
341 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 382 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
342 ah->config.spurchans[i][0] = AR_NO_SPUR; 383 ah->config.spurchans[i][0] = AR_NO_SPUR;
@@ -351,6 +392,12 @@ static void ath9k_hw_init_config(struct ath_hw *ah)
351 ah->config.rx_intr_mitigation = true; 392 ah->config.rx_intr_mitigation = true;
352 393
353 /* 394 /*
395 * Tx IQ Calibration (ah->config.tx_iq_calibration) is only
396 * used by AR9003, but it is showing reliability issues.
397 * It will take a while to fix so this is currently disabled.
398 */
399
400 /*
354 * We need this for PCI devices only (Cardbus, PCI, miniPCI) 401 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
355 * _and_ if on non-uniprocessor systems (Multiprocessor/HT). 402 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
356 * This means we use it for all AR5416 devices, and the few 403 * This means we use it for all AR5416 devices, and the few
@@ -369,7 +416,6 @@ static void ath9k_hw_init_config(struct ath_hw *ah)
369 if (num_possible_cpus() > 1) 416 if (num_possible_cpus() > 1)
370 ah->config.serialize_regmode = SER_REG_MODE_AUTO; 417 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
371} 418}
372EXPORT_SYMBOL(ath9k_hw_init);
373 419
374static void ath9k_hw_init_defaults(struct ath_hw *ah) 420static void ath9k_hw_init_defaults(struct ath_hw *ah)
375{ 421{
@@ -383,8 +429,6 @@ static void ath9k_hw_init_defaults(struct ath_hw *ah)
383 ah->hw_version.subvendorid = 0; 429 ah->hw_version.subvendorid = 0;
384 430
385 ah->ah_flags = 0; 431 ah->ah_flags = 0;
386 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
387 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
388 if (!AR_SREV_9100(ah)) 432 if (!AR_SREV_9100(ah))
389 ah->ah_flags = AH_USE_EEPROM; 433 ah->ah_flags = AH_USE_EEPROM;
390 434
@@ -397,44 +441,17 @@ static void ath9k_hw_init_defaults(struct ath_hw *ah)
397 ah->power_mode = ATH9K_PM_UNDEFINED; 441 ah->power_mode = ATH9K_PM_UNDEFINED;
398} 442}
399 443
400static int ath9k_hw_rf_claim(struct ath_hw *ah)
401{
402 u32 val;
403
404 REG_WRITE(ah, AR_PHY(0), 0x00000007);
405
406 val = ath9k_hw_get_radiorev(ah);
407 switch (val & AR_RADIO_SREV_MAJOR) {
408 case 0:
409 val = AR_RAD5133_SREV_MAJOR;
410 break;
411 case AR_RAD5133_SREV_MAJOR:
412 case AR_RAD5122_SREV_MAJOR:
413 case AR_RAD2133_SREV_MAJOR:
414 case AR_RAD2122_SREV_MAJOR:
415 break;
416 default:
417 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
418 "Radio Chip Rev 0x%02X not supported\n",
419 val & AR_RADIO_SREV_MAJOR);
420 return -EOPNOTSUPP;
421 }
422
423 ah->hw_version.analog5GhzRev = val;
424
425 return 0;
426}
427
428static int ath9k_hw_init_macaddr(struct ath_hw *ah) 444static int ath9k_hw_init_macaddr(struct ath_hw *ah)
429{ 445{
430 struct ath_common *common = ath9k_hw_common(ah); 446 struct ath_common *common = ath9k_hw_common(ah);
431 u32 sum; 447 u32 sum;
432 int i; 448 int i;
433 u16 eeval; 449 u16 eeval;
450 u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
434 451
435 sum = 0; 452 sum = 0;
436 for (i = 0; i < 3; i++) { 453 for (i = 0; i < 3; i++) {
437 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i)); 454 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
438 sum += eeval; 455 sum += eeval;
439 common->macaddr[2 * i] = eeval >> 8; 456 common->macaddr[2 * i] = eeval >> 8;
440 common->macaddr[2 * i + 1] = eeval & 0xff; 457 common->macaddr[2 * i + 1] = eeval & 0xff;
@@ -445,54 +462,6 @@ static int ath9k_hw_init_macaddr(struct ath_hw *ah)
445 return 0; 462 return 0;
446} 463}
447 464
448static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
449{
450 u32 rxgain_type;
451
452 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
453 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
454
455 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
456 INIT_INI_ARRAY(&ah->iniModesRxGain,
457 ar9280Modes_backoff_13db_rxgain_9280_2,
458 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
459 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
460 INIT_INI_ARRAY(&ah->iniModesRxGain,
461 ar9280Modes_backoff_23db_rxgain_9280_2,
462 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
463 else
464 INIT_INI_ARRAY(&ah->iniModesRxGain,
465 ar9280Modes_original_rxgain_9280_2,
466 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
467 } else {
468 INIT_INI_ARRAY(&ah->iniModesRxGain,
469 ar9280Modes_original_rxgain_9280_2,
470 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
471 }
472}
473
474static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
475{
476 u32 txgain_type;
477
478 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
479 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
480
481 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
482 INIT_INI_ARRAY(&ah->iniModesTxGain,
483 ar9280Modes_high_power_tx_gain_9280_2,
484 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
485 else
486 INIT_INI_ARRAY(&ah->iniModesTxGain,
487 ar9280Modes_original_tx_gain_9280_2,
488 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
489 } else {
490 INIT_INI_ARRAY(&ah->iniModesTxGain,
491 ar9280Modes_original_tx_gain_9280_2,
492 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
493 }
494}
495
496static int ath9k_hw_post_init(struct ath_hw *ah) 465static int ath9k_hw_post_init(struct ath_hw *ah)
497{ 466{
498 int ecode; 467 int ecode;
@@ -502,9 +471,11 @@ static int ath9k_hw_post_init(struct ath_hw *ah)
502 return -ENODEV; 471 return -ENODEV;
503 } 472 }
504 473
505 ecode = ath9k_hw_rf_claim(ah); 474 if (!AR_SREV_9300_20_OR_LATER(ah)) {
506 if (ecode != 0) 475 ecode = ar9002_hw_rf_claim(ah);
507 return ecode; 476 if (ecode != 0)
477 return ecode;
478 }
508 479
509 ecode = ath9k_hw_eeprom_init(ah); 480 ecode = ath9k_hw_eeprom_init(ah);
510 if (ecode != 0) 481 if (ecode != 0)
@@ -515,14 +486,12 @@ static int ath9k_hw_post_init(struct ath_hw *ah)
515 ah->eep_ops->get_eeprom_ver(ah), 486 ah->eep_ops->get_eeprom_ver(ah),
516 ah->eep_ops->get_eeprom_rev(ah)); 487 ah->eep_ops->get_eeprom_rev(ah));
517 488
518 if (!AR_SREV_9280_10_OR_LATER(ah)) { 489 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
519 ecode = ath9k_hw_rf_alloc_ext_banks(ah); 490 if (ecode) {
520 if (ecode) { 491 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
521 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 492 "Failed allocating banks for "
522 "Failed allocating banks for " 493 "external radio\n");
523 "external radio\n"); 494 return ecode;
524 return ecode;
525 }
526 } 495 }
527 496
528 if (!AR_SREV_9100(ah)) { 497 if (!AR_SREV_9100(ah)) {
@@ -533,344 +502,22 @@ static int ath9k_hw_post_init(struct ath_hw *ah)
533 return 0; 502 return 0;
534} 503}
535 504
536static bool ath9k_hw_devid_supported(u16 devid) 505static void ath9k_hw_attach_ops(struct ath_hw *ah)
537{
538 switch (devid) {
539 case AR5416_DEVID_PCI:
540 case AR5416_DEVID_PCIE:
541 case AR5416_AR9100_DEVID:
542 case AR9160_DEVID_PCI:
543 case AR9280_DEVID_PCI:
544 case AR9280_DEVID_PCIE:
545 case AR9285_DEVID_PCIE:
546 case AR5416_DEVID_AR9287_PCI:
547 case AR5416_DEVID_AR9287_PCIE:
548 case AR2427_DEVID_PCIE:
549 return true;
550 default:
551 break;
552 }
553 return false;
554}
555
556static bool ath9k_hw_macversion_supported(u32 macversion)
557{ 506{
558 switch (macversion) { 507 if (AR_SREV_9300_20_OR_LATER(ah))
559 case AR_SREV_VERSION_5416_PCI: 508 ar9003_hw_attach_ops(ah);
560 case AR_SREV_VERSION_5416_PCIE: 509 else
561 case AR_SREV_VERSION_9160: 510 ar9002_hw_attach_ops(ah);
562 case AR_SREV_VERSION_9100:
563 case AR_SREV_VERSION_9280:
564 case AR_SREV_VERSION_9285:
565 case AR_SREV_VERSION_9287:
566 case AR_SREV_VERSION_9271:
567 return true;
568 default:
569 break;
570 }
571 return false;
572}
573
574static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
575{
576 if (AR_SREV_9160_10_OR_LATER(ah)) {
577 if (AR_SREV_9280_10_OR_LATER(ah)) {
578 ah->iq_caldata.calData = &iq_cal_single_sample;
579 ah->adcgain_caldata.calData =
580 &adc_gain_cal_single_sample;
581 ah->adcdc_caldata.calData =
582 &adc_dc_cal_single_sample;
583 ah->adcdc_calinitdata.calData =
584 &adc_init_dc_cal;
585 } else {
586 ah->iq_caldata.calData = &iq_cal_multi_sample;
587 ah->adcgain_caldata.calData =
588 &adc_gain_cal_multi_sample;
589 ah->adcdc_caldata.calData =
590 &adc_dc_cal_multi_sample;
591 ah->adcdc_calinitdata.calData =
592 &adc_init_dc_cal;
593 }
594 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
595 }
596}
597
598static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
599{
600 if (AR_SREV_9271(ah)) {
601 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
602 ARRAY_SIZE(ar9271Modes_9271), 6);
603 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
604 ARRAY_SIZE(ar9271Common_9271), 2);
605 INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271,
606 ar9271Common_normal_cck_fir_coeff_9271,
607 ARRAY_SIZE(ar9271Common_normal_cck_fir_coeff_9271), 2);
608 INIT_INI_ARRAY(&ah->iniCommon_japan_2484_cck_fir_coeff_9271,
609 ar9271Common_japan_2484_cck_fir_coeff_9271,
610 ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271), 2);
611 INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
612 ar9271Modes_9271_1_0_only,
613 ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
614 INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg,
615 ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 6);
616 INIT_INI_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
617 ar9271Modes_high_power_tx_gain_9271,
618 ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 6);
619 INIT_INI_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
620 ar9271Modes_normal_power_tx_gain_9271,
621 ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 6);
622 return;
623 }
624
625 if (AR_SREV_9287_11_OR_LATER(ah)) {
626 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
627 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
628 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
629 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
630 if (ah->config.pcie_clock_req)
631 INIT_INI_ARRAY(&ah->iniPcieSerdes,
632 ar9287PciePhy_clkreq_off_L1_9287_1_1,
633 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
634 else
635 INIT_INI_ARRAY(&ah->iniPcieSerdes,
636 ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
637 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
638 2);
639 } else if (AR_SREV_9287_10_OR_LATER(ah)) {
640 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
641 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
642 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
643 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
644
645 if (ah->config.pcie_clock_req)
646 INIT_INI_ARRAY(&ah->iniPcieSerdes,
647 ar9287PciePhy_clkreq_off_L1_9287_1_0,
648 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
649 else
650 INIT_INI_ARRAY(&ah->iniPcieSerdes,
651 ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
652 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
653 2);
654 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
655
656
657 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
658 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
659 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
660 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
661
662 if (ah->config.pcie_clock_req) {
663 INIT_INI_ARRAY(&ah->iniPcieSerdes,
664 ar9285PciePhy_clkreq_off_L1_9285_1_2,
665 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
666 } else {
667 INIT_INI_ARRAY(&ah->iniPcieSerdes,
668 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
669 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
670 2);
671 }
672 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
673 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
674 ARRAY_SIZE(ar9285Modes_9285), 6);
675 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
676 ARRAY_SIZE(ar9285Common_9285), 2);
677
678 if (ah->config.pcie_clock_req) {
679 INIT_INI_ARRAY(&ah->iniPcieSerdes,
680 ar9285PciePhy_clkreq_off_L1_9285,
681 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
682 } else {
683 INIT_INI_ARRAY(&ah->iniPcieSerdes,
684 ar9285PciePhy_clkreq_always_on_L1_9285,
685 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
686 }
687 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
688 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
689 ARRAY_SIZE(ar9280Modes_9280_2), 6);
690 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
691 ARRAY_SIZE(ar9280Common_9280_2), 2);
692
693 if (ah->config.pcie_clock_req) {
694 INIT_INI_ARRAY(&ah->iniPcieSerdes,
695 ar9280PciePhy_clkreq_off_L1_9280,
696 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
697 } else {
698 INIT_INI_ARRAY(&ah->iniPcieSerdes,
699 ar9280PciePhy_clkreq_always_on_L1_9280,
700 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
701 }
702 INIT_INI_ARRAY(&ah->iniModesAdditional,
703 ar9280Modes_fast_clock_9280_2,
704 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
705 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
706 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
707 ARRAY_SIZE(ar9280Modes_9280), 6);
708 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
709 ARRAY_SIZE(ar9280Common_9280), 2);
710 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
711 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
712 ARRAY_SIZE(ar5416Modes_9160), 6);
713 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
714 ARRAY_SIZE(ar5416Common_9160), 2);
715 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
716 ARRAY_SIZE(ar5416Bank0_9160), 2);
717 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
718 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
719 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
720 ARRAY_SIZE(ar5416Bank1_9160), 2);
721 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
722 ARRAY_SIZE(ar5416Bank2_9160), 2);
723 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
724 ARRAY_SIZE(ar5416Bank3_9160), 3);
725 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
726 ARRAY_SIZE(ar5416Bank6_9160), 3);
727 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
728 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
729 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
730 ARRAY_SIZE(ar5416Bank7_9160), 2);
731 if (AR_SREV_9160_11(ah)) {
732 INIT_INI_ARRAY(&ah->iniAddac,
733 ar5416Addac_91601_1,
734 ARRAY_SIZE(ar5416Addac_91601_1), 2);
735 } else {
736 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
737 ARRAY_SIZE(ar5416Addac_9160), 2);
738 }
739 } else if (AR_SREV_9100_OR_LATER(ah)) {
740 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
741 ARRAY_SIZE(ar5416Modes_9100), 6);
742 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
743 ARRAY_SIZE(ar5416Common_9100), 2);
744 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
745 ARRAY_SIZE(ar5416Bank0_9100), 2);
746 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
747 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
748 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
749 ARRAY_SIZE(ar5416Bank1_9100), 2);
750 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
751 ARRAY_SIZE(ar5416Bank2_9100), 2);
752 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
753 ARRAY_SIZE(ar5416Bank3_9100), 3);
754 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
755 ARRAY_SIZE(ar5416Bank6_9100), 3);
756 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
757 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
758 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
759 ARRAY_SIZE(ar5416Bank7_9100), 2);
760 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
761 ARRAY_SIZE(ar5416Addac_9100), 2);
762 } else {
763 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
764 ARRAY_SIZE(ar5416Modes), 6);
765 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
766 ARRAY_SIZE(ar5416Common), 2);
767 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
768 ARRAY_SIZE(ar5416Bank0), 2);
769 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
770 ARRAY_SIZE(ar5416BB_RfGain), 3);
771 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
772 ARRAY_SIZE(ar5416Bank1), 2);
773 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
774 ARRAY_SIZE(ar5416Bank2), 2);
775 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
776 ARRAY_SIZE(ar5416Bank3), 3);
777 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
778 ARRAY_SIZE(ar5416Bank6), 3);
779 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
780 ARRAY_SIZE(ar5416Bank6TPC), 3);
781 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
782 ARRAY_SIZE(ar5416Bank7), 2);
783 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
784 ARRAY_SIZE(ar5416Addac), 2);
785 }
786}
787
788static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
789{
790 if (AR_SREV_9287_11_OR_LATER(ah))
791 INIT_INI_ARRAY(&ah->iniModesRxGain,
792 ar9287Modes_rx_gain_9287_1_1,
793 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
794 else if (AR_SREV_9287_10(ah))
795 INIT_INI_ARRAY(&ah->iniModesRxGain,
796 ar9287Modes_rx_gain_9287_1_0,
797 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
798 else if (AR_SREV_9280_20(ah))
799 ath9k_hw_init_rxgain_ini(ah);
800
801 if (AR_SREV_9287_11_OR_LATER(ah)) {
802 INIT_INI_ARRAY(&ah->iniModesTxGain,
803 ar9287Modes_tx_gain_9287_1_1,
804 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
805 } else if (AR_SREV_9287_10(ah)) {
806 INIT_INI_ARRAY(&ah->iniModesTxGain,
807 ar9287Modes_tx_gain_9287_1_0,
808 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
809 } else if (AR_SREV_9280_20(ah)) {
810 ath9k_hw_init_txgain_ini(ah);
811 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
812 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
813
814 /* txgain table */
815 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
816 if (AR_SREV_9285E_20(ah)) {
817 INIT_INI_ARRAY(&ah->iniModesTxGain,
818 ar9285Modes_XE2_0_high_power,
819 ARRAY_SIZE(
820 ar9285Modes_XE2_0_high_power), 6);
821 } else {
822 INIT_INI_ARRAY(&ah->iniModesTxGain,
823 ar9285Modes_high_power_tx_gain_9285_1_2,
824 ARRAY_SIZE(
825 ar9285Modes_high_power_tx_gain_9285_1_2), 6);
826 }
827 } else {
828 if (AR_SREV_9285E_20(ah)) {
829 INIT_INI_ARRAY(&ah->iniModesTxGain,
830 ar9285Modes_XE2_0_normal_power,
831 ARRAY_SIZE(
832 ar9285Modes_XE2_0_normal_power), 6);
833 } else {
834 INIT_INI_ARRAY(&ah->iniModesTxGain,
835 ar9285Modes_original_tx_gain_9285_1_2,
836 ARRAY_SIZE(
837 ar9285Modes_original_tx_gain_9285_1_2), 6);
838 }
839 }
840 }
841}
842
843static void ath9k_hw_init_eeprom_fix(struct ath_hw *ah)
844{
845 struct base_eep_header *pBase = &(ah->eeprom.def.baseEepHeader);
846 struct ath_common *common = ath9k_hw_common(ah);
847
848 ah->need_an_top2_fixup = (ah->hw_version.devid == AR9280_DEVID_PCI) &&
849 (ah->eep_map != EEP_MAP_4KBITS) &&
850 ((pBase->version & 0xff) > 0x0a) &&
851 (pBase->pwdclkind == 0);
852
853 if (ah->need_an_top2_fixup)
854 ath_print(common, ATH_DBG_EEPROM,
855 "needs fixup for AR_AN_TOP2 register\n");
856} 511}
857 512
858int ath9k_hw_init(struct ath_hw *ah) 513/* Called for all hardware families */
514static int __ath9k_hw_init(struct ath_hw *ah)
859{ 515{
860 struct ath_common *common = ath9k_hw_common(ah); 516 struct ath_common *common = ath9k_hw_common(ah);
861 int r = 0; 517 int r = 0;
862 518
863 if (common->bus_ops->ath_bus_type != ATH_USB) { 519 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
864 if (!ath9k_hw_devid_supported(ah->hw_version.devid)) { 520 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
865 ath_print(common, ATH_DBG_FATAL,
866 "Unsupported device ID: 0x%0x\n",
867 ah->hw_version.devid);
868 return -EOPNOTSUPP;
869 }
870 }
871
872 ath9k_hw_init_defaults(ah);
873 ath9k_hw_init_config(ah);
874 521
875 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 522 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
876 ath_print(common, ATH_DBG_FATAL, 523 ath_print(common, ATH_DBG_FATAL,
@@ -878,6 +525,11 @@ int ath9k_hw_init(struct ath_hw *ah)
878 return -EIO; 525 return -EIO;
879 } 526 }
880 527
528 ath9k_hw_init_defaults(ah);
529 ath9k_hw_init_config(ah);
530
531 ath9k_hw_attach_ops(ah);
532
881 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 533 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
882 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n"); 534 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
883 return -EIO; 535 return -EIO;
@@ -902,7 +554,7 @@ int ath9k_hw_init(struct ath_hw *ah)
902 else 554 else
903 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; 555 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
904 556
905 if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) { 557 if (!ath9k_hw_macversion_supported(ah)) {
906 ath_print(common, ATH_DBG_FATAL, 558 ath_print(common, ATH_DBG_FATAL,
907 "Mac Chip Rev 0x%02x.%x is not supported by " 559 "Mac Chip Rev 0x%02x.%x is not supported by "
908 "this driver\n", ah->hw_version.macVersion, 560 "this driver\n", ah->hw_version.macVersion,
@@ -910,28 +562,15 @@ int ath9k_hw_init(struct ath_hw *ah)
910 return -EOPNOTSUPP; 562 return -EOPNOTSUPP;
911 } 563 }
912 564
913 if (AR_SREV_9100(ah)) { 565 if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
914 ah->iq_caldata.calData = &iq_cal_multi_sample;
915 ah->supp_cals = IQ_MISMATCH_CAL;
916 ah->is_pciexpress = false;
917 }
918
919 if (AR_SREV_9271(ah))
920 ah->is_pciexpress = false; 566 ah->is_pciexpress = false;
921 567
922 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 568 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
923
924 ath9k_hw_init_cal_settings(ah); 569 ath9k_hw_init_cal_settings(ah);
925 570
926 ah->ani_function = ATH9K_ANI_ALL; 571 ah->ani_function = ATH9K_ANI_ALL;
927 if (AR_SREV_9280_10_OR_LATER(ah)) { 572 if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
928 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; 573 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
929 ah->ath9k_hw_rf_set_freq = &ath9k_hw_ar9280_set_channel;
930 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_9280_spur_mitigate;
931 } else {
932 ah->ath9k_hw_rf_set_freq = &ath9k_hw_set_channel;
933 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_spur_mitigate;
934 }
935 574
936 ath9k_hw_init_mode_regs(ah); 575 ath9k_hw_init_mode_regs(ah);
937 576
@@ -940,15 +579,8 @@ int ath9k_hw_init(struct ath_hw *ah)
940 else 579 else
941 ath9k_hw_disablepcie(ah); 580 ath9k_hw_disablepcie(ah);
942 581
943 /* Support for Japan ch.14 (2484) spread */ 582 if (!AR_SREV_9300_20_OR_LATER(ah))
944 if (AR_SREV_9287_11_OR_LATER(ah)) { 583 ar9002_hw_cck_chan14_spread(ah);
945 INIT_INI_ARRAY(&ah->iniCckfirNormal,
946 ar9287Common_normal_cck_fir_coeff_92871_1,
947 ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
948 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
949 ar9287Common_japan_2484_cck_fir_coeff_92871_1,
950 ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
951 }
952 584
953 r = ath9k_hw_post_init(ah); 585 r = ath9k_hw_post_init(ah);
954 if (r) 586 if (r)
@@ -959,8 +591,6 @@ int ath9k_hw_init(struct ath_hw *ah)
959 if (r) 591 if (r)
960 return r; 592 return r;
961 593
962 ath9k_hw_init_eeprom_fix(ah);
963
964 r = ath9k_hw_init_macaddr(ah); 594 r = ath9k_hw_init_macaddr(ah);
965 if (r) { 595 if (r) {
966 ath_print(common, ATH_DBG_FATAL, 596 ath_print(common, ATH_DBG_FATAL,
@@ -973,6 +603,9 @@ int ath9k_hw_init(struct ath_hw *ah)
973 else 603 else
974 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 604 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
975 605
606 if (AR_SREV_9300_20_OR_LATER(ah))
607 ar9003_hw_set_nf_limits(ah);
608
976 ath9k_init_nfcal_hist_buffer(ah); 609 ath9k_init_nfcal_hist_buffer(ah);
977 610
978 common->state = ATH_HW_INITIALIZED; 611 common->state = ATH_HW_INITIALIZED;
@@ -980,24 +613,50 @@ int ath9k_hw_init(struct ath_hw *ah)
980 return 0; 613 return 0;
981} 614}
982 615
983static void ath9k_hw_init_bb(struct ath_hw *ah, 616int ath9k_hw_init(struct ath_hw *ah)
984 struct ath9k_channel *chan)
985{ 617{
986 u32 synthDelay; 618 int ret;
619 struct ath_common *common = ath9k_hw_common(ah);
987 620
988 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 621 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
989 if (IS_CHAN_B(chan)) 622 switch (ah->hw_version.devid) {
990 synthDelay = (4 * synthDelay) / 22; 623 case AR5416_DEVID_PCI:
991 else 624 case AR5416_DEVID_PCIE:
992 synthDelay /= 10; 625 case AR5416_AR9100_DEVID:
626 case AR9160_DEVID_PCI:
627 case AR9280_DEVID_PCI:
628 case AR9280_DEVID_PCIE:
629 case AR9285_DEVID_PCIE:
630 case AR9287_DEVID_PCI:
631 case AR9287_DEVID_PCIE:
632 case AR2427_DEVID_PCIE:
633 case AR9300_DEVID_PCIE:
634 break;
635 default:
636 if (common->bus_ops->ath_bus_type == ATH_USB)
637 break;
638 ath_print(common, ATH_DBG_FATAL,
639 "Hardware device ID 0x%04x not supported\n",
640 ah->hw_version.devid);
641 return -EOPNOTSUPP;
642 }
993 643
994 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 644 ret = __ath9k_hw_init(ah);
645 if (ret) {
646 ath_print(common, ATH_DBG_FATAL,
647 "Unable to initialize hardware; "
648 "initialization status: %d\n", ret);
649 return ret;
650 }
995 651
996 udelay(synthDelay + BASE_ACTIVATE_DELAY); 652 return 0;
997} 653}
654EXPORT_SYMBOL(ath9k_hw_init);
998 655
999static void ath9k_hw_init_qos(struct ath_hw *ah) 656static void ath9k_hw_init_qos(struct ath_hw *ah)
1000{ 657{
658 ENABLE_REGWRITE_BUFFER(ah);
659
1001 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); 660 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
1002 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); 661 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
1003 662
@@ -1011,69 +670,16 @@ static void ath9k_hw_init_qos(struct ath_hw *ah)
1011 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); 670 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
1012 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); 671 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
1013 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 672 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
673
674 REGWRITE_BUFFER_FLUSH(ah);
675 DISABLE_REGWRITE_BUFFER(ah);
1014} 676}
1015 677
1016static void ath9k_hw_init_pll(struct ath_hw *ah, 678static void ath9k_hw_init_pll(struct ath_hw *ah,
1017 struct ath9k_channel *chan) 679 struct ath9k_channel *chan)
1018{ 680{
1019 u32 pll; 681 u32 pll = ath9k_hw_compute_pll_control(ah, chan);
1020
1021 if (AR_SREV_9100(ah)) {
1022 if (chan && IS_CHAN_5GHZ(chan))
1023 pll = 0x1450;
1024 else
1025 pll = 0x1458;
1026 } else {
1027 if (AR_SREV_9280_10_OR_LATER(ah)) {
1028 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1029
1030 if (chan && IS_CHAN_HALF_RATE(chan))
1031 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1032 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1033 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1034
1035 if (chan && IS_CHAN_5GHZ(chan)) {
1036 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1037
1038 682
1039 if (AR_SREV_9280_20(ah)) {
1040 if (((chan->channel % 20) == 0)
1041 || ((chan->channel % 10) == 0))
1042 pll = 0x2850;
1043 else
1044 pll = 0x142c;
1045 }
1046 } else {
1047 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1048 }
1049
1050 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1051
1052 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1053
1054 if (chan && IS_CHAN_HALF_RATE(chan))
1055 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1056 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1057 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1058
1059 if (chan && IS_CHAN_5GHZ(chan))
1060 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1061 else
1062 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1063 } else {
1064 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1065
1066 if (chan && IS_CHAN_HALF_RATE(chan))
1067 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1068 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1069 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1070
1071 if (chan && IS_CHAN_5GHZ(chan))
1072 pll |= SM(0xa, AR_RTC_PLL_DIV);
1073 else
1074 pll |= SM(0xb, AR_RTC_PLL_DIV);
1075 }
1076 }
1077 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 683 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1078 684
1079 /* Switch the core clock for ar9271 to 117Mhz */ 685 /* Switch the core clock for ar9271 to 117Mhz */
@@ -1087,43 +693,6 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
1087 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 693 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1088} 694}
1089 695
1090static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1091{
1092 int rx_chainmask, tx_chainmask;
1093
1094 rx_chainmask = ah->rxchainmask;
1095 tx_chainmask = ah->txchainmask;
1096
1097 switch (rx_chainmask) {
1098 case 0x5:
1099 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1100 AR_PHY_SWAP_ALT_CHAIN);
1101 case 0x3:
1102 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
1103 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1104 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1105 break;
1106 }
1107 case 0x1:
1108 case 0x2:
1109 case 0x7:
1110 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1111 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1112 break;
1113 default:
1114 break;
1115 }
1116
1117 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1118 if (tx_chainmask == 0x5) {
1119 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1120 AR_PHY_SWAP_ALT_CHAIN);
1121 }
1122 if (AR_SREV_9100(ah))
1123 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1124 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1125}
1126
1127static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, 696static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1128 enum nl80211_iftype opmode) 697 enum nl80211_iftype opmode)
1129{ 698{
@@ -1133,16 +702,30 @@ static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1133 AR_IMR_RXORN | 702 AR_IMR_RXORN |
1134 AR_IMR_BCNMISC; 703 AR_IMR_BCNMISC;
1135 704
1136 if (ah->config.rx_intr_mitigation) 705 if (AR_SREV_9300_20_OR_LATER(ah)) {
1137 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 706 imr_reg |= AR_IMR_RXOK_HP;
1138 else 707 if (ah->config.rx_intr_mitigation)
1139 imr_reg |= AR_IMR_RXOK; 708 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
709 else
710 imr_reg |= AR_IMR_RXOK_LP;
1140 711
1141 imr_reg |= AR_IMR_TXOK; 712 } else {
713 if (ah->config.rx_intr_mitigation)
714 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
715 else
716 imr_reg |= AR_IMR_RXOK;
717 }
718
719 if (ah->config.tx_intr_mitigation)
720 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
721 else
722 imr_reg |= AR_IMR_TXOK;
1142 723
1143 if (opmode == NL80211_IFTYPE_AP) 724 if (opmode == NL80211_IFTYPE_AP)
1144 imr_reg |= AR_IMR_MIB; 725 imr_reg |= AR_IMR_MIB;
1145 726
727 ENABLE_REGWRITE_BUFFER(ah);
728
1146 REG_WRITE(ah, AR_IMR, imr_reg); 729 REG_WRITE(ah, AR_IMR, imr_reg);
1147 ah->imrs2_reg |= AR_IMR_S2_GTT; 730 ah->imrs2_reg |= AR_IMR_S2_GTT;
1148 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); 731 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
@@ -1152,6 +735,16 @@ static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1152 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT); 735 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1153 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); 736 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1154 } 737 }
738
739 REGWRITE_BUFFER_FLUSH(ah);
740 DISABLE_REGWRITE_BUFFER(ah);
741
742 if (AR_SREV_9300_20_OR_LATER(ah)) {
743 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
744 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
745 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
746 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
747 }
1155} 748}
1156 749
1157static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) 750static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
@@ -1237,14 +830,10 @@ void ath9k_hw_deinit(struct ath_hw *ah)
1237 if (common->state < ATH_HW_INITIALIZED) 830 if (common->state < ATH_HW_INITIALIZED)
1238 goto free_hw; 831 goto free_hw;
1239 832
1240 if (!AR_SREV_9100(ah))
1241 ath9k_hw_ani_disable(ah);
1242
1243 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 833 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1244 834
1245free_hw: 835free_hw:
1246 if (!AR_SREV_9280_10_OR_LATER(ah)) 836 ath9k_hw_rf_free_ext_banks(ah);
1247 ath9k_hw_rf_free_ext_banks(ah);
1248} 837}
1249EXPORT_SYMBOL(ath9k_hw_deinit); 838EXPORT_SYMBOL(ath9k_hw_deinit);
1250 839
@@ -1252,73 +841,7 @@ EXPORT_SYMBOL(ath9k_hw_deinit);
1252/* INI */ 841/* INI */
1253/*******/ 842/*******/
1254 843
1255static void ath9k_hw_override_ini(struct ath_hw *ah, 844u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
1256 struct ath9k_channel *chan)
1257{
1258 u32 val;
1259
1260 /*
1261 * Set the RX_ABORT and RX_DIS and clear if off only after
1262 * RXE is set for MAC. This prevents frames with corrupted
1263 * descriptor status.
1264 */
1265 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1266
1267 if (AR_SREV_9280_10_OR_LATER(ah)) {
1268 val = REG_READ(ah, AR_PCU_MISC_MODE2);
1269
1270 if (!AR_SREV_9271(ah))
1271 val &= ~AR_PCU_MISC_MODE2_HWWAR1;
1272
1273 if (AR_SREV_9287_10_OR_LATER(ah))
1274 val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
1275
1276 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
1277 }
1278
1279 if (!AR_SREV_5416_20_OR_LATER(ah) ||
1280 AR_SREV_9280_10_OR_LATER(ah))
1281 return;
1282 /*
1283 * Disable BB clock gating
1284 * Necessary to avoid issues on AR5416 2.0
1285 */
1286 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1287
1288 /*
1289 * Disable RIFS search on some chips to avoid baseband
1290 * hang issues.
1291 */
1292 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
1293 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
1294 val &= ~AR_PHY_RIFS_INIT_DELAY;
1295 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
1296 }
1297}
1298
1299static void ath9k_olc_init(struct ath_hw *ah)
1300{
1301 u32 i;
1302
1303 if (OLC_FOR_AR9287_10_LATER) {
1304 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
1305 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
1306 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
1307 AR9287_AN_TXPC0_TXPCMODE,
1308 AR9287_AN_TXPC0_TXPCMODE_S,
1309 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
1310 udelay(100);
1311 } else {
1312 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1313 ah->originalGain[i] =
1314 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1315 AR_PHY_TX_GAIN);
1316 ah->PDADCdelta = 0;
1317 }
1318}
1319
1320static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1321 struct ath9k_channel *chan)
1322{ 845{
1323 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); 846 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1324 847
@@ -1332,193 +855,24 @@ static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1332 return ctl; 855 return ctl;
1333} 856}
1334 857
1335static int ath9k_hw_process_ini(struct ath_hw *ah,
1336 struct ath9k_channel *chan)
1337{
1338 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1339 int i, regWrites = 0;
1340 struct ieee80211_channel *channel = chan->chan;
1341 u32 modesIndex, freqIndex;
1342
1343 switch (chan->chanmode) {
1344 case CHANNEL_A:
1345 case CHANNEL_A_HT20:
1346 modesIndex = 1;
1347 freqIndex = 1;
1348 break;
1349 case CHANNEL_A_HT40PLUS:
1350 case CHANNEL_A_HT40MINUS:
1351 modesIndex = 2;
1352 freqIndex = 1;
1353 break;
1354 case CHANNEL_G:
1355 case CHANNEL_G_HT20:
1356 case CHANNEL_B:
1357 modesIndex = 4;
1358 freqIndex = 2;
1359 break;
1360 case CHANNEL_G_HT40PLUS:
1361 case CHANNEL_G_HT40MINUS:
1362 modesIndex = 3;
1363 freqIndex = 2;
1364 break;
1365
1366 default:
1367 return -EINVAL;
1368 }
1369
1370 /* Set correct baseband to analog shift setting to access analog chips */
1371 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1372
1373 /* Write ADDAC shifts */
1374 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1375 ah->eep_ops->set_addac(ah, chan);
1376
1377 if (AR_SREV_5416_22_OR_LATER(ah)) {
1378 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1379 } else {
1380 struct ar5416IniArray temp;
1381 u32 addacSize =
1382 sizeof(u32) * ah->iniAddac.ia_rows *
1383 ah->iniAddac.ia_columns;
1384
1385 /* For AR5416 2.0/2.1 */
1386 memcpy(ah->addac5416_21,
1387 ah->iniAddac.ia_array, addacSize);
1388
1389 /* override CLKDRV value at [row, column] = [31, 1] */
1390 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1391
1392 temp.ia_array = ah->addac5416_21;
1393 temp.ia_columns = ah->iniAddac.ia_columns;
1394 temp.ia_rows = ah->iniAddac.ia_rows;
1395 REG_WRITE_ARRAY(&temp, 1, regWrites);
1396 }
1397
1398 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1399
1400 for (i = 0; i < ah->iniModes.ia_rows; i++) {
1401 u32 reg = INI_RA(&ah->iniModes, i, 0);
1402 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1403
1404 if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup)
1405 val &= ~AR_AN_TOP2_PWDCLKIND;
1406
1407 REG_WRITE(ah, reg, val);
1408
1409 if (reg >= 0x7800 && reg < 0x78a0
1410 && ah->config.analog_shiftreg) {
1411 udelay(100);
1412 }
1413
1414 DO_DELAY(regWrites);
1415 }
1416
1417 if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1418 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1419
1420 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1421 AR_SREV_9287_10_OR_LATER(ah))
1422 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1423
1424 if (AR_SREV_9271_10(ah))
1425 REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
1426 modesIndex, regWrites);
1427
1428 /* Write common array parameters */
1429 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1430 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1431 u32 val = INI_RA(&ah->iniCommon, i, 1);
1432
1433 REG_WRITE(ah, reg, val);
1434
1435 if (reg >= 0x7800 && reg < 0x78a0
1436 && ah->config.analog_shiftreg) {
1437 udelay(100);
1438 }
1439
1440 DO_DELAY(regWrites);
1441 }
1442
1443 if (AR_SREV_9271(ah)) {
1444 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1)
1445 REG_WRITE_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
1446 modesIndex, regWrites);
1447 else
1448 REG_WRITE_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
1449 modesIndex, regWrites);
1450 }
1451
1452 ath9k_hw_write_regs(ah, freqIndex, regWrites);
1453
1454 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1455 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1456 regWrites);
1457 }
1458
1459 ath9k_hw_override_ini(ah, chan);
1460 ath9k_hw_set_regs(ah, chan);
1461 ath9k_hw_init_chain_masks(ah);
1462
1463 if (OLC_FOR_AR9280_20_LATER)
1464 ath9k_olc_init(ah);
1465
1466 /* Set TX power */
1467 ah->eep_ops->set_txpower(ah, chan,
1468 ath9k_regd_get_ctl(regulatory, chan),
1469 channel->max_antenna_gain * 2,
1470 channel->max_power * 2,
1471 min((u32) MAX_RATE_POWER,
1472 (u32) regulatory->power_limit));
1473
1474 /* Write analog registers */
1475 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1476 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1477 "ar5416SetRfRegs failed\n");
1478 return -EIO;
1479 }
1480
1481 return 0;
1482}
1483
1484/****************************************/ 858/****************************************/
1485/* Reset and Channel Switching Routines */ 859/* Reset and Channel Switching Routines */
1486/****************************************/ 860/****************************************/
1487 861
1488static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1489{
1490 u32 rfMode = 0;
1491
1492 if (chan == NULL)
1493 return;
1494
1495 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1496 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1497
1498 if (!AR_SREV_9280_10_OR_LATER(ah))
1499 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1500 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1501
1502 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1503 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1504
1505 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1506}
1507
1508static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1509{
1510 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1511}
1512
1513static inline void ath9k_hw_set_dma(struct ath_hw *ah) 862static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1514{ 863{
864 struct ath_common *common = ath9k_hw_common(ah);
1515 u32 regval; 865 u32 regval;
1516 866
867 ENABLE_REGWRITE_BUFFER(ah);
868
1517 /* 869 /*
1518 * set AHB_MODE not to do cacheline prefetches 870 * set AHB_MODE not to do cacheline prefetches
1519 */ 871 */
1520 regval = REG_READ(ah, AR_AHB_MODE); 872 if (!AR_SREV_9300_20_OR_LATER(ah)) {
1521 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN); 873 regval = REG_READ(ah, AR_AHB_MODE);
874 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
875 }
1522 876
1523 /* 877 /*
1524 * let mac dma reads be in 128 byte chunks 878 * let mac dma reads be in 128 byte chunks
@@ -1526,12 +880,18 @@ static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1526 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK; 880 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1527 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B); 881 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1528 882
883 REGWRITE_BUFFER_FLUSH(ah);
884 DISABLE_REGWRITE_BUFFER(ah);
885
1529 /* 886 /*
1530 * Restore TX Trigger Level to its pre-reset value. 887 * Restore TX Trigger Level to its pre-reset value.
1531 * The initial value depends on whether aggregation is enabled, and is 888 * The initial value depends on whether aggregation is enabled, and is
1532 * adjusted whenever underruns are detected. 889 * adjusted whenever underruns are detected.
1533 */ 890 */
1534 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); 891 if (!AR_SREV_9300_20_OR_LATER(ah))
892 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
893
894 ENABLE_REGWRITE_BUFFER(ah);
1535 895
1536 /* 896 /*
1537 * let mac dma writes be in 128 byte chunks 897 * let mac dma writes be in 128 byte chunks
@@ -1544,6 +904,14 @@ static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1544 */ 904 */
1545 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); 905 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1546 906
907 if (AR_SREV_9300_20_OR_LATER(ah)) {
908 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
909 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
910
911 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
912 ah->caps.rx_status_len);
913 }
914
1547 /* 915 /*
1548 * reduce the number of usable entries in PCU TXBUF to avoid 916 * reduce the number of usable entries in PCU TXBUF to avoid
1549 * wrap around issues. 917 * wrap around issues.
@@ -1559,6 +927,12 @@ static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1559 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 927 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1560 AR_PCU_TXBUF_CTRL_USABLE_SIZE); 928 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1561 } 929 }
930
931 REGWRITE_BUFFER_FLUSH(ah);
932 DISABLE_REGWRITE_BUFFER(ah);
933
934 if (AR_SREV_9300_20_OR_LATER(ah))
935 ath9k_hw_reset_txstatus_ring(ah);
1562} 936}
1563 937
1564static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) 938static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
@@ -1586,10 +960,8 @@ static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1586 } 960 }
1587} 961}
1588 962
1589static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, 963void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1590 u32 coef_scaled, 964 u32 *coef_mantissa, u32 *coef_exponent)
1591 u32 *coef_mantissa,
1592 u32 *coef_exponent)
1593{ 965{
1594 u32 coef_exp, coef_man; 966 u32 coef_exp, coef_man;
1595 967
@@ -1605,40 +977,6 @@ static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1605 *coef_exponent = coef_exp - 16; 977 *coef_exponent = coef_exp - 16;
1606} 978}
1607 979
1608static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1609 struct ath9k_channel *chan)
1610{
1611 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1612 u32 clockMhzScaled = 0x64000000;
1613 struct chan_centers centers;
1614
1615 if (IS_CHAN_HALF_RATE(chan))
1616 clockMhzScaled = clockMhzScaled >> 1;
1617 else if (IS_CHAN_QUARTER_RATE(chan))
1618 clockMhzScaled = clockMhzScaled >> 2;
1619
1620 ath9k_hw_get_channel_centers(ah, chan, &centers);
1621 coef_scaled = clockMhzScaled / centers.synth_center;
1622
1623 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1624 &ds_coef_exp);
1625
1626 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1627 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1628 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1629 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1630
1631 coef_scaled = (9 * coef_scaled) / 10;
1632
1633 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1634 &ds_coef_exp);
1635
1636 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1637 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1638 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1639 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1640}
1641
1642static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) 980static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1643{ 981{
1644 u32 rst_flags; 982 u32 rst_flags;
@@ -1652,6 +990,8 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1652 (void)REG_READ(ah, AR_RTC_DERIVED_CLK); 990 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1653 } 991 }
1654 992
993 ENABLE_REGWRITE_BUFFER(ah);
994
1655 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 995 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1656 AR_RTC_FORCE_WAKE_ON_INT); 996 AR_RTC_FORCE_WAKE_ON_INT);
1657 997
@@ -1663,11 +1003,16 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1663 if (tmpReg & 1003 if (tmpReg &
1664 (AR_INTR_SYNC_LOCAL_TIMEOUT | 1004 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1665 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { 1005 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1006 u32 val;
1666 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 1007 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1667 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 1008
1668 } else { 1009 val = AR_RC_HOSTIF;
1010 if (!AR_SREV_9300_20_OR_LATER(ah))
1011 val |= AR_RC_AHB;
1012 REG_WRITE(ah, AR_RC, val);
1013
1014 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1669 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1015 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1670 }
1671 1016
1672 rst_flags = AR_RTC_RC_MAC_WARM; 1017 rst_flags = AR_RTC_RC_MAC_WARM;
1673 if (type == ATH9K_RESET_COLD) 1018 if (type == ATH9K_RESET_COLD)
@@ -1675,6 +1020,10 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1675 } 1020 }
1676 1021
1677 REG_WRITE(ah, AR_RTC_RC, rst_flags); 1022 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1023
1024 REGWRITE_BUFFER_FLUSH(ah);
1025 DISABLE_REGWRITE_BUFFER(ah);
1026
1678 udelay(50); 1027 udelay(50);
1679 1028
1680 REG_WRITE(ah, AR_RTC_RC, 0); 1029 REG_WRITE(ah, AR_RTC_RC, 0);
@@ -1695,16 +1044,23 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1695 1044
1696static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) 1045static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1697{ 1046{
1047 ENABLE_REGWRITE_BUFFER(ah);
1048
1698 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1049 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1699 AR_RTC_FORCE_WAKE_ON_INT); 1050 AR_RTC_FORCE_WAKE_ON_INT);
1700 1051
1701 if (!AR_SREV_9100(ah)) 1052 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1702 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1053 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1703 1054
1704 REG_WRITE(ah, AR_RTC_RESET, 0); 1055 REG_WRITE(ah, AR_RTC_RESET, 0);
1705 udelay(2);
1706 1056
1707 if (!AR_SREV_9100(ah)) 1057 REGWRITE_BUFFER_FLUSH(ah);
1058 DISABLE_REGWRITE_BUFFER(ah);
1059
1060 if (!AR_SREV_9300_20_OR_LATER(ah))
1061 udelay(2);
1062
1063 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1708 REG_WRITE(ah, AR_RC, 0); 1064 REG_WRITE(ah, AR_RC, 0);
1709 1065
1710 REG_WRITE(ah, AR_RTC_RESET, 1); 1066 REG_WRITE(ah, AR_RTC_RESET, 1);
@@ -1740,34 +1096,6 @@ static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1740 } 1096 }
1741} 1097}
1742 1098
1743static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan)
1744{
1745 u32 phymode;
1746 u32 enableDacFifo = 0;
1747
1748 if (AR_SREV_9285_10_OR_LATER(ah))
1749 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1750 AR_PHY_FC_ENABLE_DAC_FIFO);
1751
1752 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1753 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1754
1755 if (IS_CHAN_HT40(chan)) {
1756 phymode |= AR_PHY_FC_DYN2040_EN;
1757
1758 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1759 (chan->chanmode == CHANNEL_G_HT40PLUS))
1760 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1761
1762 }
1763 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1764
1765 ath9k_hw_set11nmac2040(ah);
1766
1767 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1768 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1769}
1770
1771static bool ath9k_hw_chip_reset(struct ath_hw *ah, 1099static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1772 struct ath9k_channel *chan) 1100 struct ath9k_channel *chan)
1773{ 1101{
@@ -1793,7 +1121,7 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1793 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 1121 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1794 struct ath_common *common = ath9k_hw_common(ah); 1122 struct ath_common *common = ath9k_hw_common(ah);
1795 struct ieee80211_channel *channel = chan->chan; 1123 struct ieee80211_channel *channel = chan->chan;
1796 u32 synthDelay, qnum; 1124 u32 qnum;
1797 int r; 1125 int r;
1798 1126
1799 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1127 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
@@ -1805,17 +1133,15 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1805 } 1133 }
1806 } 1134 }
1807 1135
1808 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); 1136 if (!ath9k_hw_rfbus_req(ah)) {
1809 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1810 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1811 ath_print(common, ATH_DBG_FATAL, 1137 ath_print(common, ATH_DBG_FATAL,
1812 "Could not kill baseband RX\n"); 1138 "Could not kill baseband RX\n");
1813 return false; 1139 return false;
1814 } 1140 }
1815 1141
1816 ath9k_hw_set_regs(ah, chan); 1142 ath9k_hw_set_channel_regs(ah, chan);
1817 1143
1818 r = ah->ath9k_hw_rf_set_freq(ah, chan); 1144 r = ath9k_hw_rf_set_freq(ah, chan);
1819 if (r) { 1145 if (r) {
1820 ath_print(common, ATH_DBG_FATAL, 1146 ath_print(common, ATH_DBG_FATAL,
1821 "Failed to set channel\n"); 1147 "Failed to set channel\n");
@@ -1829,20 +1155,12 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1829 min((u32) MAX_RATE_POWER, 1155 min((u32) MAX_RATE_POWER,
1830 (u32) regulatory->power_limit)); 1156 (u32) regulatory->power_limit));
1831 1157
1832 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 1158 ath9k_hw_rfbus_done(ah);
1833 if (IS_CHAN_B(chan))
1834 synthDelay = (4 * synthDelay) / 22;
1835 else
1836 synthDelay /= 10;
1837
1838 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1839
1840 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1841 1159
1842 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1160 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1843 ath9k_hw_set_delta_slope(ah, chan); 1161 ath9k_hw_set_delta_slope(ah, chan);
1844 1162
1845 ah->ath9k_hw_spur_mitigate_freq(ah, chan); 1163 ath9k_hw_spur_mitigate_freq(ah, chan);
1846 1164
1847 if (!chan->oneTimeCalsDone) 1165 if (!chan->oneTimeCalsDone)
1848 chan->oneTimeCalsDone = true; 1166 chan->oneTimeCalsDone = true;
@@ -1850,17 +1168,33 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1850 return true; 1168 return true;
1851} 1169}
1852 1170
1853static void ath9k_enable_rfkill(struct ath_hw *ah) 1171bool ath9k_hw_check_alive(struct ath_hw *ah)
1854{ 1172{
1855 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, 1173 int count = 50;
1856 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB); 1174 u32 reg;
1175
1176 if (AR_SREV_9285_10_OR_LATER(ah))
1177 return true;
1178
1179 do {
1180 reg = REG_READ(ah, AR_OBS_BUS_1);
1857 1181
1858 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2, 1182 if ((reg & 0x7E7FFFEF) == 0x00702400)
1859 AR_GPIO_INPUT_MUX2_RFSILENT); 1183 continue;
1860 1184
1861 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio); 1185 switch (reg & 0x7E000B00) {
1862 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB); 1186 case 0x1E000000:
1187 case 0x52000B00:
1188 case 0x18000B00:
1189 continue;
1190 default:
1191 return true;
1192 }
1193 } while (count-- > 0);
1194
1195 return false;
1863} 1196}
1197EXPORT_SYMBOL(ath9k_hw_check_alive);
1864 1198
1865int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 1199int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1866 bool bChannelChange) 1200 bool bChannelChange)
@@ -1871,11 +1205,18 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1871 u32 saveDefAntenna; 1205 u32 saveDefAntenna;
1872 u32 macStaId1; 1206 u32 macStaId1;
1873 u64 tsf = 0; 1207 u64 tsf = 0;
1874 int i, rx_chainmask, r; 1208 int i, r;
1875 1209
1876 ah->txchainmask = common->tx_chainmask; 1210 ah->txchainmask = common->tx_chainmask;
1877 ah->rxchainmask = common->rx_chainmask; 1211 ah->rxchainmask = common->rx_chainmask;
1878 1212
1213 if (!ah->chip_fullsleep) {
1214 ath9k_hw_abortpcurecv(ah);
1215 if (!ath9k_hw_stopdmarecv(ah))
1216 ath_print(common, ATH_DBG_XMIT,
1217 "Failed to stop receive dma\n");
1218 }
1219
1879 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1220 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1880 return -EIO; 1221 return -EIO;
1881 1222
@@ -1888,8 +1229,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1888 (chan->channel != ah->curchan->channel) && 1229 (chan->channel != ah->curchan->channel) &&
1889 ((chan->channelFlags & CHANNEL_ALL) == 1230 ((chan->channelFlags & CHANNEL_ALL) ==
1890 (ah->curchan->channelFlags & CHANNEL_ALL)) && 1231 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1891 !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) || 1232 !AR_SREV_9280(ah)) {
1892 IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
1893 1233
1894 if (ath9k_hw_channel_change(ah, chan)) { 1234 if (ath9k_hw_channel_change(ah, chan)) {
1895 ath9k_hw_loadnf(ah, ah->curchan); 1235 ath9k_hw_loadnf(ah, ah->curchan);
@@ -1943,16 +1283,6 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1943 if (AR_SREV_9280_10_OR_LATER(ah)) 1283 if (AR_SREV_9280_10_OR_LATER(ah))
1944 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 1284 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1945 1285
1946 if (AR_SREV_9287_12_OR_LATER(ah)) {
1947 /* Enable ASYNC FIFO */
1948 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1949 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
1950 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
1951 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1952 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
1953 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1954 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
1955 }
1956 r = ath9k_hw_process_ini(ah, chan); 1286 r = ath9k_hw_process_ini(ah, chan);
1957 if (r) 1287 if (r)
1958 return r; 1288 return r;
@@ -1977,9 +1307,13 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1977 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1307 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1978 ath9k_hw_set_delta_slope(ah, chan); 1308 ath9k_hw_set_delta_slope(ah, chan);
1979 1309
1980 ah->ath9k_hw_spur_mitigate_freq(ah, chan); 1310 ath9k_hw_spur_mitigate_freq(ah, chan);
1981 ah->eep_ops->set_board_values(ah, chan); 1311 ah->eep_ops->set_board_values(ah, chan);
1982 1312
1313 ath9k_hw_set_operating_mode(ah, ah->opmode);
1314
1315 ENABLE_REGWRITE_BUFFER(ah);
1316
1983 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); 1317 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1984 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4) 1318 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1985 | macStaId1 1319 | macStaId1
@@ -1987,25 +1321,27 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1987 | (ah->config. 1321 | (ah->config.
1988 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) 1322 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1989 | ah->sta_id1_defaults); 1323 | ah->sta_id1_defaults);
1990 ath9k_hw_set_operating_mode(ah, ah->opmode);
1991
1992 ath_hw_setbssidmask(common); 1324 ath_hw_setbssidmask(common);
1993
1994 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 1325 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1995
1996 ath9k_hw_write_associd(ah); 1326 ath9k_hw_write_associd(ah);
1997
1998 REG_WRITE(ah, AR_ISR, ~0); 1327 REG_WRITE(ah, AR_ISR, ~0);
1999
2000 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 1328 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2001 1329
2002 r = ah->ath9k_hw_rf_set_freq(ah, chan); 1330 REGWRITE_BUFFER_FLUSH(ah);
1331 DISABLE_REGWRITE_BUFFER(ah);
1332
1333 r = ath9k_hw_rf_set_freq(ah, chan);
2003 if (r) 1334 if (r)
2004 return r; 1335 return r;
2005 1336
1337 ENABLE_REGWRITE_BUFFER(ah);
1338
2006 for (i = 0; i < AR_NUM_DCU; i++) 1339 for (i = 0; i < AR_NUM_DCU; i++)
2007 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 1340 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2008 1341
1342 REGWRITE_BUFFER_FLUSH(ah);
1343 DISABLE_REGWRITE_BUFFER(ah);
1344
2009 ah->intr_txqs = 0; 1345 ah->intr_txqs = 0;
2010 for (i = 0; i < ah->caps.total_queues; i++) 1346 for (i = 0; i < ah->caps.total_queues; i++)
2011 ath9k_hw_resettxqueue(ah, i); 1347 ath9k_hw_resettxqueue(ah, i);
@@ -2018,25 +1354,9 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2018 1354
2019 ath9k_hw_init_global_settings(ah); 1355 ath9k_hw_init_global_settings(ah);
2020 1356
2021 if (AR_SREV_9287_12_OR_LATER(ah)) { 1357 if (!AR_SREV_9300_20_OR_LATER(ah)) {
2022 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 1358 ar9002_hw_enable_async_fifo(ah);
2023 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR); 1359 ar9002_hw_enable_wep_aggregation(ah);
2024 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2025 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2026 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2027 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2028
2029 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2030 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2031
2032 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2033 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2034 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2035 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2036 }
2037 if (AR_SREV_9287_12_OR_LATER(ah)) {
2038 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2039 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2040 } 1360 }
2041 1361
2042 REG_WRITE(ah, AR_STA_ID1, 1362 REG_WRITE(ah, AR_STA_ID1,
@@ -2051,19 +1371,24 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2051 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); 1371 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2052 } 1372 }
2053 1373
1374 if (ah->config.tx_intr_mitigation) {
1375 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1376 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1377 }
1378
2054 ath9k_hw_init_bb(ah, chan); 1379 ath9k_hw_init_bb(ah, chan);
2055 1380
2056 if (!ath9k_hw_init_cal(ah, chan)) 1381 if (!ath9k_hw_init_cal(ah, chan))
2057 return -EIO; 1382 return -EIO;
2058 1383
2059 rx_chainmask = ah->rxchainmask; 1384 ENABLE_REGWRITE_BUFFER(ah);
2060 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2061 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2062 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2063 }
2064 1385
1386 ath9k_hw_restore_chainmask(ah);
2065 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); 1387 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2066 1388
1389 REGWRITE_BUFFER_FLUSH(ah);
1390 DISABLE_REGWRITE_BUFFER(ah);
1391
2067 /* 1392 /*
2068 * For big endian systems turn on swapping for descriptors 1393 * For big endian systems turn on swapping for descriptors
2069 */ 1394 */
@@ -2093,6 +1418,11 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2093 if (ah->btcoex_hw.enabled) 1418 if (ah->btcoex_hw.enabled)
2094 ath9k_hw_btcoex_enable(ah); 1419 ath9k_hw_btcoex_enable(ah);
2095 1420
1421 if (AR_SREV_9300_20_OR_LATER(ah)) {
1422 ath9k_hw_loadnf(ah, curchan);
1423 ath9k_hw_start_nfcal(ah);
1424 }
1425
2096 return 0; 1426 return 0;
2097} 1427}
2098EXPORT_SYMBOL(ath9k_hw_reset); 1428EXPORT_SYMBOL(ath9k_hw_reset);
@@ -2379,21 +1709,35 @@ EXPORT_SYMBOL(ath9k_hw_keyisvalid);
2379/* Power Management (Chipset) */ 1709/* Power Management (Chipset) */
2380/******************************/ 1710/******************************/
2381 1711
1712/*
1713 * Notify Power Mgt is disabled in self-generated frames.
1714 * If requested, force chip to sleep.
1715 */
2382static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip) 1716static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2383{ 1717{
2384 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1718 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2385 if (setChip) { 1719 if (setChip) {
1720 /*
1721 * Clear the RTC force wake bit to allow the
1722 * mac to go to sleep.
1723 */
2386 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, 1724 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2387 AR_RTC_FORCE_WAKE_EN); 1725 AR_RTC_FORCE_WAKE_EN);
2388 if (!AR_SREV_9100(ah)) 1726 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
2389 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 1727 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2390 1728
1729 /* Shutdown chip. Active low */
2391 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) 1730 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
2392 REG_CLR_BIT(ah, (AR_RTC_RESET), 1731 REG_CLR_BIT(ah, (AR_RTC_RESET),
2393 AR_RTC_RESET_EN); 1732 AR_RTC_RESET_EN);
2394 } 1733 }
2395} 1734}
2396 1735
1736/*
1737 * Notify Power Management is enabled in self-generating
1738 * frames. If request, set power mode of chip to
1739 * auto/normal. Duration in units of 128us (1/8 TU).
1740 */
2397static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip) 1741static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2398{ 1742{
2399 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1743 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
@@ -2401,9 +1745,14 @@ static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2401 struct ath9k_hw_capabilities *pCap = &ah->caps; 1745 struct ath9k_hw_capabilities *pCap = &ah->caps;
2402 1746
2403 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1747 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1748 /* Set WakeOnInterrupt bit; clear ForceWake bit */
2404 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1749 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2405 AR_RTC_FORCE_WAKE_ON_INT); 1750 AR_RTC_FORCE_WAKE_ON_INT);
2406 } else { 1751 } else {
1752 /*
1753 * Clear the RTC force wake bit to allow the
1754 * mac to go to sleep.
1755 */
2407 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, 1756 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2408 AR_RTC_FORCE_WAKE_EN); 1757 AR_RTC_FORCE_WAKE_EN);
2409 } 1758 }
@@ -2422,7 +1771,8 @@ static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2422 ATH9K_RESET_POWER_ON) != true) { 1771 ATH9K_RESET_POWER_ON) != true) {
2423 return false; 1772 return false;
2424 } 1773 }
2425 ath9k_hw_init_pll(ah, NULL); 1774 if (!AR_SREV_9300_20_OR_LATER(ah))
1775 ath9k_hw_init_pll(ah, NULL);
2426 } 1776 }
2427 if (AR_SREV_9100(ah)) 1777 if (AR_SREV_9100(ah))
2428 REG_SET_BIT(ah, AR_RTC_RESET, 1778 REG_SET_BIT(ah, AR_RTC_RESET,
@@ -2492,420 +1842,6 @@ bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2492} 1842}
2493EXPORT_SYMBOL(ath9k_hw_setpower); 1843EXPORT_SYMBOL(ath9k_hw_setpower);
2494 1844
2495/*
2496 * Helper for ASPM support.
2497 *
2498 * Disable PLL when in L0s as well as receiver clock when in L1.
2499 * This power saving option must be enabled through the SerDes.
2500 *
2501 * Programming the SerDes must go through the same 288 bit serial shift
2502 * register as the other analog registers. Hence the 9 writes.
2503 */
2504void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
2505{
2506 u8 i;
2507 u32 val;
2508
2509 if (ah->is_pciexpress != true)
2510 return;
2511
2512 /* Do not touch SerDes registers */
2513 if (ah->config.pcie_powersave_enable == 2)
2514 return;
2515
2516 /* Nothing to do on restore for 11N */
2517 if (!restore) {
2518 if (AR_SREV_9280_20_OR_LATER(ah)) {
2519 /*
2520 * AR9280 2.0 or later chips use SerDes values from the
2521 * initvals.h initialized depending on chipset during
2522 * ath9k_hw_init()
2523 */
2524 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2525 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2526 INI_RA(&ah->iniPcieSerdes, i, 1));
2527 }
2528 } else if (AR_SREV_9280(ah) &&
2529 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2530 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2531 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2532
2533 /* RX shut off when elecidle is asserted */
2534 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2535 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2536 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2537
2538 /* Shut off CLKREQ active in L1 */
2539 if (ah->config.pcie_clock_req)
2540 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2541 else
2542 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2543
2544 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2545 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2546 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2547
2548 /* Load the new settings */
2549 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2550
2551 } else {
2552 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2553 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2554
2555 /* RX shut off when elecidle is asserted */
2556 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2557 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2558 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2559
2560 /*
2561 * Ignore ah->ah_config.pcie_clock_req setting for
2562 * pre-AR9280 11n
2563 */
2564 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2565
2566 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2567 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2568 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2569
2570 /* Load the new settings */
2571 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2572 }
2573
2574 udelay(1000);
2575
2576 /* set bit 19 to allow forcing of pcie core into L1 state */
2577 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2578
2579 /* Several PCIe massages to ensure proper behaviour */
2580 if (ah->config.pcie_waen) {
2581 val = ah->config.pcie_waen;
2582 if (!power_off)
2583 val &= (~AR_WA_D3_L1_DISABLE);
2584 } else {
2585 if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2586 AR_SREV_9287(ah)) {
2587 val = AR9285_WA_DEFAULT;
2588 if (!power_off)
2589 val &= (~AR_WA_D3_L1_DISABLE);
2590 } else if (AR_SREV_9280(ah)) {
2591 /*
2592 * On AR9280 chips bit 22 of 0x4004 needs to be
2593 * set otherwise card may disappear.
2594 */
2595 val = AR9280_WA_DEFAULT;
2596 if (!power_off)
2597 val &= (~AR_WA_D3_L1_DISABLE);
2598 } else
2599 val = AR_WA_DEFAULT;
2600 }
2601
2602 REG_WRITE(ah, AR_WA, val);
2603 }
2604
2605 if (power_off) {
2606 /*
2607 * Set PCIe workaround bits
2608 * bit 14 in WA register (disable L1) should only
2609 * be set when device enters D3 and be cleared
2610 * when device comes back to D0.
2611 */
2612 if (ah->config.pcie_waen) {
2613 if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
2614 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2615 } else {
2616 if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2617 AR_SREV_9287(ah)) &&
2618 (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
2619 (AR_SREV_9280(ah) &&
2620 (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
2621 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2622 }
2623 }
2624 }
2625}
2626EXPORT_SYMBOL(ath9k_hw_configpcipowersave);
2627
2628/**********************/
2629/* Interrupt Handling */
2630/**********************/
2631
2632bool ath9k_hw_intrpend(struct ath_hw *ah)
2633{
2634 u32 host_isr;
2635
2636 if (AR_SREV_9100(ah))
2637 return true;
2638
2639 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2640 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2641 return true;
2642
2643 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2644 if ((host_isr & AR_INTR_SYNC_DEFAULT)
2645 && (host_isr != AR_INTR_SPURIOUS))
2646 return true;
2647
2648 return false;
2649}
2650EXPORT_SYMBOL(ath9k_hw_intrpend);
2651
2652bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2653{
2654 u32 isr = 0;
2655 u32 mask2 = 0;
2656 struct ath9k_hw_capabilities *pCap = &ah->caps;
2657 u32 sync_cause = 0;
2658 bool fatal_int = false;
2659 struct ath_common *common = ath9k_hw_common(ah);
2660
2661 if (!AR_SREV_9100(ah)) {
2662 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2663 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2664 == AR_RTC_STATUS_ON) {
2665 isr = REG_READ(ah, AR_ISR);
2666 }
2667 }
2668
2669 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2670 AR_INTR_SYNC_DEFAULT;
2671
2672 *masked = 0;
2673
2674 if (!isr && !sync_cause)
2675 return false;
2676 } else {
2677 *masked = 0;
2678 isr = REG_READ(ah, AR_ISR);
2679 }
2680
2681 if (isr) {
2682 if (isr & AR_ISR_BCNMISC) {
2683 u32 isr2;
2684 isr2 = REG_READ(ah, AR_ISR_S2);
2685 if (isr2 & AR_ISR_S2_TIM)
2686 mask2 |= ATH9K_INT_TIM;
2687 if (isr2 & AR_ISR_S2_DTIM)
2688 mask2 |= ATH9K_INT_DTIM;
2689 if (isr2 & AR_ISR_S2_DTIMSYNC)
2690 mask2 |= ATH9K_INT_DTIMSYNC;
2691 if (isr2 & (AR_ISR_S2_CABEND))
2692 mask2 |= ATH9K_INT_CABEND;
2693 if (isr2 & AR_ISR_S2_GTT)
2694 mask2 |= ATH9K_INT_GTT;
2695 if (isr2 & AR_ISR_S2_CST)
2696 mask2 |= ATH9K_INT_CST;
2697 if (isr2 & AR_ISR_S2_TSFOOR)
2698 mask2 |= ATH9K_INT_TSFOOR;
2699 }
2700
2701 isr = REG_READ(ah, AR_ISR_RAC);
2702 if (isr == 0xffffffff) {
2703 *masked = 0;
2704 return false;
2705 }
2706
2707 *masked = isr & ATH9K_INT_COMMON;
2708
2709 if (ah->config.rx_intr_mitigation) {
2710 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2711 *masked |= ATH9K_INT_RX;
2712 }
2713
2714 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2715 *masked |= ATH9K_INT_RX;
2716 if (isr &
2717 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2718 AR_ISR_TXEOL)) {
2719 u32 s0_s, s1_s;
2720
2721 *masked |= ATH9K_INT_TX;
2722
2723 s0_s = REG_READ(ah, AR_ISR_S0_S);
2724 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2725 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2726
2727 s1_s = REG_READ(ah, AR_ISR_S1_S);
2728 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2729 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2730 }
2731
2732 if (isr & AR_ISR_RXORN) {
2733 ath_print(common, ATH_DBG_INTERRUPT,
2734 "receive FIFO overrun interrupt\n");
2735 }
2736
2737 if (!AR_SREV_9100(ah)) {
2738 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2739 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2740 if (isr5 & AR_ISR_S5_TIM_TIMER)
2741 *masked |= ATH9K_INT_TIM_TIMER;
2742 }
2743 }
2744
2745 *masked |= mask2;
2746 }
2747
2748 if (AR_SREV_9100(ah))
2749 return true;
2750
2751 if (isr & AR_ISR_GENTMR) {
2752 u32 s5_s;
2753
2754 s5_s = REG_READ(ah, AR_ISR_S5_S);
2755 if (isr & AR_ISR_GENTMR) {
2756 ah->intr_gen_timer_trigger =
2757 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
2758
2759 ah->intr_gen_timer_thresh =
2760 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
2761
2762 if (ah->intr_gen_timer_trigger)
2763 *masked |= ATH9K_INT_GENTIMER;
2764
2765 }
2766 }
2767
2768 if (sync_cause) {
2769 fatal_int =
2770 (sync_cause &
2771 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2772 ? true : false;
2773
2774 if (fatal_int) {
2775 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2776 ath_print(common, ATH_DBG_ANY,
2777 "received PCI FATAL interrupt\n");
2778 }
2779 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2780 ath_print(common, ATH_DBG_ANY,
2781 "received PCI PERR interrupt\n");
2782 }
2783 *masked |= ATH9K_INT_FATAL;
2784 }
2785 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2786 ath_print(common, ATH_DBG_INTERRUPT,
2787 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2788 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2789 REG_WRITE(ah, AR_RC, 0);
2790 *masked |= ATH9K_INT_FATAL;
2791 }
2792 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2793 ath_print(common, ATH_DBG_INTERRUPT,
2794 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2795 }
2796
2797 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2798 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2799 }
2800
2801 return true;
2802}
2803EXPORT_SYMBOL(ath9k_hw_getisr);
2804
2805enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
2806{
2807 enum ath9k_int omask = ah->imask;
2808 u32 mask, mask2;
2809 struct ath9k_hw_capabilities *pCap = &ah->caps;
2810 struct ath_common *common = ath9k_hw_common(ah);
2811
2812 ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
2813
2814 if (omask & ATH9K_INT_GLOBAL) {
2815 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
2816 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2817 (void) REG_READ(ah, AR_IER);
2818 if (!AR_SREV_9100(ah)) {
2819 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2820 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2821
2822 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2823 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2824 }
2825 }
2826
2827 mask = ints & ATH9K_INT_COMMON;
2828 mask2 = 0;
2829
2830 if (ints & ATH9K_INT_TX) {
2831 if (ah->txok_interrupt_mask)
2832 mask |= AR_IMR_TXOK;
2833 if (ah->txdesc_interrupt_mask)
2834 mask |= AR_IMR_TXDESC;
2835 if (ah->txerr_interrupt_mask)
2836 mask |= AR_IMR_TXERR;
2837 if (ah->txeol_interrupt_mask)
2838 mask |= AR_IMR_TXEOL;
2839 }
2840 if (ints & ATH9K_INT_RX) {
2841 mask |= AR_IMR_RXERR;
2842 if (ah->config.rx_intr_mitigation)
2843 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2844 else
2845 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
2846 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
2847 mask |= AR_IMR_GENTMR;
2848 }
2849
2850 if (ints & (ATH9K_INT_BMISC)) {
2851 mask |= AR_IMR_BCNMISC;
2852 if (ints & ATH9K_INT_TIM)
2853 mask2 |= AR_IMR_S2_TIM;
2854 if (ints & ATH9K_INT_DTIM)
2855 mask2 |= AR_IMR_S2_DTIM;
2856 if (ints & ATH9K_INT_DTIMSYNC)
2857 mask2 |= AR_IMR_S2_DTIMSYNC;
2858 if (ints & ATH9K_INT_CABEND)
2859 mask2 |= AR_IMR_S2_CABEND;
2860 if (ints & ATH9K_INT_TSFOOR)
2861 mask2 |= AR_IMR_S2_TSFOOR;
2862 }
2863
2864 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
2865 mask |= AR_IMR_BCNMISC;
2866 if (ints & ATH9K_INT_GTT)
2867 mask2 |= AR_IMR_S2_GTT;
2868 if (ints & ATH9K_INT_CST)
2869 mask2 |= AR_IMR_S2_CST;
2870 }
2871
2872 ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
2873 REG_WRITE(ah, AR_IMR, mask);
2874 ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
2875 AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
2876 AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
2877 ah->imrs2_reg |= mask2;
2878 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
2879
2880 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2881 if (ints & ATH9K_INT_TIM_TIMER)
2882 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2883 else
2884 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2885 }
2886
2887 if (ints & ATH9K_INT_GLOBAL) {
2888 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
2889 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
2890 if (!AR_SREV_9100(ah)) {
2891 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
2892 AR_INTR_MAC_IRQ);
2893 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
2894
2895
2896 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
2897 AR_INTR_SYNC_DEFAULT);
2898 REG_WRITE(ah, AR_INTR_SYNC_MASK,
2899 AR_INTR_SYNC_DEFAULT);
2900 }
2901 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
2902 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
2903 }
2904
2905 return omask;
2906}
2907EXPORT_SYMBOL(ath9k_hw_set_interrupts);
2908
2909/*******************/ 1845/*******************/
2910/* Beacon Handling */ 1846/* Beacon Handling */
2911/*******************/ 1847/*******************/
@@ -2916,6 +1852,8 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2916 1852
2917 ah->beacon_interval = beacon_period; 1853 ah->beacon_interval = beacon_period;
2918 1854
1855 ENABLE_REGWRITE_BUFFER(ah);
1856
2919 switch (ah->opmode) { 1857 switch (ah->opmode) {
2920 case NL80211_IFTYPE_STATION: 1858 case NL80211_IFTYPE_STATION:
2921 case NL80211_IFTYPE_MONITOR: 1859 case NL80211_IFTYPE_MONITOR:
@@ -2959,6 +1897,9 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2959 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period)); 1897 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
2960 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period)); 1898 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
2961 1899
1900 REGWRITE_BUFFER_FLUSH(ah);
1901 DISABLE_REGWRITE_BUFFER(ah);
1902
2962 beacon_period &= ~ATH9K_BEACON_ENA; 1903 beacon_period &= ~ATH9K_BEACON_ENA;
2963 if (beacon_period & ATH9K_BEACON_RESET_TSF) { 1904 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
2964 ath9k_hw_reset_tsf(ah); 1905 ath9k_hw_reset_tsf(ah);
@@ -2975,6 +1916,8 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
2975 struct ath9k_hw_capabilities *pCap = &ah->caps; 1916 struct ath9k_hw_capabilities *pCap = &ah->caps;
2976 struct ath_common *common = ath9k_hw_common(ah); 1917 struct ath_common *common = ath9k_hw_common(ah);
2977 1918
1919 ENABLE_REGWRITE_BUFFER(ah);
1920
2978 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); 1921 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
2979 1922
2980 REG_WRITE(ah, AR_BEACON_PERIOD, 1923 REG_WRITE(ah, AR_BEACON_PERIOD,
@@ -2982,6 +1925,9 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
2982 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, 1925 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
2983 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); 1926 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
2984 1927
1928 REGWRITE_BUFFER_FLUSH(ah);
1929 DISABLE_REGWRITE_BUFFER(ah);
1930
2985 REG_RMW_FIELD(ah, AR_RSSI_THR, 1931 REG_RMW_FIELD(ah, AR_RSSI_THR,
2986 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); 1932 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2987 1933
@@ -3004,6 +1950,8 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3004 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval); 1950 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3005 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod); 1951 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3006 1952
1953 ENABLE_REGWRITE_BUFFER(ah);
1954
3007 REG_WRITE(ah, AR_NEXT_DTIM, 1955 REG_WRITE(ah, AR_NEXT_DTIM,
3008 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); 1956 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3009 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP)); 1957 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
@@ -3023,6 +1971,9 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3023 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval)); 1971 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3024 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); 1972 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3025 1973
1974 REGWRITE_BUFFER_FLUSH(ah);
1975 DISABLE_REGWRITE_BUFFER(ah);
1976
3026 REG_SET_BIT(ah, AR_TIMER_MODE, 1977 REG_SET_BIT(ah, AR_TIMER_MODE,
3027 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | 1978 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3028 AR_DTIM_TIMER_EN); 1979 AR_DTIM_TIMER_EN);
@@ -3241,6 +2192,26 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
3241 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE; 2192 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
3242 } 2193 }
3243 2194
2195 if (AR_SREV_9300_20_OR_LATER(ah)) {
2196 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_LDPC |
2197 ATH9K_HW_CAP_FASTCLOCK;
2198 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2199 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2200 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2201 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2202 pCap->txs_len = sizeof(struct ar9003_txs);
2203 } else {
2204 pCap->tx_desc_len = sizeof(struct ath_desc);
2205 if (AR_SREV_9280_20(ah) &&
2206 ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <=
2207 AR5416_EEP_MINOR_VER_16) ||
2208 ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G)))
2209 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2210 }
2211
2212 if (AR_SREV_9300_20_OR_LATER(ah))
2213 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2214
3244 return 0; 2215 return 0;
3245} 2216}
3246 2217
@@ -3273,10 +2244,6 @@ bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3273 case ATH9K_CAP_TKIP_SPLIT: 2244 case ATH9K_CAP_TKIP_SPLIT:
3274 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ? 2245 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3275 false : true; 2246 false : true;
3276 case ATH9K_CAP_DIVERSITY:
3277 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3278 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3279 true : false;
3280 case ATH9K_CAP_MCAST_KEYSRCH: 2247 case ATH9K_CAP_MCAST_KEYSRCH:
3281 switch (capability) { 2248 switch (capability) {
3282 case 0: 2249 case 0:
@@ -3319,8 +2286,6 @@ EXPORT_SYMBOL(ath9k_hw_getcapability);
3319bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type, 2286bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3320 u32 capability, u32 setting, int *status) 2287 u32 capability, u32 setting, int *status)
3321{ 2288{
3322 u32 v;
3323
3324 switch (type) { 2289 switch (type) {
3325 case ATH9K_CAP_TKIP_MIC: 2290 case ATH9K_CAP_TKIP_MIC:
3326 if (setting) 2291 if (setting)
@@ -3330,14 +2295,6 @@ bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3330 ah->sta_id1_defaults &= 2295 ah->sta_id1_defaults &=
3331 ~AR_STA_ID1_CRPT_MIC_ENABLE; 2296 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3332 return true; 2297 return true;
3333 case ATH9K_CAP_DIVERSITY:
3334 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3335 if (setting)
3336 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3337 else
3338 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3339 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3340 return true;
3341 case ATH9K_CAP_MCAST_KEYSRCH: 2298 case ATH9K_CAP_MCAST_KEYSRCH:
3342 if (setting) 2299 if (setting)
3343 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH; 2300 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
@@ -3405,7 +2362,9 @@ u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3405 if (gpio >= ah->caps.num_gpio_pins) 2362 if (gpio >= ah->caps.num_gpio_pins)
3406 return 0xffffffff; 2363 return 0xffffffff;
3407 2364
3408 if (AR_SREV_9271(ah)) 2365 if (AR_SREV_9300_20_OR_LATER(ah))
2366 return MS_REG_READ(AR9300, gpio) != 0;
2367 else if (AR_SREV_9271(ah))
3409 return MS_REG_READ(AR9271, gpio) != 0; 2368 return MS_REG_READ(AR9271, gpio) != 0;
3410 else if (AR_SREV_9287_10_OR_LATER(ah)) 2369 else if (AR_SREV_9287_10_OR_LATER(ah))
3411 return MS_REG_READ(AR9287, gpio) != 0; 2370 return MS_REG_READ(AR9287, gpio) != 0;
@@ -3478,6 +2437,8 @@ void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3478{ 2437{
3479 u32 phybits; 2438 u32 phybits;
3480 2439
2440 ENABLE_REGWRITE_BUFFER(ah);
2441
3481 REG_WRITE(ah, AR_RX_FILTER, bits); 2442 REG_WRITE(ah, AR_RX_FILTER, bits);
3482 2443
3483 phybits = 0; 2444 phybits = 0;
@@ -3493,6 +2454,9 @@ void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3493 else 2454 else
3494 REG_WRITE(ah, AR_RXCFG, 2455 REG_WRITE(ah, AR_RXCFG,
3495 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA); 2456 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
2457
2458 REGWRITE_BUFFER_FLUSH(ah);
2459 DISABLE_REGWRITE_BUFFER(ah);
3496} 2460}
3497EXPORT_SYMBOL(ath9k_hw_setrxfilter); 2461EXPORT_SYMBOL(ath9k_hw_setrxfilter);
3498 2462
@@ -3565,14 +2529,25 @@ void ath9k_hw_write_associd(struct ath_hw *ah)
3565} 2529}
3566EXPORT_SYMBOL(ath9k_hw_write_associd); 2530EXPORT_SYMBOL(ath9k_hw_write_associd);
3567 2531
2532#define ATH9K_MAX_TSF_READ 10
2533
3568u64 ath9k_hw_gettsf64(struct ath_hw *ah) 2534u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3569{ 2535{
3570 u64 tsf; 2536 u32 tsf_lower, tsf_upper1, tsf_upper2;
2537 int i;
2538
2539 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2540 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2541 tsf_lower = REG_READ(ah, AR_TSF_L32);
2542 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2543 if (tsf_upper2 == tsf_upper1)
2544 break;
2545 tsf_upper1 = tsf_upper2;
2546 }
3571 2547
3572 tsf = REG_READ(ah, AR_TSF_U32); 2548 WARN_ON( i == ATH9K_MAX_TSF_READ );
3573 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3574 2549
3575 return tsf; 2550 return (((u64)tsf_upper1 << 32) | tsf_lower);
3576} 2551}
3577EXPORT_SYMBOL(ath9k_hw_gettsf64); 2552EXPORT_SYMBOL(ath9k_hw_gettsf64);
3578 2553
@@ -3847,6 +2822,7 @@ static struct {
3847 { AR_SREV_VERSION_9285, "9285" }, 2822 { AR_SREV_VERSION_9285, "9285" },
3848 { AR_SREV_VERSION_9287, "9287" }, 2823 { AR_SREV_VERSION_9287, "9287" },
3849 { AR_SREV_VERSION_9271, "9271" }, 2824 { AR_SREV_VERSION_9271, "9271" },
2825 { AR_SREV_VERSION_9300, "9300" },
3850}; 2826};
3851 2827
3852/* For devices with external radios */ 2828/* For devices with external radios */
diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
index f4821cf33b87..77245dff5993 100644
--- a/drivers/net/wireless/ath/ath9k/hw.h
+++ b/drivers/net/wireless/ath/ath9k/hw.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2008-2009 Atheros Communications Inc. 2 * Copyright (c) 2008-2010 Atheros Communications Inc.
3 * 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any 4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above 5 * purpose with or without fee is hereby granted, provided that the above
@@ -41,6 +41,9 @@
41#define AR9280_DEVID_PCIE 0x002a 41#define AR9280_DEVID_PCIE 0x002a
42#define AR9285_DEVID_PCIE 0x002b 42#define AR9285_DEVID_PCIE 0x002b
43#define AR2427_DEVID_PCIE 0x002c 43#define AR2427_DEVID_PCIE 0x002c
44#define AR9287_DEVID_PCI 0x002d
45#define AR9287_DEVID_PCIE 0x002e
46#define AR9300_DEVID_PCIE 0x0030
44 47
45#define AR5416_AR9100_DEVID 0x000b 48#define AR5416_AR9100_DEVID 0x000b
46 49
@@ -48,9 +51,6 @@
48#define AR_SUBVENDOR_ID_NEW_A 0x7065 51#define AR_SUBVENDOR_ID_NEW_A 0x7065
49#define AR5416_MAGIC 0x19641014 52#define AR5416_MAGIC 0x19641014
50 53
51#define AR5416_DEVID_AR9287_PCI 0x002D
52#define AR5416_DEVID_AR9287_PCIE 0x002E
53
54#define AR9280_COEX2WIRE_SUBSYSID 0x309b 54#define AR9280_COEX2WIRE_SUBSYSID 0x309b
55#define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa 55#define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
56#define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab 56#define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
@@ -68,6 +68,24 @@
68#define REG_READ(_ah, _reg) \ 68#define REG_READ(_ah, _reg) \
69 ath9k_hw_common(_ah)->ops->read((_ah), (_reg)) 69 ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
70 70
71#define ENABLE_REGWRITE_BUFFER(_ah) \
72 do { \
73 if (AR_SREV_9271(_ah)) \
74 ath9k_hw_common(_ah)->ops->enable_write_buffer((_ah)); \
75 } while (0)
76
77#define DISABLE_REGWRITE_BUFFER(_ah) \
78 do { \
79 if (AR_SREV_9271(_ah)) \
80 ath9k_hw_common(_ah)->ops->disable_write_buffer((_ah)); \
81 } while (0)
82
83#define REGWRITE_BUFFER_FLUSH(_ah) \
84 do { \
85 if (AR_SREV_9271(_ah)) \
86 ath9k_hw_common(_ah)->ops->write_flush((_ah)); \
87 } while (0)
88
71#define SM(_v, _f) (((_v) << _f##_S) & _f) 89#define SM(_v, _f) (((_v) << _f##_S) & _f)
72#define MS(_v, _f) (((_v) & _f) >> _f##_S) 90#define MS(_v, _f) (((_v) & _f) >> _f##_S)
73#define REG_RMW(_a, _r, _set, _clr) \ 91#define REG_RMW(_a, _r, _set, _clr) \
@@ -75,6 +93,8 @@
75#define REG_RMW_FIELD(_a, _r, _f, _v) \ 93#define REG_RMW_FIELD(_a, _r, _f, _v) \
76 REG_WRITE(_a, _r, \ 94 REG_WRITE(_a, _r, \
77 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f)) 95 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
96#define REG_READ_FIELD(_a, _r, _f) \
97 (((REG_READ(_a, _r) & _f) >> _f##_S))
78#define REG_SET_BIT(_a, _r, _f) \ 98#define REG_SET_BIT(_a, _r, _f) \
79 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f) 99 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
80#define REG_CLR_BIT(_a, _r, _f) \ 100#define REG_CLR_BIT(_a, _r, _f) \
@@ -135,6 +155,16 @@
135 155
136#define TU_TO_USEC(_tu) ((_tu) << 10) 156#define TU_TO_USEC(_tu) ((_tu) << 10)
137 157
158#define ATH9K_HW_RX_HP_QDEPTH 16
159#define ATH9K_HW_RX_LP_QDEPTH 128
160
161enum ath_ini_subsys {
162 ATH_INI_PRE = 0,
163 ATH_INI_CORE,
164 ATH_INI_POST,
165 ATH_INI_NUM_SPLIT,
166};
167
138enum wireless_mode { 168enum wireless_mode {
139 ATH9K_MODE_11A = 0, 169 ATH9K_MODE_11A = 0,
140 ATH9K_MODE_11G, 170 ATH9K_MODE_11G,
@@ -165,13 +195,16 @@ enum ath9k_hw_caps {
165 ATH9K_HW_CAP_ENHANCEDPM = BIT(14), 195 ATH9K_HW_CAP_ENHANCEDPM = BIT(14),
166 ATH9K_HW_CAP_AUTOSLEEP = BIT(15), 196 ATH9K_HW_CAP_AUTOSLEEP = BIT(15),
167 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(16), 197 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(16),
198 ATH9K_HW_CAP_EDMA = BIT(17),
199 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(18),
200 ATH9K_HW_CAP_LDPC = BIT(19),
201 ATH9K_HW_CAP_FASTCLOCK = BIT(20),
168}; 202};
169 203
170enum ath9k_capability_type { 204enum ath9k_capability_type {
171 ATH9K_CAP_CIPHER = 0, 205 ATH9K_CAP_CIPHER = 0,
172 ATH9K_CAP_TKIP_MIC, 206 ATH9K_CAP_TKIP_MIC,
173 ATH9K_CAP_TKIP_SPLIT, 207 ATH9K_CAP_TKIP_SPLIT,
174 ATH9K_CAP_DIVERSITY,
175 ATH9K_CAP_TXPOW, 208 ATH9K_CAP_TXPOW,
176 ATH9K_CAP_MCAST_KEYSRCH, 209 ATH9K_CAP_MCAST_KEYSRCH,
177 ATH9K_CAP_DS 210 ATH9K_CAP_DS
@@ -192,6 +225,11 @@ struct ath9k_hw_capabilities {
192 u8 num_gpio_pins; 225 u8 num_gpio_pins;
193 u8 num_antcfg_2ghz; 226 u8 num_antcfg_2ghz;
194 u8 num_antcfg_5ghz; 227 u8 num_antcfg_5ghz;
228 u8 rx_hp_qdepth;
229 u8 rx_lp_qdepth;
230 u8 rx_status_len;
231 u8 tx_desc_len;
232 u8 txs_len;
195}; 233};
196 234
197struct ath9k_ops_config { 235struct ath9k_ops_config {
@@ -212,6 +250,7 @@ struct ath9k_ops_config {
212 u32 enable_ani; 250 u32 enable_ani;
213 int serialize_regmode; 251 int serialize_regmode;
214 bool rx_intr_mitigation; 252 bool rx_intr_mitigation;
253 bool tx_intr_mitigation;
215#define SPUR_DISABLE 0 254#define SPUR_DISABLE 0
216#define SPUR_ENABLE_IOCTL 1 255#define SPUR_ENABLE_IOCTL 1
217#define SPUR_ENABLE_EEPROM 2 256#define SPUR_ENABLE_EEPROM 2
@@ -223,6 +262,7 @@ struct ath9k_ops_config {
223#define AR_BASE_FREQ_5GHZ 4900 262#define AR_BASE_FREQ_5GHZ 4900
224#define AR_SPUR_FEEQ_BOUND_HT40 19 263#define AR_SPUR_FEEQ_BOUND_HT40 19
225#define AR_SPUR_FEEQ_BOUND_HT20 10 264#define AR_SPUR_FEEQ_BOUND_HT20 10
265 bool tx_iq_calibration; /* Only available for >= AR9003 */
226 int spurmode; 266 int spurmode;
227 u16 spurchans[AR_EEPROM_MODAL_SPURS][2]; 267 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
228 u8 max_txtrig_level; 268 u8 max_txtrig_level;
@@ -231,6 +271,8 @@ struct ath9k_ops_config {
231enum ath9k_int { 271enum ath9k_int {
232 ATH9K_INT_RX = 0x00000001, 272 ATH9K_INT_RX = 0x00000001,
233 ATH9K_INT_RXDESC = 0x00000002, 273 ATH9K_INT_RXDESC = 0x00000002,
274 ATH9K_INT_RXHP = 0x00000001,
275 ATH9K_INT_RXLP = 0x00000002,
234 ATH9K_INT_RXNOFRM = 0x00000008, 276 ATH9K_INT_RXNOFRM = 0x00000008,
235 ATH9K_INT_RXEOL = 0x00000010, 277 ATH9K_INT_RXEOL = 0x00000010,
236 ATH9K_INT_RXORN = 0x00000020, 278 ATH9K_INT_RXORN = 0x00000020,
@@ -327,10 +369,9 @@ struct ath9k_channel {
327#define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0) 369#define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
328#define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0) 370#define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
329#define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0) 371#define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
330#define IS_CHAN_A_5MHZ_SPACED(_c) \ 372#define IS_CHAN_A_FAST_CLOCK(_ah, _c) \
331 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \ 373 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
332 (((_c)->channel % 20) != 0) && \ 374 ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
333 (((_c)->channel % 10) != 0))
334 375
335/* These macros check chanmode and not channelFlags */ 376/* These macros check chanmode and not channelFlags */
336#define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B) 377#define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
@@ -363,6 +404,12 @@ enum ser_reg_mode {
363 SER_REG_MODE_AUTO = 2, 404 SER_REG_MODE_AUTO = 2,
364}; 405};
365 406
407enum ath9k_rx_qtype {
408 ATH9K_RX_QUEUE_HP,
409 ATH9K_RX_QUEUE_LP,
410 ATH9K_RX_QUEUE_MAX,
411};
412
366struct ath9k_beacon_state { 413struct ath9k_beacon_state {
367 u32 bs_nexttbtt; 414 u32 bs_nexttbtt;
368 u32 bs_nextdtim; 415 u32 bs_nextdtim;
@@ -440,6 +487,124 @@ struct ath_gen_timer_table {
440 } timer_mask; 487 } timer_mask;
441}; 488};
442 489
490/**
491 * struct ath_hw_private_ops - callbacks used internally by hardware code
492 *
493 * This structure contains private callbacks designed to only be used internally
494 * by the hardware core.
495 *
496 * @init_cal_settings: setup types of calibrations supported
497 * @init_cal: starts actual calibration
498 *
499 * @init_mode_regs: Initializes mode registers
500 * @init_mode_gain_regs: Initialize TX/RX gain registers
501 * @macversion_supported: If this specific mac revision is supported
502 *
503 * @rf_set_freq: change frequency
504 * @spur_mitigate_freq: spur mitigation
505 * @rf_alloc_ext_banks:
506 * @rf_free_ext_banks:
507 * @set_rf_regs:
508 * @compute_pll_control: compute the PLL control value to use for
509 * AR_RTC_PLL_CONTROL for a given channel
510 * @setup_calibration: set up calibration
511 * @iscal_supported: used to query if a type of calibration is supported
512 * @loadnf: load noise floor read from each chain on the CCA registers
513 */
514struct ath_hw_private_ops {
515 /* Calibration ops */
516 void (*init_cal_settings)(struct ath_hw *ah);
517 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
518
519 void (*init_mode_regs)(struct ath_hw *ah);
520 void (*init_mode_gain_regs)(struct ath_hw *ah);
521 bool (*macversion_supported)(u32 macversion);
522 void (*setup_calibration)(struct ath_hw *ah,
523 struct ath9k_cal_list *currCal);
524 bool (*iscal_supported)(struct ath_hw *ah,
525 enum ath9k_cal_types calType);
526
527 /* PHY ops */
528 int (*rf_set_freq)(struct ath_hw *ah,
529 struct ath9k_channel *chan);
530 void (*spur_mitigate_freq)(struct ath_hw *ah,
531 struct ath9k_channel *chan);
532 int (*rf_alloc_ext_banks)(struct ath_hw *ah);
533 void (*rf_free_ext_banks)(struct ath_hw *ah);
534 bool (*set_rf_regs)(struct ath_hw *ah,
535 struct ath9k_channel *chan,
536 u16 modesIndex);
537 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
538 void (*init_bb)(struct ath_hw *ah,
539 struct ath9k_channel *chan);
540 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
541 void (*olc_init)(struct ath_hw *ah);
542 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
543 void (*mark_phy_inactive)(struct ath_hw *ah);
544 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
545 bool (*rfbus_req)(struct ath_hw *ah);
546 void (*rfbus_done)(struct ath_hw *ah);
547 void (*enable_rfkill)(struct ath_hw *ah);
548 void (*restore_chainmask)(struct ath_hw *ah);
549 void (*set_diversity)(struct ath_hw *ah, bool value);
550 u32 (*compute_pll_control)(struct ath_hw *ah,
551 struct ath9k_channel *chan);
552 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
553 int param);
554 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
555 void (*loadnf)(struct ath_hw *ah, struct ath9k_channel *chan);
556};
557
558/**
559 * struct ath_hw_ops - callbacks used by hardware code and driver code
560 *
561 * This structure contains callbacks designed to to be used internally by
562 * hardware code and also by the lower level driver.
563 *
564 * @config_pci_powersave:
565 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
566 */
567struct ath_hw_ops {
568 void (*config_pci_powersave)(struct ath_hw *ah,
569 int restore,
570 int power_off);
571 void (*rx_enable)(struct ath_hw *ah);
572 void (*set_desc_link)(void *ds, u32 link);
573 void (*get_desc_link)(void *ds, u32 **link);
574 bool (*calibrate)(struct ath_hw *ah,
575 struct ath9k_channel *chan,
576 u8 rxchainmask,
577 bool longcal);
578 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
579 void (*fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen,
580 bool is_firstseg, bool is_is_lastseg,
581 const void *ds0, dma_addr_t buf_addr,
582 unsigned int qcu);
583 int (*proc_txdesc)(struct ath_hw *ah, void *ds,
584 struct ath_tx_status *ts);
585 void (*set11n_txdesc)(struct ath_hw *ah, void *ds,
586 u32 pktLen, enum ath9k_pkt_type type,
587 u32 txPower, u32 keyIx,
588 enum ath9k_key_type keyType,
589 u32 flags);
590 void (*set11n_ratescenario)(struct ath_hw *ah, void *ds,
591 void *lastds,
592 u32 durUpdateEn, u32 rtsctsRate,
593 u32 rtsctsDuration,
594 struct ath9k_11n_rate_series series[],
595 u32 nseries, u32 flags);
596 void (*set11n_aggr_first)(struct ath_hw *ah, void *ds,
597 u32 aggrLen);
598 void (*set11n_aggr_middle)(struct ath_hw *ah, void *ds,
599 u32 numDelims);
600 void (*set11n_aggr_last)(struct ath_hw *ah, void *ds);
601 void (*clr11n_aggr)(struct ath_hw *ah, void *ds);
602 void (*set11n_burstduration)(struct ath_hw *ah, void *ds,
603 u32 burstDuration);
604 void (*set11n_virtualmorefrag)(struct ath_hw *ah, void *ds,
605 u32 vmf);
606};
607
443struct ath_hw { 608struct ath_hw {
444 struct ieee80211_hw *hw; 609 struct ieee80211_hw *hw;
445 struct ath_common common; 610 struct ath_common common;
@@ -453,14 +618,18 @@ struct ath_hw {
453 struct ar5416_eeprom_def def; 618 struct ar5416_eeprom_def def;
454 struct ar5416_eeprom_4k map4k; 619 struct ar5416_eeprom_4k map4k;
455 struct ar9287_eeprom map9287; 620 struct ar9287_eeprom map9287;
621 struct ar9300_eeprom ar9300_eep;
456 } eeprom; 622 } eeprom;
457 const struct eeprom_ops *eep_ops; 623 const struct eeprom_ops *eep_ops;
458 enum ath9k_eep_map eep_map;
459 624
460 bool sw_mgmt_crypto; 625 bool sw_mgmt_crypto;
461 bool is_pciexpress; 626 bool is_pciexpress;
462 bool need_an_top2_fixup; 627 bool need_an_top2_fixup;
463 u16 tx_trig_level; 628 u16 tx_trig_level;
629 s16 nf_2g_max;
630 s16 nf_2g_min;
631 s16 nf_5g_max;
632 s16 nf_5g_min;
464 u16 rfsilent; 633 u16 rfsilent;
465 u32 rfkill_gpio; 634 u32 rfkill_gpio;
466 u32 rfkill_polarity; 635 u32 rfkill_polarity;
@@ -493,6 +662,7 @@ struct ath_hw {
493 struct ath9k_cal_list adcgain_caldata; 662 struct ath9k_cal_list adcgain_caldata;
494 struct ath9k_cal_list adcdc_calinitdata; 663 struct ath9k_cal_list adcdc_calinitdata;
495 struct ath9k_cal_list adcdc_caldata; 664 struct ath9k_cal_list adcdc_caldata;
665 struct ath9k_cal_list tempCompCalData;
496 struct ath9k_cal_list *cal_list; 666 struct ath9k_cal_list *cal_list;
497 struct ath9k_cal_list *cal_list_last; 667 struct ath9k_cal_list *cal_list_last;
498 struct ath9k_cal_list *cal_list_curr; 668 struct ath9k_cal_list *cal_list_curr;
@@ -533,12 +703,10 @@ struct ath_hw {
533 DONT_USE_32KHZ, 703 DONT_USE_32KHZ,
534 } enable_32kHz_clock; 704 } enable_32kHz_clock;
535 705
536 /* Callback for radio frequency change */ 706 /* Private to hardware code */
537 int (*ath9k_hw_rf_set_freq)(struct ath_hw *ah, struct ath9k_channel *chan); 707 struct ath_hw_private_ops private_ops;
538 708 /* Accessed by the lower level driver */
539 /* Callback for baseband spur frequency */ 709 struct ath_hw_ops ops;
540 void (*ath9k_hw_spur_mitigate_freq)(struct ath_hw *ah,
541 struct ath9k_channel *chan);
542 710
543 /* Used to program the radio on non single-chip devices */ 711 /* Used to program the radio on non single-chip devices */
544 u32 *analogBank0Data; 712 u32 *analogBank0Data;
@@ -551,6 +719,7 @@ struct ath_hw {
551 u32 *addac5416_21; 719 u32 *addac5416_21;
552 u32 *bank6Temp; 720 u32 *bank6Temp;
553 721
722 u8 txpower_limit;
554 int16_t txpower_indexoffset; 723 int16_t txpower_indexoffset;
555 int coverage_class; 724 int coverage_class;
556 u32 beacon_interval; 725 u32 beacon_interval;
@@ -592,6 +761,7 @@ struct ath_hw {
592 struct ar5416IniArray iniBank7; 761 struct ar5416IniArray iniBank7;
593 struct ar5416IniArray iniAddac; 762 struct ar5416IniArray iniAddac;
594 struct ar5416IniArray iniPcieSerdes; 763 struct ar5416IniArray iniPcieSerdes;
764 struct ar5416IniArray iniPcieSerdesLowPower;
595 struct ar5416IniArray iniModesAdditional; 765 struct ar5416IniArray iniModesAdditional;
596 struct ar5416IniArray iniModesRxGain; 766 struct ar5416IniArray iniModesRxGain;
597 struct ar5416IniArray iniModesTxGain; 767 struct ar5416IniArray iniModesTxGain;
@@ -604,9 +774,21 @@ struct ath_hw {
604 struct ar5416IniArray iniModes_high_power_tx_gain_9271; 774 struct ar5416IniArray iniModes_high_power_tx_gain_9271;
605 struct ar5416IniArray iniModes_normal_power_tx_gain_9271; 775 struct ar5416IniArray iniModes_normal_power_tx_gain_9271;
606 776
777 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
778 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
779 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
780 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
781
607 u32 intr_gen_timer_trigger; 782 u32 intr_gen_timer_trigger;
608 u32 intr_gen_timer_thresh; 783 u32 intr_gen_timer_thresh;
609 struct ath_gen_timer_table hw_gen_timers; 784 struct ath_gen_timer_table hw_gen_timers;
785
786 struct ar9003_txs *ts_ring;
787 void *ts_start;
788 u32 ts_paddr_start;
789 u32 ts_paddr_end;
790 u16 ts_tail;
791 u8 ts_size;
610}; 792};
611 793
612static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah) 794static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
@@ -619,6 +801,16 @@ static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
619 return &(ath9k_hw_common(ah)->regulatory); 801 return &(ath9k_hw_common(ah)->regulatory);
620} 802}
621 803
804static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
805{
806 return &ah->private_ops;
807}
808
809static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
810{
811 return &ah->ops;
812}
813
622/* Initialization, Detach, Reset */ 814/* Initialization, Detach, Reset */
623const char *ath9k_hw_probe(u16 vendorid, u16 devid); 815const char *ath9k_hw_probe(u16 vendorid, u16 devid);
624void ath9k_hw_deinit(struct ath_hw *ah); 816void ath9k_hw_deinit(struct ath_hw *ah);
@@ -630,6 +822,7 @@ bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
630 u32 capability, u32 *result); 822 u32 capability, u32 *result);
631bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type, 823bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
632 u32 capability, u32 setting, int *status); 824 u32 capability, u32 setting, int *status);
825u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
633 826
634/* Key Cache Management */ 827/* Key Cache Management */
635bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry); 828bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry);
@@ -678,16 +871,10 @@ void ath9k_hw_set11nmac2040(struct ath_hw *ah);
678void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period); 871void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
679void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 872void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
680 const struct ath9k_beacon_state *bs); 873 const struct ath9k_beacon_state *bs);
874bool ath9k_hw_check_alive(struct ath_hw *ah);
681 875
682bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode); 876bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
683 877
684void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off);
685
686/* Interrupt Handling */
687bool ath9k_hw_intrpend(struct ath_hw *ah);
688bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked);
689enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints);
690
691/* Generic hw timer primitives */ 878/* Generic hw timer primitives */
692struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 879struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
693 void (*trigger)(void *), 880 void (*trigger)(void *),
@@ -709,6 +896,36 @@ void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
709/* HTC */ 896/* HTC */
710void ath9k_hw_htc_resetinit(struct ath_hw *ah); 897void ath9k_hw_htc_resetinit(struct ath_hw *ah);
711 898
899/* PHY */
900void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
901 u32 *coef_mantissa, u32 *coef_exponent);
902
903/*
904 * Code Specific to AR5008, AR9001 or AR9002,
905 * we stuff these here to avoid callbacks for AR9003.
906 */
907void ar9002_hw_cck_chan14_spread(struct ath_hw *ah);
908int ar9002_hw_rf_claim(struct ath_hw *ah);
909void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
910void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah);
911
912/*
913 * Code specifric to AR9003, we stuff these here to avoid callbacks
914 * for older families
915 */
916void ar9003_hw_set_nf_limits(struct ath_hw *ah);
917
918/* Hardware family op attach helpers */
919void ar5008_hw_attach_phy_ops(struct ath_hw *ah);
920void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
921void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
922
923void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
924void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
925
926void ar9002_hw_attach_ops(struct ath_hw *ah);
927void ar9003_hw_attach_ops(struct ath_hw *ah);
928
712#define ATH_PCIE_CAP_LINK_CTRL 0x70 929#define ATH_PCIE_CAP_LINK_CTRL 0x70
713#define ATH_PCIE_CAP_LINK_L0S 1 930#define ATH_PCIE_CAP_LINK_L0S 1
714#define ATH_PCIE_CAP_LINK_L1 2 931#define ATH_PCIE_CAP_LINK_L1 2
diff --git a/drivers/net/wireless/ath/ath9k/init.c b/drivers/net/wireless/ath/ath9k/init.c
index b78308c3c4d4..8c795488ebc3 100644
--- a/drivers/net/wireless/ath/ath9k/init.c
+++ b/drivers/net/wireless/ath/ath9k/init.c
@@ -175,6 +175,18 @@ static const struct ath_ops ath9k_common_ops = {
175 .write = ath9k_iowrite32, 175 .write = ath9k_iowrite32,
176}; 176};
177 177
178static int count_streams(unsigned int chainmask, int max)
179{
180 int streams = 0;
181
182 do {
183 if (++streams == max)
184 break;
185 } while ((chainmask = chainmask & (chainmask - 1)));
186
187 return streams;
188}
189
178/**************************/ 190/**************************/
179/* Initialization */ 191/* Initialization */
180/**************************/ 192/**************************/
@@ -182,8 +194,10 @@ static const struct ath_ops ath9k_common_ops = {
182static void setup_ht_cap(struct ath_softc *sc, 194static void setup_ht_cap(struct ath_softc *sc,
183 struct ieee80211_sta_ht_cap *ht_info) 195 struct ieee80211_sta_ht_cap *ht_info)
184{ 196{
185 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 197 struct ath_hw *ah = sc->sc_ah;
198 struct ath_common *common = ath9k_hw_common(ah);
186 u8 tx_streams, rx_streams; 199 u8 tx_streams, rx_streams;
200 int i, max_streams;
187 201
188 ht_info->ht_supported = true; 202 ht_info->ht_supported = true;
189 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 203 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
@@ -191,28 +205,40 @@ static void setup_ht_cap(struct ath_softc *sc,
191 IEEE80211_HT_CAP_SGI_40 | 205 IEEE80211_HT_CAP_SGI_40 |
192 IEEE80211_HT_CAP_DSSSCCK40; 206 IEEE80211_HT_CAP_DSSSCCK40;
193 207
208 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_LDPC)
209 ht_info->cap |= IEEE80211_HT_CAP_LDPC_CODING;
210
194 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 211 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
195 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8; 212 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
196 213
214 if (AR_SREV_9300_20_OR_LATER(ah))
215 max_streams = 3;
216 else
217 max_streams = 2;
218
219 if (AR_SREV_9280_10_OR_LATER(ah)) {
220 if (max_streams >= 2)
221 ht_info->cap |= IEEE80211_HT_CAP_TX_STBC;
222 ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
223 }
224
197 /* set up supported mcs set */ 225 /* set up supported mcs set */
198 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs)); 226 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
199 tx_streams = !(common->tx_chainmask & (common->tx_chainmask - 1)) ? 227 tx_streams = count_streams(common->tx_chainmask, max_streams);
200 1 : 2; 228 rx_streams = count_streams(common->rx_chainmask, max_streams);
201 rx_streams = !(common->rx_chainmask & (common->rx_chainmask - 1)) ? 229
202 1 : 2; 230 ath_print(common, ATH_DBG_CONFIG,
231 "TX streams %d, RX streams: %d\n",
232 tx_streams, rx_streams);
203 233
204 if (tx_streams != rx_streams) { 234 if (tx_streams != rx_streams) {
205 ath_print(common, ATH_DBG_CONFIG,
206 "TX streams %d, RX streams: %d\n",
207 tx_streams, rx_streams);
208 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; 235 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
209 ht_info->mcs.tx_params |= ((tx_streams - 1) << 236 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
210 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); 237 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
211 } 238 }
212 239
213 ht_info->mcs.rx_mask[0] = 0xff; 240 for (i = 0; i < rx_streams; i++)
214 if (rx_streams >= 2) 241 ht_info->mcs.rx_mask[i] = 0xff;
215 ht_info->mcs.rx_mask[1] = 0xff;
216 242
217 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED; 243 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
218} 244}
@@ -235,31 +261,37 @@ static int ath9k_reg_notifier(struct wiphy *wiphy,
235*/ 261*/
236int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, 262int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
237 struct list_head *head, const char *name, 263 struct list_head *head, const char *name,
238 int nbuf, int ndesc) 264 int nbuf, int ndesc, bool is_tx)
239{ 265{
240#define DS2PHYS(_dd, _ds) \ 266#define DS2PHYS(_dd, _ds) \
241 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) 267 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
242#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0) 268#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
243#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096) 269#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
244 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 270 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
245 struct ath_desc *ds; 271 u8 *ds;
246 struct ath_buf *bf; 272 struct ath_buf *bf;
247 int i, bsize, error; 273 int i, bsize, error, desc_len;
248 274
249 ath_print(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n", 275 ath_print(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
250 name, nbuf, ndesc); 276 name, nbuf, ndesc);
251 277
252 INIT_LIST_HEAD(head); 278 INIT_LIST_HEAD(head);
279
280 if (is_tx)
281 desc_len = sc->sc_ah->caps.tx_desc_len;
282 else
283 desc_len = sizeof(struct ath_desc);
284
253 /* ath_desc must be a multiple of DWORDs */ 285 /* ath_desc must be a multiple of DWORDs */
254 if ((sizeof(struct ath_desc) % 4) != 0) { 286 if ((desc_len % 4) != 0) {
255 ath_print(common, ATH_DBG_FATAL, 287 ath_print(common, ATH_DBG_FATAL,
256 "ath_desc not DWORD aligned\n"); 288 "ath_desc not DWORD aligned\n");
257 BUG_ON((sizeof(struct ath_desc) % 4) != 0); 289 BUG_ON((desc_len % 4) != 0);
258 error = -ENOMEM; 290 error = -ENOMEM;
259 goto fail; 291 goto fail;
260 } 292 }
261 293
262 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc; 294 dd->dd_desc_len = desc_len * nbuf * ndesc;
263 295
264 /* 296 /*
265 * Need additional DMA memory because we can't use 297 * Need additional DMA memory because we can't use
@@ -272,7 +304,7 @@ int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
272 u32 dma_len; 304 u32 dma_len;
273 305
274 while (ndesc_skipped) { 306 while (ndesc_skipped) {
275 dma_len = ndesc_skipped * sizeof(struct ath_desc); 307 dma_len = ndesc_skipped * desc_len;
276 dd->dd_desc_len += dma_len; 308 dd->dd_desc_len += dma_len;
277 309
278 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len); 310 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
@@ -286,7 +318,7 @@ int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
286 error = -ENOMEM; 318 error = -ENOMEM;
287 goto fail; 319 goto fail;
288 } 320 }
289 ds = dd->dd_desc; 321 ds = (u8 *) dd->dd_desc;
290 ath_print(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n", 322 ath_print(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
291 name, ds, (u32) dd->dd_desc_len, 323 name, ds, (u32) dd->dd_desc_len,
292 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len); 324 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
@@ -300,7 +332,7 @@ int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
300 } 332 }
301 dd->dd_bufptr = bf; 333 dd->dd_bufptr = bf;
302 334
303 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) { 335 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
304 bf->bf_desc = ds; 336 bf->bf_desc = ds;
305 bf->bf_daddr = DS2PHYS(dd, ds); 337 bf->bf_daddr = DS2PHYS(dd, ds);
306 338
@@ -316,7 +348,7 @@ int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
316 ((caddr_t) dd->dd_desc + 348 ((caddr_t) dd->dd_desc +
317 dd->dd_desc_len)); 349 dd->dd_desc_len));
318 350
319 ds += ndesc; 351 ds += (desc_len * ndesc);
320 bf->bf_desc = ds; 352 bf->bf_desc = ds;
321 bf->bf_daddr = DS2PHYS(dd, ds); 353 bf->bf_daddr = DS2PHYS(dd, ds);
322 } 354 }
@@ -514,7 +546,7 @@ static void ath9k_init_misc(struct ath_softc *sc)
514 common->tx_chainmask = sc->sc_ah->caps.tx_chainmask; 546 common->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
515 common->rx_chainmask = sc->sc_ah->caps.rx_chainmask; 547 common->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
516 548
517 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_DIVERSITY, 1, true, NULL); 549 ath9k_hw_set_diversity(sc->sc_ah, true);
518 sc->rx.defant = ath9k_hw_getdefantenna(sc->sc_ah); 550 sc->rx.defant = ath9k_hw_getdefantenna(sc->sc_ah);
519 551
520 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) 552 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
@@ -568,13 +600,10 @@ static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
568 ath_read_cachesize(common, &csz); 600 ath_read_cachesize(common, &csz);
569 common->cachelsz = csz << 2; /* convert to bytes */ 601 common->cachelsz = csz << 2; /* convert to bytes */
570 602
603 /* Initializes the hardware for all supported chipsets */
571 ret = ath9k_hw_init(ah); 604 ret = ath9k_hw_init(ah);
572 if (ret) { 605 if (ret)
573 ath_print(common, ATH_DBG_FATAL,
574 "Unable to initialize hardware; "
575 "initialization status: %d\n", ret);
576 goto err_hw; 606 goto err_hw;
577 }
578 607
579 ret = ath9k_init_debug(ah); 608 ret = ath9k_init_debug(ah);
580 if (ret) { 609 if (ret) {
diff --git a/drivers/net/wireless/ath/ath9k/mac.c b/drivers/net/wireless/ath/ath9k/mac.c
index 4a2060e5a777..0e425cb4bbb1 100644
--- a/drivers/net/wireless/ath/ath9k/mac.c
+++ b/drivers/net/wireless/ath/ath9k/mac.c
@@ -25,6 +25,8 @@ static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah,
25 ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask, 25 ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask,
26 ah->txurn_interrupt_mask); 26 ah->txurn_interrupt_mask);
27 27
28 ENABLE_REGWRITE_BUFFER(ah);
29
28 REG_WRITE(ah, AR_IMR_S0, 30 REG_WRITE(ah, AR_IMR_S0,
29 SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK) 31 SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK)
30 | SM(ah->txdesc_interrupt_mask, AR_IMR_S0_QCU_TXDESC)); 32 | SM(ah->txdesc_interrupt_mask, AR_IMR_S0_QCU_TXDESC));
@@ -35,6 +37,9 @@ static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah,
35 ah->imrs2_reg &= ~AR_IMR_S2_QCU_TXURN; 37 ah->imrs2_reg &= ~AR_IMR_S2_QCU_TXURN;
36 ah->imrs2_reg |= (ah->txurn_interrupt_mask & AR_IMR_S2_QCU_TXURN); 38 ah->imrs2_reg |= (ah->txurn_interrupt_mask & AR_IMR_S2_QCU_TXURN);
37 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); 39 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
40
41 REGWRITE_BUFFER_FLUSH(ah);
42 DISABLE_REGWRITE_BUFFER(ah);
38} 43}
39 44
40u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q) 45u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q)
@@ -57,6 +62,18 @@ void ath9k_hw_txstart(struct ath_hw *ah, u32 q)
57} 62}
58EXPORT_SYMBOL(ath9k_hw_txstart); 63EXPORT_SYMBOL(ath9k_hw_txstart);
59 64
65void ath9k_hw_cleartxdesc(struct ath_hw *ah, void *ds)
66{
67 struct ar5416_desc *ads = AR5416DESC(ds);
68
69 ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
70 ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
71 ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
72 ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
73 ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
74}
75EXPORT_SYMBOL(ath9k_hw_cleartxdesc);
76
60u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q) 77u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q)
61{ 78{
62 u32 npend; 79 u32 npend;
@@ -207,281 +224,6 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
207} 224}
208EXPORT_SYMBOL(ath9k_hw_stoptxdma); 225EXPORT_SYMBOL(ath9k_hw_stoptxdma);
209 226
210void ath9k_hw_filltxdesc(struct ath_hw *ah, struct ath_desc *ds,
211 u32 segLen, bool firstSeg,
212 bool lastSeg, const struct ath_desc *ds0)
213{
214 struct ar5416_desc *ads = AR5416DESC(ds);
215
216 if (firstSeg) {
217 ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_TxMore);
218 } else if (lastSeg) {
219 ads->ds_ctl0 = 0;
220 ads->ds_ctl1 = segLen;
221 ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
222 ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
223 } else {
224 ads->ds_ctl0 = 0;
225 ads->ds_ctl1 = segLen | AR_TxMore;
226 ads->ds_ctl2 = 0;
227 ads->ds_ctl3 = 0;
228 }
229 ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
230 ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
231 ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
232 ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
233 ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
234}
235EXPORT_SYMBOL(ath9k_hw_filltxdesc);
236
237void ath9k_hw_cleartxdesc(struct ath_hw *ah, struct ath_desc *ds)
238{
239 struct ar5416_desc *ads = AR5416DESC(ds);
240
241 ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
242 ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
243 ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
244 ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
245 ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
246}
247EXPORT_SYMBOL(ath9k_hw_cleartxdesc);
248
249int ath9k_hw_txprocdesc(struct ath_hw *ah, struct ath_desc *ds,
250 struct ath_tx_status *ts)
251{
252 struct ar5416_desc *ads = AR5416DESC(ds);
253
254 if ((ads->ds_txstatus9 & AR_TxDone) == 0)
255 return -EINPROGRESS;
256
257 ts->ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
258 ts->ts_tstamp = ads->AR_SendTimestamp;
259 ts->ts_status = 0;
260 ts->ts_flags = 0;
261
262 if (ads->ds_txstatus1 & AR_FrmXmitOK)
263 ts->ts_status |= ATH9K_TX_ACKED;
264 if (ads->ds_txstatus1 & AR_ExcessiveRetries)
265 ts->ts_status |= ATH9K_TXERR_XRETRY;
266 if (ads->ds_txstatus1 & AR_Filtered)
267 ts->ts_status |= ATH9K_TXERR_FILT;
268 if (ads->ds_txstatus1 & AR_FIFOUnderrun) {
269 ts->ts_status |= ATH9K_TXERR_FIFO;
270 ath9k_hw_updatetxtriglevel(ah, true);
271 }
272 if (ads->ds_txstatus9 & AR_TxOpExceeded)
273 ts->ts_status |= ATH9K_TXERR_XTXOP;
274 if (ads->ds_txstatus1 & AR_TxTimerExpired)
275 ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
276
277 if (ads->ds_txstatus1 & AR_DescCfgErr)
278 ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
279 if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
280 ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
281 ath9k_hw_updatetxtriglevel(ah, true);
282 }
283 if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
284 ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
285 ath9k_hw_updatetxtriglevel(ah, true);
286 }
287 if (ads->ds_txstatus0 & AR_TxBaStatus) {
288 ts->ts_flags |= ATH9K_TX_BA;
289 ts->ba_low = ads->AR_BaBitmapLow;
290 ts->ba_high = ads->AR_BaBitmapHigh;
291 }
292
293 ts->ts_rateindex = MS(ads->ds_txstatus9, AR_FinalTxIdx);
294 switch (ts->ts_rateindex) {
295 case 0:
296 ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate0);
297 break;
298 case 1:
299 ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate1);
300 break;
301 case 2:
302 ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate2);
303 break;
304 case 3:
305 ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate3);
306 break;
307 }
308
309 ts->ts_rssi = MS(ads->ds_txstatus5, AR_TxRSSICombined);
310 ts->ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
311 ts->ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
312 ts->ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
313 ts->ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
314 ts->ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
315 ts->ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
316 ts->evm0 = ads->AR_TxEVM0;
317 ts->evm1 = ads->AR_TxEVM1;
318 ts->evm2 = ads->AR_TxEVM2;
319 ts->ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
320 ts->ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
321 ts->ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
322 ts->ts_antenna = 0;
323
324 return 0;
325}
326EXPORT_SYMBOL(ath9k_hw_txprocdesc);
327
328void ath9k_hw_set11n_txdesc(struct ath_hw *ah, struct ath_desc *ds,
329 u32 pktLen, enum ath9k_pkt_type type, u32 txPower,
330 u32 keyIx, enum ath9k_key_type keyType, u32 flags)
331{
332 struct ar5416_desc *ads = AR5416DESC(ds);
333
334 txPower += ah->txpower_indexoffset;
335 if (txPower > 63)
336 txPower = 63;
337
338 ads->ds_ctl0 = (pktLen & AR_FrameLen)
339 | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
340 | SM(txPower, AR_XmitPower)
341 | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
342 | (flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
343 | (flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0)
344 | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0);
345
346 ads->ds_ctl1 =
347 (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
348 | SM(type, AR_FrameType)
349 | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
350 | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
351 | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
352
353 ads->ds_ctl6 = SM(keyType, AR_EncrType);
354
355 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) {
356 ads->ds_ctl8 = 0;
357 ads->ds_ctl9 = 0;
358 ads->ds_ctl10 = 0;
359 ads->ds_ctl11 = 0;
360 }
361}
362EXPORT_SYMBOL(ath9k_hw_set11n_txdesc);
363
364void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, struct ath_desc *ds,
365 struct ath_desc *lastds,
366 u32 durUpdateEn, u32 rtsctsRate,
367 u32 rtsctsDuration,
368 struct ath9k_11n_rate_series series[],
369 u32 nseries, u32 flags)
370{
371 struct ar5416_desc *ads = AR5416DESC(ds);
372 struct ar5416_desc *last_ads = AR5416DESC(lastds);
373 u32 ds_ctl0;
374
375 if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
376 ds_ctl0 = ads->ds_ctl0;
377
378 if (flags & ATH9K_TXDESC_RTSENA) {
379 ds_ctl0 &= ~AR_CTSEnable;
380 ds_ctl0 |= AR_RTSEnable;
381 } else {
382 ds_ctl0 &= ~AR_RTSEnable;
383 ds_ctl0 |= AR_CTSEnable;
384 }
385
386 ads->ds_ctl0 = ds_ctl0;
387 } else {
388 ads->ds_ctl0 =
389 (ads->ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
390 }
391
392 ads->ds_ctl2 = set11nTries(series, 0)
393 | set11nTries(series, 1)
394 | set11nTries(series, 2)
395 | set11nTries(series, 3)
396 | (durUpdateEn ? AR_DurUpdateEna : 0)
397 | SM(0, AR_BurstDur);
398
399 ads->ds_ctl3 = set11nRate(series, 0)
400 | set11nRate(series, 1)
401 | set11nRate(series, 2)
402 | set11nRate(series, 3);
403
404 ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
405 | set11nPktDurRTSCTS(series, 1);
406
407 ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
408 | set11nPktDurRTSCTS(series, 3);
409
410 ads->ds_ctl7 = set11nRateFlags(series, 0)
411 | set11nRateFlags(series, 1)
412 | set11nRateFlags(series, 2)
413 | set11nRateFlags(series, 3)
414 | SM(rtsctsRate, AR_RTSCTSRate);
415 last_ads->ds_ctl2 = ads->ds_ctl2;
416 last_ads->ds_ctl3 = ads->ds_ctl3;
417}
418EXPORT_SYMBOL(ath9k_hw_set11n_ratescenario);
419
420void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, struct ath_desc *ds,
421 u32 aggrLen)
422{
423 struct ar5416_desc *ads = AR5416DESC(ds);
424
425 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
426 ads->ds_ctl6 &= ~AR_AggrLen;
427 ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen);
428}
429EXPORT_SYMBOL(ath9k_hw_set11n_aggr_first);
430
431void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, struct ath_desc *ds,
432 u32 numDelims)
433{
434 struct ar5416_desc *ads = AR5416DESC(ds);
435 unsigned int ctl6;
436
437 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
438
439 ctl6 = ads->ds_ctl6;
440 ctl6 &= ~AR_PadDelim;
441 ctl6 |= SM(numDelims, AR_PadDelim);
442 ads->ds_ctl6 = ctl6;
443}
444EXPORT_SYMBOL(ath9k_hw_set11n_aggr_middle);
445
446void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, struct ath_desc *ds)
447{
448 struct ar5416_desc *ads = AR5416DESC(ds);
449
450 ads->ds_ctl1 |= AR_IsAggr;
451 ads->ds_ctl1 &= ~AR_MoreAggr;
452 ads->ds_ctl6 &= ~AR_PadDelim;
453}
454EXPORT_SYMBOL(ath9k_hw_set11n_aggr_last);
455
456void ath9k_hw_clr11n_aggr(struct ath_hw *ah, struct ath_desc *ds)
457{
458 struct ar5416_desc *ads = AR5416DESC(ds);
459
460 ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
461}
462EXPORT_SYMBOL(ath9k_hw_clr11n_aggr);
463
464void ath9k_hw_set11n_burstduration(struct ath_hw *ah, struct ath_desc *ds,
465 u32 burstDuration)
466{
467 struct ar5416_desc *ads = AR5416DESC(ds);
468
469 ads->ds_ctl2 &= ~AR_BurstDur;
470 ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
471}
472EXPORT_SYMBOL(ath9k_hw_set11n_burstduration);
473
474void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, struct ath_desc *ds,
475 u32 vmf)
476{
477 struct ar5416_desc *ads = AR5416DESC(ds);
478
479 if (vmf)
480 ads->ds_ctl0 |= AR_VirtMoreFrag;
481 else
482 ads->ds_ctl0 &= ~AR_VirtMoreFrag;
483}
484
485void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs) 227void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs)
486{ 228{
487 *txqs &= ah->intr_txqs; 229 *txqs &= ah->intr_txqs;
@@ -733,6 +475,8 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
733 } else 475 } else
734 cwMin = qi->tqi_cwmin; 476 cwMin = qi->tqi_cwmin;
735 477
478 ENABLE_REGWRITE_BUFFER(ah);
479
736 REG_WRITE(ah, AR_DLCL_IFS(q), 480 REG_WRITE(ah, AR_DLCL_IFS(q),
737 SM(cwMin, AR_D_LCL_IFS_CWMIN) | 481 SM(cwMin, AR_D_LCL_IFS_CWMIN) |
738 SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) | 482 SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) |
@@ -747,6 +491,8 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
747 REG_WRITE(ah, AR_DMISC(q), 491 REG_WRITE(ah, AR_DMISC(q),
748 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2); 492 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2);
749 493
494 REGWRITE_BUFFER_FLUSH(ah);
495
750 if (qi->tqi_cbrPeriod) { 496 if (qi->tqi_cbrPeriod) {
751 REG_WRITE(ah, AR_QCBRCFG(q), 497 REG_WRITE(ah, AR_QCBRCFG(q),
752 SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) | 498 SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) |
@@ -762,6 +508,8 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
762 AR_Q_RDYTIMECFG_EN); 508 AR_Q_RDYTIMECFG_EN);
763 } 509 }
764 510
511 REGWRITE_BUFFER_FLUSH(ah);
512
765 REG_WRITE(ah, AR_DCHNTIME(q), 513 REG_WRITE(ah, AR_DCHNTIME(q),
766 SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) | 514 SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |
767 (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0)); 515 (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
@@ -779,6 +527,10 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
779 REG_READ(ah, AR_DMISC(q)) | 527 REG_READ(ah, AR_DMISC(q)) |
780 AR_D_MISC_POST_FR_BKOFF_DIS); 528 AR_D_MISC_POST_FR_BKOFF_DIS);
781 } 529 }
530
531 REGWRITE_BUFFER_FLUSH(ah);
532 DISABLE_REGWRITE_BUFFER(ah);
533
782 if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) { 534 if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) {
783 REG_WRITE(ah, AR_DMISC(q), 535 REG_WRITE(ah, AR_DMISC(q),
784 REG_READ(ah, AR_DMISC(q)) | 536 REG_READ(ah, AR_DMISC(q)) |
@@ -786,6 +538,8 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
786 } 538 }
787 switch (qi->tqi_type) { 539 switch (qi->tqi_type) {
788 case ATH9K_TX_QUEUE_BEACON: 540 case ATH9K_TX_QUEUE_BEACON:
541 ENABLE_REGWRITE_BUFFER(ah);
542
789 REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q)) 543 REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
790 | AR_Q_MISC_FSP_DBA_GATED 544 | AR_Q_MISC_FSP_DBA_GATED
791 | AR_Q_MISC_BEACON_USE 545 | AR_Q_MISC_BEACON_USE
@@ -796,8 +550,20 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
796 AR_D_MISC_ARB_LOCKOUT_CNTRL_S) 550 AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
797 | AR_D_MISC_BEACON_USE 551 | AR_D_MISC_BEACON_USE
798 | AR_D_MISC_POST_FR_BKOFF_DIS); 552 | AR_D_MISC_POST_FR_BKOFF_DIS);
553
554 REGWRITE_BUFFER_FLUSH(ah);
555 DISABLE_REGWRITE_BUFFER(ah);
556
557 /* cwmin and cwmax should be 0 for beacon queue */
558 if (AR_SREV_9300_20_OR_LATER(ah)) {
559 REG_WRITE(ah, AR_DLCL_IFS(q), SM(0, AR_D_LCL_IFS_CWMIN)
560 | SM(0, AR_D_LCL_IFS_CWMAX)
561 | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
562 }
799 break; 563 break;
800 case ATH9K_TX_QUEUE_CAB: 564 case ATH9K_TX_QUEUE_CAB:
565 ENABLE_REGWRITE_BUFFER(ah);
566
801 REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q)) 567 REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
802 | AR_Q_MISC_FSP_DBA_GATED 568 | AR_Q_MISC_FSP_DBA_GATED
803 | AR_Q_MISC_CBR_INCR_DIS1 569 | AR_Q_MISC_CBR_INCR_DIS1
@@ -811,6 +577,10 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
811 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q)) 577 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
812 | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL << 578 | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
813 AR_D_MISC_ARB_LOCKOUT_CNTRL_S)); 579 AR_D_MISC_ARB_LOCKOUT_CNTRL_S));
580
581 REGWRITE_BUFFER_FLUSH(ah);
582 DISABLE_REGWRITE_BUFFER(ah);
583
814 break; 584 break;
815 case ATH9K_TX_QUEUE_PSPOLL: 585 case ATH9K_TX_QUEUE_PSPOLL:
816 REG_WRITE(ah, AR_QMISC(q), 586 REG_WRITE(ah, AR_QMISC(q),
@@ -832,6 +602,9 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
832 AR_D_MISC_POST_FR_BKOFF_DIS); 602 AR_D_MISC_POST_FR_BKOFF_DIS);
833 } 603 }
834 604
605 if (AR_SREV_9300_20_OR_LATER(ah))
606 REG_WRITE(ah, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN);
607
835 if (qi->tqi_qflags & TXQ_FLAG_TXOKINT_ENABLE) 608 if (qi->tqi_qflags & TXQ_FLAG_TXOKINT_ENABLE)
836 ah->txok_interrupt_mask |= 1 << q; 609 ah->txok_interrupt_mask |= 1 << q;
837 else 610 else
@@ -940,22 +713,6 @@ int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
940} 713}
941EXPORT_SYMBOL(ath9k_hw_rxprocdesc); 714EXPORT_SYMBOL(ath9k_hw_rxprocdesc);
942 715
943void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
944 u32 size, u32 flags)
945{
946 struct ar5416_desc *ads = AR5416DESC(ds);
947 struct ath9k_hw_capabilities *pCap = &ah->caps;
948
949 ads->ds_ctl1 = size & AR_BufLen;
950 if (flags & ATH9K_RXDESC_INTREQ)
951 ads->ds_ctl1 |= AR_RxIntrReq;
952
953 ads->ds_rxstatus8 &= ~AR_RxDone;
954 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
955 memset(&(ads->u), 0, sizeof(ads->u));
956}
957EXPORT_SYMBOL(ath9k_hw_setuprxdesc);
958
959/* 716/*
960 * This can stop or re-enables RX. 717 * This can stop or re-enables RX.
961 * 718 *
@@ -999,12 +756,6 @@ void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp)
999} 756}
1000EXPORT_SYMBOL(ath9k_hw_putrxbuf); 757EXPORT_SYMBOL(ath9k_hw_putrxbuf);
1001 758
1002void ath9k_hw_rxena(struct ath_hw *ah)
1003{
1004 REG_WRITE(ah, AR_CR, AR_CR_RXE);
1005}
1006EXPORT_SYMBOL(ath9k_hw_rxena);
1007
1008void ath9k_hw_startpcureceive(struct ath_hw *ah) 759void ath9k_hw_startpcureceive(struct ath_hw *ah)
1009{ 760{
1010 ath9k_enable_mib_counters(ah); 761 ath9k_enable_mib_counters(ah);
@@ -1023,6 +774,14 @@ void ath9k_hw_stoppcurecv(struct ath_hw *ah)
1023} 774}
1024EXPORT_SYMBOL(ath9k_hw_stoppcurecv); 775EXPORT_SYMBOL(ath9k_hw_stoppcurecv);
1025 776
777void ath9k_hw_abortpcurecv(struct ath_hw *ah)
778{
779 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_ABORT | AR_DIAG_RX_DIS);
780
781 ath9k_hw_disable_mib_counters(ah);
782}
783EXPORT_SYMBOL(ath9k_hw_abortpcurecv);
784
1026bool ath9k_hw_stopdmarecv(struct ath_hw *ah) 785bool ath9k_hw_stopdmarecv(struct ath_hw *ah)
1027{ 786{
1028#define AH_RX_STOP_DMA_TIMEOUT 10000 /* usec */ 787#define AH_RX_STOP_DMA_TIMEOUT 10000 /* usec */
@@ -1068,3 +827,142 @@ int ath9k_hw_beaconq_setup(struct ath_hw *ah)
1068 return ath9k_hw_setuptxqueue(ah, ATH9K_TX_QUEUE_BEACON, &qi); 827 return ath9k_hw_setuptxqueue(ah, ATH9K_TX_QUEUE_BEACON, &qi);
1069} 828}
1070EXPORT_SYMBOL(ath9k_hw_beaconq_setup); 829EXPORT_SYMBOL(ath9k_hw_beaconq_setup);
830
831bool ath9k_hw_intrpend(struct ath_hw *ah)
832{
833 u32 host_isr;
834
835 if (AR_SREV_9100(ah))
836 return true;
837
838 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
839 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
840 return true;
841
842 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
843 if ((host_isr & AR_INTR_SYNC_DEFAULT)
844 && (host_isr != AR_INTR_SPURIOUS))
845 return true;
846
847 return false;
848}
849EXPORT_SYMBOL(ath9k_hw_intrpend);
850
851enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah,
852 enum ath9k_int ints)
853{
854 enum ath9k_int omask = ah->imask;
855 u32 mask, mask2;
856 struct ath9k_hw_capabilities *pCap = &ah->caps;
857 struct ath_common *common = ath9k_hw_common(ah);
858
859 ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
860
861 if (omask & ATH9K_INT_GLOBAL) {
862 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
863 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
864 (void) REG_READ(ah, AR_IER);
865 if (!AR_SREV_9100(ah)) {
866 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
867 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
868
869 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
870 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
871 }
872 }
873
874 /* TODO: global int Ref count */
875 mask = ints & ATH9K_INT_COMMON;
876 mask2 = 0;
877
878 if (ints & ATH9K_INT_TX) {
879 if (ah->config.tx_intr_mitigation)
880 mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM;
881 else {
882 if (ah->txok_interrupt_mask)
883 mask |= AR_IMR_TXOK;
884 if (ah->txdesc_interrupt_mask)
885 mask |= AR_IMR_TXDESC;
886 }
887 if (ah->txerr_interrupt_mask)
888 mask |= AR_IMR_TXERR;
889 if (ah->txeol_interrupt_mask)
890 mask |= AR_IMR_TXEOL;
891 }
892 if (ints & ATH9K_INT_RX) {
893 if (AR_SREV_9300_20_OR_LATER(ah)) {
894 mask |= AR_IMR_RXERR | AR_IMR_RXOK_HP;
895 if (ah->config.rx_intr_mitigation) {
896 mask &= ~AR_IMR_RXOK_LP;
897 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
898 } else {
899 mask |= AR_IMR_RXOK_LP;
900 }
901 } else {
902 if (ah->config.rx_intr_mitigation)
903 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
904 else
905 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
906 }
907 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
908 mask |= AR_IMR_GENTMR;
909 }
910
911 if (ints & (ATH9K_INT_BMISC)) {
912 mask |= AR_IMR_BCNMISC;
913 if (ints & ATH9K_INT_TIM)
914 mask2 |= AR_IMR_S2_TIM;
915 if (ints & ATH9K_INT_DTIM)
916 mask2 |= AR_IMR_S2_DTIM;
917 if (ints & ATH9K_INT_DTIMSYNC)
918 mask2 |= AR_IMR_S2_DTIMSYNC;
919 if (ints & ATH9K_INT_CABEND)
920 mask2 |= AR_IMR_S2_CABEND;
921 if (ints & ATH9K_INT_TSFOOR)
922 mask2 |= AR_IMR_S2_TSFOOR;
923 }
924
925 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
926 mask |= AR_IMR_BCNMISC;
927 if (ints & ATH9K_INT_GTT)
928 mask2 |= AR_IMR_S2_GTT;
929 if (ints & ATH9K_INT_CST)
930 mask2 |= AR_IMR_S2_CST;
931 }
932
933 ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
934 REG_WRITE(ah, AR_IMR, mask);
935 ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
936 AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
937 AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
938 ah->imrs2_reg |= mask2;
939 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
940
941 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
942 if (ints & ATH9K_INT_TIM_TIMER)
943 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
944 else
945 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
946 }
947
948 if (ints & ATH9K_INT_GLOBAL) {
949 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
950 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
951 if (!AR_SREV_9100(ah)) {
952 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
953 AR_INTR_MAC_IRQ);
954 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
955
956
957 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
958 AR_INTR_SYNC_DEFAULT);
959 REG_WRITE(ah, AR_INTR_SYNC_MASK,
960 AR_INTR_SYNC_DEFAULT);
961 }
962 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
963 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
964 }
965
966 return omask;
967}
968EXPORT_SYMBOL(ath9k_hw_set_interrupts);
diff --git a/drivers/net/wireless/ath/ath9k/mac.h b/drivers/net/wireless/ath/ath9k/mac.h
index 68dbd7a8ddca..00f3e0c7528a 100644
--- a/drivers/net/wireless/ath/ath9k/mac.h
+++ b/drivers/net/wireless/ath/ath9k/mac.h
@@ -37,6 +37,8 @@
37 AR_2040_##_index : 0) \ 37 AR_2040_##_index : 0) \
38 |((_series)[_index].RateFlags & ATH9K_RATESERIES_HALFGI ? \ 38 |((_series)[_index].RateFlags & ATH9K_RATESERIES_HALFGI ? \
39 AR_GI##_index : 0) \ 39 AR_GI##_index : 0) \
40 |((_series)[_index].RateFlags & ATH9K_RATESERIES_STBC ? \
41 AR_STBC##_index : 0) \
40 |SM((_series)[_index].ChSel, AR_ChainSel##_index)) 42 |SM((_series)[_index].ChSel, AR_ChainSel##_index))
41 43
42#define CCK_SIFS_TIME 10 44#define CCK_SIFS_TIME 10
@@ -86,7 +88,6 @@
86#define ATH9K_TX_DESC_CFG_ERR 0x04 88#define ATH9K_TX_DESC_CFG_ERR 0x04
87#define ATH9K_TX_DATA_UNDERRUN 0x08 89#define ATH9K_TX_DATA_UNDERRUN 0x08
88#define ATH9K_TX_DELIM_UNDERRUN 0x10 90#define ATH9K_TX_DELIM_UNDERRUN 0x10
89#define ATH9K_TX_SW_ABORTED 0x40
90#define ATH9K_TX_SW_FILTERED 0x80 91#define ATH9K_TX_SW_FILTERED 0x80
91 92
92/* 64 bytes */ 93/* 64 bytes */
@@ -117,7 +118,10 @@ struct ath_tx_status {
117 int8_t ts_rssi_ext0; 118 int8_t ts_rssi_ext0;
118 int8_t ts_rssi_ext1; 119 int8_t ts_rssi_ext1;
119 int8_t ts_rssi_ext2; 120 int8_t ts_rssi_ext2;
120 u8 pad[3]; 121 u8 qid;
122 u16 desc_id;
123 u8 tid;
124 u8 pad[2];
121 u32 ba_low; 125 u32 ba_low;
122 u32 ba_high; 126 u32 ba_high;
123 u32 evm0; 127 u32 evm0;
@@ -148,11 +152,13 @@ struct ath_rx_status {
148 u32 evm0; 152 u32 evm0;
149 u32 evm1; 153 u32 evm1;
150 u32 evm2; 154 u32 evm2;
155 u32 evm3;
156 u32 evm4;
151}; 157};
152 158
153struct ath_htc_rx_status { 159struct ath_htc_rx_status {
154 u64 rs_tstamp; 160 __be64 rs_tstamp;
155 u16 rs_datalen; 161 __be16 rs_datalen;
156 u8 rs_status; 162 u8 rs_status;
157 u8 rs_phyerr; 163 u8 rs_phyerr;
158 int8_t rs_rssi; 164 int8_t rs_rssi;
@@ -171,9 +177,9 @@ struct ath_htc_rx_status {
171 u8 rs_num_delims; 177 u8 rs_num_delims;
172 u8 rs_flags; 178 u8 rs_flags;
173 u8 rs_dummy; 179 u8 rs_dummy;
174 u32 evm0; 180 __be32 evm0;
175 u32 evm1; 181 __be32 evm1;
176 u32 evm2; 182 __be32 evm2;
177}; 183};
178 184
179#define ATH9K_RXERR_CRC 0x01 185#define ATH9K_RXERR_CRC 0x01
@@ -259,7 +265,8 @@ struct ath_desc {
259#define ATH9K_TXDESC_EXT_AND_CTL 0x0080 265#define ATH9K_TXDESC_EXT_AND_CTL 0x0080
260#define ATH9K_TXDESC_VMF 0x0100 266#define ATH9K_TXDESC_VMF 0x0100
261#define ATH9K_TXDESC_FRAG_IS_ON 0x0200 267#define ATH9K_TXDESC_FRAG_IS_ON 0x0200
262#define ATH9K_TXDESC_CAB 0x0400 268#define ATH9K_TXDESC_LOWRXCHAIN 0x0400
269#define ATH9K_TXDESC_LDPC 0x00010000
263 270
264#define ATH9K_RXDESC_INTREQ 0x0020 271#define ATH9K_RXDESC_INTREQ 0x0020
265 272
@@ -353,7 +360,6 @@ struct ar5416_desc {
353#define AR_DestIdxValid 0x40000000 360#define AR_DestIdxValid 0x40000000
354#define AR_CTSEnable 0x80000000 361#define AR_CTSEnable 0x80000000
355 362
356#define AR_BufLen 0x00000fff
357#define AR_TxMore 0x00001000 363#define AR_TxMore 0x00001000
358#define AR_DestIdx 0x000fe000 364#define AR_DestIdx 0x000fe000
359#define AR_DestIdx_S 13 365#define AR_DestIdx_S 13
@@ -410,6 +416,7 @@ struct ar5416_desc {
410#define AR_EncrType 0x0c000000 416#define AR_EncrType 0x0c000000
411#define AR_EncrType_S 26 417#define AR_EncrType_S 26
412#define AR_TxCtlRsvd61 0xf0000000 418#define AR_TxCtlRsvd61 0xf0000000
419#define AR_LDPC 0x80000000
413 420
414#define AR_2040_0 0x00000001 421#define AR_2040_0 0x00000001
415#define AR_GI0 0x00000002 422#define AR_GI0 0x00000002
@@ -429,7 +436,10 @@ struct ar5416_desc {
429#define AR_ChainSel3_S 17 436#define AR_ChainSel3_S 17
430#define AR_RTSCTSRate 0x0ff00000 437#define AR_RTSCTSRate 0x0ff00000
431#define AR_RTSCTSRate_S 20 438#define AR_RTSCTSRate_S 20
432#define AR_TxCtlRsvd70 0xf0000000 439#define AR_STBC0 0x10000000
440#define AR_STBC1 0x20000000
441#define AR_STBC2 0x40000000
442#define AR_STBC3 0x80000000
433 443
434#define AR_TxRSSIAnt00 0x000000ff 444#define AR_TxRSSIAnt00 0x000000ff
435#define AR_TxRSSIAnt00_S 0 445#define AR_TxRSSIAnt00_S 0
@@ -493,7 +503,6 @@ struct ar5416_desc {
493 503
494#define AR_RxCTLRsvd00 0xffffffff 504#define AR_RxCTLRsvd00 0xffffffff
495 505
496#define AR_BufLen 0x00000fff
497#define AR_RxCtlRsvd00 0x00001000 506#define AR_RxCtlRsvd00 0x00001000
498#define AR_RxIntrReq 0x00002000 507#define AR_RxIntrReq 0x00002000
499#define AR_RxCtlRsvd01 0xffffc000 508#define AR_RxCtlRsvd01 0xffffc000
@@ -643,6 +652,7 @@ enum ath9k_rx_filter {
643#define ATH9K_RATESERIES_RTS_CTS 0x0001 652#define ATH9K_RATESERIES_RTS_CTS 0x0001
644#define ATH9K_RATESERIES_2040 0x0002 653#define ATH9K_RATESERIES_2040 0x0002
645#define ATH9K_RATESERIES_HALFGI 0x0004 654#define ATH9K_RATESERIES_HALFGI 0x0004
655#define ATH9K_RATESERIES_STBC 0x0008
646 656
647struct ath9k_11n_rate_series { 657struct ath9k_11n_rate_series {
648 u32 Tries; 658 u32 Tries;
@@ -686,34 +696,10 @@ struct ath9k_channel;
686u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q); 696u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q);
687void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp); 697void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp);
688void ath9k_hw_txstart(struct ath_hw *ah, u32 q); 698void ath9k_hw_txstart(struct ath_hw *ah, u32 q);
699void ath9k_hw_cleartxdesc(struct ath_hw *ah, void *ds);
689u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q); 700u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q);
690bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel); 701bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel);
691bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q); 702bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q);
692void ath9k_hw_filltxdesc(struct ath_hw *ah, struct ath_desc *ds,
693 u32 segLen, bool firstSeg,
694 bool lastSeg, const struct ath_desc *ds0);
695void ath9k_hw_cleartxdesc(struct ath_hw *ah, struct ath_desc *ds);
696int ath9k_hw_txprocdesc(struct ath_hw *ah, struct ath_desc *ds,
697 struct ath_tx_status *ts);
698void ath9k_hw_set11n_txdesc(struct ath_hw *ah, struct ath_desc *ds,
699 u32 pktLen, enum ath9k_pkt_type type, u32 txPower,
700 u32 keyIx, enum ath9k_key_type keyType, u32 flags);
701void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, struct ath_desc *ds,
702 struct ath_desc *lastds,
703 u32 durUpdateEn, u32 rtsctsRate,
704 u32 rtsctsDuration,
705 struct ath9k_11n_rate_series series[],
706 u32 nseries, u32 flags);
707void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, struct ath_desc *ds,
708 u32 aggrLen);
709void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, struct ath_desc *ds,
710 u32 numDelims);
711void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, struct ath_desc *ds);
712void ath9k_hw_clr11n_aggr(struct ath_hw *ah, struct ath_desc *ds);
713void ath9k_hw_set11n_burstduration(struct ath_hw *ah, struct ath_desc *ds,
714 u32 burstDuration);
715void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, struct ath_desc *ds,
716 u32 vmf);
717void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs); 703void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs);
718bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q, 704bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
719 const struct ath9k_tx_queue_info *qinfo); 705 const struct ath9k_tx_queue_info *qinfo);
@@ -729,10 +715,17 @@ void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
729 u32 size, u32 flags); 715 u32 size, u32 flags);
730bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set); 716bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set);
731void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp); 717void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp);
732void ath9k_hw_rxena(struct ath_hw *ah);
733void ath9k_hw_startpcureceive(struct ath_hw *ah); 718void ath9k_hw_startpcureceive(struct ath_hw *ah);
734void ath9k_hw_stoppcurecv(struct ath_hw *ah); 719void ath9k_hw_stoppcurecv(struct ath_hw *ah);
720void ath9k_hw_abortpcurecv(struct ath_hw *ah);
735bool ath9k_hw_stopdmarecv(struct ath_hw *ah); 721bool ath9k_hw_stopdmarecv(struct ath_hw *ah);
736int ath9k_hw_beaconq_setup(struct ath_hw *ah); 722int ath9k_hw_beaconq_setup(struct ath_hw *ah);
737 723
724/* Interrupt Handling */
725bool ath9k_hw_intrpend(struct ath_hw *ah);
726enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah,
727 enum ath9k_int ints);
728
729void ar9002_hw_attach_mac_ops(struct ath_hw *ah);
730
738#endif /* MAC_H */ 731#endif /* MAC_H */
diff --git a/drivers/net/wireless/ath/ath9k/main.c b/drivers/net/wireless/ath/ath9k/main.c
index f7ef11407e27..893b552981a0 100644
--- a/drivers/net/wireless/ath/ath9k/main.c
+++ b/drivers/net/wireless/ath/ath9k/main.c
@@ -401,23 +401,41 @@ void ath9k_tasklet(unsigned long data)
401 struct ath_common *common = ath9k_hw_common(ah); 401 struct ath_common *common = ath9k_hw_common(ah);
402 402
403 u32 status = sc->intrstatus; 403 u32 status = sc->intrstatus;
404 u32 rxmask;
404 405
405 ath9k_ps_wakeup(sc); 406 ath9k_ps_wakeup(sc);
406 407
407 if (status & ATH9K_INT_FATAL) { 408 if ((status & ATH9K_INT_FATAL) ||
409 !ath9k_hw_check_alive(ah)) {
408 ath_reset(sc, false); 410 ath_reset(sc, false);
409 ath9k_ps_restore(sc); 411 ath9k_ps_restore(sc);
410 return; 412 return;
411 } 413 }
412 414
413 if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) { 415 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
416 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
417 ATH9K_INT_RXORN);
418 else
419 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
420
421 if (status & rxmask) {
414 spin_lock_bh(&sc->rx.rxflushlock); 422 spin_lock_bh(&sc->rx.rxflushlock);
415 ath_rx_tasklet(sc, 0); 423
424 /* Check for high priority Rx first */
425 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
426 (status & ATH9K_INT_RXHP))
427 ath_rx_tasklet(sc, 0, true);
428
429 ath_rx_tasklet(sc, 0, false);
416 spin_unlock_bh(&sc->rx.rxflushlock); 430 spin_unlock_bh(&sc->rx.rxflushlock);
417 } 431 }
418 432
419 if (status & ATH9K_INT_TX) 433 if (status & ATH9K_INT_TX) {
420 ath_tx_tasklet(sc); 434 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
435 ath_tx_edma_tasklet(sc);
436 else
437 ath_tx_tasklet(sc);
438 }
421 439
422 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { 440 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
423 /* 441 /*
@@ -445,6 +463,8 @@ irqreturn_t ath_isr(int irq, void *dev)
445 ATH9K_INT_RXORN | \ 463 ATH9K_INT_RXORN | \
446 ATH9K_INT_RXEOL | \ 464 ATH9K_INT_RXEOL | \
447 ATH9K_INT_RX | \ 465 ATH9K_INT_RX | \
466 ATH9K_INT_RXLP | \
467 ATH9K_INT_RXHP | \
448 ATH9K_INT_TX | \ 468 ATH9K_INT_TX | \
449 ATH9K_INT_BMISS | \ 469 ATH9K_INT_BMISS | \
450 ATH9K_INT_CST | \ 470 ATH9K_INT_CST | \
@@ -496,7 +516,8 @@ irqreturn_t ath_isr(int irq, void *dev)
496 * If a FATAL or RXORN interrupt is received, we have to reset the 516 * If a FATAL or RXORN interrupt is received, we have to reset the
497 * chip immediately. 517 * chip immediately.
498 */ 518 */
499 if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN)) 519 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
520 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
500 goto chip_reset; 521 goto chip_reset;
501 522
502 if (status & ATH9K_INT_SWBA) 523 if (status & ATH9K_INT_SWBA)
@@ -505,6 +526,13 @@ irqreturn_t ath_isr(int irq, void *dev)
505 if (status & ATH9K_INT_TXURN) 526 if (status & ATH9K_INT_TXURN)
506 ath9k_hw_updatetxtriglevel(ah, true); 527 ath9k_hw_updatetxtriglevel(ah, true);
507 528
529 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
530 if (status & ATH9K_INT_RXEOL) {
531 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
532 ath9k_hw_set_interrupts(ah, ah->imask);
533 }
534 }
535
508 if (status & ATH9K_INT_MIB) { 536 if (status & ATH9K_INT_MIB) {
509 /* 537 /*
510 * Disable interrupts until we service the MIB 538 * Disable interrupts until we service the MIB
@@ -724,6 +752,7 @@ static int ath_key_config(struct ath_common *common,
724 struct ath_hw *ah = common->ah; 752 struct ath_hw *ah = common->ah;
725 struct ath9k_keyval hk; 753 struct ath9k_keyval hk;
726 const u8 *mac = NULL; 754 const u8 *mac = NULL;
755 u8 gmac[ETH_ALEN];
727 int ret = 0; 756 int ret = 0;
728 int idx; 757 int idx;
729 758
@@ -747,9 +776,30 @@ static int ath_key_config(struct ath_common *common,
747 memcpy(hk.kv_val, key->key, key->keylen); 776 memcpy(hk.kv_val, key->key, key->keylen);
748 777
749 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) { 778 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
750 /* For now, use the default keys for broadcast keys. This may 779
751 * need to change with virtual interfaces. */ 780 if (key->ap_addr) {
752 idx = key->keyidx; 781 /*
782 * Group keys on hardware that supports multicast frame
783 * key search use a mac that is the sender's address with
784 * the high bit set instead of the app-specified address.
785 */
786 memcpy(gmac, key->ap_addr, ETH_ALEN);
787 gmac[0] |= 0x80;
788 mac = gmac;
789
790 if (key->alg == ALG_TKIP)
791 idx = ath_reserve_key_cache_slot_tkip(common);
792 else
793 idx = ath_reserve_key_cache_slot(common);
794 if (idx < 0)
795 mac = NULL; /* no free key cache entries */
796 }
797
798 if (!mac) {
799 /* For now, use the default keys for broadcast keys. This may
800 * need to change with virtual interfaces. */
801 idx = key->keyidx;
802 }
753 } else if (key->keyidx) { 803 } else if (key->keyidx) {
754 if (WARN_ON(!sta)) 804 if (WARN_ON(!sta))
755 return -EOPNOTSUPP; 805 return -EOPNOTSUPP;
@@ -1162,9 +1212,14 @@ static int ath9k_start(struct ieee80211_hw *hw)
1162 } 1212 }
1163 1213
1164 /* Setup our intr mask. */ 1214 /* Setup our intr mask. */
1165 ah->imask = ATH9K_INT_RX | ATH9K_INT_TX 1215 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
1166 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN 1216 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
1167 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL; 1217 ATH9K_INT_GLOBAL;
1218
1219 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
1220 ah->imask |= ATH9K_INT_RXHP | ATH9K_INT_RXLP;
1221 else
1222 ah->imask |= ATH9K_INT_RX;
1168 1223
1169 if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT) 1224 if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
1170 ah->imask |= ATH9K_INT_GTT; 1225 ah->imask |= ATH9K_INT_GTT;
@@ -1436,7 +1491,8 @@ static int ath9k_add_interface(struct ieee80211_hw *hw,
1436 if ((vif->type == NL80211_IFTYPE_STATION) || 1491 if ((vif->type == NL80211_IFTYPE_STATION) ||
1437 (vif->type == NL80211_IFTYPE_ADHOC) || 1492 (vif->type == NL80211_IFTYPE_ADHOC) ||
1438 (vif->type == NL80211_IFTYPE_MESH_POINT)) { 1493 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
1439 ah->imask |= ATH9K_INT_MIB; 1494 if (ah->config.enable_ani)
1495 ah->imask |= ATH9K_INT_MIB;
1440 ah->imask |= ATH9K_INT_TSFOOR; 1496 ah->imask |= ATH9K_INT_TSFOOR;
1441 } 1497 }
1442 1498
@@ -1988,6 +2044,25 @@ static int ath9k_ampdu_action(struct ieee80211_hw *hw,
1988 return ret; 2044 return ret;
1989} 2045}
1990 2046
2047static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
2048 struct survey_info *survey)
2049{
2050 struct ath_wiphy *aphy = hw->priv;
2051 struct ath_softc *sc = aphy->sc;
2052 struct ath_hw *ah = sc->sc_ah;
2053 struct ath_common *common = ath9k_hw_common(ah);
2054 struct ieee80211_conf *conf = &hw->conf;
2055
2056 if (idx != 0)
2057 return -ENOENT;
2058
2059 survey->channel = conf->channel;
2060 survey->filled = SURVEY_INFO_NOISE_DBM;
2061 survey->noise = common->ani.noise_floor;
2062
2063 return 0;
2064}
2065
1991static void ath9k_sw_scan_start(struct ieee80211_hw *hw) 2066static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
1992{ 2067{
1993 struct ath_wiphy *aphy = hw->priv; 2068 struct ath_wiphy *aphy = hw->priv;
@@ -2059,6 +2134,7 @@ struct ieee80211_ops ath9k_ops = {
2059 .set_tsf = ath9k_set_tsf, 2134 .set_tsf = ath9k_set_tsf,
2060 .reset_tsf = ath9k_reset_tsf, 2135 .reset_tsf = ath9k_reset_tsf,
2061 .ampdu_action = ath9k_ampdu_action, 2136 .ampdu_action = ath9k_ampdu_action,
2137 .get_survey = ath9k_get_survey,
2062 .sw_scan_start = ath9k_sw_scan_start, 2138 .sw_scan_start = ath9k_sw_scan_start,
2063 .sw_scan_complete = ath9k_sw_scan_complete, 2139 .sw_scan_complete = ath9k_sw_scan_complete,
2064 .rfkill_poll = ath9k_rfkill_poll_state, 2140 .rfkill_poll = ath9k_rfkill_poll_state,
diff --git a/drivers/net/wireless/ath/ath9k/pci.c b/drivers/net/wireless/ath/ath9k/pci.c
index 1ec836cf1c0d..257b10ba6f57 100644
--- a/drivers/net/wireless/ath/ath9k/pci.c
+++ b/drivers/net/wireless/ath/ath9k/pci.c
@@ -28,6 +28,7 @@ static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
28 { PCI_VDEVICE(ATHEROS, 0x002C) }, /* PCI-E 802.11n bonded out */ 28 { PCI_VDEVICE(ATHEROS, 0x002C) }, /* PCI-E 802.11n bonded out */
29 { PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI */ 29 { PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI */
30 { PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */ 30 { PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */
31 { PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E AR9300 */
31 { 0 } 32 { 0 }
32}; 33};
33 34
diff --git a/drivers/net/wireless/ath/ath9k/phy.c b/drivers/net/wireless/ath/ath9k/phy.c
deleted file mode 100644
index 2547b3c4a26c..000000000000
--- a/drivers/net/wireless/ath/ath9k/phy.c
+++ /dev/null
@@ -1,978 +0,0 @@
1/*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17/**
18 * DOC: Programming Atheros 802.11n analog front end radios
19 *
20 * AR5416 MAC based PCI devices and AR518 MAC based PCI-Express
21 * devices have either an external AR2133 analog front end radio for single
22 * band 2.4 GHz communication or an AR5133 analog front end radio for dual
23 * band 2.4 GHz / 5 GHz communication.
24 *
25 * All devices after the AR5416 and AR5418 family starting with the AR9280
26 * have their analog front radios, MAC/BB and host PCIe/USB interface embedded
27 * into a single-chip and require less programming.
28 *
29 * The following single-chips exist with a respective embedded radio:
30 *
31 * AR9280 - 11n dual-band 2x2 MIMO for PCIe
32 * AR9281 - 11n single-band 1x2 MIMO for PCIe
33 * AR9285 - 11n single-band 1x1 for PCIe
34 * AR9287 - 11n single-band 2x2 MIMO for PCIe
35 *
36 * AR9220 - 11n dual-band 2x2 MIMO for PCI
37 * AR9223 - 11n single-band 2x2 MIMO for PCI
38 *
39 * AR9287 - 11n single-band 1x1 MIMO for USB
40 */
41
42#include <linux/slab.h>
43
44#include "hw.h"
45
46/**
47 * ath9k_hw_write_regs - ??
48 *
49 * @ah: atheros hardware structure
50 * @freqIndex:
51 * @regWrites:
52 *
53 * Used for both the chipsets with an external AR2133/AR5133 radios and
54 * single-chip devices.
55 */
56void ath9k_hw_write_regs(struct ath_hw *ah, u32 freqIndex, int regWrites)
57{
58 REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
59}
60
61/**
62 * ath9k_hw_ar9280_set_channel - set channel on single-chip device
63 * @ah: atheros hardware structure
64 * @chan:
65 *
66 * This is the function to change channel on single-chip devices, that is
67 * all devices after ar9280.
68 *
69 * This function takes the channel value in MHz and sets
70 * hardware channel value. Assumes writes have been enabled to analog bus.
71 *
72 * Actual Expression,
73 *
74 * For 2GHz channel,
75 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
76 * (freq_ref = 40MHz)
77 *
78 * For 5GHz channel,
79 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
80 * (freq_ref = 40MHz/(24>>amodeRefSel))
81 */
82int ath9k_hw_ar9280_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
83{
84 u16 bMode, fracMode, aModeRefSel = 0;
85 u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
86 struct chan_centers centers;
87 u32 refDivA = 24;
88
89 ath9k_hw_get_channel_centers(ah, chan, &centers);
90 freq = centers.synth_center;
91
92 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL);
93 reg32 &= 0xc0000000;
94
95 if (freq < 4800) { /* 2 GHz, fractional mode */
96 u32 txctl;
97 int regWrites = 0;
98
99 bMode = 1;
100 fracMode = 1;
101 aModeRefSel = 0;
102 channelSel = (freq * 0x10000) / 15;
103
104 if (AR_SREV_9287_11_OR_LATER(ah)) {
105 if (freq == 2484) {
106 /* Enable channel spreading for channel 14 */
107 REG_WRITE_ARRAY(&ah->iniCckfirJapan2484,
108 1, regWrites);
109 } else {
110 REG_WRITE_ARRAY(&ah->iniCckfirNormal,
111 1, regWrites);
112 }
113 } else {
114 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
115 if (freq == 2484) {
116 /* Enable channel spreading for channel 14 */
117 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
118 txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
119 } else {
120 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
121 txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);
122 }
123 }
124 } else {
125 bMode = 0;
126 fracMode = 0;
127
128 switch(ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) {
129 case 0:
130 if ((freq % 20) == 0) {
131 aModeRefSel = 3;
132 } else if ((freq % 10) == 0) {
133 aModeRefSel = 2;
134 }
135 if (aModeRefSel)
136 break;
137 case 1:
138 default:
139 aModeRefSel = 0;
140 /*
141 * Enable 2G (fractional) mode for channels
142 * which are 5MHz spaced.
143 */
144 fracMode = 1;
145 refDivA = 1;
146 channelSel = (freq * 0x8000) / 15;
147
148 /* RefDivA setting */
149 REG_RMW_FIELD(ah, AR_AN_SYNTH9,
150 AR_AN_SYNTH9_REFDIVA, refDivA);
151
152 }
153
154 if (!fracMode) {
155 ndiv = (freq * (refDivA >> aModeRefSel)) / 60;
156 channelSel = ndiv & 0x1ff;
157 channelFrac = (ndiv & 0xfffffe00) * 2;
158 channelSel = (channelSel << 17) | channelFrac;
159 }
160 }
161
162 reg32 = reg32 |
163 (bMode << 29) |
164 (fracMode << 28) | (aModeRefSel << 26) | (channelSel);
165
166 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
167
168 ah->curchan = chan;
169 ah->curchan_rad_index = -1;
170
171 return 0;
172}
173
174/**
175 * ath9k_hw_9280_spur_mitigate - convert baseband spur frequency
176 * @ah: atheros hardware structure
177 * @chan:
178 *
179 * For single-chip solutions. Converts to baseband spur frequency given the
180 * input channel frequency and compute register settings below.
181 */
182void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
183{
184 int bb_spur = AR_NO_SPUR;
185 int freq;
186 int bin, cur_bin;
187 int bb_spur_off, spur_subchannel_sd;
188 int spur_freq_sd;
189 int spur_delta_phase;
190 int denominator;
191 int upper, lower, cur_vit_mask;
192 int tmp, newVal;
193 int i;
194 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
195 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
196 };
197 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
198 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
199 };
200 int inc[4] = { 0, 100, 0, 0 };
201 struct chan_centers centers;
202
203 int8_t mask_m[123];
204 int8_t mask_p[123];
205 int8_t mask_amt;
206 int tmp_mask;
207 int cur_bb_spur;
208 bool is2GHz = IS_CHAN_2GHZ(chan);
209
210 memset(&mask_m, 0, sizeof(int8_t) * 123);
211 memset(&mask_p, 0, sizeof(int8_t) * 123);
212
213 ath9k_hw_get_channel_centers(ah, chan, &centers);
214 freq = centers.synth_center;
215
216 ah->config.spurmode = SPUR_ENABLE_EEPROM;
217 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
218 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
219
220 if (is2GHz)
221 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
222 else
223 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
224
225 if (AR_NO_SPUR == cur_bb_spur)
226 break;
227 cur_bb_spur = cur_bb_spur - freq;
228
229 if (IS_CHAN_HT40(chan)) {
230 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
231 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
232 bb_spur = cur_bb_spur;
233 break;
234 }
235 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
236 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
237 bb_spur = cur_bb_spur;
238 break;
239 }
240 }
241
242 if (AR_NO_SPUR == bb_spur) {
243 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
244 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
245 return;
246 } else {
247 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
248 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
249 }
250
251 bin = bb_spur * 320;
252
253 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
254
255 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
256 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
257 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
258 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
259 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
260
261 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
262 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
263 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
264 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
265 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
266 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
267
268 if (IS_CHAN_HT40(chan)) {
269 if (bb_spur < 0) {
270 spur_subchannel_sd = 1;
271 bb_spur_off = bb_spur + 10;
272 } else {
273 spur_subchannel_sd = 0;
274 bb_spur_off = bb_spur - 10;
275 }
276 } else {
277 spur_subchannel_sd = 0;
278 bb_spur_off = bb_spur;
279 }
280
281 if (IS_CHAN_HT40(chan))
282 spur_delta_phase =
283 ((bb_spur * 262144) /
284 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
285 else
286 spur_delta_phase =
287 ((bb_spur * 524288) /
288 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
289
290 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
291 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
292
293 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
294 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
295 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
296 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
297
298 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
299 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
300
301 cur_bin = -6000;
302 upper = bin + 100;
303 lower = bin - 100;
304
305 for (i = 0; i < 4; i++) {
306 int pilot_mask = 0;
307 int chan_mask = 0;
308 int bp = 0;
309 for (bp = 0; bp < 30; bp++) {
310 if ((cur_bin > lower) && (cur_bin < upper)) {
311 pilot_mask = pilot_mask | 0x1 << bp;
312 chan_mask = chan_mask | 0x1 << bp;
313 }
314 cur_bin += 100;
315 }
316 cur_bin += inc[i];
317 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
318 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
319 }
320
321 cur_vit_mask = 6100;
322 upper = bin + 120;
323 lower = bin - 120;
324
325 for (i = 0; i < 123; i++) {
326 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
327
328 /* workaround for gcc bug #37014 */
329 volatile int tmp_v = abs(cur_vit_mask - bin);
330
331 if (tmp_v < 75)
332 mask_amt = 1;
333 else
334 mask_amt = 0;
335 if (cur_vit_mask < 0)
336 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
337 else
338 mask_p[cur_vit_mask / 100] = mask_amt;
339 }
340 cur_vit_mask -= 100;
341 }
342
343 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
344 | (mask_m[48] << 26) | (mask_m[49] << 24)
345 | (mask_m[50] << 22) | (mask_m[51] << 20)
346 | (mask_m[52] << 18) | (mask_m[53] << 16)
347 | (mask_m[54] << 14) | (mask_m[55] << 12)
348 | (mask_m[56] << 10) | (mask_m[57] << 8)
349 | (mask_m[58] << 6) | (mask_m[59] << 4)
350 | (mask_m[60] << 2) | (mask_m[61] << 0);
351 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
352 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
353
354 tmp_mask = (mask_m[31] << 28)
355 | (mask_m[32] << 26) | (mask_m[33] << 24)
356 | (mask_m[34] << 22) | (mask_m[35] << 20)
357 | (mask_m[36] << 18) | (mask_m[37] << 16)
358 | (mask_m[48] << 14) | (mask_m[39] << 12)
359 | (mask_m[40] << 10) | (mask_m[41] << 8)
360 | (mask_m[42] << 6) | (mask_m[43] << 4)
361 | (mask_m[44] << 2) | (mask_m[45] << 0);
362 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
363 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
364
365 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
366 | (mask_m[18] << 26) | (mask_m[18] << 24)
367 | (mask_m[20] << 22) | (mask_m[20] << 20)
368 | (mask_m[22] << 18) | (mask_m[22] << 16)
369 | (mask_m[24] << 14) | (mask_m[24] << 12)
370 | (mask_m[25] << 10) | (mask_m[26] << 8)
371 | (mask_m[27] << 6) | (mask_m[28] << 4)
372 | (mask_m[29] << 2) | (mask_m[30] << 0);
373 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
374 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
375
376 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
377 | (mask_m[2] << 26) | (mask_m[3] << 24)
378 | (mask_m[4] << 22) | (mask_m[5] << 20)
379 | (mask_m[6] << 18) | (mask_m[7] << 16)
380 | (mask_m[8] << 14) | (mask_m[9] << 12)
381 | (mask_m[10] << 10) | (mask_m[11] << 8)
382 | (mask_m[12] << 6) | (mask_m[13] << 4)
383 | (mask_m[14] << 2) | (mask_m[15] << 0);
384 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
385 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
386
387 tmp_mask = (mask_p[15] << 28)
388 | (mask_p[14] << 26) | (mask_p[13] << 24)
389 | (mask_p[12] << 22) | (mask_p[11] << 20)
390 | (mask_p[10] << 18) | (mask_p[9] << 16)
391 | (mask_p[8] << 14) | (mask_p[7] << 12)
392 | (mask_p[6] << 10) | (mask_p[5] << 8)
393 | (mask_p[4] << 6) | (mask_p[3] << 4)
394 | (mask_p[2] << 2) | (mask_p[1] << 0);
395 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
396 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
397
398 tmp_mask = (mask_p[30] << 28)
399 | (mask_p[29] << 26) | (mask_p[28] << 24)
400 | (mask_p[27] << 22) | (mask_p[26] << 20)
401 | (mask_p[25] << 18) | (mask_p[24] << 16)
402 | (mask_p[23] << 14) | (mask_p[22] << 12)
403 | (mask_p[21] << 10) | (mask_p[20] << 8)
404 | (mask_p[19] << 6) | (mask_p[18] << 4)
405 | (mask_p[17] << 2) | (mask_p[16] << 0);
406 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
407 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
408
409 tmp_mask = (mask_p[45] << 28)
410 | (mask_p[44] << 26) | (mask_p[43] << 24)
411 | (mask_p[42] << 22) | (mask_p[41] << 20)
412 | (mask_p[40] << 18) | (mask_p[39] << 16)
413 | (mask_p[38] << 14) | (mask_p[37] << 12)
414 | (mask_p[36] << 10) | (mask_p[35] << 8)
415 | (mask_p[34] << 6) | (mask_p[33] << 4)
416 | (mask_p[32] << 2) | (mask_p[31] << 0);
417 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
418 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
419
420 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
421 | (mask_p[59] << 26) | (mask_p[58] << 24)
422 | (mask_p[57] << 22) | (mask_p[56] << 20)
423 | (mask_p[55] << 18) | (mask_p[54] << 16)
424 | (mask_p[53] << 14) | (mask_p[52] << 12)
425 | (mask_p[51] << 10) | (mask_p[50] << 8)
426 | (mask_p[49] << 6) | (mask_p[48] << 4)
427 | (mask_p[47] << 2) | (mask_p[46] << 0);
428 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
429 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
430}
431
432/* All code below is for non single-chip solutions */
433
434/**
435 * ath9k_phy_modify_rx_buffer() - perform analog swizzling of parameters
436 * @rfbuf:
437 * @reg32:
438 * @numBits:
439 * @firstBit:
440 * @column:
441 *
442 * Performs analog "swizzling" of parameters into their location.
443 * Used on external AR2133/AR5133 radios.
444 */
445static void ath9k_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
446 u32 numBits, u32 firstBit,
447 u32 column)
448{
449 u32 tmp32, mask, arrayEntry, lastBit;
450 int32_t bitPosition, bitsLeft;
451
452 tmp32 = ath9k_hw_reverse_bits(reg32, numBits);
453 arrayEntry = (firstBit - 1) / 8;
454 bitPosition = (firstBit - 1) % 8;
455 bitsLeft = numBits;
456 while (bitsLeft > 0) {
457 lastBit = (bitPosition + bitsLeft > 8) ?
458 8 : bitPosition + bitsLeft;
459 mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) <<
460 (column * 8);
461 rfBuf[arrayEntry] &= ~mask;
462 rfBuf[arrayEntry] |= ((tmp32 << bitPosition) <<
463 (column * 8)) & mask;
464 bitsLeft -= 8 - bitPosition;
465 tmp32 = tmp32 >> (8 - bitPosition);
466 bitPosition = 0;
467 arrayEntry++;
468 }
469}
470
471/*
472 * Fix on 2.4 GHz band for orientation sensitivity issue by increasing
473 * rf_pwd_icsyndiv.
474 *
475 * Theoretical Rules:
476 * if 2 GHz band
477 * if forceBiasAuto
478 * if synth_freq < 2412
479 * bias = 0
480 * else if 2412 <= synth_freq <= 2422
481 * bias = 1
482 * else // synth_freq > 2422
483 * bias = 2
484 * else if forceBias > 0
485 * bias = forceBias & 7
486 * else
487 * no change, use value from ini file
488 * else
489 * no change, invalid band
490 *
491 * 1st Mod:
492 * 2422 also uses value of 2
493 * <approved>
494 *
495 * 2nd Mod:
496 * Less than 2412 uses value of 0, 2412 and above uses value of 2
497 */
498static void ath9k_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
499{
500 struct ath_common *common = ath9k_hw_common(ah);
501 u32 tmp_reg;
502 int reg_writes = 0;
503 u32 new_bias = 0;
504
505 if (!AR_SREV_5416(ah) || synth_freq >= 3000) {
506 return;
507 }
508
509 BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
510
511 if (synth_freq < 2412)
512 new_bias = 0;
513 else if (synth_freq < 2422)
514 new_bias = 1;
515 else
516 new_bias = 2;
517
518 /* pre-reverse this field */
519 tmp_reg = ath9k_hw_reverse_bits(new_bias, 3);
520
521 ath_print(common, ATH_DBG_CONFIG,
522 "Force rf_pwd_icsyndiv to %1d on %4d\n",
523 new_bias, synth_freq);
524
525 /* swizzle rf_pwd_icsyndiv */
526 ath9k_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3);
527
528 /* write Bank 6 with new params */
529 REG_WRITE_RF_ARRAY(&ah->iniBank6, ah->analogBank6Data, reg_writes);
530}
531
532/**
533 * ath9k_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios
534 * @ah: atheros hardware stucture
535 * @chan:
536 *
537 * For the external AR2133/AR5133 radios, takes the MHz channel value and set
538 * the channel value. Assumes writes enabled to analog bus and bank6 register
539 * cache in ah->analogBank6Data.
540 */
541int ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
542{
543 struct ath_common *common = ath9k_hw_common(ah);
544 u32 channelSel = 0;
545 u32 bModeSynth = 0;
546 u32 aModeRefSel = 0;
547 u32 reg32 = 0;
548 u16 freq;
549 struct chan_centers centers;
550
551 ath9k_hw_get_channel_centers(ah, chan, &centers);
552 freq = centers.synth_center;
553
554 if (freq < 4800) {
555 u32 txctl;
556
557 if (((freq - 2192) % 5) == 0) {
558 channelSel = ((freq - 672) * 2 - 3040) / 10;
559 bModeSynth = 0;
560 } else if (((freq - 2224) % 5) == 0) {
561 channelSel = ((freq - 704) * 2 - 3040) / 10;
562 bModeSynth = 1;
563 } else {
564 ath_print(common, ATH_DBG_FATAL,
565 "Invalid channel %u MHz\n", freq);
566 return -EINVAL;
567 }
568
569 channelSel = (channelSel << 2) & 0xff;
570 channelSel = ath9k_hw_reverse_bits(channelSel, 8);
571
572 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
573 if (freq == 2484) {
574
575 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
576 txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
577 } else {
578 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
579 txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
580 }
581
582 } else if ((freq % 20) == 0 && freq >= 5120) {
583 channelSel =
584 ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
585 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
586 } else if ((freq % 10) == 0) {
587 channelSel =
588 ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
589 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
590 aModeRefSel = ath9k_hw_reverse_bits(2, 2);
591 else
592 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
593 } else if ((freq % 5) == 0) {
594 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
595 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
596 } else {
597 ath_print(common, ATH_DBG_FATAL,
598 "Invalid channel %u MHz\n", freq);
599 return -EINVAL;
600 }
601
602 ath9k_hw_force_bias(ah, freq);
603
604 reg32 =
605 (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
606 (1 << 5) | 0x1;
607
608 REG_WRITE(ah, AR_PHY(0x37), reg32);
609
610 ah->curchan = chan;
611 ah->curchan_rad_index = -1;
612
613 return 0;
614}
615
616/**
617 * ath9k_hw_spur_mitigate - convert baseband spur frequency for external radios
618 * @ah: atheros hardware structure
619 * @chan:
620 *
621 * For non single-chip solutions. Converts to baseband spur frequency given the
622 * input channel frequency and compute register settings below.
623 */
624void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
625{
626 int bb_spur = AR_NO_SPUR;
627 int bin, cur_bin;
628 int spur_freq_sd;
629 int spur_delta_phase;
630 int denominator;
631 int upper, lower, cur_vit_mask;
632 int tmp, new;
633 int i;
634 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
635 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
636 };
637 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
638 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
639 };
640 int inc[4] = { 0, 100, 0, 0 };
641
642 int8_t mask_m[123];
643 int8_t mask_p[123];
644 int8_t mask_amt;
645 int tmp_mask;
646 int cur_bb_spur;
647 bool is2GHz = IS_CHAN_2GHZ(chan);
648
649 memset(&mask_m, 0, sizeof(int8_t) * 123);
650 memset(&mask_p, 0, sizeof(int8_t) * 123);
651
652 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
653 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
654 if (AR_NO_SPUR == cur_bb_spur)
655 break;
656 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
657 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
658 bb_spur = cur_bb_spur;
659 break;
660 }
661 }
662
663 if (AR_NO_SPUR == bb_spur)
664 return;
665
666 bin = bb_spur * 32;
667
668 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
669 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
670 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
671 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
672 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
673
674 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
675
676 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
677 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
678 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
679 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
680 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
681 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
682
683 spur_delta_phase = ((bb_spur * 524288) / 100) &
684 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
685
686 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
687 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
688
689 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
690 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
691 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
692 REG_WRITE(ah, AR_PHY_TIMING11, new);
693
694 cur_bin = -6000;
695 upper = bin + 100;
696 lower = bin - 100;
697
698 for (i = 0; i < 4; i++) {
699 int pilot_mask = 0;
700 int chan_mask = 0;
701 int bp = 0;
702 for (bp = 0; bp < 30; bp++) {
703 if ((cur_bin > lower) && (cur_bin < upper)) {
704 pilot_mask = pilot_mask | 0x1 << bp;
705 chan_mask = chan_mask | 0x1 << bp;
706 }
707 cur_bin += 100;
708 }
709 cur_bin += inc[i];
710 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
711 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
712 }
713
714 cur_vit_mask = 6100;
715 upper = bin + 120;
716 lower = bin - 120;
717
718 for (i = 0; i < 123; i++) {
719 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
720
721 /* workaround for gcc bug #37014 */
722 volatile int tmp_v = abs(cur_vit_mask - bin);
723
724 if (tmp_v < 75)
725 mask_amt = 1;
726 else
727 mask_amt = 0;
728 if (cur_vit_mask < 0)
729 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
730 else
731 mask_p[cur_vit_mask / 100] = mask_amt;
732 }
733 cur_vit_mask -= 100;
734 }
735
736 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
737 | (mask_m[48] << 26) | (mask_m[49] << 24)
738 | (mask_m[50] << 22) | (mask_m[51] << 20)
739 | (mask_m[52] << 18) | (mask_m[53] << 16)
740 | (mask_m[54] << 14) | (mask_m[55] << 12)
741 | (mask_m[56] << 10) | (mask_m[57] << 8)
742 | (mask_m[58] << 6) | (mask_m[59] << 4)
743 | (mask_m[60] << 2) | (mask_m[61] << 0);
744 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
745 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
746
747 tmp_mask = (mask_m[31] << 28)
748 | (mask_m[32] << 26) | (mask_m[33] << 24)
749 | (mask_m[34] << 22) | (mask_m[35] << 20)
750 | (mask_m[36] << 18) | (mask_m[37] << 16)
751 | (mask_m[48] << 14) | (mask_m[39] << 12)
752 | (mask_m[40] << 10) | (mask_m[41] << 8)
753 | (mask_m[42] << 6) | (mask_m[43] << 4)
754 | (mask_m[44] << 2) | (mask_m[45] << 0);
755 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
756 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
757
758 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
759 | (mask_m[18] << 26) | (mask_m[18] << 24)
760 | (mask_m[20] << 22) | (mask_m[20] << 20)
761 | (mask_m[22] << 18) | (mask_m[22] << 16)
762 | (mask_m[24] << 14) | (mask_m[24] << 12)
763 | (mask_m[25] << 10) | (mask_m[26] << 8)
764 | (mask_m[27] << 6) | (mask_m[28] << 4)
765 | (mask_m[29] << 2) | (mask_m[30] << 0);
766 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
767 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
768
769 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
770 | (mask_m[2] << 26) | (mask_m[3] << 24)
771 | (mask_m[4] << 22) | (mask_m[5] << 20)
772 | (mask_m[6] << 18) | (mask_m[7] << 16)
773 | (mask_m[8] << 14) | (mask_m[9] << 12)
774 | (mask_m[10] << 10) | (mask_m[11] << 8)
775 | (mask_m[12] << 6) | (mask_m[13] << 4)
776 | (mask_m[14] << 2) | (mask_m[15] << 0);
777 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
778 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
779
780 tmp_mask = (mask_p[15] << 28)
781 | (mask_p[14] << 26) | (mask_p[13] << 24)
782 | (mask_p[12] << 22) | (mask_p[11] << 20)
783 | (mask_p[10] << 18) | (mask_p[9] << 16)
784 | (mask_p[8] << 14) | (mask_p[7] << 12)
785 | (mask_p[6] << 10) | (mask_p[5] << 8)
786 | (mask_p[4] << 6) | (mask_p[3] << 4)
787 | (mask_p[2] << 2) | (mask_p[1] << 0);
788 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
789 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
790
791 tmp_mask = (mask_p[30] << 28)
792 | (mask_p[29] << 26) | (mask_p[28] << 24)
793 | (mask_p[27] << 22) | (mask_p[26] << 20)
794 | (mask_p[25] << 18) | (mask_p[24] << 16)
795 | (mask_p[23] << 14) | (mask_p[22] << 12)
796 | (mask_p[21] << 10) | (mask_p[20] << 8)
797 | (mask_p[19] << 6) | (mask_p[18] << 4)
798 | (mask_p[17] << 2) | (mask_p[16] << 0);
799 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
800 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
801
802 tmp_mask = (mask_p[45] << 28)
803 | (mask_p[44] << 26) | (mask_p[43] << 24)
804 | (mask_p[42] << 22) | (mask_p[41] << 20)
805 | (mask_p[40] << 18) | (mask_p[39] << 16)
806 | (mask_p[38] << 14) | (mask_p[37] << 12)
807 | (mask_p[36] << 10) | (mask_p[35] << 8)
808 | (mask_p[34] << 6) | (mask_p[33] << 4)
809 | (mask_p[32] << 2) | (mask_p[31] << 0);
810 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
811 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
812
813 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
814 | (mask_p[59] << 26) | (mask_p[58] << 24)
815 | (mask_p[57] << 22) | (mask_p[56] << 20)
816 | (mask_p[55] << 18) | (mask_p[54] << 16)
817 | (mask_p[53] << 14) | (mask_p[52] << 12)
818 | (mask_p[51] << 10) | (mask_p[50] << 8)
819 | (mask_p[49] << 6) | (mask_p[48] << 4)
820 | (mask_p[47] << 2) | (mask_p[46] << 0);
821 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
822 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
823}
824
825/**
826 * ath9k_hw_rf_alloc_ext_banks - allocates banks for external radio programming
827 * @ah: atheros hardware structure
828 *
829 * Only required for older devices with external AR2133/AR5133 radios.
830 */
831int ath9k_hw_rf_alloc_ext_banks(struct ath_hw *ah)
832{
833#define ATH_ALLOC_BANK(bank, size) do { \
834 bank = kzalloc((sizeof(u32) * size), GFP_KERNEL); \
835 if (!bank) { \
836 ath_print(common, ATH_DBG_FATAL, \
837 "Cannot allocate RF banks\n"); \
838 return -ENOMEM; \
839 } \
840 } while (0);
841
842 struct ath_common *common = ath9k_hw_common(ah);
843
844 BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
845
846 ATH_ALLOC_BANK(ah->analogBank0Data, ah->iniBank0.ia_rows);
847 ATH_ALLOC_BANK(ah->analogBank1Data, ah->iniBank1.ia_rows);
848 ATH_ALLOC_BANK(ah->analogBank2Data, ah->iniBank2.ia_rows);
849 ATH_ALLOC_BANK(ah->analogBank3Data, ah->iniBank3.ia_rows);
850 ATH_ALLOC_BANK(ah->analogBank6Data, ah->iniBank6.ia_rows);
851 ATH_ALLOC_BANK(ah->analogBank6TPCData, ah->iniBank6TPC.ia_rows);
852 ATH_ALLOC_BANK(ah->analogBank7Data, ah->iniBank7.ia_rows);
853 ATH_ALLOC_BANK(ah->addac5416_21,
854 ah->iniAddac.ia_rows * ah->iniAddac.ia_columns);
855 ATH_ALLOC_BANK(ah->bank6Temp, ah->iniBank6.ia_rows);
856
857 return 0;
858#undef ATH_ALLOC_BANK
859}
860
861
862/**
863 * ath9k_hw_rf_free_ext_banks - Free memory for analog bank scratch buffers
864 * @ah: atheros hardware struture
865 * For the external AR2133/AR5133 radios banks.
866 */
867void
868ath9k_hw_rf_free_ext_banks(struct ath_hw *ah)
869{
870#define ATH_FREE_BANK(bank) do { \
871 kfree(bank); \
872 bank = NULL; \
873 } while (0);
874
875 BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
876
877 ATH_FREE_BANK(ah->analogBank0Data);
878 ATH_FREE_BANK(ah->analogBank1Data);
879 ATH_FREE_BANK(ah->analogBank2Data);
880 ATH_FREE_BANK(ah->analogBank3Data);
881 ATH_FREE_BANK(ah->analogBank6Data);
882 ATH_FREE_BANK(ah->analogBank6TPCData);
883 ATH_FREE_BANK(ah->analogBank7Data);
884 ATH_FREE_BANK(ah->addac5416_21);
885 ATH_FREE_BANK(ah->bank6Temp);
886
887#undef ATH_FREE_BANK
888}
889
890/* *
891 * ath9k_hw_set_rf_regs - programs rf registers based on EEPROM
892 * @ah: atheros hardware structure
893 * @chan:
894 * @modesIndex:
895 *
896 * Used for the external AR2133/AR5133 radios.
897 *
898 * Reads the EEPROM header info from the device structure and programs
899 * all rf registers. This routine requires access to the analog
900 * rf device. This is not required for single-chip devices.
901 */
902bool ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan,
903 u16 modesIndex)
904{
905 u32 eepMinorRev;
906 u32 ob5GHz = 0, db5GHz = 0;
907 u32 ob2GHz = 0, db2GHz = 0;
908 int regWrites = 0;
909
910 /*
911 * Software does not need to program bank data
912 * for single chip devices, that is AR9280 or anything
913 * after that.
914 */
915 if (AR_SREV_9280_10_OR_LATER(ah))
916 return true;
917
918 /* Setup rf parameters */
919 eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
920
921 /* Setup Bank 0 Write */
922 RF_BANK_SETUP(ah->analogBank0Data, &ah->iniBank0, 1);
923
924 /* Setup Bank 1 Write */
925 RF_BANK_SETUP(ah->analogBank1Data, &ah->iniBank1, 1);
926
927 /* Setup Bank 2 Write */
928 RF_BANK_SETUP(ah->analogBank2Data, &ah->iniBank2, 1);
929
930 /* Setup Bank 6 Write */
931 RF_BANK_SETUP(ah->analogBank3Data, &ah->iniBank3,
932 modesIndex);
933 {
934 int i;
935 for (i = 0; i < ah->iniBank6TPC.ia_rows; i++) {
936 ah->analogBank6Data[i] =
937 INI_RA(&ah->iniBank6TPC, i, modesIndex);
938 }
939 }
940
941 /* Only the 5 or 2 GHz OB/DB need to be set for a mode */
942 if (eepMinorRev >= 2) {
943 if (IS_CHAN_2GHZ(chan)) {
944 ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2);
945 db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2);
946 ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
947 ob2GHz, 3, 197, 0);
948 ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
949 db2GHz, 3, 194, 0);
950 } else {
951 ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5);
952 db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5);
953 ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
954 ob5GHz, 3, 203, 0);
955 ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
956 db5GHz, 3, 200, 0);
957 }
958 }
959
960 /* Setup Bank 7 Setup */
961 RF_BANK_SETUP(ah->analogBank7Data, &ah->iniBank7, 1);
962
963 /* Write Analog registers */
964 REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
965 regWrites);
966 REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data,
967 regWrites);
968 REG_WRITE_RF_ARRAY(&ah->iniBank2, ah->analogBank2Data,
969 regWrites);
970 REG_WRITE_RF_ARRAY(&ah->iniBank3, ah->analogBank3Data,
971 regWrites);
972 REG_WRITE_RF_ARRAY(&ah->iniBank6TPC, ah->analogBank6Data,
973 regWrites);
974 REG_WRITE_RF_ARRAY(&ah->iniBank7, ah->analogBank7Data,
975 regWrites);
976
977 return true;
978}
diff --git a/drivers/net/wireless/ath/ath9k/phy.h b/drivers/net/wireless/ath/ath9k/phy.h
index 0132e4c9a9f9..e724c2c1ae2a 100644
--- a/drivers/net/wireless/ath/ath9k/phy.h
+++ b/drivers/net/wireless/ath/ath9k/phy.h
@@ -17,504 +17,15 @@
17#ifndef PHY_H 17#ifndef PHY_H
18#define PHY_H 18#define PHY_H
19 19
20/* Common between single chip and non single-chip solutions */ 20#define CHANSEL_DIV 15
21void ath9k_hw_write_regs(struct ath_hw *ah, u32 freqIndex, int regWrites); 21#define CHANSEL_2G(_freq) (((_freq) * 0x10000) / CHANSEL_DIV)
22 22#define CHANSEL_5G(_freq) (((_freq) * 0x8000) / CHANSEL_DIV)
23/* Single chip radio settings */
24int ath9k_hw_ar9280_set_channel(struct ath_hw *ah, struct ath9k_channel *chan);
25void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
26
27/* Routines below are for non single-chip solutions */
28int ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan);
29void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
30
31int ath9k_hw_rf_alloc_ext_banks(struct ath_hw *ah);
32void ath9k_hw_rf_free_ext_banks(struct ath_hw *ah);
33
34bool ath9k_hw_set_rf_regs(struct ath_hw *ah,
35 struct ath9k_channel *chan,
36 u16 modesIndex);
37 23
38#define AR_PHY_BASE 0x9800 24#define AR_PHY_BASE 0x9800
39#define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2)) 25#define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2))
40 26
41#define AR_PHY_TEST 0x9800
42#define PHY_AGC_CLR 0x10000000
43#define RFSILENT_BB 0x00002000
44
45#define AR_PHY_TURBO 0x9804
46#define AR_PHY_FC_TURBO_MODE 0x00000001
47#define AR_PHY_FC_TURBO_SHORT 0x00000002
48#define AR_PHY_FC_DYN2040_EN 0x00000004
49#define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008
50#define AR_PHY_FC_DYN2040_PRI_CH 0x00000010
51/* For 25 MHz channel spacing -- not used but supported by hw */
52#define AR_PHY_FC_DYN2040_EXT_CH 0x00000020
53#define AR_PHY_FC_HT_EN 0x00000040
54#define AR_PHY_FC_SHORT_GI_40 0x00000080
55#define AR_PHY_FC_WALSH 0x00000100
56#define AR_PHY_FC_SINGLE_HT_LTF1 0x00000200
57#define AR_PHY_FC_ENABLE_DAC_FIFO 0x00000800
58
59#define AR_PHY_TEST2 0x9808
60
61#define AR_PHY_TIMING2 0x9810
62#define AR_PHY_TIMING3 0x9814
63#define AR_PHY_TIMING3_DSC_MAN 0xFFFE0000
64#define AR_PHY_TIMING3_DSC_MAN_S 17
65#define AR_PHY_TIMING3_DSC_EXP 0x0001E000
66#define AR_PHY_TIMING3_DSC_EXP_S 13
67
68#define AR_PHY_CHIP_ID 0x9818
69#define AR_PHY_CHIP_ID_REV_0 0x80
70#define AR_PHY_CHIP_ID_REV_1 0x81
71#define AR_PHY_CHIP_ID_9160_REV_0 0xb0
72
73#define AR_PHY_ACTIVE 0x981C
74#define AR_PHY_ACTIVE_EN 0x00000001
75#define AR_PHY_ACTIVE_DIS 0x00000000
76
77#define AR_PHY_RF_CTL2 0x9824
78#define AR_PHY_TX_END_DATA_START 0x000000FF
79#define AR_PHY_TX_END_DATA_START_S 0
80#define AR_PHY_TX_END_PA_ON 0x0000FF00
81#define AR_PHY_TX_END_PA_ON_S 8
82
83#define AR_PHY_RF_CTL3 0x9828
84#define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000
85#define AR_PHY_TX_END_TO_A2_RX_ON_S 16
86
87#define AR_PHY_ADC_CTL 0x982C
88#define AR_PHY_ADC_CTL_OFF_INBUFGAIN 0x00000003
89#define AR_PHY_ADC_CTL_OFF_INBUFGAIN_S 0
90#define AR_PHY_ADC_CTL_OFF_PWDDAC 0x00002000
91#define AR_PHY_ADC_CTL_OFF_PWDBANDGAP 0x00004000
92#define AR_PHY_ADC_CTL_OFF_PWDADC 0x00008000
93#define AR_PHY_ADC_CTL_ON_INBUFGAIN 0x00030000
94#define AR_PHY_ADC_CTL_ON_INBUFGAIN_S 16
95
96#define AR_PHY_ADC_SERIAL_CTL 0x9830
97#define AR_PHY_SEL_INTERNAL_ADDAC 0x00000000
98#define AR_PHY_SEL_EXTERNAL_RADIO 0x00000001
99
100#define AR_PHY_RF_CTL4 0x9834
101#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF 0xFF000000
102#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_S 24
103#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF 0x00FF0000
104#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_S 16
105#define AR_PHY_RF_CTL4_FRAME_XPAB_ON 0x0000FF00
106#define AR_PHY_RF_CTL4_FRAME_XPAB_ON_S 8
107#define AR_PHY_RF_CTL4_FRAME_XPAA_ON 0x000000FF
108#define AR_PHY_RF_CTL4_FRAME_XPAA_ON_S 0
109
110#define AR_PHY_TSTDAC_CONST 0x983c
111
112#define AR_PHY_SETTLING 0x9844
113#define AR_PHY_SETTLING_SWITCH 0x00003F80
114#define AR_PHY_SETTLING_SWITCH_S 7
115
116#define AR_PHY_RXGAIN 0x9848
117#define AR_PHY_RXGAIN_TXRX_ATTEN 0x0003F000
118#define AR_PHY_RXGAIN_TXRX_ATTEN_S 12
119#define AR_PHY_RXGAIN_TXRX_RF_MAX 0x007C0000
120#define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18
121#define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80
122#define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7
123#define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000
124#define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14
125
126#define AR_PHY_DESIRED_SZ 0x9850
127#define AR_PHY_DESIRED_SZ_ADC 0x000000FF
128#define AR_PHY_DESIRED_SZ_ADC_S 0
129#define AR_PHY_DESIRED_SZ_PGA 0x0000FF00
130#define AR_PHY_DESIRED_SZ_PGA_S 8
131#define AR_PHY_DESIRED_SZ_TOT_DES 0x0FF00000
132#define AR_PHY_DESIRED_SZ_TOT_DES_S 20
133
134#define AR_PHY_FIND_SIG 0x9858
135#define AR_PHY_FIND_SIG_FIRSTEP 0x0003F000
136#define AR_PHY_FIND_SIG_FIRSTEP_S 12
137#define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000
138#define AR_PHY_FIND_SIG_FIRPWR_S 18
139
140#define AR_PHY_AGC_CTL1 0x985C
141#define AR_PHY_AGC_CTL1_COARSE_LOW 0x00007F80
142#define AR_PHY_AGC_CTL1_COARSE_LOW_S 7
143#define AR_PHY_AGC_CTL1_COARSE_HIGH 0x003F8000
144#define AR_PHY_AGC_CTL1_COARSE_HIGH_S 15
145
146#define AR_PHY_AGC_CONTROL 0x9860
147#define AR_PHY_AGC_CONTROL_CAL 0x00000001
148#define AR_PHY_AGC_CONTROL_NF 0x00000002
149#define AR_PHY_AGC_CONTROL_ENABLE_NF 0x00008000
150#define AR_PHY_AGC_CONTROL_FLTR_CAL 0x00010000
151#define AR_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000
152
153#define AR_PHY_CCA 0x9864
154#define AR_PHY_MINCCA_PWR 0x0FF80000
155#define AR_PHY_MINCCA_PWR_S 19
156#define AR_PHY_CCA_THRESH62 0x0007F000
157#define AR_PHY_CCA_THRESH62_S 12
158#define AR9280_PHY_MINCCA_PWR 0x1FF00000
159#define AR9280_PHY_MINCCA_PWR_S 20
160#define AR9280_PHY_CCA_THRESH62 0x000FF000
161#define AR9280_PHY_CCA_THRESH62_S 12
162
163#define AR_PHY_SFCORR_LOW 0x986C
164#define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001
165#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003F00
166#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8
167#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001FC000
168#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14
169#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0FE00000
170#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21
171
172#define AR_PHY_SFCORR 0x9868
173#define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F
174#define AR_PHY_SFCORR_M2COUNT_THR_S 0
175#define AR_PHY_SFCORR_M1_THRESH 0x00FE0000
176#define AR_PHY_SFCORR_M1_THRESH_S 17
177#define AR_PHY_SFCORR_M2_THRESH 0x7F000000
178#define AR_PHY_SFCORR_M2_THRESH_S 24
179
180#define AR_PHY_SLEEP_CTR_CONTROL 0x9870
181#define AR_PHY_SLEEP_CTR_LIMIT 0x9874
182#define AR_PHY_SYNTH_CONTROL 0x9874
183#define AR_PHY_SLEEP_SCAL 0x9878
184
185#define AR_PHY_PLL_CTL 0x987c
186#define AR_PHY_PLL_CTL_40 0xaa
187#define AR_PHY_PLL_CTL_40_5413 0x04
188#define AR_PHY_PLL_CTL_44 0xab
189#define AR_PHY_PLL_CTL_44_2133 0xeb
190#define AR_PHY_PLL_CTL_40_2133 0xea
191
192#define AR_PHY_SPECTRAL_SCAN 0x9910 /* AR9280 spectral scan configuration register */
193#define AR_PHY_SPECTRAL_SCAN_ENABLE 0x1
194#define AR_PHY_SPECTRAL_SCAN_ENA 0x00000001 /* Enable spectral scan, reg 68, bit 0 */
195#define AR_PHY_SPECTRAL_SCAN_ENA_S 0 /* Enable spectral scan, reg 68, bit 0 */
196#define AR_PHY_SPECTRAL_SCAN_ACTIVE 0x00000002 /* Activate spectral scan reg 68, bit 1*/
197#define AR_PHY_SPECTRAL_SCAN_ACTIVE_S 1 /* Activate spectral scan reg 68, bit 1*/
198#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD 0x000000F0 /* Interval for FFT reports, reg 68, bits 4-7*/
199#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S 4
200#define AR_PHY_SPECTRAL_SCAN_PERIOD 0x0000FF00 /* Interval for FFT reports, reg 68, bits 8-15*/
201#define AR_PHY_SPECTRAL_SCAN_PERIOD_S 8
202#define AR_PHY_SPECTRAL_SCAN_COUNT 0x00FF0000 /* Number of reports, reg 68, bits 16-23*/
203#define AR_PHY_SPECTRAL_SCAN_COUNT_S 16
204#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x01000000 /* Short repeat, reg 68, bit 24*/
205#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 24 /* Short repeat, reg 68, bit 24*/
206
207#define AR_PHY_RX_DELAY 0x9914
208#define AR_PHY_SEARCH_START_DELAY 0x9918
209#define AR_PHY_RX_DELAY_DELAY 0x00003FFF
210
211#define AR_PHY_TIMING_CTRL4(_i) (0x9920 + ((_i) << 12))
212#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF 0x01F
213#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S 0
214#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF 0x7E0
215#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S 5
216#define AR_PHY_TIMING_CTRL4_IQCORR_ENABLE 0x800
217#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX 0xF000
218#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S 12
219#define AR_PHY_TIMING_CTRL4_DO_CAL 0x10000
220
221#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI 0x80000000
222#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER 0x40000000
223#define AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK 0x20000000
224#define AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK 0x10000000
225
226#define AR_PHY_TIMING5 0x9924
227#define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE
228#define AR_PHY_TIMING5_CYCPWR_THR1_S 1
229
230#define AR_PHY_POWER_TX_RATE1 0x9934
231#define AR_PHY_POWER_TX_RATE2 0x9938
232#define AR_PHY_POWER_TX_RATE_MAX 0x993c
233#define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040
234
235#define AR_PHY_FRAME_CTL 0x9944
236#define AR_PHY_FRAME_CTL_TX_CLIP 0x00000038
237#define AR_PHY_FRAME_CTL_TX_CLIP_S 3
238
239#define AR_PHY_TXPWRADJ 0x994C
240#define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA 0x00000FC0
241#define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA_S 6
242#define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX 0x00FC0000
243#define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX_S 18
244
245#define AR_PHY_RADAR_EXT 0x9940
246#define AR_PHY_RADAR_EXT_ENA 0x00004000
247
248#define AR_PHY_RADAR_0 0x9954
249#define AR_PHY_RADAR_0_ENA 0x00000001
250#define AR_PHY_RADAR_0_FFT_ENA 0x80000000
251#define AR_PHY_RADAR_0_INBAND 0x0000003e
252#define AR_PHY_RADAR_0_INBAND_S 1
253#define AR_PHY_RADAR_0_PRSSI 0x00000FC0
254#define AR_PHY_RADAR_0_PRSSI_S 6
255#define AR_PHY_RADAR_0_HEIGHT 0x0003F000
256#define AR_PHY_RADAR_0_HEIGHT_S 12
257#define AR_PHY_RADAR_0_RRSSI 0x00FC0000
258#define AR_PHY_RADAR_0_RRSSI_S 18
259#define AR_PHY_RADAR_0_FIRPWR 0x7F000000
260#define AR_PHY_RADAR_0_FIRPWR_S 24
261
262#define AR_PHY_RADAR_1 0x9958
263#define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000
264#define AR_PHY_RADAR_1_USE_FIR128 0x00400000
265#define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000
266#define AR_PHY_RADAR_1_RELPWR_THRESH_S 16
267#define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000
268#define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000
269#define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000
270#define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00
271#define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8
272#define AR_PHY_RADAR_1_MAXLEN 0x000000FF
273#define AR_PHY_RADAR_1_MAXLEN_S 0
274
275#define AR_PHY_SWITCH_CHAIN_0 0x9960
276#define AR_PHY_SWITCH_COM 0x9964
277
278#define AR_PHY_SIGMA_DELTA 0x996C
279#define AR_PHY_SIGMA_DELTA_ADC_SEL 0x00000003
280#define AR_PHY_SIGMA_DELTA_ADC_SEL_S 0
281#define AR_PHY_SIGMA_DELTA_FILT2 0x000000F8
282#define AR_PHY_SIGMA_DELTA_FILT2_S 3
283#define AR_PHY_SIGMA_DELTA_FILT1 0x00001F00
284#define AR_PHY_SIGMA_DELTA_FILT1_S 8
285#define AR_PHY_SIGMA_DELTA_ADC_CLIP 0x01FFE000
286#define AR_PHY_SIGMA_DELTA_ADC_CLIP_S 13
287
288#define AR_PHY_RESTART 0x9970
289#define AR_PHY_RESTART_DIV_GC 0x001C0000
290#define AR_PHY_RESTART_DIV_GC_S 18
291
292#define AR_PHY_RFBUS_REQ 0x997C
293#define AR_PHY_RFBUS_REQ_EN 0x00000001
294
295#define AR_PHY_TIMING7 0x9980
296#define AR_PHY_TIMING8 0x9984
297#define AR_PHY_TIMING8_PILOT_MASK_2 0x000FFFFF
298#define AR_PHY_TIMING8_PILOT_MASK_2_S 0
299
300#define AR_PHY_BIN_MASK2_1 0x9988
301#define AR_PHY_BIN_MASK2_2 0x998c
302#define AR_PHY_BIN_MASK2_3 0x9990
303#define AR_PHY_BIN_MASK2_4 0x9994
304
305#define AR_PHY_BIN_MASK_1 0x9900
306#define AR_PHY_BIN_MASK_2 0x9904
307#define AR_PHY_BIN_MASK_3 0x9908
308
309#define AR_PHY_MASK_CTL 0x990c
310
311#define AR_PHY_BIN_MASK2_4_MASK_4 0x00003FFF
312#define AR_PHY_BIN_MASK2_4_MASK_4_S 0
313
314#define AR_PHY_TIMING9 0x9998
315#define AR_PHY_TIMING10 0x999c
316#define AR_PHY_TIMING10_PILOT_MASK_2 0x000FFFFF
317#define AR_PHY_TIMING10_PILOT_MASK_2_S 0
318
319#define AR_PHY_TIMING11 0x99a0
320#define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF
321#define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
322#define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000
323#define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20
324#define AR_PHY_TIMING11_USE_SPUR_IN_AGC 0x40000000
325#define AR_PHY_TIMING11_USE_SPUR_IN_SELFCOR 0x80000000
326
327#define AR_PHY_RX_CHAINMASK 0x99a4
328#define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (0x99b4 + ((_i) << 12))
329#define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000
330#define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000
331
332#define AR_PHY_MULTICHAIN_GAIN_CTL 0x99ac
333#define AR_PHY_9285_ANT_DIV_CTL_ALL 0x7f000000
334#define AR_PHY_9285_ANT_DIV_CTL 0x01000000
335#define AR_PHY_9285_ANT_DIV_CTL_S 24
336#define AR_PHY_9285_ANT_DIV_ALT_LNACONF 0x06000000
337#define AR_PHY_9285_ANT_DIV_ALT_LNACONF_S 25
338#define AR_PHY_9285_ANT_DIV_MAIN_LNACONF 0x18000000
339#define AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S 27
340#define AR_PHY_9285_ANT_DIV_ALT_GAINTB 0x20000000
341#define AR_PHY_9285_ANT_DIV_ALT_GAINTB_S 29
342#define AR_PHY_9285_ANT_DIV_MAIN_GAINTB 0x40000000
343#define AR_PHY_9285_ANT_DIV_MAIN_GAINTB_S 30
344#define AR_PHY_9285_ANT_DIV_LNA1 2
345#define AR_PHY_9285_ANT_DIV_LNA2 1
346#define AR_PHY_9285_ANT_DIV_LNA1_PLUS_LNA2 3
347#define AR_PHY_9285_ANT_DIV_LNA1_MINUS_LNA2 0
348#define AR_PHY_9285_ANT_DIV_GAINTB_0 0
349#define AR_PHY_9285_ANT_DIV_GAINTB_1 1
350
351#define AR_PHY_EXT_CCA0 0x99b8
352#define AR_PHY_EXT_CCA0_THRESH62 0x000000FF
353#define AR_PHY_EXT_CCA0_THRESH62_S 0
354
355#define AR_PHY_EXT_CCA 0x99bc
356#define AR_PHY_EXT_CCA_CYCPWR_THR1 0x0000FE00
357#define AR_PHY_EXT_CCA_CYCPWR_THR1_S 9
358#define AR_PHY_EXT_CCA_THRESH62 0x007F0000
359#define AR_PHY_EXT_CCA_THRESH62_S 16
360#define AR_PHY_EXT_MINCCA_PWR 0xFF800000
361#define AR_PHY_EXT_MINCCA_PWR_S 23
362#define AR9280_PHY_EXT_MINCCA_PWR 0x01FF0000
363#define AR9280_PHY_EXT_MINCCA_PWR_S 16
364
365#define AR_PHY_SFCORR_EXT 0x99c0
366#define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F
367#define AR_PHY_SFCORR_EXT_M1_THRESH_S 0
368#define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80
369#define AR_PHY_SFCORR_EXT_M2_THRESH_S 7
370#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000
371#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14
372#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000
373#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21
374#define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28
375
376#define AR_PHY_HALFGI 0x99D0
377#define AR_PHY_HALFGI_DSC_MAN 0x0007FFF0
378#define AR_PHY_HALFGI_DSC_MAN_S 4
379#define AR_PHY_HALFGI_DSC_EXP 0x0000000F
380#define AR_PHY_HALFGI_DSC_EXP_S 0
381
382#define AR_PHY_CHAN_INFO_MEMORY 0x99DC
383#define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001
384
385#define AR_PHY_HEAVY_CLIP_ENABLE 0x99E0
386
387#define AR_PHY_HEAVY_CLIP_FACTOR_RIFS 0x99EC
388#define AR_PHY_RIFS_INIT_DELAY 0x03ff0000
389
390#define AR_PHY_M_SLEEP 0x99f0
391#define AR_PHY_REFCLKDLY 0x99f4
392#define AR_PHY_REFCLKPD 0x99f8
393
394#define AR_PHY_CALMODE 0x99f0
395
396#define AR_PHY_CALMODE_IQ 0x00000000
397#define AR_PHY_CALMODE_ADC_GAIN 0x00000001
398#define AR_PHY_CALMODE_ADC_DC_PER 0x00000002
399#define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003
400
401#define AR_PHY_CAL_MEAS_0(_i) (0x9c10 + ((_i) << 12))
402#define AR_PHY_CAL_MEAS_1(_i) (0x9c14 + ((_i) << 12))
403#define AR_PHY_CAL_MEAS_2(_i) (0x9c18 + ((_i) << 12))
404#define AR_PHY_CAL_MEAS_3(_i) (0x9c1c + ((_i) << 12))
405
406#define AR_PHY_CURRENT_RSSI 0x9c1c
407#define AR9280_PHY_CURRENT_RSSI 0x9c3c
408
409#define AR_PHY_RFBUS_GRANT 0x9C20
410#define AR_PHY_RFBUS_GRANT_EN 0x00000001
411
412#define AR_PHY_CHAN_INFO_GAIN_DIFF 0x9CF4
413#define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320
414
415#define AR_PHY_CHAN_INFO_GAIN 0x9CFC
416
417#define AR_PHY_MODE 0xA200
418#define AR_PHY_MODE_ASYNCFIFO 0x80
419#define AR_PHY_MODE_AR2133 0x08
420#define AR_PHY_MODE_AR5111 0x00
421#define AR_PHY_MODE_AR5112 0x08
422#define AR_PHY_MODE_DYNAMIC 0x04
423#define AR_PHY_MODE_RF2GHZ 0x02
424#define AR_PHY_MODE_RF5GHZ 0x00
425#define AR_PHY_MODE_CCK 0x01
426#define AR_PHY_MODE_OFDM 0x00
427#define AR_PHY_MODE_DYN_CCK_DISABLE 0x100
428
429#define AR_PHY_CCK_TX_CTRL 0xA204
430#define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010
431#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK 0x0000000C
432#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_S 2
433
434#define AR_PHY_CCK_DETECT 0xA208
435#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F
436#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0
437/* [12:6] settling time for antenna switch */
438#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0
439#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6
440#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000
441#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV_S 13
442
443#define AR_PHY_GAIN_2GHZ 0xA20C
444#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN 0x00FC0000
445#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN_S 18
446#define AR_PHY_GAIN_2GHZ_BSW_MARGIN 0x00003C00
447#define AR_PHY_GAIN_2GHZ_BSW_MARGIN_S 10
448#define AR_PHY_GAIN_2GHZ_BSW_ATTEN 0x0000001F
449#define AR_PHY_GAIN_2GHZ_BSW_ATTEN_S 0
450
451#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN 0x003E0000
452#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S 17
453#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN 0x0001F000
454#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S 12
455#define AR_PHY_GAIN_2GHZ_XATTEN2_DB 0x00000FC0
456#define AR_PHY_GAIN_2GHZ_XATTEN2_DB_S 6
457#define AR_PHY_GAIN_2GHZ_XATTEN1_DB 0x0000003F
458#define AR_PHY_GAIN_2GHZ_XATTEN1_DB_S 0
459
460#define AR_PHY_CCK_RXCTRL4 0xA21C
461#define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT 0x01F80000
462#define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_S 19
463
464#define AR_PHY_DAG_CTRLCCK 0xA228
465#define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200
466#define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00
467#define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10
468
469#define AR_PHY_FORCE_CLKEN_CCK 0xA22C
470#define AR_PHY_FORCE_CLKEN_CCK_MRC_MUX 0x00000040
471
472#define AR_PHY_POWER_TX_RATE3 0xA234
473#define AR_PHY_POWER_TX_RATE4 0xA238
474
475#define AR_PHY_SCRM_SEQ_XR 0xA23C
476#define AR_PHY_HEADER_DETECT_XR 0xA240
477#define AR_PHY_CHIRP_DETECTED_XR 0xA244
478#define AR_PHY_BLUETOOTH 0xA254
479
480#define AR_PHY_TPCRG1 0xA258
481#define AR_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000
482#define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14
483
484#define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000
485#define AR_PHY_TPCRG1_PD_GAIN_1_S 16
486#define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000
487#define AR_PHY_TPCRG1_PD_GAIN_2_S 18
488#define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000
489#define AR_PHY_TPCRG1_PD_GAIN_3_S 20
490
491#define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000
492#define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22
493
494#define AR_PHY_TX_PWRCTRL4 0xa264
495#define AR_PHY_TX_PWRCTRL_PD_AVG_VALID 0x00000001
496#define AR_PHY_TX_PWRCTRL_PD_AVG_VALID_S 0
497#define AR_PHY_TX_PWRCTRL_PD_AVG_OUT 0x000001FE
498#define AR_PHY_TX_PWRCTRL_PD_AVG_OUT_S 1
499
500#define AR_PHY_TX_PWRCTRL6_0 0xa270
501#define AR_PHY_TX_PWRCTRL6_1 0xb270
502#define AR_PHY_TX_PWRCTRL_ERR_EST_MODE 0x03000000
503#define AR_PHY_TX_PWRCTRL_ERR_EST_MODE_S 24
504
505#define AR_PHY_TX_PWRCTRL7 0xa274
506#define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX 0x0007E000 27#define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX 0x0007E000
507#define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX_S 13 28#define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX_S 13
508#define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN 0x01F80000
509#define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN_S 19
510
511#define AR_PHY_TX_PWRCTRL9 0xa27C
512#define AR_PHY_TX_DESIRED_SCALE_CCK 0x00007C00
513#define AR_PHY_TX_DESIRED_SCALE_CCK_S 10
514#define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL 0x80000000
515#define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL_S 31
516
517#define AR_PHY_TX_GAIN_TBL1 0xa300
518#define AR_PHY_TX_GAIN_CLC 0x0000001E 29#define AR_PHY_TX_GAIN_CLC 0x0000001E
519#define AR_PHY_TX_GAIN_CLC_S 1 30#define AR_PHY_TX_GAIN_CLC_S 1
520#define AR_PHY_TX_GAIN 0x0007F000 31#define AR_PHY_TX_GAIN 0x0007F000
@@ -526,91 +37,6 @@ bool ath9k_hw_set_rf_regs(struct ath_hw *ah,
526#define AR_PHY_CLC_Q0 0x0000ffd0 37#define AR_PHY_CLC_Q0 0x0000ffd0
527#define AR_PHY_CLC_Q0_S 5 38#define AR_PHY_CLC_Q0_S 5
528 39
529#define AR_PHY_CH0_TX_PWRCTRL11 0xa398
530#define AR_PHY_CH1_TX_PWRCTRL11 0xb398
531#define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP 0x0000FC00
532#define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP_S 10
533
534#define AR_PHY_VIT_MASK2_M_46_61 0xa3a0
535#define AR_PHY_MASK2_M_31_45 0xa3a4
536#define AR_PHY_MASK2_M_16_30 0xa3a8
537#define AR_PHY_MASK2_M_00_15 0xa3ac
538#define AR_PHY_MASK2_P_15_01 0xa3b8
539#define AR_PHY_MASK2_P_30_16 0xa3bc
540#define AR_PHY_MASK2_P_45_31 0xa3c0
541#define AR_PHY_MASK2_P_61_45 0xa3c4
542#define AR_PHY_SPUR_REG 0x994c
543
544#define AR_PHY_SPUR_REG_MASK_RATE_CNTL (0xFF << 18)
545#define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18
546
547#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000
548#define AR_PHY_SPUR_REG_MASK_RATE_SELECT (0xFF << 9)
549#define AR_PHY_SPUR_REG_MASK_RATE_SELECT_S 9
550#define AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI 0x100
551#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x7F
552#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0
553
554#define AR_PHY_PILOT_MASK_01_30 0xa3b0
555#define AR_PHY_PILOT_MASK_31_60 0xa3b4
556
557#define AR_PHY_CHANNEL_MASK_01_30 0x99d4
558#define AR_PHY_CHANNEL_MASK_31_60 0x99d8
559
560#define AR_PHY_ANALOG_SWAP 0xa268
561#define AR_PHY_SWAP_ALT_CHAIN 0x00000040
562
563#define AR_PHY_TPCRG5 0xA26C
564#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000F
565#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0
566#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003F0
567#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4
568#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000FC00
569#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10
570#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003F0000
571#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16
572#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0FC00000
573#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22
574
575/* Carrier leak calibration control, do it after AGC calibration */
576#define AR_PHY_CL_CAL_CTL 0xA358
577#define AR_PHY_CL_CAL_ENABLE 0x00000002
578#define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001
579
580#define AR_PHY_POWER_TX_RATE5 0xA38C
581#define AR_PHY_POWER_TX_RATE6 0xA390
582
583#define AR_PHY_CAL_CHAINMASK 0xA39C
584
585#define AR_PHY_POWER_TX_SUB 0xA3C8
586#define AR_PHY_POWER_TX_RATE7 0xA3CC
587#define AR_PHY_POWER_TX_RATE8 0xA3D0
588#define AR_PHY_POWER_TX_RATE9 0xA3D4
589
590#define AR_PHY_XPA_CFG 0xA3D8
591#define AR_PHY_FORCE_XPA_CFG 0x000000001
592#define AR_PHY_FORCE_XPA_CFG_S 0
593
594#define AR_PHY_CH1_CCA 0xa864
595#define AR_PHY_CH1_MINCCA_PWR 0x0FF80000
596#define AR_PHY_CH1_MINCCA_PWR_S 19
597#define AR9280_PHY_CH1_MINCCA_PWR 0x1FF00000
598#define AR9280_PHY_CH1_MINCCA_PWR_S 20
599
600#define AR_PHY_CH2_CCA 0xb864
601#define AR_PHY_CH2_MINCCA_PWR 0x0FF80000
602#define AR_PHY_CH2_MINCCA_PWR_S 19
603
604#define AR_PHY_CH1_EXT_CCA 0xa9bc
605#define AR_PHY_CH1_EXT_MINCCA_PWR 0xFF800000
606#define AR_PHY_CH1_EXT_MINCCA_PWR_S 23
607#define AR9280_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000
608#define AR9280_PHY_CH1_EXT_MINCCA_PWR_S 16
609
610#define AR_PHY_CH2_EXT_CCA 0xb9bc
611#define AR_PHY_CH2_EXT_MINCCA_PWR 0xFF800000
612#define AR_PHY_CH2_EXT_MINCCA_PWR_S 23
613
614#define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) do { \ 40#define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) do { \
615 int r; \ 41 int r; \
616 for (r = 0; r < ((iniarray)->ia_rows); r++) { \ 42 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
@@ -625,6 +51,7 @@ bool ath9k_hw_set_rf_regs(struct ath_hw *ah,
625#define ANTSWAP_AB 0x0001 51#define ANTSWAP_AB 0x0001
626#define REDUCE_CHAIN_0 0x00000050 52#define REDUCE_CHAIN_0 0x00000050
627#define REDUCE_CHAIN_1 0x00000051 53#define REDUCE_CHAIN_1 0x00000051
54#define AR_PHY_CHIP_ID 0x9818
628 55
629#define RF_BANK_SETUP(_bank, _iniarray, _col) do { \ 56#define RF_BANK_SETUP(_bank, _iniarray, _col) do { \
630 int i; \ 57 int i; \
@@ -632,4 +59,7 @@ bool ath9k_hw_set_rf_regs(struct ath_hw *ah,
632 (_bank)[i] = INI_RA((_iniarray), i, _col);; \ 59 (_bank)[i] = INI_RA((_iniarray), i, _col);; \
633 } while (0) 60 } while (0)
634 61
62#define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000
63#define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20
64
635#endif 65#endif
diff --git a/drivers/net/wireless/ath/ath9k/rc.c b/drivers/net/wireless/ath/ath9k/rc.c
index ee81291f2fba..8519452c95f1 100644
--- a/drivers/net/wireless/ath/ath9k/rc.c
+++ b/drivers/net/wireless/ath/ath9k/rc.c
@@ -691,6 +691,19 @@ static void ath_get_rate(void *priv, struct ieee80211_sta *sta, void *priv_sta,
691 rate_table = sc->cur_rate_table; 691 rate_table = sc->cur_rate_table;
692 rix = ath_rc_get_highest_rix(sc, ath_rc_priv, rate_table, &is_probe); 692 rix = ath_rc_get_highest_rix(sc, ath_rc_priv, rate_table, &is_probe);
693 693
694 /*
695 * If we're in HT mode and both us and our peer supports LDPC.
696 * We don't need to check our own device's capabilities as our own
697 * ht capabilities would have already been intersected with our peer's.
698 */
699 if (conf_is_ht(&sc->hw->conf) &&
700 (sta->ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING))
701 tx_info->flags |= IEEE80211_TX_CTL_LDPC;
702
703 if (conf_is_ht(&sc->hw->conf) &&
704 (sta->ht_cap.cap & IEEE80211_HT_CAP_TX_STBC))
705 tx_info->flags |= (1 << IEEE80211_TX_CTL_STBC_SHIFT);
706
694 if (is_probe) { 707 if (is_probe) {
695 /* set one try for probe rates. For the 708 /* set one try for probe rates. For the
696 * probes don't enable rts */ 709 * probes don't enable rts */
diff --git a/drivers/net/wireless/ath/ath9k/recv.c b/drivers/net/wireless/ath/ath9k/recv.c
index 94560e2fe376..ac60c4ee62d3 100644
--- a/drivers/net/wireless/ath/ath9k/recv.c
+++ b/drivers/net/wireless/ath/ath9k/recv.c
@@ -15,6 +15,9 @@
15 */ 15 */
16 16
17#include "ath9k.h" 17#include "ath9k.h"
18#include "ar9003_mac.h"
19
20#define SKB_CB_ATHBUF(__skb) (*((struct ath_buf **)__skb->cb))
18 21
19static struct ieee80211_hw * ath_get_virt_hw(struct ath_softc *sc, 22static struct ieee80211_hw * ath_get_virt_hw(struct ath_softc *sc,
20 struct ieee80211_hdr *hdr) 23 struct ieee80211_hdr *hdr)
@@ -115,56 +118,246 @@ static void ath_opmode_init(struct ath_softc *sc)
115 ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]); 118 ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]);
116} 119}
117 120
118int ath_rx_init(struct ath_softc *sc, int nbufs) 121static bool ath_rx_edma_buf_link(struct ath_softc *sc,
122 enum ath9k_rx_qtype qtype)
119{ 123{
120 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 124 struct ath_hw *ah = sc->sc_ah;
125 struct ath_rx_edma *rx_edma;
121 struct sk_buff *skb; 126 struct sk_buff *skb;
122 struct ath_buf *bf; 127 struct ath_buf *bf;
123 int error = 0;
124 128
125 spin_lock_init(&sc->rx.rxflushlock); 129 rx_edma = &sc->rx.rx_edma[qtype];
126 sc->sc_flags &= ~SC_OP_RXFLUSH; 130 if (skb_queue_len(&rx_edma->rx_fifo) >= rx_edma->rx_fifo_hwsize)
127 spin_lock_init(&sc->rx.rxbuflock); 131 return false;
128 132
129 common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN, 133 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
130 min(common->cachelsz, (u16)64)); 134 list_del_init(&bf->list);
131 135
132 ath_print(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n", 136 skb = bf->bf_mpdu;
133 common->cachelsz, common->rx_bufsize); 137
138 ATH_RXBUF_RESET(bf);
139 memset(skb->data, 0, ah->caps.rx_status_len);
140 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
141 ah->caps.rx_status_len, DMA_TO_DEVICE);
134 142
135 /* Initialize rx descriptors */ 143 SKB_CB_ATHBUF(skb) = bf;
144 ath9k_hw_addrxbuf_edma(ah, bf->bf_buf_addr, qtype);
145 skb_queue_tail(&rx_edma->rx_fifo, skb);
136 146
137 error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf, 147 return true;
138 "rx", nbufs, 1); 148}
139 if (error != 0) { 149
140 ath_print(common, ATH_DBG_FATAL, 150static void ath_rx_addbuffer_edma(struct ath_softc *sc,
141 "failed to allocate rx descriptors: %d\n", error); 151 enum ath9k_rx_qtype qtype, int size)
142 goto err; 152{
153 struct ath_rx_edma *rx_edma;
154 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
155 u32 nbuf = 0;
156
157 rx_edma = &sc->rx.rx_edma[qtype];
158 if (list_empty(&sc->rx.rxbuf)) {
159 ath_print(common, ATH_DBG_QUEUE, "No free rx buf available\n");
160 return;
143 } 161 }
144 162
163 while (!list_empty(&sc->rx.rxbuf)) {
164 nbuf++;
165
166 if (!ath_rx_edma_buf_link(sc, qtype))
167 break;
168
169 if (nbuf >= size)
170 break;
171 }
172}
173
174static void ath_rx_remove_buffer(struct ath_softc *sc,
175 enum ath9k_rx_qtype qtype)
176{
177 struct ath_buf *bf;
178 struct ath_rx_edma *rx_edma;
179 struct sk_buff *skb;
180
181 rx_edma = &sc->rx.rx_edma[qtype];
182
183 while ((skb = skb_dequeue(&rx_edma->rx_fifo)) != NULL) {
184 bf = SKB_CB_ATHBUF(skb);
185 BUG_ON(!bf);
186 list_add_tail(&bf->list, &sc->rx.rxbuf);
187 }
188}
189
190static void ath_rx_edma_cleanup(struct ath_softc *sc)
191{
192 struct ath_buf *bf;
193
194 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
195 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
196
145 list_for_each_entry(bf, &sc->rx.rxbuf, list) { 197 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
198 if (bf->bf_mpdu)
199 dev_kfree_skb_any(bf->bf_mpdu);
200 }
201
202 INIT_LIST_HEAD(&sc->rx.rxbuf);
203
204 kfree(sc->rx.rx_bufptr);
205 sc->rx.rx_bufptr = NULL;
206}
207
208static void ath_rx_edma_init_queue(struct ath_rx_edma *rx_edma, int size)
209{
210 skb_queue_head_init(&rx_edma->rx_fifo);
211 skb_queue_head_init(&rx_edma->rx_buffers);
212 rx_edma->rx_fifo_hwsize = size;
213}
214
215static int ath_rx_edma_init(struct ath_softc *sc, int nbufs)
216{
217 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
218 struct ath_hw *ah = sc->sc_ah;
219 struct sk_buff *skb;
220 struct ath_buf *bf;
221 int error = 0, i;
222 u32 size;
223
224
225 common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN +
226 ah->caps.rx_status_len,
227 min(common->cachelsz, (u16)64));
228
229 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
230 ah->caps.rx_status_len);
231
232 ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_LP],
233 ah->caps.rx_lp_qdepth);
234 ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_HP],
235 ah->caps.rx_hp_qdepth);
236
237 size = sizeof(struct ath_buf) * nbufs;
238 bf = kzalloc(size, GFP_KERNEL);
239 if (!bf)
240 return -ENOMEM;
241
242 INIT_LIST_HEAD(&sc->rx.rxbuf);
243 sc->rx.rx_bufptr = bf;
244
245 for (i = 0; i < nbufs; i++, bf++) {
146 skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_KERNEL); 246 skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_KERNEL);
147 if (skb == NULL) { 247 if (!skb) {
148 error = -ENOMEM; 248 error = -ENOMEM;
149 goto err; 249 goto rx_init_fail;
150 } 250 }
151 251
252 memset(skb->data, 0, common->rx_bufsize);
152 bf->bf_mpdu = skb; 253 bf->bf_mpdu = skb;
254
153 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, 255 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
154 common->rx_bufsize, 256 common->rx_bufsize,
155 DMA_FROM_DEVICE); 257 DMA_BIDIRECTIONAL);
156 if (unlikely(dma_mapping_error(sc->dev, 258 if (unlikely(dma_mapping_error(sc->dev,
157 bf->bf_buf_addr))) { 259 bf->bf_buf_addr))) {
158 dev_kfree_skb_any(skb); 260 dev_kfree_skb_any(skb);
159 bf->bf_mpdu = NULL; 261 bf->bf_mpdu = NULL;
262 ath_print(common, ATH_DBG_FATAL,
263 "dma_mapping_error() on RX init\n");
264 error = -ENOMEM;
265 goto rx_init_fail;
266 }
267
268 list_add_tail(&bf->list, &sc->rx.rxbuf);
269 }
270
271 return 0;
272
273rx_init_fail:
274 ath_rx_edma_cleanup(sc);
275 return error;
276}
277
278static void ath_edma_start_recv(struct ath_softc *sc)
279{
280 spin_lock_bh(&sc->rx.rxbuflock);
281
282 ath9k_hw_rxena(sc->sc_ah);
283
284 ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_HP,
285 sc->rx.rx_edma[ATH9K_RX_QUEUE_HP].rx_fifo_hwsize);
286
287 ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_LP,
288 sc->rx.rx_edma[ATH9K_RX_QUEUE_LP].rx_fifo_hwsize);
289
290 spin_unlock_bh(&sc->rx.rxbuflock);
291
292 ath_opmode_init(sc);
293
294 ath9k_hw_startpcureceive(sc->sc_ah);
295}
296
297static void ath_edma_stop_recv(struct ath_softc *sc)
298{
299 spin_lock_bh(&sc->rx.rxbuflock);
300 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
301 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
302 spin_unlock_bh(&sc->rx.rxbuflock);
303}
304
305int ath_rx_init(struct ath_softc *sc, int nbufs)
306{
307 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
308 struct sk_buff *skb;
309 struct ath_buf *bf;
310 int error = 0;
311
312 spin_lock_init(&sc->rx.rxflushlock);
313 sc->sc_flags &= ~SC_OP_RXFLUSH;
314 spin_lock_init(&sc->rx.rxbuflock);
315
316 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
317 return ath_rx_edma_init(sc, nbufs);
318 } else {
319 common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN,
320 min(common->cachelsz, (u16)64));
321
322 ath_print(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n",
323 common->cachelsz, common->rx_bufsize);
324
325 /* Initialize rx descriptors */
326
327 error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
328 "rx", nbufs, 1, 0);
329 if (error != 0) {
160 ath_print(common, ATH_DBG_FATAL, 330 ath_print(common, ATH_DBG_FATAL,
161 "dma_mapping_error() on RX init\n"); 331 "failed to allocate rx descriptors: %d\n",
162 error = -ENOMEM; 332 error);
163 goto err; 333 goto err;
164 } 334 }
165 bf->bf_dmacontext = bf->bf_buf_addr; 335
336 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
337 skb = ath_rxbuf_alloc(common, common->rx_bufsize,
338 GFP_KERNEL);
339 if (skb == NULL) {
340 error = -ENOMEM;
341 goto err;
342 }
343
344 bf->bf_mpdu = skb;
345 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
346 common->rx_bufsize,
347 DMA_FROM_DEVICE);
348 if (unlikely(dma_mapping_error(sc->dev,
349 bf->bf_buf_addr))) {
350 dev_kfree_skb_any(skb);
351 bf->bf_mpdu = NULL;
352 ath_print(common, ATH_DBG_FATAL,
353 "dma_mapping_error() on RX init\n");
354 error = -ENOMEM;
355 goto err;
356 }
357 bf->bf_dmacontext = bf->bf_buf_addr;
358 }
359 sc->rx.rxlink = NULL;
166 } 360 }
167 sc->rx.rxlink = NULL;
168 361
169err: 362err:
170 if (error) 363 if (error)
@@ -180,17 +373,23 @@ void ath_rx_cleanup(struct ath_softc *sc)
180 struct sk_buff *skb; 373 struct sk_buff *skb;
181 struct ath_buf *bf; 374 struct ath_buf *bf;
182 375
183 list_for_each_entry(bf, &sc->rx.rxbuf, list) { 376 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
184 skb = bf->bf_mpdu; 377 ath_rx_edma_cleanup(sc);
185 if (skb) { 378 return;
186 dma_unmap_single(sc->dev, bf->bf_buf_addr, 379 } else {
187 common->rx_bufsize, DMA_FROM_DEVICE); 380 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
188 dev_kfree_skb(skb); 381 skb = bf->bf_mpdu;
382 if (skb) {
383 dma_unmap_single(sc->dev, bf->bf_buf_addr,
384 common->rx_bufsize,
385 DMA_FROM_DEVICE);
386 dev_kfree_skb(skb);
387 }
189 } 388 }
190 }
191 389
192 if (sc->rx.rxdma.dd_desc_len != 0) 390 if (sc->rx.rxdma.dd_desc_len != 0)
193 ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf); 391 ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf);
392 }
194} 393}
195 394
196/* 395/*
@@ -273,6 +472,11 @@ int ath_startrecv(struct ath_softc *sc)
273 struct ath_hw *ah = sc->sc_ah; 472 struct ath_hw *ah = sc->sc_ah;
274 struct ath_buf *bf, *tbf; 473 struct ath_buf *bf, *tbf;
275 474
475 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
476 ath_edma_start_recv(sc);
477 return 0;
478 }
479
276 spin_lock_bh(&sc->rx.rxbuflock); 480 spin_lock_bh(&sc->rx.rxbuflock);
277 if (list_empty(&sc->rx.rxbuf)) 481 if (list_empty(&sc->rx.rxbuf))
278 goto start_recv; 482 goto start_recv;
@@ -306,7 +510,11 @@ bool ath_stoprecv(struct ath_softc *sc)
306 ath9k_hw_stoppcurecv(ah); 510 ath9k_hw_stoppcurecv(ah);
307 ath9k_hw_setrxfilter(ah, 0); 511 ath9k_hw_setrxfilter(ah, 0);
308 stopped = ath9k_hw_stopdmarecv(ah); 512 stopped = ath9k_hw_stopdmarecv(ah);
309 sc->rx.rxlink = NULL; 513
514 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
515 ath_edma_stop_recv(sc);
516 else
517 sc->rx.rxlink = NULL;
310 518
311 return stopped; 519 return stopped;
312} 520}
@@ -315,7 +523,9 @@ void ath_flushrecv(struct ath_softc *sc)
315{ 523{
316 spin_lock_bh(&sc->rx.rxflushlock); 524 spin_lock_bh(&sc->rx.rxflushlock);
317 sc->sc_flags |= SC_OP_RXFLUSH; 525 sc->sc_flags |= SC_OP_RXFLUSH;
318 ath_rx_tasklet(sc, 1); 526 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
527 ath_rx_tasklet(sc, 1, true);
528 ath_rx_tasklet(sc, 1, false);
319 sc->sc_flags &= ~SC_OP_RXFLUSH; 529 sc->sc_flags &= ~SC_OP_RXFLUSH;
320 spin_unlock_bh(&sc->rx.rxflushlock); 530 spin_unlock_bh(&sc->rx.rxflushlock);
321} 531}
@@ -469,14 +679,147 @@ static void ath_rx_send_to_mac80211(struct ieee80211_hw *hw,
469 ieee80211_rx(hw, skb); 679 ieee80211_rx(hw, skb);
470} 680}
471 681
472int ath_rx_tasklet(struct ath_softc *sc, int flush) 682static bool ath_edma_get_buffers(struct ath_softc *sc,
683 enum ath9k_rx_qtype qtype)
473{ 684{
474#define PA2DESC(_sc, _pa) \ 685 struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
475 ((struct ath_desc *)((caddr_t)(_sc)->rx.rxdma.dd_desc + \ 686 struct ath_hw *ah = sc->sc_ah;
476 ((_pa) - (_sc)->rx.rxdma.dd_desc_paddr))) 687 struct ath_common *common = ath9k_hw_common(ah);
688 struct sk_buff *skb;
689 struct ath_buf *bf;
690 int ret;
691
692 skb = skb_peek(&rx_edma->rx_fifo);
693 if (!skb)
694 return false;
695
696 bf = SKB_CB_ATHBUF(skb);
697 BUG_ON(!bf);
698
699 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
700 common->rx_bufsize, DMA_FROM_DEVICE);
701
702 ret = ath9k_hw_process_rxdesc_edma(ah, NULL, skb->data);
703 if (ret == -EINPROGRESS)
704 return false;
705
706 __skb_unlink(skb, &rx_edma->rx_fifo);
707 if (ret == -EINVAL) {
708 /* corrupt descriptor, skip this one and the following one */
709 list_add_tail(&bf->list, &sc->rx.rxbuf);
710 ath_rx_edma_buf_link(sc, qtype);
711 skb = skb_peek(&rx_edma->rx_fifo);
712 if (!skb)
713 return true;
714
715 bf = SKB_CB_ATHBUF(skb);
716 BUG_ON(!bf);
717
718 __skb_unlink(skb, &rx_edma->rx_fifo);
719 list_add_tail(&bf->list, &sc->rx.rxbuf);
720 ath_rx_edma_buf_link(sc, qtype);
721 }
722 skb_queue_tail(&rx_edma->rx_buffers, skb);
723
724 return true;
725}
477 726
727static struct ath_buf *ath_edma_get_next_rx_buf(struct ath_softc *sc,
728 struct ath_rx_status *rs,
729 enum ath9k_rx_qtype qtype)
730{
731 struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
732 struct sk_buff *skb;
478 struct ath_buf *bf; 733 struct ath_buf *bf;
734
735 while (ath_edma_get_buffers(sc, qtype));
736 skb = __skb_dequeue(&rx_edma->rx_buffers);
737 if (!skb)
738 return NULL;
739
740 bf = SKB_CB_ATHBUF(skb);
741 ath9k_hw_process_rxdesc_edma(sc->sc_ah, rs, skb->data);
742 return bf;
743}
744
745static struct ath_buf *ath_get_next_rx_buf(struct ath_softc *sc,
746 struct ath_rx_status *rs)
747{
748 struct ath_hw *ah = sc->sc_ah;
749 struct ath_common *common = ath9k_hw_common(ah);
479 struct ath_desc *ds; 750 struct ath_desc *ds;
751 struct ath_buf *bf;
752 int ret;
753
754 if (list_empty(&sc->rx.rxbuf)) {
755 sc->rx.rxlink = NULL;
756 return NULL;
757 }
758
759 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
760 ds = bf->bf_desc;
761
762 /*
763 * Must provide the virtual address of the current
764 * descriptor, the physical address, and the virtual
765 * address of the next descriptor in the h/w chain.
766 * This allows the HAL to look ahead to see if the
767 * hardware is done with a descriptor by checking the
768 * done bit in the following descriptor and the address
769 * of the current descriptor the DMA engine is working
770 * on. All this is necessary because of our use of
771 * a self-linked list to avoid rx overruns.
772 */
773 ret = ath9k_hw_rxprocdesc(ah, ds, rs, 0);
774 if (ret == -EINPROGRESS) {
775 struct ath_rx_status trs;
776 struct ath_buf *tbf;
777 struct ath_desc *tds;
778
779 memset(&trs, 0, sizeof(trs));
780 if (list_is_last(&bf->list, &sc->rx.rxbuf)) {
781 sc->rx.rxlink = NULL;
782 return NULL;
783 }
784
785 tbf = list_entry(bf->list.next, struct ath_buf, list);
786
787 /*
788 * On some hardware the descriptor status words could
789 * get corrupted, including the done bit. Because of
790 * this, check if the next descriptor's done bit is
791 * set or not.
792 *
793 * If the next descriptor's done bit is set, the current
794 * descriptor has been corrupted. Force s/w to discard
795 * this descriptor and continue...
796 */
797
798 tds = tbf->bf_desc;
799 ret = ath9k_hw_rxprocdesc(ah, tds, &trs, 0);
800 if (ret == -EINPROGRESS)
801 return NULL;
802 }
803
804 if (!bf->bf_mpdu)
805 return bf;
806
807 /*
808 * Synchronize the DMA transfer with CPU before
809 * 1. accessing the frame
810 * 2. requeueing the same buffer to h/w
811 */
812 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
813 common->rx_bufsize,
814 DMA_FROM_DEVICE);
815
816 return bf;
817}
818
819
820int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
821{
822 struct ath_buf *bf;
480 struct sk_buff *skb = NULL, *requeue_skb; 823 struct sk_buff *skb = NULL, *requeue_skb;
481 struct ieee80211_rx_status *rxs; 824 struct ieee80211_rx_status *rxs;
482 struct ath_hw *ah = sc->sc_ah; 825 struct ath_hw *ah = sc->sc_ah;
@@ -491,7 +834,16 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
491 int retval; 834 int retval;
492 bool decrypt_error = false; 835 bool decrypt_error = false;
493 struct ath_rx_status rs; 836 struct ath_rx_status rs;
837 enum ath9k_rx_qtype qtype;
838 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
839 int dma_type;
494 840
841 if (edma)
842 dma_type = DMA_FROM_DEVICE;
843 else
844 dma_type = DMA_BIDIRECTIONAL;
845
846 qtype = hp ? ATH9K_RX_QUEUE_HP : ATH9K_RX_QUEUE_LP;
495 spin_lock_bh(&sc->rx.rxbuflock); 847 spin_lock_bh(&sc->rx.rxbuflock);
496 848
497 do { 849 do {
@@ -499,71 +851,19 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
499 if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0)) 851 if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0))
500 break; 852 break;
501 853
502 if (list_empty(&sc->rx.rxbuf)) {
503 sc->rx.rxlink = NULL;
504 break;
505 }
506
507 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
508 ds = bf->bf_desc;
509
510 /*
511 * Must provide the virtual address of the current
512 * descriptor, the physical address, and the virtual
513 * address of the next descriptor in the h/w chain.
514 * This allows the HAL to look ahead to see if the
515 * hardware is done with a descriptor by checking the
516 * done bit in the following descriptor and the address
517 * of the current descriptor the DMA engine is working
518 * on. All this is necessary because of our use of
519 * a self-linked list to avoid rx overruns.
520 */
521 memset(&rs, 0, sizeof(rs)); 854 memset(&rs, 0, sizeof(rs));
522 retval = ath9k_hw_rxprocdesc(ah, ds, &rs, 0); 855 if (edma)
523 if (retval == -EINPROGRESS) { 856 bf = ath_edma_get_next_rx_buf(sc, &rs, qtype);
524 struct ath_rx_status trs; 857 else
525 struct ath_buf *tbf; 858 bf = ath_get_next_rx_buf(sc, &rs);
526 struct ath_desc *tds;
527
528 memset(&trs, 0, sizeof(trs));
529 if (list_is_last(&bf->list, &sc->rx.rxbuf)) {
530 sc->rx.rxlink = NULL;
531 break;
532 }
533 859
534 tbf = list_entry(bf->list.next, struct ath_buf, list); 860 if (!bf)
535 861 break;
536 /*
537 * On some hardware the descriptor status words could
538 * get corrupted, including the done bit. Because of
539 * this, check if the next descriptor's done bit is
540 * set or not.
541 *
542 * If the next descriptor's done bit is set, the current
543 * descriptor has been corrupted. Force s/w to discard
544 * this descriptor and continue...
545 */
546
547 tds = tbf->bf_desc;
548 retval = ath9k_hw_rxprocdesc(ah, tds, &trs, 0);
549 if (retval == -EINPROGRESS) {
550 break;
551 }
552 }
553 862
554 skb = bf->bf_mpdu; 863 skb = bf->bf_mpdu;
555 if (!skb) 864 if (!skb)
556 continue; 865 continue;
557 866
558 /*
559 * Synchronize the DMA transfer with CPU before
560 * 1. accessing the frame
561 * 2. requeueing the same buffer to h/w
562 */
563 dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
564 common->rx_bufsize,
565 DMA_FROM_DEVICE);
566
567 hdr = (struct ieee80211_hdr *) skb->data; 867 hdr = (struct ieee80211_hdr *) skb->data;
568 rxs = IEEE80211_SKB_RXCB(skb); 868 rxs = IEEE80211_SKB_RXCB(skb);
569 869
@@ -597,9 +897,11 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
597 /* Unmap the frame */ 897 /* Unmap the frame */
598 dma_unmap_single(sc->dev, bf->bf_buf_addr, 898 dma_unmap_single(sc->dev, bf->bf_buf_addr,
599 common->rx_bufsize, 899 common->rx_bufsize,
600 DMA_FROM_DEVICE); 900 dma_type);
601 901
602 skb_put(skb, rs.rs_datalen); 902 skb_put(skb, rs.rs_datalen + ah->caps.rx_status_len);
903 if (ah->caps.rx_status_len)
904 skb_pull(skb, ah->caps.rx_status_len);
603 905
604 ath9k_cmn_rx_skb_postprocess(common, skb, &rs, 906 ath9k_cmn_rx_skb_postprocess(common, skb, &rs,
605 rxs, decrypt_error); 907 rxs, decrypt_error);
@@ -608,7 +910,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
608 bf->bf_mpdu = requeue_skb; 910 bf->bf_mpdu = requeue_skb;
609 bf->bf_buf_addr = dma_map_single(sc->dev, requeue_skb->data, 911 bf->bf_buf_addr = dma_map_single(sc->dev, requeue_skb->data,
610 common->rx_bufsize, 912 common->rx_bufsize,
611 DMA_FROM_DEVICE); 913 dma_type);
612 if (unlikely(dma_mapping_error(sc->dev, 914 if (unlikely(dma_mapping_error(sc->dev,
613 bf->bf_buf_addr))) { 915 bf->bf_buf_addr))) {
614 dev_kfree_skb_any(requeue_skb); 916 dev_kfree_skb_any(requeue_skb);
@@ -639,12 +941,16 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
639 ath_rx_send_to_mac80211(hw, sc, skb, rxs); 941 ath_rx_send_to_mac80211(hw, sc, skb, rxs);
640 942
641requeue: 943requeue:
642 list_move_tail(&bf->list, &sc->rx.rxbuf); 944 if (edma) {
643 ath_rx_buf_link(sc, bf); 945 list_add_tail(&bf->list, &sc->rx.rxbuf);
946 ath_rx_edma_buf_link(sc, qtype);
947 } else {
948 list_move_tail(&bf->list, &sc->rx.rxbuf);
949 ath_rx_buf_link(sc, bf);
950 }
644 } while (1); 951 } while (1);
645 952
646 spin_unlock_bh(&sc->rx.rxbuflock); 953 spin_unlock_bh(&sc->rx.rxbuflock);
647 954
648 return 0; 955 return 0;
649#undef PA2DESC
650} 956}
diff --git a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h
index 7e36ad7421b7..d4371a43bdaa 100644
--- a/drivers/net/wireless/ath/ath9k/reg.h
+++ b/drivers/net/wireless/ath/ath9k/reg.h
@@ -20,7 +20,7 @@
20#include "../reg.h" 20#include "../reg.h"
21 21
22#define AR_CR 0x0008 22#define AR_CR 0x0008
23#define AR_CR_RXE 0x00000004 23#define AR_CR_RXE (AR_SREV_9300_20_OR_LATER(ah) ? 0x0000000c : 0x00000004)
24#define AR_CR_RXD 0x00000020 24#define AR_CR_RXD 0x00000020
25#define AR_CR_SWI 0x00000040 25#define AR_CR_SWI 0x00000040
26 26
@@ -39,6 +39,12 @@
39#define AR_CFG_PCI_MASTER_REQ_Q_THRESH 0x00060000 39#define AR_CFG_PCI_MASTER_REQ_Q_THRESH 0x00060000
40#define AR_CFG_PCI_MASTER_REQ_Q_THRESH_S 17 40#define AR_CFG_PCI_MASTER_REQ_Q_THRESH_S 17
41 41
42#define AR_RXBP_THRESH 0x0018
43#define AR_RXBP_THRESH_HP 0x0000000f
44#define AR_RXBP_THRESH_HP_S 0
45#define AR_RXBP_THRESH_LP 0x00003f00
46#define AR_RXBP_THRESH_LP_S 8
47
42#define AR_MIRT 0x0020 48#define AR_MIRT 0x0020
43#define AR_MIRT_VAL 0x0000ffff 49#define AR_MIRT_VAL 0x0000ffff
44#define AR_MIRT_VAL_S 16 50#define AR_MIRT_VAL_S 16
@@ -144,6 +150,9 @@
144#define AR_MACMISC_MISC_OBS_BUS_MSB_S 15 150#define AR_MACMISC_MISC_OBS_BUS_MSB_S 15
145#define AR_MACMISC_MISC_OBS_BUS_1 1 151#define AR_MACMISC_MISC_OBS_BUS_1 1
146 152
153#define AR_DATABUF_SIZE 0x0060
154#define AR_DATABUF_SIZE_MASK 0x00000FFF
155
147#define AR_GTXTO 0x0064 156#define AR_GTXTO 0x0064
148#define AR_GTXTO_TIMEOUT_COUNTER 0x0000FFFF 157#define AR_GTXTO_TIMEOUT_COUNTER 0x0000FFFF
149#define AR_GTXTO_TIMEOUT_LIMIT 0xFFFF0000 158#define AR_GTXTO_TIMEOUT_LIMIT 0xFFFF0000
@@ -160,9 +169,14 @@
160#define AR_CST_TIMEOUT_LIMIT 0xFFFF0000 169#define AR_CST_TIMEOUT_LIMIT 0xFFFF0000
161#define AR_CST_TIMEOUT_LIMIT_S 16 170#define AR_CST_TIMEOUT_LIMIT_S 16
162 171
172#define AR_HP_RXDP 0x0074
173#define AR_LP_RXDP 0x0078
174
163#define AR_ISR 0x0080 175#define AR_ISR 0x0080
164#define AR_ISR_RXOK 0x00000001 176#define AR_ISR_RXOK 0x00000001
165#define AR_ISR_RXDESC 0x00000002 177#define AR_ISR_RXDESC 0x00000002
178#define AR_ISR_HP_RXOK 0x00000001
179#define AR_ISR_LP_RXOK 0x00000002
166#define AR_ISR_RXERR 0x00000004 180#define AR_ISR_RXERR 0x00000004
167#define AR_ISR_RXNOPKT 0x00000008 181#define AR_ISR_RXNOPKT 0x00000008
168#define AR_ISR_RXEOL 0x00000010 182#define AR_ISR_RXEOL 0x00000010
@@ -232,7 +246,6 @@
232#define AR_ISR_S5_TIMER_THRESH 0x0007FE00 246#define AR_ISR_S5_TIMER_THRESH 0x0007FE00
233#define AR_ISR_S5_TIM_TIMER 0x00000010 247#define AR_ISR_S5_TIM_TIMER 0x00000010
234#define AR_ISR_S5_DTIM_TIMER 0x00000020 248#define AR_ISR_S5_DTIM_TIMER 0x00000020
235#define AR_ISR_S5_S 0x00d8
236#define AR_IMR_S5 0x00b8 249#define AR_IMR_S5 0x00b8
237#define AR_IMR_S5_TIM_TIMER 0x00000010 250#define AR_IMR_S5_TIM_TIMER 0x00000010
238#define AR_IMR_S5_DTIM_TIMER 0x00000020 251#define AR_IMR_S5_DTIM_TIMER 0x00000020
@@ -240,7 +253,6 @@
240#define AR_ISR_S5_GENTIMER_TRIG_S 0 253#define AR_ISR_S5_GENTIMER_TRIG_S 0
241#define AR_ISR_S5_GENTIMER_THRESH 0xFF800000 254#define AR_ISR_S5_GENTIMER_THRESH 0xFF800000
242#define AR_ISR_S5_GENTIMER_THRESH_S 16 255#define AR_ISR_S5_GENTIMER_THRESH_S 16
243#define AR_ISR_S5_S 0x00d8
244#define AR_IMR_S5_GENTIMER_TRIG 0x0000FF80 256#define AR_IMR_S5_GENTIMER_TRIG 0x0000FF80
245#define AR_IMR_S5_GENTIMER_TRIG_S 0 257#define AR_IMR_S5_GENTIMER_TRIG_S 0
246#define AR_IMR_S5_GENTIMER_THRESH 0xFF800000 258#define AR_IMR_S5_GENTIMER_THRESH 0xFF800000
@@ -249,6 +261,8 @@
249#define AR_IMR 0x00a0 261#define AR_IMR 0x00a0
250#define AR_IMR_RXOK 0x00000001 262#define AR_IMR_RXOK 0x00000001
251#define AR_IMR_RXDESC 0x00000002 263#define AR_IMR_RXDESC 0x00000002
264#define AR_IMR_RXOK_HP 0x00000001
265#define AR_IMR_RXOK_LP 0x00000002
252#define AR_IMR_RXERR 0x00000004 266#define AR_IMR_RXERR 0x00000004
253#define AR_IMR_RXNOPKT 0x00000008 267#define AR_IMR_RXNOPKT 0x00000008
254#define AR_IMR_RXEOL 0x00000010 268#define AR_IMR_RXEOL 0x00000010
@@ -332,10 +346,10 @@
332#define AR_ISR_S1_QCU_TXEOL 0x03FF0000 346#define AR_ISR_S1_QCU_TXEOL 0x03FF0000
333#define AR_ISR_S1_QCU_TXEOL_S 16 347#define AR_ISR_S1_QCU_TXEOL_S 16
334 348
335#define AR_ISR_S2_S 0x00cc 349#define AR_ISR_S2_S (AR_SREV_9300_20_OR_LATER(ah) ? 0x00d0 : 0x00cc)
336#define AR_ISR_S3_S 0x00d0 350#define AR_ISR_S3_S (AR_SREV_9300_20_OR_LATER(ah) ? 0x00d4 : 0x00d0)
337#define AR_ISR_S4_S 0x00d4 351#define AR_ISR_S4_S (AR_SREV_9300_20_OR_LATER(ah) ? 0x00d8 : 0x00d4)
338#define AR_ISR_S5_S 0x00d8 352#define AR_ISR_S5_S (AR_SREV_9300_20_OR_LATER(ah) ? 0x00dc : 0x00d8)
339#define AR_DMADBG_0 0x00e0 353#define AR_DMADBG_0 0x00e0
340#define AR_DMADBG_1 0x00e4 354#define AR_DMADBG_1 0x00e4
341#define AR_DMADBG_2 0x00e8 355#define AR_DMADBG_2 0x00e8
@@ -369,6 +383,9 @@
369#define AR_Q9_TXDP 0x0824 383#define AR_Q9_TXDP 0x0824
370#define AR_QTXDP(_i) (AR_Q0_TXDP + ((_i)<<2)) 384#define AR_QTXDP(_i) (AR_Q0_TXDP + ((_i)<<2))
371 385
386#define AR_Q_STATUS_RING_START 0x830
387#define AR_Q_STATUS_RING_END 0x834
388
372#define AR_Q_TXE 0x0840 389#define AR_Q_TXE 0x0840
373#define AR_Q_TXE_M 0x000003FF 390#define AR_Q_TXE_M 0x000003FF
374 391
@@ -461,6 +478,10 @@
461#define AR_Q_RDYTIMESHDN 0x0a40 478#define AR_Q_RDYTIMESHDN 0x0a40
462#define AR_Q_RDYTIMESHDN_M 0x000003FF 479#define AR_Q_RDYTIMESHDN_M 0x000003FF
463 480
481/* MAC Descriptor CRC check */
482#define AR_Q_DESC_CRCCHK 0xa44
483/* Enable CRC check on the descriptor fetched from host */
484#define AR_Q_DESC_CRCCHK_EN 1
464 485
465#define AR_NUM_DCU 10 486#define AR_NUM_DCU 10
466#define AR_DCU_0 0x0001 487#define AR_DCU_0 0x0001
@@ -759,6 +780,8 @@
759#define AR_SREV_VERSION_9271 0x140 780#define AR_SREV_VERSION_9271 0x140
760#define AR_SREV_REVISION_9271_10 0 781#define AR_SREV_REVISION_9271_10 0
761#define AR_SREV_REVISION_9271_11 1 782#define AR_SREV_REVISION_9271_11 1
783#define AR_SREV_VERSION_9300 0x1c0
784#define AR_SREV_REVISION_9300_20 2 /* 2.0 and 2.1 */
762 785
763#define AR_SREV_5416(_ah) \ 786#define AR_SREV_5416(_ah) \
764 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \ 787 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \
@@ -844,6 +867,15 @@
844#define AR_SREV_9271_11(_ah) \ 867#define AR_SREV_9271_11(_ah) \
845 (AR_SREV_9271(_ah) && \ 868 (AR_SREV_9271(_ah) && \
846 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9271_11)) 869 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9271_11))
870#define AR_SREV_9300(_ah) \
871 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9300))
872#define AR_SREV_9300_20(_ah) \
873 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9300) && \
874 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9300_20))
875#define AR_SREV_9300_20_OR_LATER(_ah) \
876 (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9300) || \
877 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9300) && \
878 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9300_20)))
847 879
848#define AR_SREV_9285E_20(_ah) \ 880#define AR_SREV_9285E_20(_ah) \
849 (AR_SREV_9285_12_OR_LATER(_ah) && \ 881 (AR_SREV_9285_12_OR_LATER(_ah) && \
@@ -945,6 +977,7 @@ enum {
945#define AR9285_NUM_GPIO 12 977#define AR9285_NUM_GPIO 12
946#define AR9287_NUM_GPIO 11 978#define AR9287_NUM_GPIO 11
947#define AR9271_NUM_GPIO 16 979#define AR9271_NUM_GPIO 16
980#define AR9300_NUM_GPIO 17
948 981
949#define AR_GPIO_IN_OUT 0x4048 982#define AR_GPIO_IN_OUT 0x4048
950#define AR_GPIO_IN_VAL 0x0FFFC000 983#define AR_GPIO_IN_VAL 0x0FFFC000
@@ -957,19 +990,21 @@ enum {
957#define AR9287_GPIO_IN_VAL_S 11 990#define AR9287_GPIO_IN_VAL_S 11
958#define AR9271_GPIO_IN_VAL 0xFFFF0000 991#define AR9271_GPIO_IN_VAL 0xFFFF0000
959#define AR9271_GPIO_IN_VAL_S 16 992#define AR9271_GPIO_IN_VAL_S 16
993#define AR9300_GPIO_IN_VAL 0x0001FFFF
994#define AR9300_GPIO_IN_VAL_S 0
960 995
961#define AR_GPIO_OE_OUT 0x404c 996#define AR_GPIO_OE_OUT (AR_SREV_9300_20_OR_LATER(ah) ? 0x4050 : 0x404c)
962#define AR_GPIO_OE_OUT_DRV 0x3 997#define AR_GPIO_OE_OUT_DRV 0x3
963#define AR_GPIO_OE_OUT_DRV_NO 0x0 998#define AR_GPIO_OE_OUT_DRV_NO 0x0
964#define AR_GPIO_OE_OUT_DRV_LOW 0x1 999#define AR_GPIO_OE_OUT_DRV_LOW 0x1
965#define AR_GPIO_OE_OUT_DRV_HI 0x2 1000#define AR_GPIO_OE_OUT_DRV_HI 0x2
966#define AR_GPIO_OE_OUT_DRV_ALL 0x3 1001#define AR_GPIO_OE_OUT_DRV_ALL 0x3
967 1002
968#define AR_GPIO_INTR_POL 0x4050 1003#define AR_GPIO_INTR_POL (AR_SREV_9300_20_OR_LATER(ah) ? 0x4058 : 0x4050)
969#define AR_GPIO_INTR_POL_VAL 0x00001FFF 1004#define AR_GPIO_INTR_POL_VAL 0x0001FFFF
970#define AR_GPIO_INTR_POL_VAL_S 0 1005#define AR_GPIO_INTR_POL_VAL_S 0
971 1006
972#define AR_GPIO_INPUT_EN_VAL 0x4054 1007#define AR_GPIO_INPUT_EN_VAL (AR_SREV_9300_20_OR_LATER(ah) ? 0x405c : 0x4054)
973#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF 0x00000004 1008#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF 0x00000004
974#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_S 2 1009#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_S 2
975#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF 0x00000008 1010#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF 0x00000008
@@ -987,13 +1022,13 @@ enum {
987#define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000 1022#define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000
988#define AR_GPIO_JTAG_DISABLE 0x00020000 1023#define AR_GPIO_JTAG_DISABLE 0x00020000
989 1024
990#define AR_GPIO_INPUT_MUX1 0x4058 1025#define AR_GPIO_INPUT_MUX1 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4060 : 0x4058)
991#define AR_GPIO_INPUT_MUX1_BT_ACTIVE 0x000f0000 1026#define AR_GPIO_INPUT_MUX1_BT_ACTIVE 0x000f0000
992#define AR_GPIO_INPUT_MUX1_BT_ACTIVE_S 16 1027#define AR_GPIO_INPUT_MUX1_BT_ACTIVE_S 16
993#define AR_GPIO_INPUT_MUX1_BT_PRIORITY 0x00000f00 1028#define AR_GPIO_INPUT_MUX1_BT_PRIORITY 0x00000f00
994#define AR_GPIO_INPUT_MUX1_BT_PRIORITY_S 8 1029#define AR_GPIO_INPUT_MUX1_BT_PRIORITY_S 8
995 1030
996#define AR_GPIO_INPUT_MUX2 0x405c 1031#define AR_GPIO_INPUT_MUX2 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4064 : 0x405c)
997#define AR_GPIO_INPUT_MUX2_CLK25 0x0000000f 1032#define AR_GPIO_INPUT_MUX2_CLK25 0x0000000f
998#define AR_GPIO_INPUT_MUX2_CLK25_S 0 1033#define AR_GPIO_INPUT_MUX2_CLK25_S 0
999#define AR_GPIO_INPUT_MUX2_RFSILENT 0x000000f0 1034#define AR_GPIO_INPUT_MUX2_RFSILENT 0x000000f0
@@ -1001,13 +1036,13 @@ enum {
1001#define AR_GPIO_INPUT_MUX2_RTC_RESET 0x00000f00 1036#define AR_GPIO_INPUT_MUX2_RTC_RESET 0x00000f00
1002#define AR_GPIO_INPUT_MUX2_RTC_RESET_S 8 1037#define AR_GPIO_INPUT_MUX2_RTC_RESET_S 8
1003 1038
1004#define AR_GPIO_OUTPUT_MUX1 0x4060 1039#define AR_GPIO_OUTPUT_MUX1 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4068 : 0x4060)
1005#define AR_GPIO_OUTPUT_MUX2 0x4064 1040#define AR_GPIO_OUTPUT_MUX2 (AR_SREV_9300_20_OR_LATER(ah) ? 0x406c : 0x4064)
1006#define AR_GPIO_OUTPUT_MUX3 0x4068 1041#define AR_GPIO_OUTPUT_MUX3 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4070 : 0x4068)
1007 1042
1008#define AR_INPUT_STATE 0x406c 1043#define AR_INPUT_STATE (AR_SREV_9300_20_OR_LATER(ah) ? 0x4074 : 0x406c)
1009 1044
1010#define AR_EEPROM_STATUS_DATA 0x407c 1045#define AR_EEPROM_STATUS_DATA (AR_SREV_9300_20_OR_LATER(ah) ? 0x4084 : 0x407c)
1011#define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff 1046#define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff
1012#define AR_EEPROM_STATUS_DATA_VAL_S 0 1047#define AR_EEPROM_STATUS_DATA_VAL_S 0
1013#define AR_EEPROM_STATUS_DATA_BUSY 0x00010000 1048#define AR_EEPROM_STATUS_DATA_BUSY 0x00010000
@@ -1015,13 +1050,24 @@ enum {
1015#define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000 1050#define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000
1016#define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000 1051#define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000
1017 1052
1018#define AR_OBS 0x4080 1053#define AR_OBS (AR_SREV_9300_20_OR_LATER(ah) ? 0x4088 : 0x4080)
1019 1054
1020#define AR_GPIO_PDPU 0x4088 1055#define AR_GPIO_PDPU (AR_SREV_9300_20_OR_LATER(ah) ? 0x4090 : 0x4088)
1021 1056
1022#define AR_PCIE_MSI 0x4094 1057#define AR_PCIE_MSI (AR_SREV_9300_20_OR_LATER(ah) ? 0x40a4 : 0x4094)
1023#define AR_PCIE_MSI_ENABLE 0x00000001 1058#define AR_PCIE_MSI_ENABLE 0x00000001
1024 1059
1060#define AR_INTR_PRIO_SYNC_ENABLE 0x40c4
1061#define AR_INTR_PRIO_ASYNC_MASK 0x40c8
1062#define AR_INTR_PRIO_SYNC_MASK 0x40cc
1063#define AR_INTR_PRIO_ASYNC_ENABLE 0x40d4
1064
1065#define AR_RTC_9300_PLL_DIV 0x000003ff
1066#define AR_RTC_9300_PLL_DIV_S 0
1067#define AR_RTC_9300_PLL_REFDIV 0x00003C00
1068#define AR_RTC_9300_PLL_REFDIV_S 10
1069#define AR_RTC_9300_PLL_CLKSEL 0x0000C000
1070#define AR_RTC_9300_PLL_CLKSEL_S 14
1025 1071
1026#define AR_RTC_9160_PLL_DIV 0x000003ff 1072#define AR_RTC_9160_PLL_DIV 0x000003ff
1027#define AR_RTC_9160_PLL_DIV_S 0 1073#define AR_RTC_9160_PLL_DIV_S 0
@@ -1039,6 +1085,16 @@ enum {
1039#define AR_RTC_RC_COLD_RESET 0x00000004 1085#define AR_RTC_RC_COLD_RESET 0x00000004
1040#define AR_RTC_RC_WARM_RESET 0x00000008 1086#define AR_RTC_RC_WARM_RESET 0x00000008
1041 1087
1088/* Crystal Control */
1089#define AR_RTC_XTAL_CONTROL 0x7004
1090
1091/* Reg Control 0 */
1092#define AR_RTC_REG_CONTROL0 0x7008
1093
1094/* Reg Control 1 */
1095#define AR_RTC_REG_CONTROL1 0x700c
1096#define AR_RTC_REG_CONTROL1_SWREG_PROGRAM 0x00000001
1097
1042#define AR_RTC_PLL_CONTROL \ 1098#define AR_RTC_PLL_CONTROL \
1043 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0014) : 0x7014) 1099 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0014) : 0x7014)
1044 1100
@@ -1069,6 +1125,7 @@ enum {
1069#define AR_RTC_SLEEP_CLK \ 1125#define AR_RTC_SLEEP_CLK \
1070 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0048) : 0x7048) 1126 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0048) : 0x7048)
1071#define AR_RTC_FORCE_DERIVED_CLK 0x2 1127#define AR_RTC_FORCE_DERIVED_CLK 0x2
1128#define AR_RTC_FORCE_SWREG_PRD 0x00000004
1072 1129
1073#define AR_RTC_FORCE_WAKE \ 1130#define AR_RTC_FORCE_WAKE \
1074 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x004c) : 0x704c) 1131 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x004c) : 0x704c)
@@ -1533,7 +1590,7 @@ enum {
1533#define AR_TSFOOR_THRESHOLD 0x813c 1590#define AR_TSFOOR_THRESHOLD 0x813c
1534#define AR_TSFOOR_THRESHOLD_VAL 0x0000FFFF 1591#define AR_TSFOOR_THRESHOLD_VAL 0x0000FFFF
1535 1592
1536#define AR_PHY_ERR_EIFS_MASK 8144 1593#define AR_PHY_ERR_EIFS_MASK 0x8144
1537 1594
1538#define AR_PHY_ERR_3 0x8168 1595#define AR_PHY_ERR_3 0x8168
1539#define AR_PHY_ERR_3_COUNT 0x00FFFFFF 1596#define AR_PHY_ERR_3_COUNT 0x00FFFFFF
@@ -1599,24 +1656,26 @@ enum {
1599#define AR_FIRST_NDP_TIMER 7 1656#define AR_FIRST_NDP_TIMER 7
1600#define AR_NDP2_PERIOD 0x81a0 1657#define AR_NDP2_PERIOD 0x81a0
1601#define AR_NDP2_TIMER_MODE 0x81c0 1658#define AR_NDP2_TIMER_MODE 0x81c0
1602#define AR_NEXT_TBTT_TIMER 0x8200 1659
1603#define AR_NEXT_DMA_BEACON_ALERT 0x8204 1660#define AR_GEN_TIMERS(_i) (0x8200 + ((_i) << 2))
1604#define AR_NEXT_SWBA 0x8208 1661#define AR_NEXT_TBTT_TIMER AR_GEN_TIMERS(0)
1605#define AR_NEXT_CFP 0x8208 1662#define AR_NEXT_DMA_BEACON_ALERT AR_GEN_TIMERS(1)
1606#define AR_NEXT_HCF 0x820C 1663#define AR_NEXT_SWBA AR_GEN_TIMERS(2)
1607#define AR_NEXT_TIM 0x8210 1664#define AR_NEXT_CFP AR_GEN_TIMERS(2)
1608#define AR_NEXT_DTIM 0x8214 1665#define AR_NEXT_HCF AR_GEN_TIMERS(3)
1609#define AR_NEXT_QUIET_TIMER 0x8218 1666#define AR_NEXT_TIM AR_GEN_TIMERS(4)
1610#define AR_NEXT_NDP_TIMER 0x821C 1667#define AR_NEXT_DTIM AR_GEN_TIMERS(5)
1611 1668#define AR_NEXT_QUIET_TIMER AR_GEN_TIMERS(6)
1612#define AR_BEACON_PERIOD 0x8220 1669#define AR_NEXT_NDP_TIMER AR_GEN_TIMERS(7)
1613#define AR_DMA_BEACON_PERIOD 0x8224 1670
1614#define AR_SWBA_PERIOD 0x8228 1671#define AR_BEACON_PERIOD AR_GEN_TIMERS(8)
1615#define AR_HCF_PERIOD 0x822C 1672#define AR_DMA_BEACON_PERIOD AR_GEN_TIMERS(9)
1616#define AR_TIM_PERIOD 0x8230 1673#define AR_SWBA_PERIOD AR_GEN_TIMERS(10)
1617#define AR_DTIM_PERIOD 0x8234 1674#define AR_HCF_PERIOD AR_GEN_TIMERS(11)
1618#define AR_QUIET_PERIOD 0x8238 1675#define AR_TIM_PERIOD AR_GEN_TIMERS(12)
1619#define AR_NDP_PERIOD 0x823C 1676#define AR_DTIM_PERIOD AR_GEN_TIMERS(13)
1677#define AR_QUIET_PERIOD AR_GEN_TIMERS(14)
1678#define AR_NDP_PERIOD AR_GEN_TIMERS(15)
1620 1679
1621#define AR_TIMER_MODE 0x8240 1680#define AR_TIMER_MODE 0x8240
1622#define AR_TBTT_TIMER_EN 0x00000001 1681#define AR_TBTT_TIMER_EN 0x00000001
@@ -1730,4 +1789,32 @@ enum {
1730#define AR9271_CORE_CLOCK 117 /* clock to 117Mhz */ 1789#define AR9271_CORE_CLOCK 117 /* clock to 117Mhz */
1731#define AR9271_TARGET_BAUD_RATE 19200 /* 115200 */ 1790#define AR9271_TARGET_BAUD_RATE 19200 /* 115200 */
1732 1791
1792#define AR_AGG_WEP_ENABLE_FIX 0x00000008 /* This allows the use of AR_AGG_WEP_ENABLE */
1793#define AR_ADHOC_MCAST_KEYID_ENABLE 0x00000040 /* This bit enables the Multicast search
1794 * based on both MAC Address and Key ID.
1795 * If bit is 0, then Multicast search is
1796 * based on MAC address only.
1797 * For Merlin and above only.
1798 */
1799#define AR_AGG_WEP_ENABLE 0x00020000 /* This field enables AGG_WEP feature,
1800 * when it is enable, AGG_WEP would takes
1801 * charge of the encryption interface of
1802 * pcu_txsm.
1803 */
1804
1805#define AR9300_SM_BASE 0xa200
1806#define AR9002_PHY_AGC_CONTROL 0x9860
1807#define AR9003_PHY_AGC_CONTROL AR9300_SM_BASE + 0xc4
1808#define AR_PHY_AGC_CONTROL (AR_SREV_9300_20_OR_LATER(ah) ? AR9003_PHY_AGC_CONTROL : AR9002_PHY_AGC_CONTROL)
1809#define AR_PHY_AGC_CONTROL_CAL 0x00000001 /* do internal calibration */
1810#define AR_PHY_AGC_CONTROL_NF 0x00000002 /* do noise-floor calibration */
1811#define AR_PHY_AGC_CONTROL_OFFSET_CAL 0x00000800 /* allow offset calibration */
1812#define AR_PHY_AGC_CONTROL_ENABLE_NF 0x00008000 /* enable noise floor calibration to happen */
1813#define AR_PHY_AGC_CONTROL_FLTR_CAL 0x00010000 /* allow tx filter calibration */
1814#define AR_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000 /* don't update noise floor automatically */
1815#define AR_PHY_AGC_CONTROL_EXT_NF_PWR_MEAS 0x00040000 /* extend noise floor power measurement */
1816#define AR_PHY_AGC_CONTROL_CLC_SUCCESS 0x00080000 /* carrier leak calibration done */
1817#define AR_PHY_AGC_CONTROL_YCOK_MAX 0x000003c0
1818#define AR_PHY_AGC_CONTROL_YCOK_MAX_S 6
1819
1733#endif 1820#endif
diff --git a/drivers/net/wireless/ath/ath9k/wmi.c b/drivers/net/wireless/ath/ath9k/wmi.c
index f2ff18cf3e60..e23172c9caaf 100644
--- a/drivers/net/wireless/ath/ath9k/wmi.c
+++ b/drivers/net/wireless/ath/ath9k/wmi.c
@@ -101,6 +101,7 @@ struct wmi *ath9k_init_wmi(struct ath9k_htc_priv *priv)
101 wmi->drv_priv = priv; 101 wmi->drv_priv = priv;
102 wmi->stopped = false; 102 wmi->stopped = false;
103 mutex_init(&wmi->op_mutex); 103 mutex_init(&wmi->op_mutex);
104 mutex_init(&wmi->multi_write_mutex);
104 init_completion(&wmi->cmd_wait); 105 init_completion(&wmi->cmd_wait);
105 106
106 return wmi; 107 return wmi;
@@ -128,7 +129,7 @@ void ath9k_wmi_tasklet(unsigned long data)
128 void *wmi_event; 129 void *wmi_event;
129 unsigned long flags; 130 unsigned long flags;
130#ifdef CONFIG_ATH9K_HTC_DEBUGFS 131#ifdef CONFIG_ATH9K_HTC_DEBUGFS
131 u32 txrate; 132 __be32 txrate;
132#endif 133#endif
133 134
134 spin_lock_irqsave(&priv->wmi->wmi_lock, flags); 135 spin_lock_irqsave(&priv->wmi->wmi_lock, flags);
@@ -203,6 +204,14 @@ static void ath9k_wmi_ctrl_rx(void *priv, struct sk_buff *skb,
203 return; 204 return;
204 } 205 }
205 206
207 /* Check if there has been a timeout. */
208 spin_lock(&wmi->wmi_lock);
209 if (cmd_id != wmi->last_cmd_id) {
210 spin_unlock(&wmi->wmi_lock);
211 goto free_skb;
212 }
213 spin_unlock(&wmi->wmi_lock);
214
206 /* WMI command response */ 215 /* WMI command response */
207 ath9k_wmi_rsp_callback(wmi, skb); 216 ath9k_wmi_rsp_callback(wmi, skb);
208 217
@@ -265,6 +274,10 @@ int ath9k_wmi_cmd(struct wmi *wmi, enum wmi_cmd_id cmd_id,
265 struct sk_buff *skb; 274 struct sk_buff *skb;
266 u8 *data; 275 u8 *data;
267 int time_left, ret = 0; 276 int time_left, ret = 0;
277 unsigned long flags;
278
279 if (wmi->drv_priv->op_flags & OP_UNPLUGGED)
280 return 0;
268 281
269 if (!wmi) 282 if (!wmi)
270 return -EINVAL; 283 return -EINVAL;
@@ -292,6 +305,10 @@ int ath9k_wmi_cmd(struct wmi *wmi, enum wmi_cmd_id cmd_id,
292 wmi->cmd_rsp_buf = rsp_buf; 305 wmi->cmd_rsp_buf = rsp_buf;
293 wmi->cmd_rsp_len = rsp_len; 306 wmi->cmd_rsp_len = rsp_len;
294 307
308 spin_lock_irqsave(&wmi->wmi_lock, flags);
309 wmi->last_cmd_id = cmd_id;
310 spin_unlock_irqrestore(&wmi->wmi_lock, flags);
311
295 ret = ath9k_wmi_cmd_issue(wmi, skb, cmd_id, cmd_len); 312 ret = ath9k_wmi_cmd_issue(wmi, skb, cmd_id, cmd_len);
296 if (ret) 313 if (ret)
297 goto out; 314 goto out;
diff --git a/drivers/net/wireless/ath/ath9k/wmi.h b/drivers/net/wireless/ath/ath9k/wmi.h
index 39ef926f27c2..765db5faa2d3 100644
--- a/drivers/net/wireless/ath/ath9k/wmi.h
+++ b/drivers/net/wireless/ath/ath9k/wmi.h
@@ -19,7 +19,7 @@
19 19
20 20
21struct wmi_event_txrate { 21struct wmi_event_txrate {
22 u32 txrate; 22 __be32 txrate;
23 struct { 23 struct {
24 u8 rssi_thresh; 24 u8 rssi_thresh;
25 u8 per; 25 u8 per;
@@ -27,8 +27,8 @@ struct wmi_event_txrate {
27} __packed; 27} __packed;
28 28
29struct wmi_cmd_hdr { 29struct wmi_cmd_hdr {
30 u16 command_id; 30 __be16 command_id;
31 u16 seq_no; 31 __be16 seq_no;
32} __packed; 32} __packed;
33 33
34struct wmi_swba { 34struct wmi_swba {
@@ -84,12 +84,20 @@ enum wmi_event_id {
84 WMI_TXRATE_EVENTID, 84 WMI_TXRATE_EVENTID,
85}; 85};
86 86
87#define MAX_CMD_NUMBER 62
88
89struct register_write {
90 __be32 reg;
91 __be32 val;
92};
93
87struct wmi { 94struct wmi {
88 struct ath9k_htc_priv *drv_priv; 95 struct ath9k_htc_priv *drv_priv;
89 struct htc_target *htc; 96 struct htc_target *htc;
90 enum htc_endpoint_id ctrl_epid; 97 enum htc_endpoint_id ctrl_epid;
91 struct mutex op_mutex; 98 struct mutex op_mutex;
92 struct completion cmd_wait; 99 struct completion cmd_wait;
100 enum wmi_cmd_id last_cmd_id;
93 u16 tx_seq_id; 101 u16 tx_seq_id;
94 u8 *cmd_rsp_buf; 102 u8 *cmd_rsp_buf;
95 u32 cmd_rsp_len; 103 u32 cmd_rsp_len;
@@ -97,6 +105,11 @@ struct wmi {
97 105
98 struct sk_buff *wmi_skb; 106 struct sk_buff *wmi_skb;
99 spinlock_t wmi_lock; 107 spinlock_t wmi_lock;
108
109 atomic_t mwrite_cnt;
110 struct register_write multi_write[MAX_CMD_NUMBER];
111 u32 multi_write_idx;
112 struct mutex multi_write_mutex;
100}; 113};
101 114
102struct wmi *ath9k_init_wmi(struct ath9k_htc_priv *priv); 115struct wmi *ath9k_init_wmi(struct ath9k_htc_priv *priv);
@@ -113,14 +126,14 @@ void ath9k_wmi_tasklet(unsigned long data);
113 do { \ 126 do { \
114 ret = ath9k_wmi_cmd(priv->wmi, _wmi_cmd, NULL, 0, \ 127 ret = ath9k_wmi_cmd(priv->wmi, _wmi_cmd, NULL, 0, \
115 (u8 *) &cmd_rsp, \ 128 (u8 *) &cmd_rsp, \
116 sizeof(cmd_rsp), HZ); \ 129 sizeof(cmd_rsp), HZ*2); \
117 } while (0) 130 } while (0)
118 131
119#define WMI_CMD_BUF(_wmi_cmd, _buf) \ 132#define WMI_CMD_BUF(_wmi_cmd, _buf) \
120 do { \ 133 do { \
121 ret = ath9k_wmi_cmd(priv->wmi, _wmi_cmd, \ 134 ret = ath9k_wmi_cmd(priv->wmi, _wmi_cmd, \
122 (u8 *) _buf, sizeof(*_buf), \ 135 (u8 *) _buf, sizeof(*_buf), \
123 &cmd_rsp, sizeof(cmd_rsp), HZ); \ 136 &cmd_rsp, sizeof(cmd_rsp), HZ*2); \
124 } while (0) 137 } while (0)
125 138
126#endif /* WMI_H */ 139#endif /* WMI_H */
diff --git a/drivers/net/wireless/ath/ath9k/xmit.c b/drivers/net/wireless/ath/ath9k/xmit.c
index 02df4cbf179f..3db19172b43b 100644
--- a/drivers/net/wireless/ath/ath9k/xmit.c
+++ b/drivers/net/wireless/ath/ath9k/xmit.c
@@ -15,10 +15,11 @@
15 */ 15 */
16 16
17#include "ath9k.h" 17#include "ath9k.h"
18#include "ar9003_mac.h"
18 19
19#define BITS_PER_BYTE 8 20#define BITS_PER_BYTE 8
20#define OFDM_PLCP_BITS 22 21#define OFDM_PLCP_BITS 22
21#define HT_RC_2_MCS(_rc) ((_rc) & 0x0f) 22#define HT_RC_2_MCS(_rc) ((_rc) & 0x1f)
22#define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1) 23#define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
23#define L_STF 8 24#define L_STF 8
24#define L_LTF 8 25#define L_LTF 8
@@ -33,7 +34,7 @@
33 34
34#define OFDM_SIFS_TIME 16 35#define OFDM_SIFS_TIME 16
35 36
36static u32 bits_per_symbol[][2] = { 37static u16 bits_per_symbol[][2] = {
37 /* 20MHz 40MHz */ 38 /* 20MHz 40MHz */
38 { 26, 54 }, /* 0: BPSK */ 39 { 26, 54 }, /* 0: BPSK */
39 { 52, 108 }, /* 1: QPSK 1/2 */ 40 { 52, 108 }, /* 1: QPSK 1/2 */
@@ -43,14 +44,6 @@ static u32 bits_per_symbol[][2] = {
43 { 208, 432 }, /* 5: 64-QAM 2/3 */ 44 { 208, 432 }, /* 5: 64-QAM 2/3 */
44 { 234, 486 }, /* 6: 64-QAM 3/4 */ 45 { 234, 486 }, /* 6: 64-QAM 3/4 */
45 { 260, 540 }, /* 7: 64-QAM 5/6 */ 46 { 260, 540 }, /* 7: 64-QAM 5/6 */
46 { 52, 108 }, /* 8: BPSK */
47 { 104, 216 }, /* 9: QPSK 1/2 */
48 { 156, 324 }, /* 10: QPSK 3/4 */
49 { 208, 432 }, /* 11: 16-QAM 1/2 */
50 { 312, 648 }, /* 12: 16-QAM 3/4 */
51 { 416, 864 }, /* 13: 64-QAM 2/3 */
52 { 468, 972 }, /* 14: 64-QAM 3/4 */
53 { 520, 1080 }, /* 15: 64-QAM 5/6 */
54}; 47};
55 48
56#define IS_HT_RATE(_rate) ((_rate) & 0x80) 49#define IS_HT_RATE(_rate) ((_rate) & 0x80)
@@ -70,28 +63,39 @@ static void ath_tx_rc_status(struct ath_buf *bf, struct ath_tx_status *ts,
70 int nbad, int txok, bool update_rc); 63 int nbad, int txok, bool update_rc);
71 64
72enum { 65enum {
73 MCS_DEFAULT, 66 MCS_HT20,
67 MCS_HT20_SGI,
74 MCS_HT40, 68 MCS_HT40,
75 MCS_HT40_SGI, 69 MCS_HT40_SGI,
76}; 70};
77 71
78static int ath_max_4ms_framelen[3][16] = { 72static int ath_max_4ms_framelen[4][32] = {
79 [MCS_DEFAULT] = { 73 [MCS_HT20] = {
80 3216, 6434, 9650, 12868, 19304, 25740, 28956, 32180, 74 3212, 6432, 9648, 12864, 19300, 25736, 28952, 32172,
81 6430, 12860, 19300, 25736, 38600, 51472, 57890, 64320, 75 6424, 12852, 19280, 25708, 38568, 51424, 57852, 64280,
76 9628, 19260, 28896, 38528, 57792, 65532, 65532, 65532,
77 12828, 25656, 38488, 51320, 65532, 65532, 65532, 65532,
78 },
79 [MCS_HT20_SGI] = {
80 3572, 7144, 10720, 14296, 21444, 28596, 32172, 35744,
81 7140, 14284, 21428, 28568, 42856, 57144, 64288, 65532,
82 10700, 21408, 32112, 42816, 64228, 65532, 65532, 65532,
83 14256, 28516, 42780, 57040, 65532, 65532, 65532, 65532,
82 }, 84 },
83 [MCS_HT40] = { 85 [MCS_HT40] = {
84 6684, 13368, 20052, 26738, 40104, 53476, 60156, 66840, 86 6680, 13360, 20044, 26724, 40092, 53456, 60140, 65532,
85 13360, 26720, 40080, 53440, 80160, 106880, 120240, 133600, 87 13348, 26700, 40052, 53400, 65532, 65532, 65532, 65532,
88 20004, 40008, 60016, 65532, 65532, 65532, 65532, 65532,
89 26644, 53292, 65532, 65532, 65532, 65532, 65532, 65532,
86 }, 90 },
87 [MCS_HT40_SGI] = { 91 [MCS_HT40_SGI] = {
88 /* TODO: Only MCS 7 and 15 updated, recalculate the rest */ 92 7420, 14844, 22272, 29696, 44544, 59396, 65532, 65532,
89 6684, 13368, 20052, 26738, 40104, 53476, 60156, 74200, 93 14832, 29668, 44504, 59340, 65532, 65532, 65532, 65532,
90 13360, 26720, 40080, 53440, 80160, 106880, 120240, 148400, 94 22232, 44464, 65532, 65532, 65532, 65532, 65532, 65532,
95 29616, 59232, 65532, 65532, 65532, 65532, 65532, 65532,
91 } 96 }
92}; 97};
93 98
94
95/*********************/ 99/*********************/
96/* Aggregation logic */ 100/* Aggregation logic */
97/*********************/ 101/*********************/
@@ -261,25 +265,46 @@ static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
261 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY); 265 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
262} 266}
263 267
264static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf) 268static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
265{ 269{
266 struct ath_buf *tbf; 270 struct ath_buf *bf = NULL;
267 271
268 spin_lock_bh(&sc->tx.txbuflock); 272 spin_lock_bh(&sc->tx.txbuflock);
269 if (WARN_ON(list_empty(&sc->tx.txbuf))) { 273
274 if (unlikely(list_empty(&sc->tx.txbuf))) {
270 spin_unlock_bh(&sc->tx.txbuflock); 275 spin_unlock_bh(&sc->tx.txbuflock);
271 return NULL; 276 return NULL;
272 } 277 }
273 tbf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list); 278
274 list_del(&tbf->list); 279 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
280 list_del(&bf->list);
281
275 spin_unlock_bh(&sc->tx.txbuflock); 282 spin_unlock_bh(&sc->tx.txbuflock);
276 283
284 return bf;
285}
286
287static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
288{
289 spin_lock_bh(&sc->tx.txbuflock);
290 list_add_tail(&bf->list, &sc->tx.txbuf);
291 spin_unlock_bh(&sc->tx.txbuflock);
292}
293
294static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
295{
296 struct ath_buf *tbf;
297
298 tbf = ath_tx_get_buffer(sc);
299 if (WARN_ON(!tbf))
300 return NULL;
301
277 ATH_TXBUF_RESET(tbf); 302 ATH_TXBUF_RESET(tbf);
278 303
279 tbf->aphy = bf->aphy; 304 tbf->aphy = bf->aphy;
280 tbf->bf_mpdu = bf->bf_mpdu; 305 tbf->bf_mpdu = bf->bf_mpdu;
281 tbf->bf_buf_addr = bf->bf_buf_addr; 306 tbf->bf_buf_addr = bf->bf_buf_addr;
282 *(tbf->bf_desc) = *(bf->bf_desc); 307 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
283 tbf->bf_state = bf->bf_state; 308 tbf->bf_state = bf->bf_state;
284 tbf->bf_dmacontext = bf->bf_dmacontext; 309 tbf->bf_dmacontext = bf->bf_dmacontext;
285 310
@@ -359,7 +384,7 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
359 acked_cnt++; 384 acked_cnt++;
360 } else { 385 } else {
361 if (!(tid->state & AGGR_CLEANUP) && 386 if (!(tid->state & AGGR_CLEANUP) &&
362 ts->ts_flags != ATH9K_TX_SW_ABORTED) { 387 !bf_last->bf_tx_aborted) {
363 if (bf->bf_retries < ATH_MAX_SW_RETRIES) { 388 if (bf->bf_retries < ATH_MAX_SW_RETRIES) {
364 ath_tx_set_retry(sc, txq, bf); 389 ath_tx_set_retry(sc, txq, bf);
365 txpending = 1; 390 txpending = 1;
@@ -378,7 +403,8 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
378 } 403 }
379 } 404 }
380 405
381 if (bf_next == NULL) { 406 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
407 bf_next == NULL) {
382 /* 408 /*
383 * Make sure the last desc is reclaimed if it 409 * Make sure the last desc is reclaimed if it
384 * not a holding desc. 410 * not a holding desc.
@@ -412,36 +438,43 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
412 !txfail, sendbar); 438 !txfail, sendbar);
413 } else { 439 } else {
414 /* retry the un-acked ones */ 440 /* retry the un-acked ones */
415 if (bf->bf_next == NULL && bf_last->bf_stale) { 441 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) {
416 struct ath_buf *tbf; 442 if (bf->bf_next == NULL && bf_last->bf_stale) {
417 443 struct ath_buf *tbf;
418 tbf = ath_clone_txbuf(sc, bf_last); 444
419 /* 445 tbf = ath_clone_txbuf(sc, bf_last);
420 * Update tx baw and complete the frame with 446 /*
421 * failed status if we run out of tx buf 447 * Update tx baw and complete the
422 */ 448 * frame with failed status if we
423 if (!tbf) { 449 * run out of tx buf.
424 spin_lock_bh(&txq->axq_lock); 450 */
425 ath_tx_update_baw(sc, tid, 451 if (!tbf) {
426 bf->bf_seqno); 452 spin_lock_bh(&txq->axq_lock);
427 spin_unlock_bh(&txq->axq_lock); 453 ath_tx_update_baw(sc, tid,
428 454 bf->bf_seqno);
429 bf->bf_state.bf_type |= BUF_XRETRY; 455 spin_unlock_bh(&txq->axq_lock);
430 ath_tx_rc_status(bf, ts, nbad, 456
431 0, false); 457 bf->bf_state.bf_type |=
432 ath_tx_complete_buf(sc, bf, txq, 458 BUF_XRETRY;
433 &bf_head, ts, 0, 0); 459 ath_tx_rc_status(bf, ts, nbad,
434 break; 460 0, false);
461 ath_tx_complete_buf(sc, bf, txq,
462 &bf_head,
463 ts, 0, 0);
464 break;
465 }
466
467 ath9k_hw_cleartxdesc(sc->sc_ah,
468 tbf->bf_desc);
469 list_add_tail(&tbf->list, &bf_head);
470 } else {
471 /*
472 * Clear descriptor status words for
473 * software retry
474 */
475 ath9k_hw_cleartxdesc(sc->sc_ah,
476 bf->bf_desc);
435 } 477 }
436
437 ath9k_hw_cleartxdesc(sc->sc_ah, tbf->bf_desc);
438 list_add_tail(&tbf->list, &bf_head);
439 } else {
440 /*
441 * Clear descriptor status words for
442 * software retry
443 */
444 ath9k_hw_cleartxdesc(sc->sc_ah, bf->bf_desc);
445 } 478 }
446 479
447 /* 480 /*
@@ -509,12 +542,13 @@ static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
509 break; 542 break;
510 } 543 }
511 544
512 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) 545 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
513 modeidx = MCS_HT40_SGI;
514 else if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
515 modeidx = MCS_HT40; 546 modeidx = MCS_HT40;
516 else 547 else
517 modeidx = MCS_DEFAULT; 548 modeidx = MCS_HT20;
549
550 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
551 modeidx++;
518 552
519 frmlen = ath_max_4ms_framelen[modeidx][rates[i].idx]; 553 frmlen = ath_max_4ms_framelen[modeidx][rates[i].idx];
520 max_4ms_framelen = min(max_4ms_framelen, frmlen); 554 max_4ms_framelen = min(max_4ms_framelen, frmlen);
@@ -559,7 +593,7 @@ static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
559 u32 nsymbits, nsymbols; 593 u32 nsymbits, nsymbols;
560 u16 minlen; 594 u16 minlen;
561 u8 flags, rix; 595 u8 flags, rix;
562 int width, half_gi, ndelim, mindelim; 596 int width, streams, half_gi, ndelim, mindelim;
563 597
564 /* Select standard number of delimiters based on frame length alone */ 598 /* Select standard number of delimiters based on frame length alone */
565 ndelim = ATH_AGGR_GET_NDELIM(frmlen); 599 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
@@ -599,7 +633,8 @@ static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
599 if (nsymbols == 0) 633 if (nsymbols == 0)
600 nsymbols = 1; 634 nsymbols = 1;
601 635
602 nsymbits = bits_per_symbol[rix][width]; 636 streams = HT_RC_2_STREAMS(rix);
637 nsymbits = bits_per_symbol[rix % 8][width] * streams;
603 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE; 638 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
604 639
605 if (frmlen < minlen) { 640 if (frmlen < minlen) {
@@ -665,7 +700,7 @@ static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
665 bpad = PADBYTES(al_delta) + (ndelim << 2); 700 bpad = PADBYTES(al_delta) + (ndelim << 2);
666 701
667 bf->bf_next = NULL; 702 bf->bf_next = NULL;
668 bf->bf_desc->ds_link = 0; 703 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, 0);
669 704
670 /* link buffers of this frame to the aggregate */ 705 /* link buffers of this frame to the aggregate */
671 ath_tx_addto_baw(sc, tid, bf); 706 ath_tx_addto_baw(sc, tid, bf);
@@ -673,7 +708,8 @@ static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
673 list_move_tail(&bf->list, bf_q); 708 list_move_tail(&bf->list, bf_q);
674 if (bf_prev) { 709 if (bf_prev) {
675 bf_prev->bf_next = bf; 710 bf_prev->bf_next = bf;
676 bf_prev->bf_desc->ds_link = bf->bf_daddr; 711 ath9k_hw_set_desc_link(sc->sc_ah, bf_prev->bf_desc,
712 bf->bf_daddr);
677 } 713 }
678 bf_prev = bf; 714 bf_prev = bf;
679 715
@@ -853,7 +889,7 @@ struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
853 struct ath_hw *ah = sc->sc_ah; 889 struct ath_hw *ah = sc->sc_ah;
854 struct ath_common *common = ath9k_hw_common(ah); 890 struct ath_common *common = ath9k_hw_common(ah);
855 struct ath9k_tx_queue_info qi; 891 struct ath9k_tx_queue_info qi;
856 int qnum; 892 int qnum, i;
857 893
858 memset(&qi, 0, sizeof(qi)); 894 memset(&qi, 0, sizeof(qi));
859 qi.tqi_subtype = subtype; 895 qi.tqi_subtype = subtype;
@@ -877,11 +913,16 @@ struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
877 * The UAPSD queue is an exception, since we take a desc- 913 * The UAPSD queue is an exception, since we take a desc-
878 * based intr on the EOSP frames. 914 * based intr on the EOSP frames.
879 */ 915 */
880 if (qtype == ATH9K_TX_QUEUE_UAPSD) 916 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
881 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE; 917 qi.tqi_qflags = TXQ_FLAG_TXOKINT_ENABLE |
882 else 918 TXQ_FLAG_TXERRINT_ENABLE;
883 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE | 919 } else {
884 TXQ_FLAG_TXDESCINT_ENABLE; 920 if (qtype == ATH9K_TX_QUEUE_UAPSD)
921 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
922 else
923 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
924 TXQ_FLAG_TXDESCINT_ENABLE;
925 }
885 qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi); 926 qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
886 if (qnum == -1) { 927 if (qnum == -1) {
887 /* 928 /*
@@ -908,6 +949,11 @@ struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
908 txq->axq_depth = 0; 949 txq->axq_depth = 0;
909 txq->axq_tx_inprogress = false; 950 txq->axq_tx_inprogress = false;
910 sc->tx.txqsetup |= 1<<qnum; 951 sc->tx.txqsetup |= 1<<qnum;
952
953 txq->txq_headidx = txq->txq_tailidx = 0;
954 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
955 INIT_LIST_HEAD(&txq->txq_fifo[i]);
956 INIT_LIST_HEAD(&txq->txq_fifo_pending);
911 } 957 }
912 return &sc->tx.txq[qnum]; 958 return &sc->tx.txq[qnum];
913} 959}
@@ -1035,36 +1081,52 @@ void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1035 struct ath_tx_status ts; 1081 struct ath_tx_status ts;
1036 1082
1037 memset(&ts, 0, sizeof(ts)); 1083 memset(&ts, 0, sizeof(ts));
1038 if (!retry_tx)
1039 ts.ts_flags = ATH9K_TX_SW_ABORTED;
1040
1041 INIT_LIST_HEAD(&bf_head); 1084 INIT_LIST_HEAD(&bf_head);
1042 1085
1043 for (;;) { 1086 for (;;) {
1044 spin_lock_bh(&txq->axq_lock); 1087 spin_lock_bh(&txq->axq_lock);
1045 1088
1046 if (list_empty(&txq->axq_q)) { 1089 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1047 txq->axq_link = NULL; 1090 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
1048 spin_unlock_bh(&txq->axq_lock); 1091 txq->txq_headidx = txq->txq_tailidx = 0;
1049 break; 1092 spin_unlock_bh(&txq->axq_lock);
1050 } 1093 break;
1051 1094 } else {
1052 bf = list_first_entry(&txq->axq_q, struct ath_buf, list); 1095 bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
1096 struct ath_buf, list);
1097 }
1098 } else {
1099 if (list_empty(&txq->axq_q)) {
1100 txq->axq_link = NULL;
1101 spin_unlock_bh(&txq->axq_lock);
1102 break;
1103 }
1104 bf = list_first_entry(&txq->axq_q, struct ath_buf,
1105 list);
1053 1106
1054 if (bf->bf_stale) { 1107 if (bf->bf_stale) {
1055 list_del(&bf->list); 1108 list_del(&bf->list);
1056 spin_unlock_bh(&txq->axq_lock); 1109 spin_unlock_bh(&txq->axq_lock);
1057 1110
1058 spin_lock_bh(&sc->tx.txbuflock); 1111 ath_tx_return_buffer(sc, bf);
1059 list_add_tail(&bf->list, &sc->tx.txbuf); 1112 continue;
1060 spin_unlock_bh(&sc->tx.txbuflock); 1113 }
1061 continue;
1062 } 1114 }
1063 1115
1064 lastbf = bf->bf_lastbf; 1116 lastbf = bf->bf_lastbf;
1117 if (!retry_tx)
1118 lastbf->bf_tx_aborted = true;
1119
1120 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1121 list_cut_position(&bf_head,
1122 &txq->txq_fifo[txq->txq_tailidx],
1123 &lastbf->list);
1124 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
1125 } else {
1126 /* remove ath_buf's of the same mpdu from txq */
1127 list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
1128 }
1065 1129
1066 /* remove ath_buf's of the same mpdu from txq */
1067 list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
1068 txq->axq_depth--; 1130 txq->axq_depth--;
1069 1131
1070 spin_unlock_bh(&txq->axq_lock); 1132 spin_unlock_bh(&txq->axq_lock);
@@ -1087,6 +1149,27 @@ void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1087 spin_unlock_bh(&txq->axq_lock); 1149 spin_unlock_bh(&txq->axq_lock);
1088 } 1150 }
1089 } 1151 }
1152
1153 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1154 spin_lock_bh(&txq->axq_lock);
1155 while (!list_empty(&txq->txq_fifo_pending)) {
1156 bf = list_first_entry(&txq->txq_fifo_pending,
1157 struct ath_buf, list);
1158 list_cut_position(&bf_head,
1159 &txq->txq_fifo_pending,
1160 &bf->bf_lastbf->list);
1161 spin_unlock_bh(&txq->axq_lock);
1162
1163 if (bf_isampdu(bf))
1164 ath_tx_complete_aggr(sc, txq, bf, &bf_head,
1165 &ts, 0);
1166 else
1167 ath_tx_complete_buf(sc, bf, txq, &bf_head,
1168 &ts, 0, 0);
1169 spin_lock_bh(&txq->axq_lock);
1170 }
1171 spin_unlock_bh(&txq->axq_lock);
1172 }
1090} 1173}
1091 1174
1092void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx) 1175void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
@@ -1224,44 +1307,47 @@ static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1224 1307
1225 bf = list_first_entry(head, struct ath_buf, list); 1308 bf = list_first_entry(head, struct ath_buf, list);
1226 1309
1227 list_splice_tail_init(head, &txq->axq_q);
1228 txq->axq_depth++;
1229
1230 ath_print(common, ATH_DBG_QUEUE, 1310 ath_print(common, ATH_DBG_QUEUE,
1231 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth); 1311 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1232 1312
1233 if (txq->axq_link == NULL) { 1313 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1314 if (txq->axq_depth >= ATH_TXFIFO_DEPTH) {
1315 list_splice_tail_init(head, &txq->txq_fifo_pending);
1316 return;
1317 }
1318 if (!list_empty(&txq->txq_fifo[txq->txq_headidx]))
1319 ath_print(common, ATH_DBG_XMIT,
1320 "Initializing tx fifo %d which "
1321 "is non-empty\n",
1322 txq->txq_headidx);
1323 INIT_LIST_HEAD(&txq->txq_fifo[txq->txq_headidx]);
1324 list_splice_init(head, &txq->txq_fifo[txq->txq_headidx]);
1325 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1234 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 1326 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1235 ath_print(common, ATH_DBG_XMIT, 1327 ath_print(common, ATH_DBG_XMIT,
1236 "TXDP[%u] = %llx (%p)\n", 1328 "TXDP[%u] = %llx (%p)\n",
1237 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc); 1329 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1238 } else { 1330 } else {
1239 *txq->axq_link = bf->bf_daddr; 1331 list_splice_tail_init(head, &txq->axq_q);
1240 ath_print(common, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n",
1241 txq->axq_qnum, txq->axq_link,
1242 ito64(bf->bf_daddr), bf->bf_desc);
1243 }
1244 txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link);
1245 ath9k_hw_txstart(ah, txq->axq_qnum);
1246}
1247
1248static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
1249{
1250 struct ath_buf *bf = NULL;
1251 1332
1252 spin_lock_bh(&sc->tx.txbuflock); 1333 if (txq->axq_link == NULL) {
1253 1334 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1254 if (unlikely(list_empty(&sc->tx.txbuf))) { 1335 ath_print(common, ATH_DBG_XMIT,
1255 spin_unlock_bh(&sc->tx.txbuflock); 1336 "TXDP[%u] = %llx (%p)\n",
1256 return NULL; 1337 txq->axq_qnum, ito64(bf->bf_daddr),
1338 bf->bf_desc);
1339 } else {
1340 *txq->axq_link = bf->bf_daddr;
1341 ath_print(common, ATH_DBG_XMIT,
1342 "link[%u] (%p)=%llx (%p)\n",
1343 txq->axq_qnum, txq->axq_link,
1344 ito64(bf->bf_daddr), bf->bf_desc);
1345 }
1346 ath9k_hw_get_desc_link(ah, bf->bf_lastbf->bf_desc,
1347 &txq->axq_link);
1348 ath9k_hw_txstart(ah, txq->axq_qnum);
1257 } 1349 }
1258 1350 txq->axq_depth++;
1259 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
1260 list_del(&bf->list);
1261
1262 spin_unlock_bh(&sc->tx.txbuflock);
1263
1264 return bf;
1265} 1351}
1266 1352
1267static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid, 1353static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
@@ -1408,8 +1494,7 @@ static void assign_aggr_tid_seqno(struct sk_buff *skb,
1408 INCR(tid->seq_next, IEEE80211_SEQ_MAX); 1494 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1409} 1495}
1410 1496
1411static int setup_tx_flags(struct ath_softc *sc, struct sk_buff *skb, 1497static int setup_tx_flags(struct sk_buff *skb, bool use_ldpc)
1412 struct ath_txq *txq)
1413{ 1498{
1414 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1499 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1415 int flags = 0; 1500 int flags = 0;
@@ -1420,6 +1505,9 @@ static int setup_tx_flags(struct ath_softc *sc, struct sk_buff *skb,
1420 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) 1505 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1421 flags |= ATH9K_TXDESC_NOACK; 1506 flags |= ATH9K_TXDESC_NOACK;
1422 1507
1508 if (use_ldpc)
1509 flags |= ATH9K_TXDESC_LDPC;
1510
1423 return flags; 1511 return flags;
1424} 1512}
1425 1513
@@ -1438,8 +1526,9 @@ static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf,
1438 pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen; 1526 pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen;
1439 1527
1440 /* find number of symbols: PLCP + data */ 1528 /* find number of symbols: PLCP + data */
1529 streams = HT_RC_2_STREAMS(rix);
1441 nbits = (pktlen << 3) + OFDM_PLCP_BITS; 1530 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1442 nsymbits = bits_per_symbol[rix][width]; 1531 nsymbits = bits_per_symbol[rix % 8][width] * streams;
1443 nsymbols = (nbits + nsymbits - 1) / nsymbits; 1532 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1444 1533
1445 if (!half_gi) 1534 if (!half_gi)
@@ -1448,7 +1537,6 @@ static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf,
1448 duration = SYMBOL_TIME_HALFGI(nsymbols); 1537 duration = SYMBOL_TIME_HALFGI(nsymbols);
1449 1538
1450 /* addup duration for legacy/ht training and signal fields */ 1539 /* addup duration for legacy/ht training and signal fields */
1451 streams = HT_RC_2_STREAMS(rix);
1452 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); 1540 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1453 1541
1454 return duration; 1542 return duration;
@@ -1519,6 +1607,8 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
1519 series[i].Rate = rix | 0x80; 1607 series[i].Rate = rix | 0x80;
1520 series[i].PktDuration = ath_pkt_duration(sc, rix, bf, 1608 series[i].PktDuration = ath_pkt_duration(sc, rix, bf,
1521 is_40, is_sgi, is_sp); 1609 is_40, is_sgi, is_sp);
1610 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1611 series[i].RateFlags |= ATH9K_RATESERIES_STBC;
1522 continue; 1612 continue;
1523 } 1613 }
1524 1614
@@ -1571,6 +1661,7 @@ static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf,
1571 int hdrlen; 1661 int hdrlen;
1572 __le16 fc; 1662 __le16 fc;
1573 int padpos, padsize; 1663 int padpos, padsize;
1664 bool use_ldpc = false;
1574 1665
1575 tx_info->pad[0] = 0; 1666 tx_info->pad[0] = 0;
1576 switch (txctl->frame_type) { 1667 switch (txctl->frame_type) {
@@ -1597,10 +1688,13 @@ static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf,
1597 bf->bf_frmlen -= padsize; 1688 bf->bf_frmlen -= padsize;
1598 } 1689 }
1599 1690
1600 if (conf_is_ht(&hw->conf)) 1691 if (conf_is_ht(&hw->conf)) {
1601 bf->bf_state.bf_type |= BUF_HT; 1692 bf->bf_state.bf_type |= BUF_HT;
1693 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1694 use_ldpc = true;
1695 }
1602 1696
1603 bf->bf_flags = setup_tx_flags(sc, skb, txctl->txq); 1697 bf->bf_flags = setup_tx_flags(skb, use_ldpc);
1604 1698
1605 bf->bf_keytype = get_hw_crypto_keytype(skb); 1699 bf->bf_keytype = get_hw_crypto_keytype(skb);
1606 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) { 1700 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) {
@@ -1659,8 +1753,7 @@ static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
1659 list_add_tail(&bf->list, &bf_head); 1753 list_add_tail(&bf->list, &bf_head);
1660 1754
1661 ds = bf->bf_desc; 1755 ds = bf->bf_desc;
1662 ds->ds_link = 0; 1756 ath9k_hw_set_desc_link(ah, ds, 0);
1663 ds->ds_data = bf->bf_buf_addr;
1664 1757
1665 ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER, 1758 ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER,
1666 bf->bf_keyix, bf->bf_keytype, bf->bf_flags); 1759 bf->bf_keyix, bf->bf_keytype, bf->bf_flags);
@@ -1669,7 +1762,9 @@ static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
1669 skb->len, /* segment length */ 1762 skb->len, /* segment length */
1670 true, /* first segment */ 1763 true, /* first segment */
1671 true, /* last segment */ 1764 true, /* last segment */
1672 ds); /* first descriptor */ 1765 ds, /* first descriptor */
1766 bf->bf_buf_addr,
1767 txctl->txq->axq_qnum);
1673 1768
1674 spin_lock_bh(&txctl->txq->axq_lock); 1769 spin_lock_bh(&txctl->txq->axq_lock);
1675 1770
@@ -1738,9 +1833,7 @@ int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1738 } 1833 }
1739 spin_unlock_bh(&txq->axq_lock); 1834 spin_unlock_bh(&txq->axq_lock);
1740 1835
1741 spin_lock_bh(&sc->tx.txbuflock); 1836 ath_tx_return_buffer(sc, bf);
1742 list_add_tail(&bf->list, &sc->tx.txbuf);
1743 spin_unlock_bh(&sc->tx.txbuflock);
1744 1837
1745 return r; 1838 return r;
1746 } 1839 }
@@ -1896,7 +1989,7 @@ static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
1896 int nbad = 0; 1989 int nbad = 0;
1897 int isaggr = 0; 1990 int isaggr = 0;
1898 1991
1899 if (ts->ts_flags == ATH9K_TX_SW_ABORTED) 1992 if (bf->bf_tx_aborted)
1900 return 0; 1993 return 0;
1901 1994
1902 isaggr = bf_isaggr(bf); 1995 isaggr = bf_isaggr(bf);
@@ -2054,13 +2147,12 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2054 txq->axq_depth--; 2147 txq->axq_depth--;
2055 txok = !(ts.ts_status & ATH9K_TXERR_MASK); 2148 txok = !(ts.ts_status & ATH9K_TXERR_MASK);
2056 txq->axq_tx_inprogress = false; 2149 txq->axq_tx_inprogress = false;
2150 if (bf_held)
2151 list_del(&bf_held->list);
2057 spin_unlock_bh(&txq->axq_lock); 2152 spin_unlock_bh(&txq->axq_lock);
2058 2153
2059 if (bf_held) { 2154 if (bf_held)
2060 spin_lock_bh(&sc->tx.txbuflock); 2155 ath_tx_return_buffer(sc, bf_held);
2061 list_move_tail(&bf_held->list, &sc->tx.txbuf);
2062 spin_unlock_bh(&sc->tx.txbuflock);
2063 }
2064 2156
2065 if (!bf_isampdu(bf)) { 2157 if (!bf_isampdu(bf)) {
2066 /* 2158 /*
@@ -2138,10 +2230,121 @@ void ath_tx_tasklet(struct ath_softc *sc)
2138 } 2230 }
2139} 2231}
2140 2232
2233void ath_tx_edma_tasklet(struct ath_softc *sc)
2234{
2235 struct ath_tx_status txs;
2236 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2237 struct ath_hw *ah = sc->sc_ah;
2238 struct ath_txq *txq;
2239 struct ath_buf *bf, *lastbf;
2240 struct list_head bf_head;
2241 int status;
2242 int txok;
2243
2244 for (;;) {
2245 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&txs);
2246 if (status == -EINPROGRESS)
2247 break;
2248 if (status == -EIO) {
2249 ath_print(common, ATH_DBG_XMIT,
2250 "Error processing tx status\n");
2251 break;
2252 }
2253
2254 /* Skip beacon completions */
2255 if (txs.qid == sc->beacon.beaconq)
2256 continue;
2257
2258 txq = &sc->tx.txq[txs.qid];
2259
2260 spin_lock_bh(&txq->axq_lock);
2261 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2262 spin_unlock_bh(&txq->axq_lock);
2263 return;
2264 }
2265
2266 bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
2267 struct ath_buf, list);
2268 lastbf = bf->bf_lastbf;
2269
2270 INIT_LIST_HEAD(&bf_head);
2271 list_cut_position(&bf_head, &txq->txq_fifo[txq->txq_tailidx],
2272 &lastbf->list);
2273 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2274 txq->axq_depth--;
2275 txq->axq_tx_inprogress = false;
2276 spin_unlock_bh(&txq->axq_lock);
2277
2278 txok = !(txs.ts_status & ATH9K_TXERR_MASK);
2279
2280 if (!bf_isampdu(bf)) {
2281 bf->bf_retries = txs.ts_longretry;
2282 if (txs.ts_status & ATH9K_TXERR_XRETRY)
2283 bf->bf_state.bf_type |= BUF_XRETRY;
2284 ath_tx_rc_status(bf, &txs, 0, txok, true);
2285 }
2286
2287 if (bf_isampdu(bf))
2288 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &txs, txok);
2289 else
2290 ath_tx_complete_buf(sc, bf, txq, &bf_head,
2291 &txs, txok, 0);
2292
2293 ath_wake_mac80211_queue(sc, txq);
2294
2295 spin_lock_bh(&txq->axq_lock);
2296 if (!list_empty(&txq->txq_fifo_pending)) {
2297 INIT_LIST_HEAD(&bf_head);
2298 bf = list_first_entry(&txq->txq_fifo_pending,
2299 struct ath_buf, list);
2300 list_cut_position(&bf_head, &txq->txq_fifo_pending,
2301 &bf->bf_lastbf->list);
2302 ath_tx_txqaddbuf(sc, txq, &bf_head);
2303 } else if (sc->sc_flags & SC_OP_TXAGGR)
2304 ath_txq_schedule(sc, txq);
2305 spin_unlock_bh(&txq->axq_lock);
2306 }
2307}
2308
2141/*****************/ 2309/*****************/
2142/* Init, Cleanup */ 2310/* Init, Cleanup */
2143/*****************/ 2311/*****************/
2144 2312
2313static int ath_txstatus_setup(struct ath_softc *sc, int size)
2314{
2315 struct ath_descdma *dd = &sc->txsdma;
2316 u8 txs_len = sc->sc_ah->caps.txs_len;
2317
2318 dd->dd_desc_len = size * txs_len;
2319 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
2320 &dd->dd_desc_paddr, GFP_KERNEL);
2321 if (!dd->dd_desc)
2322 return -ENOMEM;
2323
2324 return 0;
2325}
2326
2327static int ath_tx_edma_init(struct ath_softc *sc)
2328{
2329 int err;
2330
2331 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2332 if (!err)
2333 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2334 sc->txsdma.dd_desc_paddr,
2335 ATH_TXSTATUS_RING_SIZE);
2336
2337 return err;
2338}
2339
2340static void ath_tx_edma_cleanup(struct ath_softc *sc)
2341{
2342 struct ath_descdma *dd = &sc->txsdma;
2343
2344 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2345 dd->dd_desc_paddr);
2346}
2347
2145int ath_tx_init(struct ath_softc *sc, int nbufs) 2348int ath_tx_init(struct ath_softc *sc, int nbufs)
2146{ 2349{
2147 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2350 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
@@ -2150,7 +2353,7 @@ int ath_tx_init(struct ath_softc *sc, int nbufs)
2150 spin_lock_init(&sc->tx.txbuflock); 2353 spin_lock_init(&sc->tx.txbuflock);
2151 2354
2152 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf, 2355 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2153 "tx", nbufs, 1); 2356 "tx", nbufs, 1, 1);
2154 if (error != 0) { 2357 if (error != 0) {
2155 ath_print(common, ATH_DBG_FATAL, 2358 ath_print(common, ATH_DBG_FATAL,
2156 "Failed to allocate tx descriptors: %d\n", error); 2359 "Failed to allocate tx descriptors: %d\n", error);
@@ -2158,7 +2361,7 @@ int ath_tx_init(struct ath_softc *sc, int nbufs)
2158 } 2361 }
2159 2362
2160 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf, 2363 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2161 "beacon", ATH_BCBUF, 1); 2364 "beacon", ATH_BCBUF, 1, 1);
2162 if (error != 0) { 2365 if (error != 0) {
2163 ath_print(common, ATH_DBG_FATAL, 2366 ath_print(common, ATH_DBG_FATAL,
2164 "Failed to allocate beacon descriptors: %d\n", error); 2367 "Failed to allocate beacon descriptors: %d\n", error);
@@ -2167,6 +2370,12 @@ int ath_tx_init(struct ath_softc *sc, int nbufs)
2167 2370
2168 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work); 2371 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2169 2372
2373 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
2374 error = ath_tx_edma_init(sc);
2375 if (error)
2376 goto err;
2377 }
2378
2170err: 2379err:
2171 if (error != 0) 2380 if (error != 0)
2172 ath_tx_cleanup(sc); 2381 ath_tx_cleanup(sc);
@@ -2181,6 +2390,9 @@ void ath_tx_cleanup(struct ath_softc *sc)
2181 2390
2182 if (sc->tx.txdma.dd_desc_len != 0) 2391 if (sc->tx.txdma.dd_desc_len != 0)
2183 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf); 2392 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
2393
2394 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2395 ath_tx_edma_cleanup(sc);
2184} 2396}
2185 2397
2186void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an) 2398void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-07 03:20:48 -0500