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Diffstat (limited to 'drivers/net/wireless/ath/ath9k/reg.h')
-rw-r--r--drivers/net/wireless/ath/ath9k/reg.h15
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h
index a1499700bcf2..2a938f4feac5 100644
--- a/drivers/net/wireless/ath/ath9k/reg.h
+++ b/drivers/net/wireless/ath/ath9k/reg.h
@@ -903,6 +903,10 @@
903#define AR_SREV_9340(_ah) \ 903#define AR_SREV_9340(_ah) \
904 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9340)) 904 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9340))
905 905
906#define AR_SREV_9340_13(_ah) \
907 (AR_SREV_9340((_ah)) && \
908 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9340_13))
909
906#define AR_SREV_9340_13_OR_LATER(_ah) \ 910#define AR_SREV_9340_13_OR_LATER(_ah) \
907 (AR_SREV_9340((_ah)) && \ 911 (AR_SREV_9340((_ah)) && \
908 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9340_13)) 912 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9340_13))
@@ -1240,12 +1244,23 @@ enum {
1240#define AR_CH0_DPLL3_PHASE_SHIFT_S 23 1244#define AR_CH0_DPLL3_PHASE_SHIFT_S 23
1241#define AR_PHY_CCA_NOM_VAL_2GHZ -118 1245#define AR_PHY_CCA_NOM_VAL_2GHZ -118
1242 1246
1247#define AR_RTC_9300_SOC_PLL_DIV_INT 0x0000003f
1248#define AR_RTC_9300_SOC_PLL_DIV_INT_S 0
1249#define AR_RTC_9300_SOC_PLL_DIV_FRAC 0x000fffc0
1250#define AR_RTC_9300_SOC_PLL_DIV_FRAC_S 6
1251#define AR_RTC_9300_SOC_PLL_REFDIV 0x01f00000
1252#define AR_RTC_9300_SOC_PLL_REFDIV_S 20
1253#define AR_RTC_9300_SOC_PLL_CLKSEL 0x06000000
1254#define AR_RTC_9300_SOC_PLL_CLKSEL_S 25
1255#define AR_RTC_9300_SOC_PLL_BYPASS 0x08000000
1256
1243#define AR_RTC_9300_PLL_DIV 0x000003ff 1257#define AR_RTC_9300_PLL_DIV 0x000003ff
1244#define AR_RTC_9300_PLL_DIV_S 0 1258#define AR_RTC_9300_PLL_DIV_S 0
1245#define AR_RTC_9300_PLL_REFDIV 0x00003C00 1259#define AR_RTC_9300_PLL_REFDIV 0x00003C00
1246#define AR_RTC_9300_PLL_REFDIV_S 10 1260#define AR_RTC_9300_PLL_REFDIV_S 10
1247#define AR_RTC_9300_PLL_CLKSEL 0x0000C000 1261#define AR_RTC_9300_PLL_CLKSEL 0x0000C000
1248#define AR_RTC_9300_PLL_CLKSEL_S 14 1262#define AR_RTC_9300_PLL_CLKSEL_S 14
1263#define AR_RTC_9300_PLL_BYPASS 0x00010000
1249 1264
1250#define AR_RTC_9160_PLL_DIV 0x000003ff 1265#define AR_RTC_9160_PLL_DIV 0x000003ff
1251#define AR_RTC_9160_PLL_DIV_S 0 1266#define AR_RTC_9160_PLL_DIV_S 0