diff options
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/reg.h')
-rw-r--r-- | drivers/net/wireless/ath/ath9k/reg.h | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h index 1d8e0a8b587c..3ddb243f0000 100644 --- a/drivers/net/wireless/ath/ath9k/reg.h +++ b/drivers/net/wireless/ath/ath9k/reg.h | |||
@@ -970,6 +970,8 @@ enum { | |||
970 | #define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF_S 7 | 970 | #define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF_S 7 |
971 | #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB 0x00001000 | 971 | #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB 0x00001000 |
972 | #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB_S 12 | 972 | #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB_S 12 |
973 | #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB 0x00001000 | ||
974 | #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB_S 1 | ||
973 | #define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB 0x00008000 | 975 | #define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB 0x00008000 |
974 | #define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB_S 15 | 976 | #define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB_S 15 |
975 | #define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000 | 977 | #define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000 |
@@ -978,6 +980,8 @@ enum { | |||
978 | #define AR_GPIO_INPUT_MUX1 0x4058 | 980 | #define AR_GPIO_INPUT_MUX1 0x4058 |
979 | #define AR_GPIO_INPUT_MUX1_BT_ACTIVE 0x000f0000 | 981 | #define AR_GPIO_INPUT_MUX1_BT_ACTIVE 0x000f0000 |
980 | #define AR_GPIO_INPUT_MUX1_BT_ACTIVE_S 16 | 982 | #define AR_GPIO_INPUT_MUX1_BT_ACTIVE_S 16 |
983 | #define AR_GPIO_INPUT_MUX1_BT_PRIORITY 0x00000f00 | ||
984 | #define AR_GPIO_INPUT_MUX1_BT_PRIORITY_S 8 | ||
981 | 985 | ||
982 | #define AR_GPIO_INPUT_MUX2 0x405c | 986 | #define AR_GPIO_INPUT_MUX2 0x405c |
983 | #define AR_GPIO_INPUT_MUX2_CLK25 0x0000000f | 987 | #define AR_GPIO_INPUT_MUX2_CLK25 0x0000000f |
@@ -1003,6 +1007,8 @@ enum { | |||
1003 | 1007 | ||
1004 | #define AR_OBS 0x4080 | 1008 | #define AR_OBS 0x4080 |
1005 | 1009 | ||
1010 | #define AR_GPIO_PDPU 0x4088 | ||
1011 | |||
1006 | #define AR_PCIE_MSI 0x4094 | 1012 | #define AR_PCIE_MSI 0x4094 |
1007 | #define AR_PCIE_MSI_ENABLE 0x00000001 | 1013 | #define AR_PCIE_MSI_ENABLE 0x00000001 |
1008 | 1014 | ||
@@ -1436,6 +1442,7 @@ enum { | |||
1436 | #define AR_QUIET1_NEXT_QUIET_M 0x0000ffff | 1442 | #define AR_QUIET1_NEXT_QUIET_M 0x0000ffff |
1437 | #define AR_QUIET1_QUIET_ENABLE 0x00010000 | 1443 | #define AR_QUIET1_QUIET_ENABLE 0x00010000 |
1438 | #define AR_QUIET1_QUIET_ACK_CTS_ENABLE 0x00020000 | 1444 | #define AR_QUIET1_QUIET_ACK_CTS_ENABLE 0x00020000 |
1445 | #define AR_QUIET1_QUIET_ACK_CTS_ENABLE_S 17 | ||
1439 | #define AR_QUIET2 0x8100 | 1446 | #define AR_QUIET2 0x8100 |
1440 | #define AR_QUIET2_QUIET_PERIOD_S 0 | 1447 | #define AR_QUIET2_QUIET_PERIOD_S 0 |
1441 | #define AR_QUIET2_QUIET_PERIOD_M 0x0000ffff | 1448 | #define AR_QUIET2_QUIET_PERIOD_M 0x0000ffff |
@@ -1481,6 +1488,8 @@ enum { | |||
1481 | #define AR_PCU_CLEAR_VMF 0x01000000 | 1488 | #define AR_PCU_CLEAR_VMF 0x01000000 |
1482 | #define AR_PCU_CLEAR_BA_VALID 0x04000000 | 1489 | #define AR_PCU_CLEAR_BA_VALID 0x04000000 |
1483 | 1490 | ||
1491 | #define AR_PCU_BT_ANT_PREVENT_RX 0x00100000 | ||
1492 | #define AR_PCU_BT_ANT_PREVENT_RX_S 20 | ||
1484 | 1493 | ||
1485 | #define AR_FILT_OFDM 0x8124 | 1494 | #define AR_FILT_OFDM 0x8124 |
1486 | #define AR_FILT_OFDM_COUNT 0x00FFFFFF | 1495 | #define AR_FILT_OFDM_COUNT 0x00FFFFFF |
@@ -1508,6 +1517,46 @@ enum { | |||
1508 | #define AR_PHY_ERR_3_COUNT 0x00FFFFFF | 1517 | #define AR_PHY_ERR_3_COUNT 0x00FFFFFF |
1509 | #define AR_PHY_ERR_MASK_3 0x816c | 1518 | #define AR_PHY_ERR_MASK_3 0x816c |
1510 | 1519 | ||
1520 | #define AR_BT_COEX_MODE 0x8170 | ||
1521 | #define AR_BT_TIME_EXTEND 0x000000ff | ||
1522 | #define AR_BT_TIME_EXTEND_S 0 | ||
1523 | #define AR_BT_TXSTATE_EXTEND 0x00000100 | ||
1524 | #define AR_BT_TXSTATE_EXTEND_S 8 | ||
1525 | #define AR_BT_TX_FRAME_EXTEND 0x00000200 | ||
1526 | #define AR_BT_TX_FRAME_EXTEND_S 9 | ||
1527 | #define AR_BT_MODE 0x00000c00 | ||
1528 | #define AR_BT_MODE_S 10 | ||
1529 | #define AR_BT_QUIET 0x00001000 | ||
1530 | #define AR_BT_QUIET_S 12 | ||
1531 | #define AR_BT_QCU_THRESH 0x0001e000 | ||
1532 | #define AR_BT_QCU_THRESH_S 13 | ||
1533 | #define AR_BT_RX_CLEAR_POLARITY 0x00020000 | ||
1534 | #define AR_BT_RX_CLEAR_POLARITY_S 17 | ||
1535 | #define AR_BT_PRIORITY_TIME 0x00fc0000 | ||
1536 | #define AR_BT_PRIORITY_TIME_S 18 | ||
1537 | #define AR_BT_FIRST_SLOT_TIME 0xff000000 | ||
1538 | #define AR_BT_FIRST_SLOT_TIME_S 24 | ||
1539 | |||
1540 | #define AR_BT_COEX_WEIGHT 0x8174 | ||
1541 | #define AR_BT_COEX_WGHT 0xff55 | ||
1542 | #define AR_STOMP_ALL_WLAN_WGHT 0xffcc | ||
1543 | #define AR_STOMP_LOW_WLAN_WGHT 0xaaa8 | ||
1544 | #define AR_STOMP_NONE_WLAN_WGHT 0xaa00 | ||
1545 | #define AR_BTCOEX_BT_WGHT 0x0000ffff | ||
1546 | #define AR_BTCOEX_BT_WGHT_S 0 | ||
1547 | #define AR_BTCOEX_WL_WGHT 0xffff0000 | ||
1548 | #define AR_BTCOEX_WL_WGHT_S 16 | ||
1549 | |||
1550 | #define AR_BT_COEX_MODE2 0x817c | ||
1551 | #define AR_BT_BCN_MISS_THRESH 0x000000ff | ||
1552 | #define AR_BT_BCN_MISS_THRESH_S 0 | ||
1553 | #define AR_BT_BCN_MISS_CNT 0x0000ff00 | ||
1554 | #define AR_BT_BCN_MISS_CNT_S 8 | ||
1555 | #define AR_BT_HOLD_RX_CLEAR 0x00010000 | ||
1556 | #define AR_BT_HOLD_RX_CLEAR_S 16 | ||
1557 | #define AR_BT_DISABLE_BT_ANT 0x00100000 | ||
1558 | #define AR_BT_DISABLE_BT_ANT_S 20 | ||
1559 | |||
1511 | #define AR_TXSIFS 0x81d0 | 1560 | #define AR_TXSIFS 0x81d0 |
1512 | #define AR_TXSIFS_TIME 0x000000FF | 1561 | #define AR_TXSIFS_TIME 0x000000FF |
1513 | #define AR_TXSIFS_TX_LATENCY 0x00000F00 | 1562 | #define AR_TXSIFS_TX_LATENCY 0x00000F00 |