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path: root/drivers/net/wireless/ath/ath9k/reg.h
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Diffstat (limited to 'drivers/net/wireless/ath/ath9k/reg.h')
-rw-r--r--drivers/net/wireless/ath/ath9k/reg.h99
1 files changed, 68 insertions, 31 deletions
diff --git a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h
index 6acbf0e2240b..456f3ec20fef 100644
--- a/drivers/net/wireless/ath/ath9k/reg.h
+++ b/drivers/net/wireless/ath/ath9k/reg.h
@@ -693,7 +693,7 @@
693#define AR_RC_APB 0x00000002 693#define AR_RC_APB 0x00000002
694#define AR_RC_HOSTIF 0x00000100 694#define AR_RC_HOSTIF 0x00000100
695 695
696#define AR_WA 0x4004 696#define AR_WA (AR_SREV_9340(ah) ? 0x40c4 : 0x4004)
697#define AR_WA_BIT6 (1 << 6) 697#define AR_WA_BIT6 (1 << 6)
698#define AR_WA_BIT7 (1 << 7) 698#define AR_WA_BIT7 (1 << 7)
699#define AR_WA_BIT23 (1 << 23) 699#define AR_WA_BIT23 (1 << 23)
@@ -712,7 +712,7 @@
712#define AR_PM_STATE 0x4008 712#define AR_PM_STATE 0x4008
713#define AR_PM_STATE_PME_D3COLD_VAUX 0x00100000 713#define AR_PM_STATE_PME_D3COLD_VAUX 0x00100000
714 714
715#define AR_HOST_TIMEOUT 0x4018 715#define AR_HOST_TIMEOUT (AR_SREV_9340(ah) ? 0x4008 : 0x4018)
716#define AR_HOST_TIMEOUT_APB_CNTR 0x0000FFFF 716#define AR_HOST_TIMEOUT_APB_CNTR 0x0000FFFF
717#define AR_HOST_TIMEOUT_APB_CNTR_S 0 717#define AR_HOST_TIMEOUT_APB_CNTR_S 0
718#define AR_HOST_TIMEOUT_LCL_CNTR 0xFFFF0000 718#define AR_HOST_TIMEOUT_LCL_CNTR 0xFFFF0000
@@ -742,7 +742,8 @@
742#define EEPROM_PROTECT_WP_1024_2047 0x8000 742#define EEPROM_PROTECT_WP_1024_2047 0x8000
743 743
744#define AR_SREV \ 744#define AR_SREV \
745 ((AR_SREV_9100(ah)) ? 0x0600 : 0x4020) 745 ((AR_SREV_9100(ah)) ? 0x0600 : (AR_SREV_9340(ah) \
746 ? 0x400c : 0x4020))
746 747
747#define AR_SREV_ID \ 748#define AR_SREV_ID \
748 ((AR_SREV_9100(ah)) ? 0x00000FFF : 0x000000FF) 749 ((AR_SREV_9100(ah)) ? 0x00000FFF : 0x000000FF)
@@ -790,6 +791,7 @@
790#define AR_SREV_VERSION_9485 0x240 791#define AR_SREV_VERSION_9485 0x240
791#define AR_SREV_REVISION_9485_10 0 792#define AR_SREV_REVISION_9485_10 0
792#define AR_SREV_REVISION_9485_11 1 793#define AR_SREV_REVISION_9485_11 1
794#define AR_SREV_VERSION_9340 0x300
793 795
794#define AR_SREV_5416(_ah) \ 796#define AR_SREV_5416(_ah) \
795 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \ 797 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \
@@ -868,6 +870,11 @@
868#define AR_SREV_9485_11(_ah) \ 870#define AR_SREV_9485_11(_ah) \
869 (AR_SREV_9485(_ah) && \ 871 (AR_SREV_9485(_ah) && \
870 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9485_11)) 872 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9485_11))
873#define AR_SREV_9485_OR_LATER(_ah) \
874 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9485))
875
876#define AR_SREV_9340(_ah) \
877 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9340))
871 878
872#define AR_SREV_9285E_20(_ah) \ 879#define AR_SREV_9285E_20(_ah) \
873 (AR_SREV_9285_12_OR_LATER(_ah) && \ 880 (AR_SREV_9285_12_OR_LATER(_ah) && \
@@ -910,11 +917,11 @@ enum ath_usb_dev {
910#define AR_INTR_SPURIOUS 0xFFFFFFFF 917#define AR_INTR_SPURIOUS 0xFFFFFFFF
911 918
912 919
913#define AR_INTR_SYNC_CAUSE_CLR 0x4028 920#define AR_INTR_SYNC_CAUSE (AR_SREV_9340(ah) ? 0x4010 : 0x4028)
921#define AR_INTR_SYNC_CAUSE_CLR (AR_SREV_9340(ah) ? 0x4010 : 0x4028)
914 922
915#define AR_INTR_SYNC_CAUSE 0x4028
916 923
917#define AR_INTR_SYNC_ENABLE 0x402c 924#define AR_INTR_SYNC_ENABLE (AR_SREV_9340(ah) ? 0x4014 : 0x402c)
918#define AR_INTR_SYNC_ENABLE_GPIO 0xFFFC0000 925#define AR_INTR_SYNC_ENABLE_GPIO 0xFFFC0000
919#define AR_INTR_SYNC_ENABLE_GPIO_S 18 926#define AR_INTR_SYNC_ENABLE_GPIO_S 18
920 927
@@ -954,24 +961,24 @@ enum {
954 961
955}; 962};
956 963
957#define AR_INTR_ASYNC_MASK 0x4030 964#define AR_INTR_ASYNC_MASK (AR_SREV_9340(ah) ? 0x4018 : 0x4030)
958#define AR_INTR_ASYNC_MASK_GPIO 0xFFFC0000 965#define AR_INTR_ASYNC_MASK_GPIO 0xFFFC0000
959#define AR_INTR_ASYNC_MASK_GPIO_S 18 966#define AR_INTR_ASYNC_MASK_GPIO_S 18
960 967
961#define AR_INTR_SYNC_MASK 0x4034 968#define AR_INTR_SYNC_MASK (AR_SREV_9340(ah) ? 0x401c : 0x4034)
962#define AR_INTR_SYNC_MASK_GPIO 0xFFFC0000 969#define AR_INTR_SYNC_MASK_GPIO 0xFFFC0000
963#define AR_INTR_SYNC_MASK_GPIO_S 18 970#define AR_INTR_SYNC_MASK_GPIO_S 18
964 971
965#define AR_INTR_ASYNC_CAUSE_CLR 0x4038 972#define AR_INTR_ASYNC_CAUSE_CLR (AR_SREV_9340(ah) ? 0x4020 : 0x4038)
966#define AR_INTR_ASYNC_CAUSE 0x4038 973#define AR_INTR_ASYNC_CAUSE (AR_SREV_9340(ah) ? 0x4020 : 0x4038)
967 974
968#define AR_INTR_ASYNC_ENABLE 0x403c 975#define AR_INTR_ASYNC_ENABLE (AR_SREV_9340(ah) ? 0x4024 : 0x403c)
969#define AR_INTR_ASYNC_ENABLE_GPIO 0xFFFC0000 976#define AR_INTR_ASYNC_ENABLE_GPIO 0xFFFC0000
970#define AR_INTR_ASYNC_ENABLE_GPIO_S 18 977#define AR_INTR_ASYNC_ENABLE_GPIO_S 18
971 978
972#define AR_PCIE_SERDES 0x4040 979#define AR_PCIE_SERDES 0x4040
973#define AR_PCIE_SERDES2 0x4044 980#define AR_PCIE_SERDES2 0x4044
974#define AR_PCIE_PM_CTRL 0x4014 981#define AR_PCIE_PM_CTRL (AR_SREV_9340(ah) ? 0x4004 : 0x4014)
975#define AR_PCIE_PM_CTRL_ENA 0x00080000 982#define AR_PCIE_PM_CTRL_ENA 0x00080000
976 983
977#define AR_NUM_GPIO 14 984#define AR_NUM_GPIO 14
@@ -982,7 +989,7 @@ enum {
982#define AR9300_NUM_GPIO 17 989#define AR9300_NUM_GPIO 17
983#define AR7010_NUM_GPIO 16 990#define AR7010_NUM_GPIO 16
984 991
985#define AR_GPIO_IN_OUT 0x4048 992#define AR_GPIO_IN_OUT (AR_SREV_9340(ah) ? 0x4028 : 0x4048)
986#define AR_GPIO_IN_VAL 0x0FFFC000 993#define AR_GPIO_IN_VAL 0x0FFFC000
987#define AR_GPIO_IN_VAL_S 14 994#define AR_GPIO_IN_VAL_S 14
988#define AR928X_GPIO_IN_VAL 0x000FFC00 995#define AR928X_GPIO_IN_VAL 0x000FFC00
@@ -996,11 +1003,12 @@ enum {
996#define AR7010_GPIO_IN_VAL 0x0000FFFF 1003#define AR7010_GPIO_IN_VAL 0x0000FFFF
997#define AR7010_GPIO_IN_VAL_S 0 1004#define AR7010_GPIO_IN_VAL_S 0
998 1005
999#define AR_GPIO_IN 0x404c 1006#define AR_GPIO_IN (AR_SREV_9340(ah) ? 0x402c : 0x404c)
1000#define AR9300_GPIO_IN_VAL 0x0001FFFF 1007#define AR9300_GPIO_IN_VAL 0x0001FFFF
1001#define AR9300_GPIO_IN_VAL_S 0 1008#define AR9300_GPIO_IN_VAL_S 0
1002 1009
1003#define AR_GPIO_OE_OUT (AR_SREV_9300_20_OR_LATER(ah) ? 0x4050 : 0x404c) 1010#define AR_GPIO_OE_OUT (AR_SREV_9340(ah) ? 0x4030 : \
1011 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4050 : 0x404c))
1004#define AR_GPIO_OE_OUT_DRV 0x3 1012#define AR_GPIO_OE_OUT_DRV 0x3
1005#define AR_GPIO_OE_OUT_DRV_NO 0x0 1013#define AR_GPIO_OE_OUT_DRV_NO 0x0
1006#define AR_GPIO_OE_OUT_DRV_LOW 0x1 1014#define AR_GPIO_OE_OUT_DRV_LOW 0x1
@@ -1022,11 +1030,13 @@ enum {
1022#define AR7010_GPIO_INT_MASK 0x52024 1030#define AR7010_GPIO_INT_MASK 0x52024
1023#define AR7010_GPIO_FUNCTION 0x52028 1031#define AR7010_GPIO_FUNCTION 0x52028
1024 1032
1025#define AR_GPIO_INTR_POL (AR_SREV_9300_20_OR_LATER(ah) ? 0x4058 : 0x4050) 1033#define AR_GPIO_INTR_POL (AR_SREV_9340(ah) ? 0x4038 : \
1034 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4058 : 0x4050))
1026#define AR_GPIO_INTR_POL_VAL 0x0001FFFF 1035#define AR_GPIO_INTR_POL_VAL 0x0001FFFF
1027#define AR_GPIO_INTR_POL_VAL_S 0 1036#define AR_GPIO_INTR_POL_VAL_S 0
1028 1037
1029#define AR_GPIO_INPUT_EN_VAL (AR_SREV_9300_20_OR_LATER(ah) ? 0x405c : 0x4054) 1038#define AR_GPIO_INPUT_EN_VAL (AR_SREV_9340(ah) ? 0x403c : \
1039 (AR_SREV_9300_20_OR_LATER(ah) ? 0x405c : 0x4054))
1030#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF 0x00000004 1040#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF 0x00000004
1031#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_S 2 1041#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_S 2
1032#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF 0x00000008 1042#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF 0x00000008
@@ -1044,13 +1054,15 @@ enum {
1044#define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000 1054#define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000
1045#define AR_GPIO_JTAG_DISABLE 0x00020000 1055#define AR_GPIO_JTAG_DISABLE 0x00020000
1046 1056
1047#define AR_GPIO_INPUT_MUX1 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4060 : 0x4058) 1057#define AR_GPIO_INPUT_MUX1 (AR_SREV_9340(ah) ? 0x4040 : \
1058 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4060 : 0x4058))
1048#define AR_GPIO_INPUT_MUX1_BT_ACTIVE 0x000f0000 1059#define AR_GPIO_INPUT_MUX1_BT_ACTIVE 0x000f0000
1049#define AR_GPIO_INPUT_MUX1_BT_ACTIVE_S 16 1060#define AR_GPIO_INPUT_MUX1_BT_ACTIVE_S 16
1050#define AR_GPIO_INPUT_MUX1_BT_PRIORITY 0x00000f00 1061#define AR_GPIO_INPUT_MUX1_BT_PRIORITY 0x00000f00
1051#define AR_GPIO_INPUT_MUX1_BT_PRIORITY_S 8 1062#define AR_GPIO_INPUT_MUX1_BT_PRIORITY_S 8
1052 1063
1053#define AR_GPIO_INPUT_MUX2 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4064 : 0x405c) 1064#define AR_GPIO_INPUT_MUX2 (AR_SREV_9340(ah) ? 0x4044 : \
1065 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4064 : 0x405c))
1054#define AR_GPIO_INPUT_MUX2_CLK25 0x0000000f 1066#define AR_GPIO_INPUT_MUX2_CLK25 0x0000000f
1055#define AR_GPIO_INPUT_MUX2_CLK25_S 0 1067#define AR_GPIO_INPUT_MUX2_CLK25_S 0
1056#define AR_GPIO_INPUT_MUX2_RFSILENT 0x000000f0 1068#define AR_GPIO_INPUT_MUX2_RFSILENT 0x000000f0
@@ -1058,13 +1070,18 @@ enum {
1058#define AR_GPIO_INPUT_MUX2_RTC_RESET 0x00000f00 1070#define AR_GPIO_INPUT_MUX2_RTC_RESET 0x00000f00
1059#define AR_GPIO_INPUT_MUX2_RTC_RESET_S 8 1071#define AR_GPIO_INPUT_MUX2_RTC_RESET_S 8
1060 1072
1061#define AR_GPIO_OUTPUT_MUX1 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4068 : 0x4060) 1073#define AR_GPIO_OUTPUT_MUX1 (AR_SREV_9340(ah) ? 0x4048 : \
1062#define AR_GPIO_OUTPUT_MUX2 (AR_SREV_9300_20_OR_LATER(ah) ? 0x406c : 0x4064) 1074 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4068 : 0x4060))
1063#define AR_GPIO_OUTPUT_MUX3 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4070 : 0x4068) 1075#define AR_GPIO_OUTPUT_MUX2 (AR_SREV_9340(ah) ? 0x404c : \
1076 (AR_SREV_9300_20_OR_LATER(ah) ? 0x406c : 0x4064))
1077#define AR_GPIO_OUTPUT_MUX3 (AR_SREV_9340(ah) ? 0x4050 : \
1078 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4070 : 0x4068))
1064 1079
1065#define AR_INPUT_STATE (AR_SREV_9300_20_OR_LATER(ah) ? 0x4074 : 0x406c) 1080#define AR_INPUT_STATE (AR_SREV_9340(ah) ? 0x4054 : \
1081 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4074 : 0x406c))
1066 1082
1067#define AR_EEPROM_STATUS_DATA (AR_SREV_9300_20_OR_LATER(ah) ? 0x4084 : 0x407c) 1083#define AR_EEPROM_STATUS_DATA (AR_SREV_9340(ah) ? 0x40c8 : \
1084 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4084 : 0x407c))
1068#define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff 1085#define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff
1069#define AR_EEPROM_STATUS_DATA_VAL_S 0 1086#define AR_EEPROM_STATUS_DATA_VAL_S 0
1070#define AR_EEPROM_STATUS_DATA_BUSY 0x00010000 1087#define AR_EEPROM_STATUS_DATA_BUSY 0x00010000
@@ -1072,17 +1089,19 @@ enum {
1072#define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000 1089#define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000
1073#define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000 1090#define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000
1074 1091
1075#define AR_OBS (AR_SREV_9300_20_OR_LATER(ah) ? 0x4088 : 0x4080) 1092#define AR_OBS (AR_SREV_9340(ah) ? 0x405c : \
1093 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4088 : 0x4080))
1076 1094
1077#define AR_GPIO_PDPU (AR_SREV_9300_20_OR_LATER(ah) ? 0x4090 : 0x4088) 1095#define AR_GPIO_PDPU (AR_SREV_9300_20_OR_LATER(ah) ? 0x4090 : 0x4088)
1078 1096
1079#define AR_PCIE_MSI (AR_SREV_9300_20_OR_LATER(ah) ? 0x40a4 : 0x4094) 1097#define AR_PCIE_MSI (AR_SREV_9340(ah) ? 0x40d8 : \
1098 (AR_SREV_9300_20_OR_LATER(ah) ? 0x40a4 : 0x4094))
1080#define AR_PCIE_MSI_ENABLE 0x00000001 1099#define AR_PCIE_MSI_ENABLE 0x00000001
1081 1100
1082#define AR_INTR_PRIO_SYNC_ENABLE 0x40c4 1101#define AR_INTR_PRIO_SYNC_ENABLE (AR_SREV_9340(ah) ? 0x4088 : 0x40c4)
1083#define AR_INTR_PRIO_ASYNC_MASK 0x40c8 1102#define AR_INTR_PRIO_ASYNC_MASK (AR_SREV_9340(ah) ? 0x408c : 0x40c8)
1084#define AR_INTR_PRIO_SYNC_MASK 0x40cc 1103#define AR_INTR_PRIO_SYNC_MASK (AR_SREV_9340(ah) ? 0x4090 : 0x40cc)
1085#define AR_INTR_PRIO_ASYNC_ENABLE 0x40d4 1104#define AR_INTR_PRIO_ASYNC_ENABLE (AR_SREV_9340(ah) ? 0x4094 : 0x40d4)
1086#define AR_ENT_OTP 0x40d8 1105#define AR_ENT_OTP 0x40d8
1087#define AR_ENT_OTP_CHAIN2_DISABLE 0x00020000 1106#define AR_ENT_OTP_CHAIN2_DISABLE 0x00020000
1088#define AR_ENT_OTP_MPSD 0x00800000 1107#define AR_ENT_OTP_MPSD 0x00800000
@@ -1163,6 +1182,7 @@ enum {
1163#define AR_RTC_PLL_REFDIV_5 0x000000c0 1182#define AR_RTC_PLL_REFDIV_5 0x000000c0
1164#define AR_RTC_PLL_CLKSEL 0x00000300 1183#define AR_RTC_PLL_CLKSEL 0x00000300
1165#define AR_RTC_PLL_CLKSEL_S 8 1184#define AR_RTC_PLL_CLKSEL_S 8
1185#define AR_RTC_PLL_BYPASS 0x00010000
1166 1186
1167#define PLL3 0x16188 1187#define PLL3 0x16188
1168#define PLL3_DO_MEAS_MASK 0x40000000 1188#define PLL3_DO_MEAS_MASK 0x40000000
@@ -1209,7 +1229,8 @@ enum {
1209 1229
1210/* RTC_DERIVED_* - only for AR9100 */ 1230/* RTC_DERIVED_* - only for AR9100 */
1211 1231
1212#define AR_RTC_DERIVED_CLK (AR_RTC_BASE + 0x0038) 1232#define AR_RTC_DERIVED_CLK \
1233 (AR_SREV_9100(ah) ? (AR_RTC_BASE + 0x0038) : 0x7038)
1213#define AR_RTC_DERIVED_CLK_PERIOD 0x0000fffe 1234#define AR_RTC_DERIVED_CLK_PERIOD 0x0000fffe
1214#define AR_RTC_DERIVED_CLK_PERIOD_S 1 1235#define AR_RTC_DERIVED_CLK_PERIOD_S 1
1215 1236
@@ -1688,6 +1709,22 @@ enum {
1688#define AR_BTCOEX_WL_WGHT 0xffff0000 1709#define AR_BTCOEX_WL_WGHT 0xffff0000
1689#define AR_BTCOEX_WL_WGHT_S 16 1710#define AR_BTCOEX_WL_WGHT_S 16
1690 1711
1712#define AR_BT_COEX_WL_WEIGHTS0 0x8174
1713#define AR_BT_COEX_WL_WEIGHTS1 0x81c4
1714
1715#define AR_BT_COEX_BT_WEIGHTS0 0x83ac
1716#define AR_BT_COEX_BT_WEIGHTS1 0x83b0
1717#define AR_BT_COEX_BT_WEIGHTS2 0x83b4
1718#define AR_BT_COEX_BT_WEIGHTS3 0x83b8
1719
1720#define AR9300_BT_WGHT 0xcccc4444
1721#define AR9300_STOMP_ALL_WLAN_WGHT0 0xfffffff0
1722#define AR9300_STOMP_ALL_WLAN_WGHT1 0xfffffff0
1723#define AR9300_STOMP_LOW_WLAN_WGHT0 0x88888880
1724#define AR9300_STOMP_LOW_WLAN_WGHT1 0x88888880
1725#define AR9300_STOMP_NONE_WLAN_WGHT0 0x00000000
1726#define AR9300_STOMP_NONE_WLAN_WGHT1 0x00000000
1727
1691#define AR_BT_COEX_MODE2 0x817c 1728#define AR_BT_COEX_MODE2 0x817c
1692#define AR_BT_BCN_MISS_THRESH 0x000000ff 1729#define AR_BT_BCN_MISS_THRESH 0x000000ff
1693#define AR_BT_BCN_MISS_THRESH_S 0 1730#define AR_BT_BCN_MISS_THRESH_S 0
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-05 16:36:47 -0500