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path: root/drivers/net/wireless/ath/ath9k/mac.h
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Diffstat (limited to 'drivers/net/wireless/ath/ath9k/mac.h')
-rw-r--r--drivers/net/wireless/ath/ath9k/mac.h67
1 files changed, 30 insertions, 37 deletions
diff --git a/drivers/net/wireless/ath/ath9k/mac.h b/drivers/net/wireless/ath/ath9k/mac.h
index 68dbd7a8ddca..00f3e0c7528a 100644
--- a/drivers/net/wireless/ath/ath9k/mac.h
+++ b/drivers/net/wireless/ath/ath9k/mac.h
@@ -37,6 +37,8 @@
37 AR_2040_##_index : 0) \ 37 AR_2040_##_index : 0) \
38 |((_series)[_index].RateFlags & ATH9K_RATESERIES_HALFGI ? \ 38 |((_series)[_index].RateFlags & ATH9K_RATESERIES_HALFGI ? \
39 AR_GI##_index : 0) \ 39 AR_GI##_index : 0) \
40 |((_series)[_index].RateFlags & ATH9K_RATESERIES_STBC ? \
41 AR_STBC##_index : 0) \
40 |SM((_series)[_index].ChSel, AR_ChainSel##_index)) 42 |SM((_series)[_index].ChSel, AR_ChainSel##_index))
41 43
42#define CCK_SIFS_TIME 10 44#define CCK_SIFS_TIME 10
@@ -86,7 +88,6 @@
86#define ATH9K_TX_DESC_CFG_ERR 0x04 88#define ATH9K_TX_DESC_CFG_ERR 0x04
87#define ATH9K_TX_DATA_UNDERRUN 0x08 89#define ATH9K_TX_DATA_UNDERRUN 0x08
88#define ATH9K_TX_DELIM_UNDERRUN 0x10 90#define ATH9K_TX_DELIM_UNDERRUN 0x10
89#define ATH9K_TX_SW_ABORTED 0x40
90#define ATH9K_TX_SW_FILTERED 0x80 91#define ATH9K_TX_SW_FILTERED 0x80
91 92
92/* 64 bytes */ 93/* 64 bytes */
@@ -117,7 +118,10 @@ struct ath_tx_status {
117 int8_t ts_rssi_ext0; 118 int8_t ts_rssi_ext0;
118 int8_t ts_rssi_ext1; 119 int8_t ts_rssi_ext1;
119 int8_t ts_rssi_ext2; 120 int8_t ts_rssi_ext2;
120 u8 pad[3]; 121 u8 qid;
122 u16 desc_id;
123 u8 tid;
124 u8 pad[2];
121 u32 ba_low; 125 u32 ba_low;
122 u32 ba_high; 126 u32 ba_high;
123 u32 evm0; 127 u32 evm0;
@@ -148,11 +152,13 @@ struct ath_rx_status {
148 u32 evm0; 152 u32 evm0;
149 u32 evm1; 153 u32 evm1;
150 u32 evm2; 154 u32 evm2;
155 u32 evm3;
156 u32 evm4;
151}; 157};
152 158
153struct ath_htc_rx_status { 159struct ath_htc_rx_status {
154 u64 rs_tstamp; 160 __be64 rs_tstamp;
155 u16 rs_datalen; 161 __be16 rs_datalen;
156 u8 rs_status; 162 u8 rs_status;
157 u8 rs_phyerr; 163 u8 rs_phyerr;
158 int8_t rs_rssi; 164 int8_t rs_rssi;
@@ -171,9 +177,9 @@ struct ath_htc_rx_status {
171 u8 rs_num_delims; 177 u8 rs_num_delims;
172 u8 rs_flags; 178 u8 rs_flags;
173 u8 rs_dummy; 179 u8 rs_dummy;
174 u32 evm0; 180 __be32 evm0;
175 u32 evm1; 181 __be32 evm1;
176 u32 evm2; 182 __be32 evm2;
177}; 183};
178 184
179#define ATH9K_RXERR_CRC 0x01 185#define ATH9K_RXERR_CRC 0x01
@@ -259,7 +265,8 @@ struct ath_desc {
259#define ATH9K_TXDESC_EXT_AND_CTL 0x0080 265#define ATH9K_TXDESC_EXT_AND_CTL 0x0080
260#define ATH9K_TXDESC_VMF 0x0100 266#define ATH9K_TXDESC_VMF 0x0100
261#define ATH9K_TXDESC_FRAG_IS_ON 0x0200 267#define ATH9K_TXDESC_FRAG_IS_ON 0x0200
262#define ATH9K_TXDESC_CAB 0x0400 268#define ATH9K_TXDESC_LOWRXCHAIN 0x0400
269#define ATH9K_TXDESC_LDPC 0x00010000
263 270
264#define ATH9K_RXDESC_INTREQ 0x0020 271#define ATH9K_RXDESC_INTREQ 0x0020
265 272
@@ -353,7 +360,6 @@ struct ar5416_desc {
353#define AR_DestIdxValid 0x40000000 360#define AR_DestIdxValid 0x40000000
354#define AR_CTSEnable 0x80000000 361#define AR_CTSEnable 0x80000000
355 362
356#define AR_BufLen 0x00000fff
357#define AR_TxMore 0x00001000 363#define AR_TxMore 0x00001000
358#define AR_DestIdx 0x000fe000 364#define AR_DestIdx 0x000fe000
359#define AR_DestIdx_S 13 365#define AR_DestIdx_S 13
@@ -410,6 +416,7 @@ struct ar5416_desc {
410#define AR_EncrType 0x0c000000 416#define AR_EncrType 0x0c000000
411#define AR_EncrType_S 26 417#define AR_EncrType_S 26
412#define AR_TxCtlRsvd61 0xf0000000 418#define AR_TxCtlRsvd61 0xf0000000
419#define AR_LDPC 0x80000000
413 420
414#define AR_2040_0 0x00000001 421#define AR_2040_0 0x00000001
415#define AR_GI0 0x00000002 422#define AR_GI0 0x00000002
@@ -429,7 +436,10 @@ struct ar5416_desc {
429#define AR_ChainSel3_S 17 436#define AR_ChainSel3_S 17
430#define AR_RTSCTSRate 0x0ff00000 437#define AR_RTSCTSRate 0x0ff00000
431#define AR_RTSCTSRate_S 20 438#define AR_RTSCTSRate_S 20
432#define AR_TxCtlRsvd70 0xf0000000 439#define AR_STBC0 0x10000000
440#define AR_STBC1 0x20000000
441#define AR_STBC2 0x40000000
442#define AR_STBC3 0x80000000
433 443
434#define AR_TxRSSIAnt00 0x000000ff 444#define AR_TxRSSIAnt00 0x000000ff
435#define AR_TxRSSIAnt00_S 0 445#define AR_TxRSSIAnt00_S 0
@@ -493,7 +503,6 @@ struct ar5416_desc {
493 503
494#define AR_RxCTLRsvd00 0xffffffff 504#define AR_RxCTLRsvd00 0xffffffff
495 505
496#define AR_BufLen 0x00000fff
497#define AR_RxCtlRsvd00 0x00001000 506#define AR_RxCtlRsvd00 0x00001000
498#define AR_RxIntrReq 0x00002000 507#define AR_RxIntrReq 0x00002000
499#define AR_RxCtlRsvd01 0xffffc000 508#define AR_RxCtlRsvd01 0xffffc000
@@ -643,6 +652,7 @@ enum ath9k_rx_filter {
643#define ATH9K_RATESERIES_RTS_CTS 0x0001 652#define ATH9K_RATESERIES_RTS_CTS 0x0001
644#define ATH9K_RATESERIES_2040 0x0002 653#define ATH9K_RATESERIES_2040 0x0002
645#define ATH9K_RATESERIES_HALFGI 0x0004 654#define ATH9K_RATESERIES_HALFGI 0x0004
655#define ATH9K_RATESERIES_STBC 0x0008
646 656
647struct ath9k_11n_rate_series { 657struct ath9k_11n_rate_series {
648 u32 Tries; 658 u32 Tries;
@@ -686,34 +696,10 @@ struct ath9k_channel;
686u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q); 696u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q);
687void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp); 697void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp);
688void ath9k_hw_txstart(struct ath_hw *ah, u32 q); 698void ath9k_hw_txstart(struct ath_hw *ah, u32 q);
699void ath9k_hw_cleartxdesc(struct ath_hw *ah, void *ds);
689u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q); 700u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q);
690bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel); 701bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel);
691bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q); 702bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q);
692void ath9k_hw_filltxdesc(struct ath_hw *ah, struct ath_desc *ds,
693 u32 segLen, bool firstSeg,
694 bool lastSeg, const struct ath_desc *ds0);
695void ath9k_hw_cleartxdesc(struct ath_hw *ah, struct ath_desc *ds);
696int ath9k_hw_txprocdesc(struct ath_hw *ah, struct ath_desc *ds,
697 struct ath_tx_status *ts);
698void ath9k_hw_set11n_txdesc(struct ath_hw *ah, struct ath_desc *ds,
699 u32 pktLen, enum ath9k_pkt_type type, u32 txPower,
700 u32 keyIx, enum ath9k_key_type keyType, u32 flags);
701void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, struct ath_desc *ds,
702 struct ath_desc *lastds,
703 u32 durUpdateEn, u32 rtsctsRate,
704 u32 rtsctsDuration,
705 struct ath9k_11n_rate_series series[],
706 u32 nseries, u32 flags);
707void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, struct ath_desc *ds,
708 u32 aggrLen);
709void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, struct ath_desc *ds,
710 u32 numDelims);
711void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, struct ath_desc *ds);
712void ath9k_hw_clr11n_aggr(struct ath_hw *ah, struct ath_desc *ds);
713void ath9k_hw_set11n_burstduration(struct ath_hw *ah, struct ath_desc *ds,
714 u32 burstDuration);
715void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, struct ath_desc *ds,
716 u32 vmf);
717void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs); 703void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs);
718bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q, 704bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
719 const struct ath9k_tx_queue_info *qinfo); 705 const struct ath9k_tx_queue_info *qinfo);
@@ -729,10 +715,17 @@ void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
729 u32 size, u32 flags); 715 u32 size, u32 flags);
730bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set); 716bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set);
731void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp); 717void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp);
732void ath9k_hw_rxena(struct ath_hw *ah);
733void ath9k_hw_startpcureceive(struct ath_hw *ah); 718void ath9k_hw_startpcureceive(struct ath_hw *ah);
734void ath9k_hw_stoppcurecv(struct ath_hw *ah); 719void ath9k_hw_stoppcurecv(struct ath_hw *ah);
720void ath9k_hw_abortpcurecv(struct ath_hw *ah);
735bool ath9k_hw_stopdmarecv(struct ath_hw *ah); 721bool ath9k_hw_stopdmarecv(struct ath_hw *ah);
736int ath9k_hw_beaconq_setup(struct ath_hw *ah); 722int ath9k_hw_beaconq_setup(struct ath_hw *ah);
737 723
724/* Interrupt Handling */
725bool ath9k_hw_intrpend(struct ath_hw *ah);
726enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah,
727 enum ath9k_int ints);
728
729void ar9002_hw_attach_mac_ops(struct ath_hw *ah);
730
738#endif /* MAC_H */ 731#endif /* MAC_H */