1 files changed, 16 insertions, 20 deletions

diff --git a/drivers/net/wireless/ath/ath9k/mac.c b/drivers/net/wireless/ath/ath9k/mac.c
index 0e4fbb3bea33..fd3f19c2e550 100644
--- a/drivers/net/wireless/ath/ath9k/mac.c
+++ b/drivers/net/wireless/ath/ath9k/mac.c
@@ -21,7 +21,7 @@
 static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah,
                                         struct ath9k_tx_queue_info *qi)
 {
-        ath_dbg(ath9k_hw_common(ah), ATH_DBG_INTERRUPT,
+        ath_dbg(ath9k_hw_common(ah), INTERRUPT,
                 "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
                 ah->txok_interrupt_mask, ah->txerr_interrupt_mask,
                 ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask,
@@ -57,8 +57,7 @@ EXPORT_SYMBOL(ath9k_hw_puttxbuf);
 
 void ath9k_hw_txstart(struct ath_hw *ah, u32 q)
 {
-        ath_dbg(ath9k_hw_common(ah), ATH_DBG_QUEUE,
-                "Enable TXE on queue: %u\n", q);
+        ath_dbg(ath9k_hw_common(ah), QUEUE, "Enable TXE on queue: %u\n", q);
         REG_WRITE(ah, AR_Q_TXE, 1 << q);
 }
 EXPORT_SYMBOL(ath9k_hw_txstart);
@@ -202,12 +201,12 @@ bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
 
         qi = &ah->txq[q];
         if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
-                ath_dbg(common, ATH_DBG_QUEUE,
+                ath_dbg(common, QUEUE,
                         "Set TXQ properties, inactive queue: %u\n", q);
                 return false;
         }
 
-        ath_dbg(common, ATH_DBG_QUEUE, "Set queue properties for: %u\n", q);
+        ath_dbg(common, QUEUE, "Set queue properties for: %u\n", q);
 
         qi->tqi_ver = qinfo->tqi_ver;
         qi->tqi_subtype = qinfo->tqi_subtype;
@@ -266,7 +265,7 @@ bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
 
         qi = &ah->txq[q];
         if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
-                ath_dbg(common, ATH_DBG_QUEUE,
+                ath_dbg(common, QUEUE,
                         "Get TXQ properties, inactive queue: %u\n", q);
                 return false;
         }
@@ -325,7 +324,7 @@ int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
                 return -1;
         }
 
-        ath_dbg(common, ATH_DBG_QUEUE, "Setup TX queue: %u\n", q);
+        ath_dbg(common, QUEUE, "Setup TX queue: %u\n", q);
 
         qi = &ah->txq[q];
         if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) {
@@ -348,12 +347,11 @@ bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
 
         qi = &ah->txq[q];
         if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
-                ath_dbg(common, ATH_DBG_QUEUE,
-                        "Release TXQ, inactive queue: %u\n", q);
+                ath_dbg(common, QUEUE, "Release TXQ, inactive queue: %u\n", q);
                 return false;
         }
 
-        ath_dbg(common, ATH_DBG_QUEUE, "Release TX queue: %u\n", q);
+        ath_dbg(common, QUEUE, "Release TX queue: %u\n", q);
 
         qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE;
         ah->txok_interrupt_mask &= ~(1 << q);
@@ -376,12 +374,11 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
 
         qi = &ah->txq[q];
         if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
-                ath_dbg(common, ATH_DBG_QUEUE,
-                        "Reset TXQ, inactive queue: %u\n", q);
+                ath_dbg(common, QUEUE, "Reset TXQ, inactive queue: %u\n", q);
                 return true;
         }
 
-        ath_dbg(common, ATH_DBG_QUEUE, "Reset TX queue: %u\n", q);
+        ath_dbg(common, QUEUE, "Reset TX queue: %u\n", q);
 
         if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) {
                 if (chan && IS_CHAN_B(chan))
@@ -784,7 +781,7 @@ void ath9k_hw_disable_interrupts(struct ath_hw *ah)
         else
                 atomic_dec(&ah->intr_ref_cnt);
 
-        ath_dbg(common, ATH_DBG_INTERRUPT, "disable IER\n");
+        ath_dbg(common, INTERRUPT, "disable IER\n");
         REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
         (void) REG_READ(ah, AR_IER);
         if (!AR_SREV_9100(ah)) {
@@ -807,8 +804,7 @@ void ath9k_hw_enable_interrupts(struct ath_hw *ah)
                 return;
 
         if (!atomic_inc_and_test(&ah->intr_ref_cnt)) {
-                ath_dbg(common, ATH_DBG_INTERRUPT,
-                        "Do not enable IER ref count %d\n",
+                ath_dbg(common, INTERRUPT, "Do not enable IER ref count %d\n",
                         atomic_read(&ah->intr_ref_cnt));
                 return;
         }
@@ -821,7 +817,7 @@ void ath9k_hw_enable_interrupts(struct ath_hw *ah)
         if (ah->imask & ATH9K_INT_MCI)
                 async_mask |= AR_INTR_ASYNC_MASK_MCI;
 
-        ath_dbg(common, ATH_DBG_INTERRUPT, "enable IER\n");
+        ath_dbg(common, INTERRUPT, "enable IER\n");
         REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
         if (!AR_SREV_9100(ah)) {
                 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, async_mask);
@@ -830,7 +826,7 @@ void ath9k_hw_enable_interrupts(struct ath_hw *ah)
                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
                 REG_WRITE(ah, AR_INTR_SYNC_MASK, sync_default);
         }
-        ath_dbg(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
+        ath_dbg(common, INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
                 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
 }
 EXPORT_SYMBOL(ath9k_hw_enable_interrupts);
@@ -845,7 +841,7 @@ void ath9k_hw_set_interrupts(struct ath_hw *ah)
         if (!(ints & ATH9K_INT_GLOBAL))
                 ath9k_hw_disable_interrupts(ah);
 
-        ath_dbg(common, ATH_DBG_INTERRUPT, "New interrupt mask 0x%x\n", ints);
+        ath_dbg(common, INTERRUPT, "New interrupt mask 0x%x\n", ints);
 
         mask = ints & ATH9K_INT_COMMON;
         mask2 = 0;
@@ -908,7 +904,7 @@ void ath9k_hw_set_interrupts(struct ath_hw *ah)
                         mask2 |= AR_IMR_S2_CST;
         }
 
-        ath_dbg(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
+        ath_dbg(common, INTERRUPT, "new IMR 0x%x\n", mask);
         REG_WRITE(ah, AR_IMR, mask);
         ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
                            AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |