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path: root/drivers/net/wireless/ath/ath9k/mac.c
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Diffstat (limited to 'drivers/net/wireless/ath/ath9k/mac.c')
-rw-r--r--drivers/net/wireless/ath/ath9k/mac.c149
1 files changed, 75 insertions, 74 deletions
diff --git a/drivers/net/wireless/ath/ath9k/mac.c b/drivers/net/wireless/ath/ath9k/mac.c
index 7af823a1527d..4a2060e5a777 100644
--- a/drivers/net/wireless/ath/ath9k/mac.c
+++ b/drivers/net/wireless/ath/ath9k/mac.c
@@ -105,7 +105,7 @@ bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel)
105 if (ah->tx_trig_level >= ah->config.max_txtrig_level) 105 if (ah->tx_trig_level >= ah->config.max_txtrig_level)
106 return false; 106 return false;
107 107
108 omask = ath9k_hw_set_interrupts(ah, ah->mask_reg & ~ATH9K_INT_GLOBAL); 108 omask = ath9k_hw_set_interrupts(ah, ah->imask & ~ATH9K_INT_GLOBAL);
109 109
110 txcfg = REG_READ(ah, AR_TXCFG); 110 txcfg = REG_READ(ah, AR_TXCFG);
111 curLevel = MS(txcfg, AR_FTRIG); 111 curLevel = MS(txcfg, AR_FTRIG);
@@ -246,79 +246,80 @@ void ath9k_hw_cleartxdesc(struct ath_hw *ah, struct ath_desc *ds)
246} 246}
247EXPORT_SYMBOL(ath9k_hw_cleartxdesc); 247EXPORT_SYMBOL(ath9k_hw_cleartxdesc);
248 248
249int ath9k_hw_txprocdesc(struct ath_hw *ah, struct ath_desc *ds) 249int ath9k_hw_txprocdesc(struct ath_hw *ah, struct ath_desc *ds,
250 struct ath_tx_status *ts)
250{ 251{
251 struct ar5416_desc *ads = AR5416DESC(ds); 252 struct ar5416_desc *ads = AR5416DESC(ds);
252 253
253 if ((ads->ds_txstatus9 & AR_TxDone) == 0) 254 if ((ads->ds_txstatus9 & AR_TxDone) == 0)
254 return -EINPROGRESS; 255 return -EINPROGRESS;
255 256
256 ds->ds_txstat.ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum); 257 ts->ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
257 ds->ds_txstat.ts_tstamp = ads->AR_SendTimestamp; 258 ts->ts_tstamp = ads->AR_SendTimestamp;
258 ds->ds_txstat.ts_status = 0; 259 ts->ts_status = 0;
259 ds->ds_txstat.ts_flags = 0; 260 ts->ts_flags = 0;
260 261
261 if (ads->ds_txstatus1 & AR_FrmXmitOK) 262 if (ads->ds_txstatus1 & AR_FrmXmitOK)
262 ds->ds_txstat.ts_status |= ATH9K_TX_ACKED; 263 ts->ts_status |= ATH9K_TX_ACKED;
263 if (ads->ds_txstatus1 & AR_ExcessiveRetries) 264 if (ads->ds_txstatus1 & AR_ExcessiveRetries)
264 ds->ds_txstat.ts_status |= ATH9K_TXERR_XRETRY; 265 ts->ts_status |= ATH9K_TXERR_XRETRY;
265 if (ads->ds_txstatus1 & AR_Filtered) 266 if (ads->ds_txstatus1 & AR_Filtered)
266 ds->ds_txstat.ts_status |= ATH9K_TXERR_FILT; 267 ts->ts_status |= ATH9K_TXERR_FILT;
267 if (ads->ds_txstatus1 & AR_FIFOUnderrun) { 268 if (ads->ds_txstatus1 & AR_FIFOUnderrun) {
268 ds->ds_txstat.ts_status |= ATH9K_TXERR_FIFO; 269 ts->ts_status |= ATH9K_TXERR_FIFO;
269 ath9k_hw_updatetxtriglevel(ah, true); 270 ath9k_hw_updatetxtriglevel(ah, true);
270 } 271 }
271 if (ads->ds_txstatus9 & AR_TxOpExceeded) 272 if (ads->ds_txstatus9 & AR_TxOpExceeded)
272 ds->ds_txstat.ts_status |= ATH9K_TXERR_XTXOP; 273 ts->ts_status |= ATH9K_TXERR_XTXOP;
273 if (ads->ds_txstatus1 & AR_TxTimerExpired) 274 if (ads->ds_txstatus1 & AR_TxTimerExpired)
274 ds->ds_txstat.ts_status |= ATH9K_TXERR_TIMER_EXPIRED; 275 ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
275 276
276 if (ads->ds_txstatus1 & AR_DescCfgErr) 277 if (ads->ds_txstatus1 & AR_DescCfgErr)
277 ds->ds_txstat.ts_flags |= ATH9K_TX_DESC_CFG_ERR; 278 ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
278 if (ads->ds_txstatus1 & AR_TxDataUnderrun) { 279 if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
279 ds->ds_txstat.ts_flags |= ATH9K_TX_DATA_UNDERRUN; 280 ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
280 ath9k_hw_updatetxtriglevel(ah, true); 281 ath9k_hw_updatetxtriglevel(ah, true);
281 } 282 }
282 if (ads->ds_txstatus1 & AR_TxDelimUnderrun) { 283 if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
283 ds->ds_txstat.ts_flags |= ATH9K_TX_DELIM_UNDERRUN; 284 ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
284 ath9k_hw_updatetxtriglevel(ah, true); 285 ath9k_hw_updatetxtriglevel(ah, true);
285 } 286 }
286 if (ads->ds_txstatus0 & AR_TxBaStatus) { 287 if (ads->ds_txstatus0 & AR_TxBaStatus) {
287 ds->ds_txstat.ts_flags |= ATH9K_TX_BA; 288 ts->ts_flags |= ATH9K_TX_BA;
288 ds->ds_txstat.ba_low = ads->AR_BaBitmapLow; 289 ts->ba_low = ads->AR_BaBitmapLow;
289 ds->ds_txstat.ba_high = ads->AR_BaBitmapHigh; 290 ts->ba_high = ads->AR_BaBitmapHigh;
290 } 291 }
291 292
292 ds->ds_txstat.ts_rateindex = MS(ads->ds_txstatus9, AR_FinalTxIdx); 293 ts->ts_rateindex = MS(ads->ds_txstatus9, AR_FinalTxIdx);
293 switch (ds->ds_txstat.ts_rateindex) { 294 switch (ts->ts_rateindex) {
294 case 0: 295 case 0:
295 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate0); 296 ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate0);
296 break; 297 break;
297 case 1: 298 case 1:
298 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate1); 299 ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate1);
299 break; 300 break;
300 case 2: 301 case 2:
301 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate2); 302 ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate2);
302 break; 303 break;
303 case 3: 304 case 3:
304 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate3); 305 ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate3);
305 break; 306 break;
306 } 307 }
307 308
308 ds->ds_txstat.ts_rssi = MS(ads->ds_txstatus5, AR_TxRSSICombined); 309 ts->ts_rssi = MS(ads->ds_txstatus5, AR_TxRSSICombined);
309 ds->ds_txstat.ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00); 310 ts->ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
310 ds->ds_txstat.ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01); 311 ts->ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
311 ds->ds_txstat.ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02); 312 ts->ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
312 ds->ds_txstat.ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10); 313 ts->ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
313 ds->ds_txstat.ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11); 314 ts->ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
314 ds->ds_txstat.ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12); 315 ts->ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
315 ds->ds_txstat.evm0 = ads->AR_TxEVM0; 316 ts->evm0 = ads->AR_TxEVM0;
316 ds->ds_txstat.evm1 = ads->AR_TxEVM1; 317 ts->evm1 = ads->AR_TxEVM1;
317 ds->ds_txstat.evm2 = ads->AR_TxEVM2; 318 ts->evm2 = ads->AR_TxEVM2;
318 ds->ds_txstat.ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt); 319 ts->ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
319 ds->ds_txstat.ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt); 320 ts->ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
320 ds->ds_txstat.ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt); 321 ts->ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
321 ds->ds_txstat.ts_antenna = 0; 322 ts->ts_antenna = 0;
322 323
323 return 0; 324 return 0;
324} 325}
@@ -858,7 +859,7 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
858EXPORT_SYMBOL(ath9k_hw_resettxqueue); 859EXPORT_SYMBOL(ath9k_hw_resettxqueue);
859 860
860int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds, 861int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
861 u32 pa, struct ath_desc *nds, u64 tsf) 862 struct ath_rx_status *rs, u64 tsf)
862{ 863{
863 struct ar5416_desc ads; 864 struct ar5416_desc ads;
864 struct ar5416_desc *adsp = AR5416DESC(ds); 865 struct ar5416_desc *adsp = AR5416DESC(ds);
@@ -869,70 +870,70 @@ int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
869 870
870 ads.u.rx = adsp->u.rx; 871 ads.u.rx = adsp->u.rx;
871 872
872 ds->ds_rxstat.rs_status = 0; 873 rs->rs_status = 0;
873 ds->ds_rxstat.rs_flags = 0; 874 rs->rs_flags = 0;
874 875
875 ds->ds_rxstat.rs_datalen = ads.ds_rxstatus1 & AR_DataLen; 876 rs->rs_datalen = ads.ds_rxstatus1 & AR_DataLen;
876 ds->ds_rxstat.rs_tstamp = ads.AR_RcvTimestamp; 877 rs->rs_tstamp = ads.AR_RcvTimestamp;
877 878
878 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr) { 879 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr) {
879 ds->ds_rxstat.rs_rssi = ATH9K_RSSI_BAD; 880 rs->rs_rssi = ATH9K_RSSI_BAD;
880 ds->ds_rxstat.rs_rssi_ctl0 = ATH9K_RSSI_BAD; 881 rs->rs_rssi_ctl0 = ATH9K_RSSI_BAD;
881 ds->ds_rxstat.rs_rssi_ctl1 = ATH9K_RSSI_BAD; 882 rs->rs_rssi_ctl1 = ATH9K_RSSI_BAD;
882 ds->ds_rxstat.rs_rssi_ctl2 = ATH9K_RSSI_BAD; 883 rs->rs_rssi_ctl2 = ATH9K_RSSI_BAD;
883 ds->ds_rxstat.rs_rssi_ext0 = ATH9K_RSSI_BAD; 884 rs->rs_rssi_ext0 = ATH9K_RSSI_BAD;
884 ds->ds_rxstat.rs_rssi_ext1 = ATH9K_RSSI_BAD; 885 rs->rs_rssi_ext1 = ATH9K_RSSI_BAD;
885 ds->ds_rxstat.rs_rssi_ext2 = ATH9K_RSSI_BAD; 886 rs->rs_rssi_ext2 = ATH9K_RSSI_BAD;
886 } else { 887 } else {
887 ds->ds_rxstat.rs_rssi = MS(ads.ds_rxstatus4, AR_RxRSSICombined); 888 rs->rs_rssi = MS(ads.ds_rxstatus4, AR_RxRSSICombined);
888 ds->ds_rxstat.rs_rssi_ctl0 = MS(ads.ds_rxstatus0, 889 rs->rs_rssi_ctl0 = MS(ads.ds_rxstatus0,
889 AR_RxRSSIAnt00); 890 AR_RxRSSIAnt00);
890 ds->ds_rxstat.rs_rssi_ctl1 = MS(ads.ds_rxstatus0, 891 rs->rs_rssi_ctl1 = MS(ads.ds_rxstatus0,
891 AR_RxRSSIAnt01); 892 AR_RxRSSIAnt01);
892 ds->ds_rxstat.rs_rssi_ctl2 = MS(ads.ds_rxstatus0, 893 rs->rs_rssi_ctl2 = MS(ads.ds_rxstatus0,
893 AR_RxRSSIAnt02); 894 AR_RxRSSIAnt02);
894 ds->ds_rxstat.rs_rssi_ext0 = MS(ads.ds_rxstatus4, 895 rs->rs_rssi_ext0 = MS(ads.ds_rxstatus4,
895 AR_RxRSSIAnt10); 896 AR_RxRSSIAnt10);
896 ds->ds_rxstat.rs_rssi_ext1 = MS(ads.ds_rxstatus4, 897 rs->rs_rssi_ext1 = MS(ads.ds_rxstatus4,
897 AR_RxRSSIAnt11); 898 AR_RxRSSIAnt11);
898 ds->ds_rxstat.rs_rssi_ext2 = MS(ads.ds_rxstatus4, 899 rs->rs_rssi_ext2 = MS(ads.ds_rxstatus4,
899 AR_RxRSSIAnt12); 900 AR_RxRSSIAnt12);
900 } 901 }
901 if (ads.ds_rxstatus8 & AR_RxKeyIdxValid) 902 if (ads.ds_rxstatus8 & AR_RxKeyIdxValid)
902 ds->ds_rxstat.rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx); 903 rs->rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx);
903 else 904 else
904 ds->ds_rxstat.rs_keyix = ATH9K_RXKEYIX_INVALID; 905 rs->rs_keyix = ATH9K_RXKEYIX_INVALID;
905 906
906 ds->ds_rxstat.rs_rate = RXSTATUS_RATE(ah, (&ads)); 907 rs->rs_rate = RXSTATUS_RATE(ah, (&ads));
907 ds->ds_rxstat.rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0; 908 rs->rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0;
908 909
909 ds->ds_rxstat.rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0; 910 rs->rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
910 ds->ds_rxstat.rs_moreaggr = 911 rs->rs_moreaggr =
911 (ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0; 912 (ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
912 ds->ds_rxstat.rs_antenna = MS(ads.ds_rxstatus3, AR_RxAntenna); 913 rs->rs_antenna = MS(ads.ds_rxstatus3, AR_RxAntenna);
913 ds->ds_rxstat.rs_flags = 914 rs->rs_flags =
914 (ads.ds_rxstatus3 & AR_GI) ? ATH9K_RX_GI : 0; 915 (ads.ds_rxstatus3 & AR_GI) ? ATH9K_RX_GI : 0;
915 ds->ds_rxstat.rs_flags |= 916 rs->rs_flags |=
916 (ads.ds_rxstatus3 & AR_2040) ? ATH9K_RX_2040 : 0; 917 (ads.ds_rxstatus3 & AR_2040) ? ATH9K_RX_2040 : 0;
917 918
918 if (ads.ds_rxstatus8 & AR_PreDelimCRCErr) 919 if (ads.ds_rxstatus8 & AR_PreDelimCRCErr)
919 ds->ds_rxstat.rs_flags |= ATH9K_RX_DELIM_CRC_PRE; 920 rs->rs_flags |= ATH9K_RX_DELIM_CRC_PRE;
920 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr) 921 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr)
921 ds->ds_rxstat.rs_flags |= ATH9K_RX_DELIM_CRC_POST; 922 rs->rs_flags |= ATH9K_RX_DELIM_CRC_POST;
922 if (ads.ds_rxstatus8 & AR_DecryptBusyErr) 923 if (ads.ds_rxstatus8 & AR_DecryptBusyErr)
923 ds->ds_rxstat.rs_flags |= ATH9K_RX_DECRYPT_BUSY; 924 rs->rs_flags |= ATH9K_RX_DECRYPT_BUSY;
924 925
925 if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) { 926 if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) {
926 if (ads.ds_rxstatus8 & AR_CRCErr) 927 if (ads.ds_rxstatus8 & AR_CRCErr)
927 ds->ds_rxstat.rs_status |= ATH9K_RXERR_CRC; 928 rs->rs_status |= ATH9K_RXERR_CRC;
928 else if (ads.ds_rxstatus8 & AR_PHYErr) { 929 else if (ads.ds_rxstatus8 & AR_PHYErr) {
929 ds->ds_rxstat.rs_status |= ATH9K_RXERR_PHY; 930 rs->rs_status |= ATH9K_RXERR_PHY;
930 phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode); 931 phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode);
931 ds->ds_rxstat.rs_phyerr = phyerr; 932 rs->rs_phyerr = phyerr;
932 } else if (ads.ds_rxstatus8 & AR_DecryptCRCErr) 933 } else if (ads.ds_rxstatus8 & AR_DecryptCRCErr)
933 ds->ds_rxstat.rs_status |= ATH9K_RXERR_DECRYPT; 934 rs->rs_status |= ATH9K_RXERR_DECRYPT;
934 else if (ads.ds_rxstatus8 & AR_MichaelErr) 935 else if (ads.ds_rxstatus8 & AR_MichaelErr)
935 ds->ds_rxstat.rs_status |= ATH9K_RXERR_MIC; 936 rs->rs_status |= ATH9K_RXERR_MIC;
936 } 937 }
937 938
938 return 0; 939 return 0;