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path: root/drivers/net/wireless/ath/ath9k/hw.c
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Diffstat (limited to 'drivers/net/wireless/ath/ath9k/hw.c')
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.c296
1 files changed, 151 insertions, 145 deletions
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index c7fbe25cc128..4b51ed47fe69 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -54,13 +54,6 @@ static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
54 ath9k_hw_private_ops(ah)->init_mode_regs(ah); 54 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
55} 55}
56 56
57static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
58{
59 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
60
61 return priv_ops->macversion_supported(ah->hw_version.macVersion);
62}
63
64static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah, 57static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
65 struct ath9k_channel *chan) 58 struct ath9k_channel *chan)
66{ 59{
@@ -129,9 +122,9 @@ bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
129 udelay(AH_TIME_QUANTUM); 122 udelay(AH_TIME_QUANTUM);
130 } 123 }
131 124
132 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY, 125 ath_dbg(ath9k_hw_common(ah), ATH_DBG_ANY,
133 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 126 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
134 timeout, reg, REG_READ(ah, reg), mask, val); 127 timeout, reg, REG_READ(ah, reg), mask, val);
135 128
136 return false; 129 return false;
137} 130}
@@ -211,8 +204,8 @@ u16 ath9k_hw_computetxtime(struct ath_hw *ah,
211 } 204 }
212 break; 205 break;
213 default: 206 default:
214 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 207 ath_err(ath9k_hw_common(ah),
215 "Unknown phy %u (rate ix %u)\n", phy, rateix); 208 "Unknown phy %u (rate ix %u)\n", phy, rateix);
216 txTime = 0; 209 txTime = 0;
217 break; 210 break;
218 } 211 }
@@ -284,11 +277,9 @@ static void ath9k_hw_read_revisions(struct ath_hw *ah)
284 277
285static void ath9k_hw_disablepcie(struct ath_hw *ah) 278static void ath9k_hw_disablepcie(struct ath_hw *ah)
286{ 279{
287 if (AR_SREV_9100(ah)) 280 if (!AR_SREV_5416(ah))
288 return; 281 return;
289 282
290 ENABLE_REGWRITE_BUFFER(ah);
291
292 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 283 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
293 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 284 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
294 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 285 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
@@ -300,8 +291,6 @@ static void ath9k_hw_disablepcie(struct ath_hw *ah)
300 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 291 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
301 292
302 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 293 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
303
304 REGWRITE_BUFFER_FLUSH(ah);
305} 294}
306 295
307/* This should work for all families including legacy */ 296/* This should work for all families including legacy */
@@ -310,10 +299,9 @@ static bool ath9k_hw_chip_test(struct ath_hw *ah)
310 struct ath_common *common = ath9k_hw_common(ah); 299 struct ath_common *common = ath9k_hw_common(ah);
311 u32 regAddr[2] = { AR_STA_ID0 }; 300 u32 regAddr[2] = { AR_STA_ID0 };
312 u32 regHold[2]; 301 u32 regHold[2];
313 u32 patternData[4] = { 0x55555555, 302 static const u32 patternData[4] = {
314 0xaaaaaaaa, 303 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
315 0x66666666, 304 };
316 0x99999999 };
317 int i, j, loop_max; 305 int i, j, loop_max;
318 306
319 if (!AR_SREV_9300_20_OR_LATER(ah)) { 307 if (!AR_SREV_9300_20_OR_LATER(ah)) {
@@ -332,11 +320,9 @@ static bool ath9k_hw_chip_test(struct ath_hw *ah)
332 REG_WRITE(ah, addr, wrData); 320 REG_WRITE(ah, addr, wrData);
333 rdData = REG_READ(ah, addr); 321 rdData = REG_READ(ah, addr);
334 if (rdData != wrData) { 322 if (rdData != wrData) {
335 ath_print(common, ATH_DBG_FATAL, 323 ath_err(common,
336 "address test failed " 324 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
337 "addr: 0x%08x - wr:0x%08x != " 325 addr, wrData, rdData);
338 "rd:0x%08x\n",
339 addr, wrData, rdData);
340 return false; 326 return false;
341 } 327 }
342 } 328 }
@@ -345,11 +331,9 @@ static bool ath9k_hw_chip_test(struct ath_hw *ah)
345 REG_WRITE(ah, addr, wrData); 331 REG_WRITE(ah, addr, wrData);
346 rdData = REG_READ(ah, addr); 332 rdData = REG_READ(ah, addr);
347 if (wrData != rdData) { 333 if (wrData != rdData) {
348 ath_print(common, ATH_DBG_FATAL, 334 ath_err(common,
349 "address test failed " 335 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
350 "addr: 0x%08x - wr:0x%08x != " 336 addr, wrData, rdData);
351 "rd:0x%08x\n",
352 addr, wrData, rdData);
353 return false; 337 return false;
354 } 338 }
355 } 339 }
@@ -419,17 +403,12 @@ static void ath9k_hw_init_defaults(struct ath_hw *ah)
419 ah->hw_version.magic = AR5416_MAGIC; 403 ah->hw_version.magic = AR5416_MAGIC;
420 ah->hw_version.subvendorid = 0; 404 ah->hw_version.subvendorid = 0;
421 405
422 ah->ah_flags = 0;
423 if (!AR_SREV_9100(ah))
424 ah->ah_flags = AH_USE_EEPROM;
425
426 ah->atim_window = 0; 406 ah->atim_window = 0;
427 ah->sta_id1_defaults = 407 ah->sta_id1_defaults =
428 AR_STA_ID1_CRPT_MIC_ENABLE | 408 AR_STA_ID1_CRPT_MIC_ENABLE |
429 AR_STA_ID1_MCAST_KSRCH; 409 AR_STA_ID1_MCAST_KSRCH;
430 ah->beacon_interval = 100;
431 ah->enable_32kHz_clock = DONT_USE_32KHZ; 410 ah->enable_32kHz_clock = DONT_USE_32KHZ;
432 ah->slottime = (u32) -1; 411 ah->slottime = 20;
433 ah->globaltxtimeout = (u32) -1; 412 ah->globaltxtimeout = (u32) -1;
434 ah->power_mode = ATH9K_PM_UNDEFINED; 413 ah->power_mode = ATH9K_PM_UNDEFINED;
435} 414}
@@ -440,7 +419,7 @@ static int ath9k_hw_init_macaddr(struct ath_hw *ah)
440 u32 sum; 419 u32 sum;
441 int i; 420 int i;
442 u16 eeval; 421 u16 eeval;
443 u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; 422 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
444 423
445 sum = 0; 424 sum = 0;
446 for (i = 0; i < 3; i++) { 425 for (i = 0; i < 3; i++) {
@@ -474,16 +453,15 @@ static int ath9k_hw_post_init(struct ath_hw *ah)
474 if (ecode != 0) 453 if (ecode != 0)
475 return ecode; 454 return ecode;
476 455
477 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG, 456 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CONFIG,
478 "Eeprom VER: %d, REV: %d\n", 457 "Eeprom VER: %d, REV: %d\n",
479 ah->eep_ops->get_eeprom_ver(ah), 458 ah->eep_ops->get_eeprom_ver(ah),
480 ah->eep_ops->get_eeprom_rev(ah)); 459 ah->eep_ops->get_eeprom_rev(ah));
481 460
482 ecode = ath9k_hw_rf_alloc_ext_banks(ah); 461 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
483 if (ecode) { 462 if (ecode) {
484 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 463 ath_err(ath9k_hw_common(ah),
485 "Failed allocating banks for " 464 "Failed allocating banks for external radio\n");
486 "external radio\n");
487 ath9k_hw_rf_free_ext_banks(ah); 465 ath9k_hw_rf_free_ext_banks(ah);
488 return ecode; 466 return ecode;
489 } 467 }
@@ -514,8 +492,7 @@ static int __ath9k_hw_init(struct ath_hw *ah)
514 ah->hw_version.macVersion = AR_SREV_VERSION_9100; 492 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
515 493
516 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 494 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
517 ath_print(common, ATH_DBG_FATAL, 495 ath_err(common, "Couldn't reset chip\n");
518 "Couldn't reset chip\n");
519 return -EIO; 496 return -EIO;
520 } 497 }
521 498
@@ -525,7 +502,7 @@ static int __ath9k_hw_init(struct ath_hw *ah)
525 ath9k_hw_attach_ops(ah); 502 ath9k_hw_attach_ops(ah);
526 503
527 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 504 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
528 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n"); 505 ath_err(common, "Couldn't wakeup chip\n");
529 return -EIO; 506 return -EIO;
530 } 507 }
531 508
@@ -541,7 +518,7 @@ static int __ath9k_hw_init(struct ath_hw *ah)
541 } 518 }
542 } 519 }
543 520
544 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n", 521 ath_dbg(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
545 ah->config.serialize_regmode); 522 ah->config.serialize_regmode);
546 523
547 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 524 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
@@ -549,11 +526,22 @@ static int __ath9k_hw_init(struct ath_hw *ah)
549 else 526 else
550 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; 527 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
551 528
552 if (!ath9k_hw_macversion_supported(ah)) { 529 switch (ah->hw_version.macVersion) {
553 ath_print(common, ATH_DBG_FATAL, 530 case AR_SREV_VERSION_5416_PCI:
554 "Mac Chip Rev 0x%02x.%x is not supported by " 531 case AR_SREV_VERSION_5416_PCIE:
555 "this driver\n", ah->hw_version.macVersion, 532 case AR_SREV_VERSION_9160:
556 ah->hw_version.macRev); 533 case AR_SREV_VERSION_9100:
534 case AR_SREV_VERSION_9280:
535 case AR_SREV_VERSION_9285:
536 case AR_SREV_VERSION_9287:
537 case AR_SREV_VERSION_9271:
538 case AR_SREV_VERSION_9300:
539 case AR_SREV_VERSION_9485:
540 break;
541 default:
542 ath_err(common,
543 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
544 ah->hw_version.macVersion, ah->hw_version.macRev);
557 return -EOPNOTSUPP; 545 return -EOPNOTSUPP;
558 } 546 }
559 547
@@ -599,8 +587,7 @@ static int __ath9k_hw_init(struct ath_hw *ah)
599 587
600 r = ath9k_hw_init_macaddr(ah); 588 r = ath9k_hw_init_macaddr(ah);
601 if (r) { 589 if (r) {
602 ath_print(common, ATH_DBG_FATAL, 590 ath_err(common, "Failed to initialize MAC address\n");
603 "Failed to initialize MAC address\n");
604 return r; 591 return r;
605 } 592 }
606 593
@@ -634,21 +621,21 @@ int ath9k_hw_init(struct ath_hw *ah)
634 case AR9287_DEVID_PCIE: 621 case AR9287_DEVID_PCIE:
635 case AR2427_DEVID_PCIE: 622 case AR2427_DEVID_PCIE:
636 case AR9300_DEVID_PCIE: 623 case AR9300_DEVID_PCIE:
624 case AR9300_DEVID_AR9485_PCIE:
637 break; 625 break;
638 default: 626 default:
639 if (common->bus_ops->ath_bus_type == ATH_USB) 627 if (common->bus_ops->ath_bus_type == ATH_USB)
640 break; 628 break;
641 ath_print(common, ATH_DBG_FATAL, 629 ath_err(common, "Hardware device ID 0x%04x not supported\n",
642 "Hardware device ID 0x%04x not supported\n", 630 ah->hw_version.devid);
643 ah->hw_version.devid);
644 return -EOPNOTSUPP; 631 return -EOPNOTSUPP;
645 } 632 }
646 633
647 ret = __ath9k_hw_init(ah); 634 ret = __ath9k_hw_init(ah);
648 if (ret) { 635 if (ret) {
649 ath_print(common, ATH_DBG_FATAL, 636 ath_err(common,
650 "Unable to initialize hardware; " 637 "Unable to initialize hardware; initialization status: %d\n",
651 "initialization status: %d\n", ret); 638 ret);
652 return ret; 639 return ret;
653 } 640 }
654 641
@@ -680,7 +667,12 @@ static void ath9k_hw_init_qos(struct ath_hw *ah)
680static void ath9k_hw_init_pll(struct ath_hw *ah, 667static void ath9k_hw_init_pll(struct ath_hw *ah,
681 struct ath9k_channel *chan) 668 struct ath9k_channel *chan)
682{ 669{
683 u32 pll = ath9k_hw_compute_pll_control(ah, chan); 670 u32 pll;
671
672 if (AR_SREV_9485(ah))
673 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, 0x886666);
674
675 pll = ath9k_hw_compute_pll_control(ah, chan);
684 676
685 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 677 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
686 678
@@ -772,8 +764,8 @@ static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
772static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) 764static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
773{ 765{
774 if (tu > 0xFFFF) { 766 if (tu > 0xFFFF) {
775 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT, 767 ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT,
776 "bad global tx timeout %u\n", tu); 768 "bad global tx timeout %u\n", tu);
777 ah->globaltxtimeout = (u32) -1; 769 ah->globaltxtimeout = (u32) -1;
778 return false; 770 return false;
779 } else { 771 } else {
@@ -790,8 +782,8 @@ void ath9k_hw_init_global_settings(struct ath_hw *ah)
790 int slottime; 782 int slottime;
791 int sifstime; 783 int sifstime;
792 784
793 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n", 785 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
794 ah->misc_mode); 786 ah->misc_mode);
795 787
796 if (ah->misc_mode != 0) 788 if (ah->misc_mode != 0)
797 REG_WRITE(ah, AR_PCU_MISC, 789 REG_WRITE(ah, AR_PCU_MISC,
@@ -816,7 +808,7 @@ void ath9k_hw_init_global_settings(struct ath_hw *ah)
816 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ) 808 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
817 acktimeout += 64 - sifstime - ah->slottime; 809 acktimeout += 64 - sifstime - ah->slottime;
818 810
819 ath9k_hw_setslottime(ah, slottime); 811 ath9k_hw_setslottime(ah, ah->slottime);
820 ath9k_hw_set_ack_timeout(ah, acktimeout); 812 ath9k_hw_set_ack_timeout(ah, acktimeout);
821 ath9k_hw_set_cts_timeout(ah, acktimeout); 813 ath9k_hw_set_cts_timeout(ah, acktimeout);
822 if (ah->globaltxtimeout != (u32) -1) 814 if (ah->globaltxtimeout != (u32) -1)
@@ -1034,8 +1026,8 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1034 1026
1035 REG_WRITE(ah, AR_RTC_RC, 0); 1027 REG_WRITE(ah, AR_RTC_RC, 0);
1036 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { 1028 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1037 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, 1029 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1038 "RTC stuck in MAC reset\n"); 1030 "RTC stuck in MAC reset\n");
1039 return false; 1031 return false;
1040 } 1032 }
1041 1033
@@ -1081,8 +1073,8 @@ static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1081 AR_RTC_STATUS_M, 1073 AR_RTC_STATUS_M,
1082 AR_RTC_STATUS_ON, 1074 AR_RTC_STATUS_ON,
1083 AH_WAIT_TIMEOUT)) { 1075 AH_WAIT_TIMEOUT)) {
1084 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, 1076 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1085 "RTC not waking up\n"); 1077 "RTC not waking up\n");
1086 return false; 1078 return false;
1087 } 1079 }
1088 1080
@@ -1142,16 +1134,14 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1142 1134
1143 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1135 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1144 if (ath9k_hw_numtxpending(ah, qnum)) { 1136 if (ath9k_hw_numtxpending(ah, qnum)) {
1145 ath_print(common, ATH_DBG_QUEUE, 1137 ath_dbg(common, ATH_DBG_QUEUE,
1146 "Transmit frames pending on " 1138 "Transmit frames pending on queue %d\n", qnum);
1147 "queue %d\n", qnum);
1148 return false; 1139 return false;
1149 } 1140 }
1150 } 1141 }
1151 1142
1152 if (!ath9k_hw_rfbus_req(ah)) { 1143 if (!ath9k_hw_rfbus_req(ah)) {
1153 ath_print(common, ATH_DBG_FATAL, 1144 ath_err(common, "Could not kill baseband RX\n");
1154 "Could not kill baseband RX\n");
1155 return false; 1145 return false;
1156 } 1146 }
1157 1147
@@ -1159,8 +1149,7 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1159 1149
1160 r = ath9k_hw_rf_set_freq(ah, chan); 1150 r = ath9k_hw_rf_set_freq(ah, chan);
1161 if (r) { 1151 if (r) {
1162 ath_print(common, ATH_DBG_FATAL, 1152 ath_err(common, "Failed to set channel\n");
1163 "Failed to set channel\n");
1164 return false; 1153 return false;
1165 } 1154 }
1166 ath9k_hw_set_clockrate(ah); 1155 ath9k_hw_set_clockrate(ah);
@@ -1170,7 +1159,7 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1170 channel->max_antenna_gain * 2, 1159 channel->max_antenna_gain * 2,
1171 channel->max_power * 2, 1160 channel->max_power * 2,
1172 min((u32) MAX_RATE_POWER, 1161 min((u32) MAX_RATE_POWER,
1173 (u32) regulatory->power_limit)); 1162 (u32) regulatory->power_limit), false);
1174 1163
1175 ath9k_hw_rfbus_done(ah); 1164 ath9k_hw_rfbus_done(ah);
1176 1165
@@ -1227,7 +1216,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1227 if (!ah->chip_fullsleep) { 1216 if (!ah->chip_fullsleep) {
1228 ath9k_hw_abortpcurecv(ah); 1217 ath9k_hw_abortpcurecv(ah);
1229 if (!ath9k_hw_stopdmarecv(ah)) { 1218 if (!ath9k_hw_stopdmarecv(ah)) {
1230 ath_print(common, ATH_DBG_XMIT, 1219 ath_dbg(common, ATH_DBG_XMIT,
1231 "Failed to stop receive dma\n"); 1220 "Failed to stop receive dma\n");
1232 bChannelChange = false; 1221 bChannelChange = false;
1233 } 1222 }
@@ -1283,6 +1272,8 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1283 1272
1284 ath9k_hw_mark_phy_inactive(ah); 1273 ath9k_hw_mark_phy_inactive(ah);
1285 1274
1275 ah->paprd_table_write_done = false;
1276
1286 /* Only required on the first reset */ 1277 /* Only required on the first reset */
1287 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1278 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1288 REG_WRITE(ah, 1279 REG_WRITE(ah,
@@ -1292,7 +1283,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1292 } 1283 }
1293 1284
1294 if (!ath9k_hw_chip_reset(ah, chan)) { 1285 if (!ath9k_hw_chip_reset(ah, chan)) {
1295 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n"); 1286 ath_err(common, "Chip reset failed\n");
1296 return -EINVAL; 1287 return -EINVAL;
1297 } 1288 }
1298 1289
@@ -1394,7 +1385,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1394 ath9k_hw_init_qos(ah); 1385 ath9k_hw_init_qos(ah);
1395 1386
1396 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 1387 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1397 ath9k_enable_rfkill(ah); 1388 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1398 1389
1399 ath9k_hw_init_global_settings(ah); 1390 ath9k_hw_init_global_settings(ah);
1400 1391
@@ -1439,13 +1430,13 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1439 u32 mask; 1430 u32 mask;
1440 mask = REG_READ(ah, AR_CFG); 1431 mask = REG_READ(ah, AR_CFG);
1441 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 1432 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1442 ath_print(common, ATH_DBG_RESET, 1433 ath_dbg(common, ATH_DBG_RESET,
1443 "CFG Byte Swap Set 0x%x\n", mask); 1434 "CFG Byte Swap Set 0x%x\n", mask);
1444 } else { 1435 } else {
1445 mask = 1436 mask =
1446 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 1437 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1447 REG_WRITE(ah, AR_CFG, mask); 1438 REG_WRITE(ah, AR_CFG, mask);
1448 ath_print(common, ATH_DBG_RESET, 1439 ath_dbg(common, ATH_DBG_RESET,
1449 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG)); 1440 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1450 } 1441 }
1451 } else { 1442 } else {
@@ -1573,9 +1564,9 @@ static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
1573 AR_RTC_FORCE_WAKE_EN); 1564 AR_RTC_FORCE_WAKE_EN);
1574 } 1565 }
1575 if (i == 0) { 1566 if (i == 0) {
1576 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 1567 ath_err(ath9k_hw_common(ah),
1577 "Failed to wakeup in %uus\n", 1568 "Failed to wakeup in %uus\n",
1578 POWER_UP_TIME / 20); 1569 POWER_UP_TIME / 20);
1579 return false; 1570 return false;
1580 } 1571 }
1581 } 1572 }
@@ -1599,8 +1590,8 @@ bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1599 if (ah->power_mode == mode) 1590 if (ah->power_mode == mode)
1600 return status; 1591 return status;
1601 1592
1602 ath_print(common, ATH_DBG_RESET, "%s -> %s\n", 1593 ath_dbg(common, ATH_DBG_RESET, "%s -> %s\n",
1603 modes[ah->power_mode], modes[mode]); 1594 modes[ah->power_mode], modes[mode]);
1604 1595
1605 switch (mode) { 1596 switch (mode) {
1606 case ATH9K_PM_AWAKE: 1597 case ATH9K_PM_AWAKE:
@@ -1614,12 +1605,18 @@ bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1614 ath9k_set_power_network_sleep(ah, setChip); 1605 ath9k_set_power_network_sleep(ah, setChip);
1615 break; 1606 break;
1616 default: 1607 default:
1617 ath_print(common, ATH_DBG_FATAL, 1608 ath_err(common, "Unknown power mode %u\n", mode);
1618 "Unknown power mode %u\n", mode);
1619 return false; 1609 return false;
1620 } 1610 }
1621 ah->power_mode = mode; 1611 ah->power_mode = mode;
1622 1612
1613 /*
1614 * XXX: If this warning never comes up after a while then
1615 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
1616 * ath9k_hw_setpower() return type void.
1617 */
1618 ATH_DBG_WARN_ON_ONCE(!status);
1619
1623 return status; 1620 return status;
1624} 1621}
1625EXPORT_SYMBOL(ath9k_hw_setpower); 1622EXPORT_SYMBOL(ath9k_hw_setpower);
@@ -1632,17 +1629,9 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1632{ 1629{
1633 int flags = 0; 1630 int flags = 0;
1634 1631
1635 ah->beacon_interval = beacon_period;
1636
1637 ENABLE_REGWRITE_BUFFER(ah); 1632 ENABLE_REGWRITE_BUFFER(ah);
1638 1633
1639 switch (ah->opmode) { 1634 switch (ah->opmode) {
1640 case NL80211_IFTYPE_STATION:
1641 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1642 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
1643 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
1644 flags |= AR_TBTT_TIMER_EN;
1645 break;
1646 case NL80211_IFTYPE_ADHOC: 1635 case NL80211_IFTYPE_ADHOC:
1647 case NL80211_IFTYPE_MESH_POINT: 1636 case NL80211_IFTYPE_MESH_POINT:
1648 REG_SET_BIT(ah, AR_TXCFG, 1637 REG_SET_BIT(ah, AR_TXCFG,
@@ -1666,17 +1655,9 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1666 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 1655 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1667 break; 1656 break;
1668 default: 1657 default:
1669 if (ah->is_monitoring) { 1658 ath_dbg(ath9k_hw_common(ah), ATH_DBG_BEACON,
1670 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, 1659 "%s: unsupported opmode: %d\n",
1671 TU_TO_USEC(next_beacon)); 1660 __func__, ah->opmode);
1672 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
1673 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
1674 flags |= AR_TBTT_TIMER_EN;
1675 break;
1676 }
1677 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
1678 "%s: unsupported opmode: %d\n",
1679 __func__, ah->opmode);
1680 return; 1661 return;
1681 break; 1662 break;
1682 } 1663 }
@@ -1732,10 +1713,10 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1732 else 1713 else
1733 nextTbtt = bs->bs_nexttbtt; 1714 nextTbtt = bs->bs_nexttbtt;
1734 1715
1735 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim); 1716 ath_dbg(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1736 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt); 1717 ath_dbg(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1737 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval); 1718 ath_dbg(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1738 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod); 1719 ath_dbg(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
1739 1720
1740 ENABLE_REGWRITE_BUFFER(ah); 1721 ENABLE_REGWRITE_BUFFER(ah);
1741 1722
@@ -1781,7 +1762,7 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1781 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw; 1762 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
1782 1763
1783 u16 capField = 0, eeval; 1764 u16 capField = 0, eeval;
1784 u8 ant_div_ctl1; 1765 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
1785 1766
1786 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 1767 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
1787 regulatory->current_rd = eeval; 1768 regulatory->current_rd = eeval;
@@ -1800,14 +1781,14 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1800 regulatory->current_rd += 5; 1781 regulatory->current_rd += 5;
1801 else if (regulatory->current_rd == 0x41) 1782 else if (regulatory->current_rd == 0x41)
1802 regulatory->current_rd = 0x43; 1783 regulatory->current_rd = 0x43;
1803 ath_print(common, ATH_DBG_REGULATORY, 1784 ath_dbg(common, ATH_DBG_REGULATORY,
1804 "regdomain mapped to 0x%x\n", regulatory->current_rd); 1785 "regdomain mapped to 0x%x\n", regulatory->current_rd);
1805 } 1786 }
1806 1787
1807 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); 1788 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
1808 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) { 1789 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
1809 ath_print(common, ATH_DBG_FATAL, 1790 ath_err(common,
1810 "no band has been marked as supported in EEPROM.\n"); 1791 "no band has been marked as supported in EEPROM\n");
1811 return -EINVAL; 1792 return -EINVAL;
1812 } 1793 }
1813 1794
@@ -1833,6 +1814,10 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1833 1814
1834 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 1815 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
1835 1816
1817 /* enable key search for every frame in an aggregate */
1818 if (AR_SREV_9300_20_OR_LATER(ah))
1819 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
1820
1836 pCap->low_2ghz_chan = 2312; 1821 pCap->low_2ghz_chan = 2312;
1837 pCap->high_2ghz_chan = 2732; 1822 pCap->high_2ghz_chan = 2732;
1838 1823
@@ -1921,13 +1906,7 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1921 AR_SREV_5416(ah)) 1906 AR_SREV_5416(ah))
1922 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND; 1907 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
1923 1908
1924 pCap->num_antcfg_5ghz = 1909 if (AR_SREV_9280_20_OR_LATER(ah) && common->btcoex_enabled) {
1925 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
1926 pCap->num_antcfg_2ghz =
1927 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
1928
1929 if (AR_SREV_9280_20_OR_LATER(ah) &&
1930 ath9k_hw_btcoex_supported(ah)) {
1931 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO; 1910 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
1932 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO; 1911 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
1933 1912
@@ -1942,8 +1921,10 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1942 } 1921 }
1943 1922
1944 if (AR_SREV_9300_20_OR_LATER(ah)) { 1923 if (AR_SREV_9300_20_OR_LATER(ah)) {
1945 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_LDPC | 1924 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
1946 ATH9K_HW_CAP_FASTCLOCK; 1925 if (!AR_SREV_9485(ah))
1926 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
1927
1947 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; 1928 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
1948 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; 1929 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
1949 pCap->rx_status_len = sizeof(struct ar9003_rxs); 1930 pCap->rx_status_len = sizeof(struct ar9003_rxs);
@@ -1963,6 +1944,9 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1963 if (AR_SREV_9300_20_OR_LATER(ah)) 1944 if (AR_SREV_9300_20_OR_LATER(ah))
1964 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; 1945 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
1965 1946
1947 if (AR_SREV_9300_20_OR_LATER(ah))
1948 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
1949
1966 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah)) 1950 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
1967 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20; 1951 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
1968 1952
@@ -1973,6 +1957,29 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1973 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) 1957 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
1974 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 1958 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
1975 } 1959 }
1960 if (AR_SREV_9300_20_OR_LATER(ah)) {
1961 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
1962 pCap->hw_caps |= ATH9K_HW_CAP_APM;
1963 }
1964
1965
1966
1967 if (AR_SREV_9485_10(ah)) {
1968 pCap->pcie_lcr_extsync_en = true;
1969 pCap->pcie_lcr_offset = 0x80;
1970 }
1971
1972 tx_chainmask = pCap->tx_chainmask;
1973 rx_chainmask = pCap->rx_chainmask;
1974 while (tx_chainmask || rx_chainmask) {
1975 if (tx_chainmask & BIT(0))
1976 pCap->max_txchains++;
1977 if (rx_chainmask & BIT(0))
1978 pCap->max_rxchains++;
1979
1980 tx_chainmask >>= 1;
1981 rx_chainmask >>= 1;
1982 }
1976 1983
1977 return 0; 1984 return 0;
1978} 1985}
@@ -2177,7 +2184,7 @@ bool ath9k_hw_disable(struct ath_hw *ah)
2177} 2184}
2178EXPORT_SYMBOL(ath9k_hw_disable); 2185EXPORT_SYMBOL(ath9k_hw_disable);
2179 2186
2180void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit) 2187void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2181{ 2188{
2182 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 2189 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2183 struct ath9k_channel *chan = ah->curchan; 2190 struct ath9k_channel *chan = ah->curchan;
@@ -2190,7 +2197,7 @@ void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
2190 channel->max_antenna_gain * 2, 2197 channel->max_antenna_gain * 2,
2191 channel->max_power * 2, 2198 channel->max_power * 2,
2192 min((u32) MAX_RATE_POWER, 2199 min((u32) MAX_RATE_POWER,
2193 (u32) regulatory->power_limit)); 2200 (u32) regulatory->power_limit), test);
2194} 2201}
2195EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); 2202EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2196 2203
@@ -2250,8 +2257,8 @@ void ath9k_hw_reset_tsf(struct ath_hw *ah)
2250{ 2257{
2251 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, 2258 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2252 AH_TSF_WRITE_TIMEOUT)) 2259 AH_TSF_WRITE_TIMEOUT))
2253 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, 2260 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
2254 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); 2261 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2255 2262
2256 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 2263 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2257} 2264}
@@ -2324,11 +2331,10 @@ static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2324 return timer_table->gen_timer_index[b]; 2331 return timer_table->gen_timer_index[b];
2325} 2332}
2326 2333
2327u32 ath9k_hw_gettsf32(struct ath_hw *ah) 2334static u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2328{ 2335{
2329 return REG_READ(ah, AR_TSF_L32); 2336 return REG_READ(ah, AR_TSF_L32);
2330} 2337}
2331EXPORT_SYMBOL(ath9k_hw_gettsf32);
2332 2338
2333struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 2339struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2334 void (*trigger)(void *), 2340 void (*trigger)(void *),
@@ -2342,9 +2348,9 @@ struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2342 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); 2348 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2343 2349
2344 if (timer == NULL) { 2350 if (timer == NULL) {
2345 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 2351 ath_err(ath9k_hw_common(ah),
2346 "Failed to allocate memory" 2352 "Failed to allocate memory for hw timer[%d]\n",
2347 "for hw timer[%d]\n", timer_index); 2353 timer_index);
2348 return NULL; 2354 return NULL;
2349 } 2355 }
2350 2356
@@ -2373,9 +2379,9 @@ void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2373 2379
2374 tsf = ath9k_hw_gettsf32(ah); 2380 tsf = ath9k_hw_gettsf32(ah);
2375 2381
2376 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER, 2382 ath_dbg(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2377 "curent tsf %x period %x" 2383 "current tsf %x period %x timer_next %x\n",
2378 "timer_next %x\n", tsf, timer_period, timer_next); 2384 tsf, timer_period, timer_next);
2379 2385
2380 /* 2386 /*
2381 * Pull timer_next forward if the current TSF already passed it 2387 * Pull timer_next forward if the current TSF already passed it
@@ -2455,8 +2461,8 @@ void ath_gen_timer_isr(struct ath_hw *ah)
2455 index = rightmost_index(timer_table, &thresh_mask); 2461 index = rightmost_index(timer_table, &thresh_mask);
2456 timer = timer_table->timers[index]; 2462 timer = timer_table->timers[index];
2457 BUG_ON(!timer); 2463 BUG_ON(!timer);
2458 ath_print(common, ATH_DBG_HWTIMER, 2464 ath_dbg(common, ATH_DBG_HWTIMER,
2459 "TSF overflow for Gen timer %d\n", index); 2465 "TSF overflow for Gen timer %d\n", index);
2460 timer->overflow(timer->arg); 2466 timer->overflow(timer->arg);
2461 } 2467 }
2462 2468
@@ -2464,8 +2470,8 @@ void ath_gen_timer_isr(struct ath_hw *ah)
2464 index = rightmost_index(timer_table, &trigger_mask); 2470 index = rightmost_index(timer_table, &trigger_mask);
2465 timer = timer_table->timers[index]; 2471 timer = timer_table->timers[index];
2466 BUG_ON(!timer); 2472 BUG_ON(!timer);
2467 ath_print(common, ATH_DBG_HWTIMER, 2473 ath_dbg(common, ATH_DBG_HWTIMER,
2468 "Gen timer[%d] trigger\n", index); 2474 "Gen timer[%d] trigger\n", index);
2469 timer->trigger(timer->arg); 2475 timer->trigger(timer->arg);
2470 } 2476 }
2471} 2477}
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-01 11:16:08 -0400