diff options
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/hw.c')
-rw-r--r-- | drivers/net/wireless/ath/ath9k/hw.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c index 9a139dcc69b3..df62113d89d6 100644 --- a/drivers/net/wireless/ath/ath9k/hw.c +++ b/drivers/net/wireless/ath/ath9k/hw.c | |||
@@ -2392,7 +2392,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, | |||
2392 | if (AR_SREV_9280_10_OR_LATER(ah)) | 2392 | if (AR_SREV_9280_10_OR_LATER(ah)) |
2393 | REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); | 2393 | REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); |
2394 | 2394 | ||
2395 | if (AR_SREV_9287_10_OR_LATER(ah)) { | 2395 | if (AR_SREV_9287_12_OR_LATER(ah)) { |
2396 | /* Enable ASYNC FIFO */ | 2396 | /* Enable ASYNC FIFO */ |
2397 | REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, | 2397 | REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, |
2398 | AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL); | 2398 | AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL); |
@@ -2478,7 +2478,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, | |||
2478 | 2478 | ||
2479 | ath9k_hw_init_user_settings(ah); | 2479 | ath9k_hw_init_user_settings(ah); |
2480 | 2480 | ||
2481 | if (AR_SREV_9287_10_OR_LATER(ah)) { | 2481 | if (AR_SREV_9287_12_OR_LATER(ah)) { |
2482 | REG_WRITE(ah, AR_D_GBL_IFS_SIFS, | 2482 | REG_WRITE(ah, AR_D_GBL_IFS_SIFS, |
2483 | AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR); | 2483 | AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR); |
2484 | REG_WRITE(ah, AR_D_GBL_IFS_SLOT, | 2484 | REG_WRITE(ah, AR_D_GBL_IFS_SLOT, |
@@ -2494,7 +2494,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, | |||
2494 | REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN, | 2494 | REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN, |
2495 | AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL); | 2495 | AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL); |
2496 | } | 2496 | } |
2497 | if (AR_SREV_9287_10_OR_LATER(ah)) { | 2497 | if (AR_SREV_9287_12_OR_LATER(ah)) { |
2498 | REG_SET_BIT(ah, AR_PCU_MISC_MODE2, | 2498 | REG_SET_BIT(ah, AR_PCU_MISC_MODE2, |
2499 | AR_PCU_MISC_MODE2_ENABLE_AGGWEP); | 2499 | AR_PCU_MISC_MODE2_ENABLE_AGGWEP); |
2500 | } | 2500 | } |