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path: root/drivers/net/wireless/ath/ath9k/hw.c
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Diffstat (limited to 'drivers/net/wireless/ath/ath9k/hw.c')
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.c25
1 files changed, 17 insertions, 8 deletions
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index 7f25da8444fe..15dfefcf2d0f 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -1172,6 +1172,7 @@ u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
1172static inline void ath9k_hw_set_dma(struct ath_hw *ah) 1172static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1173{ 1173{
1174 struct ath_common *common = ath9k_hw_common(ah); 1174 struct ath_common *common = ath9k_hw_common(ah);
1175 int txbuf_size;
1175 1176
1176 ENABLE_REGWRITE_BUFFER(ah); 1177 ENABLE_REGWRITE_BUFFER(ah);
1177 1178
@@ -1225,13 +1226,17 @@ static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1225 * So set the usable tx buf size also to half to 1226 * So set the usable tx buf size also to half to
1226 * avoid data/delimiter underruns 1227 * avoid data/delimiter underruns
1227 */ 1228 */
1228 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 1229 txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE;
1229 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE); 1230 } else if (AR_SREV_9340_13_OR_LATER(ah)) {
1230 } else if (!AR_SREV_9271(ah)) { 1231 /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */
1231 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 1232 txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE;
1232 AR_PCU_TXBUF_CTRL_USABLE_SIZE); 1233 } else {
1234 txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE;
1233 } 1235 }
1234 1236
1237 if (!AR_SREV_9271(ah))
1238 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size);
1239
1235 REGWRITE_BUFFER_FLUSH(ah); 1240 REGWRITE_BUFFER_FLUSH(ah);
1236 1241
1237 if (AR_SREV_9300_20_OR_LATER(ah)) 1242 if (AR_SREV_9300_20_OR_LATER(ah))
@@ -1306,9 +1311,13 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1306 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; 1311 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1307 } else { 1312 } else {
1308 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); 1313 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1309 if (tmpReg & 1314 if (AR_SREV_9340(ah))
1310 (AR_INTR_SYNC_LOCAL_TIMEOUT | 1315 tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT;
1311 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { 1316 else
1317 tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT |
1318 AR_INTR_SYNC_RADM_CPL_TIMEOUT;
1319
1320 if (tmpReg) {
1312 u32 val; 1321 u32 val;
1313 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 1322 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1314 1323