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path: root/drivers/net/wireless/ath/ath9k/hw.c
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Diffstat (limited to 'drivers/net/wireless/ath/ath9k/hw.c')
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.c41
1 files changed, 29 insertions, 12 deletions
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index c33f17dbe6f1..2adc7e78cebf 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -392,12 +392,6 @@ static void ath9k_hw_init_config(struct ath_hw *ah)
392 ah->config.rx_intr_mitigation = true; 392 ah->config.rx_intr_mitigation = true;
393 393
394 /* 394 /*
395 * Tx IQ Calibration (ah->config.tx_iq_calibration) is only
396 * used by AR9003, but it is showing reliability issues.
397 * It will take a while to fix so this is currently disabled.
398 */
399
400 /*
401 * We need this for PCI devices only (Cardbus, PCI, miniPCI) 395 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
402 * _and_ if on non-uniprocessor systems (Multiprocessor/HT). 396 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
403 * This means we use it for all AR5416 devices, and the few 397 * This means we use it for all AR5416 devices, and the few
@@ -627,6 +621,7 @@ static int __ath9k_hw_init(struct ath_hw *ah)
627 ar9003_hw_set_nf_limits(ah); 621 ar9003_hw_set_nf_limits(ah);
628 622
629 ath9k_init_nfcal_hist_buffer(ah); 623 ath9k_init_nfcal_hist_buffer(ah);
624 ah->bb_watchdog_timeout_ms = 25;
630 625
631 common->state = ATH_HW_INITIALIZED; 626 common->state = ATH_HW_INITIALIZED;
632 627
@@ -1303,6 +1298,9 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1303 if (AR_SREV_9280_10_OR_LATER(ah)) 1298 if (AR_SREV_9280_10_OR_LATER(ah))
1304 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 1299 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1305 1300
1301 if (!AR_SREV_9300_20_OR_LATER(ah))
1302 ar9002_hw_enable_async_fifo(ah);
1303
1306 r = ath9k_hw_process_ini(ah, chan); 1304 r = ath9k_hw_process_ini(ah, chan);
1307 if (r) 1305 if (r)
1308 return r; 1306 return r;
@@ -1375,7 +1373,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1375 ath9k_hw_init_global_settings(ah); 1373 ath9k_hw_init_global_settings(ah);
1376 1374
1377 if (!AR_SREV_9300_20_OR_LATER(ah)) { 1375 if (!AR_SREV_9300_20_OR_LATER(ah)) {
1378 ar9002_hw_enable_async_fifo(ah); 1376 ar9002_hw_update_async_fifo(ah);
1379 ar9002_hw_enable_wep_aggregation(ah); 1377 ar9002_hw_enable_wep_aggregation(ah);
1380 } 1378 }
1381 1379
@@ -1426,9 +1424,13 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1426 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG)); 1424 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1427 } 1425 }
1428 } else { 1426 } else {
1429 /* Configure AR9271 target WLAN */ 1427 if (common->bus_ops->ath_bus_type == ATH_USB) {
1430 if (AR_SREV_9271(ah)) 1428 /* Configure AR9271 target WLAN */
1431 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 1429 if (AR_SREV_9271(ah))
1430 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1431 else
1432 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1433 }
1432#ifdef __BIG_ENDIAN 1434#ifdef __BIG_ENDIAN
1433 else 1435 else
1434 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1436 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
@@ -1441,6 +1443,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1441 if (AR_SREV_9300_20_OR_LATER(ah)) { 1443 if (AR_SREV_9300_20_OR_LATER(ah)) {
1442 ath9k_hw_loadnf(ah, curchan); 1444 ath9k_hw_loadnf(ah, curchan);
1443 ath9k_hw_start_nfcal(ah); 1445 ath9k_hw_start_nfcal(ah);
1446 ar9003_hw_bb_watchdog_config(ah);
1444 } 1447 }
1445 1448
1446 return 0; 1449 return 0;
@@ -1489,6 +1492,7 @@ EXPORT_SYMBOL(ath9k_hw_keyreset);
1489bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac) 1492bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
1490{ 1493{
1491 u32 macHi, macLo; 1494 u32 macHi, macLo;
1495 u32 unicast_flag = AR_KEYTABLE_VALID;
1492 1496
1493 if (entry >= ah->caps.keycache_size) { 1497 if (entry >= ah->caps.keycache_size) {
1494 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 1498 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
@@ -1497,6 +1501,16 @@ bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
1497 } 1501 }
1498 1502
1499 if (mac != NULL) { 1503 if (mac != NULL) {
1504 /*
1505 * AR_KEYTABLE_VALID indicates that the address is a unicast
1506 * address, which must match the transmitter address for
1507 * decrypting frames.
1508 * Not setting this bit allows the hardware to use the key
1509 * for multicast frame decryption.
1510 */
1511 if (mac[0] & 0x01)
1512 unicast_flag = 0;
1513
1500 macHi = (mac[5] << 8) | mac[4]; 1514 macHi = (mac[5] << 8) | mac[4];
1501 macLo = (mac[3] << 24) | 1515 macLo = (mac[3] << 24) |
1502 (mac[2] << 16) | 1516 (mac[2] << 16) |
@@ -1509,7 +1523,7 @@ bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
1509 macLo = macHi = 0; 1523 macLo = macHi = 0;
1510 } 1524 }
1511 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo); 1525 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
1512 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID); 1526 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | unicast_flag);
1513 1527
1514 return true; 1528 return true;
1515} 1529}
@@ -2165,7 +2179,7 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2165 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; 2179 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2166 } 2180 }
2167#endif 2181#endif
2168 if (AR_SREV_9271(ah)) 2182 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
2169 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; 2183 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2170 else 2184 else
2171 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; 2185 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
@@ -2232,6 +2246,9 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2232 if (AR_SREV_9300_20_OR_LATER(ah)) 2246 if (AR_SREV_9300_20_OR_LATER(ah))
2233 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; 2247 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2234 2248
2249 if (AR_SREV_9287_10_OR_LATER(ah) || AR_SREV_9271(ah))
2250 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2251
2235 return 0; 2252 return 0;
2236} 2253}
2237 2254