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path: root/drivers/net/wireless/ath/ath9k/eeprom.c
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Diffstat (limited to 'drivers/net/wireless/ath/ath9k/eeprom.c')
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom.c219
1 files changed, 216 insertions, 3 deletions
diff --git a/drivers/net/wireless/ath/ath9k/eeprom.c b/drivers/net/wireless/ath/ath9k/eeprom.c
index 2bbf94d0191e..d05163159572 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom.c
@@ -234,7 +234,7 @@ void ath9k_hw_get_target_powers(struct ath_hw *ah,
234u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower, 234u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower,
235 bool is2GHz, int num_band_edges) 235 bool is2GHz, int num_band_edges)
236{ 236{
237 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 237 u16 twiceMaxEdgePower = MAX_RATE_POWER;
238 int i; 238 int i;
239 239
240 for (i = 0; (i < num_band_edges) && 240 for (i = 0; (i < num_band_edges) &&
@@ -273,12 +273,225 @@ void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah)
273 regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN; 273 regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
274 break; 274 break;
275 default: 275 default:
276 ath_print(common, ATH_DBG_EEPROM, 276 ath_dbg(common, ATH_DBG_EEPROM,
277 "Invalid chainmask configuration\n"); 277 "Invalid chainmask configuration\n");
278 break; 278 break;
279 } 279 }
280} 280}
281 281
282void ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hw *ah,
283 struct ath9k_channel *chan,
284 void *pRawDataSet,
285 u8 *bChans, u16 availPiers,
286 u16 tPdGainOverlap,
287 u16 *pPdGainBoundaries, u8 *pPDADCValues,
288 u16 numXpdGains)
289{
290 int i, j, k;
291 int16_t ss;
292 u16 idxL = 0, idxR = 0, numPiers;
293 static u8 vpdTableL[AR5416_NUM_PD_GAINS]
294 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
295 static u8 vpdTableR[AR5416_NUM_PD_GAINS]
296 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
297 static u8 vpdTableI[AR5416_NUM_PD_GAINS]
298 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
299
300 u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
301 u8 minPwrT4[AR5416_NUM_PD_GAINS];
302 u8 maxPwrT4[AR5416_NUM_PD_GAINS];
303 int16_t vpdStep;
304 int16_t tmpVal;
305 u16 sizeCurrVpdTable, maxIndex, tgtIndex;
306 bool match;
307 int16_t minDelta = 0;
308 struct chan_centers centers;
309 int pdgain_boundary_default;
310 struct cal_data_per_freq *data_def = pRawDataSet;
311 struct cal_data_per_freq_4k *data_4k = pRawDataSet;
312 struct cal_data_per_freq_ar9287 *data_9287 = pRawDataSet;
313 bool eeprom_4k = AR_SREV_9285(ah) || AR_SREV_9271(ah);
314 int intercepts;
315
316 if (AR_SREV_9287(ah))
317 intercepts = AR9287_PD_GAIN_ICEPTS;
318 else
319 intercepts = AR5416_PD_GAIN_ICEPTS;
320
321 memset(&minPwrT4, 0, AR5416_NUM_PD_GAINS);
322 ath9k_hw_get_channel_centers(ah, chan, &centers);
323
324 for (numPiers = 0; numPiers < availPiers; numPiers++) {
325 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
326 break;
327 }
328
329 match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center,
330 IS_CHAN_2GHZ(chan)),
331 bChans, numPiers, &idxL, &idxR);
332
333 if (match) {
334 if (AR_SREV_9287(ah)) {
335 /* FIXME: array overrun? */
336 for (i = 0; i < numXpdGains; i++) {
337 minPwrT4[i] = data_9287[idxL].pwrPdg[i][0];
338 maxPwrT4[i] = data_9287[idxL].pwrPdg[i][4];
339 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
340 data_9287[idxL].pwrPdg[i],
341 data_9287[idxL].vpdPdg[i],
342 intercepts,
343 vpdTableI[i]);
344 }
345 } else if (eeprom_4k) {
346 for (i = 0; i < numXpdGains; i++) {
347 minPwrT4[i] = data_4k[idxL].pwrPdg[i][0];
348 maxPwrT4[i] = data_4k[idxL].pwrPdg[i][4];
349 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
350 data_4k[idxL].pwrPdg[i],
351 data_4k[idxL].vpdPdg[i],
352 intercepts,
353 vpdTableI[i]);
354 }
355 } else {
356 for (i = 0; i < numXpdGains; i++) {
357 minPwrT4[i] = data_def[idxL].pwrPdg[i][0];
358 maxPwrT4[i] = data_def[idxL].pwrPdg[i][4];
359 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
360 data_def[idxL].pwrPdg[i],
361 data_def[idxL].vpdPdg[i],
362 intercepts,
363 vpdTableI[i]);
364 }
365 }
366 } else {
367 for (i = 0; i < numXpdGains; i++) {
368 if (AR_SREV_9287(ah)) {
369 pVpdL = data_9287[idxL].vpdPdg[i];
370 pPwrL = data_9287[idxL].pwrPdg[i];
371 pVpdR = data_9287[idxR].vpdPdg[i];
372 pPwrR = data_9287[idxR].pwrPdg[i];
373 } else if (eeprom_4k) {
374 pVpdL = data_4k[idxL].vpdPdg[i];
375 pPwrL = data_4k[idxL].pwrPdg[i];
376 pVpdR = data_4k[idxR].vpdPdg[i];
377 pPwrR = data_4k[idxR].pwrPdg[i];
378 } else {
379 pVpdL = data_def[idxL].vpdPdg[i];
380 pPwrL = data_def[idxL].pwrPdg[i];
381 pVpdR = data_def[idxR].vpdPdg[i];
382 pPwrR = data_def[idxR].pwrPdg[i];
383 }
384
385 minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
386
387 maxPwrT4[i] =
388 min(pPwrL[intercepts - 1],
389 pPwrR[intercepts - 1]);
390
391
392 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
393 pPwrL, pVpdL,
394 intercepts,
395 vpdTableL[i]);
396 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
397 pPwrR, pVpdR,
398 intercepts,
399 vpdTableR[i]);
400
401 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
402 vpdTableI[i][j] =
403 (u8)(ath9k_hw_interpolate((u16)
404 FREQ2FBIN(centers.
405 synth_center,
406 IS_CHAN_2GHZ
407 (chan)),
408 bChans[idxL], bChans[idxR],
409 vpdTableL[i][j], vpdTableR[i][j]));
410 }
411 }
412 }
413
414 k = 0;
415
416 for (i = 0; i < numXpdGains; i++) {
417 if (i == (numXpdGains - 1))
418 pPdGainBoundaries[i] =
419 (u16)(maxPwrT4[i] / 2);
420 else
421 pPdGainBoundaries[i] =
422 (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
423
424 pPdGainBoundaries[i] =
425 min((u16)MAX_RATE_POWER, pPdGainBoundaries[i]);
426
427 if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
428 minDelta = pPdGainBoundaries[0] - 23;
429 pPdGainBoundaries[0] = 23;
430 } else {
431 minDelta = 0;
432 }
433
434 if (i == 0) {
435 if (AR_SREV_9280_20_OR_LATER(ah))
436 ss = (int16_t)(0 - (minPwrT4[i] / 2));
437 else
438 ss = 0;
439 } else {
440 ss = (int16_t)((pPdGainBoundaries[i - 1] -
441 (minPwrT4[i] / 2)) -
442 tPdGainOverlap + 1 + minDelta);
443 }
444 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
445 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
446
447 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
448 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
449 pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
450 ss++;
451 }
452
453 sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
454 tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
455 (minPwrT4[i] / 2));
456 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
457 tgtIndex : sizeCurrVpdTable;
458
459 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
460 pPDADCValues[k++] = vpdTableI[i][ss++];
461 }
462
463 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
464 vpdTableI[i][sizeCurrVpdTable - 2]);
465 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
466
467 if (tgtIndex >= maxIndex) {
468 while ((ss <= tgtIndex) &&
469 (k < (AR5416_NUM_PDADC_VALUES - 1))) {
470 tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
471 (ss - maxIndex + 1) * vpdStep));
472 pPDADCValues[k++] = (u8)((tmpVal > 255) ?
473 255 : tmpVal);
474 ss++;
475 }
476 }
477 }
478
479 if (eeprom_4k)
480 pdgain_boundary_default = 58;
481 else
482 pdgain_boundary_default = pPdGainBoundaries[i - 1];
483
484 while (i < AR5416_PD_GAINS_IN_MASK) {
485 pPdGainBoundaries[i] = pdgain_boundary_default;
486 i++;
487 }
488
489 while (k < AR5416_NUM_PDADC_VALUES) {
490 pPDADCValues[k] = pPDADCValues[k - 1];
491 k++;
492 }
493}
494
282int ath9k_hw_eeprom_init(struct ath_hw *ah) 495int ath9k_hw_eeprom_init(struct ath_hw *ah)
283{ 496{
284 int status; 497 int status;