11 files changed, 755 insertions, 203 deletions

diff --git a/drivers/net/wireless/ath/ath5k/ath5k.h b/drivers/net/wireless/ath/ath5k/ath5k.h
index 60c6d2edc4b9..813718210338 100644
--- a/drivers/net/wireless/ath/ath5k/ath5k.h
+++ b/drivers/net/wireless/ath/ath5k/ath5k.h
@@ -209,7 +209,6 @@
 #define AR5K_TUNE_MAX_TXPOWER                   63
 #define AR5K_TUNE_DEFAULT_TXPOWER               25
 #define AR5K_TUNE_TPC_TXPOWER                   false
-#define AR5K_TUNE_ANT_DIVERSITY                 true
 #define AR5K_TUNE_HWTXTRIES                     4
 
 #define AR5K_INIT_CARR_SENSE_EN                 1
@@ -420,6 +419,17 @@ enum ath5k_driver_mode {
         AR5K_MODE_MAX           =       5
 };
 
+enum ath5k_ant_mode {
+        AR5K_ANTMODE_DEFAULT    = 0,    /* default antenna setup */
+        AR5K_ANTMODE_FIXED_A    = 1,    /* only antenna A is present */
+        AR5K_ANTMODE_FIXED_B    = 2,    /* only antenna B is present */
+        AR5K_ANTMODE_SINGLE_AP  = 3,    /* sta locked on a single ap */
+        AR5K_ANTMODE_SECTOR_AP  = 4,    /* AP with tx antenna set on tx desc */
+        AR5K_ANTMODE_SECTOR_STA = 5,    /* STA with tx antenna set on tx desc */
+        AR5K_ANTMODE_DEBUG      = 6,    /* Debug mode -A -> Rx, B-> Tx- */
+        AR5K_ANTMODE_MAX,
+};
+
 
 /****************\
   TX DEFINITIONS
@@ -1051,8 +1061,11 @@ struct ath5k_hw {
         bool                    ah_software_retry;
         u32                     ah_limit_tx_retries;
 
-        u32                     ah_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
-        bool                    ah_ant_diversity;
+        /* Antenna Control */
+        u32                     ah_ant_ctl[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
+        u8                      ah_ant_mode;
+        u8                      ah_tx_ant;
+        u8                      ah_def_ant;
 
         u8                      ah_sta_id[ETH_ALEN];
 
@@ -1100,11 +1113,12 @@ struct ath5k_hw {
                 /* Values in 0.25dB units */
                 s16             txp_min_pwr;
                 s16             txp_max_pwr;
+                /* Values in 0.5dB units */
                 s16             txp_offset;
                 s16             txp_ofdm;
-                /* Values in dB units */
-                s16             txp_cck_ofdm_pwr_delta;
                 s16             txp_cck_ofdm_gainf_delta;
+                /* Value in dB units */
+                s16             txp_cck_ofdm_pwr_delta;
         } ah_txpower;
 
         struct {
@@ -1264,14 +1278,21 @@ extern int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *chann
 /* PHY calibration */
 extern int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, struct ieee80211_channel *channel);
 extern int ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq);
+/* Spur mitigation */
+bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
+                                struct ieee80211_channel *channel);
+void ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
+                                struct ieee80211_channel *channel);
 /* Misc PHY functions */
 extern u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan);
-extern void ath5k_hw_set_def_antenna(struct ath5k_hw *ah, unsigned int ant);
-extern unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah);
 extern int ath5k_hw_phy_disable(struct ath5k_hw *ah);
+/* Antenna control */
+extern void ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode);
+extern void ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant);
+extern unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah);
 /* TX power setup */
 extern int ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel, u8 ee_mode, u8 txpower);
-extern int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 ee_mode, u8 txpower);
+extern int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower);
 
 /*
  * Functions used internaly
diff --git a/drivers/net/wireless/ath/ath5k/attach.c b/drivers/net/wireless/ath/ath5k/attach.c
index 70d376c63aac..c41ef58393e7 100644
--- a/drivers/net/wireless/ath/ath5k/attach.c
+++ b/drivers/net/wireless/ath/ath5k/attach.c
@@ -133,7 +133,6 @@ struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
         ah->ah_cw_min = AR5K_TUNE_CWMIN;
         ah->ah_limit_tx_retries = AR5K_INIT_TX_RETRY;
         ah->ah_software_retry = false;
-        ah->ah_ant_diversity = AR5K_TUNE_ANT_DIVERSITY;
 
         /*
          * Set the mac version based on the pci id
diff --git a/drivers/net/wireless/ath/ath5k/base.c b/drivers/net/wireless/ath/ath5k/base.c
index c8c658bfcf9d..6789c5dfcc76 100644
--- a/drivers/net/wireless/ath/ath5k/base.c
+++ b/drivers/net/wireless/ath/ath5k/base.c
@@ -227,9 +227,6 @@ static int ath5k_add_interface(struct ieee80211_hw *hw,
 static void ath5k_remove_interface(struct ieee80211_hw *hw,
                 struct ieee80211_if_init_conf *conf);
 static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
-static int ath5k_config_interface(struct ieee80211_hw *hw,
-                struct ieee80211_vif *vif,
-                struct ieee80211_if_conf *conf);
 static void ath5k_configure_filter(struct ieee80211_hw *hw,
                 unsigned int changed_flags,
                 unsigned int *new_flags,
@@ -259,7 +256,6 @@ static const struct ieee80211_ops ath5k_hw_ops = {
         .add_interface  = ath5k_add_interface,
         .remove_interface = ath5k_remove_interface,
         .config         = ath5k_config,
-        .config_interface = ath5k_config_interface,
         .configure_filter = ath5k_configure_filter,
         .set_key        = ath5k_set_key,
         .get_stats      = ath5k_get_stats,
@@ -520,6 +516,7 @@ ath5k_pci_probe(struct pci_dev *pdev,
                     IEEE80211_HW_NOISE_DBM;
 
         hw->wiphy->interface_modes =
+                BIT(NL80211_IFTYPE_AP) |
                 BIT(NL80211_IFTYPE_STATION) |
                 BIT(NL80211_IFTYPE_ADHOC) |
                 BIT(NL80211_IFTYPE_MESH_POINT);
@@ -1282,7 +1279,7 @@ ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
                 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
                 (sc->power_level * 2),
                 hw_rate,
-                info->control.rates[0].count, keyidx, 0, flags,
+                info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
                 cts_rate, duration);
         if (ret)
                 goto err_unmap;
@@ -1742,35 +1739,6 @@ ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
         }
 }
 
-static void ath5k_tasklet_beacon(unsigned long data)
-{
-        struct ath5k_softc *sc = (struct ath5k_softc *) data;
-
-        /*
-         * Software beacon alert--time to send a beacon.
-         *
-         * In IBSS mode we use this interrupt just to
-         * keep track of the next TBTT (target beacon
-         * transmission time) in order to detect wether
-         * automatic TSF updates happened.
-         */
-        if (sc->opmode == NL80211_IFTYPE_ADHOC) {
-                /* XXX: only if VEOL suppported */
-                u64 tsf = ath5k_hw_get_tsf64(sc->ah);
-                sc->nexttbtt += sc->bintval;
-                ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
-                                "SWBA nexttbtt: %x hw_tu: %x "
-                                "TSF: %llx\n",
-                                sc->nexttbtt,
-                                TSF_TO_TU(tsf),
-                                (unsigned long long) tsf);
-        } else {
-                spin_lock(&sc->block);
-                ath5k_beacon_send(sc);
-                spin_unlock(&sc->block);
-        }
-}
-
 static void
 ath5k_tasklet_rx(unsigned long data)
 {
@@ -2041,7 +2009,8 @@ ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
         struct  ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
         struct ath5k_hw *ah = sc->ah;
         struct ath5k_desc *ds;
-        int ret, antenna = 0;
+        int ret = 0;
+        u8 antenna;
         u32 flags;
 
         bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
@@ -2055,23 +2024,35 @@ ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
         }
 
         ds = bf->desc;
+        antenna = ah->ah_tx_ant;
 
         flags = AR5K_TXDESC_NOACK;
         if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
                 ds->ds_link = bf->daddr;        /* self-linked */
                 flags |= AR5K_TXDESC_VEOL;
-                /*
-                 * Let hardware handle antenna switching if txantenna is not set
-                 */
-        } else {
+        } else
                 ds->ds_link = 0;
-                /*
-                 * Switch antenna every 4 beacons if txantenna is not set
-                 * XXX assumes two antennas
-                 */
-                if (antenna == 0)
-                        antenna = sc->bsent & 4 ? 2 : 1;
-        }
+
+        /*
+         * If we use multiple antennas on AP and use
+         * the Sectored AP scenario, switch antenna every
+         * 4 beacons to make sure everybody hears our AP.
+         * When a client tries to associate, hw will keep
+         * track of the tx antenna to be used for this client
+         * automaticaly, based on ACKed packets.
+         *
+         * Note: AP still listens and transmits RTS on the
+         * default antenna which is supposed to be an omni.
+         *
+         * Note2: On sectored scenarios it's possible to have
+         * multiple antennas (1omni -the default- and 14 sectors)
+         * so if we choose to actually support this mode we need
+         * to allow user to set how many antennas we have and tweak
+         * the code below to send beacons on all of them.
+         */
+        if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
+                antenna = sc->bsent & 4 ? 2 : 1;
+
 
         /* FIXME: If we are in g mode and rate is a CCK rate
          * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
@@ -2124,7 +2105,7 @@ ath5k_beacon_send(struct ath5k_softc *sc)
                 sc->bmisscount++;
                 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
                         "missed %u consecutive beacons\n", sc->bmisscount);
-                if (sc->bmisscount > 3) {               /* NB: 3 is a guess */
+                if (sc->bmisscount > 10) {      /* NB: 10 is a guess */
                         ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
                                 "stuck beacon time (%u missed)\n",
                                 sc->bmisscount);
@@ -2145,10 +2126,12 @@ ath5k_beacon_send(struct ath5k_softc *sc)
          * are still pending on the queue.
          */
         if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
-                ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
+                ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
                 /* NB: hw still stops DMA, so proceed */
         }
 
+        /* Note: Beacon buffer is updated on beacon_update when mac80211
+         * calls config_interface */
         ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
         ath5k_hw_start_tx_dma(ah, sc->bhalq);
         ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
@@ -2305,6 +2288,35 @@ ath5k_beacon_config(struct ath5k_softc *sc)
         ath5k_hw_set_imr(ah, sc->imask);
 }
 
+static void ath5k_tasklet_beacon(unsigned long data)
+{
+        struct ath5k_softc *sc = (struct ath5k_softc *) data;
+
+        /*
+         * Software beacon alert--time to send a beacon.
+         *
+         * In IBSS mode we use this interrupt just to
+         * keep track of the next TBTT (target beacon
+         * transmission time) in order to detect wether
+         * automatic TSF updates happened.
+         */
+        if (sc->opmode == NL80211_IFTYPE_ADHOC) {
+                /* XXX: only if VEOL suppported */
+                u64 tsf = ath5k_hw_get_tsf64(sc->ah);
+                sc->nexttbtt += sc->bintval;
+                ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
+                                "SWBA nexttbtt: %x hw_tu: %x "
+                                "TSF: %llx\n",
+                                sc->nexttbtt,
+                                TSF_TO_TU(tsf),
+                                (unsigned long long) tsf);
+        } else {
+                spin_lock(&sc->block);
+                ath5k_beacon_send(sc);
+                spin_unlock(&sc->block);
+        }
+}
+
 
 /********************\
 * Interrupt handling *
@@ -2509,7 +2521,7 @@ ath5k_intr(int irq, void *dev_id)
                                 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
                         }
                 }
-        } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
+        } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
 
         if (unlikely(!counter))
                 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
@@ -2751,56 +2763,47 @@ static int
 ath5k_config(struct ieee80211_hw *hw, u32 changed)
 {
         struct ath5k_softc *sc = hw->priv;
+        struct ath5k_hw *ah = sc->ah;
         struct ieee80211_conf *conf = &hw->conf;
-        int ret;
+        int ret = 0;
 
         mutex_lock(&sc->lock);
 
         sc->bintval = conf->beacon_int;
-        sc->power_level = conf->power_level;
 
         ret = ath5k_chan_set(sc, conf->channel);
+        if (ret < 0)
+                return ret;
 
-        mutex_unlock(&sc->lock);
-        return ret;
-}
-
-static int
-ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
-                        struct ieee80211_if_conf *conf)
-{
-        struct ath5k_softc *sc = hw->priv;
-        struct ath5k_hw *ah = sc->ah;
-        int ret = 0;
+        if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
+        (sc->power_level != conf->power_level)) {
+                sc->power_level = conf->power_level;
 
-        mutex_lock(&sc->lock);
-        if (sc->vif != vif) {
-                ret = -EIO;
-                goto unlock;
-        }
-        if (conf->changed & IEEE80211_IFCC_BSSID && conf->bssid) {
-                /* Cache for later use during resets */
-                memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
-                /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
-                 * a clean way of letting us retrieve this yet. */
-                ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
-                mmiowb();
-        }
-        if (conf->changed & IEEE80211_IFCC_BEACON &&
-                        (vif->type == NL80211_IFTYPE_ADHOC ||
-                         vif->type == NL80211_IFTYPE_MESH_POINT ||
-                         vif->type == NL80211_IFTYPE_AP)) {
-                struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
-                if (!beacon) {
-                        ret = -ENOMEM;
-                        goto unlock;
-                }
-                ath5k_beacon_update(sc, beacon);
+                /* Half dB steps */
+                ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
         }
 
-unlock:
+        /* TODO:
+         * 1) Move this on config_interface and handle each case
+         * separately eg. when we have only one STA vif, use
+         * AR5K_ANTMODE_SINGLE_AP
+         *
+         * 2) Allow the user to change antenna mode eg. when only
+         * one antenna is present
+         *
+         * 3) Allow the user to set default/tx antenna when possible
+         *
+         * 4) Default mode should handle 90% of the cases, together
+         * with fixed a/b and single AP modes we should be able to
+         * handle 99%. Sectored modes are extreme cases and i still
+         * haven't found a usage for them. If we decide to support them,
+         * then we must allow the user to set how many tx antennas we
+         * have available
+         */
+        ath5k_hw_set_antenna_mode(ah, AR5K_ANTMODE_DEFAULT);
+
         mutex_unlock(&sc->lock);
-        return ret;
+        return 0;
 }
 
 #define SUPPORTED_FIF_FLAGS \
@@ -3083,11 +3086,40 @@ static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
                                     u32 changes)
 {
         struct ath5k_softc *sc = hw->priv;
+        struct ath5k_hw *ah = sc->ah;
+
+        mutex_lock(&sc->lock);
+        if (WARN_ON(sc->vif != vif))
+                goto unlock;
+
+        if (changes & BSS_CHANGED_BSSID) {
+                /* Cache for later use during resets */
+                memcpy(ah->ah_bssid, bss_conf->bssid, ETH_ALEN);
+                /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
+                 * a clean way of letting us retrieve this yet. */
+                ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
+                mmiowb();
+        }
+
+        if (changes & BSS_CHANGED_BEACON_INT)
+                sc->bintval = bss_conf->beacon_int;
+
         if (changes & BSS_CHANGED_ASSOC) {
-                mutex_lock(&sc->lock);
                 sc->assoc = bss_conf->assoc;
                 if (sc->opmode == NL80211_IFTYPE_STATION)
                         set_beacon_filter(hw, sc->assoc);
-                mutex_unlock(&sc->lock);
         }
+
+        if (changes & BSS_CHANGED_BEACON &&
+            (vif->type == NL80211_IFTYPE_ADHOC ||
+             vif->type == NL80211_IFTYPE_MESH_POINT ||
+             vif->type == NL80211_IFTYPE_AP)) {
+                struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
+
+                if (beacon)
+                        ath5k_beacon_update(sc, beacon);
+        }
+
+ unlock:
+        mutex_unlock(&sc->lock);
 }
diff --git a/drivers/net/wireless/ath/ath5k/eeprom.c b/drivers/net/wireless/ath/ath5k/eeprom.c
index c0fb3b09ba45..c56b494d417a 100644
--- a/drivers/net/wireless/ath/ath5k/eeprom.c
+++ b/drivers/net/wireless/ath/ath5k/eeprom.c
@@ -156,6 +156,17 @@ ath5k_eeprom_init_header(struct ath5k_hw *ah)
                 ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7;
         }
 
+        AR5K_EEPROM_READ(AR5K_EEPROM_IS_HB63, val);
+
+        if ((ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4)) && val)
+                ee->ee_is_hb63 = true;
+        else
+                ee->ee_is_hb63 = false;
+
+        AR5K_EEPROM_READ(AR5K_EEPROM_RFKILL, val);
+        ee->ee_rfkill_pin = (u8) AR5K_REG_MS(val, AR5K_EEPROM_RFKILL_GPIO_SEL);
+        ee->ee_rfkill_pol = val & AR5K_EEPROM_RFKILL_POLARITY ? true : false;
+
         return 0;
 }
 
@@ -197,16 +208,16 @@ static int ath5k_eeprom_read_ants(struct ath5k_hw *ah, u32 *offset,
         ee->ee_ant_control[mode][i++]   = (val >> 6) & 0x3f;
         ee->ee_ant_control[mode][i++]   = val & 0x3f;
 
-        /* Get antenna modes */
-        ah->ah_antenna[mode][0] =
+        /* Get antenna switch tables */
+        ah->ah_ant_ctl[mode][AR5K_ANT_CTL] =
             (ee->ee_ant_control[mode][0] << 4);
-        ah->ah_antenna[mode][AR5K_ANT_FIXED_A] =
+        ah->ah_ant_ctl[mode][AR5K_ANT_SWTABLE_A] =
              ee->ee_ant_control[mode][1]        |
             (ee->ee_ant_control[mode][2] << 6)  |
             (ee->ee_ant_control[mode][3] << 12) |
             (ee->ee_ant_control[mode][4] << 18) |
             (ee->ee_ant_control[mode][5] << 24);
-        ah->ah_antenna[mode][AR5K_ANT_FIXED_B] =
+        ah->ah_ant_ctl[mode][AR5K_ANT_SWTABLE_B] =
              ee->ee_ant_control[mode][6]        |
             (ee->ee_ant_control[mode][7] << 6)  |
             (ee->ee_ant_control[mode][8] << 12) |
@@ -640,9 +651,9 @@ ath5k_eeprom_init_11bg_2413(struct ath5k_hw *ah, unsigned int mode, int offset)
 static inline void
 ath5k_get_pcdac_intercepts(struct ath5k_hw *ah, u8 min, u8 max, u8 *vp)
 {
-        const static u16 intercepts3[] =
+        static const u16 intercepts3[] =
                 { 0, 5, 10, 20, 30, 50, 70, 85, 90, 95, 100 };
-        const static u16 intercepts3_2[] =
+        static const u16 intercepts3_2[] =
                 { 0, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100 };
         const u16 *ip;
         int i;
@@ -1694,9 +1705,40 @@ ath5k_eeprom_read_ctl_info(struct ath5k_hw *ah)
         return 0;
 }
 
+static int
+ath5k_eeprom_read_spur_chans(struct ath5k_hw *ah)
+{
+        struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
+        u32 offset;
+        u16 val;
+        int ret = 0, i;
+
+        offset = AR5K_EEPROM_CTL(ee->ee_version) +
+                                AR5K_EEPROM_N_CTLS(ee->ee_version);
+
+        if (ee->ee_version < AR5K_EEPROM_VERSION_5_3) {
+                /* No spur info for 5GHz */
+                ee->ee_spur_chans[0][0] = AR5K_EEPROM_NO_SPUR;
+                /* 2 channels for 2GHz (2464/2420) */
+                ee->ee_spur_chans[0][1] = AR5K_EEPROM_5413_SPUR_CHAN_1;
+                ee->ee_spur_chans[1][1] = AR5K_EEPROM_5413_SPUR_CHAN_2;
+                ee->ee_spur_chans[2][1] = AR5K_EEPROM_NO_SPUR;
+        } else if (ee->ee_version >= AR5K_EEPROM_VERSION_5_3) {
+                for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) {
+                        AR5K_EEPROM_READ(offset, val);
+                        ee->ee_spur_chans[i][0] = val;
+                        AR5K_EEPROM_READ(offset + AR5K_EEPROM_N_SPUR_CHANS,
+                                                                        val);
+                        ee->ee_spur_chans[i][1] = val;
+                        offset++;
+                }
+        }
+
+        return ret;
+}
 
 /*
- * Initialize eeprom power tables
+ * Initialize eeprom data structure
  */
 int
 ath5k_eeprom_init(struct ath5k_hw *ah)
@@ -1719,6 +1761,10 @@ ath5k_eeprom_init(struct ath5k_hw *ah)
         if (err < 0)
                 return err;
 
+        err = ath5k_eeprom_read_spur_chans(ah);
+        if (err < 0)
+                return err;
+
         return 0;
 }
 
@@ -1754,16 +1800,3 @@ int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac)
 
         return 0;
 }
-
-bool ath5k_eeprom_is_hb63(struct ath5k_hw *ah)
-{
-        u16 data;
-
-        ath5k_hw_eeprom_read(ah, AR5K_EEPROM_IS_HB63, &data);
-
-        if ((ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4)) && data)
-                return true;
-        else
-                return false;
-}
-
diff --git a/drivers/net/wireless/ath/ath5k/eeprom.h b/drivers/net/wireless/ath/ath5k/eeprom.h
index b0c0606dea0b..64be73a5edae 100644
--- a/drivers/net/wireless/ath/ath5k/eeprom.h
+++ b/drivers/net/wireless/ath/ath5k/eeprom.h
@@ -26,6 +26,13 @@
 #define AR5K_EEPROM_MAGIC_5210          0x0000145a /* 5210 */
 
 #define AR5K_EEPROM_IS_HB63             0x000b  /* Talon detect */
+
+#define AR5K_EEPROM_RFKILL              0x0f
+#define AR5K_EEPROM_RFKILL_GPIO_SEL     0x0000001c
+#define AR5K_EEPROM_RFKILL_GPIO_SEL_S   2
+#define AR5K_EEPROM_RFKILL_POLARITY     0x00000002
+#define AR5K_EEPROM_RFKILL_POLARITY_S   1
+
 #define AR5K_EEPROM_REG_DOMAIN          0x00bf  /* EEPROM regdom */
 #define AR5K_EEPROM_CHECKSUM            0x00c0  /* EEPROM checksum */
 #define AR5K_EEPROM_INFO_BASE           0x00c0  /* EEPROM header */
@@ -66,11 +73,6 @@
 #define AR5K_EEPROM_HDR_RFKILL(_v)      (((_v) >> 14) & 0x1)    /* Device has RFKill support */
 #define AR5K_EEPROM_HDR_T_5GHZ_DIS(_v)  (((_v) >> 15) & 0x1)    /* Disable turbo for 5Ghz */
 
-#define AR5K_EEPROM_RFKILL_GPIO_SEL     0x0000001c
-#define AR5K_EEPROM_RFKILL_GPIO_SEL_S   2
-#define AR5K_EEPROM_RFKILL_POLARITY     0x00000002
-#define AR5K_EEPROM_RFKILL_POLARITY_S   1
-
 /* Newer EEPROMs are using a different offset */
 #define AR5K_EEPROM_OFF(_v, _v3_0, _v3_3) \
         (((_v) >= AR5K_EEPROM_VERSION_3_3) ? _v3_3 : _v3_0)
@@ -211,6 +213,23 @@
 #define AR5K_EEPROM_I_GAIN              10
 #define AR5K_EEPROM_CCK_OFDM_DELTA      15
 #define AR5K_EEPROM_N_IQ_CAL            2
+/* 5GHz/2GHz */
+enum ath5k_eeprom_freq_bands{
+        AR5K_EEPROM_BAND_5GHZ = 0,
+        AR5K_EEPROM_BAND_2GHZ = 1,
+        AR5K_EEPROM_N_FREQ_BANDS,
+};
+/* Spur chans per freq band */
+#define AR5K_EEPROM_N_SPUR_CHANS        5
+/* fbin value for chan 2464 x2 */
+#define AR5K_EEPROM_5413_SPUR_CHAN_1    1640
+/* fbin value for chan 2420 x2 */
+#define AR5K_EEPROM_5413_SPUR_CHAN_2    1200
+#define AR5K_EEPROM_SPUR_CHAN_MASK      0x3FFF
+#define AR5K_EEPROM_NO_SPUR             0x8000
+#define AR5K_SPUR_CHAN_WIDTH                    87
+#define AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz       3125
+#define AR5K_SPUR_SYMBOL_WIDTH_TURBO_100Hz      6250
 
 #define AR5K_EEPROM_READ(_o, _v) do {                   \
         ret = ath5k_hw_eeprom_read(ah, (_o), &(_v));    \
@@ -221,11 +240,11 @@
 #define AR5K_EEPROM_READ_HDR(_o, _v)                                    \
         AR5K_EEPROM_READ(_o, ah->ah_capabilities.cap_eeprom._v);        \
 
-enum ath5k_ant_setting {
-        AR5K_ANT_VARIABLE       = 0,    /* variable by programming */
-        AR5K_ANT_FIXED_A        = 1,    /* fixed to 11a frequencies */
-        AR5K_ANT_FIXED_B        = 2,    /* fixed to 11b frequencies */
-        AR5K_ANT_MAX            = 3,
+enum ath5k_ant_table {
+        AR5K_ANT_CTL            = 0,    /* Idle switch table settings */
+        AR5K_ANT_SWTABLE_A      = 1,    /* Switch table for antenna A */
+        AR5K_ANT_SWTABLE_B      = 2,    /* Switch table for antenna B */
+        AR5K_ANT_MAX,
 };
 
 enum ath5k_ctl_mode {
@@ -369,6 +388,9 @@ struct ath5k_eeprom_info {
         u16     ee_version;
         u16     ee_header;
         u16     ee_ant_gain;
+        u8      ee_rfkill_pin;
+        bool    ee_rfkill_pol;
+        bool    ee_is_hb63;
         u16     ee_misc0;
         u16     ee_misc1;
         u16     ee_misc2;
@@ -436,6 +458,10 @@ struct ath5k_eeprom_info {
         s8      ee_pga_desired_size_turbo[AR5K_EEPROM_N_MODES];
         s8      ee_pd_gain_overlap;
 
+        /* Spur mitigation data (fbin values for spur channels) */
+        u16     ee_spur_chans[AR5K_EEPROM_N_SPUR_CHANS][AR5K_EEPROM_N_FREQ_BANDS];
+
+        /* Antenna raw switch tables */
         u32     ee_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
 };
 
diff --git a/drivers/net/wireless/ath/ath5k/led.c b/drivers/net/wireless/ath/ath5k/led.c
index cbdc0b308429..876725f08b6c 100644
--- a/drivers/net/wireless/ath/ath5k/led.c
+++ b/drivers/net/wireless/ath/ath5k/led.c
@@ -53,8 +53,6 @@
 
 /* Devices we match on for LED config info (typically laptops) */
 static const struct pci_device_id ath5k_led_devices[] = {
-        /* IBM-specific AR5212 */
-        { PCI_VDEVICE(ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5212_IBM), ATH_LED(0, 0) },
         /* AR5211 */
         { PCI_VDEVICE(ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5211), ATH_LED(0, 0) },
         /* HP Compaq nc6xx, nc4000, nx6000 */
@@ -69,6 +67,10 @@ static const struct pci_device_id ath5k_led_devices[] = {
         { ATH_SDEVICE(PCI_VENDOR_ID_QMI, 0x0105), ATH_LED(3, 0) },
         /* Fukato Datacask Jupiter 1014a (mrb74@gmx.at) */
         { ATH_SDEVICE(PCI_VENDOR_ID_AZWAVE, 0x1026), ATH_LED(3, 0) },
+        /* IBM ThinkPad AR5BXB6 (legovini@spiro.fisica.unipd.it) */
+        { ATH_SDEVICE(PCI_VENDOR_ID_IBM, 0x058a), ATH_LED(1, 0) },
+        /* IBM-specific AR5212 (all others) */
+        { PCI_VDEVICE(ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5212_IBM), ATH_LED(0, 0) },
         { }
 };
 
diff --git a/drivers/net/wireless/ath/ath5k/pcu.c b/drivers/net/wireless/ath/ath5k/pcu.c
index 55122f1e1986..579aa0a96ab8 100644
--- a/drivers/net/wireless/ath/ath5k/pcu.c
+++ b/drivers/net/wireless/ath/ath5k/pcu.c
@@ -736,8 +736,8 @@ void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval)
         /* When in AP mode zero timer0 to start TSF */
         if (ah->ah_op_mode == NL80211_IFTYPE_AP)
                 ath5k_hw_reg_write(ah, 0, AR5K_TIMER0);
-        else
-                ath5k_hw_reg_write(ah, next_beacon, AR5K_TIMER0);
+
+        ath5k_hw_reg_write(ah, next_beacon, AR5K_TIMER0);
         ath5k_hw_reg_write(ah, timer1, AR5K_TIMER1);
         ath5k_hw_reg_write(ah, timer2, AR5K_TIMER2);
         ath5k_hw_reg_write(ah, timer3, AR5K_TIMER3);
@@ -1003,7 +1003,7 @@ int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry)
          * Note2: Windows driver (ndiswrapper) sets this to
          *        0x00000714 instead of 0x00000007
          */
-        if (ah->ah_version > AR5K_AR5211) {
+        if (ah->ah_version >= AR5K_AR5211) {
                 ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL,
                                 AR5K_KEYTABLE_TYPE(entry));
 
diff --git a/drivers/net/wireless/ath/ath5k/phy.c b/drivers/net/wireless/ath/ath5k/phy.c
index b48b29dca3d2..d0d1c350025a 100644
--- a/drivers/net/wireless/ath/ath5k/phy.c
+++ b/drivers/net/wireless/ath/ath5k/phy.c
@@ -168,9 +168,6 @@ int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah)
  * tx power and a Peak to Average Power Detector (PAPD) will try
  * to measure the gain.
  *
- * TODO: Use propper tx power setting for the probe packet so
- * that we don't observe a serious power drop on the receiver
- *
  * XXX:  How about forcing a tx packet (bypassing PCU arbitrator etc)
  * just after we enable the probe so that we don't mess with
  * standard traffic ? Maybe it's time to use sw interrupts and
@@ -186,7 +183,7 @@ static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah)
 
         /* Send the packet with 2dB below max power as
          * patent doc suggest */
-        ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_max_pwr - 4,
+        ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_ofdm - 4,
                         AR5K_PHY_PAPD_PROBE_TXPOWER) |
                         AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE);
 
@@ -1356,6 +1353,257 @@ int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
         return ret;
 }
 
+/***************************\
+* Spur mitigation functions *
+\***************************/
+
+bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
+                                struct ieee80211_channel *channel)
+{
+        u8 refclk_freq;
+
+        if ((ah->ah_radio == AR5K_RF5112) ||
+        (ah->ah_radio == AR5K_RF5413) ||
+        (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
+                refclk_freq = 40;
+        else
+                refclk_freq = 32;
+
+        if ((channel->center_freq % refclk_freq != 0) &&
+        ((channel->center_freq % refclk_freq < 10) ||
+        (channel->center_freq % refclk_freq > 22)))
+                return true;
+        else
+                return false;
+}
+
+void
+ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
+                                struct ieee80211_channel *channel)
+{
+        struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
+        u32 mag_mask[4] = {0, 0, 0, 0};
+        u32 pilot_mask[2] = {0, 0};
+        /* Note: fbin values are scaled up by 2 */
+        u16 spur_chan_fbin, chan_fbin, symbol_width, spur_detection_window;
+        s32 spur_delta_phase, spur_freq_sigma_delta;
+        s32 spur_offset, num_symbols_x16;
+        u8 num_symbol_offsets, i, freq_band;
+
+        /* Convert current frequency to fbin value (the same way channels
+         * are stored on EEPROM, check out ath5k_eeprom_bin2freq) and scale
+         * up by 2 so we can compare it later */
+        if (channel->hw_value & CHANNEL_2GHZ) {
+                chan_fbin = (channel->center_freq - 2300) * 10;
+                freq_band = AR5K_EEPROM_BAND_2GHZ;
+        } else {
+                chan_fbin = (channel->center_freq - 4900) * 10;
+                freq_band = AR5K_EEPROM_BAND_5GHZ;
+        }
+
+        /* Check if any spur_chan_fbin from EEPROM is
+         * within our current channel's spur detection range */
+        spur_chan_fbin = AR5K_EEPROM_NO_SPUR;
+        spur_detection_window = AR5K_SPUR_CHAN_WIDTH;
+        /* XXX: Half/Quarter channels ?*/
+        if (channel->hw_value & CHANNEL_TURBO)
+                spur_detection_window *= 2;
+
+        for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) {
+                spur_chan_fbin = ee->ee_spur_chans[i][freq_band];
+
+                /* Note: mask cleans AR5K_EEPROM_NO_SPUR flag
+                 * so it's zero if we got nothing from EEPROM */
+                if (spur_chan_fbin == AR5K_EEPROM_NO_SPUR) {
+                        spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK;
+                        break;
+                }
+
+                if ((chan_fbin - spur_detection_window <=
+                (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK)) &&
+                (chan_fbin + spur_detection_window >=
+                (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK))) {
+                        spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK;
+                        break;
+                }
+        }
+
+        /* We need to enable spur filter for this channel */
+        if (spur_chan_fbin) {
+                spur_offset = spur_chan_fbin - chan_fbin;
+                /*
+                 * Calculate deltas:
+                 * spur_freq_sigma_delta -> spur_offset / sample_freq << 21
+                 * spur_delta_phase -> spur_offset / chip_freq << 11
+                 * Note: Both values have 100KHz resolution
+                 */
+                /* XXX: Half/Quarter rate channels ? */
+                switch (channel->hw_value) {
+                case CHANNEL_A:
+                        /* Both sample_freq and chip_freq are 40MHz */
+                        spur_delta_phase = (spur_offset << 17) / 25;
+                        spur_freq_sigma_delta = (spur_delta_phase >> 10);
+                        symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
+                        break;
+                case CHANNEL_G:
+                        /* sample_freq -> 40MHz chip_freq -> 44MHz
+                         * (for b compatibility) */
+                        spur_freq_sigma_delta = (spur_offset << 8) / 55;
+                        spur_delta_phase = (spur_offset << 17) / 25;
+                        symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
+                        break;
+                case CHANNEL_T:
+                case CHANNEL_TG:
+                        /* Both sample_freq and chip_freq are 80MHz */
+                        spur_delta_phase = (spur_offset << 16) / 25;
+                        spur_freq_sigma_delta = (spur_delta_phase >> 10);
+                        symbol_width = AR5K_SPUR_SYMBOL_WIDTH_TURBO_100Hz;
+                        break;
+                default:
+                        return;
+                }
+
+                /* Calculate pilot and magnitude masks */
+
+                /* Scale up spur_offset by 1000 to switch to 100HZ resolution
+                 * and divide by symbol_width to find how many symbols we have
+                 * Note: number of symbols is scaled up by 16 */
+                num_symbols_x16 = ((spur_offset * 1000) << 4) / symbol_width;
+
+                /* Spur is on a symbol if num_symbols_x16 % 16 is zero */
+                if (!(num_symbols_x16 & 0xF))
+                        /* _X_ */
+                        num_symbol_offsets = 3;
+                else
+                        /* _xx_ */
+                        num_symbol_offsets = 4;
+
+                for (i = 0; i < num_symbol_offsets; i++) {
+
+                        /* Calculate pilot mask */
+                        s32 curr_sym_off =
+                                (num_symbols_x16 / 16) + i + 25;
+
+                        /* Pilot magnitude mask seems to be a way to
+                         * declare the boundaries for our detection
+                         * window or something, it's 2 for the middle
+                         * value(s) where the symbol is expected to be
+                         * and 1 on the boundary values */
+                        u8 plt_mag_map =
+                                (i == 0 || i == (num_symbol_offsets - 1))
+                                                                ? 1 : 2;
+
+                        if (curr_sym_off >= 0 && curr_sym_off <= 32) {
+                                if (curr_sym_off <= 25)
+                                        pilot_mask[0] |= 1 << curr_sym_off;
+                                else if (curr_sym_off >= 27)
+                                        pilot_mask[0] |= 1 << (curr_sym_off - 1);
+                        } else if (curr_sym_off >= 33 && curr_sym_off <= 52)
+                                pilot_mask[1] |= 1 << (curr_sym_off - 33);
+
+                        /* Calculate magnitude mask (for viterbi decoder) */
+                        if (curr_sym_off >= -1 && curr_sym_off <= 14)
+                                mag_mask[0] |=
+                                        plt_mag_map << (curr_sym_off + 1) * 2;
+                        else if (curr_sym_off >= 15 && curr_sym_off <= 30)
+                                mag_mask[1] |=
+                                        plt_mag_map << (curr_sym_off - 15) * 2;
+                        else if (curr_sym_off >= 31 && curr_sym_off <= 46)
+                                mag_mask[2] |=
+                                        plt_mag_map << (curr_sym_off - 31) * 2;
+                        else if (curr_sym_off >= 46 && curr_sym_off <= 53)
+                                mag_mask[3] |=
+                                        plt_mag_map << (curr_sym_off - 47) * 2;
+
+                }
+
+                /* Write settings on hw to enable spur filter */
+                AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
+                                        AR5K_PHY_BIN_MASK_CTL_RATE, 0xff);
+                /* XXX: Self correlator also ? */
+                AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
+                                        AR5K_PHY_IQ_PILOT_MASK_EN |
+                                        AR5K_PHY_IQ_CHAN_MASK_EN |
+                                        AR5K_PHY_IQ_SPUR_FILT_EN);
+
+                /* Set delta phase and freq sigma delta */
+                ath5k_hw_reg_write(ah,
+                                AR5K_REG_SM(spur_delta_phase,
+                                        AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE) |
+                                AR5K_REG_SM(spur_freq_sigma_delta,
+                                AR5K_PHY_TIMING_11_SPUR_FREQ_SD) |
+                                AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC,
+                                AR5K_PHY_TIMING_11);
+
+                /* Write pilot masks */
+                ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_7);
+                AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8,
+                                        AR5K_PHY_TIMING_8_PILOT_MASK_2,
+                                        pilot_mask[1]);
+
+                ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_9);
+                AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10,
+                                        AR5K_PHY_TIMING_10_PILOT_MASK_2,
+                                        pilot_mask[1]);
+
+                /* Write magnitude masks */
+                ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK_1);
+                ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK_2);
+                ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK_3);
+                AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
+                                        AR5K_PHY_BIN_MASK_CTL_MASK_4,
+                                        mag_mask[3]);
+
+                ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK2_1);
+                ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK2_2);
+                ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK2_3);
+                AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4,
+                                        AR5K_PHY_BIN_MASK2_4_MASK_4,
+                                        mag_mask[3]);
+
+        } else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) &
+        AR5K_PHY_IQ_SPUR_FILT_EN) {
+                /* Clean up spur mitigation settings and disable fliter */
+                AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
+                                        AR5K_PHY_BIN_MASK_CTL_RATE, 0);
+                AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_IQ,
+                                        AR5K_PHY_IQ_PILOT_MASK_EN |
+                                        AR5K_PHY_IQ_CHAN_MASK_EN |
+                                        AR5K_PHY_IQ_SPUR_FILT_EN);
+                ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_11);
+
+                /* Clear pilot masks */
+                ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_7);
+                AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8,
+                                        AR5K_PHY_TIMING_8_PILOT_MASK_2,
+                                        0);
+
+                ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_9);
+                AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10,
+                                        AR5K_PHY_TIMING_10_PILOT_MASK_2,
+                                        0);
+
+                /* Clear magnitude masks */
+                ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_1);
+                ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_2);
+                ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_3);
+                AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
+                                        AR5K_PHY_BIN_MASK_CTL_MASK_4,
+                                        0);
+
+                ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_1);
+                ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_2);
+                ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_3);
+                AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4,
+                                        AR5K_PHY_BIN_MASK2_4_MASK_4,
+                                        0);
+        }
+}
+
+/********************\
+  Misc PHY functions
+\********************/
+
 int ath5k_hw_phy_disable(struct ath5k_hw *ah)
 {
         ATH5K_TRACE(ah->ah_sc);
@@ -1365,10 +1613,6 @@ int ath5k_hw_phy_disable(struct ath5k_hw *ah)
         return 0;
 }
 
-/********************\
-  Misc PHY functions
-\********************/
-
 /*
  * Get the PHY Chip revision
  */
@@ -1417,25 +1661,189 @@ u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
         return ret;
 }
 
+/*****************\
+* Antenna control *
+\*****************/
+
 void /*TODO:Boundary check*/
-ath5k_hw_set_def_antenna(struct ath5k_hw *ah, unsigned int ant)
+ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant)
 {
         ATH5K_TRACE(ah->ah_sc);
-        /*Just a try M.F.*/
+
         if (ah->ah_version != AR5K_AR5210)
-                ath5k_hw_reg_write(ah, ant, AR5K_DEFAULT_ANTENNA);
+                ath5k_hw_reg_write(ah, ant & 0x7, AR5K_DEFAULT_ANTENNA);
 }
 
 unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah)
 {
         ATH5K_TRACE(ah->ah_sc);
-        /*Just a try M.F.*/
+
         if (ah->ah_version != AR5K_AR5210)
-                return ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA);
+                return ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA) & 0x7;
 
         return false; /*XXX: What do we return for 5210 ?*/
 }
 
+/*
+ * Enable/disable fast rx antenna diversity
+ */
+static void
+ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable)
+{
+        switch (ee_mode) {
+        case AR5K_EEPROM_MODE_11G:
+                /* XXX: This is set to
+                 * disabled on initvals !!! */
+        case AR5K_EEPROM_MODE_11A:
+                if (enable)
+                        AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGCCTL,
+                                        AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
+                else
+                        AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
+                                        AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
+                break;
+        case AR5K_EEPROM_MODE_11B:
+                AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
+                                        AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
+                break;
+        default:
+                return;
+        }
+
+        if (enable) {
+                AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
+                                AR5K_PHY_RESTART_DIV_GC, 0xc);
+
+                AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
+                                        AR5K_PHY_FAST_ANT_DIV_EN);
+        } else {
+                AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
+                                AR5K_PHY_RESTART_DIV_GC, 0x8);
+
+                AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
+                                        AR5K_PHY_FAST_ANT_DIV_EN);
+        }
+}
+
+/*
+ * Set antenna operating mode
+ */
+void
+ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode)
+{
+        struct ieee80211_channel *channel = &ah->ah_current_channel;
+        bool use_def_for_tx, update_def_on_tx, use_def_for_rts, fast_div;
+        bool use_def_for_sg;
+        u8 def_ant, tx_ant, ee_mode;
+        u32 sta_id1 = 0;
+
+        def_ant = ah->ah_def_ant;
+
+        ATH5K_TRACE(ah->ah_sc);
+
+        switch (channel->hw_value & CHANNEL_MODES) {
+        case CHANNEL_A:
+        case CHANNEL_T:
+        case CHANNEL_XR:
+                ee_mode = AR5K_EEPROM_MODE_11A;
+                break;
+        case CHANNEL_G:
+        case CHANNEL_TG:
+                ee_mode = AR5K_EEPROM_MODE_11G;
+                break;
+        case CHANNEL_B:
+                ee_mode = AR5K_EEPROM_MODE_11B;
+                break;
+        default:
+                ATH5K_ERR(ah->ah_sc,
+                        "invalid channel: %d\n", channel->center_freq);
+                return;
+        }
+
+        switch (ant_mode) {
+        case AR5K_ANTMODE_DEFAULT:
+                tx_ant = 0;
+                use_def_for_tx = false;
+                update_def_on_tx = false;
+                use_def_for_rts = false;
+                use_def_for_sg = false;
+                fast_div = true;
+                break;
+        case AR5K_ANTMODE_FIXED_A:
+                def_ant = 1;
+                tx_ant = 0;
+                use_def_for_tx = true;
+                update_def_on_tx = false;
+                use_def_for_rts = true;
+                use_def_for_sg = true;
+                fast_div = false;
+                break;
+        case AR5K_ANTMODE_FIXED_B:
+                def_ant = 2;
+                tx_ant = 0;
+                use_def_for_tx = true;
+                update_def_on_tx = false;
+                use_def_for_rts = true;
+                use_def_for_sg = true;
+                fast_div = false;
+                break;
+        case AR5K_ANTMODE_SINGLE_AP:
+                def_ant = 1;    /* updated on tx */
+                tx_ant = 0;
+                use_def_for_tx = true;
+                update_def_on_tx = true;
+                use_def_for_rts = true;
+                use_def_for_sg = true;
+                fast_div = true;
+                break;
+        case AR5K_ANTMODE_SECTOR_AP:
+                tx_ant = 1;     /* variable */
+                use_def_for_tx = false;
+                update_def_on_tx = false;
+                use_def_for_rts = true;
+                use_def_for_sg = false;
+                fast_div = false;
+                break;
+        case AR5K_ANTMODE_SECTOR_STA:
+                tx_ant = 1;     /* variable */
+                use_def_for_tx = true;
+                update_def_on_tx = false;
+                use_def_for_rts = true;
+                use_def_for_sg = false;
+                fast_div = true;
+                break;
+        case AR5K_ANTMODE_DEBUG:
+                def_ant = 1;
+                tx_ant = 2;
+                use_def_for_tx = false;
+                update_def_on_tx = false;
+                use_def_for_rts = false;
+                use_def_for_sg = false;
+                fast_div = false;
+                break;
+        default:
+                return;
+        }
+
+        ah->ah_tx_ant = tx_ant;
+        ah->ah_ant_mode = ant_mode;
+
+        sta_id1 |= use_def_for_tx ? AR5K_STA_ID1_DEFAULT_ANTENNA : 0;
+        sta_id1 |= update_def_on_tx ? AR5K_STA_ID1_DESC_ANTENNA : 0;
+        sta_id1 |= use_def_for_rts ? AR5K_STA_ID1_RTS_DEF_ANTENNA : 0;
+        sta_id1 |= use_def_for_sg ? AR5K_STA_ID1_SELFGEN_DEF_ANT : 0;
+
+        AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_ANTENNA_SETTINGS);
+
+        if (sta_id1)
+                AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, sta_id1);
+
+        /* Note: set diversity before default antenna
+         * because it won't work correctly */
+        ath5k_hw_set_fast_div(ah, ee_mode, fast_div);
+        ath5k_hw_set_def_antenna(ah, def_ant);
+}
+
 
 /****************\
 * TX power setup *
@@ -1750,8 +2158,6 @@ done:
  * Get the max edge power for this channel if
  * we have such data from EEPROM's Conformance Test
  * Limits (CTL), and limit max power if needed.
- *
- * FIXME: Only works for world regulatory domains
  */
 static void
 ath5k_get_max_ctl_power(struct ath5k_hw *ah,
@@ -1767,26 +2173,23 @@ ath5k_get_max_ctl_power(struct ath5k_hw *ah,
         u8 ctl_idx = 0xFF;
         u32 target = channel->center_freq;
 
-        /* Find out a CTL for our mode that's not mapped
-         * on a specific reg domain.
-         *
-         * TODO: Map our current reg domain to one of the 3 available
-         * reg domain ids so that we can support more CTLs. */
+        ctl_mode = ath_regd_get_band_ctl(&ah->ah_regulatory, channel->band);
+
         switch (channel->hw_value & CHANNEL_MODES) {
         case CHANNEL_A:
-                ctl_mode = AR5K_CTL_11A | AR5K_CTL_NO_REGDOMAIN;
+                ctl_mode |= AR5K_CTL_11A;
                 break;
         case CHANNEL_G:
-                ctl_mode = AR5K_CTL_11G | AR5K_CTL_NO_REGDOMAIN;
+                ctl_mode |= AR5K_CTL_11G;
                 break;
         case CHANNEL_B:
-                ctl_mode = AR5K_CTL_11B | AR5K_CTL_NO_REGDOMAIN;
+                ctl_mode |= AR5K_CTL_11B;
                 break;
         case CHANNEL_T:
-                ctl_mode = AR5K_CTL_TURBO | AR5K_CTL_NO_REGDOMAIN;
+                ctl_mode |= AR5K_CTL_TURBO;
                 break;
         case CHANNEL_TG:
-                ctl_mode = AR5K_CTL_TURBOG | AR5K_CTL_NO_REGDOMAIN;
+                ctl_mode |= AR5K_CTL_TURBOG;
                 break;
         case CHANNEL_XR:
                 /* Fall through */
@@ -2482,8 +2885,19 @@ ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr,
                 for (i = 8; i <= 15; i++)
                         rates[i] -= ah->ah_txpower.txp_cck_ofdm_gainf_delta;
 
-        ah->ah_txpower.txp_min_pwr = rates[7];
-        ah->ah_txpower.txp_max_pwr = rates[0];
+        /* Now that we have all rates setup use table offset to
+         * match the power range set by user with the power indices
+         * on PCDAC/PDADC table */
+        for (i = 0; i < 16; i++) {
+                rates[i] += ah->ah_txpower.txp_offset;
+                /* Don't get out of bounds */
+                if (rates[i] > 63)
+                        rates[i] = 63;
+        }
+
+        /* Min/max in 0.25dB units */
+        ah->ah_txpower.txp_min_pwr = 2 * rates[7];
+        ah->ah_txpower.txp_max_pwr = 2 * rates[0];
         ah->ah_txpower.txp_ofdm = rates[7];
 }
 
@@ -2591,16 +3005,37 @@ ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
         return 0;
 }
 
-int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 mode, u8 txpower)
+int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower)
 {
         /*Just a try M.F.*/
         struct ieee80211_channel *channel = &ah->ah_current_channel;
+        u8 ee_mode;
 
         ATH5K_TRACE(ah->ah_sc);
+
+        switch (channel->hw_value & CHANNEL_MODES) {
+        case CHANNEL_A:
+        case CHANNEL_T:
+        case CHANNEL_XR:
+                ee_mode = AR5K_EEPROM_MODE_11A;
+                break;
+        case CHANNEL_G:
+        case CHANNEL_TG:
+                ee_mode = AR5K_EEPROM_MODE_11G;
+                break;
+        case CHANNEL_B:
+                ee_mode = AR5K_EEPROM_MODE_11B;
+                break;
+        default:
+                ATH5K_ERR(ah->ah_sc,
+                        "invalid channel: %d\n", channel->center_freq);
+                return -EINVAL;
+        }
+
         ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER,
                 "changing txpower to %d\n", txpower);
 
-        return ath5k_hw_txpower(ah, channel, mode, txpower);
+        return ath5k_hw_txpower(ah, channel, ee_mode, txpower);
 }
 
 #undef _ATH5K_PHY
diff --git a/drivers/net/wireless/ath/ath5k/qcu.c b/drivers/net/wireless/ath/ath5k/qcu.c
index 5094c394a4b2..73407b3f53ef 100644
--- a/drivers/net/wireless/ath/ath5k/qcu.c
+++ b/drivers/net/wireless/ath/ath5k/qcu.c
@@ -160,7 +160,8 @@ u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue)
         if (ah->ah_version == AR5K_AR5210)
                 return false;
 
-        pending = (AR5K_QUEUE_STATUS(queue) & AR5K_QCU_STS_FRMPENDCNT);
+        pending = ath5k_hw_reg_read(ah, AR5K_QUEUE_STATUS(queue));
+        pending &= AR5K_QCU_STS_FRMPENDCNT;
 
         /* It's possible to have no frames pending even if TXE
          * is set. To indicate that q has not stopped return
@@ -401,14 +402,16 @@ int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
                         AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
                                 (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL <<
                                 AR5K_DCU_MISC_ARBLOCK_CTL_S) |
+                                AR5K_DCU_MISC_ARBLOCK_IGNORE |
                                 AR5K_DCU_MISC_POST_FR_BKOFF_DIS |
                                 AR5K_DCU_MISC_BCN_ENABLE);
                         break;
 
                 case AR5K_TX_QUEUE_CAB:
                         AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
-                                AR5K_QCU_MISC_FRSHED_DBA_GT |
+                                AR5K_QCU_MISC_FRSHED_BCN_SENT_GT |
                                 AR5K_QCU_MISC_CBREXP_DIS |
+                                AR5K_QCU_MISC_RDY_VEOL_POLICY |
                                 AR5K_QCU_MISC_CBREXP_BCN_DIS);
 
                         ath5k_hw_reg_write(ah, ((AR5K_TUNE_BEACON_INTERVAL -
diff --git a/drivers/net/wireless/ath/ath5k/reg.h b/drivers/net/wireless/ath/ath5k/reg.h
index 7070d1543cdc..6809b54a2ad7 100644
--- a/drivers/net/wireless/ath/ath5k/reg.h
+++ b/drivers/net/wireless/ath/ath5k/reg.h
@@ -1148,6 +1148,11 @@
 #define AR5K_STA_ID1_CBCIV_ENDIAN       0x40000000      /* ??? */
 #define AR5K_STA_ID1_KEYSRCH_MCAST      0x80000000      /* Do key cache search for mcast frames */
 
+#define AR5K_STA_ID1_ANTENNA_SETTINGS   (AR5K_STA_ID1_DEFAULT_ANTENNA | \
+                                        AR5K_STA_ID1_DESC_ANTENNA | \
+                                        AR5K_STA_ID1_RTS_DEF_ANTENNA | \
+                                        AR5K_STA_ID1_SELFGEN_DEF_ANT)
+
 /*
  * First BSSID register (MAC address, lower 32bits)
  */
@@ -2028,7 +2033,9 @@
 #define AR5K_PHY_AGCCTL                 0x9860                  /* Register address */
 #define AR5K_PHY_AGCCTL_CAL             0x00000001      /* Enable PHY calibration */
 #define AR5K_PHY_AGCCTL_NF              0x00000002      /* Enable Noise Floor calibration */
+#define AR5K_PHY_AGCCTL_OFDM_DIV_DIS    0x00000008      /* Disable antenna diversity on OFDM modes */
 #define AR5K_PHY_AGCCTL_NF_EN           0x00008000      /* Enable nf calibration to happen (?) */
+#define AR5K_PHY_AGCTL_FLTR_CAL         0x00010000      /* Allow filter calibration (?) */
 #define AR5K_PHY_AGCCTL_NF_NOUPDATE     0x00020000      /* Don't update nf automaticaly */
 
 /*
@@ -2528,7 +2535,7 @@
  * PHY CCK Cross-correlator Barker RSSI threshold register [5212+]
  */
 #define AR5K_PHY_CCK_CROSSCORR                  0xa208
-#define AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR     0x0000000f
+#define AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR     0x0000003f
 #define AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR_S   0
 
 /* Same address is used for antenna diversity activation */
diff --git a/drivers/net/wireless/ath/ath5k/reset.c b/drivers/net/wireless/ath/ath5k/reset.c
index 775fdf78554b..c1862f8a2e7b 100644
--- a/drivers/net/wireless/ath/ath5k/reset.c
+++ b/drivers/net/wireless/ath/ath5k/reset.c
@@ -507,7 +507,7 @@ static void ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable)
 
                 if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))
                         scal = AR5K_PHY_SCAL_32MHZ_2417;
-                else if (ath5k_eeprom_is_hb63(ah))
+                else if (ee->ee_is_hb63)
                         scal = AR5K_PHY_SCAL_32MHZ_HB63;
                 else
                         scal = AR5K_PHY_SCAL_32MHZ;
@@ -536,26 +536,6 @@ static void ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable)
         return;
 }
 
-static bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
-                                struct ieee80211_channel *channel)
-{
-        u8 refclk_freq;
-
-        if ((ah->ah_radio == AR5K_RF5112) ||
-        (ah->ah_radio == AR5K_RF5413) ||
-        (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
-                refclk_freq = 40;
-        else
-                refclk_freq = 32;
-
-        if ((channel->center_freq % refclk_freq != 0) &&
-        ((channel->center_freq % refclk_freq < 10) ||
-        (channel->center_freq % refclk_freq > 22)))
-                return true;
-        else
-                return false;
-}
-
 /* TODO: Half/Quarter rate */
 static void ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah,
                                 struct ieee80211_channel *channel)
@@ -598,9 +578,10 @@ static void ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah,
         /* Set DAC/ADC delays */
         if (ah->ah_version == AR5K_AR5212) {
                 u32 scal;
+                struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
                 if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))
                         scal = AR5K_PHY_SCAL_32MHZ_2417;
-                else if (ath5k_eeprom_is_hb63(ah))
+                else if (ee->ee_is_hb63)
                         scal = AR5K_PHY_SCAL_32MHZ_HB63;
                 else
                         scal = AR5K_PHY_SCAL_32MHZ;
@@ -697,13 +678,13 @@ static void ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah,
         /* Set antenna idle switch table */
         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_ANT_CTL,
                         AR5K_PHY_ANT_CTL_SWTABLE_IDLE,
-                        (ah->ah_antenna[ee_mode][0] |
+                        (ah->ah_ant_ctl[ee_mode][0] |
                         AR5K_PHY_ANT_CTL_TXRX_EN));
 
-        /* Set antenna switch table */
-        ath5k_hw_reg_write(ah, ah->ah_antenna[ee_mode][ant[0]],
+        /* Set antenna switch tables */
+        ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant[0]],
                 AR5K_PHY_ANT_SWITCH_TABLE_0);
-        ath5k_hw_reg_write(ah, ah->ah_antenna[ee_mode][ant[1]],
+        ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant[1]],
                 AR5K_PHY_ANT_SWITCH_TABLE_1);
 
         /* Noise floor threshold */
@@ -997,10 +978,10 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
                 ath5k_hw_tweak_initval_settings(ah, channel);
 
                 /*
-                 * Set TX power (FIXME)
+                 * Set TX power
                  */
                 ret = ath5k_hw_txpower(ah, channel, ee_mode,
-                                        AR5K_TUNE_DEFAULT_TXPOWER);
+                                        ah->ah_txpower.txp_max_pwr / 2);
                 if (ret)
                         return ret;
 
@@ -1023,9 +1004,22 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
                 /* Write OFDM timings on 5212*/
                 if (ah->ah_version == AR5K_AR5212 &&
                         channel->hw_value & CHANNEL_OFDM) {
+                        struct ath5k_eeprom_info *ee =
+                                        &ah->ah_capabilities.cap_eeprom;
+
                         ret = ath5k_hw_write_ofdm_timings(ah, channel);
                         if (ret)
                                 return ret;
+
+                        /* Note: According to docs we can have a newer
+                         * EEPROM on old hardware, so we need to verify
+                         * that our hardware is new enough to have spur
+                         * mitigation registers (delta phase etc) */
+                        if (ah->ah_mac_srev >= AR5K_SREV_AR5424 ||
+                        (ah->ah_mac_srev >= AR5K_SREV_AR5424 &&
+                        ee->ee_version >= AR5K_EEPROM_VERSION_5_3))
+                                ath5k_hw_set_spur_mitigation_filter(ah,
+                                                                channel);
                 }
 
                 /*Enable/disable 802.11b mode on 5111
@@ -1041,17 +1035,15 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
 
                 /*
                  * In case a fixed antenna was set as default
-                 * write the same settings on both AR5K_PHY_ANT_SWITCH_TABLE
-                 * registers.
+                 * use the same switch table twice.
                  */
-                if (s_ant != 0) {
-                        if (s_ant == AR5K_ANT_FIXED_A) /* 1 - Main */
-                                ant[0] = ant[1] = AR5K_ANT_FIXED_A;
-                        else    /* 2 - Aux */
-                                ant[0] = ant[1] = AR5K_ANT_FIXED_B;
-                } else {
-                        ant[0] = AR5K_ANT_FIXED_A;
-                        ant[1] = AR5K_ANT_FIXED_B;
+                if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_A)
+                                ant[0] = ant[1] = AR5K_ANT_SWTABLE_A;
+                else if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_B)
+                                ant[0] = ant[1] = AR5K_ANT_SWTABLE_B;
+                else {
+                        ant[0] = AR5K_ANT_SWTABLE_A;
+                        ant[1] = AR5K_ANT_SWTABLE_B;
                 }
 
                 /* Commit values from EEPROM */
@@ -1259,6 +1251,8 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
          */
         ath5k_hw_noise_floor_calibration(ah, channel->center_freq);
 
+        /* Restore antenna mode */
+        ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
 
         /*
          * Configure QCUs/DCUs