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path: root/drivers/net/wireless/ath/ath5k/qcu.c
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Diffstat (limited to 'drivers/net/wireless/ath/ath5k/qcu.c')
-rw-r--r--drivers/net/wireless/ath/ath5k/qcu.c7
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/net/wireless/ath/ath5k/qcu.c b/drivers/net/wireless/ath/ath5k/qcu.c
index 5094c394a4b2..73407b3f53ef 100644
--- a/drivers/net/wireless/ath/ath5k/qcu.c
+++ b/drivers/net/wireless/ath/ath5k/qcu.c
@@ -160,7 +160,8 @@ u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue)
160 if (ah->ah_version == AR5K_AR5210) 160 if (ah->ah_version == AR5K_AR5210)
161 return false; 161 return false;
162 162
163 pending = (AR5K_QUEUE_STATUS(queue) & AR5K_QCU_STS_FRMPENDCNT); 163 pending = ath5k_hw_reg_read(ah, AR5K_QUEUE_STATUS(queue));
164 pending &= AR5K_QCU_STS_FRMPENDCNT;
164 165
165 /* It's possible to have no frames pending even if TXE 166 /* It's possible to have no frames pending even if TXE
166 * is set. To indicate that q has not stopped return 167 * is set. To indicate that q has not stopped return
@@ -401,14 +402,16 @@ int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
401 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue), 402 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
402 (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL << 403 (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL <<
403 AR5K_DCU_MISC_ARBLOCK_CTL_S) | 404 AR5K_DCU_MISC_ARBLOCK_CTL_S) |
405 AR5K_DCU_MISC_ARBLOCK_IGNORE |
404 AR5K_DCU_MISC_POST_FR_BKOFF_DIS | 406 AR5K_DCU_MISC_POST_FR_BKOFF_DIS |
405 AR5K_DCU_MISC_BCN_ENABLE); 407 AR5K_DCU_MISC_BCN_ENABLE);
406 break; 408 break;
407 409
408 case AR5K_TX_QUEUE_CAB: 410 case AR5K_TX_QUEUE_CAB:
409 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue), 411 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
410 AR5K_QCU_MISC_FRSHED_DBA_GT | 412 AR5K_QCU_MISC_FRSHED_BCN_SENT_GT |
411 AR5K_QCU_MISC_CBREXP_DIS | 413 AR5K_QCU_MISC_CBREXP_DIS |
414 AR5K_QCU_MISC_RDY_VEOL_POLICY |
412 AR5K_QCU_MISC_CBREXP_BCN_DIS); 415 AR5K_QCU_MISC_CBREXP_BCN_DIS);
413 416
414 ath5k_hw_reg_write(ah, ((AR5K_TUNE_BEACON_INTERVAL - 417 ath5k_hw_reg_write(ah, ((AR5K_TUNE_BEACON_INTERVAL -