diff options
Diffstat (limited to 'drivers/net/wireless/ath/ath5k/qcu.c')
-rw-r--r-- | drivers/net/wireless/ath/ath5k/qcu.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/net/wireless/ath/ath5k/qcu.c b/drivers/net/wireless/ath/ath5k/qcu.c index ed62273cdf01..778fb59d89f5 100644 --- a/drivers/net/wireless/ath/ath5k/qcu.c +++ b/drivers/net/wireless/ath/ath5k/qcu.c | |||
@@ -246,21 +246,21 @@ int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue) | |||
246 | return 0; | 246 | return 0; |
247 | 247 | ||
248 | /* Set Slot time */ | 248 | /* Set Slot time */ |
249 | ath5k_hw_reg_write(ah, ah->ah_turbo ? | 249 | ath5k_hw_reg_write(ah, (ah->ah_bwmode == AR5K_BWMODE_40MHZ) ? |
250 | AR5K_INIT_SLOT_TIME_TURBO : AR5K_INIT_SLOT_TIME, | 250 | AR5K_INIT_SLOT_TIME_TURBO : AR5K_INIT_SLOT_TIME, |
251 | AR5K_SLOT_TIME); | 251 | AR5K_SLOT_TIME); |
252 | /* Set ACK_CTS timeout */ | 252 | /* Set ACK_CTS timeout */ |
253 | ath5k_hw_reg_write(ah, ah->ah_turbo ? | 253 | ath5k_hw_reg_write(ah, (ah->ah_bwmode == AR5K_BWMODE_40MHZ) ? |
254 | AR5K_INIT_ACK_CTS_TIMEOUT_TURBO : | 254 | AR5K_INIT_ACK_CTS_TIMEOUT_TURBO : |
255 | AR5K_INIT_ACK_CTS_TIMEOUT, AR5K_SLOT_TIME); | 255 | AR5K_INIT_ACK_CTS_TIMEOUT, AR5K_SLOT_TIME); |
256 | /* Set Transmit Latency */ | 256 | /* Set Transmit Latency */ |
257 | ath5k_hw_reg_write(ah, ah->ah_turbo ? | 257 | ath5k_hw_reg_write(ah, (ah->ah_bwmode == AR5K_BWMODE_40MHZ) ? |
258 | AR5K_INIT_TRANSMIT_LATENCY_TURBO : | 258 | AR5K_INIT_TRANSMIT_LATENCY_TURBO : |
259 | AR5K_INIT_TRANSMIT_LATENCY, AR5K_USEC_5210); | 259 | AR5K_INIT_TRANSMIT_LATENCY, AR5K_USEC_5210); |
260 | 260 | ||
261 | /* Set IFS0 */ | 261 | /* Set IFS0 */ |
262 | if (ah->ah_turbo) { | 262 | if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) { |
263 | ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS_TURBO + | 263 | ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS_TURBO + |
264 | tq->tqi_aifs * AR5K_INIT_SLOT_TIME_TURBO) << | 264 | tq->tqi_aifs * AR5K_INIT_SLOT_TIME_TURBO) << |
265 | AR5K_IFS0_DIFS_S) | AR5K_INIT_SIFS_TURBO, | 265 | AR5K_IFS0_DIFS_S) | AR5K_INIT_SIFS_TURBO, |
266 | AR5K_IFS0); | 266 | AR5K_IFS0); |
@@ -272,18 +272,18 @@ int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue) | |||
272 | } | 272 | } |
273 | 273 | ||
274 | /* Set IFS1 */ | 274 | /* Set IFS1 */ |
275 | ath5k_hw_reg_write(ah, ah->ah_turbo ? | 275 | ath5k_hw_reg_write(ah, (ah->ah_bwmode == AR5K_BWMODE_40MHZ) ? |
276 | AR5K_INIT_PROTO_TIME_CNTRL_TURBO : | 276 | AR5K_INIT_PROTO_TIME_CNTRL_TURBO : |
277 | AR5K_INIT_PROTO_TIME_CNTRL, AR5K_IFS1); | 277 | AR5K_INIT_PROTO_TIME_CNTRL, AR5K_IFS1); |
278 | /* Set AR5K_PHY_SETTLING */ | 278 | /* Set AR5K_PHY_SETTLING */ |
279 | ath5k_hw_reg_write(ah, ah->ah_turbo ? | 279 | ath5k_hw_reg_write(ah, (ah->ah_bwmode == AR5K_BWMODE_40MHZ) ? |
280 | (ath5k_hw_reg_read(ah, AR5K_PHY_SETTLING) & ~0x7F) | 280 | (ath5k_hw_reg_read(ah, AR5K_PHY_SETTLING) & ~0x7F) |
281 | | 0x38 : | 281 | | 0x38 : |
282 | (ath5k_hw_reg_read(ah, AR5K_PHY_SETTLING) & ~0x7F) | 282 | (ath5k_hw_reg_read(ah, AR5K_PHY_SETTLING) & ~0x7F) |
283 | | 0x1C, | 283 | | 0x1C, |
284 | AR5K_PHY_SETTLING); | 284 | AR5K_PHY_SETTLING); |
285 | /* Set Frame Control Register */ | 285 | /* Set Frame Control Register */ |
286 | ath5k_hw_reg_write(ah, ah->ah_turbo ? | 286 | ath5k_hw_reg_write(ah, (ah->ah_bwmode == AR5K_BWMODE_40MHZ) ? |
287 | (AR5K_PHY_FRAME_CTL_INI | AR5K_PHY_TURBO_MODE | | 287 | (AR5K_PHY_FRAME_CTL_INI | AR5K_PHY_TURBO_MODE | |
288 | AR5K_PHY_TURBO_SHORT | 0x2020) : | 288 | AR5K_PHY_TURBO_SHORT | 0x2020) : |
289 | (AR5K_PHY_FRAME_CTL_INI | 0x1020), | 289 | (AR5K_PHY_FRAME_CTL_INI | 0x1020), |