diff options
Diffstat (limited to 'drivers/net/wireless/ath/ath5k/phy.c')
-rw-r--r-- | drivers/net/wireless/ath/ath5k/phy.c | 41 |
1 files changed, 19 insertions, 22 deletions
diff --git a/drivers/net/wireless/ath/ath5k/phy.c b/drivers/net/wireless/ath/ath5k/phy.c index dd2b417729ba..81e465e70175 100644 --- a/drivers/net/wireless/ath/ath5k/phy.c +++ b/drivers/net/wireless/ath/ath5k/phy.c | |||
@@ -22,6 +22,7 @@ | |||
22 | 22 | ||
23 | #include <linux/delay.h> | 23 | #include <linux/delay.h> |
24 | #include <linux/slab.h> | 24 | #include <linux/slab.h> |
25 | #include <asm/unaligned.h> | ||
25 | 26 | ||
26 | #include "ath5k.h" | 27 | #include "ath5k.h" |
27 | #include "reg.h" | 28 | #include "reg.h" |
@@ -561,7 +562,7 @@ static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah) | |||
561 | } | 562 | } |
562 | 563 | ||
563 | done: | 564 | done: |
564 | ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, | 565 | ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, |
565 | "ret %d, gain step %u, current gain %u, target gain %u\n", | 566 | "ret %d, gain step %u, current gain %u, target gain %u\n", |
566 | ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current, | 567 | ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current, |
567 | ah->ah_gain.g_target); | 568 | ah->ah_gain.g_target); |
@@ -773,7 +774,7 @@ static int ath5k_hw_rfregs_init(struct ath5k_hw *ah, | |||
773 | ah->ah_rf_banks = kmalloc(sizeof(u32) * ah->ah_rf_banks_size, | 774 | ah->ah_rf_banks = kmalloc(sizeof(u32) * ah->ah_rf_banks_size, |
774 | GFP_KERNEL); | 775 | GFP_KERNEL); |
775 | if (ah->ah_rf_banks == NULL) { | 776 | if (ah->ah_rf_banks == NULL) { |
776 | ATH5K_ERR(ah->ah_sc, "out of memory\n"); | 777 | ATH5K_ERR(ah, "out of memory\n"); |
777 | return -ENOMEM; | 778 | return -ENOMEM; |
778 | } | 779 | } |
779 | } | 780 | } |
@@ -783,7 +784,7 @@ static int ath5k_hw_rfregs_init(struct ath5k_hw *ah, | |||
783 | 784 | ||
784 | for (i = 0; i < ah->ah_rf_banks_size; i++) { | 785 | for (i = 0; i < ah->ah_rf_banks_size; i++) { |
785 | if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) { | 786 | if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) { |
786 | ATH5K_ERR(ah->ah_sc, "invalid bank\n"); | 787 | ATH5K_ERR(ah, "invalid bank\n"); |
787 | return -EINVAL; | 788 | return -EINVAL; |
788 | } | 789 | } |
789 | 790 | ||
@@ -1268,7 +1269,7 @@ static int ath5k_hw_channel(struct ath5k_hw *ah, | |||
1268 | * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok() | 1269 | * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok() |
1269 | * of the band by that */ | 1270 | * of the band by that */ |
1270 | if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) { | 1271 | if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) { |
1271 | ATH5K_ERR(ah->ah_sc, | 1272 | ATH5K_ERR(ah, |
1272 | "channel frequency (%u MHz) out of supported " | 1273 | "channel frequency (%u MHz) out of supported " |
1273 | "band range\n", | 1274 | "band range\n", |
1274 | channel->center_freq); | 1275 | channel->center_freq); |
@@ -1356,7 +1357,7 @@ static s16 ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah) | |||
1356 | } | 1357 | } |
1357 | } | 1358 | } |
1358 | for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) { | 1359 | for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) { |
1359 | ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, | 1360 | ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, |
1360 | "cal %d:%d\n", i, sort[i]); | 1361 | "cal %d:%d\n", i, sort[i]); |
1361 | } | 1362 | } |
1362 | return sort[(ATH5K_NF_CAL_HIST_MAX - 1) / 2]; | 1363 | return sort[(ATH5K_NF_CAL_HIST_MAX - 1) / 2]; |
@@ -1382,7 +1383,7 @@ void ath5k_hw_update_noise_floor(struct ath5k_hw *ah) | |||
1382 | 1383 | ||
1383 | /* keep last value if calibration hasn't completed */ | 1384 | /* keep last value if calibration hasn't completed */ |
1384 | if (ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL) & AR5K_PHY_AGCCTL_NF) { | 1385 | if (ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL) & AR5K_PHY_AGCCTL_NF) { |
1385 | ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, | 1386 | ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, |
1386 | "NF did not complete in calibration window\n"); | 1387 | "NF did not complete in calibration window\n"); |
1387 | 1388 | ||
1388 | return; | 1389 | return; |
@@ -1395,7 +1396,7 @@ void ath5k_hw_update_noise_floor(struct ath5k_hw *ah) | |||
1395 | threshold = ee->ee_noise_floor_thr[ee_mode]; | 1396 | threshold = ee->ee_noise_floor_thr[ee_mode]; |
1396 | 1397 | ||
1397 | if (nf > threshold) { | 1398 | if (nf > threshold) { |
1398 | ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, | 1399 | ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, |
1399 | "noise floor failure detected; " | 1400 | "noise floor failure detected; " |
1400 | "read %d, threshold %d\n", | 1401 | "read %d, threshold %d\n", |
1401 | nf, threshold); | 1402 | nf, threshold); |
@@ -1432,7 +1433,7 @@ void ath5k_hw_update_noise_floor(struct ath5k_hw *ah) | |||
1432 | 1433 | ||
1433 | ah->ah_noise_floor = nf; | 1434 | ah->ah_noise_floor = nf; |
1434 | 1435 | ||
1435 | ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, | 1436 | ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, |
1436 | "noise floor calibrated: %d\n", nf); | 1437 | "noise floor calibrated: %d\n", nf); |
1437 | } | 1438 | } |
1438 | 1439 | ||
@@ -1520,7 +1521,7 @@ static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah, | |||
1520 | ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT); | 1521 | ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT); |
1521 | 1522 | ||
1522 | if (ret) { | 1523 | if (ret) { |
1523 | ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n", | 1524 | ATH5K_ERR(ah, "calibration timeout (%uMHz)\n", |
1524 | channel->center_freq); | 1525 | channel->center_freq); |
1525 | return ret; | 1526 | return ret; |
1526 | } | 1527 | } |
@@ -1555,7 +1556,7 @@ ath5k_hw_rf511x_iq_calibrate(struct ath5k_hw *ah) | |||
1555 | iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR); | 1556 | iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR); |
1556 | i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I); | 1557 | i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I); |
1557 | q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q); | 1558 | q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q); |
1558 | ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, | 1559 | ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_CALIBRATE, |
1559 | "iq_corr:%x i_pwr:%x q_pwr:%x", iq_corr, i_pwr, q_pwr); | 1560 | "iq_corr:%x i_pwr:%x q_pwr:%x", iq_corr, i_pwr, q_pwr); |
1560 | if (i_pwr && q_pwr) | 1561 | if (i_pwr && q_pwr) |
1561 | break; | 1562 | break; |
@@ -1581,7 +1582,7 @@ ath5k_hw_rf511x_iq_calibrate(struct ath5k_hw *ah) | |||
1581 | q_coff = (i_pwr / q_coffd) - 128; | 1582 | q_coff = (i_pwr / q_coffd) - 128; |
1582 | q_coff = clamp(q_coff, -16, 15); /* signed 5 bit */ | 1583 | q_coff = clamp(q_coff, -16, 15); /* signed 5 bit */ |
1583 | 1584 | ||
1584 | ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, | 1585 | ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_CALIBRATE, |
1585 | "new I:%d Q:%d (i_coffd:%x q_coffd:%x)", | 1586 | "new I:%d Q:%d (i_coffd:%x q_coffd:%x)", |
1586 | i_coff, q_coff, i_coffd, q_coffd); | 1587 | i_coff, q_coff, i_coffd, q_coffd); |
1587 | 1588 | ||
@@ -1966,7 +1967,7 @@ ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode) | |||
1966 | 1967 | ||
1967 | ee_mode = ath5k_eeprom_mode_from_channel(channel); | 1968 | ee_mode = ath5k_eeprom_mode_from_channel(channel); |
1968 | if (ee_mode < 0) { | 1969 | if (ee_mode < 0) { |
1969 | ATH5K_ERR(ah->ah_sc, | 1970 | ATH5K_ERR(ah, |
1970 | "invalid channel: %d\n", channel->center_freq); | 1971 | "invalid channel: %d\n", channel->center_freq); |
1971 | return; | 1972 | return; |
1972 | } | 1973 | } |
@@ -2794,12 +2795,8 @@ ath5k_write_pwr_to_pdadc_table(struct ath5k_hw *ah, u8 ee_mode) | |||
2794 | * Write TX power values | 2795 | * Write TX power values |
2795 | */ | 2796 | */ |
2796 | for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { | 2797 | for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { |
2797 | ath5k_hw_reg_write(ah, | 2798 | u32 val = get_unaligned_le32(&pdadc_out[4 * i]); |
2798 | ((pdadc_out[4 * i + 0] & 0xff) << 0) | | 2799 | ath5k_hw_reg_write(ah, val, AR5K_PHY_PDADC_TXPOWER(i)); |
2799 | ((pdadc_out[4 * i + 1] & 0xff) << 8) | | ||
2800 | ((pdadc_out[4 * i + 2] & 0xff) << 16) | | ||
2801 | ((pdadc_out[4 * i + 3] & 0xff) << 24), | ||
2802 | AR5K_PHY_PDADC_TXPOWER(i)); | ||
2803 | } | 2800 | } |
2804 | } | 2801 | } |
2805 | 2802 | ||
@@ -3122,13 +3119,13 @@ ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel, | |||
3122 | int ret; | 3119 | int ret; |
3123 | 3120 | ||
3124 | if (txpower > AR5K_TUNE_MAX_TXPOWER) { | 3121 | if (txpower > AR5K_TUNE_MAX_TXPOWER) { |
3125 | ATH5K_ERR(ah->ah_sc, "invalid tx power: %u\n", txpower); | 3122 | ATH5K_ERR(ah, "invalid tx power: %u\n", txpower); |
3126 | return -EINVAL; | 3123 | return -EINVAL; |
3127 | } | 3124 | } |
3128 | 3125 | ||
3129 | ee_mode = ath5k_eeprom_mode_from_channel(channel); | 3126 | ee_mode = ath5k_eeprom_mode_from_channel(channel); |
3130 | if (ee_mode < 0) { | 3127 | if (ee_mode < 0) { |
3131 | ATH5K_ERR(ah->ah_sc, | 3128 | ATH5K_ERR(ah, |
3132 | "invalid channel: %d\n", channel->center_freq); | 3129 | "invalid channel: %d\n", channel->center_freq); |
3133 | return -EINVAL; | 3130 | return -EINVAL; |
3134 | } | 3131 | } |
@@ -3229,7 +3226,7 @@ ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel, | |||
3229 | 3226 | ||
3230 | int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower) | 3227 | int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower) |
3231 | { | 3228 | { |
3232 | ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER, | 3229 | ATH5K_DBG(ah, ATH5K_DEBUG_TXPOWER, |
3233 | "changing txpower to %d\n", txpower); | 3230 | "changing txpower to %d\n", txpower); |
3234 | 3231 | ||
3235 | return ath5k_hw_txpower(ah, ah->ah_current_channel, txpower); | 3232 | return ath5k_hw_txpower(ah, ah->ah_current_channel, txpower); |
@@ -3440,7 +3437,7 @@ int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel, | |||
3440 | * during ath5k_phy_calibrate) */ | 3437 | * during ath5k_phy_calibrate) */ |
3441 | if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, | 3438 | if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, |
3442 | AR5K_PHY_AGCCTL_CAL, 0, false)) { | 3439 | AR5K_PHY_AGCCTL_CAL, 0, false)) { |
3443 | ATH5K_ERR(ah->ah_sc, "gain calibration timeout (%uMHz)\n", | 3440 | ATH5K_ERR(ah, "gain calibration timeout (%uMHz)\n", |
3444 | channel->center_freq); | 3441 | channel->center_freq); |
3445 | } | 3442 | } |
3446 | 3443 | ||