1 files changed, 464 insertions, 29 deletions

diff --git a/drivers/net/wireless/ath/ath5k/phy.c b/drivers/net/wireless/ath/ath5k/phy.c
index b48b29dca3d2..d0d1c350025a 100644
--- a/drivers/net/wireless/ath/ath5k/phy.c
+++ b/drivers/net/wireless/ath/ath5k/phy.c
@@ -168,9 +168,6 @@ int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah)
  * tx power and a Peak to Average Power Detector (PAPD) will try
  * to measure the gain.
  *
- * TODO: Use propper tx power setting for the probe packet so
- * that we don't observe a serious power drop on the receiver
- *
  * XXX:  How about forcing a tx packet (bypassing PCU arbitrator etc)
  * just after we enable the probe so that we don't mess with
  * standard traffic ? Maybe it's time to use sw interrupts and
@@ -186,7 +183,7 @@ static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah)
 
         /* Send the packet with 2dB below max power as
          * patent doc suggest */
-        ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_max_pwr - 4,
+        ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_ofdm - 4,
                         AR5K_PHY_PAPD_PROBE_TXPOWER) |
                         AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE);
 
@@ -1356,6 +1353,257 @@ int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
         return ret;
 }
 
+/***************************\
+* Spur mitigation functions *
+\***************************/
+
+bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
+                                struct ieee80211_channel *channel)
+{
+        u8 refclk_freq;
+
+        if ((ah->ah_radio == AR5K_RF5112) ||
+        (ah->ah_radio == AR5K_RF5413) ||
+        (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
+                refclk_freq = 40;
+        else
+                refclk_freq = 32;
+
+        if ((channel->center_freq % refclk_freq != 0) &&
+        ((channel->center_freq % refclk_freq < 10) ||
+        (channel->center_freq % refclk_freq > 22)))
+                return true;
+        else
+                return false;
+}
+
+void
+ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
+                                struct ieee80211_channel *channel)
+{
+        struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
+        u32 mag_mask[4] = {0, 0, 0, 0};
+        u32 pilot_mask[2] = {0, 0};
+        /* Note: fbin values are scaled up by 2 */
+        u16 spur_chan_fbin, chan_fbin, symbol_width, spur_detection_window;
+        s32 spur_delta_phase, spur_freq_sigma_delta;
+        s32 spur_offset, num_symbols_x16;
+        u8 num_symbol_offsets, i, freq_band;
+
+        /* Convert current frequency to fbin value (the same way channels
+         * are stored on EEPROM, check out ath5k_eeprom_bin2freq) and scale
+         * up by 2 so we can compare it later */
+        if (channel->hw_value & CHANNEL_2GHZ) {
+                chan_fbin = (channel->center_freq - 2300) * 10;
+                freq_band = AR5K_EEPROM_BAND_2GHZ;
+        } else {
+                chan_fbin = (channel->center_freq - 4900) * 10;
+                freq_band = AR5K_EEPROM_BAND_5GHZ;
+        }
+
+        /* Check if any spur_chan_fbin from EEPROM is
+         * within our current channel's spur detection range */
+        spur_chan_fbin = AR5K_EEPROM_NO_SPUR;
+        spur_detection_window = AR5K_SPUR_CHAN_WIDTH;
+        /* XXX: Half/Quarter channels ?*/
+        if (channel->hw_value & CHANNEL_TURBO)
+                spur_detection_window *= 2;
+
+        for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) {
+                spur_chan_fbin = ee->ee_spur_chans[i][freq_band];
+
+                /* Note: mask cleans AR5K_EEPROM_NO_SPUR flag
+                 * so it's zero if we got nothing from EEPROM */
+                if (spur_chan_fbin == AR5K_EEPROM_NO_SPUR) {
+                        spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK;
+                        break;
+                }
+
+                if ((chan_fbin - spur_detection_window <=
+                (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK)) &&
+                (chan_fbin + spur_detection_window >=
+                (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK))) {
+                        spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK;
+                        break;
+                }
+        }
+
+        /* We need to enable spur filter for this channel */
+        if (spur_chan_fbin) {
+                spur_offset = spur_chan_fbin - chan_fbin;
+                /*
+                 * Calculate deltas:
+                 * spur_freq_sigma_delta -> spur_offset / sample_freq << 21
+                 * spur_delta_phase -> spur_offset / chip_freq << 11
+                 * Note: Both values have 100KHz resolution
+                 */
+                /* XXX: Half/Quarter rate channels ? */
+                switch (channel->hw_value) {
+                case CHANNEL_A:
+                        /* Both sample_freq and chip_freq are 40MHz */
+                        spur_delta_phase = (spur_offset << 17) / 25;
+                        spur_freq_sigma_delta = (spur_delta_phase >> 10);
+                        symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
+                        break;
+                case CHANNEL_G:
+                        /* sample_freq -> 40MHz chip_freq -> 44MHz
+                         * (for b compatibility) */
+                        spur_freq_sigma_delta = (spur_offset << 8) / 55;
+                        spur_delta_phase = (spur_offset << 17) / 25;
+                        symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
+                        break;
+                case CHANNEL_T:
+                case CHANNEL_TG:
+                        /* Both sample_freq and chip_freq are 80MHz */
+                        spur_delta_phase = (spur_offset << 16) / 25;
+                        spur_freq_sigma_delta = (spur_delta_phase >> 10);
+                        symbol_width = AR5K_SPUR_SYMBOL_WIDTH_TURBO_100Hz;
+                        break;
+                default:
+                        return;
+                }
+
+                /* Calculate pilot and magnitude masks */
+
+                /* Scale up spur_offset by 1000 to switch to 100HZ resolution
+                 * and divide by symbol_width to find how many symbols we have
+                 * Note: number of symbols is scaled up by 16 */
+                num_symbols_x16 = ((spur_offset * 1000) << 4) / symbol_width;
+
+                /* Spur is on a symbol if num_symbols_x16 % 16 is zero */
+                if (!(num_symbols_x16 & 0xF))
+                        /* _X_ */
+                        num_symbol_offsets = 3;
+                else
+                        /* _xx_ */
+                        num_symbol_offsets = 4;
+
+                for (i = 0; i < num_symbol_offsets; i++) {
+
+                        /* Calculate pilot mask */
+                        s32 curr_sym_off =
+                                (num_symbols_x16 / 16) + i + 25;
+
+                        /* Pilot magnitude mask seems to be a way to
+                         * declare the boundaries for our detection
+                         * window or something, it's 2 for the middle
+                         * value(s) where the symbol is expected to be
+                         * and 1 on the boundary values */
+                        u8 plt_mag_map =
+                                (i == 0 || i == (num_symbol_offsets - 1))
+                                                                ? 1 : 2;
+
+                        if (curr_sym_off >= 0 && curr_sym_off <= 32) {
+                                if (curr_sym_off <= 25)
+                                        pilot_mask[0] |= 1 << curr_sym_off;
+                                else if (curr_sym_off >= 27)
+                                        pilot_mask[0] |= 1 << (curr_sym_off - 1);
+                        } else if (curr_sym_off >= 33 && curr_sym_off <= 52)
+                                pilot_mask[1] |= 1 << (curr_sym_off - 33);
+
+                        /* Calculate magnitude mask (for viterbi decoder) */
+                        if (curr_sym_off >= -1 && curr_sym_off <= 14)
+                                mag_mask[0] |=
+                                        plt_mag_map << (curr_sym_off + 1) * 2;
+                        else if (curr_sym_off >= 15 && curr_sym_off <= 30)
+                                mag_mask[1] |=
+                                        plt_mag_map << (curr_sym_off - 15) * 2;
+                        else if (curr_sym_off >= 31 && curr_sym_off <= 46)
+                                mag_mask[2] |=
+                                        plt_mag_map << (curr_sym_off - 31) * 2;
+                        else if (curr_sym_off >= 46 && curr_sym_off <= 53)
+                                mag_mask[3] |=
+                                        plt_mag_map << (curr_sym_off - 47) * 2;
+
+                }
+
+                /* Write settings on hw to enable spur filter */
+                AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
+                                        AR5K_PHY_BIN_MASK_CTL_RATE, 0xff);
+                /* XXX: Self correlator also ? */
+                AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
+                                        AR5K_PHY_IQ_PILOT_MASK_EN |
+                                        AR5K_PHY_IQ_CHAN_MASK_EN |
+                                        AR5K_PHY_IQ_SPUR_FILT_EN);
+
+                /* Set delta phase and freq sigma delta */
+                ath5k_hw_reg_write(ah,
+                                AR5K_REG_SM(spur_delta_phase,
+                                        AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE) |
+                                AR5K_REG_SM(spur_freq_sigma_delta,
+                                AR5K_PHY_TIMING_11_SPUR_FREQ_SD) |
+                                AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC,
+                                AR5K_PHY_TIMING_11);
+
+                /* Write pilot masks */
+                ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_7);
+                AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8,
+                                        AR5K_PHY_TIMING_8_PILOT_MASK_2,
+                                        pilot_mask[1]);
+
+                ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_9);
+                AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10,
+                                        AR5K_PHY_TIMING_10_PILOT_MASK_2,
+                                        pilot_mask[1]);
+
+                /* Write magnitude masks */
+                ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK_1);
+                ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK_2);
+                ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK_3);
+                AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
+                                        AR5K_PHY_BIN_MASK_CTL_MASK_4,
+                                        mag_mask[3]);
+
+                ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK2_1);
+                ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK2_2);
+                ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK2_3);
+                AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4,
+                                        AR5K_PHY_BIN_MASK2_4_MASK_4,
+                                        mag_mask[3]);
+
+        } else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) &
+        AR5K_PHY_IQ_SPUR_FILT_EN) {
+                /* Clean up spur mitigation settings and disable fliter */
+                AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
+                                        AR5K_PHY_BIN_MASK_CTL_RATE, 0);
+                AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_IQ,
+                                        AR5K_PHY_IQ_PILOT_MASK_EN |
+                                        AR5K_PHY_IQ_CHAN_MASK_EN |
+                                        AR5K_PHY_IQ_SPUR_FILT_EN);
+                ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_11);
+
+                /* Clear pilot masks */
+                ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_7);
+                AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8,
+                                        AR5K_PHY_TIMING_8_PILOT_MASK_2,
+                                        0);
+
+                ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_9);
+                AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10,
+                                        AR5K_PHY_TIMING_10_PILOT_MASK_2,
+                                        0);
+
+                /* Clear magnitude masks */
+                ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_1);
+                ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_2);
+                ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_3);
+                AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
+                                        AR5K_PHY_BIN_MASK_CTL_MASK_4,
+                                        0);
+
+                ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_1);
+                ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_2);
+                ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_3);
+                AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4,
+                                        AR5K_PHY_BIN_MASK2_4_MASK_4,
+                                        0);
+        }
+}
+
+/********************\
+  Misc PHY functions
+\********************/
+
 int ath5k_hw_phy_disable(struct ath5k_hw *ah)
 {
         ATH5K_TRACE(ah->ah_sc);
@@ -1365,10 +1613,6 @@ int ath5k_hw_phy_disable(struct ath5k_hw *ah)
         return 0;
 }
 
-/********************\
-  Misc PHY functions
-\********************/
-
 /*
  * Get the PHY Chip revision
  */
@@ -1417,25 +1661,189 @@ u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
         return ret;
 }
 
+/*****************\
+* Antenna control *
+\*****************/
+
 void /*TODO:Boundary check*/
-ath5k_hw_set_def_antenna(struct ath5k_hw *ah, unsigned int ant)
+ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant)
 {
         ATH5K_TRACE(ah->ah_sc);
-        /*Just a try M.F.*/
+
         if (ah->ah_version != AR5K_AR5210)
-                ath5k_hw_reg_write(ah, ant, AR5K_DEFAULT_ANTENNA);
+                ath5k_hw_reg_write(ah, ant & 0x7, AR5K_DEFAULT_ANTENNA);
 }
 
 unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah)
 {
         ATH5K_TRACE(ah->ah_sc);
-        /*Just a try M.F.*/
+
         if (ah->ah_version != AR5K_AR5210)
-                return ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA);
+                return ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA) & 0x7;
 
         return false; /*XXX: What do we return for 5210 ?*/
 }
 
+/*
+ * Enable/disable fast rx antenna diversity
+ */
+static void
+ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable)
+{
+        switch (ee_mode) {
+        case AR5K_EEPROM_MODE_11G:
+                /* XXX: This is set to
+                 * disabled on initvals !!! */
+        case AR5K_EEPROM_MODE_11A:
+                if (enable)
+                        AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGCCTL,
+                                        AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
+                else
+                        AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
+                                        AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
+                break;
+        case AR5K_EEPROM_MODE_11B:
+                AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
+                                        AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
+                break;
+        default:
+                return;
+        }
+
+        if (enable) {
+                AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
+                                AR5K_PHY_RESTART_DIV_GC, 0xc);
+
+                AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
+                                        AR5K_PHY_FAST_ANT_DIV_EN);
+        } else {
+                AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
+                                AR5K_PHY_RESTART_DIV_GC, 0x8);
+
+                AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
+                                        AR5K_PHY_FAST_ANT_DIV_EN);
+        }
+}
+
+/*
+ * Set antenna operating mode
+ */
+void
+ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode)
+{
+        struct ieee80211_channel *channel = &ah->ah_current_channel;
+        bool use_def_for_tx, update_def_on_tx, use_def_for_rts, fast_div;
+        bool use_def_for_sg;
+        u8 def_ant, tx_ant, ee_mode;
+        u32 sta_id1 = 0;
+
+        def_ant = ah->ah_def_ant;
+
+        ATH5K_TRACE(ah->ah_sc);
+
+        switch (channel->hw_value & CHANNEL_MODES) {
+        case CHANNEL_A:
+        case CHANNEL_T:
+        case CHANNEL_XR:
+                ee_mode = AR5K_EEPROM_MODE_11A;
+                break;
+        case CHANNEL_G:
+        case CHANNEL_TG:
+                ee_mode = AR5K_EEPROM_MODE_11G;
+                break;
+        case CHANNEL_B:
+                ee_mode = AR5K_EEPROM_MODE_11B;
+                break;
+        default:
+                ATH5K_ERR(ah->ah_sc,
+                        "invalid channel: %d\n", channel->center_freq);
+                return;
+        }
+
+        switch (ant_mode) {
+        case AR5K_ANTMODE_DEFAULT:
+                tx_ant = 0;
+                use_def_for_tx = false;
+                update_def_on_tx = false;
+                use_def_for_rts = false;
+                use_def_for_sg = false;
+                fast_div = true;
+                break;
+        case AR5K_ANTMODE_FIXED_A:
+                def_ant = 1;
+                tx_ant = 0;
+                use_def_for_tx = true;
+                update_def_on_tx = false;
+                use_def_for_rts = true;
+                use_def_for_sg = true;
+                fast_div = false;
+                break;
+        case AR5K_ANTMODE_FIXED_B:
+                def_ant = 2;
+                tx_ant = 0;
+                use_def_for_tx = true;
+                update_def_on_tx = false;
+                use_def_for_rts = true;
+                use_def_for_sg = true;
+                fast_div = false;
+                break;
+        case AR5K_ANTMODE_SINGLE_AP:
+                def_ant = 1;    /* updated on tx */
+                tx_ant = 0;
+                use_def_for_tx = true;
+                update_def_on_tx = true;
+                use_def_for_rts = true;
+                use_def_for_sg = true;
+                fast_div = true;
+                break;
+        case AR5K_ANTMODE_SECTOR_AP:
+                tx_ant = 1;     /* variable */
+                use_def_for_tx = false;
+                update_def_on_tx = false;
+                use_def_for_rts = true;
+                use_def_for_sg = false;
+                fast_div = false;
+                break;
+        case AR5K_ANTMODE_SECTOR_STA:
+                tx_ant = 1;     /* variable */
+                use_def_for_tx = true;
+                update_def_on_tx = false;
+                use_def_for_rts = true;
+                use_def_for_sg = false;
+                fast_div = true;
+                break;
+        case AR5K_ANTMODE_DEBUG:
+                def_ant = 1;
+                tx_ant = 2;
+                use_def_for_tx = false;
+                update_def_on_tx = false;
+                use_def_for_rts = false;
+                use_def_for_sg = false;
+                fast_div = false;
+                break;
+        default:
+                return;
+        }
+
+        ah->ah_tx_ant = tx_ant;
+        ah->ah_ant_mode = ant_mode;
+
+        sta_id1 |= use_def_for_tx ? AR5K_STA_ID1_DEFAULT_ANTENNA : 0;
+        sta_id1 |= update_def_on_tx ? AR5K_STA_ID1_DESC_ANTENNA : 0;
+        sta_id1 |= use_def_for_rts ? AR5K_STA_ID1_RTS_DEF_ANTENNA : 0;
+        sta_id1 |= use_def_for_sg ? AR5K_STA_ID1_SELFGEN_DEF_ANT : 0;
+
+        AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_ANTENNA_SETTINGS);
+
+        if (sta_id1)
+                AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, sta_id1);
+
+        /* Note: set diversity before default antenna
+         * because it won't work correctly */
+        ath5k_hw_set_fast_div(ah, ee_mode, fast_div);
+        ath5k_hw_set_def_antenna(ah, def_ant);
+}
+
 
 /****************\
 * TX power setup *
@@ -1750,8 +2158,6 @@ done:
  * Get the max edge power for this channel if
  * we have such data from EEPROM's Conformance Test
  * Limits (CTL), and limit max power if needed.
- *
- * FIXME: Only works for world regulatory domains
  */
 static void
 ath5k_get_max_ctl_power(struct ath5k_hw *ah,
@@ -1767,26 +2173,23 @@ ath5k_get_max_ctl_power(struct ath5k_hw *ah,
         u8 ctl_idx = 0xFF;
         u32 target = channel->center_freq;
 
-        /* Find out a CTL for our mode that's not mapped
-         * on a specific reg domain.
-         *
-         * TODO: Map our current reg domain to one of the 3 available
-         * reg domain ids so that we can support more CTLs. */
+        ctl_mode = ath_regd_get_band_ctl(&ah->ah_regulatory, channel->band);
+
         switch (channel->hw_value & CHANNEL_MODES) {
         case CHANNEL_A:
-                ctl_mode = AR5K_CTL_11A | AR5K_CTL_NO_REGDOMAIN;
+                ctl_mode |= AR5K_CTL_11A;
                 break;
         case CHANNEL_G:
-                ctl_mode = AR5K_CTL_11G | AR5K_CTL_NO_REGDOMAIN;
+                ctl_mode |= AR5K_CTL_11G;
                 break;
         case CHANNEL_B:
-                ctl_mode = AR5K_CTL_11B | AR5K_CTL_NO_REGDOMAIN;
+                ctl_mode |= AR5K_CTL_11B;
                 break;
         case CHANNEL_T:
-                ctl_mode = AR5K_CTL_TURBO | AR5K_CTL_NO_REGDOMAIN;
+                ctl_mode |= AR5K_CTL_TURBO;
                 break;
         case CHANNEL_TG:
-                ctl_mode = AR5K_CTL_TURBOG | AR5K_CTL_NO_REGDOMAIN;
+                ctl_mode |= AR5K_CTL_TURBOG;
                 break;
         case CHANNEL_XR:
                 /* Fall through */
@@ -2482,8 +2885,19 @@ ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr,
                 for (i = 8; i <= 15; i++)
                         rates[i] -= ah->ah_txpower.txp_cck_ofdm_gainf_delta;
 
-        ah->ah_txpower.txp_min_pwr = rates[7];
-        ah->ah_txpower.txp_max_pwr = rates[0];
+        /* Now that we have all rates setup use table offset to
+         * match the power range set by user with the power indices
+         * on PCDAC/PDADC table */
+        for (i = 0; i < 16; i++) {
+                rates[i] += ah->ah_txpower.txp_offset;
+                /* Don't get out of bounds */
+                if (rates[i] > 63)
+                        rates[i] = 63;
+        }
+
+        /* Min/max in 0.25dB units */
+        ah->ah_txpower.txp_min_pwr = 2 * rates[7];
+        ah->ah_txpower.txp_max_pwr = 2 * rates[0];
         ah->ah_txpower.txp_ofdm = rates[7];
 }
 
@@ -2591,16 +3005,37 @@ ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
         return 0;
 }
 
-int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 mode, u8 txpower)
+int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower)
 {
         /*Just a try M.F.*/
         struct ieee80211_channel *channel = &ah->ah_current_channel;
+        u8 ee_mode;
 
         ATH5K_TRACE(ah->ah_sc);
+
+        switch (channel->hw_value & CHANNEL_MODES) {
+        case CHANNEL_A:
+        case CHANNEL_T:
+        case CHANNEL_XR:
+                ee_mode = AR5K_EEPROM_MODE_11A;
+                break;
+        case CHANNEL_G:
+        case CHANNEL_TG:
+                ee_mode = AR5K_EEPROM_MODE_11G;
+                break;
+        case CHANNEL_B:
+                ee_mode = AR5K_EEPROM_MODE_11B;
+                break;
+        default:
+                ATH5K_ERR(ah->ah_sc,
+                        "invalid channel: %d\n", channel->center_freq);
+                return -EINVAL;
+        }
+
         ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER,
                 "changing txpower to %d\n", txpower);
 
-        return ath5k_hw_txpower(ah, channel, mode, txpower);
+        return ath5k_hw_txpower(ah, channel, ee_mode, txpower);
 }
 
 #undef _ATH5K_PHY