diff options
Diffstat (limited to 'drivers/net/wireless/ath/ath5k/eeprom.h')
-rw-r--r-- | drivers/net/wireless/ath/ath5k/eeprom.h | 88 |
1 files changed, 64 insertions, 24 deletions
diff --git a/drivers/net/wireless/ath/ath5k/eeprom.h b/drivers/net/wireless/ath/ath5k/eeprom.h index 473a483bb9c3..c4a6d5f26af4 100644 --- a/drivers/net/wireless/ath/ath5k/eeprom.h +++ b/drivers/net/wireless/ath/ath5k/eeprom.h | |||
@@ -24,9 +24,6 @@ | |||
24 | * SERDES infos are present */ | 24 | * SERDES infos are present */ |
25 | #define AR5K_EEPROM_MAGIC 0x003d /* EEPROM Magic number */ | 25 | #define AR5K_EEPROM_MAGIC 0x003d /* EEPROM Magic number */ |
26 | #define AR5K_EEPROM_MAGIC_VALUE 0x5aa5 /* Default - found on EEPROM */ | 26 | #define AR5K_EEPROM_MAGIC_VALUE 0x5aa5 /* Default - found on EEPROM */ |
27 | #define AR5K_EEPROM_MAGIC_5212 0x0000145c /* 5212 */ | ||
28 | #define AR5K_EEPROM_MAGIC_5211 0x0000145b /* 5211 */ | ||
29 | #define AR5K_EEPROM_MAGIC_5210 0x0000145a /* 5210 */ | ||
30 | 27 | ||
31 | #define AR5K_EEPROM_IS_HB63 0x000b /* Talon detect */ | 28 | #define AR5K_EEPROM_IS_HB63 0x000b /* Talon detect */ |
32 | 29 | ||
@@ -78,9 +75,9 @@ | |||
78 | #define AR5K_EEPROM_HDR_11A(_v) (((_v) >> AR5K_EEPROM_MODE_11A) & 0x1) | 75 | #define AR5K_EEPROM_HDR_11A(_v) (((_v) >> AR5K_EEPROM_MODE_11A) & 0x1) |
79 | #define AR5K_EEPROM_HDR_11B(_v) (((_v) >> AR5K_EEPROM_MODE_11B) & 0x1) | 76 | #define AR5K_EEPROM_HDR_11B(_v) (((_v) >> AR5K_EEPROM_MODE_11B) & 0x1) |
80 | #define AR5K_EEPROM_HDR_11G(_v) (((_v) >> AR5K_EEPROM_MODE_11G) & 0x1) | 77 | #define AR5K_EEPROM_HDR_11G(_v) (((_v) >> AR5K_EEPROM_MODE_11G) & 0x1) |
81 | #define AR5K_EEPROM_HDR_T_2GHZ_DIS(_v) (((_v) >> 3) & 0x1) /* Disable turbo for 2Ghz (?) */ | 78 | #define AR5K_EEPROM_HDR_T_2GHZ_DIS(_v) (((_v) >> 3) & 0x1) /* Disable turbo for 2Ghz */ |
82 | #define AR5K_EEPROM_HDR_T_5GHZ_DBM(_v) (((_v) >> 4) & 0x7f) /* Max turbo power for a/XR mode (eeprom_init) */ | 79 | #define AR5K_EEPROM_HDR_T_5GHZ_DBM(_v) (((_v) >> 4) & 0x7f) /* Max turbo power for < 2W power consumption */ |
83 | #define AR5K_EEPROM_HDR_DEVICE(_v) (((_v) >> 11) & 0x7) | 80 | #define AR5K_EEPROM_HDR_DEVICE(_v) (((_v) >> 11) & 0x7) /* Device type (1 Cardbus, 2 PCI, 3 MiniPCI, 4 AP) */ |
84 | #define AR5K_EEPROM_HDR_RFKILL(_v) (((_v) >> 14) & 0x1) /* Device has RFKill support */ | 81 | #define AR5K_EEPROM_HDR_RFKILL(_v) (((_v) >> 14) & 0x1) /* Device has RFKill support */ |
85 | #define AR5K_EEPROM_HDR_T_5GHZ_DIS(_v) (((_v) >> 15) & 0x1) /* Disable turbo for 5Ghz */ | 82 | #define AR5K_EEPROM_HDR_T_5GHZ_DIS(_v) (((_v) >> 15) & 0x1) /* Disable turbo for 5Ghz */ |
86 | 83 | ||
@@ -101,7 +98,7 @@ | |||
101 | 98 | ||
102 | #define AR5K_EEPROM_MISC1 AR5K_EEPROM_INFO(5) | 99 | #define AR5K_EEPROM_MISC1 AR5K_EEPROM_INFO(5) |
103 | #define AR5K_EEPROM_TARGET_PWRSTART(_v) ((_v) & 0xfff) | 100 | #define AR5K_EEPROM_TARGET_PWRSTART(_v) ((_v) & 0xfff) |
104 | #define AR5K_EEPROM_HAS32KHZCRYSTAL(_v) (((_v) >> 14) & 0x1) | 101 | #define AR5K_EEPROM_HAS32KHZCRYSTAL(_v) (((_v) >> 14) & 0x1) /* has 32KHz crystal for sleep mode */ |
105 | #define AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(_v) (((_v) >> 15) & 0x1) | 102 | #define AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(_v) (((_v) >> 15) & 0x1) |
106 | 103 | ||
107 | #define AR5K_EEPROM_MISC2 AR5K_EEPROM_INFO(6) | 104 | #define AR5K_EEPROM_MISC2 AR5K_EEPROM_INFO(6) |
@@ -114,26 +111,27 @@ | |||
114 | 111 | ||
115 | #define AR5K_EEPROM_MISC4 AR5K_EEPROM_INFO(8) | 112 | #define AR5K_EEPROM_MISC4 AR5K_EEPROM_INFO(8) |
116 | #define AR5K_EEPROM_CAL_DATA_START(_v) (((_v) >> 4) & 0xfff) | 113 | #define AR5K_EEPROM_CAL_DATA_START(_v) (((_v) >> 4) & 0xfff) |
117 | #define AR5K_EEPROM_MASK_R0(_v) (((_v) >> 2) & 0x3) | 114 | #define AR5K_EEPROM_MASK_R0(_v) (((_v) >> 2) & 0x3) /* modes supported by radio 0 (bit 1: G, bit 2: A) */ |
118 | #define AR5K_EEPROM_MASK_R1(_v) ((_v) & 0x3) | 115 | #define AR5K_EEPROM_MASK_R1(_v) ((_v) & 0x3) /* modes supported by radio 1 (bit 1: G, bit 2: A) */ |
119 | 116 | ||
120 | #define AR5K_EEPROM_MISC5 AR5K_EEPROM_INFO(9) | 117 | #define AR5K_EEPROM_MISC5 AR5K_EEPROM_INFO(9) |
121 | #define AR5K_EEPROM_COMP_DIS(_v) ((_v) & 0x1) | 118 | #define AR5K_EEPROM_COMP_DIS(_v) ((_v) & 0x1) /* disable compression */ |
122 | #define AR5K_EEPROM_AES_DIS(_v) (((_v) >> 1) & 0x1) | 119 | #define AR5K_EEPROM_AES_DIS(_v) (((_v) >> 1) & 0x1) /* disable AES */ |
123 | #define AR5K_EEPROM_FF_DIS(_v) (((_v) >> 2) & 0x1) | 120 | #define AR5K_EEPROM_FF_DIS(_v) (((_v) >> 2) & 0x1) /* disable fast frames */ |
124 | #define AR5K_EEPROM_BURST_DIS(_v) (((_v) >> 3) & 0x1) | 121 | #define AR5K_EEPROM_BURST_DIS(_v) (((_v) >> 3) & 0x1) /* disable bursting */ |
125 | #define AR5K_EEPROM_MAX_QCU(_v) (((_v) >> 4) & 0xf) | 122 | #define AR5K_EEPROM_MAX_QCU(_v) (((_v) >> 4) & 0xf) /* max number of QCUs. defaults to 10 */ |
126 | #define AR5K_EEPROM_HEAVY_CLIP_EN(_v) (((_v) >> 8) & 0x1) | 123 | #define AR5K_EEPROM_HEAVY_CLIP_EN(_v) (((_v) >> 8) & 0x1) /* enable heayy clipping */ |
127 | #define AR5K_EEPROM_KEY_CACHE_SIZE(_v) (((_v) >> 12) & 0xf) | 124 | #define AR5K_EEPROM_KEY_CACHE_SIZE(_v) (((_v) >> 12) & 0xf) /* key cache size. defaults to 128 */ |
128 | 125 | ||
129 | #define AR5K_EEPROM_MISC6 AR5K_EEPROM_INFO(10) | 126 | #define AR5K_EEPROM_MISC6 AR5K_EEPROM_INFO(10) |
130 | #define AR5K_EEPROM_TX_CHAIN_DIS ((_v) & 0x8) | 127 | #define AR5K_EEPROM_TX_CHAIN_DIS ((_v) & 0x7) /* MIMO chains disabled for TX bitmask */ |
131 | #define AR5K_EEPROM_RX_CHAIN_DIS (((_v) >> 3) & 0x8) | 128 | #define AR5K_EEPROM_RX_CHAIN_DIS (((_v) >> 3) & 0x7) /* MIMO chains disabled for RX bitmask */ |
132 | #define AR5K_EEPROM_FCC_MID_EN (((_v) >> 6) & 0x1) | 129 | #define AR5K_EEPROM_FCC_MID_EN (((_v) >> 6) & 0x1) /* 5.47-5.7GHz supported */ |
133 | #define AR5K_EEPROM_JAP_U1EVEN_EN (((_v) >> 7) & 0x1) | 130 | #define AR5K_EEPROM_JAP_U1EVEN_EN (((_v) >> 7) & 0x1) /* Japan UNII1 band (5.15-5.25GHz) on even channels (5180, 5200, 5220, 5240) supported */ |
134 | #define AR5K_EEPROM_JAP_U2_EN (((_v) >> 8) & 0x1) | 131 | #define AR5K_EEPROM_JAP_U2_EN (((_v) >> 8) & 0x1) /* Japan UNII2 band (5.25-5.35GHz) supported */ |
135 | #define AR5K_EEPROM_JAP_U1ODD_EN (((_v) >> 9) & 0x1) | 132 | #define AR5K_EEPROM_JAP_MID_EN (((_v) >> 9) & 0x1) /* Japan band from 5.47-5.7GHz supported */ |
136 | #define AR5K_EEPROM_JAP_11A_NEW_EN (((_v) >> 10) & 0x1) | 133 | #define AR5K_EEPROM_JAP_U1ODD_EN (((_v) >> 10) & 0x1) /* Japan UNII2 band (5.15-5.25GHz) on odd channels (5170, 5190, 5210, 5230) supported */ |
134 | #define AR5K_EEPROM_JAP_11A_NEW_EN (((_v) >> 11) & 0x1) /* Japan A mode enabled (using even channels) */ | ||
137 | 135 | ||
138 | /* calibration settings */ | 136 | /* calibration settings */ |
139 | #define AR5K_EEPROM_MODES_11A(_v) AR5K_EEPROM_OFF(_v, 0x00c5, 0x00d4) | 137 | #define AR5K_EEPROM_MODES_11A(_v) AR5K_EEPROM_OFF(_v, 0x00c5, 0x00d4) |
@@ -389,7 +387,49 @@ struct ath5k_edge_power { | |||
389 | bool flag; | 387 | bool flag; |
390 | }; | 388 | }; |
391 | 389 | ||
392 | /* EEPROM calibration data */ | 390 | /** |
391 | * struct ath5k_eeprom_info - EEPROM calibration data | ||
392 | * | ||
393 | * @ee_regdomain: ath/regd.c takes care of COUNTRY_ERD and WORLDWIDE_ROAMING | ||
394 | * flags | ||
395 | * @ee_ant_gain: Antenna gain in 0.5dB steps signed [5211 only?] | ||
396 | * @ee_cck_ofdm_gain_delta: difference in gainF to output the same power for | ||
397 | * OFDM and CCK packets | ||
398 | * @ee_cck_ofdm_power_delta: power difference between OFDM (6Mbps) and CCK | ||
399 | * (11Mbps) rate in G mode. 0.1dB steps | ||
400 | * @ee_scaled_cck_delta: for Japan Channel 14: 0.1dB resolution | ||
401 | * | ||
402 | * @ee_i_cal: Initial I coefficient to correct I/Q mismatch in the receive path | ||
403 | * @ee_q_cal: Initial Q coefficient to correct I/Q mismatch in the receive path | ||
404 | * @ee_fixed_bias: use ee_ob and ee_db settings or use automatic control | ||
405 | * @ee_switch_settling: RX/TX Switch settling time | ||
406 | * @ee_atn_tx_rx: Difference in attenuation between TX and RX in 1dB steps | ||
407 | * @ee_ant_control: Antenna Control Settings | ||
408 | * @ee_ob: Bias current for Output stage of PA | ||
409 | * B/G mode: Index [0] is used for AR2112/5112, otherwise [1] | ||
410 | * A mode: [0] 5.15-5.25 [1] 5.25-5.50 [2] 5.50-5.70 [3] 5.70-5.85 GHz | ||
411 | * @ee_db: Bias current for Output stage of PA. see @ee_ob | ||
412 | * @ee_tx_end2xlna_enable: Time difference from when BB finishes sending a frame | ||
413 | * to when the external LNA is activated | ||
414 | * @ee_tx_end2xpa_disable: Time difference from when BB finishes sending a frame | ||
415 | * to when the external PA switch is deactivated | ||
416 | * @ee_tx_frm2xpa_enable: Time difference from when MAC sends frame to when | ||
417 | * external PA switch is activated | ||
418 | * @ee_thr_62: Clear Channel Assessment (CCA) sensitivity | ||
419 | * (IEEE802.11a section 17.3.10.5 ) | ||
420 | * @ee_xlna_gain: Total gain of the LNA (information only) | ||
421 | * @ee_xpd: Use external (1) or internal power detector | ||
422 | * @ee_x_gain: Gain for external power detector output (differences in EEMAP | ||
423 | * versions!) | ||
424 | * @ee_i_gain: Initial gain value after reset | ||
425 | * @ee_margin_tx_rx: Margin in dB when final attenuation stage should be used | ||
426 | * | ||
427 | * @ee_false_detect: Backoff in Sensitivity (dB) on channels with spur signals | ||
428 | * @ee_noise_floor_thr: Noise floor threshold in 1dB steps | ||
429 | * @ee_adc_desired_size: Desired amplitude for ADC, used by AGC; in 0.5 dB steps | ||
430 | * @ee_pga_desired_size: Desired output of PGA (for BB gain) in 0.5 dB steps | ||
431 | * @ee_pd_gain_overlap: PD ADC curves need to overlap in 0.5dB steps (ee_map>=2) | ||
432 | */ | ||
393 | struct ath5k_eeprom_info { | 433 | struct ath5k_eeprom_info { |
394 | 434 | ||
395 | /* Header information */ | 435 | /* Header information */ |