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path: root/drivers/net/wireless/ath/ath5k/base.c
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Diffstat (limited to 'drivers/net/wireless/ath/ath5k/base.c')
-rw-r--r--drivers/net/wireless/ath/ath5k/base.c1138
1 files changed, 550 insertions, 588 deletions
diff --git a/drivers/net/wireless/ath/ath5k/base.c b/drivers/net/wireless/ath/ath5k/base.c
index dce848f76d7c..f54dff44ed50 100644
--- a/drivers/net/wireless/ath/ath5k/base.c
+++ b/drivers/net/wireless/ath/ath5k/base.c
@@ -86,7 +86,7 @@ MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
86MODULE_LICENSE("Dual BSD/GPL"); 86MODULE_LICENSE("Dual BSD/GPL");
87 87
88static int ath5k_init(struct ieee80211_hw *hw); 88static int ath5k_init(struct ieee80211_hw *hw);
89static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan, 89static int ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
90 bool skip_pcu); 90 bool skip_pcu);
91 91
92/* Known SREVs */ 92/* Known SREVs */
@@ -238,8 +238,8 @@ static const struct ath_ops ath5k_common_ops = {
238static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request) 238static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
239{ 239{
240 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 240 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
241 struct ath5k_softc *sc = hw->priv; 241 struct ath5k_hw *ah = hw->priv;
242 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah); 242 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
243 243
244 return ath_reg_notifier_apply(wiphy, request, regulatory); 244 return ath_reg_notifier_apply(wiphy, request, regulatory);
245} 245}
@@ -289,7 +289,7 @@ ath5k_setup_channels(struct ath5k_hw *ah, struct ieee80211_channel *channels,
289 band = IEEE80211_BAND_2GHZ; 289 band = IEEE80211_BAND_2GHZ;
290 break; 290 break;
291 default: 291 default:
292 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n"); 292 ATH5K_WARN(ah, "bad mode, not copying channels\n");
293 return 0; 293 return 0;
294 } 294 }
295 295
@@ -327,51 +327,50 @@ ath5k_setup_channels(struct ath5k_hw *ah, struct ieee80211_channel *channels,
327} 327}
328 328
329static void 329static void
330ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b) 330ath5k_setup_rate_idx(struct ath5k_hw *ah, struct ieee80211_supported_band *b)
331{ 331{
332 u8 i; 332 u8 i;
333 333
334 for (i = 0; i < AR5K_MAX_RATES; i++) 334 for (i = 0; i < AR5K_MAX_RATES; i++)
335 sc->rate_idx[b->band][i] = -1; 335 ah->rate_idx[b->band][i] = -1;
336 336
337 for (i = 0; i < b->n_bitrates; i++) { 337 for (i = 0; i < b->n_bitrates; i++) {
338 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i; 338 ah->rate_idx[b->band][b->bitrates[i].hw_value] = i;
339 if (b->bitrates[i].hw_value_short) 339 if (b->bitrates[i].hw_value_short)
340 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i; 340 ah->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
341 } 341 }
342} 342}
343 343
344static int 344static int
345ath5k_setup_bands(struct ieee80211_hw *hw) 345ath5k_setup_bands(struct ieee80211_hw *hw)
346{ 346{
347 struct ath5k_softc *sc = hw->priv; 347 struct ath5k_hw *ah = hw->priv;
348 struct ath5k_hw *ah = sc->ah;
349 struct ieee80211_supported_band *sband; 348 struct ieee80211_supported_band *sband;
350 int max_c, count_c = 0; 349 int max_c, count_c = 0;
351 int i; 350 int i;
352 351
353 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS); 352 BUILD_BUG_ON(ARRAY_SIZE(ah->sbands) < IEEE80211_NUM_BANDS);
354 max_c = ARRAY_SIZE(sc->channels); 353 max_c = ARRAY_SIZE(ah->channels);
355 354
356 /* 2GHz band */ 355 /* 2GHz band */
357 sband = &sc->sbands[IEEE80211_BAND_2GHZ]; 356 sband = &ah->sbands[IEEE80211_BAND_2GHZ];
358 sband->band = IEEE80211_BAND_2GHZ; 357 sband->band = IEEE80211_BAND_2GHZ;
359 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0]; 358 sband->bitrates = &ah->rates[IEEE80211_BAND_2GHZ][0];
360 359
361 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) { 360 if (test_bit(AR5K_MODE_11G, ah->ah_capabilities.cap_mode)) {
362 /* G mode */ 361 /* G mode */
363 memcpy(sband->bitrates, &ath5k_rates[0], 362 memcpy(sband->bitrates, &ath5k_rates[0],
364 sizeof(struct ieee80211_rate) * 12); 363 sizeof(struct ieee80211_rate) * 12);
365 sband->n_bitrates = 12; 364 sband->n_bitrates = 12;
366 365
367 sband->channels = sc->channels; 366 sband->channels = ah->channels;
368 sband->n_channels = ath5k_setup_channels(ah, sband->channels, 367 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
369 AR5K_MODE_11G, max_c); 368 AR5K_MODE_11G, max_c);
370 369
371 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband; 370 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
372 count_c = sband->n_channels; 371 count_c = sband->n_channels;
373 max_c -= count_c; 372 max_c -= count_c;
374 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) { 373 } else if (test_bit(AR5K_MODE_11B, ah->ah_capabilities.cap_mode)) {
375 /* B mode */ 374 /* B mode */
376 memcpy(sband->bitrates, &ath5k_rates[0], 375 memcpy(sband->bitrates, &ath5k_rates[0],
377 sizeof(struct ieee80211_rate) * 4); 376 sizeof(struct ieee80211_rate) * 4);
@@ -390,7 +389,7 @@ ath5k_setup_bands(struct ieee80211_hw *hw)
390 } 389 }
391 } 390 }
392 391
393 sband->channels = sc->channels; 392 sband->channels = ah->channels;
394 sband->n_channels = ath5k_setup_channels(ah, sband->channels, 393 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
395 AR5K_MODE_11B, max_c); 394 AR5K_MODE_11B, max_c);
396 395
@@ -398,27 +397,27 @@ ath5k_setup_bands(struct ieee80211_hw *hw)
398 count_c = sband->n_channels; 397 count_c = sband->n_channels;
399 max_c -= count_c; 398 max_c -= count_c;
400 } 399 }
401 ath5k_setup_rate_idx(sc, sband); 400 ath5k_setup_rate_idx(ah, sband);
402 401
403 /* 5GHz band, A mode */ 402 /* 5GHz band, A mode */
404 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) { 403 if (test_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode)) {
405 sband = &sc->sbands[IEEE80211_BAND_5GHZ]; 404 sband = &ah->sbands[IEEE80211_BAND_5GHZ];
406 sband->band = IEEE80211_BAND_5GHZ; 405 sband->band = IEEE80211_BAND_5GHZ;
407 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0]; 406 sband->bitrates = &ah->rates[IEEE80211_BAND_5GHZ][0];
408 407
409 memcpy(sband->bitrates, &ath5k_rates[4], 408 memcpy(sband->bitrates, &ath5k_rates[4],
410 sizeof(struct ieee80211_rate) * 8); 409 sizeof(struct ieee80211_rate) * 8);
411 sband->n_bitrates = 8; 410 sband->n_bitrates = 8;
412 411
413 sband->channels = &sc->channels[count_c]; 412 sband->channels = &ah->channels[count_c];
414 sband->n_channels = ath5k_setup_channels(ah, sband->channels, 413 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
415 AR5K_MODE_11A, max_c); 414 AR5K_MODE_11A, max_c);
416 415
417 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband; 416 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
418 } 417 }
419 ath5k_setup_rate_idx(sc, sband); 418 ath5k_setup_rate_idx(ah, sband);
420 419
421 ath5k_debug_dump_bands(sc); 420 ath5k_debug_dump_bands(ah);
422 421
423 return 0; 422 return 0;
424} 423}
@@ -428,14 +427,14 @@ ath5k_setup_bands(struct ieee80211_hw *hw)
428 * To accomplish this we must first cleanup any pending DMA, 427 * To accomplish this we must first cleanup any pending DMA,
429 * then restart stuff after a la ath5k_init. 428 * then restart stuff after a la ath5k_init.
430 * 429 *
431 * Called with sc->lock. 430 * Called with ah->lock.
432 */ 431 */
433int 432int
434ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan) 433ath5k_chan_set(struct ath5k_hw *ah, struct ieee80211_channel *chan)
435{ 434{
436 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, 435 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
437 "channel set, resetting (%u -> %u MHz)\n", 436 "channel set, resetting (%u -> %u MHz)\n",
438 sc->curchan->center_freq, chan->center_freq); 437 ah->curchan->center_freq, chan->center_freq);
439 438
440 /* 439 /*
441 * To switch channels clear any pending DMA operations; 440 * To switch channels clear any pending DMA operations;
@@ -443,7 +442,7 @@ ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
443 * hardware at the new frequency, and then re-enable 442 * hardware at the new frequency, and then re-enable
444 * the relevant bits of the h/w. 443 * the relevant bits of the h/w.
445 */ 444 */
446 return ath5k_reset(sc, chan, true); 445 return ath5k_reset(ah, chan, true);
447} 446}
448 447
449void ath5k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 448void ath5k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
@@ -487,10 +486,10 @@ void ath5k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
487} 486}
488 487
489void 488void
490ath5k_update_bssid_mask_and_opmode(struct ath5k_softc *sc, 489ath5k_update_bssid_mask_and_opmode(struct ath5k_hw *ah,
491 struct ieee80211_vif *vif) 490 struct ieee80211_vif *vif)
492{ 491{
493 struct ath_common *common = ath5k_hw_common(sc->ah); 492 struct ath_common *common = ath5k_hw_common(ah);
494 struct ath5k_vif_iter_data iter_data; 493 struct ath5k_vif_iter_data iter_data;
495 u32 rfilt; 494 u32 rfilt;
496 495
@@ -509,24 +508,24 @@ ath5k_update_bssid_mask_and_opmode(struct ath5k_softc *sc,
509 ath5k_vif_iter(&iter_data, vif->addr, vif); 508 ath5k_vif_iter(&iter_data, vif->addr, vif);
510 509
511 /* Get list of all active MAC addresses */ 510 /* Get list of all active MAC addresses */
512 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath5k_vif_iter, 511 ieee80211_iterate_active_interfaces_atomic(ah->hw, ath5k_vif_iter,
513 &iter_data); 512 &iter_data);
514 memcpy(sc->bssidmask, iter_data.mask, ETH_ALEN); 513 memcpy(ah->bssidmask, iter_data.mask, ETH_ALEN);
515 514
516 sc->opmode = iter_data.opmode; 515 ah->opmode = iter_data.opmode;
517 if (sc->opmode == NL80211_IFTYPE_UNSPECIFIED) 516 if (ah->opmode == NL80211_IFTYPE_UNSPECIFIED)
518 /* Nothing active, default to station mode */ 517 /* Nothing active, default to station mode */
519 sc->opmode = NL80211_IFTYPE_STATION; 518 ah->opmode = NL80211_IFTYPE_STATION;
520 519
521 ath5k_hw_set_opmode(sc->ah, sc->opmode); 520 ath5k_hw_set_opmode(ah, ah->opmode);
522 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n", 521 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n",
523 sc->opmode, ath_opmode_to_string(sc->opmode)); 522 ah->opmode, ath_opmode_to_string(ah->opmode));
524 523
525 if (iter_data.need_set_hw_addr && iter_data.found_active) 524 if (iter_data.need_set_hw_addr && iter_data.found_active)
526 ath5k_hw_set_lladdr(sc->ah, iter_data.active_mac); 525 ath5k_hw_set_lladdr(ah, iter_data.active_mac);
527 526
528 if (ath5k_hw_hasbssidmask(sc->ah)) 527 if (ath5k_hw_hasbssidmask(ah))
529 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask); 528 ath5k_hw_set_bssid_mask(ah, ah->bssidmask);
530 529
531 /* Set up RX Filter */ 530 /* Set up RX Filter */
532 if (iter_data.n_stas > 1) { 531 if (iter_data.n_stas > 1) {
@@ -534,16 +533,16 @@ ath5k_update_bssid_mask_and_opmode(struct ath5k_softc *sc,
534 * different APs, ARPs are not received (most of the time?) 533 * different APs, ARPs are not received (most of the time?)
535 * Enabling PROMISC appears to fix that problem. 534 * Enabling PROMISC appears to fix that problem.
536 */ 535 */
537 sc->filter_flags |= AR5K_RX_FILTER_PROM; 536 ah->filter_flags |= AR5K_RX_FILTER_PROM;
538 } 537 }
539 538
540 rfilt = sc->filter_flags; 539 rfilt = ah->filter_flags;
541 ath5k_hw_set_rx_filter(sc->ah, rfilt); 540 ath5k_hw_set_rx_filter(ah, rfilt);
542 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt); 541 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
543} 542}
544 543
545static inline int 544static inline int
546ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix) 545ath5k_hw_to_driver_rix(struct ath5k_hw *ah, int hw_rix)
547{ 546{
548 int rix; 547 int rix;
549 548
@@ -552,7 +551,7 @@ ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
552 "hw_rix out of bounds: %x\n", hw_rix)) 551 "hw_rix out of bounds: %x\n", hw_rix))
553 return 0; 552 return 0;
554 553
555 rix = sc->rate_idx[sc->curchan->band][hw_rix]; 554 rix = ah->rate_idx[ah->curchan->band][hw_rix];
556 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix)) 555 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
557 rix = 0; 556 rix = 0;
558 557
@@ -564,9 +563,9 @@ ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
564\***************/ 563\***************/
565 564
566static 565static
567struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr) 566struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_hw *ah, dma_addr_t *skb_addr)
568{ 567{
569 struct ath_common *common = ath5k_hw_common(sc->ah); 568 struct ath_common *common = ath5k_hw_common(ah);
570 struct sk_buff *skb; 569 struct sk_buff *skb;
571 570
572 /* 571 /*
@@ -578,17 +577,17 @@ struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
578 GFP_ATOMIC); 577 GFP_ATOMIC);
579 578
580 if (!skb) { 579 if (!skb) {
581 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n", 580 ATH5K_ERR(ah, "can't alloc skbuff of size %u\n",
582 common->rx_bufsize); 581 common->rx_bufsize);
583 return NULL; 582 return NULL;
584 } 583 }
585 584
586 *skb_addr = dma_map_single(sc->dev, 585 *skb_addr = dma_map_single(ah->dev,
587 skb->data, common->rx_bufsize, 586 skb->data, common->rx_bufsize,
588 DMA_FROM_DEVICE); 587 DMA_FROM_DEVICE);
589 588
590 if (unlikely(dma_mapping_error(sc->dev, *skb_addr))) { 589 if (unlikely(dma_mapping_error(ah->dev, *skb_addr))) {
591 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__); 590 ATH5K_ERR(ah, "%s: DMA mapping failed\n", __func__);
592 dev_kfree_skb(skb); 591 dev_kfree_skb(skb);
593 return NULL; 592 return NULL;
594 } 593 }
@@ -596,15 +595,14 @@ struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
596} 595}
597 596
598static int 597static int
599ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf) 598ath5k_rxbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf)
600{ 599{
601 struct ath5k_hw *ah = sc->ah;
602 struct sk_buff *skb = bf->skb; 600 struct sk_buff *skb = bf->skb;
603 struct ath5k_desc *ds; 601 struct ath5k_desc *ds;
604 int ret; 602 int ret;
605 603
606 if (!skb) { 604 if (!skb) {
607 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr); 605 skb = ath5k_rx_skb_alloc(ah, &bf->skbaddr);
608 if (!skb) 606 if (!skb)
609 return -ENOMEM; 607 return -ENOMEM;
610 bf->skb = skb; 608 bf->skb = skb;
@@ -630,13 +628,13 @@ ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
630 ds->ds_data = bf->skbaddr; 628 ds->ds_data = bf->skbaddr;
631 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0); 629 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
632 if (ret) { 630 if (ret) {
633 ATH5K_ERR(sc, "%s: could not setup RX desc\n", __func__); 631 ATH5K_ERR(ah, "%s: could not setup RX desc\n", __func__);
634 return ret; 632 return ret;
635 } 633 }
636 634
637 if (sc->rxlink != NULL) 635 if (ah->rxlink != NULL)
638 *sc->rxlink = bf->daddr; 636 *ah->rxlink = bf->daddr;
639 sc->rxlink = &ds->ds_link; 637 ah->rxlink = &ds->ds_link;
640 return 0; 638 return 0;
641} 639}
642 640
@@ -664,10 +662,9 @@ static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
664} 662}
665 663
666static int 664static int
667ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf, 665ath5k_txbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf,
668 struct ath5k_txq *txq, int padsize) 666 struct ath5k_txq *txq, int padsize)
669{ 667{
670 struct ath5k_hw *ah = sc->ah;
671 struct ath5k_desc *ds = bf->desc; 668 struct ath5k_desc *ds = bf->desc;
672 struct sk_buff *skb = bf->skb; 669 struct sk_buff *skb = bf->skb;
673 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 670 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
@@ -683,10 +680,10 @@ ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
683 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK; 680 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
684 681
685 /* XXX endianness */ 682 /* XXX endianness */
686 bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len, 683 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len,
687 DMA_TO_DEVICE); 684 DMA_TO_DEVICE);
688 685
689 rate = ieee80211_get_tx_rate(sc->hw, info); 686 rate = ieee80211_get_tx_rate(ah->hw, info);
690 if (!rate) { 687 if (!rate) {
691 ret = -EINVAL; 688 ret = -EINVAL;
692 goto err_unmap; 689 goto err_unmap;
@@ -710,20 +707,20 @@ ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
710 } 707 }
711 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) { 708 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
712 flags |= AR5K_TXDESC_RTSENA; 709 flags |= AR5K_TXDESC_RTSENA;
713 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value; 710 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value;
714 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw, 711 duration = le16_to_cpu(ieee80211_rts_duration(ah->hw,
715 info->control.vif, pktlen, info)); 712 info->control.vif, pktlen, info));
716 } 713 }
717 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { 714 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
718 flags |= AR5K_TXDESC_CTSENA; 715 flags |= AR5K_TXDESC_CTSENA;
719 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value; 716 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value;
720 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw, 717 duration = le16_to_cpu(ieee80211_ctstoself_duration(ah->hw,
721 info->control.vif, pktlen, info)); 718 info->control.vif, pktlen, info));
722 } 719 }
723 ret = ah->ah_setup_tx_desc(ah, ds, pktlen, 720 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
724 ieee80211_get_hdrlen_from_skb(skb), padsize, 721 ieee80211_get_hdrlen_from_skb(skb), padsize,
725 get_hw_packet_type(skb), 722 get_hw_packet_type(skb),
726 (sc->power_level * 2), 723 (ah->power_level * 2),
727 hw_rate, 724 hw_rate,
728 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags, 725 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
729 cts_rate, duration); 726 cts_rate, duration);
@@ -733,7 +730,7 @@ ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
733 memset(mrr_rate, 0, sizeof(mrr_rate)); 730 memset(mrr_rate, 0, sizeof(mrr_rate));
734 memset(mrr_tries, 0, sizeof(mrr_tries)); 731 memset(mrr_tries, 0, sizeof(mrr_tries));
735 for (i = 0; i < 3; i++) { 732 for (i = 0; i < 3; i++) {
736 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i); 733 rate = ieee80211_get_alt_retry_rate(ah->hw, info, i);
737 if (!rate) 734 if (!rate)
738 break; 735 break;
739 736
@@ -764,7 +761,7 @@ ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
764 761
765 return 0; 762 return 0;
766err_unmap: 763err_unmap:
767 dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE); 764 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
768 return ret; 765 return ret;
769} 766}
770 767
@@ -773,7 +770,7 @@ err_unmap:
773\*******************/ 770\*******************/
774 771
775static int 772static int
776ath5k_desc_alloc(struct ath5k_softc *sc) 773ath5k_desc_alloc(struct ath5k_hw *ah)
777{ 774{
778 struct ath5k_desc *ds; 775 struct ath5k_desc *ds;
779 struct ath5k_buf *bf; 776 struct ath5k_buf *bf;
@@ -782,68 +779,68 @@ ath5k_desc_alloc(struct ath5k_softc *sc)
782 int ret; 779 int ret;
783 780
784 /* allocate descriptors */ 781 /* allocate descriptors */
785 sc->desc_len = sizeof(struct ath5k_desc) * 782 ah->desc_len = sizeof(struct ath5k_desc) *
786 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1); 783 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
787 784
788 sc->desc = dma_alloc_coherent(sc->dev, sc->desc_len, 785 ah->desc = dma_alloc_coherent(ah->dev, ah->desc_len,
789 &sc->desc_daddr, GFP_KERNEL); 786 &ah->desc_daddr, GFP_KERNEL);
790 if (sc->desc == NULL) { 787 if (ah->desc == NULL) {
791 ATH5K_ERR(sc, "can't allocate descriptors\n"); 788 ATH5K_ERR(ah, "can't allocate descriptors\n");
792 ret = -ENOMEM; 789 ret = -ENOMEM;
793 goto err; 790 goto err;
794 } 791 }
795 ds = sc->desc; 792 ds = ah->desc;
796 da = sc->desc_daddr; 793 da = ah->desc_daddr;
797 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n", 794 ATH5K_DBG(ah, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
798 ds, sc->desc_len, (unsigned long long)sc->desc_daddr); 795 ds, ah->desc_len, (unsigned long long)ah->desc_daddr);
799 796
800 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF, 797 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
801 sizeof(struct ath5k_buf), GFP_KERNEL); 798 sizeof(struct ath5k_buf), GFP_KERNEL);
802 if (bf == NULL) { 799 if (bf == NULL) {
803 ATH5K_ERR(sc, "can't allocate bufptr\n"); 800 ATH5K_ERR(ah, "can't allocate bufptr\n");
804 ret = -ENOMEM; 801 ret = -ENOMEM;
805 goto err_free; 802 goto err_free;
806 } 803 }
807 sc->bufptr = bf; 804 ah->bufptr = bf;
808 805
809 INIT_LIST_HEAD(&sc->rxbuf); 806 INIT_LIST_HEAD(&ah->rxbuf);
810 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) { 807 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
811 bf->desc = ds; 808 bf->desc = ds;
812 bf->daddr = da; 809 bf->daddr = da;
813 list_add_tail(&bf->list, &sc->rxbuf); 810 list_add_tail(&bf->list, &ah->rxbuf);
814 } 811 }
815 812
816 INIT_LIST_HEAD(&sc->txbuf); 813 INIT_LIST_HEAD(&ah->txbuf);
817 sc->txbuf_len = ATH_TXBUF; 814 ah->txbuf_len = ATH_TXBUF;
818 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, da += sizeof(*ds)) { 815 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
819 bf->desc = ds; 816 bf->desc = ds;
820 bf->daddr = da; 817 bf->daddr = da;
821 list_add_tail(&bf->list, &sc->txbuf); 818 list_add_tail(&bf->list, &ah->txbuf);
822 } 819 }
823 820
824 /* beacon buffers */ 821 /* beacon buffers */
825 INIT_LIST_HEAD(&sc->bcbuf); 822 INIT_LIST_HEAD(&ah->bcbuf);
826 for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) { 823 for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) {
827 bf->desc = ds; 824 bf->desc = ds;
828 bf->daddr = da; 825 bf->daddr = da;
829 list_add_tail(&bf->list, &sc->bcbuf); 826 list_add_tail(&bf->list, &ah->bcbuf);
830 } 827 }
831 828
832 return 0; 829 return 0;
833err_free: 830err_free:
834 dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr); 831 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr);
835err: 832err:
836 sc->desc = NULL; 833 ah->desc = NULL;
837 return ret; 834 return ret;
838} 835}
839 836
840void 837void
841ath5k_txbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf) 838ath5k_txbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf)
842{ 839{
843 BUG_ON(!bf); 840 BUG_ON(!bf);
844 if (!bf->skb) 841 if (!bf->skb)
845 return; 842 return;
846 dma_unmap_single(sc->dev, bf->skbaddr, bf->skb->len, 843 dma_unmap_single(ah->dev, bf->skbaddr, bf->skb->len,
847 DMA_TO_DEVICE); 844 DMA_TO_DEVICE);
848 dev_kfree_skb_any(bf->skb); 845 dev_kfree_skb_any(bf->skb);
849 bf->skb = NULL; 846 bf->skb = NULL;
@@ -852,15 +849,14 @@ ath5k_txbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf)
852} 849}
853 850
854void 851void
855ath5k_rxbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf) 852ath5k_rxbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf)
856{ 853{
857 struct ath5k_hw *ah = sc->ah;
858 struct ath_common *common = ath5k_hw_common(ah); 854 struct ath_common *common = ath5k_hw_common(ah);
859 855
860 BUG_ON(!bf); 856 BUG_ON(!bf);
861 if (!bf->skb) 857 if (!bf->skb)
862 return; 858 return;
863 dma_unmap_single(sc->dev, bf->skbaddr, common->rx_bufsize, 859 dma_unmap_single(ah->dev, bf->skbaddr, common->rx_bufsize,
864 DMA_FROM_DEVICE); 860 DMA_FROM_DEVICE);
865 dev_kfree_skb_any(bf->skb); 861 dev_kfree_skb_any(bf->skb);
866 bf->skb = NULL; 862 bf->skb = NULL;
@@ -869,24 +865,24 @@ ath5k_rxbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf)
869} 865}
870 866
871static void 867static void
872ath5k_desc_free(struct ath5k_softc *sc) 868ath5k_desc_free(struct ath5k_hw *ah)
873{ 869{
874 struct ath5k_buf *bf; 870 struct ath5k_buf *bf;
875 871
876 list_for_each_entry(bf, &sc->txbuf, list) 872 list_for_each_entry(bf, &ah->txbuf, list)
877 ath5k_txbuf_free_skb(sc, bf); 873 ath5k_txbuf_free_skb(ah, bf);
878 list_for_each_entry(bf, &sc->rxbuf, list) 874 list_for_each_entry(bf, &ah->rxbuf, list)
879 ath5k_rxbuf_free_skb(sc, bf); 875 ath5k_rxbuf_free_skb(ah, bf);
880 list_for_each_entry(bf, &sc->bcbuf, list) 876 list_for_each_entry(bf, &ah->bcbuf, list)
881 ath5k_txbuf_free_skb(sc, bf); 877 ath5k_txbuf_free_skb(ah, bf);
882 878
883 /* Free memory associated with all descriptors */ 879 /* Free memory associated with all descriptors */
884 dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr); 880 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr);
885 sc->desc = NULL; 881 ah->desc = NULL;
886 sc->desc_daddr = 0; 882 ah->desc_daddr = 0;
887 883
888 kfree(sc->bufptr); 884 kfree(ah->bufptr);
889 sc->bufptr = NULL; 885 ah->bufptr = NULL;
890} 886}
891 887
892 888
@@ -895,10 +891,9 @@ ath5k_desc_free(struct ath5k_softc *sc)
895\**************/ 891\**************/
896 892
897static struct ath5k_txq * 893static struct ath5k_txq *
898ath5k_txq_setup(struct ath5k_softc *sc, 894ath5k_txq_setup(struct ath5k_hw *ah,
899 int qtype, int subtype) 895 int qtype, int subtype)
900{ 896{
901 struct ath5k_hw *ah = sc->ah;
902 struct ath5k_txq *txq; 897 struct ath5k_txq *txq;
903 struct ath5k_txq_info qi = { 898 struct ath5k_txq_info qi = {
904 .tqi_subtype = subtype, 899 .tqi_subtype = subtype,
@@ -932,13 +927,13 @@ ath5k_txq_setup(struct ath5k_softc *sc,
932 */ 927 */
933 return ERR_PTR(qnum); 928 return ERR_PTR(qnum);
934 } 929 }
935 if (qnum >= ARRAY_SIZE(sc->txqs)) { 930 if (qnum >= ARRAY_SIZE(ah->txqs)) {
936 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n", 931 ATH5K_ERR(ah, "hw qnum %u out of range, max %tu!\n",
937 qnum, ARRAY_SIZE(sc->txqs)); 932 qnum, ARRAY_SIZE(ah->txqs));
938 ath5k_hw_release_tx_queue(ah, qnum); 933 ath5k_hw_release_tx_queue(ah, qnum);
939 return ERR_PTR(-EINVAL); 934 return ERR_PTR(-EINVAL);
940 } 935 }
941 txq = &sc->txqs[qnum]; 936 txq = &ah->txqs[qnum];
942 if (!txq->setup) { 937 if (!txq->setup) {
943 txq->qnum = qnum; 938 txq->qnum = qnum;
944 txq->link = NULL; 939 txq->link = NULL;
@@ -950,7 +945,7 @@ ath5k_txq_setup(struct ath5k_softc *sc,
950 txq->txq_poll_mark = false; 945 txq->txq_poll_mark = false;
951 txq->txq_stuck = 0; 946 txq->txq_stuck = 0;
952 } 947 }
953 return &sc->txqs[qnum]; 948 return &ah->txqs[qnum];
954} 949}
955 950
956static int 951static int
@@ -970,18 +965,17 @@ ath5k_beaconq_setup(struct ath5k_hw *ah)
970} 965}
971 966
972static int 967static int
973ath5k_beaconq_config(struct ath5k_softc *sc) 968ath5k_beaconq_config(struct ath5k_hw *ah)
974{ 969{
975 struct ath5k_hw *ah = sc->ah;
976 struct ath5k_txq_info qi; 970 struct ath5k_txq_info qi;
977 int ret; 971 int ret;
978 972
979 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi); 973 ret = ath5k_hw_get_tx_queueprops(ah, ah->bhalq, &qi);
980 if (ret) 974 if (ret)
981 goto err; 975 goto err;
982 976
983 if (sc->opmode == NL80211_IFTYPE_AP || 977 if (ah->opmode == NL80211_IFTYPE_AP ||
984 sc->opmode == NL80211_IFTYPE_MESH_POINT) { 978 ah->opmode == NL80211_IFTYPE_MESH_POINT) {
985 /* 979 /*
986 * Always burst out beacon and CAB traffic 980 * Always burst out beacon and CAB traffic
987 * (aifs = cwmin = cwmax = 0) 981 * (aifs = cwmin = cwmax = 0)
@@ -989,7 +983,7 @@ ath5k_beaconq_config(struct ath5k_softc *sc)
989 qi.tqi_aifs = 0; 983 qi.tqi_aifs = 0;
990 qi.tqi_cw_min = 0; 984 qi.tqi_cw_min = 0;
991 qi.tqi_cw_max = 0; 985 qi.tqi_cw_max = 0;
992 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) { 986 } else if (ah->opmode == NL80211_IFTYPE_ADHOC) {
993 /* 987 /*
994 * Adhoc mode; backoff between 0 and (2 * cw_min). 988 * Adhoc mode; backoff between 0 and (2 * cw_min).
995 */ 989 */
@@ -998,17 +992,17 @@ ath5k_beaconq_config(struct ath5k_softc *sc)
998 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN; 992 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN;
999 } 993 }
1000 994
1001 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 995 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1002 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n", 996 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1003 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max); 997 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1004 998
1005 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi); 999 ret = ath5k_hw_set_tx_queueprops(ah, ah->bhalq, &qi);
1006 if (ret) { 1000 if (ret) {
1007 ATH5K_ERR(sc, "%s: unable to update parameters for beacon " 1001 ATH5K_ERR(ah, "%s: unable to update parameters for beacon "
1008 "hardware queue!\n", __func__); 1002 "hardware queue!\n", __func__);
1009 goto err; 1003 goto err;
1010 } 1004 }
1011 ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */ 1005 ret = ath5k_hw_reset_tx_queue(ah, ah->bhalq); /* push to h/w */
1012 if (ret) 1006 if (ret)
1013 goto err; 1007 goto err;
1014 1008
@@ -1017,7 +1011,7 @@ ath5k_beaconq_config(struct ath5k_softc *sc)
1017 if (ret) 1011 if (ret)
1018 goto err; 1012 goto err;
1019 1013
1020 qi.tqi_ready_time = (sc->bintval * 80) / 100; 1014 qi.tqi_ready_time = (ah->bintval * 80) / 100;
1021 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi); 1015 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1022 if (ret) 1016 if (ret)
1023 goto err; 1017 goto err;
@@ -1030,7 +1024,7 @@ err:
1030/** 1024/**
1031 * ath5k_drain_tx_buffs - Empty tx buffers 1025 * ath5k_drain_tx_buffs - Empty tx buffers
1032 * 1026 *
1033 * @sc The &struct ath5k_softc 1027 * @ah The &struct ath5k_hw
1034 * 1028 *
1035 * Empty tx buffers from all queues in preparation 1029 * Empty tx buffers from all queues in preparation
1036 * of a reset or during shutdown. 1030 * of a reset or during shutdown.
@@ -1039,26 +1033,26 @@ err:
1039 * we do not need to block ath5k_tx_tasklet 1033 * we do not need to block ath5k_tx_tasklet
1040 */ 1034 */
1041static void 1035static void
1042ath5k_drain_tx_buffs(struct ath5k_softc *sc) 1036ath5k_drain_tx_buffs(struct ath5k_hw *ah)
1043{ 1037{
1044 struct ath5k_txq *txq; 1038 struct ath5k_txq *txq;
1045 struct ath5k_buf *bf, *bf0; 1039 struct ath5k_buf *bf, *bf0;
1046 int i; 1040 int i;
1047 1041
1048 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) { 1042 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) {
1049 if (sc->txqs[i].setup) { 1043 if (ah->txqs[i].setup) {
1050 txq = &sc->txqs[i]; 1044 txq = &ah->txqs[i];
1051 spin_lock_bh(&txq->lock); 1045 spin_lock_bh(&txq->lock);
1052 list_for_each_entry_safe(bf, bf0, &txq->q, list) { 1046 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1053 ath5k_debug_printtxbuf(sc, bf); 1047 ath5k_debug_printtxbuf(ah, bf);
1054 1048
1055 ath5k_txbuf_free_skb(sc, bf); 1049 ath5k_txbuf_free_skb(ah, bf);
1056 1050
1057 spin_lock_bh(&sc->txbuflock); 1051 spin_lock_bh(&ah->txbuflock);
1058 list_move_tail(&bf->list, &sc->txbuf); 1052 list_move_tail(&bf->list, &ah->txbuf);
1059 sc->txbuf_len++; 1053 ah->txbuf_len++;
1060 txq->txq_len--; 1054 txq->txq_len--;
1061 spin_unlock_bh(&sc->txbuflock); 1055 spin_unlock_bh(&ah->txbuflock);
1062 } 1056 }
1063 txq->link = NULL; 1057 txq->link = NULL;
1064 txq->txq_poll_mark = false; 1058 txq->txq_poll_mark = false;
@@ -1068,14 +1062,14 @@ ath5k_drain_tx_buffs(struct ath5k_softc *sc)
1068} 1062}
1069 1063
1070static void 1064static void
1071ath5k_txq_release(struct ath5k_softc *sc) 1065ath5k_txq_release(struct ath5k_hw *ah)
1072{ 1066{
1073 struct ath5k_txq *txq = sc->txqs; 1067 struct ath5k_txq *txq = ah->txqs;
1074 unsigned int i; 1068 unsigned int i;
1075 1069
1076 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++) 1070 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++, txq++)
1077 if (txq->setup) { 1071 if (txq->setup) {
1078 ath5k_hw_release_tx_queue(sc->ah, txq->qnum); 1072 ath5k_hw_release_tx_queue(ah, txq->qnum);
1079 txq->setup = false; 1073 txq->setup = false;
1080 } 1074 }
1081} 1075}
@@ -1089,33 +1083,32 @@ ath5k_txq_release(struct ath5k_softc *sc)
1089 * Enable the receive h/w following a reset. 1083 * Enable the receive h/w following a reset.
1090 */ 1084 */
1091static int 1085static int
1092ath5k_rx_start(struct ath5k_softc *sc) 1086ath5k_rx_start(struct ath5k_hw *ah)
1093{ 1087{
1094 struct ath5k_hw *ah = sc->ah;
1095 struct ath_common *common = ath5k_hw_common(ah); 1088 struct ath_common *common = ath5k_hw_common(ah);
1096 struct ath5k_buf *bf; 1089 struct ath5k_buf *bf;
1097 int ret; 1090 int ret;
1098 1091
1099 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz); 1092 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz);
1100 1093
1101 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n", 1094 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1102 common->cachelsz, common->rx_bufsize); 1095 common->cachelsz, common->rx_bufsize);
1103 1096
1104 spin_lock_bh(&sc->rxbuflock); 1097 spin_lock_bh(&ah->rxbuflock);
1105 sc->rxlink = NULL; 1098 ah->rxlink = NULL;
1106 list_for_each_entry(bf, &sc->rxbuf, list) { 1099 list_for_each_entry(bf, &ah->rxbuf, list) {
1107 ret = ath5k_rxbuf_setup(sc, bf); 1100 ret = ath5k_rxbuf_setup(ah, bf);
1108 if (ret != 0) { 1101 if (ret != 0) {
1109 spin_unlock_bh(&sc->rxbuflock); 1102 spin_unlock_bh(&ah->rxbuflock);
1110 goto err; 1103 goto err;
1111 } 1104 }
1112 } 1105 }
1113 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list); 1106 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list);
1114 ath5k_hw_set_rxdp(ah, bf->daddr); 1107 ath5k_hw_set_rxdp(ah, bf->daddr);
1115 spin_unlock_bh(&sc->rxbuflock); 1108 spin_unlock_bh(&ah->rxbuflock);
1116 1109
1117 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */ 1110 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
1118 ath5k_update_bssid_mask_and_opmode(sc, NULL); /* set filters, etc. */ 1111 ath5k_update_bssid_mask_and_opmode(ah, NULL); /* set filters, etc. */
1119 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */ 1112 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1120 1113
1121 return 0; 1114 return 0;
@@ -1131,21 +1124,19 @@ err:
1131 * does. 1124 * does.
1132 */ 1125 */
1133static void 1126static void
1134ath5k_rx_stop(struct ath5k_softc *sc) 1127ath5k_rx_stop(struct ath5k_hw *ah)
1135{ 1128{
1136 struct ath5k_hw *ah = sc->ah;
1137 1129
1138 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */ 1130 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1139 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */ 1131 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
1140 1132
1141 ath5k_debug_printrxbuffs(sc, ah); 1133 ath5k_debug_printrxbuffs(ah);
1142} 1134}
1143 1135
1144static unsigned int 1136static unsigned int
1145ath5k_rx_decrypted(struct ath5k_softc *sc, struct sk_buff *skb, 1137ath5k_rx_decrypted(struct ath5k_hw *ah, struct sk_buff *skb,
1146 struct ath5k_rx_status *rs) 1138 struct ath5k_rx_status *rs)
1147{ 1139{
1148 struct ath5k_hw *ah = sc->ah;
1149 struct ath_common *common = ath5k_hw_common(ah); 1140 struct ath_common *common = ath5k_hw_common(ah);
1150 struct ieee80211_hdr *hdr = (void *)skb->data; 1141 struct ieee80211_hdr *hdr = (void *)skb->data;
1151 unsigned int keyix, hlen; 1142 unsigned int keyix, hlen;
@@ -1172,10 +1163,10 @@ ath5k_rx_decrypted(struct ath5k_softc *sc, struct sk_buff *skb,
1172 1163
1173 1164
1174static void 1165static void
1175ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb, 1166ath5k_check_ibss_tsf(struct ath5k_hw *ah, struct sk_buff *skb,
1176 struct ieee80211_rx_status *rxs) 1167 struct ieee80211_rx_status *rxs)
1177{ 1168{
1178 struct ath_common *common = ath5k_hw_common(sc->ah); 1169 struct ath_common *common = ath5k_hw_common(ah);
1179 u64 tsf, bc_tstamp; 1170 u64 tsf, bc_tstamp;
1180 u32 hw_tu; 1171 u32 hw_tu;
1181 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 1172 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
@@ -1188,11 +1179,11 @@ ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1188 * have updated the local TSF. We have to work around various 1179 * have updated the local TSF. We have to work around various
1189 * hardware bugs, though... 1180 * hardware bugs, though...
1190 */ 1181 */
1191 tsf = ath5k_hw_get_tsf64(sc->ah); 1182 tsf = ath5k_hw_get_tsf64(ah);
1192 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp); 1183 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1193 hw_tu = TSF_TO_TU(tsf); 1184 hw_tu = TSF_TO_TU(tsf);
1194 1185
1195 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 1186 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
1196 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n", 1187 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1197 (unsigned long long)bc_tstamp, 1188 (unsigned long long)bc_tstamp,
1198 (unsigned long long)rxs->mactime, 1189 (unsigned long long)rxs->mactime,
@@ -1211,7 +1202,7 @@ ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1211 * received, not like mac80211 which defines it at the start. 1202 * received, not like mac80211 which defines it at the start.
1212 */ 1203 */
1213 if (bc_tstamp > rxs->mactime) { 1204 if (bc_tstamp > rxs->mactime) {
1214 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 1205 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
1215 "fixing mactime from %llx to %llx\n", 1206 "fixing mactime from %llx to %llx\n",
1216 (unsigned long long)rxs->mactime, 1207 (unsigned long long)rxs->mactime,
1217 (unsigned long long)tsf); 1208 (unsigned long long)tsf);
@@ -1224,25 +1215,24 @@ ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1224 * beacons. This also takes care of synchronizing beacon sending 1215 * beacons. This also takes care of synchronizing beacon sending
1225 * times with other stations. 1216 * times with other stations.
1226 */ 1217 */
1227 if (hw_tu >= sc->nexttbtt) 1218 if (hw_tu >= ah->nexttbtt)
1228 ath5k_beacon_update_timers(sc, bc_tstamp); 1219 ath5k_beacon_update_timers(ah, bc_tstamp);
1229 1220
1230 /* Check if the beacon timers are still correct, because a TSF 1221 /* Check if the beacon timers are still correct, because a TSF
1231 * update might have created a window between them - for a 1222 * update might have created a window between them - for a
1232 * longer description see the comment of this function: */ 1223 * longer description see the comment of this function: */
1233 if (!ath5k_hw_check_beacon_timers(sc->ah, sc->bintval)) { 1224 if (!ath5k_hw_check_beacon_timers(ah, ah->bintval)) {
1234 ath5k_beacon_update_timers(sc, bc_tstamp); 1225 ath5k_beacon_update_timers(ah, bc_tstamp);
1235 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 1226 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
1236 "fixed beacon timers after beacon receive\n"); 1227 "fixed beacon timers after beacon receive\n");
1237 } 1228 }
1238 } 1229 }
1239} 1230}
1240 1231
1241static void 1232static void
1242ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi) 1233ath5k_update_beacon_rssi(struct ath5k_hw *ah, struct sk_buff *skb, int rssi)
1243{ 1234{
1244 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 1235 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1245 struct ath5k_hw *ah = sc->ah;
1246 struct ath_common *common = ath5k_hw_common(ah); 1236 struct ath_common *common = ath5k_hw_common(ah);
1247 1237
1248 /* only beacons from our BSSID */ 1238 /* only beacons from our BSSID */
@@ -1324,7 +1314,7 @@ static int ath5k_remove_padding(struct sk_buff *skb)
1324} 1314}
1325 1315
1326static void 1316static void
1327ath5k_receive_frame(struct ath5k_softc *sc, struct sk_buff *skb, 1317ath5k_receive_frame(struct ath5k_hw *ah, struct sk_buff *skb,
1328 struct ath5k_rx_status *rs) 1318 struct ath5k_rx_status *rs)
1329{ 1319{
1330 struct ieee80211_rx_status *rxs; 1320 struct ieee80211_rx_status *rxs;
@@ -1357,37 +1347,37 @@ ath5k_receive_frame(struct ath5k_softc *sc, struct sk_buff *skb,
1357 * impossible to comply to that. This affects IBSS merge only 1347 * impossible to comply to that. This affects IBSS merge only
1358 * right now, so it's not too bad... 1348 * right now, so it's not too bad...
1359 */ 1349 */
1360 rxs->mactime = ath5k_extend_tsf(sc->ah, rs->rs_tstamp); 1350 rxs->mactime = ath5k_extend_tsf(ah, rs->rs_tstamp);
1361 rxs->flag |= RX_FLAG_MACTIME_MPDU; 1351 rxs->flag |= RX_FLAG_MACTIME_MPDU;
1362 1352
1363 rxs->freq = sc->curchan->center_freq; 1353 rxs->freq = ah->curchan->center_freq;
1364 rxs->band = sc->curchan->band; 1354 rxs->band = ah->curchan->band;
1365 1355
1366 rxs->signal = sc->ah->ah_noise_floor + rs->rs_rssi; 1356 rxs->signal = ah->ah_noise_floor + rs->rs_rssi;
1367 1357
1368 rxs->antenna = rs->rs_antenna; 1358 rxs->antenna = rs->rs_antenna;
1369 1359
1370 if (rs->rs_antenna > 0 && rs->rs_antenna < 5) 1360 if (rs->rs_antenna > 0 && rs->rs_antenna < 5)
1371 sc->stats.antenna_rx[rs->rs_antenna]++; 1361 ah->stats.antenna_rx[rs->rs_antenna]++;
1372 else 1362 else
1373 sc->stats.antenna_rx[0]++; /* invalid */ 1363 ah->stats.antenna_rx[0]++; /* invalid */
1374 1364
1375 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs->rs_rate); 1365 rxs->rate_idx = ath5k_hw_to_driver_rix(ah, rs->rs_rate);
1376 rxs->flag |= ath5k_rx_decrypted(sc, skb, rs); 1366 rxs->flag |= ath5k_rx_decrypted(ah, skb, rs);
1377 1367
1378 if (rxs->rate_idx >= 0 && rs->rs_rate == 1368 if (rxs->rate_idx >= 0 && rs->rs_rate ==
1379 sc->sbands[sc->curchan->band].bitrates[rxs->rate_idx].hw_value_short) 1369 ah->sbands[ah->curchan->band].bitrates[rxs->rate_idx].hw_value_short)
1380 rxs->flag |= RX_FLAG_SHORTPRE; 1370 rxs->flag |= RX_FLAG_SHORTPRE;
1381 1371
1382 trace_ath5k_rx(sc, skb); 1372 trace_ath5k_rx(ah, skb);
1383 1373
1384 ath5k_update_beacon_rssi(sc, skb, rs->rs_rssi); 1374 ath5k_update_beacon_rssi(ah, skb, rs->rs_rssi);
1385 1375
1386 /* check beacons in IBSS mode */ 1376 /* check beacons in IBSS mode */
1387 if (sc->opmode == NL80211_IFTYPE_ADHOC) 1377 if (ah->opmode == NL80211_IFTYPE_ADHOC)
1388 ath5k_check_ibss_tsf(sc, skb, rxs); 1378 ath5k_check_ibss_tsf(ah, skb, rxs);
1389 1379
1390 ieee80211_rx(sc->hw, skb); 1380 ieee80211_rx(ah->hw, skb);
1391} 1381}
1392 1382
1393/** ath5k_frame_receive_ok() - Do we want to receive this frame or not? 1383/** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
@@ -1396,20 +1386,20 @@ ath5k_receive_frame(struct ath5k_softc *sc, struct sk_buff *skb,
1396 * statistics. Return true if we want this frame, false if not. 1386 * statistics. Return true if we want this frame, false if not.
1397 */ 1387 */
1398static bool 1388static bool
1399ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs) 1389ath5k_receive_frame_ok(struct ath5k_hw *ah, struct ath5k_rx_status *rs)
1400{ 1390{
1401 sc->stats.rx_all_count++; 1391 ah->stats.rx_all_count++;
1402 sc->stats.rx_bytes_count += rs->rs_datalen; 1392 ah->stats.rx_bytes_count += rs->rs_datalen;
1403 1393
1404 if (unlikely(rs->rs_status)) { 1394 if (unlikely(rs->rs_status)) {
1405 if (rs->rs_status & AR5K_RXERR_CRC) 1395 if (rs->rs_status & AR5K_RXERR_CRC)
1406 sc->stats.rxerr_crc++; 1396 ah->stats.rxerr_crc++;
1407 if (rs->rs_status & AR5K_RXERR_FIFO) 1397 if (rs->rs_status & AR5K_RXERR_FIFO)
1408 sc->stats.rxerr_fifo++; 1398 ah->stats.rxerr_fifo++;
1409 if (rs->rs_status & AR5K_RXERR_PHY) { 1399 if (rs->rs_status & AR5K_RXERR_PHY) {
1410 sc->stats.rxerr_phy++; 1400 ah->stats.rxerr_phy++;
1411 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32) 1401 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32)
1412 sc->stats.rxerr_phy_code[rs->rs_phyerr]++; 1402 ah->stats.rxerr_phy_code[rs->rs_phyerr]++;
1413 return false; 1403 return false;
1414 } 1404 }
1415 if (rs->rs_status & AR5K_RXERR_DECRYPT) { 1405 if (rs->rs_status & AR5K_RXERR_DECRYPT) {
@@ -1423,13 +1413,13 @@ ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs)
1423 * 1413 *
1424 * XXX do key cache faulting 1414 * XXX do key cache faulting
1425 */ 1415 */
1426 sc->stats.rxerr_decrypt++; 1416 ah->stats.rxerr_decrypt++;
1427 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID && 1417 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID &&
1428 !(rs->rs_status & AR5K_RXERR_CRC)) 1418 !(rs->rs_status & AR5K_RXERR_CRC))
1429 return true; 1419 return true;
1430 } 1420 }
1431 if (rs->rs_status & AR5K_RXERR_MIC) { 1421 if (rs->rs_status & AR5K_RXERR_MIC) {
1432 sc->stats.rxerr_mic++; 1422 ah->stats.rxerr_mic++;
1433 return true; 1423 return true;
1434 } 1424 }
1435 1425
@@ -1439,26 +1429,26 @@ ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs)
1439 } 1429 }
1440 1430
1441 if (unlikely(rs->rs_more)) { 1431 if (unlikely(rs->rs_more)) {
1442 sc->stats.rxerr_jumbo++; 1432 ah->stats.rxerr_jumbo++;
1443 return false; 1433 return false;
1444 } 1434 }
1445 return true; 1435 return true;
1446} 1436}
1447 1437
1448static void 1438static void
1449ath5k_set_current_imask(struct ath5k_softc *sc) 1439ath5k_set_current_imask(struct ath5k_hw *ah)
1450{ 1440{
1451 enum ath5k_int imask; 1441 enum ath5k_int imask;
1452 unsigned long flags; 1442 unsigned long flags;
1453 1443
1454 spin_lock_irqsave(&sc->irqlock, flags); 1444 spin_lock_irqsave(&ah->irqlock, flags);
1455 imask = sc->imask; 1445 imask = ah->imask;
1456 if (sc->rx_pending) 1446 if (ah->rx_pending)
1457 imask &= ~AR5K_INT_RX_ALL; 1447 imask &= ~AR5K_INT_RX_ALL;
1458 if (sc->tx_pending) 1448 if (ah->tx_pending)
1459 imask &= ~AR5K_INT_TX_ALL; 1449 imask &= ~AR5K_INT_TX_ALL;
1460 ath5k_hw_set_imr(sc->ah, imask); 1450 ath5k_hw_set_imr(ah, imask);
1461 spin_unlock_irqrestore(&sc->irqlock, flags); 1451 spin_unlock_irqrestore(&ah->irqlock, flags);
1462} 1452}
1463 1453
1464static void 1454static void
@@ -1467,39 +1457,38 @@ ath5k_tasklet_rx(unsigned long data)
1467 struct ath5k_rx_status rs = {}; 1457 struct ath5k_rx_status rs = {};
1468 struct sk_buff *skb, *next_skb; 1458 struct sk_buff *skb, *next_skb;
1469 dma_addr_t next_skb_addr; 1459 dma_addr_t next_skb_addr;
1470 struct ath5k_softc *sc = (void *)data; 1460 struct ath5k_hw *ah = (void *)data;
1471 struct ath5k_hw *ah = sc->ah;
1472 struct ath_common *common = ath5k_hw_common(ah); 1461 struct ath_common *common = ath5k_hw_common(ah);
1473 struct ath5k_buf *bf; 1462 struct ath5k_buf *bf;
1474 struct ath5k_desc *ds; 1463 struct ath5k_desc *ds;
1475 int ret; 1464 int ret;
1476 1465
1477 spin_lock(&sc->rxbuflock); 1466 spin_lock(&ah->rxbuflock);
1478 if (list_empty(&sc->rxbuf)) { 1467 if (list_empty(&ah->rxbuf)) {
1479 ATH5K_WARN(sc, "empty rx buf pool\n"); 1468 ATH5K_WARN(ah, "empty rx buf pool\n");
1480 goto unlock; 1469 goto unlock;
1481 } 1470 }
1482 do { 1471 do {
1483 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list); 1472 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list);
1484 BUG_ON(bf->skb == NULL); 1473 BUG_ON(bf->skb == NULL);
1485 skb = bf->skb; 1474 skb = bf->skb;
1486 ds = bf->desc; 1475 ds = bf->desc;
1487 1476
1488 /* bail if HW is still using self-linked descriptor */ 1477 /* bail if HW is still using self-linked descriptor */
1489 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr) 1478 if (ath5k_hw_get_rxdp(ah) == bf->daddr)
1490 break; 1479 break;
1491 1480
1492 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs); 1481 ret = ah->ah_proc_rx_desc(ah, ds, &rs);
1493 if (unlikely(ret == -EINPROGRESS)) 1482 if (unlikely(ret == -EINPROGRESS))
1494 break; 1483 break;
1495 else if (unlikely(ret)) { 1484 else if (unlikely(ret)) {
1496 ATH5K_ERR(sc, "error in processing rx descriptor\n"); 1485 ATH5K_ERR(ah, "error in processing rx descriptor\n");
1497 sc->stats.rxerr_proc++; 1486 ah->stats.rxerr_proc++;
1498 break; 1487 break;
1499 } 1488 }
1500 1489
1501 if (ath5k_receive_frame_ok(sc, &rs)) { 1490 if (ath5k_receive_frame_ok(ah, &rs)) {
1502 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr); 1491 next_skb = ath5k_rx_skb_alloc(ah, &next_skb_addr);
1503 1492
1504 /* 1493 /*
1505 * If we can't replace bf->skb with a new skb under 1494 * If we can't replace bf->skb with a new skb under
@@ -1508,24 +1497,24 @@ ath5k_tasklet_rx(unsigned long data)
1508 if (!next_skb) 1497 if (!next_skb)
1509 goto next; 1498 goto next;
1510 1499
1511 dma_unmap_single(sc->dev, bf->skbaddr, 1500 dma_unmap_single(ah->dev, bf->skbaddr,
1512 common->rx_bufsize, 1501 common->rx_bufsize,
1513 DMA_FROM_DEVICE); 1502 DMA_FROM_DEVICE);
1514 1503
1515 skb_put(skb, rs.rs_datalen); 1504 skb_put(skb, rs.rs_datalen);
1516 1505
1517 ath5k_receive_frame(sc, skb, &rs); 1506 ath5k_receive_frame(ah, skb, &rs);
1518 1507
1519 bf->skb = next_skb; 1508 bf->skb = next_skb;
1520 bf->skbaddr = next_skb_addr; 1509 bf->skbaddr = next_skb_addr;
1521 } 1510 }
1522next: 1511next:
1523 list_move_tail(&bf->list, &sc->rxbuf); 1512 list_move_tail(&bf->list, &ah->rxbuf);
1524 } while (ath5k_rxbuf_setup(sc, bf) == 0); 1513 } while (ath5k_rxbuf_setup(ah, bf) == 0);
1525unlock: 1514unlock:
1526 spin_unlock(&sc->rxbuflock); 1515 spin_unlock(&ah->rxbuflock);
1527 sc->rx_pending = false; 1516 ah->rx_pending = false;
1528 ath5k_set_current_imask(sc); 1517 ath5k_set_current_imask(ah);
1529} 1518}
1530 1519
1531 1520
@@ -1537,12 +1526,12 @@ void
1537ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb, 1526ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
1538 struct ath5k_txq *txq) 1527 struct ath5k_txq *txq)
1539{ 1528{
1540 struct ath5k_softc *sc = hw->priv; 1529 struct ath5k_hw *ah = hw->priv;
1541 struct ath5k_buf *bf; 1530 struct ath5k_buf *bf;
1542 unsigned long flags; 1531 unsigned long flags;
1543 int padsize; 1532 int padsize;
1544 1533
1545 trace_ath5k_tx(sc, skb, txq); 1534 trace_ath5k_tx(ah, skb, txq);
1546 1535
1547 /* 1536 /*
1548 * The hardware expects the header padded to 4 byte boundaries. 1537 * The hardware expects the header padded to 4 byte boundaries.
@@ -1550,7 +1539,7 @@ ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
1550 */ 1539 */
1551 padsize = ath5k_add_padding(skb); 1540 padsize = ath5k_add_padding(skb);
1552 if (padsize < 0) { 1541 if (padsize < 0) {
1553 ATH5K_ERR(sc, "tx hdrlen not %%4: not enough" 1542 ATH5K_ERR(ah, "tx hdrlen not %%4: not enough"
1554 " headroom to pad"); 1543 " headroom to pad");
1555 goto drop_packet; 1544 goto drop_packet;
1556 } 1545 }
@@ -1559,28 +1548,28 @@ ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
1559 txq->qnum <= AR5K_TX_QUEUE_ID_DATA_MAX) 1548 txq->qnum <= AR5K_TX_QUEUE_ID_DATA_MAX)
1560 ieee80211_stop_queue(hw, txq->qnum); 1549 ieee80211_stop_queue(hw, txq->qnum);
1561 1550
1562 spin_lock_irqsave(&sc->txbuflock, flags); 1551 spin_lock_irqsave(&ah->txbuflock, flags);
1563 if (list_empty(&sc->txbuf)) { 1552 if (list_empty(&ah->txbuf)) {
1564 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n"); 1553 ATH5K_ERR(ah, "no further txbuf available, dropping packet\n");
1565 spin_unlock_irqrestore(&sc->txbuflock, flags); 1554 spin_unlock_irqrestore(&ah->txbuflock, flags);
1566 ieee80211_stop_queues(hw); 1555 ieee80211_stop_queues(hw);
1567 goto drop_packet; 1556 goto drop_packet;
1568 } 1557 }
1569 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list); 1558 bf = list_first_entry(&ah->txbuf, struct ath5k_buf, list);
1570 list_del(&bf->list); 1559 list_del(&bf->list);
1571 sc->txbuf_len--; 1560 ah->txbuf_len--;
1572 if (list_empty(&sc->txbuf)) 1561 if (list_empty(&ah->txbuf))
1573 ieee80211_stop_queues(hw); 1562 ieee80211_stop_queues(hw);
1574 spin_unlock_irqrestore(&sc->txbuflock, flags); 1563 spin_unlock_irqrestore(&ah->txbuflock, flags);
1575 1564
1576 bf->skb = skb; 1565 bf->skb = skb;
1577 1566
1578 if (ath5k_txbuf_setup(sc, bf, txq, padsize)) { 1567 if (ath5k_txbuf_setup(ah, bf, txq, padsize)) {
1579 bf->skb = NULL; 1568 bf->skb = NULL;
1580 spin_lock_irqsave(&sc->txbuflock, flags); 1569 spin_lock_irqsave(&ah->txbuflock, flags);
1581 list_add_tail(&bf->list, &sc->txbuf); 1570 list_add_tail(&bf->list, &ah->txbuf);
1582 sc->txbuf_len++; 1571 ah->txbuf_len++;
1583 spin_unlock_irqrestore(&sc->txbuflock, flags); 1572 spin_unlock_irqrestore(&ah->txbuflock, flags);
1584 goto drop_packet; 1573 goto drop_packet;
1585 } 1574 }
1586 return; 1575 return;
@@ -1590,15 +1579,15 @@ drop_packet:
1590} 1579}
1591 1580
1592static void 1581static void
1593ath5k_tx_frame_completed(struct ath5k_softc *sc, struct sk_buff *skb, 1582ath5k_tx_frame_completed(struct ath5k_hw *ah, struct sk_buff *skb,
1594 struct ath5k_txq *txq, struct ath5k_tx_status *ts) 1583 struct ath5k_txq *txq, struct ath5k_tx_status *ts)
1595{ 1584{
1596 struct ieee80211_tx_info *info; 1585 struct ieee80211_tx_info *info;
1597 u8 tries[3]; 1586 u8 tries[3];
1598 int i; 1587 int i;
1599 1588
1600 sc->stats.tx_all_count++; 1589 ah->stats.tx_all_count++;
1601 sc->stats.tx_bytes_count += skb->len; 1590 ah->stats.tx_bytes_count += skb->len;
1602 info = IEEE80211_SKB_CB(skb); 1591 info = IEEE80211_SKB_CB(skb);
1603 1592
1604 tries[0] = info->status.rates[0].count; 1593 tries[0] = info->status.rates[0].count;
@@ -1618,15 +1607,15 @@ ath5k_tx_frame_completed(struct ath5k_softc *sc, struct sk_buff *skb,
1618 info->status.rates[ts->ts_final_idx + 1].idx = -1; 1607 info->status.rates[ts->ts_final_idx + 1].idx = -1;
1619 1608
1620 if (unlikely(ts->ts_status)) { 1609 if (unlikely(ts->ts_status)) {
1621 sc->stats.ack_fail++; 1610 ah->stats.ack_fail++;
1622 if (ts->ts_status & AR5K_TXERR_FILT) { 1611 if (ts->ts_status & AR5K_TXERR_FILT) {
1623 info->flags |= IEEE80211_TX_STAT_TX_FILTERED; 1612 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1624 sc->stats.txerr_filt++; 1613 ah->stats.txerr_filt++;
1625 } 1614 }
1626 if (ts->ts_status & AR5K_TXERR_XRETRY) 1615 if (ts->ts_status & AR5K_TXERR_XRETRY)
1627 sc->stats.txerr_retry++; 1616 ah->stats.txerr_retry++;
1628 if (ts->ts_status & AR5K_TXERR_FIFO) 1617 if (ts->ts_status & AR5K_TXERR_FIFO)
1629 sc->stats.txerr_fifo++; 1618 ah->stats.txerr_fifo++;
1630 } else { 1619 } else {
1631 info->flags |= IEEE80211_TX_STAT_ACK; 1620 info->flags |= IEEE80211_TX_STAT_ACK;
1632 info->status.ack_signal = ts->ts_rssi; 1621 info->status.ack_signal = ts->ts_rssi;
@@ -1642,16 +1631,16 @@ ath5k_tx_frame_completed(struct ath5k_softc *sc, struct sk_buff *skb,
1642 ath5k_remove_padding(skb); 1631 ath5k_remove_padding(skb);
1643 1632
1644 if (ts->ts_antenna > 0 && ts->ts_antenna < 5) 1633 if (ts->ts_antenna > 0 && ts->ts_antenna < 5)
1645 sc->stats.antenna_tx[ts->ts_antenna]++; 1634 ah->stats.antenna_tx[ts->ts_antenna]++;
1646 else 1635 else
1647 sc->stats.antenna_tx[0]++; /* invalid */ 1636 ah->stats.antenna_tx[0]++; /* invalid */
1648 1637
1649 trace_ath5k_tx_complete(sc, skb, txq, ts); 1638 trace_ath5k_tx_complete(ah, skb, txq, ts);
1650 ieee80211_tx_status(sc->hw, skb); 1639 ieee80211_tx_status(ah->hw, skb);
1651} 1640}
1652 1641
1653static void 1642static void
1654ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq) 1643ath5k_tx_processq(struct ath5k_hw *ah, struct ath5k_txq *txq)
1655{ 1644{
1656 struct ath5k_tx_status ts = {}; 1645 struct ath5k_tx_status ts = {};
1657 struct ath5k_buf *bf, *bf0; 1646 struct ath5k_buf *bf, *bf0;
@@ -1668,11 +1657,11 @@ ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1668 if (bf->skb != NULL) { 1657 if (bf->skb != NULL) {
1669 ds = bf->desc; 1658 ds = bf->desc;
1670 1659
1671 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts); 1660 ret = ah->ah_proc_tx_desc(ah, ds, &ts);
1672 if (unlikely(ret == -EINPROGRESS)) 1661 if (unlikely(ret == -EINPROGRESS))
1673 break; 1662 break;
1674 else if (unlikely(ret)) { 1663 else if (unlikely(ret)) {
1675 ATH5K_ERR(sc, 1664 ATH5K_ERR(ah,
1676 "error %d while processing " 1665 "error %d while processing "
1677 "queue %u\n", ret, txq->qnum); 1666 "queue %u\n", ret, txq->qnum);
1678 break; 1667 break;
@@ -1681,9 +1670,9 @@ ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1681 skb = bf->skb; 1670 skb = bf->skb;
1682 bf->skb = NULL; 1671 bf->skb = NULL;
1683 1672
1684 dma_unmap_single(sc->dev, bf->skbaddr, skb->len, 1673 dma_unmap_single(ah->dev, bf->skbaddr, skb->len,
1685 DMA_TO_DEVICE); 1674 DMA_TO_DEVICE);
1686 ath5k_tx_frame_completed(sc, skb, txq, &ts); 1675 ath5k_tx_frame_completed(ah, skb, txq, &ts);
1687 } 1676 }
1688 1677
1689 /* 1678 /*
@@ -1692,31 +1681,31 @@ ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1692 * host memory and moved on. 1681 * host memory and moved on.
1693 * Always keep the last descriptor to avoid HW races... 1682 * Always keep the last descriptor to avoid HW races...
1694 */ 1683 */
1695 if (ath5k_hw_get_txdp(sc->ah, txq->qnum) != bf->daddr) { 1684 if (ath5k_hw_get_txdp(ah, txq->qnum) != bf->daddr) {
1696 spin_lock(&sc->txbuflock); 1685 spin_lock(&ah->txbuflock);
1697 list_move_tail(&bf->list, &sc->txbuf); 1686 list_move_tail(&bf->list, &ah->txbuf);
1698 sc->txbuf_len++; 1687 ah->txbuf_len++;
1699 txq->txq_len--; 1688 txq->txq_len--;
1700 spin_unlock(&sc->txbuflock); 1689 spin_unlock(&ah->txbuflock);
1701 } 1690 }
1702 } 1691 }
1703 spin_unlock(&txq->lock); 1692 spin_unlock(&txq->lock);
1704 if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4) 1693 if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4)
1705 ieee80211_wake_queue(sc->hw, txq->qnum); 1694 ieee80211_wake_queue(ah->hw, txq->qnum);
1706} 1695}
1707 1696
1708static void 1697static void
1709ath5k_tasklet_tx(unsigned long data) 1698ath5k_tasklet_tx(unsigned long data)
1710{ 1699{
1711 int i; 1700 int i;
1712 struct ath5k_softc *sc = (void *)data; 1701 struct ath5k_hw *ah = (void *)data;
1713 1702
1714 for (i = 0; i < AR5K_NUM_TX_QUEUES; i++) 1703 for (i = 0; i < AR5K_NUM_TX_QUEUES; i++)
1715 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i))) 1704 if (ah->txqs[i].setup && (ah->ah_txq_isr & BIT(i)))
1716 ath5k_tx_processq(sc, &sc->txqs[i]); 1705 ath5k_tx_processq(ah, &ah->txqs[i]);
1717 1706
1718 sc->tx_pending = false; 1707 ah->tx_pending = false;
1719 ath5k_set_current_imask(sc); 1708 ath5k_set_current_imask(ah);
1720} 1709}
1721 1710
1722 1711
@@ -1728,25 +1717,24 @@ ath5k_tasklet_tx(unsigned long data)
1728 * Setup the beacon frame for transmit. 1717 * Setup the beacon frame for transmit.
1729 */ 1718 */
1730static int 1719static int
1731ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf) 1720ath5k_beacon_setup(struct ath5k_hw *ah, struct ath5k_buf *bf)
1732{ 1721{
1733 struct sk_buff *skb = bf->skb; 1722 struct sk_buff *skb = bf->skb;
1734 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1723 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1735 struct ath5k_hw *ah = sc->ah;
1736 struct ath5k_desc *ds; 1724 struct ath5k_desc *ds;
1737 int ret = 0; 1725 int ret = 0;
1738 u8 antenna; 1726 u8 antenna;
1739 u32 flags; 1727 u32 flags;
1740 const int padsize = 0; 1728 const int padsize = 0;
1741 1729
1742 bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len, 1730 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len,
1743 DMA_TO_DEVICE); 1731 DMA_TO_DEVICE);
1744 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] " 1732 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1745 "skbaddr %llx\n", skb, skb->data, skb->len, 1733 "skbaddr %llx\n", skb, skb->data, skb->len,
1746 (unsigned long long)bf->skbaddr); 1734 (unsigned long long)bf->skbaddr);
1747 1735
1748 if (dma_mapping_error(sc->dev, bf->skbaddr)) { 1736 if (dma_mapping_error(ah->dev, bf->skbaddr)) {
1749 ATH5K_ERR(sc, "beacon DMA mapping failed\n"); 1737 ATH5K_ERR(ah, "beacon DMA mapping failed\n");
1750 return -EIO; 1738 return -EIO;
1751 } 1739 }
1752 1740
@@ -1754,7 +1742,7 @@ ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1754 antenna = ah->ah_tx_ant; 1742 antenna = ah->ah_tx_ant;
1755 1743
1756 flags = AR5K_TXDESC_NOACK; 1744 flags = AR5K_TXDESC_NOACK;
1757 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) { 1745 if (ah->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
1758 ds->ds_link = bf->daddr; /* self-linked */ 1746 ds->ds_link = bf->daddr; /* self-linked */
1759 flags |= AR5K_TXDESC_VEOL; 1747 flags |= AR5K_TXDESC_VEOL;
1760 } else 1748 } else
@@ -1779,7 +1767,7 @@ ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1779 * on all of them. 1767 * on all of them.
1780 */ 1768 */
1781 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP) 1769 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
1782 antenna = sc->bsent & 4 ? 2 : 1; 1770 antenna = ah->bsent & 4 ? 2 : 1;
1783 1771
1784 1772
1785 /* FIXME: If we are in g mode and rate is a CCK rate 1773 /* FIXME: If we are in g mode and rate is a CCK rate
@@ -1788,8 +1776,8 @@ ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1788 ds->ds_data = bf->skbaddr; 1776 ds->ds_data = bf->skbaddr;
1789 ret = ah->ah_setup_tx_desc(ah, ds, skb->len, 1777 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
1790 ieee80211_get_hdrlen_from_skb(skb), padsize, 1778 ieee80211_get_hdrlen_from_skb(skb), padsize,
1791 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2), 1779 AR5K_PKT_TYPE_BEACON, (ah->power_level * 2),
1792 ieee80211_get_tx_rate(sc->hw, info)->hw_value, 1780 ieee80211_get_tx_rate(ah->hw, info)->hw_value,
1793 1, AR5K_TXKEYIX_INVALID, 1781 1, AR5K_TXKEYIX_INVALID,
1794 antenna, flags, 0, 0); 1782 antenna, flags, 0, 0);
1795 if (ret) 1783 if (ret)
@@ -1797,7 +1785,7 @@ ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1797 1785
1798 return 0; 1786 return 0;
1799err_unmap: 1787err_unmap:
1800 dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE); 1788 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
1801 return ret; 1789 return ret;
1802} 1790}
1803 1791
@@ -1812,7 +1800,7 @@ int
1812ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1800ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1813{ 1801{
1814 int ret; 1802 int ret;
1815 struct ath5k_softc *sc = hw->priv; 1803 struct ath5k_hw *ah = hw->priv;
1816 struct ath5k_vif *avf = (void *)vif->drv_priv; 1804 struct ath5k_vif *avf = (void *)vif->drv_priv;
1817 struct sk_buff *skb; 1805 struct sk_buff *skb;
1818 1806
@@ -1828,9 +1816,9 @@ ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1828 goto out; 1816 goto out;
1829 } 1817 }
1830 1818
1831 ath5k_txbuf_free_skb(sc, avf->bbuf); 1819 ath5k_txbuf_free_skb(ah, avf->bbuf);
1832 avf->bbuf->skb = skb; 1820 avf->bbuf->skb = skb;
1833 ret = ath5k_beacon_setup(sc, avf->bbuf); 1821 ret = ath5k_beacon_setup(ah, avf->bbuf);
1834 if (ret) 1822 if (ret)
1835 avf->bbuf->skb = NULL; 1823 avf->bbuf->skb = NULL;
1836out: 1824out:
@@ -1846,15 +1834,14 @@ out:
1846 * or user context from ath5k_beacon_config. 1834 * or user context from ath5k_beacon_config.
1847 */ 1835 */
1848static void 1836static void
1849ath5k_beacon_send(struct ath5k_softc *sc) 1837ath5k_beacon_send(struct ath5k_hw *ah)
1850{ 1838{
1851 struct ath5k_hw *ah = sc->ah;
1852 struct ieee80211_vif *vif; 1839 struct ieee80211_vif *vif;
1853 struct ath5k_vif *avf; 1840 struct ath5k_vif *avf;
1854 struct ath5k_buf *bf; 1841 struct ath5k_buf *bf;
1855 struct sk_buff *skb; 1842 struct sk_buff *skb;
1856 1843
1857 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n"); 1844 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "in beacon_send\n");
1858 1845
1859 /* 1846 /*
1860 * Check if the previous beacon has gone out. If 1847 * Check if the previous beacon has gone out. If
@@ -1863,47 +1850,47 @@ ath5k_beacon_send(struct ath5k_softc *sc)
1863 * indicate a problem and should not occur. If we 1850 * indicate a problem and should not occur. If we
1864 * miss too many consecutive beacons reset the device. 1851 * miss too many consecutive beacons reset the device.
1865 */ 1852 */
1866 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) { 1853 if (unlikely(ath5k_hw_num_tx_pending(ah, ah->bhalq) != 0)) {
1867 sc->bmisscount++; 1854 ah->bmisscount++;
1868 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 1855 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1869 "missed %u consecutive beacons\n", sc->bmisscount); 1856 "missed %u consecutive beacons\n", ah->bmisscount);
1870 if (sc->bmisscount > 10) { /* NB: 10 is a guess */ 1857 if (ah->bmisscount > 10) { /* NB: 10 is a guess */
1871 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 1858 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1872 "stuck beacon time (%u missed)\n", 1859 "stuck beacon time (%u missed)\n",
1873 sc->bmisscount); 1860 ah->bmisscount);
1874 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, 1861 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
1875 "stuck beacon, resetting\n"); 1862 "stuck beacon, resetting\n");
1876 ieee80211_queue_work(sc->hw, &sc->reset_work); 1863 ieee80211_queue_work(ah->hw, &ah->reset_work);
1877 } 1864 }
1878 return; 1865 return;
1879 } 1866 }
1880 if (unlikely(sc->bmisscount != 0)) { 1867 if (unlikely(ah->bmisscount != 0)) {
1881 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 1868 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1882 "resume beacon xmit after %u misses\n", 1869 "resume beacon xmit after %u misses\n",
1883 sc->bmisscount); 1870 ah->bmisscount);
1884 sc->bmisscount = 0; 1871 ah->bmisscount = 0;
1885 } 1872 }
1886 1873
1887 if ((sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) || 1874 if ((ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs > 1) ||
1888 sc->opmode == NL80211_IFTYPE_MESH_POINT) { 1875 ah->opmode == NL80211_IFTYPE_MESH_POINT) {
1889 u64 tsf = ath5k_hw_get_tsf64(ah); 1876 u64 tsf = ath5k_hw_get_tsf64(ah);
1890 u32 tsftu = TSF_TO_TU(tsf); 1877 u32 tsftu = TSF_TO_TU(tsf);
1891 int slot = ((tsftu % sc->bintval) * ATH_BCBUF) / sc->bintval; 1878 int slot = ((tsftu % ah->bintval) * ATH_BCBUF) / ah->bintval;
1892 vif = sc->bslot[(slot + 1) % ATH_BCBUF]; 1879 vif = ah->bslot[(slot + 1) % ATH_BCBUF];
1893 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 1880 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1894 "tsf %llx tsftu %x intval %u slot %u vif %p\n", 1881 "tsf %llx tsftu %x intval %u slot %u vif %p\n",
1895 (unsigned long long)tsf, tsftu, sc->bintval, slot, vif); 1882 (unsigned long long)tsf, tsftu, ah->bintval, slot, vif);
1896 } else /* only one interface */ 1883 } else /* only one interface */
1897 vif = sc->bslot[0]; 1884 vif = ah->bslot[0];
1898 1885
1899 if (!vif) 1886 if (!vif)
1900 return; 1887 return;
1901 1888
1902 avf = (void *)vif->drv_priv; 1889 avf = (void *)vif->drv_priv;
1903 bf = avf->bbuf; 1890 bf = avf->bbuf;
1904 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION || 1891 if (unlikely(bf->skb == NULL || ah->opmode == NL80211_IFTYPE_STATION ||
1905 sc->opmode == NL80211_IFTYPE_MONITOR)) { 1892 ah->opmode == NL80211_IFTYPE_MONITOR)) {
1906 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL); 1893 ATH5K_WARN(ah, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1907 return; 1894 return;
1908 } 1895 }
1909 1896
@@ -1912,40 +1899,40 @@ ath5k_beacon_send(struct ath5k_softc *sc)
1912 * This should never fail since we check above that no frames 1899 * This should never fail since we check above that no frames
1913 * are still pending on the queue. 1900 * are still pending on the queue.
1914 */ 1901 */
1915 if (unlikely(ath5k_hw_stop_beacon_queue(ah, sc->bhalq))) { 1902 if (unlikely(ath5k_hw_stop_beacon_queue(ah, ah->bhalq))) {
1916 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq); 1903 ATH5K_WARN(ah, "beacon queue %u didn't start/stop ?\n", ah->bhalq);
1917 /* NB: hw still stops DMA, so proceed */ 1904 /* NB: hw still stops DMA, so proceed */
1918 } 1905 }
1919 1906
1920 /* refresh the beacon for AP or MESH mode */ 1907 /* refresh the beacon for AP or MESH mode */
1921 if (sc->opmode == NL80211_IFTYPE_AP || 1908 if (ah->opmode == NL80211_IFTYPE_AP ||
1922 sc->opmode == NL80211_IFTYPE_MESH_POINT) 1909 ah->opmode == NL80211_IFTYPE_MESH_POINT)
1923 ath5k_beacon_update(sc->hw, vif); 1910 ath5k_beacon_update(ah->hw, vif);
1924 1911
1925 trace_ath5k_tx(sc, bf->skb, &sc->txqs[sc->bhalq]); 1912 trace_ath5k_tx(ah, bf->skb, &ah->txqs[ah->bhalq]);
1926 1913
1927 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr); 1914 ath5k_hw_set_txdp(ah, ah->bhalq, bf->daddr);
1928 ath5k_hw_start_tx_dma(ah, sc->bhalq); 1915 ath5k_hw_start_tx_dma(ah, ah->bhalq);
1929 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n", 1916 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
1930 sc->bhalq, (unsigned long long)bf->daddr, bf->desc); 1917 ah->bhalq, (unsigned long long)bf->daddr, bf->desc);
1931 1918
1932 skb = ieee80211_get_buffered_bc(sc->hw, vif); 1919 skb = ieee80211_get_buffered_bc(ah->hw, vif);
1933 while (skb) { 1920 while (skb) {
1934 ath5k_tx_queue(sc->hw, skb, sc->cabq); 1921 ath5k_tx_queue(ah->hw, skb, ah->cabq);
1935 1922
1936 if (sc->cabq->txq_len >= sc->cabq->txq_max) 1923 if (ah->cabq->txq_len >= ah->cabq->txq_max)
1937 break; 1924 break;
1938 1925
1939 skb = ieee80211_get_buffered_bc(sc->hw, vif); 1926 skb = ieee80211_get_buffered_bc(ah->hw, vif);
1940 } 1927 }
1941 1928
1942 sc->bsent++; 1929 ah->bsent++;
1943} 1930}
1944 1931
1945/** 1932/**
1946 * ath5k_beacon_update_timers - update beacon timers 1933 * ath5k_beacon_update_timers - update beacon timers
1947 * 1934 *
1948 * @sc: struct ath5k_softc pointer we are operating on 1935 * @ah: struct ath5k_hw pointer we are operating on
1949 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a 1936 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
1950 * beacon timer update based on the current HW TSF. 1937 * beacon timer update based on the current HW TSF.
1951 * 1938 *
@@ -1959,17 +1946,16 @@ ath5k_beacon_send(struct ath5k_softc *sc)
1959 * function to have it all together in one place. 1946 * function to have it all together in one place.
1960 */ 1947 */
1961void 1948void
1962ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf) 1949ath5k_beacon_update_timers(struct ath5k_hw *ah, u64 bc_tsf)
1963{ 1950{
1964 struct ath5k_hw *ah = sc->ah;
1965 u32 nexttbtt, intval, hw_tu, bc_tu; 1951 u32 nexttbtt, intval, hw_tu, bc_tu;
1966 u64 hw_tsf; 1952 u64 hw_tsf;
1967 1953
1968 intval = sc->bintval & AR5K_BEACON_PERIOD; 1954 intval = ah->bintval & AR5K_BEACON_PERIOD;
1969 if (sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) { 1955 if (ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs > 1) {
1970 intval /= ATH_BCBUF; /* staggered multi-bss beacons */ 1956 intval /= ATH_BCBUF; /* staggered multi-bss beacons */
1971 if (intval < 15) 1957 if (intval < 15)
1972 ATH5K_WARN(sc, "intval %u is too low, min 15\n", 1958 ATH5K_WARN(ah, "intval %u is too low, min 15\n",
1973 intval); 1959 intval);
1974 } 1960 }
1975 if (WARN_ON(!intval)) 1961 if (WARN_ON(!intval))
@@ -2008,7 +1994,7 @@ ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2008 * automatically update the TSF and then we need to reconfigure 1994 * automatically update the TSF and then we need to reconfigure
2009 * the timers. 1995 * the timers.
2010 */ 1996 */
2011 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 1997 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2012 "need to wait for HW TSF sync\n"); 1998 "need to wait for HW TSF sync\n");
2013 return; 1999 return;
2014 } else { 2000 } else {
@@ -2023,7 +2009,7 @@ ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2023 } 2009 }
2024#undef FUDGE 2010#undef FUDGE
2025 2011
2026 sc->nexttbtt = nexttbtt; 2012 ah->nexttbtt = nexttbtt;
2027 2013
2028 intval |= AR5K_BEACON_ENA; 2014 intval |= AR5K_BEACON_ENA;
2029 ath5k_hw_init_beacon(ah, nexttbtt, intval); 2015 ath5k_hw_init_beacon(ah, nexttbtt, intval);
@@ -2033,20 +2019,20 @@ ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2033 * of this function 2019 * of this function
2034 */ 2020 */
2035 if (bc_tsf == -1) 2021 if (bc_tsf == -1)
2036 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2022 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2037 "reconfigured timers based on HW TSF\n"); 2023 "reconfigured timers based on HW TSF\n");
2038 else if (bc_tsf == 0) 2024 else if (bc_tsf == 0)
2039 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2025 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2040 "reset HW TSF and timers\n"); 2026 "reset HW TSF and timers\n");
2041 else 2027 else
2042 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2028 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2043 "updated timers based on beacon TSF\n"); 2029 "updated timers based on beacon TSF\n");
2044 2030
2045 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2031 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2046 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n", 2032 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2047 (unsigned long long) bc_tsf, 2033 (unsigned long long) bc_tsf,
2048 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt); 2034 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2049 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n", 2035 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2050 intval & AR5K_BEACON_PERIOD, 2036 intval & AR5K_BEACON_PERIOD,
2051 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "", 2037 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2052 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : ""); 2038 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
@@ -2055,22 +2041,21 @@ ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2055/** 2041/**
2056 * ath5k_beacon_config - Configure the beacon queues and interrupts 2042 * ath5k_beacon_config - Configure the beacon queues and interrupts
2057 * 2043 *
2058 * @sc: struct ath5k_softc pointer we are operating on 2044 * @ah: struct ath5k_hw pointer we are operating on
2059 * 2045 *
2060 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA 2046 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2061 * interrupts to detect TSF updates only. 2047 * interrupts to detect TSF updates only.
2062 */ 2048 */
2063void 2049void
2064ath5k_beacon_config(struct ath5k_softc *sc) 2050ath5k_beacon_config(struct ath5k_hw *ah)
2065{ 2051{
2066 struct ath5k_hw *ah = sc->ah;
2067 unsigned long flags; 2052 unsigned long flags;
2068 2053
2069 spin_lock_irqsave(&sc->block, flags); 2054 spin_lock_irqsave(&ah->block, flags);
2070 sc->bmisscount = 0; 2055 ah->bmisscount = 0;
2071 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA); 2056 ah->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2072 2057
2073 if (sc->enable_beacon) { 2058 if (ah->enable_beacon) {
2074 /* 2059 /*
2075 * In IBSS mode we use a self-linked tx descriptor and let the 2060 * In IBSS mode we use a self-linked tx descriptor and let the
2076 * hardware send the beacons automatically. We have to load it 2061 * hardware send the beacons automatically. We have to load it
@@ -2078,27 +2063,27 @@ ath5k_beacon_config(struct ath5k_softc *sc)
2078 * We use the SWBA interrupt only to keep track of the beacon 2063 * We use the SWBA interrupt only to keep track of the beacon
2079 * timers in order to detect automatic TSF updates. 2064 * timers in order to detect automatic TSF updates.
2080 */ 2065 */
2081 ath5k_beaconq_config(sc); 2066 ath5k_beaconq_config(ah);
2082 2067
2083 sc->imask |= AR5K_INT_SWBA; 2068 ah->imask |= AR5K_INT_SWBA;
2084 2069
2085 if (sc->opmode == NL80211_IFTYPE_ADHOC) { 2070 if (ah->opmode == NL80211_IFTYPE_ADHOC) {
2086 if (ath5k_hw_hasveol(ah)) 2071 if (ath5k_hw_hasveol(ah))
2087 ath5k_beacon_send(sc); 2072 ath5k_beacon_send(ah);
2088 } else 2073 } else
2089 ath5k_beacon_update_timers(sc, -1); 2074 ath5k_beacon_update_timers(ah, -1);
2090 } else { 2075 } else {
2091 ath5k_hw_stop_beacon_queue(sc->ah, sc->bhalq); 2076 ath5k_hw_stop_beacon_queue(ah, ah->bhalq);
2092 } 2077 }
2093 2078
2094 ath5k_hw_set_imr(ah, sc->imask); 2079 ath5k_hw_set_imr(ah, ah->imask);
2095 mmiowb(); 2080 mmiowb();
2096 spin_unlock_irqrestore(&sc->block, flags); 2081 spin_unlock_irqrestore(&ah->block, flags);
2097} 2082}
2098 2083
2099static void ath5k_tasklet_beacon(unsigned long data) 2084static void ath5k_tasklet_beacon(unsigned long data)
2100{ 2085{
2101 struct ath5k_softc *sc = (struct ath5k_softc *) data; 2086 struct ath5k_hw *ah = (struct ath5k_hw *) data;
2102 2087
2103 /* 2088 /*
2104 * Software beacon alert--time to send a beacon. 2089 * Software beacon alert--time to send a beacon.
@@ -2108,20 +2093,20 @@ static void ath5k_tasklet_beacon(unsigned long data)
2108 * transmission time) in order to detect whether 2093 * transmission time) in order to detect whether
2109 * automatic TSF updates happened. 2094 * automatic TSF updates happened.
2110 */ 2095 */
2111 if (sc->opmode == NL80211_IFTYPE_ADHOC) { 2096 if (ah->opmode == NL80211_IFTYPE_ADHOC) {
2112 /* XXX: only if VEOL supported */ 2097 /* XXX: only if VEOL supported */
2113 u64 tsf = ath5k_hw_get_tsf64(sc->ah); 2098 u64 tsf = ath5k_hw_get_tsf64(ah);
2114 sc->nexttbtt += sc->bintval; 2099 ah->nexttbtt += ah->bintval;
2115 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 2100 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
2116 "SWBA nexttbtt: %x hw_tu: %x " 2101 "SWBA nexttbtt: %x hw_tu: %x "
2117 "TSF: %llx\n", 2102 "TSF: %llx\n",
2118 sc->nexttbtt, 2103 ah->nexttbtt,
2119 TSF_TO_TU(tsf), 2104 TSF_TO_TU(tsf),
2120 (unsigned long long) tsf); 2105 (unsigned long long) tsf);
2121 } else { 2106 } else {
2122 spin_lock(&sc->block); 2107 spin_lock(&ah->block);
2123 ath5k_beacon_send(sc); 2108 ath5k_beacon_send(ah);
2124 spin_unlock(&sc->block); 2109 spin_unlock(&ah->block);
2125 } 2110 }
2126} 2111}
2127 2112
@@ -2138,12 +2123,12 @@ ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2138 /* run ANI only when full calibration is not active */ 2123 /* run ANI only when full calibration is not active */
2139 ah->ah_cal_next_ani = jiffies + 2124 ah->ah_cal_next_ani = jiffies +
2140 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI); 2125 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2141 tasklet_schedule(&ah->ah_sc->ani_tasklet); 2126 tasklet_schedule(&ah->ani_tasklet);
2142 2127
2143 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) { 2128 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
2144 ah->ah_cal_next_full = jiffies + 2129 ah->ah_cal_next_full = jiffies +
2145 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL); 2130 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2146 tasklet_schedule(&ah->ah_sc->calib); 2131 tasklet_schedule(&ah->calib);
2147 } 2132 }
2148 /* we could use SWI to generate enough interrupts to meet our 2133 /* we could use SWI to generate enough interrupts to meet our
2149 * calibration interval requirements, if necessary: 2134 * calibration interval requirements, if necessary:
@@ -2151,44 +2136,43 @@ ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2151} 2136}
2152 2137
2153static void 2138static void
2154ath5k_schedule_rx(struct ath5k_softc *sc) 2139ath5k_schedule_rx(struct ath5k_hw *ah)
2155{ 2140{
2156 sc->rx_pending = true; 2141 ah->rx_pending = true;
2157 tasklet_schedule(&sc->rxtq); 2142 tasklet_schedule(&ah->rxtq);
2158} 2143}
2159 2144
2160static void 2145static void
2161ath5k_schedule_tx(struct ath5k_softc *sc) 2146ath5k_schedule_tx(struct ath5k_hw *ah)
2162{ 2147{
2163 sc->tx_pending = true; 2148 ah->tx_pending = true;
2164 tasklet_schedule(&sc->txtq); 2149 tasklet_schedule(&ah->txtq);
2165} 2150}
2166 2151
2167static irqreturn_t 2152static irqreturn_t
2168ath5k_intr(int irq, void *dev_id) 2153ath5k_intr(int irq, void *dev_id)
2169{ 2154{
2170 struct ath5k_softc *sc = dev_id; 2155 struct ath5k_hw *ah = dev_id;
2171 struct ath5k_hw *ah = sc->ah;
2172 enum ath5k_int status; 2156 enum ath5k_int status;
2173 unsigned int counter = 1000; 2157 unsigned int counter = 1000;
2174 2158
2175 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) || 2159 if (unlikely(test_bit(ATH_STAT_INVALID, ah->status) ||
2176 ((ath5k_get_bus_type(ah) != ATH_AHB) && 2160 ((ath5k_get_bus_type(ah) != ATH_AHB) &&
2177 !ath5k_hw_is_intr_pending(ah)))) 2161 !ath5k_hw_is_intr_pending(ah))))
2178 return IRQ_NONE; 2162 return IRQ_NONE;
2179 2163
2180 do { 2164 do {
2181 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */ 2165 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2182 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n", 2166 ATH5K_DBG(ah, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2183 status, sc->imask); 2167 status, ah->imask);
2184 if (unlikely(status & AR5K_INT_FATAL)) { 2168 if (unlikely(status & AR5K_INT_FATAL)) {
2185 /* 2169 /*
2186 * Fatal errors are unrecoverable. 2170 * Fatal errors are unrecoverable.
2187 * Typically these are caused by DMA errors. 2171 * Typically these are caused by DMA errors.
2188 */ 2172 */
2189 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, 2173 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2190 "fatal int, resetting\n"); 2174 "fatal int, resetting\n");
2191 ieee80211_queue_work(sc->hw, &sc->reset_work); 2175 ieee80211_queue_work(ah->hw, &ah->reset_work);
2192 } else if (unlikely(status & AR5K_INT_RXORN)) { 2176 } else if (unlikely(status & AR5K_INT_RXORN)) {
2193 /* 2177 /*
2194 * Receive buffers are full. Either the bus is busy or 2178 * Receive buffers are full. Either the bus is busy or
@@ -2199,16 +2183,16 @@ ath5k_intr(int irq, void *dev_id)
2199 * We don't know exactly which versions need a reset - 2183 * We don't know exactly which versions need a reset -
2200 * this guess is copied from the HAL. 2184 * this guess is copied from the HAL.
2201 */ 2185 */
2202 sc->stats.rxorn_intr++; 2186 ah->stats.rxorn_intr++;
2203 if (ah->ah_mac_srev < AR5K_SREV_AR5212) { 2187 if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
2204 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, 2188 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2205 "rx overrun, resetting\n"); 2189 "rx overrun, resetting\n");
2206 ieee80211_queue_work(sc->hw, &sc->reset_work); 2190 ieee80211_queue_work(ah->hw, &ah->reset_work);
2207 } else 2191 } else
2208 ath5k_schedule_rx(sc); 2192 ath5k_schedule_rx(ah);
2209 } else { 2193 } else {
2210 if (status & AR5K_INT_SWBA) 2194 if (status & AR5K_INT_SWBA)
2211 tasklet_hi_schedule(&sc->beacontq); 2195 tasklet_hi_schedule(&ah->beacontq);
2212 2196
2213 if (status & AR5K_INT_RXEOL) { 2197 if (status & AR5K_INT_RXEOL) {
2214 /* 2198 /*
@@ -2216,27 +2200,27 @@ ath5k_intr(int irq, void *dev_id)
2216 * RXE bit is written, but it doesn't work at 2200 * RXE bit is written, but it doesn't work at
2217 * least on older hardware revs. 2201 * least on older hardware revs.
2218 */ 2202 */
2219 sc->stats.rxeol_intr++; 2203 ah->stats.rxeol_intr++;
2220 } 2204 }
2221 if (status & AR5K_INT_TXURN) { 2205 if (status & AR5K_INT_TXURN) {
2222 /* bump tx trigger level */ 2206 /* bump tx trigger level */
2223 ath5k_hw_update_tx_triglevel(ah, true); 2207 ath5k_hw_update_tx_triglevel(ah, true);
2224 } 2208 }
2225 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR)) 2209 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2226 ath5k_schedule_rx(sc); 2210 ath5k_schedule_rx(ah);
2227 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC 2211 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2228 | AR5K_INT_TXERR | AR5K_INT_TXEOL)) 2212 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
2229 ath5k_schedule_tx(sc); 2213 ath5k_schedule_tx(ah);
2230 if (status & AR5K_INT_BMISS) { 2214 if (status & AR5K_INT_BMISS) {
2231 /* TODO */ 2215 /* TODO */
2232 } 2216 }
2233 if (status & AR5K_INT_MIB) { 2217 if (status & AR5K_INT_MIB) {
2234 sc->stats.mib_intr++; 2218 ah->stats.mib_intr++;
2235 ath5k_hw_update_mib_counters(ah); 2219 ath5k_hw_update_mib_counters(ah);
2236 ath5k_ani_mib_intr(ah); 2220 ath5k_ani_mib_intr(ah);
2237 } 2221 }
2238 if (status & AR5K_INT_GPIO) 2222 if (status & AR5K_INT_GPIO)
2239 tasklet_schedule(&sc->rf_kill.toggleq); 2223 tasklet_schedule(&ah->rf_kill.toggleq);
2240 2224
2241 } 2225 }
2242 2226
@@ -2245,11 +2229,11 @@ ath5k_intr(int irq, void *dev_id)
2245 2229
2246 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0); 2230 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
2247 2231
2248 if (sc->rx_pending || sc->tx_pending) 2232 if (ah->rx_pending || ah->tx_pending)
2249 ath5k_set_current_imask(sc); 2233 ath5k_set_current_imask(ah);
2250 2234
2251 if (unlikely(!counter)) 2235 if (unlikely(!counter))
2252 ATH5K_WARN(sc, "too many interrupts, giving up for now\n"); 2236 ATH5K_WARN(ah, "too many interrupts, giving up for now\n");
2253 2237
2254 ath5k_intr_calibration_poll(ah); 2238 ath5k_intr_calibration_poll(ah);
2255 2239
@@ -2263,28 +2247,27 @@ ath5k_intr(int irq, void *dev_id)
2263static void 2247static void
2264ath5k_tasklet_calibrate(unsigned long data) 2248ath5k_tasklet_calibrate(unsigned long data)
2265{ 2249{
2266 struct ath5k_softc *sc = (void *)data; 2250 struct ath5k_hw *ah = (void *)data;
2267 struct ath5k_hw *ah = sc->ah;
2268 2251
2269 /* Only full calibration for now */ 2252 /* Only full calibration for now */
2270 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL; 2253 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
2271 2254
2272 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n", 2255 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2273 ieee80211_frequency_to_channel(sc->curchan->center_freq), 2256 ieee80211_frequency_to_channel(ah->curchan->center_freq),
2274 sc->curchan->hw_value); 2257 ah->curchan->hw_value);
2275 2258
2276 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) { 2259 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2277 /* 2260 /*
2278 * Rfgain is out of bounds, reset the chip 2261 * Rfgain is out of bounds, reset the chip
2279 * to load new gain values. 2262 * to load new gain values.
2280 */ 2263 */
2281 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n"); 2264 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2282 ieee80211_queue_work(sc->hw, &sc->reset_work); 2265 ieee80211_queue_work(ah->hw, &ah->reset_work);
2283 } 2266 }
2284 if (ath5k_hw_phy_calibrate(ah, sc->curchan)) 2267 if (ath5k_hw_phy_calibrate(ah, ah->curchan))
2285 ATH5K_ERR(sc, "calibration of channel %u failed\n", 2268 ATH5K_ERR(ah, "calibration of channel %u failed\n",
2286 ieee80211_frequency_to_channel( 2269 ieee80211_frequency_to_channel(
2287 sc->curchan->center_freq)); 2270 ah->curchan->center_freq));
2288 2271
2289 /* Noise floor calibration interrupts rx/tx path while I/Q calibration 2272 /* Noise floor calibration interrupts rx/tx path while I/Q calibration
2290 * doesn't. 2273 * doesn't.
@@ -2303,8 +2286,7 @@ ath5k_tasklet_calibrate(unsigned long data)
2303static void 2286static void
2304ath5k_tasklet_ani(unsigned long data) 2287ath5k_tasklet_ani(unsigned long data)
2305{ 2288{
2306 struct ath5k_softc *sc = (void *)data; 2289 struct ath5k_hw *ah = (void *)data;
2307 struct ath5k_hw *ah = sc->ah;
2308 2290
2309 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI; 2291 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2310 ath5k_ani_calibration(ah); 2292 ath5k_ani_calibration(ah);
@@ -2315,21 +2297,21 @@ ath5k_tasklet_ani(unsigned long data)
2315static void 2297static void
2316ath5k_tx_complete_poll_work(struct work_struct *work) 2298ath5k_tx_complete_poll_work(struct work_struct *work)
2317{ 2299{
2318 struct ath5k_softc *sc = container_of(work, struct ath5k_softc, 2300 struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
2319 tx_complete_work.work); 2301 tx_complete_work.work);
2320 struct ath5k_txq *txq; 2302 struct ath5k_txq *txq;
2321 int i; 2303 int i;
2322 bool needreset = false; 2304 bool needreset = false;
2323 2305
2324 mutex_lock(&sc->lock); 2306 mutex_lock(&ah->lock);
2325 2307
2326 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) { 2308 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) {
2327 if (sc->txqs[i].setup) { 2309 if (ah->txqs[i].setup) {
2328 txq = &sc->txqs[i]; 2310 txq = &ah->txqs[i];
2329 spin_lock_bh(&txq->lock); 2311 spin_lock_bh(&txq->lock);
2330 if (txq->txq_len > 1) { 2312 if (txq->txq_len > 1) {
2331 if (txq->txq_poll_mark) { 2313 if (txq->txq_poll_mark) {
2332 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, 2314 ATH5K_DBG(ah, ATH5K_DEBUG_XMIT,
2333 "TX queue stuck %d\n", 2315 "TX queue stuck %d\n",
2334 txq->qnum); 2316 txq->qnum);
2335 needreset = true; 2317 needreset = true;
@@ -2345,14 +2327,14 @@ ath5k_tx_complete_poll_work(struct work_struct *work)
2345 } 2327 }
2346 2328
2347 if (needreset) { 2329 if (needreset) {
2348 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, 2330 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2349 "TX queues stuck, resetting\n"); 2331 "TX queues stuck, resetting\n");
2350 ath5k_reset(sc, NULL, true); 2332 ath5k_reset(ah, NULL, true);
2351 } 2333 }
2352 2334
2353 mutex_unlock(&sc->lock); 2335 mutex_unlock(&ah->lock);
2354 2336
2355 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 2337 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work,
2356 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT)); 2338 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2357} 2339}
2358 2340
@@ -2362,15 +2344,15 @@ ath5k_tx_complete_poll_work(struct work_struct *work)
2362\*************************/ 2344\*************************/
2363 2345
2364int __devinit 2346int __devinit
2365ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops) 2347ath5k_init_softc(struct ath5k_hw *ah, const struct ath_bus_ops *bus_ops)
2366{ 2348{
2367 struct ieee80211_hw *hw = sc->hw; 2349 struct ieee80211_hw *hw = ah->hw;
2368 struct ath_common *common; 2350 struct ath_common *common;
2369 int ret; 2351 int ret;
2370 int csz; 2352 int csz;
2371 2353
2372 /* Initialize driver private data */ 2354 /* Initialize driver private data */
2373 SET_IEEE80211_DEV(hw, sc->dev); 2355 SET_IEEE80211_DEV(hw, ah->dev);
2374 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | 2356 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
2375 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | 2357 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2376 IEEE80211_HW_SIGNAL_DBM | 2358 IEEE80211_HW_SIGNAL_DBM |
@@ -2393,39 +2375,29 @@ ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops)
2393 * Mark the device as detached to avoid processing 2375 * Mark the device as detached to avoid processing
2394 * interrupts until setup is complete. 2376 * interrupts until setup is complete.
2395 */ 2377 */
2396 __set_bit(ATH_STAT_INVALID, sc->status); 2378 __set_bit(ATH_STAT_INVALID, ah->status);
2397 2379
2398 sc->opmode = NL80211_IFTYPE_STATION; 2380 ah->opmode = NL80211_IFTYPE_STATION;
2399 sc->bintval = 1000; 2381 ah->bintval = 1000;
2400 mutex_init(&sc->lock); 2382 mutex_init(&ah->lock);
2401 spin_lock_init(&sc->rxbuflock); 2383 spin_lock_init(&ah->rxbuflock);
2402 spin_lock_init(&sc->txbuflock); 2384 spin_lock_init(&ah->txbuflock);
2403 spin_lock_init(&sc->block); 2385 spin_lock_init(&ah->block);
2404 spin_lock_init(&sc->irqlock); 2386 spin_lock_init(&ah->irqlock);
2405 2387
2406 /* Setup interrupt handler */ 2388 /* Setup interrupt handler */
2407 ret = request_irq(sc->irq, ath5k_intr, IRQF_SHARED, "ath", sc); 2389 ret = request_irq(ah->irq, ath5k_intr, IRQF_SHARED, "ath", ah);
2408 if (ret) { 2390 if (ret) {
2409 ATH5K_ERR(sc, "request_irq failed\n"); 2391 ATH5K_ERR(ah, "request_irq failed\n");
2410 goto err; 2392 goto err;
2411 } 2393 }
2412 2394
2413 /* If we passed the test, malloc an ath5k_hw struct */ 2395 common = ath5k_hw_common(ah);
2414 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
2415 if (!sc->ah) {
2416 ret = -ENOMEM;
2417 ATH5K_ERR(sc, "out of memory\n");
2418 goto err_irq;
2419 }
2420
2421 sc->ah->ah_sc = sc;
2422 sc->ah->ah_iobase = sc->iobase;
2423 common = ath5k_hw_common(sc->ah);
2424 common->ops = &ath5k_common_ops; 2396 common->ops = &ath5k_common_ops;
2425 common->bus_ops = bus_ops; 2397 common->bus_ops = bus_ops;
2426 common->ah = sc->ah; 2398 common->ah = ah;
2427 common->hw = hw; 2399 common->hw = hw;
2428 common->priv = sc; 2400 common->priv = ah;
2429 common->clockrate = 40; 2401 common->clockrate = 40;
2430 2402
2431 /* 2403 /*
@@ -2438,12 +2410,12 @@ ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops)
2438 spin_lock_init(&common->cc_lock); 2410 spin_lock_init(&common->cc_lock);
2439 2411
2440 /* Initialize device */ 2412 /* Initialize device */
2441 ret = ath5k_hw_init(sc); 2413 ret = ath5k_hw_init(ah);
2442 if (ret) 2414 if (ret)
2443 goto err_free_ah; 2415 goto err_irq;
2444 2416
2445 /* set up multi-rate retry capabilities */ 2417 /* set up multi-rate retry capabilities */
2446 if (sc->ah->ah_version == AR5K_AR5212) { 2418 if (ah->ah_version == AR5K_AR5212) {
2447 hw->max_rates = 4; 2419 hw->max_rates = 4;
2448 hw->max_rate_tries = max(AR5K_INIT_RETRY_SHORT, 2420 hw->max_rate_tries = max(AR5K_INIT_RETRY_SHORT,
2449 AR5K_INIT_RETRY_LONG); 2421 AR5K_INIT_RETRY_LONG);
@@ -2456,77 +2428,74 @@ ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops)
2456 if (ret) 2428 if (ret)
2457 goto err_ah; 2429 goto err_ah;
2458 2430
2459 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n", 2431 ATH5K_INFO(ah, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
2460 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev), 2432 ath5k_chip_name(AR5K_VERSION_MAC, ah->ah_mac_srev),
2461 sc->ah->ah_mac_srev, 2433 ah->ah_mac_srev,
2462 sc->ah->ah_phy_revision); 2434 ah->ah_phy_revision);
2463 2435
2464 if (!sc->ah->ah_single_chip) { 2436 if (!ah->ah_single_chip) {
2465 /* Single chip radio (!RF5111) */ 2437 /* Single chip radio (!RF5111) */
2466 if (sc->ah->ah_radio_5ghz_revision && 2438 if (ah->ah_radio_5ghz_revision &&
2467 !sc->ah->ah_radio_2ghz_revision) { 2439 !ah->ah_radio_2ghz_revision) {
2468 /* No 5GHz support -> report 2GHz radio */ 2440 /* No 5GHz support -> report 2GHz radio */
2469 if (!test_bit(AR5K_MODE_11A, 2441 if (!test_bit(AR5K_MODE_11A,
2470 sc->ah->ah_capabilities.cap_mode)) { 2442 ah->ah_capabilities.cap_mode)) {
2471 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n", 2443 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n",
2472 ath5k_chip_name(AR5K_VERSION_RAD, 2444 ath5k_chip_name(AR5K_VERSION_RAD,
2473 sc->ah->ah_radio_5ghz_revision), 2445 ah->ah_radio_5ghz_revision),
2474 sc->ah->ah_radio_5ghz_revision); 2446 ah->ah_radio_5ghz_revision);
2475 /* No 2GHz support (5110 and some 2447 /* No 2GHz support (5110 and some
2476 * 5GHz only cards) -> report 5GHz radio */ 2448 * 5GHz only cards) -> report 5GHz radio */
2477 } else if (!test_bit(AR5K_MODE_11B, 2449 } else if (!test_bit(AR5K_MODE_11B,
2478 sc->ah->ah_capabilities.cap_mode)) { 2450 ah->ah_capabilities.cap_mode)) {
2479 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n", 2451 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n",
2480 ath5k_chip_name(AR5K_VERSION_RAD, 2452 ath5k_chip_name(AR5K_VERSION_RAD,
2481 sc->ah->ah_radio_5ghz_revision), 2453 ah->ah_radio_5ghz_revision),
2482 sc->ah->ah_radio_5ghz_revision); 2454 ah->ah_radio_5ghz_revision);
2483 /* Multiband radio */ 2455 /* Multiband radio */
2484 } else { 2456 } else {
2485 ATH5K_INFO(sc, "RF%s multiband radio found" 2457 ATH5K_INFO(ah, "RF%s multiband radio found"
2486 " (0x%x)\n", 2458 " (0x%x)\n",
2487 ath5k_chip_name(AR5K_VERSION_RAD, 2459 ath5k_chip_name(AR5K_VERSION_RAD,
2488 sc->ah->ah_radio_5ghz_revision), 2460 ah->ah_radio_5ghz_revision),
2489 sc->ah->ah_radio_5ghz_revision); 2461 ah->ah_radio_5ghz_revision);
2490 } 2462 }
2491 } 2463 }
2492 /* Multi chip radio (RF5111 - RF2111) -> 2464 /* Multi chip radio (RF5111 - RF2111) ->
2493 * report both 2GHz/5GHz radios */ 2465 * report both 2GHz/5GHz radios */
2494 else if (sc->ah->ah_radio_5ghz_revision && 2466 else if (ah->ah_radio_5ghz_revision &&
2495 sc->ah->ah_radio_2ghz_revision) { 2467 ah->ah_radio_2ghz_revision) {
2496 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n", 2468 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n",
2497 ath5k_chip_name(AR5K_VERSION_RAD, 2469 ath5k_chip_name(AR5K_VERSION_RAD,
2498 sc->ah->ah_radio_5ghz_revision), 2470 ah->ah_radio_5ghz_revision),
2499 sc->ah->ah_radio_5ghz_revision); 2471 ah->ah_radio_5ghz_revision);
2500 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n", 2472 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n",
2501 ath5k_chip_name(AR5K_VERSION_RAD, 2473 ath5k_chip_name(AR5K_VERSION_RAD,
2502 sc->ah->ah_radio_2ghz_revision), 2474 ah->ah_radio_2ghz_revision),
2503 sc->ah->ah_radio_2ghz_revision); 2475 ah->ah_radio_2ghz_revision);
2504 } 2476 }
2505 } 2477 }
2506 2478
2507 ath5k_debug_init_device(sc); 2479 ath5k_debug_init_device(ah);
2508 2480
2509 /* ready to process interrupts */ 2481 /* ready to process interrupts */
2510 __clear_bit(ATH_STAT_INVALID, sc->status); 2482 __clear_bit(ATH_STAT_INVALID, ah->status);
2511 2483
2512 return 0; 2484 return 0;
2513err_ah: 2485err_ah:
2514 ath5k_hw_deinit(sc->ah); 2486 ath5k_hw_deinit(ah);
2515err_free_ah:
2516 kfree(sc->ah);
2517err_irq: 2487err_irq:
2518 free_irq(sc->irq, sc); 2488 free_irq(ah->irq, ah);
2519err: 2489err:
2520 return ret; 2490 return ret;
2521} 2491}
2522 2492
2523static int 2493static int
2524ath5k_stop_locked(struct ath5k_softc *sc) 2494ath5k_stop_locked(struct ath5k_hw *ah)
2525{ 2495{
2526 struct ath5k_hw *ah = sc->ah;
2527 2496
2528 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n", 2497 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "invalid %u\n",
2529 test_bit(ATH_STAT_INVALID, sc->status)); 2498 test_bit(ATH_STAT_INVALID, ah->status));
2530 2499
2531 /* 2500 /*
2532 * Shutdown the hardware and driver: 2501 * Shutdown the hardware and driver:
@@ -2543,37 +2512,36 @@ ath5k_stop_locked(struct ath5k_softc *sc)
2543 * Note that some of this work is not possible if the 2512 * Note that some of this work is not possible if the
2544 * hardware is gone (invalid). 2513 * hardware is gone (invalid).
2545 */ 2514 */
2546 ieee80211_stop_queues(sc->hw); 2515 ieee80211_stop_queues(ah->hw);
2547 2516
2548 if (!test_bit(ATH_STAT_INVALID, sc->status)) { 2517 if (!test_bit(ATH_STAT_INVALID, ah->status)) {
2549 ath5k_led_off(sc); 2518 ath5k_led_off(ah);
2550 ath5k_hw_set_imr(ah, 0); 2519 ath5k_hw_set_imr(ah, 0);
2551 synchronize_irq(sc->irq); 2520 synchronize_irq(ah->irq);
2552 ath5k_rx_stop(sc); 2521 ath5k_rx_stop(ah);
2553 ath5k_hw_dma_stop(ah); 2522 ath5k_hw_dma_stop(ah);
2554 ath5k_drain_tx_buffs(sc); 2523 ath5k_drain_tx_buffs(ah);
2555 ath5k_hw_phy_disable(ah); 2524 ath5k_hw_phy_disable(ah);
2556 } 2525 }
2557 2526
2558 return 0; 2527 return 0;
2559} 2528}
2560 2529
2561int 2530int ath5k_start(struct ieee80211_hw *hw)
2562ath5k_init_hw(struct ath5k_softc *sc)
2563{ 2531{
2564 struct ath5k_hw *ah = sc->ah; 2532 struct ath5k_hw *ah = hw->priv;
2565 struct ath_common *common = ath5k_hw_common(ah); 2533 struct ath_common *common = ath5k_hw_common(ah);
2566 int ret, i; 2534 int ret, i;
2567 2535
2568 mutex_lock(&sc->lock); 2536 mutex_lock(&ah->lock);
2569 2537
2570 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode); 2538 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "mode %d\n", ah->opmode);
2571 2539
2572 /* 2540 /*
2573 * Stop anything previously setup. This is safe 2541 * Stop anything previously setup. This is safe
2574 * no matter this is the first time through or not. 2542 * no matter this is the first time through or not.
2575 */ 2543 */
2576 ath5k_stop_locked(sc); 2544 ath5k_stop_locked(ah);
2577 2545
2578 /* 2546 /*
2579 * The basic interface to setting the hardware in a good 2547 * The basic interface to setting the hardware in a good
@@ -2582,12 +2550,12 @@ ath5k_init_hw(struct ath5k_softc *sc)
2582 * be followed by initialization of the appropriate bits 2550 * be followed by initialization of the appropriate bits
2583 * and then setup of the interrupt mask. 2551 * and then setup of the interrupt mask.
2584 */ 2552 */
2585 sc->curchan = sc->hw->conf.channel; 2553 ah->curchan = ah->hw->conf.channel;
2586 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL | 2554 ah->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2587 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL | 2555 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2588 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB; 2556 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
2589 2557
2590 ret = ath5k_reset(sc, NULL, false); 2558 ret = ath5k_reset(ah, NULL, false);
2591 if (ret) 2559 if (ret)
2592 goto done; 2560 goto done;
2593 2561
@@ -2604,29 +2572,29 @@ ath5k_init_hw(struct ath5k_softc *sc)
2604 * rate */ 2572 * rate */
2605 ah->ah_ack_bitrate_high = true; 2573 ah->ah_ack_bitrate_high = true;
2606 2574
2607 for (i = 0; i < ARRAY_SIZE(sc->bslot); i++) 2575 for (i = 0; i < ARRAY_SIZE(ah->bslot); i++)
2608 sc->bslot[i] = NULL; 2576 ah->bslot[i] = NULL;
2609 2577
2610 ret = 0; 2578 ret = 0;
2611done: 2579done:
2612 mmiowb(); 2580 mmiowb();
2613 mutex_unlock(&sc->lock); 2581 mutex_unlock(&ah->lock);
2614 2582
2615 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 2583 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work,
2616 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT)); 2584 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2617 2585
2618 return ret; 2586 return ret;
2619} 2587}
2620 2588
2621static void ath5k_stop_tasklets(struct ath5k_softc *sc) 2589static void ath5k_stop_tasklets(struct ath5k_hw *ah)
2622{ 2590{
2623 sc->rx_pending = false; 2591 ah->rx_pending = false;
2624 sc->tx_pending = false; 2592 ah->tx_pending = false;
2625 tasklet_kill(&sc->rxtq); 2593 tasklet_kill(&ah->rxtq);
2626 tasklet_kill(&sc->txtq); 2594 tasklet_kill(&ah->txtq);
2627 tasklet_kill(&sc->calib); 2595 tasklet_kill(&ah->calib);
2628 tasklet_kill(&sc->beacontq); 2596 tasklet_kill(&ah->beacontq);
2629 tasklet_kill(&sc->ani_tasklet); 2597 tasklet_kill(&ah->ani_tasklet);
2630} 2598}
2631 2599
2632/* 2600/*
@@ -2635,14 +2603,14 @@ static void ath5k_stop_tasklets(struct ath5k_softc *sc)
2635 * if another thread does a system call and the thread doing the 2603 * if another thread does a system call and the thread doing the
2636 * stop is preempted). 2604 * stop is preempted).
2637 */ 2605 */
2638int 2606void ath5k_stop(struct ieee80211_hw *hw)
2639ath5k_stop_hw(struct ath5k_softc *sc)
2640{ 2607{
2608 struct ath5k_hw *ah = hw->priv;
2641 int ret; 2609 int ret;
2642 2610
2643 mutex_lock(&sc->lock); 2611 mutex_lock(&ah->lock);
2644 ret = ath5k_stop_locked(sc); 2612 ret = ath5k_stop_locked(ah);
2645 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) { 2613 if (ret == 0 && !test_bit(ATH_STAT_INVALID, ah->status)) {
2646 /* 2614 /*
2647 * Don't set the card in full sleep mode! 2615 * Don't set the card in full sleep mode!
2648 * 2616 *
@@ -2663,69 +2631,66 @@ ath5k_stop_hw(struct ath5k_softc *sc)
2663 * and Sam's HAL do anyway). Instead Perform a full reset 2631 * and Sam's HAL do anyway). Instead Perform a full reset
2664 * on the device (same as initial state after attach) and 2632 * on the device (same as initial state after attach) and
2665 * leave it idle (keep MAC/BB on warm reset) */ 2633 * leave it idle (keep MAC/BB on warm reset) */
2666 ret = ath5k_hw_on_hold(sc->ah); 2634 ret = ath5k_hw_on_hold(ah);
2667 2635
2668 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, 2636 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2669 "putting device to sleep\n"); 2637 "putting device to sleep\n");
2670 } 2638 }
2671 2639
2672 mmiowb(); 2640 mmiowb();
2673 mutex_unlock(&sc->lock); 2641 mutex_unlock(&ah->lock);
2674
2675 ath5k_stop_tasklets(sc);
2676 2642
2677 cancel_delayed_work_sync(&sc->tx_complete_work); 2643 ath5k_stop_tasklets(ah);
2678 2644
2679 ath5k_rfkill_hw_stop(sc->ah); 2645 cancel_delayed_work_sync(&ah->tx_complete_work);
2680 2646
2681 return ret; 2647 ath5k_rfkill_hw_stop(ah);
2682} 2648}
2683 2649
2684/* 2650/*
2685 * Reset the hardware. If chan is not NULL, then also pause rx/tx 2651 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2686 * and change to the given channel. 2652 * and change to the given channel.
2687 * 2653 *
2688 * This should be called with sc->lock. 2654 * This should be called with ah->lock.
2689 */ 2655 */
2690static int 2656static int
2691ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan, 2657ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
2692 bool skip_pcu) 2658 bool skip_pcu)
2693{ 2659{
2694 struct ath5k_hw *ah = sc->ah;
2695 struct ath_common *common = ath5k_hw_common(ah); 2660 struct ath_common *common = ath5k_hw_common(ah);
2696 int ret, ani_mode; 2661 int ret, ani_mode;
2697 bool fast; 2662 bool fast;
2698 2663
2699 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n"); 2664 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "resetting\n");
2700 2665
2701 ath5k_hw_set_imr(ah, 0); 2666 ath5k_hw_set_imr(ah, 0);
2702 synchronize_irq(sc->irq); 2667 synchronize_irq(ah->irq);
2703 ath5k_stop_tasklets(sc); 2668 ath5k_stop_tasklets(ah);
2704 2669
2705 /* Save ani mode and disable ANI during 2670 /* Save ani mode and disable ANI during
2706 * reset. If we don't we might get false 2671 * reset. If we don't we might get false
2707 * PHY error interrupts. */ 2672 * PHY error interrupts. */
2708 ani_mode = ah->ah_sc->ani_state.ani_mode; 2673 ani_mode = ah->ani_state.ani_mode;
2709 ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF); 2674 ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF);
2710 2675
2711 /* We are going to empty hw queues 2676 /* We are going to empty hw queues
2712 * so we should also free any remaining 2677 * so we should also free any remaining
2713 * tx buffers */ 2678 * tx buffers */
2714 ath5k_drain_tx_buffs(sc); 2679 ath5k_drain_tx_buffs(ah);
2715 if (chan) 2680 if (chan)
2716 sc->curchan = chan; 2681 ah->curchan = chan;
2717 2682
2718 fast = ((chan != NULL) && modparam_fastchanswitch) ? 1 : 0; 2683 fast = ((chan != NULL) && modparam_fastchanswitch) ? 1 : 0;
2719 2684
2720 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, fast, skip_pcu); 2685 ret = ath5k_hw_reset(ah, ah->opmode, ah->curchan, fast, skip_pcu);
2721 if (ret) { 2686 if (ret) {
2722 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret); 2687 ATH5K_ERR(ah, "can't reset hardware (%d)\n", ret);
2723 goto err; 2688 goto err;
2724 } 2689 }
2725 2690
2726 ret = ath5k_rx_start(sc); 2691 ret = ath5k_rx_start(ah);
2727 if (ret) { 2692 if (ret) {
2728 ATH5K_ERR(sc, "can't start recv logic\n"); 2693 ATH5K_ERR(ah, "can't start recv logic\n");
2729 goto err; 2694 goto err;
2730 } 2695 }
2731 2696
@@ -2737,7 +2702,7 @@ ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
2737 ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8); 2702 ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8);
2738 2703
2739 /* clear survey data and cycle counters */ 2704 /* clear survey data and cycle counters */
2740 memset(&sc->survey, 0, sizeof(sc->survey)); 2705 memset(&ah->survey, 0, sizeof(ah->survey));
2741 spin_lock_bh(&common->cc_lock); 2706 spin_lock_bh(&common->cc_lock);
2742 ath_hw_cycle_counters_update(common); 2707 ath_hw_cycle_counters_update(common);
2743 memset(&common->cc_survey, 0, sizeof(common->cc_survey)); 2708 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
@@ -2753,12 +2718,12 @@ ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
2753 * 2718 *
2754 * XXX needed? 2719 * XXX needed?
2755 */ 2720 */
2756/* ath5k_chan_change(sc, c); */ 2721/* ath5k_chan_change(ah, c); */
2757 2722
2758 ath5k_beacon_config(sc); 2723 ath5k_beacon_config(ah);
2759 /* intrs are enabled by ath5k_beacon_config */ 2724 /* intrs are enabled by ath5k_beacon_config */
2760 2725
2761 ieee80211_wake_queues(sc->hw); 2726 ieee80211_wake_queues(ah->hw);
2762 2727
2763 return 0; 2728 return 0;
2764err: 2729err:
@@ -2767,20 +2732,19 @@ err:
2767 2732
2768static void ath5k_reset_work(struct work_struct *work) 2733static void ath5k_reset_work(struct work_struct *work)
2769{ 2734{
2770 struct ath5k_softc *sc = container_of(work, struct ath5k_softc, 2735 struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
2771 reset_work); 2736 reset_work);
2772 2737
2773 mutex_lock(&sc->lock); 2738 mutex_lock(&ah->lock);
2774 ath5k_reset(sc, NULL, true); 2739 ath5k_reset(ah, NULL, true);
2775 mutex_unlock(&sc->lock); 2740 mutex_unlock(&ah->lock);
2776} 2741}
2777 2742
2778static int __devinit 2743static int __devinit
2779ath5k_init(struct ieee80211_hw *hw) 2744ath5k_init(struct ieee80211_hw *hw)
2780{ 2745{
2781 2746
2782 struct ath5k_softc *sc = hw->priv; 2747 struct ath5k_hw *ah = hw->priv;
2783 struct ath5k_hw *ah = sc->ah;
2784 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); 2748 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
2785 struct ath5k_txq *txq; 2749 struct ath5k_txq *txq;
2786 u8 mac[ETH_ALEN] = {}; 2750 u8 mac[ETH_ALEN] = {};
@@ -2799,7 +2763,7 @@ ath5k_init(struct ieee80211_hw *hw)
2799 if (ret < 0) 2763 if (ret < 0)
2800 goto err; 2764 goto err;
2801 if (ret > 0) 2765 if (ret > 0)
2802 __set_bit(ATH_STAT_MRRETRY, sc->status); 2766 __set_bit(ATH_STAT_MRRETRY, ah->status);
2803 2767
2804 /* 2768 /*
2805 * Collect the channel list. The 802.11 layer 2769 * Collect the channel list. The 802.11 layer
@@ -2809,16 +2773,16 @@ ath5k_init(struct ieee80211_hw *hw)
2809 */ 2773 */
2810 ret = ath5k_setup_bands(hw); 2774 ret = ath5k_setup_bands(hw);
2811 if (ret) { 2775 if (ret) {
2812 ATH5K_ERR(sc, "can't get channels\n"); 2776 ATH5K_ERR(ah, "can't get channels\n");
2813 goto err; 2777 goto err;
2814 } 2778 }
2815 2779
2816 /* 2780 /*
2817 * Allocate tx+rx descriptors and populate the lists. 2781 * Allocate tx+rx descriptors and populate the lists.
2818 */ 2782 */
2819 ret = ath5k_desc_alloc(sc); 2783 ret = ath5k_desc_alloc(ah);
2820 if (ret) { 2784 if (ret) {
2821 ATH5K_ERR(sc, "can't allocate descriptors\n"); 2785 ATH5K_ERR(ah, "can't allocate descriptors\n");
2822 goto err; 2786 goto err;
2823 } 2787 }
2824 2788
@@ -2830,14 +2794,14 @@ ath5k_init(struct ieee80211_hw *hw)
2830 */ 2794 */
2831 ret = ath5k_beaconq_setup(ah); 2795 ret = ath5k_beaconq_setup(ah);
2832 if (ret < 0) { 2796 if (ret < 0) {
2833 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n"); 2797 ATH5K_ERR(ah, "can't setup a beacon xmit queue\n");
2834 goto err_desc; 2798 goto err_desc;
2835 } 2799 }
2836 sc->bhalq = ret; 2800 ah->bhalq = ret;
2837 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0); 2801 ah->cabq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_CAB, 0);
2838 if (IS_ERR(sc->cabq)) { 2802 if (IS_ERR(ah->cabq)) {
2839 ATH5K_ERR(sc, "can't setup cab queue\n"); 2803 ATH5K_ERR(ah, "can't setup cab queue\n");
2840 ret = PTR_ERR(sc->cabq); 2804 ret = PTR_ERR(ah->cabq);
2841 goto err_bhal; 2805 goto err_bhal;
2842 } 2806 }
2843 2807
@@ -2846,97 +2810,97 @@ ath5k_init(struct ieee80211_hw *hw)
2846 if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) { 2810 if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) {
2847 /* This order matches mac80211's queue priority, so we can 2811 /* This order matches mac80211's queue priority, so we can
2848 * directly use the mac80211 queue number without any mapping */ 2812 * directly use the mac80211 queue number without any mapping */
2849 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO); 2813 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
2850 if (IS_ERR(txq)) { 2814 if (IS_ERR(txq)) {
2851 ATH5K_ERR(sc, "can't setup xmit queue\n"); 2815 ATH5K_ERR(ah, "can't setup xmit queue\n");
2852 ret = PTR_ERR(txq); 2816 ret = PTR_ERR(txq);
2853 goto err_queues; 2817 goto err_queues;
2854 } 2818 }
2855 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI); 2819 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
2856 if (IS_ERR(txq)) { 2820 if (IS_ERR(txq)) {
2857 ATH5K_ERR(sc, "can't setup xmit queue\n"); 2821 ATH5K_ERR(ah, "can't setup xmit queue\n");
2858 ret = PTR_ERR(txq); 2822 ret = PTR_ERR(txq);
2859 goto err_queues; 2823 goto err_queues;
2860 } 2824 }
2861 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE); 2825 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2862 if (IS_ERR(txq)) { 2826 if (IS_ERR(txq)) {
2863 ATH5K_ERR(sc, "can't setup xmit queue\n"); 2827 ATH5K_ERR(ah, "can't setup xmit queue\n");
2864 ret = PTR_ERR(txq); 2828 ret = PTR_ERR(txq);
2865 goto err_queues; 2829 goto err_queues;
2866 } 2830 }
2867 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK); 2831 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
2868 if (IS_ERR(txq)) { 2832 if (IS_ERR(txq)) {
2869 ATH5K_ERR(sc, "can't setup xmit queue\n"); 2833 ATH5K_ERR(ah, "can't setup xmit queue\n");
2870 ret = PTR_ERR(txq); 2834 ret = PTR_ERR(txq);
2871 goto err_queues; 2835 goto err_queues;
2872 } 2836 }
2873 hw->queues = 4; 2837 hw->queues = 4;
2874 } else { 2838 } else {
2875 /* older hardware (5210) can only support one data queue */ 2839 /* older hardware (5210) can only support one data queue */
2876 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE); 2840 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2877 if (IS_ERR(txq)) { 2841 if (IS_ERR(txq)) {
2878 ATH5K_ERR(sc, "can't setup xmit queue\n"); 2842 ATH5K_ERR(ah, "can't setup xmit queue\n");
2879 ret = PTR_ERR(txq); 2843 ret = PTR_ERR(txq);
2880 goto err_queues; 2844 goto err_queues;
2881 } 2845 }
2882 hw->queues = 1; 2846 hw->queues = 1;
2883 } 2847 }
2884 2848
2885 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc); 2849 tasklet_init(&ah->rxtq, ath5k_tasklet_rx, (unsigned long)ah);
2886 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc); 2850 tasklet_init(&ah->txtq, ath5k_tasklet_tx, (unsigned long)ah);
2887 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc); 2851 tasklet_init(&ah->calib, ath5k_tasklet_calibrate, (unsigned long)ah);
2888 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc); 2852 tasklet_init(&ah->beacontq, ath5k_tasklet_beacon, (unsigned long)ah);
2889 tasklet_init(&sc->ani_tasklet, ath5k_tasklet_ani, (unsigned long)sc); 2853 tasklet_init(&ah->ani_tasklet, ath5k_tasklet_ani, (unsigned long)ah);
2890 2854
2891 INIT_WORK(&sc->reset_work, ath5k_reset_work); 2855 INIT_WORK(&ah->reset_work, ath5k_reset_work);
2892 INIT_DELAYED_WORK(&sc->tx_complete_work, ath5k_tx_complete_poll_work); 2856 INIT_DELAYED_WORK(&ah->tx_complete_work, ath5k_tx_complete_poll_work);
2893 2857
2894 ret = ath5k_hw_common(ah)->bus_ops->eeprom_read_mac(ah, mac); 2858 ret = ath5k_hw_common(ah)->bus_ops->eeprom_read_mac(ah, mac);
2895 if (ret) { 2859 if (ret) {
2896 ATH5K_ERR(sc, "unable to read address from EEPROM\n"); 2860 ATH5K_ERR(ah, "unable to read address from EEPROM\n");
2897 goto err_queues; 2861 goto err_queues;
2898 } 2862 }
2899 2863
2900 SET_IEEE80211_PERM_ADDR(hw, mac); 2864 SET_IEEE80211_PERM_ADDR(hw, mac);
2901 memcpy(&sc->lladdr, mac, ETH_ALEN); 2865 memcpy(&ah->lladdr, mac, ETH_ALEN);
2902 /* All MAC address bits matter for ACKs */ 2866 /* All MAC address bits matter for ACKs */
2903 ath5k_update_bssid_mask_and_opmode(sc, NULL); 2867 ath5k_update_bssid_mask_and_opmode(ah, NULL);
2904 2868
2905 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain; 2869 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
2906 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier); 2870 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
2907 if (ret) { 2871 if (ret) {
2908 ATH5K_ERR(sc, "can't initialize regulatory system\n"); 2872 ATH5K_ERR(ah, "can't initialize regulatory system\n");
2909 goto err_queues; 2873 goto err_queues;
2910 } 2874 }
2911 2875
2912 ret = ieee80211_register_hw(hw); 2876 ret = ieee80211_register_hw(hw);
2913 if (ret) { 2877 if (ret) {
2914 ATH5K_ERR(sc, "can't register ieee80211 hw\n"); 2878 ATH5K_ERR(ah, "can't register ieee80211 hw\n");
2915 goto err_queues; 2879 goto err_queues;
2916 } 2880 }
2917 2881
2918 if (!ath_is_world_regd(regulatory)) 2882 if (!ath_is_world_regd(regulatory))
2919 regulatory_hint(hw->wiphy, regulatory->alpha2); 2883 regulatory_hint(hw->wiphy, regulatory->alpha2);
2920 2884
2921 ath5k_init_leds(sc); 2885 ath5k_init_leds(ah);
2922 2886
2923 ath5k_sysfs_register(sc); 2887 ath5k_sysfs_register(ah);
2924 2888
2925 return 0; 2889 return 0;
2926err_queues: 2890err_queues:
2927 ath5k_txq_release(sc); 2891 ath5k_txq_release(ah);
2928err_bhal: 2892err_bhal:
2929 ath5k_hw_release_tx_queue(ah, sc->bhalq); 2893 ath5k_hw_release_tx_queue(ah, ah->bhalq);
2930err_desc: 2894err_desc:
2931 ath5k_desc_free(sc); 2895 ath5k_desc_free(ah);
2932err: 2896err:
2933 return ret; 2897 return ret;
2934} 2898}
2935 2899
2936void 2900void
2937ath5k_deinit_softc(struct ath5k_softc *sc) 2901ath5k_deinit_softc(struct ath5k_hw *ah)
2938{ 2902{
2939 struct ieee80211_hw *hw = sc->hw; 2903 struct ieee80211_hw *hw = ah->hw;
2940 2904
2941 /* 2905 /*
2942 * NB: the order of these is important: 2906 * NB: the order of these is important:
@@ -2952,24 +2916,23 @@ ath5k_deinit_softc(struct ath5k_softc *sc)
2952 * Other than that, it's straightforward... 2916 * Other than that, it's straightforward...
2953 */ 2917 */
2954 ieee80211_unregister_hw(hw); 2918 ieee80211_unregister_hw(hw);
2955 ath5k_desc_free(sc); 2919 ath5k_desc_free(ah);
2956 ath5k_txq_release(sc); 2920 ath5k_txq_release(ah);
2957 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq); 2921 ath5k_hw_release_tx_queue(ah, ah->bhalq);
2958 ath5k_unregister_leds(sc); 2922 ath5k_unregister_leds(ah);
2959 2923
2960 ath5k_sysfs_unregister(sc); 2924 ath5k_sysfs_unregister(ah);
2961 /* 2925 /*
2962 * NB: can't reclaim these until after ieee80211_ifdetach 2926 * NB: can't reclaim these until after ieee80211_ifdetach
2963 * returns because we'll get called back to reclaim node 2927 * returns because we'll get called back to reclaim node
2964 * state and potentially want to use them. 2928 * state and potentially want to use them.
2965 */ 2929 */
2966 ath5k_hw_deinit(sc->ah); 2930 ath5k_hw_deinit(ah);
2967 kfree(sc->ah); 2931 free_irq(ah->irq, ah);
2968 free_irq(sc->irq, sc);
2969} 2932}
2970 2933
2971bool 2934bool
2972ath5k_any_vif_assoc(struct ath5k_softc *sc) 2935ath5k_any_vif_assoc(struct ath5k_hw *ah)
2973{ 2936{
2974 struct ath5k_vif_iter_data iter_data; 2937 struct ath5k_vif_iter_data iter_data;
2975 iter_data.hw_macaddr = NULL; 2938 iter_data.hw_macaddr = NULL;
@@ -2977,7 +2940,7 @@ ath5k_any_vif_assoc(struct ath5k_softc *sc)
2977 iter_data.need_set_hw_addr = false; 2940 iter_data.need_set_hw_addr = false;
2978 iter_data.found_active = true; 2941 iter_data.found_active = true;
2979 2942
2980 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath5k_vif_iter, 2943 ieee80211_iterate_active_interfaces_atomic(ah->hw, ath5k_vif_iter,
2981 &iter_data); 2944 &iter_data);
2982 return iter_data.any_assoc; 2945 return iter_data.any_assoc;
2983} 2946}
@@ -2985,8 +2948,7 @@ ath5k_any_vif_assoc(struct ath5k_softc *sc)
2985void 2948void
2986ath5k_set_beacon_filter(struct ieee80211_hw *hw, bool enable) 2949ath5k_set_beacon_filter(struct ieee80211_hw *hw, bool enable)
2987{ 2950{
2988 struct ath5k_softc *sc = hw->priv; 2951 struct ath5k_hw *ah = hw->priv;
2989 struct ath5k_hw *ah = sc->ah;
2990 u32 rfilt; 2952 u32 rfilt;
2991 rfilt = ath5k_hw_get_rx_filter(ah); 2953 rfilt = ath5k_hw_get_rx_filter(ah);
2992 if (enable) 2954 if (enable)
@@ -2994,5 +2956,5 @@ ath5k_set_beacon_filter(struct ieee80211_hw *hw, bool enable)
2994 else 2956 else
2995 rfilt &= ~AR5K_RX_FILTER_BEACON; 2957 rfilt &= ~AR5K_RX_FILTER_BEACON;
2996 ath5k_hw_set_rx_filter(ah, rfilt); 2958 ath5k_hw_set_rx_filter(ah, rfilt);
2997 sc->filter_flags = rfilt; 2959 ah->filter_flags = rfilt;
2998} 2960}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 01:19:21 -0500