1 files changed, 72 insertions, 66 deletions

diff --git a/drivers/net/wireless/ath/ath5k/base.c b/drivers/net/wireless/ath/ath5k/base.c
index 3a1c156d275f..2b3cf39dd4b1 100644
--- a/drivers/net/wireless/ath/ath5k/base.c
+++ b/drivers/net/wireless/ath/ath5k/base.c
@@ -59,7 +59,7 @@
 #include "reg.h"
 #include "debug.h"
 
-static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
+static u8 ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
 static int modparam_nohwcrypt;
 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
@@ -376,7 +376,7 @@ static int 	ath5k_stop_hw(struct ath5k_softc *sc);
 static irqreturn_t ath5k_intr(int irq, void *dev_id);
 static void     ath5k_tasklet_reset(unsigned long data);
 
-static void     ath5k_calibrate(unsigned long data);
+static void     ath5k_tasklet_calibrate(unsigned long data);
 
 /*
  * Module init/exit functions
@@ -471,7 +471,7 @@ ath5k_pci_probe(struct pci_dev *pdev,
                  * DMA to work so force a reasonable value here if it
                  * comes up zero.
                  */
-                csz = L1_CACHE_BYTES / sizeof(u32);
+                csz = L1_CACHE_BYTES >> 2;
                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
         }
         /*
@@ -544,7 +544,7 @@ ath5k_pci_probe(struct pci_dev *pdev,
         __set_bit(ATH_STAT_INVALID, sc->status);
 
         sc->iobase = mem; /* So we can unmap it on detach */
-        sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
+        sc->common.cachelsz = csz << 2; /* convert to bytes */
         sc->opmode = NL80211_IFTYPE_STATION;
         sc->bintval = 1000;
         mutex_init(&sc->lock);
@@ -799,8 +799,8 @@ ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
         tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
         tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
         tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
+        tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
         tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
-        setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
 
         ret = ath5k_eeprom_read_mac(ah, mac);
         if (ret) {
@@ -1071,10 +1071,9 @@ ath5k_setup_bands(struct ieee80211_hw *hw)
 }
 
 /*
- * Set/change channels.  If the channel is really being changed,
- * it's done by reseting the chip.  To accomplish this we must
- * first cleanup any pending DMA, then restart stuff after a la
- * ath5k_init.
+ * Set/change channels. We always reset the chip.
+ * To accomplish this we must first cleanup any pending DMA,
+ * then restart stuff after a la  ath5k_init.
  *
  * Called with sc->lock.
  */
@@ -1084,19 +1083,13 @@ ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
                 sc->curchan->center_freq, chan->center_freq);
 
-        if (chan->center_freq != sc->curchan->center_freq ||
-                chan->hw_value != sc->curchan->hw_value) {
-
-                /*
-                 * To switch channels clear any pending DMA operations;
-                 * wait long enough for the RX fifo to drain, reset the
-                 * hardware at the new frequency, and then re-enable
-                 * the relevant bits of the h/w.
-                 */
-                return ath5k_reset(sc, chan);
-        }
-
-        return 0;
+        /*
+         * To switch channels clear any pending DMA operations;
+         * wait long enough for the RX fifo to drain, reset the
+         * hardware at the new frequency, and then re-enable
+         * the relevant bits of the h/w.
+         */
+        return ath5k_reset(sc, chan);
 }
 
 static void
@@ -1158,27 +1151,20 @@ static
 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
 {
         struct sk_buff *skb;
-        unsigned int off;
 
         /*
          * Allocate buffer with headroom_needed space for the
          * fake physical layer header at the start.
          */
-        skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
+        skb = ath_rxbuf_alloc(&sc->common,
+                              sc->rxbufsize + sc->common.cachelsz - 1,
+                              GFP_ATOMIC);
 
         if (!skb) {
                 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
-                                sc->rxbufsize + sc->cachelsz - 1);
+                                sc->rxbufsize + sc->common.cachelsz - 1);
                 return NULL;
         }
-        /*
-         * Cache-line-align.  This is important (for the
-         * 5210 at least) as not doing so causes bogus data
-         * in rx'd frames.
-         */
-        off = ((unsigned long)skb->data) % sc->cachelsz;
-        if (off != 0)
-                skb_reserve(skb, sc->cachelsz - off);
 
         *skb_addr = pci_map_single(sc->pdev,
                 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
@@ -1620,10 +1606,10 @@ ath5k_rx_start(struct ath5k_softc *sc)
         struct ath5k_buf *bf;
         int ret;
 
-        sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
+        sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->common.cachelsz);
 
         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
-                sc->cachelsz, sc->rxbufsize);
+                sc->common.cachelsz, sc->rxbufsize);
 
         spin_lock_bh(&sc->rxbuflock);
         sc->rxlink = NULL;
@@ -2371,7 +2357,7 @@ ath5k_init(struct ath5k_softc *sc)
         sc->curband = &sc->sbands[sc->curchan->band];
         sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
                 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
-                AR5K_INT_FATAL | AR5K_INT_GLOBAL;
+                AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_SWI;
         ret = ath5k_reset(sc, NULL);
         if (ret)
                 goto done;
@@ -2388,8 +2374,8 @@ ath5k_init(struct ath5k_softc *sc)
         /* Set ack to be sent at low bit-rates */
         ath5k_hw_set_ack_bitrate_high(ah, false);
 
-        mod_timer(&sc->calib_tim, round_jiffies(jiffies +
-                        msecs_to_jiffies(ath5k_calinterval * 1000)));
+        /* Set PHY calibration inteval */
+        ah->ah_cal_intval = ath5k_calinterval;
 
         ret = 0;
 done:
@@ -2453,37 +2439,39 @@ ath5k_stop_hw(struct ath5k_softc *sc)
         ret = ath5k_stop_locked(sc);
         if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
                 /*
-                 * Set the chip in full sleep mode.  Note that we are
-                 * careful to do this only when bringing the interface
-                 * completely to a stop.  When the chip is in this state
-                 * it must be carefully woken up or references to
-                 * registers in the PCI clock domain may freeze the bus
-                 * (and system).  This varies by chip and is mostly an
-                 * issue with newer parts that go to sleep more quickly.
-                 */
-                if (sc->ah->ah_mac_srev >= 0x78) {
-                        /*
-                         * XXX
-                         * don't put newer MAC revisions > 7.8 to sleep because
-                         * of the above mentioned problems
-                         */
-                        ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
-                                "not putting device to sleep\n");
-                } else {
-                        ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
-                                "putting device to full sleep\n");
-                        ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
-                }
+                 * Don't set the card in full sleep mode!
+                 *
+                 * a) When the device is in this state it must be carefully
+                 * woken up or references to registers in the PCI clock
+                 * domain may freeze the bus (and system).  This varies
+                 * by chip and is mostly an issue with newer parts
+                 * (madwifi sources mentioned srev >= 0x78) that go to
+                 * sleep more quickly.
+                 *
+                 * b) On older chips full sleep results a weird behaviour
+                 * during wakeup. I tested various cards with srev < 0x78
+                 * and they don't wake up after module reload, a second
+                 * module reload is needed to bring the card up again.
+                 *
+                 * Until we figure out what's going on don't enable
+                 * full chip reset on any chip (this is what Legacy HAL
+                 * and Sam's HAL do anyway). Instead Perform a full reset
+                 * on the device (same as initial state after attach) and
+                 * leave it idle (keep MAC/BB on warm reset) */
+                ret = ath5k_hw_on_hold(sc->ah);
+
+                ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
+                                "putting device to sleep\n");
         }
         ath5k_txbuf_free(sc, sc->bbuf);
 
         mmiowb();
         mutex_unlock(&sc->lock);
 
-        del_timer_sync(&sc->calib_tim);
         tasklet_kill(&sc->rxtq);
         tasklet_kill(&sc->txtq);
         tasklet_kill(&sc->restq);
+        tasklet_kill(&sc->calib);
         tasklet_kill(&sc->beacontq);
 
         ath5k_rfkill_hw_stop(sc->ah);
@@ -2539,6 +2527,9 @@ ath5k_intr(int irq, void *dev_id)
                         if (status & AR5K_INT_BMISS) {
                                 /* TODO */
                         }
+                        if (status & AR5K_INT_SWI) {
+                                tasklet_schedule(&sc->calib);
+                        }
                         if (status & AR5K_INT_MIB) {
                                 /*
                                  * These stats are also used for ANI i think
@@ -2555,6 +2546,8 @@ ath5k_intr(int irq, void *dev_id)
         if (unlikely(!counter))
                 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
 
+        ath5k_hw_calibration_poll(ah);
+
         return IRQ_HANDLED;
 }
 
@@ -2571,11 +2564,19 @@ ath5k_tasklet_reset(unsigned long data)
  * for temperature/environment changes.
  */
 static void
-ath5k_calibrate(unsigned long data)
+ath5k_tasklet_calibrate(unsigned long data)
 {
         struct ath5k_softc *sc = (void *)data;
         struct ath5k_hw *ah = sc->ah;
 
+        /* Only full calibration for now */
+        if (ah->ah_swi_mask != AR5K_SWI_FULL_CALIBRATION)
+                return;
+
+        /* Stop queues so that calibration
+         * doesn't interfere with tx */
+        ieee80211_stop_queues(sc->hw);
+
         ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
                 ieee80211_frequency_to_channel(sc->curchan->center_freq),
                 sc->curchan->hw_value);
@@ -2593,8 +2594,11 @@ ath5k_calibrate(unsigned long data)
                         ieee80211_frequency_to_channel(
                                 sc->curchan->center_freq));
 
-        mod_timer(&sc->calib_tim, round_jiffies(jiffies +
-                        msecs_to_jiffies(ath5k_calinterval * 1000)));
+        ah->ah_swi_mask = 0;
+
+        /* Wake queues */
+        ieee80211_wake_queues(sc->hw);
+
 }
 
 
@@ -2811,9 +2815,11 @@ ath5k_config(struct ieee80211_hw *hw, u32 changed)
 
         mutex_lock(&sc->lock);
 
-        ret = ath5k_chan_set(sc, conf->channel);
-        if (ret < 0)
-                goto unlock;
+        if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
+                ret = ath5k_chan_set(sc, conf->channel);
+                if (ret < 0)
+                        goto unlock;
+        }
 
         if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
         (sc->power_level != conf->power_level)) {