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-rw-r--r--drivers/net/wireless/ath/ath5k/attach.c348
1 files changed, 348 insertions, 0 deletions
diff --git a/drivers/net/wireless/ath/ath5k/attach.c b/drivers/net/wireless/ath/ath5k/attach.c
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1/*
2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 *
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 */
18
19/*************************************\
20* Attach/Detach Functions and helpers *
21\*************************************/
22
23#include <linux/pci.h>
24#include "ath5k.h"
25#include "reg.h"
26#include "debug.h"
27#include "base.h"
28
29/**
30 * ath5k_hw_post - Power On Self Test helper function
31 *
32 * @ah: The &struct ath5k_hw
33 */
34static int ath5k_hw_post(struct ath5k_hw *ah)
35{
36
37 static const u32 static_pattern[4] = {
38 0x55555555, 0xaaaaaaaa,
39 0x66666666, 0x99999999
40 };
41 static const u16 regs[2] = { AR5K_STA_ID0, AR5K_PHY(8) };
42 int i, c;
43 u16 cur_reg;
44 u32 var_pattern;
45 u32 init_val;
46 u32 cur_val;
47
48 for (c = 0; c < 2; c++) {
49
50 cur_reg = regs[c];
51
52 /* Save previous value */
53 init_val = ath5k_hw_reg_read(ah, cur_reg);
54
55 for (i = 0; i < 256; i++) {
56 var_pattern = i << 16 | i;
57 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
58 cur_val = ath5k_hw_reg_read(ah, cur_reg);
59
60 if (cur_val != var_pattern) {
61 ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n");
62 return -EAGAIN;
63 }
64
65 /* Found on ndiswrapper dumps */
66 var_pattern = 0x0039080f;
67 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
68 }
69
70 for (i = 0; i < 4; i++) {
71 var_pattern = static_pattern[i];
72 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
73 cur_val = ath5k_hw_reg_read(ah, cur_reg);
74
75 if (cur_val != var_pattern) {
76 ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n");
77 return -EAGAIN;
78 }
79
80 /* Found on ndiswrapper dumps */
81 var_pattern = 0x003b080f;
82 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
83 }
84
85 /* Restore previous value */
86 ath5k_hw_reg_write(ah, init_val, cur_reg);
87
88 }
89
90 return 0;
91
92}
93
94/**
95 * ath5k_hw_attach - Check if hw is supported and init the needed structs
96 *
97 * @sc: The &struct ath5k_softc we got from the driver's attach function
98 * @mac_version: The mac version id (check out ath5k.h) based on pci id
99 *
100 * Check if the device is supported, perform a POST and initialize the needed
101 * structs. Returns -ENOMEM if we don't have memory for the needed structs,
102 * -ENODEV if the device is not supported or prints an error msg if something
103 * else went wrong.
104 */
105struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
106{
107 struct ath5k_hw *ah;
108 struct pci_dev *pdev = sc->pdev;
109 int ret;
110 u32 srev;
111
112 /*If we passed the test malloc a ath5k_hw struct*/
113 ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
114 if (ah == NULL) {
115 ret = -ENOMEM;
116 ATH5K_ERR(sc, "out of memory\n");
117 goto err;
118 }
119
120 ah->ah_sc = sc;
121 ah->ah_iobase = sc->iobase;
122
123 /*
124 * HW information
125 */
126 ah->ah_op_mode = NL80211_IFTYPE_STATION;
127 ah->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT;
128 ah->ah_turbo = false;
129 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
130 ah->ah_imr = 0;
131 ah->ah_atim_window = 0;
132 ah->ah_aifs = AR5K_TUNE_AIFS;
133 ah->ah_cw_min = AR5K_TUNE_CWMIN;
134 ah->ah_limit_tx_retries = AR5K_INIT_TX_RETRY;
135 ah->ah_software_retry = false;
136 ah->ah_ant_diversity = AR5K_TUNE_ANT_DIVERSITY;
137
138 /*
139 * Set the mac version based on the pci id
140 */
141 ah->ah_version = mac_version;
142
143 /*Fill the ath5k_hw struct with the needed functions*/
144 ret = ath5k_hw_init_desc_functions(ah);
145 if (ret)
146 goto err_free;
147
148 /* Bring device out of sleep and reset it's units */
149 ret = ath5k_hw_nic_wakeup(ah, CHANNEL_B, true);
150 if (ret)
151 goto err_free;
152
153 /* Get MAC, PHY and RADIO revisions */
154 srev = ath5k_hw_reg_read(ah, AR5K_SREV);
155 ah->ah_mac_srev = srev;
156 ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
157 ah->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV);
158 ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID) &
159 0xffffffff;
160 ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah,
161 CHANNEL_5GHZ);
162 ah->ah_phy = AR5K_PHY(0);
163
164 /* Try to identify radio chip based on it's srev */
165 switch (ah->ah_radio_5ghz_revision & 0xf0) {
166 case AR5K_SREV_RAD_5111:
167 ah->ah_radio = AR5K_RF5111;
168 ah->ah_single_chip = false;
169 ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
170 CHANNEL_2GHZ);
171 break;
172 case AR5K_SREV_RAD_5112:
173 case AR5K_SREV_RAD_2112:
174 ah->ah_radio = AR5K_RF5112;
175 ah->ah_single_chip = false;
176 ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
177 CHANNEL_2GHZ);
178 break;
179 case AR5K_SREV_RAD_2413:
180 ah->ah_radio = AR5K_RF2413;
181 ah->ah_single_chip = true;
182 break;
183 case AR5K_SREV_RAD_5413:
184 ah->ah_radio = AR5K_RF5413;
185 ah->ah_single_chip = true;
186 break;
187 case AR5K_SREV_RAD_2316:
188 ah->ah_radio = AR5K_RF2316;
189 ah->ah_single_chip = true;
190 break;
191 case AR5K_SREV_RAD_2317:
192 ah->ah_radio = AR5K_RF2317;
193 ah->ah_single_chip = true;
194 break;
195 case AR5K_SREV_RAD_5424:
196 if (ah->ah_mac_version == AR5K_SREV_AR2425 ||
197 ah->ah_mac_version == AR5K_SREV_AR2417){
198 ah->ah_radio = AR5K_RF2425;
199 ah->ah_single_chip = true;
200 } else {
201 ah->ah_radio = AR5K_RF5413;
202 ah->ah_single_chip = true;
203 }
204 break;
205 default:
206 /* Identify radio based on mac/phy srev */
207 if (ah->ah_version == AR5K_AR5210) {
208 ah->ah_radio = AR5K_RF5110;
209 ah->ah_single_chip = false;
210 } else if (ah->ah_version == AR5K_AR5211) {
211 ah->ah_radio = AR5K_RF5111;
212 ah->ah_single_chip = false;
213 ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
214 CHANNEL_2GHZ);
215 } else if (ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4) ||
216 ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4) ||
217 ah->ah_phy_revision == AR5K_SREV_PHY_2425) {
218 ah->ah_radio = AR5K_RF2425;
219 ah->ah_single_chip = true;
220 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2425;
221 } else if (srev == AR5K_SREV_AR5213A &&
222 ah->ah_phy_revision == AR5K_SREV_PHY_5212B) {
223 ah->ah_radio = AR5K_RF5112;
224 ah->ah_single_chip = false;
225 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5112B;
226 } else if (ah->ah_mac_version == (AR5K_SREV_AR2415 >> 4)) {
227 ah->ah_radio = AR5K_RF2316;
228 ah->ah_single_chip = true;
229 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2316;
230 } else if (ah->ah_mac_version == (AR5K_SREV_AR5414 >> 4) ||
231 ah->ah_phy_revision == AR5K_SREV_PHY_5413) {
232 ah->ah_radio = AR5K_RF5413;
233 ah->ah_single_chip = true;
234 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5413;
235 } else if (ah->ah_mac_version == (AR5K_SREV_AR2414 >> 4) ||
236 ah->ah_phy_revision == AR5K_SREV_PHY_2413) {
237 ah->ah_radio = AR5K_RF2413;
238 ah->ah_single_chip = true;
239 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2413;
240 } else {
241 ATH5K_ERR(sc, "Couldn't identify radio revision.\n");
242 ret = -ENODEV;
243 goto err_free;
244 }
245 }
246
247
248 /* Return on unsuported chips (unsupported eeprom etc) */
249 if ((srev >= AR5K_SREV_AR5416) &&
250 (srev < AR5K_SREV_AR2425)) {
251 ATH5K_ERR(sc, "Device not yet supported.\n");
252 ret = -ENODEV;
253 goto err_free;
254 }
255
256 /*
257 * Write PCI-E power save settings
258 */
259 if ((ah->ah_version == AR5K_AR5212) && (pdev->is_pcie)) {
260 ath5k_hw_reg_write(ah, 0x9248fc00, AR5K_PCIE_SERDES);
261 ath5k_hw_reg_write(ah, 0x24924924, AR5K_PCIE_SERDES);
262 /* Shut off RX when elecidle is asserted */
263 ath5k_hw_reg_write(ah, 0x28000039, AR5K_PCIE_SERDES);
264 ath5k_hw_reg_write(ah, 0x53160824, AR5K_PCIE_SERDES);
265 /* TODO: EEPROM work */
266 ath5k_hw_reg_write(ah, 0xe5980579, AR5K_PCIE_SERDES);
267 /* Shut off PLL and CLKREQ active in L1 */
268 ath5k_hw_reg_write(ah, 0x001defff, AR5K_PCIE_SERDES);
269 /* Preserce other settings */
270 ath5k_hw_reg_write(ah, 0x1aaabe40, AR5K_PCIE_SERDES);
271 ath5k_hw_reg_write(ah, 0xbe105554, AR5K_PCIE_SERDES);
272 ath5k_hw_reg_write(ah, 0x000e3007, AR5K_PCIE_SERDES);
273 /* Reset SERDES to load new settings */
274 ath5k_hw_reg_write(ah, 0x00000000, AR5K_PCIE_SERDES_RESET);
275 mdelay(1);
276 }
277
278 /*
279 * POST
280 */
281 ret = ath5k_hw_post(ah);
282 if (ret)
283 goto err_free;
284
285 /* Enable pci core retry fix on Hainan (5213A) and later chips */
286 if (srev >= AR5K_SREV_AR5213A)
287 ath5k_hw_reg_write(ah, AR5K_PCICFG_RETRY_FIX, AR5K_PCICFG);
288
289 /*
290 * Get card capabilities, calibration values etc
291 * TODO: EEPROM work
292 */
293 ret = ath5k_eeprom_init(ah);
294 if (ret) {
295 ATH5K_ERR(sc, "unable to init EEPROM\n");
296 goto err_free;
297 }
298
299 /* Get misc capabilities */
300 ret = ath5k_hw_set_capabilities(ah);
301 if (ret) {
302 ATH5K_ERR(sc, "unable to get device capabilities: 0x%04x\n",
303 sc->pdev->device);
304 goto err_free;
305 }
306
307 if (srev >= AR5K_SREV_AR2414) {
308 ah->ah_combined_mic = true;
309 AR5K_REG_ENABLE_BITS(ah, AR5K_MISC_MODE,
310 AR5K_MISC_MODE_COMBINED_MIC);
311 }
312
313 /* MAC address is cleared until add_interface */
314 ath5k_hw_set_lladdr(ah, (u8[ETH_ALEN]){});
315
316 /* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */
317 memset(ah->ah_bssid, 0xff, ETH_ALEN);
318 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
319 ath5k_hw_set_opmode(ah);
320
321 ath5k_hw_rfgain_opt_init(ah);
322
323 return ah;
324err_free:
325 kfree(ah);
326err:
327 return ERR_PTR(ret);
328}
329
330/**
331 * ath5k_hw_detach - Free the ath5k_hw struct
332 *
333 * @ah: The &struct ath5k_hw
334 */
335void ath5k_hw_detach(struct ath5k_hw *ah)
336{
337 ATH5K_TRACE(ah->ah_sc);
338
339 __set_bit(ATH_STAT_INVALID, ah->ah_sc->status);
340
341 if (ah->ah_rf_banks != NULL)
342 kfree(ah->ah_rf_banks);
343
344 ath5k_eeprom_detach(ah);
345
346 /* assume interrupts are down */
347 kfree(ah);
348}
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-05 12:08:09 -0500