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path: root/drivers/net/wireless/ath/ath10k/pci.c
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Diffstat (limited to 'drivers/net/wireless/ath/ath10k/pci.c')
-rw-r--r--drivers/net/wireless/ath/ath10k/pci.c1529
1 files changed, 675 insertions, 854 deletions
diff --git a/drivers/net/wireless/ath/ath10k/pci.c b/drivers/net/wireless/ath/ath10k/pci.c
index 3376963a4862..056a35a77133 100644
--- a/drivers/net/wireless/ath/ath10k/pci.c
+++ b/drivers/net/wireless/ath/ath10k/pci.c
@@ -44,13 +44,9 @@ enum ath10k_pci_reset_mode {
44 ATH10K_PCI_RESET_WARM_ONLY = 1, 44 ATH10K_PCI_RESET_WARM_ONLY = 1,
45}; 45};
46 46
47static unsigned int ath10k_pci_target_ps;
48static unsigned int ath10k_pci_irq_mode = ATH10K_PCI_IRQ_AUTO; 47static unsigned int ath10k_pci_irq_mode = ATH10K_PCI_IRQ_AUTO;
49static unsigned int ath10k_pci_reset_mode = ATH10K_PCI_RESET_AUTO; 48static unsigned int ath10k_pci_reset_mode = ATH10K_PCI_RESET_AUTO;
50 49
51module_param_named(target_ps, ath10k_pci_target_ps, uint, 0644);
52MODULE_PARM_DESC(target_ps, "Enable ath10k Target (SoC) PS option");
53
54module_param_named(irq_mode, ath10k_pci_irq_mode, uint, 0644); 50module_param_named(irq_mode, ath10k_pci_irq_mode, uint, 0644);
55MODULE_PARM_DESC(irq_mode, "0: auto, 1: legacy, 2: msi (default: 0)"); 51MODULE_PARM_DESC(irq_mode, "0: auto, 1: legacy, 2: msi (default: 0)");
56 52
@@ -71,10 +67,7 @@ static const struct pci_device_id ath10k_pci_id_table[] = {
71static int ath10k_pci_diag_read_access(struct ath10k *ar, u32 address, 67static int ath10k_pci_diag_read_access(struct ath10k *ar, u32 address,
72 u32 *data); 68 u32 *data);
73 69
74static int ath10k_pci_post_rx(struct ath10k *ar); 70static void ath10k_pci_buffer_cleanup(struct ath10k *ar);
75static int ath10k_pci_post_rx_pipe(struct ath10k_pci_pipe *pipe_info,
76 int num);
77static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pipe_info);
78static int ath10k_pci_cold_reset(struct ath10k *ar); 71static int ath10k_pci_cold_reset(struct ath10k *ar);
79static int ath10k_pci_warm_reset(struct ath10k *ar); 72static int ath10k_pci_warm_reset(struct ath10k *ar);
80static int ath10k_pci_wait_for_target_init(struct ath10k *ar); 73static int ath10k_pci_wait_for_target_init(struct ath10k *ar);
@@ -156,79 +149,175 @@ static const struct ce_attr host_ce_config_wlan[] = {
156static const struct ce_pipe_config target_ce_config_wlan[] = { 149static const struct ce_pipe_config target_ce_config_wlan[] = {
157 /* CE0: host->target HTC control and raw streams */ 150 /* CE0: host->target HTC control and raw streams */
158 { 151 {
159 .pipenum = 0, 152 .pipenum = __cpu_to_le32(0),
160 .pipedir = PIPEDIR_OUT, 153 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
161 .nentries = 32, 154 .nentries = __cpu_to_le32(32),
162 .nbytes_max = 256, 155 .nbytes_max = __cpu_to_le32(256),
163 .flags = CE_ATTR_FLAGS, 156 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
164 .reserved = 0, 157 .reserved = __cpu_to_le32(0),
165 }, 158 },
166 159
167 /* CE1: target->host HTT + HTC control */ 160 /* CE1: target->host HTT + HTC control */
168 { 161 {
169 .pipenum = 1, 162 .pipenum = __cpu_to_le32(1),
170 .pipedir = PIPEDIR_IN, 163 .pipedir = __cpu_to_le32(PIPEDIR_IN),
171 .nentries = 32, 164 .nentries = __cpu_to_le32(32),
172 .nbytes_max = 512, 165 .nbytes_max = __cpu_to_le32(512),
173 .flags = CE_ATTR_FLAGS, 166 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
174 .reserved = 0, 167 .reserved = __cpu_to_le32(0),
175 }, 168 },
176 169
177 /* CE2: target->host WMI */ 170 /* CE2: target->host WMI */
178 { 171 {
179 .pipenum = 2, 172 .pipenum = __cpu_to_le32(2),
180 .pipedir = PIPEDIR_IN, 173 .pipedir = __cpu_to_le32(PIPEDIR_IN),
181 .nentries = 32, 174 .nentries = __cpu_to_le32(32),
182 .nbytes_max = 2048, 175 .nbytes_max = __cpu_to_le32(2048),
183 .flags = CE_ATTR_FLAGS, 176 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
184 .reserved = 0, 177 .reserved = __cpu_to_le32(0),
185 }, 178 },
186 179
187 /* CE3: host->target WMI */ 180 /* CE3: host->target WMI */
188 { 181 {
189 .pipenum = 3, 182 .pipenum = __cpu_to_le32(3),
190 .pipedir = PIPEDIR_OUT, 183 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
191 .nentries = 32, 184 .nentries = __cpu_to_le32(32),
192 .nbytes_max = 2048, 185 .nbytes_max = __cpu_to_le32(2048),
193 .flags = CE_ATTR_FLAGS, 186 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
194 .reserved = 0, 187 .reserved = __cpu_to_le32(0),
195 }, 188 },
196 189
197 /* CE4: host->target HTT */ 190 /* CE4: host->target HTT */
198 { 191 {
199 .pipenum = 4, 192 .pipenum = __cpu_to_le32(4),
200 .pipedir = PIPEDIR_OUT, 193 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
201 .nentries = 256, 194 .nentries = __cpu_to_le32(256),
202 .nbytes_max = 256, 195 .nbytes_max = __cpu_to_le32(256),
203 .flags = CE_ATTR_FLAGS, 196 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
204 .reserved = 0, 197 .reserved = __cpu_to_le32(0),
205 }, 198 },
206 199
207 /* NB: 50% of src nentries, since tx has 2 frags */ 200 /* NB: 50% of src nentries, since tx has 2 frags */
208 201
209 /* CE5: unused */ 202 /* CE5: unused */
210 { 203 {
211 .pipenum = 5, 204 .pipenum = __cpu_to_le32(5),
212 .pipedir = PIPEDIR_OUT, 205 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
213 .nentries = 32, 206 .nentries = __cpu_to_le32(32),
214 .nbytes_max = 2048, 207 .nbytes_max = __cpu_to_le32(2048),
215 .flags = CE_ATTR_FLAGS, 208 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
216 .reserved = 0, 209 .reserved = __cpu_to_le32(0),
217 }, 210 },
218 211
219 /* CE6: Reserved for target autonomous hif_memcpy */ 212 /* CE6: Reserved for target autonomous hif_memcpy */
220 { 213 {
221 .pipenum = 6, 214 .pipenum = __cpu_to_le32(6),
222 .pipedir = PIPEDIR_INOUT, 215 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
223 .nentries = 32, 216 .nentries = __cpu_to_le32(32),
224 .nbytes_max = 4096, 217 .nbytes_max = __cpu_to_le32(4096),
225 .flags = CE_ATTR_FLAGS, 218 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
226 .reserved = 0, 219 .reserved = __cpu_to_le32(0),
227 }, 220 },
228 221
229 /* CE7 used only by Host */ 222 /* CE7 used only by Host */
230}; 223};
231 224
225/*
226 * Map from service/endpoint to Copy Engine.
227 * This table is derived from the CE_PCI TABLE, above.
228 * It is passed to the Target at startup for use by firmware.
229 */
230static const struct service_to_pipe target_service_to_ce_map_wlan[] = {
231 {
232 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
233 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
234 __cpu_to_le32(3),
235 },
236 {
237 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
238 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
239 __cpu_to_le32(2),
240 },
241 {
242 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK),
243 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
244 __cpu_to_le32(3),
245 },
246 {
247 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK),
248 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
249 __cpu_to_le32(2),
250 },
251 {
252 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE),
253 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
254 __cpu_to_le32(3),
255 },
256 {
257 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE),
258 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
259 __cpu_to_le32(2),
260 },
261 {
262 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI),
263 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
264 __cpu_to_le32(3),
265 },
266 {
267 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI),
268 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
269 __cpu_to_le32(2),
270 },
271 {
272 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL),
273 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
274 __cpu_to_le32(3),
275 },
276 {
277 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL),
278 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
279 __cpu_to_le32(2),
280 },
281 {
282 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL),
283 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
284 __cpu_to_le32(0),
285 },
286 {
287 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL),
288 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
289 __cpu_to_le32(1),
290 },
291 { /* not used */
292 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
293 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
294 __cpu_to_le32(0),
295 },
296 { /* not used */
297 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
298 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
299 __cpu_to_le32(1),
300 },
301 {
302 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG),
303 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
304 __cpu_to_le32(4),
305 },
306 {
307 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG),
308 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
309 __cpu_to_le32(1),
310 },
311
312 /* (Additions here) */
313
314 { /* must be last */
315 __cpu_to_le32(0),
316 __cpu_to_le32(0),
317 __cpu_to_le32(0),
318 },
319};
320
232static bool ath10k_pci_irq_pending(struct ath10k *ar) 321static bool ath10k_pci_irq_pending(struct ath10k *ar)
233{ 322{
234 u32 cause; 323 u32 cause;
@@ -270,44 +359,111 @@ static void ath10k_pci_enable_legacy_irq(struct ath10k *ar)
270 PCIE_INTR_ENABLE_ADDRESS); 359 PCIE_INTR_ENABLE_ADDRESS);
271} 360}
272 361
273static irqreturn_t ath10k_pci_early_irq_handler(int irq, void *arg) 362static inline const char *ath10k_pci_get_irq_method(struct ath10k *ar)
274{ 363{
275 struct ath10k *ar = arg;
276 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 364 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
277 365
278 if (ar_pci->num_msi_intrs == 0) { 366 if (ar_pci->num_msi_intrs > 1)
279 if (!ath10k_pci_irq_pending(ar)) 367 return "msi-x";
280 return IRQ_NONE; 368 else if (ar_pci->num_msi_intrs == 1)
281 369 return "msi";
282 ath10k_pci_disable_and_clear_legacy_irq(ar); 370 else
283 } 371 return "legacy";
284
285 tasklet_schedule(&ar_pci->early_irq_tasklet);
286
287 return IRQ_HANDLED;
288} 372}
289 373
290static int ath10k_pci_request_early_irq(struct ath10k *ar) 374static int __ath10k_pci_rx_post_buf(struct ath10k_pci_pipe *pipe)
291{ 375{
376 struct ath10k *ar = pipe->hif_ce_state;
292 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 377 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
378 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
379 struct sk_buff *skb;
380 dma_addr_t paddr;
293 int ret; 381 int ret;
294 382
295 /* Regardless whether MSI-X/MSI/legacy irqs have been set up the first 383 lockdep_assert_held(&ar_pci->ce_lock);
296 * interrupt from irq vector is triggered in all cases for FW 384
297 * indication/errors */ 385 skb = dev_alloc_skb(pipe->buf_sz);
298 ret = request_irq(ar_pci->pdev->irq, ath10k_pci_early_irq_handler, 386 if (!skb)
299 IRQF_SHARED, "ath10k_pci (early)", ar); 387 return -ENOMEM;
388
389 WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb");
390
391 paddr = dma_map_single(ar->dev, skb->data,
392 skb->len + skb_tailroom(skb),
393 DMA_FROM_DEVICE);
394 if (unlikely(dma_mapping_error(ar->dev, paddr))) {
395 ath10k_warn(ar, "failed to dma map pci rx buf\n");
396 dev_kfree_skb_any(skb);
397 return -EIO;
398 }
399
400 ATH10K_SKB_CB(skb)->paddr = paddr;
401
402 ret = __ath10k_ce_rx_post_buf(ce_pipe, skb, paddr);
300 if (ret) { 403 if (ret) {
301 ath10k_warn("failed to request early irq: %d\n", ret); 404 ath10k_warn(ar, "failed to post pci rx buf: %d\n", ret);
405 dma_unmap_single(ar->dev, paddr, skb->len + skb_tailroom(skb),
406 DMA_FROM_DEVICE);
407 dev_kfree_skb_any(skb);
302 return ret; 408 return ret;
303 } 409 }
304 410
305 return 0; 411 return 0;
306} 412}
307 413
308static void ath10k_pci_free_early_irq(struct ath10k *ar) 414static void __ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe *pipe)
415{
416 struct ath10k *ar = pipe->hif_ce_state;
417 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
418 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
419 int ret, num;
420
421 lockdep_assert_held(&ar_pci->ce_lock);
422
423 if (pipe->buf_sz == 0)
424 return;
425
426 if (!ce_pipe->dest_ring)
427 return;
428
429 num = __ath10k_ce_rx_num_free_bufs(ce_pipe);
430 while (num--) {
431 ret = __ath10k_pci_rx_post_buf(pipe);
432 if (ret) {
433 ath10k_warn(ar, "failed to post pci rx buf: %d\n", ret);
434 mod_timer(&ar_pci->rx_post_retry, jiffies +
435 ATH10K_PCI_RX_POST_RETRY_MS);
436 break;
437 }
438 }
439}
440
441static void ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe *pipe)
442{
443 struct ath10k *ar = pipe->hif_ce_state;
444 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
445
446 spin_lock_bh(&ar_pci->ce_lock);
447 __ath10k_pci_rx_post_pipe(pipe);
448 spin_unlock_bh(&ar_pci->ce_lock);
449}
450
451static void ath10k_pci_rx_post(struct ath10k *ar)
452{
453 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
454 int i;
455
456 spin_lock_bh(&ar_pci->ce_lock);
457 for (i = 0; i < CE_COUNT; i++)
458 __ath10k_pci_rx_post_pipe(&ar_pci->pipe_info[i]);
459 spin_unlock_bh(&ar_pci->ce_lock);
460}
461
462static void ath10k_pci_rx_replenish_retry(unsigned long ptr)
309{ 463{
310 free_irq(ath10k_pci_priv(ar)->pdev->irq, ar); 464 struct ath10k *ar = (void *)ptr;
465
466 ath10k_pci_rx_post(ar);
311} 467}
312 468
313/* 469/*
@@ -376,7 +532,7 @@ static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data,
376 nbytes = min_t(unsigned int, remaining_bytes, 532 nbytes = min_t(unsigned int, remaining_bytes,
377 DIAG_TRANSFER_LIMIT); 533 DIAG_TRANSFER_LIMIT);
378 534
379 ret = ath10k_ce_recv_buf_enqueue(ce_diag, NULL, ce_data); 535 ret = ath10k_ce_rx_post_buf(ce_diag, NULL, ce_data);
380 if (ret != 0) 536 if (ret != 0)
381 goto done; 537 goto done;
382 538
@@ -389,10 +545,8 @@ static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data,
389 * convert it from Target CPU virtual address space 545 * convert it from Target CPU virtual address space
390 * to CE address space 546 * to CE address space
391 */ 547 */
392 ath10k_pci_wake(ar);
393 address = TARG_CPU_SPACE_TO_CE_SPACE(ar, ar_pci->mem, 548 address = TARG_CPU_SPACE_TO_CE_SPACE(ar, ar_pci->mem,
394 address); 549 address);
395 ath10k_pci_sleep(ar);
396 550
397 ret = ath10k_ce_send(ce_diag, NULL, (u32)address, nbytes, 0, 551 ret = ath10k_ce_send(ce_diag, NULL, (u32)address, nbytes, 0,
398 0); 552 0);
@@ -448,15 +602,10 @@ static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data,
448 } 602 }
449 603
450done: 604done:
451 if (ret == 0) { 605 if (ret == 0)
452 /* Copy data from allocated DMA buf to caller's buf */ 606 memcpy(data, data_buf, orig_nbytes);
453 WARN_ON_ONCE(orig_nbytes & 3); 607 else
454 for (i = 0; i < orig_nbytes / sizeof(__le32); i++) { 608 ath10k_warn(ar, "failed to read diag value at 0x%x: %d\n",
455 ((u32 *)data)[i] =
456 __le32_to_cpu(((__le32 *)data_buf)[i]);
457 }
458 } else
459 ath10k_warn("failed to read diag value at 0x%x: %d\n",
460 address, ret); 609 address, ret);
461 610
462 if (data_buf) 611 if (data_buf)
@@ -466,17 +615,54 @@ done:
466 return ret; 615 return ret;
467} 616}
468 617
618static int ath10k_pci_diag_read32(struct ath10k *ar, u32 address, u32 *value)
619{
620 __le32 val = 0;
621 int ret;
622
623 ret = ath10k_pci_diag_read_mem(ar, address, &val, sizeof(val));
624 *value = __le32_to_cpu(val);
625
626 return ret;
627}
628
629static int __ath10k_pci_diag_read_hi(struct ath10k *ar, void *dest,
630 u32 src, u32 len)
631{
632 u32 host_addr, addr;
633 int ret;
634
635 host_addr = host_interest_item_address(src);
636
637 ret = ath10k_pci_diag_read32(ar, host_addr, &addr);
638 if (ret != 0) {
639 ath10k_warn(ar, "failed to get memcpy hi address for firmware address %d: %d\n",
640 src, ret);
641 return ret;
642 }
643
644 ret = ath10k_pci_diag_read_mem(ar, addr, dest, len);
645 if (ret != 0) {
646 ath10k_warn(ar, "failed to memcpy firmware memory from %d (%d B): %d\n",
647 addr, len, ret);
648 return ret;
649 }
650
651 return 0;
652}
653
654#define ath10k_pci_diag_read_hi(ar, dest, src, len) \
655 __ath10k_pci_diag_read_hi(ar, dest, HI_ITEM(src), len);
656
469/* Read 4-byte aligned data from Target memory or register */ 657/* Read 4-byte aligned data from Target memory or register */
470static int ath10k_pci_diag_read_access(struct ath10k *ar, u32 address, 658static int ath10k_pci_diag_read_access(struct ath10k *ar, u32 address,
471 u32 *data) 659 u32 *data)
472{ 660{
473 /* Assume range doesn't cross this boundary */ 661 /* Assume range doesn't cross this boundary */
474 if (address >= DRAM_BASE_ADDRESS) 662 if (address >= DRAM_BASE_ADDRESS)
475 return ath10k_pci_diag_read_mem(ar, address, data, sizeof(u32)); 663 return ath10k_pci_diag_read32(ar, address, data);
476 664
477 ath10k_pci_wake(ar);
478 *data = ath10k_pci_read32(ar, address); 665 *data = ath10k_pci_read32(ar, address);
479 ath10k_pci_sleep(ar);
480 return 0; 666 return 0;
481} 667}
482 668
@@ -514,9 +700,7 @@ static int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address,
514 } 700 }
515 701
516 /* Copy caller's data to allocated DMA buf */ 702 /* Copy caller's data to allocated DMA buf */
517 WARN_ON_ONCE(orig_nbytes & 3); 703 memcpy(data_buf, data, orig_nbytes);
518 for (i = 0; i < orig_nbytes / sizeof(__le32); i++)
519 ((__le32 *)data_buf)[i] = __cpu_to_le32(((u32 *)data)[i]);
520 704
521 /* 705 /*
522 * The address supplied by the caller is in the 706 * The address supplied by the caller is in the
@@ -528,9 +712,7 @@ static int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address,
528 * to 712 * to
529 * CE address space 713 * CE address space
530 */ 714 */
531 ath10k_pci_wake(ar);
532 address = TARG_CPU_SPACE_TO_CE_SPACE(ar, ar_pci->mem, address); 715 address = TARG_CPU_SPACE_TO_CE_SPACE(ar, ar_pci->mem, address);
533 ath10k_pci_sleep(ar);
534 716
535 remaining_bytes = orig_nbytes; 717 remaining_bytes = orig_nbytes;
536 ce_data = ce_data_base; 718 ce_data = ce_data_base;
@@ -539,7 +721,7 @@ static int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address,
539 nbytes = min_t(int, remaining_bytes, DIAG_TRANSFER_LIMIT); 721 nbytes = min_t(int, remaining_bytes, DIAG_TRANSFER_LIMIT);
540 722
541 /* Set up to receive directly into Target(!) address */ 723 /* Set up to receive directly into Target(!) address */
542 ret = ath10k_ce_recv_buf_enqueue(ce_diag, NULL, address); 724 ret = ath10k_ce_rx_post_buf(ce_diag, NULL, address);
543 if (ret != 0) 725 if (ret != 0)
544 goto done; 726 goto done;
545 727
@@ -608,66 +790,46 @@ done:
608 } 790 }
609 791
610 if (ret != 0) 792 if (ret != 0)
611 ath10k_warn("failed to write diag value at 0x%x: %d\n", 793 ath10k_warn(ar, "failed to write diag value at 0x%x: %d\n",
612 address, ret); 794 address, ret);
613 795
614 return ret; 796 return ret;
615} 797}
616 798
799static int ath10k_pci_diag_write32(struct ath10k *ar, u32 address, u32 value)
800{
801 __le32 val = __cpu_to_le32(value);
802
803 return ath10k_pci_diag_write_mem(ar, address, &val, sizeof(val));
804}
805
617/* Write 4B data to Target memory or register */ 806/* Write 4B data to Target memory or register */
618static int ath10k_pci_diag_write_access(struct ath10k *ar, u32 address, 807static int ath10k_pci_diag_write_access(struct ath10k *ar, u32 address,
619 u32 data) 808 u32 data)
620{ 809{
621 /* Assume range doesn't cross this boundary */ 810 /* Assume range doesn't cross this boundary */
622 if (address >= DRAM_BASE_ADDRESS) 811 if (address >= DRAM_BASE_ADDRESS)
623 return ath10k_pci_diag_write_mem(ar, address, &data, 812 return ath10k_pci_diag_write32(ar, address, data);
624 sizeof(u32));
625 813
626 ath10k_pci_wake(ar);
627 ath10k_pci_write32(ar, address, data); 814 ath10k_pci_write32(ar, address, data);
628 ath10k_pci_sleep(ar);
629 return 0; 815 return 0;
630} 816}
631 817
632static bool ath10k_pci_target_is_awake(struct ath10k *ar) 818static bool ath10k_pci_is_awake(struct ath10k *ar)
633{ 819{
634 void __iomem *mem = ath10k_pci_priv(ar)->mem; 820 u32 val = ath10k_pci_reg_read32(ar, RTC_STATE_ADDRESS);
635 u32 val; 821
636 val = ioread32(mem + PCIE_LOCAL_BASE_ADDRESS + 822 return RTC_STATE_V_GET(val) == RTC_STATE_V_ON;
637 RTC_STATE_ADDRESS);
638 return (RTC_STATE_V_GET(val) == RTC_STATE_V_ON);
639} 823}
640 824
641int ath10k_do_pci_wake(struct ath10k *ar) 825static int ath10k_pci_wake_wait(struct ath10k *ar)
642{ 826{
643 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
644 void __iomem *pci_addr = ar_pci->mem;
645 int tot_delay = 0; 827 int tot_delay = 0;
646 int curr_delay = 5; 828 int curr_delay = 5;
647 829
648 if (atomic_read(&ar_pci->keep_awake_count) == 0) { 830 while (tot_delay < PCIE_WAKE_TIMEOUT) {
649 /* Force AWAKE */ 831 if (ath10k_pci_is_awake(ar))
650 iowrite32(PCIE_SOC_WAKE_V_MASK,
651 pci_addr + PCIE_LOCAL_BASE_ADDRESS +
652 PCIE_SOC_WAKE_ADDRESS);
653 }
654 atomic_inc(&ar_pci->keep_awake_count);
655
656 if (ar_pci->verified_awake)
657 return 0;
658
659 for (;;) {
660 if (ath10k_pci_target_is_awake(ar)) {
661 ar_pci->verified_awake = true;
662 return 0; 832 return 0;
663 }
664
665 if (tot_delay > PCIE_WAKE_TIMEOUT) {
666 ath10k_warn("target took longer %d us to wake up (awake count %d)\n",
667 PCIE_WAKE_TIMEOUT,
668 atomic_read(&ar_pci->keep_awake_count));
669 return -ETIMEDOUT;
670 }
671 833
672 udelay(curr_delay); 834 udelay(curr_delay);
673 tot_delay += curr_delay; 835 tot_delay += curr_delay;
@@ -675,20 +837,21 @@ int ath10k_do_pci_wake(struct ath10k *ar)
675 if (curr_delay < 50) 837 if (curr_delay < 50)
676 curr_delay += 5; 838 curr_delay += 5;
677 } 839 }
840
841 return -ETIMEDOUT;
678} 842}
679 843
680void ath10k_do_pci_sleep(struct ath10k *ar) 844static int ath10k_pci_wake(struct ath10k *ar)
681{ 845{
682 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 846 ath10k_pci_reg_write32(ar, PCIE_SOC_WAKE_ADDRESS,
683 void __iomem *pci_addr = ar_pci->mem; 847 PCIE_SOC_WAKE_V_MASK);
848 return ath10k_pci_wake_wait(ar);
849}
684 850
685 if (atomic_dec_and_test(&ar_pci->keep_awake_count)) { 851static void ath10k_pci_sleep(struct ath10k *ar)
686 /* Allow sleep */ 852{
687 ar_pci->verified_awake = false; 853 ath10k_pci_reg_write32(ar, PCIE_SOC_WAKE_ADDRESS,
688 iowrite32(PCIE_SOC_WAKE_RESET, 854 PCIE_SOC_WAKE_RESET);
689 pci_addr + PCIE_LOCAL_BASE_ADDRESS +
690 PCIE_SOC_WAKE_ADDRESS);
691 }
692} 855}
693 856
694/* Called by lower (CE) layer when a send to Target completes. */ 857/* Called by lower (CE) layer when a send to Target completes. */
@@ -726,19 +889,17 @@ static void ath10k_pci_ce_recv_data(struct ath10k_ce_pipe *ce_state)
726 unsigned int nbytes, max_nbytes; 889 unsigned int nbytes, max_nbytes;
727 unsigned int transfer_id; 890 unsigned int transfer_id;
728 unsigned int flags; 891 unsigned int flags;
729 int err, num_replenish = 0;
730 892
731 while (ath10k_ce_completed_recv_next(ce_state, &transfer_context, 893 while (ath10k_ce_completed_recv_next(ce_state, &transfer_context,
732 &ce_data, &nbytes, &transfer_id, 894 &ce_data, &nbytes, &transfer_id,
733 &flags) == 0) { 895 &flags) == 0) {
734 num_replenish++;
735 skb = transfer_context; 896 skb = transfer_context;
736 max_nbytes = skb->len + skb_tailroom(skb); 897 max_nbytes = skb->len + skb_tailroom(skb);
737 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr, 898 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr,
738 max_nbytes, DMA_FROM_DEVICE); 899 max_nbytes, DMA_FROM_DEVICE);
739 900
740 if (unlikely(max_nbytes < nbytes)) { 901 if (unlikely(max_nbytes < nbytes)) {
741 ath10k_warn("rxed more than expected (nbytes %d, max %d)", 902 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)",
742 nbytes, max_nbytes); 903 nbytes, max_nbytes);
743 dev_kfree_skb_any(skb); 904 dev_kfree_skb_any(skb);
744 continue; 905 continue;
@@ -748,12 +909,7 @@ static void ath10k_pci_ce_recv_data(struct ath10k_ce_pipe *ce_state)
748 cb->rx_completion(ar, skb, pipe_info->pipe_num); 909 cb->rx_completion(ar, skb, pipe_info->pipe_num);
749 } 910 }
750 911
751 err = ath10k_pci_post_rx_pipe(pipe_info, num_replenish); 912 ath10k_pci_rx_post_pipe(pipe_info);
752 if (unlikely(err)) {
753 /* FIXME: retry */
754 ath10k_warn("failed to replenish CE rx ring %d (%d bufs): %d\n",
755 pipe_info->pipe_num, num_replenish, err);
756 }
757} 913}
758 914
759static int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id, 915static int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
@@ -781,10 +937,10 @@ static int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
781 } 937 }
782 938
783 for (i = 0; i < n_items - 1; i++) { 939 for (i = 0; i < n_items - 1; i++) {
784 ath10k_dbg(ATH10K_DBG_PCI, 940 ath10k_dbg(ar, ATH10K_DBG_PCI,
785 "pci tx item %d paddr 0x%08x len %d n_items %d\n", 941 "pci tx item %d paddr 0x%08x len %d n_items %d\n",
786 i, items[i].paddr, items[i].len, n_items); 942 i, items[i].paddr, items[i].len, n_items);
787 ath10k_dbg_dump(ATH10K_DBG_PCI_DUMP, NULL, "item data: ", 943 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ",
788 items[i].vaddr, items[i].len); 944 items[i].vaddr, items[i].len);
789 945
790 err = ath10k_ce_send_nolock(ce_pipe, 946 err = ath10k_ce_send_nolock(ce_pipe,
@@ -799,10 +955,10 @@ static int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
799 955
800 /* `i` is equal to `n_items -1` after for() */ 956 /* `i` is equal to `n_items -1` after for() */
801 957
802 ath10k_dbg(ATH10K_DBG_PCI, 958 ath10k_dbg(ar, ATH10K_DBG_PCI,
803 "pci tx item %d paddr 0x%08x len %d n_items %d\n", 959 "pci tx item %d paddr 0x%08x len %d n_items %d\n",
804 i, items[i].paddr, items[i].len, n_items); 960 i, items[i].paddr, items[i].len, n_items);
805 ath10k_dbg_dump(ATH10K_DBG_PCI_DUMP, NULL, "item data: ", 961 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ",
806 items[i].vaddr, items[i].len); 962 items[i].vaddr, items[i].len);
807 963
808 err = ath10k_ce_send_nolock(ce_pipe, 964 err = ath10k_ce_send_nolock(ce_pipe,
@@ -829,52 +985,64 @@ static u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe)
829{ 985{
830 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 986 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
831 987
832 ath10k_dbg(ATH10K_DBG_PCI, "pci hif get free queue number\n"); 988 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get free queue number\n");
833 989
834 return ath10k_ce_num_free_src_entries(ar_pci->pipe_info[pipe].ce_hdl); 990 return ath10k_ce_num_free_src_entries(ar_pci->pipe_info[pipe].ce_hdl);
835} 991}
836 992
837static void ath10k_pci_hif_dump_area(struct ath10k *ar) 993static void ath10k_pci_dump_registers(struct ath10k *ar,
994 struct ath10k_fw_crash_data *crash_data)
838{ 995{
839 u32 reg_dump_area = 0; 996 __le32 reg_dump_values[REG_DUMP_COUNT_QCA988X] = {};
840 u32 reg_dump_values[REG_DUMP_COUNT_QCA988X] = {}; 997 int i, ret;
841 u32 host_addr;
842 int ret;
843 u32 i;
844 998
845 ath10k_err("firmware crashed!\n"); 999 lockdep_assert_held(&ar->data_lock);
846 ath10k_err("hardware name %s version 0x%x\n",
847 ar->hw_params.name, ar->target_version);
848 ath10k_err("firmware version: %s\n", ar->hw->wiphy->fw_version);
849 1000
850 host_addr = host_interest_item_address(HI_ITEM(hi_failure_state)); 1001 ret = ath10k_pci_diag_read_hi(ar, &reg_dump_values[0],
851 ret = ath10k_pci_diag_read_mem(ar, host_addr, 1002 hi_failure_state,
852 &reg_dump_area, sizeof(u32)); 1003 REG_DUMP_COUNT_QCA988X * sizeof(__le32));
853 if (ret) { 1004 if (ret) {
854 ath10k_err("failed to read FW dump area address: %d\n", ret); 1005 ath10k_err(ar, "failed to read firmware dump area: %d\n", ret);
855 return;
856 }
857
858 ath10k_err("target register Dump Location: 0x%08X\n", reg_dump_area);
859
860 ret = ath10k_pci_diag_read_mem(ar, reg_dump_area,
861 &reg_dump_values[0],
862 REG_DUMP_COUNT_QCA988X * sizeof(u32));
863 if (ret != 0) {
864 ath10k_err("failed to read FW dump area: %d\n", ret);
865 return; 1006 return;
866 } 1007 }
867 1008
868 BUILD_BUG_ON(REG_DUMP_COUNT_QCA988X % 4); 1009 BUILD_BUG_ON(REG_DUMP_COUNT_QCA988X % 4);
869 1010
870 ath10k_err("target Register Dump\n"); 1011 ath10k_err(ar, "firmware register dump:\n");
871 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i += 4) 1012 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i += 4)
872 ath10k_err("[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n", 1013 ath10k_err(ar, "[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n",
873 i, 1014 i,
874 reg_dump_values[i], 1015 __le32_to_cpu(reg_dump_values[i]),
875 reg_dump_values[i + 1], 1016 __le32_to_cpu(reg_dump_values[i + 1]),
876 reg_dump_values[i + 2], 1017 __le32_to_cpu(reg_dump_values[i + 2]),
877 reg_dump_values[i + 3]); 1018 __le32_to_cpu(reg_dump_values[i + 3]));
1019
1020 if (!crash_data)
1021 return;
1022
1023 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i++)
1024 crash_data->registers[i] = reg_dump_values[i];
1025}
1026
1027static void ath10k_pci_fw_crashed_dump(struct ath10k *ar)
1028{
1029 struct ath10k_fw_crash_data *crash_data;
1030 char uuid[50];
1031
1032 spin_lock_bh(&ar->data_lock);
1033
1034 crash_data = ath10k_debug_get_new_fw_crash_data(ar);
1035
1036 if (crash_data)
1037 scnprintf(uuid, sizeof(uuid), "%pUl", &crash_data->uuid);
1038 else
1039 scnprintf(uuid, sizeof(uuid), "n/a");
1040
1041 ath10k_err(ar, "firmware crashed! (uuid %s)\n", uuid);
1042 ath10k_print_driver_info(ar);
1043 ath10k_pci_dump_registers(ar, crash_data);
1044
1045 spin_unlock_bh(&ar->data_lock);
878 1046
879 queue_work(ar->workqueue, &ar->restart_work); 1047 queue_work(ar->workqueue, &ar->restart_work);
880} 1048}
@@ -882,7 +1050,7 @@ static void ath10k_pci_hif_dump_area(struct ath10k *ar)
882static void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe, 1050static void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe,
883 int force) 1051 int force)
884{ 1052{
885 ath10k_dbg(ATH10K_DBG_PCI, "pci hif send complete check\n"); 1053 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif send complete check\n");
886 1054
887 if (!force) { 1055 if (!force) {
888 int resources; 1056 int resources;
@@ -910,43 +1078,12 @@ static void ath10k_pci_hif_set_callbacks(struct ath10k *ar,
910{ 1078{
911 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1079 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
912 1080
913 ath10k_dbg(ATH10K_DBG_PCI, "pci hif set callbacks\n"); 1081 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif set callbacks\n");
914 1082
915 memcpy(&ar_pci->msg_callbacks_current, callbacks, 1083 memcpy(&ar_pci->msg_callbacks_current, callbacks,
916 sizeof(ar_pci->msg_callbacks_current)); 1084 sizeof(ar_pci->msg_callbacks_current));
917} 1085}
918 1086
919static int ath10k_pci_setup_ce_irq(struct ath10k *ar)
920{
921 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
922 const struct ce_attr *attr;
923 struct ath10k_pci_pipe *pipe_info;
924 int pipe_num, disable_interrupts;
925
926 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
927 pipe_info = &ar_pci->pipe_info[pipe_num];
928
929 /* Handle Diagnostic CE specially */
930 if (pipe_info->ce_hdl == ar_pci->ce_diag)
931 continue;
932
933 attr = &host_ce_config_wlan[pipe_num];
934
935 if (attr->src_nentries) {
936 disable_interrupts = attr->flags & CE_ATTR_DIS_INTR;
937 ath10k_ce_send_cb_register(pipe_info->ce_hdl,
938 ath10k_pci_ce_send_done,
939 disable_interrupts);
940 }
941
942 if (attr->dest_nentries)
943 ath10k_ce_recv_cb_register(pipe_info->ce_hdl,
944 ath10k_pci_ce_recv_data);
945 }
946
947 return 0;
948}
949
950static void ath10k_pci_kill_tasklet(struct ath10k *ar) 1087static void ath10k_pci_kill_tasklet(struct ath10k *ar)
951{ 1088{
952 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1089 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
@@ -954,74 +1091,64 @@ static void ath10k_pci_kill_tasklet(struct ath10k *ar)
954 1091
955 tasklet_kill(&ar_pci->intr_tq); 1092 tasklet_kill(&ar_pci->intr_tq);
956 tasklet_kill(&ar_pci->msi_fw_err); 1093 tasklet_kill(&ar_pci->msi_fw_err);
957 tasklet_kill(&ar_pci->early_irq_tasklet);
958 1094
959 for (i = 0; i < CE_COUNT; i++) 1095 for (i = 0; i < CE_COUNT; i++)
960 tasklet_kill(&ar_pci->pipe_info[i].intr); 1096 tasklet_kill(&ar_pci->pipe_info[i].intr);
1097
1098 del_timer_sync(&ar_pci->rx_post_retry);
961} 1099}
962 1100
963/* TODO - temporary mapping while we have too few CE's */
964static int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar, 1101static int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar,
965 u16 service_id, u8 *ul_pipe, 1102 u16 service_id, u8 *ul_pipe,
966 u8 *dl_pipe, int *ul_is_polled, 1103 u8 *dl_pipe, int *ul_is_polled,
967 int *dl_is_polled) 1104 int *dl_is_polled)
968{ 1105{
969 int ret = 0; 1106 const struct service_to_pipe *entry;
1107 bool ul_set = false, dl_set = false;
1108 int i;
970 1109
971 ath10k_dbg(ATH10K_DBG_PCI, "pci hif map service\n"); 1110 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif map service\n");
972 1111
973 /* polling for received messages not supported */ 1112 /* polling for received messages not supported */
974 *dl_is_polled = 0; 1113 *dl_is_polled = 0;
975 1114
976 switch (service_id) { 1115 for (i = 0; i < ARRAY_SIZE(target_service_to_ce_map_wlan); i++) {
977 case ATH10K_HTC_SVC_ID_HTT_DATA_MSG: 1116 entry = &target_service_to_ce_map_wlan[i];
978 /*
979 * Host->target HTT gets its own pipe, so it can be polled
980 * while other pipes are interrupt driven.
981 */
982 *ul_pipe = 4;
983 /*
984 * Use the same target->host pipe for HTC ctrl, HTC raw
985 * streams, and HTT.
986 */
987 *dl_pipe = 1;
988 break;
989 1117
990 case ATH10K_HTC_SVC_ID_RSVD_CTRL: 1118 if (__le32_to_cpu(entry->service_id) != service_id)
991 case ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS: 1119 continue;
992 /*
993 * Note: HTC_RAW_STREAMS_SVC is currently unused, and
994 * HTC_CTRL_RSVD_SVC could share the same pipe as the
995 * WMI services. So, if another CE is needed, change
996 * this to *ul_pipe = 3, which frees up CE 0.
997 */
998 /* *ul_pipe = 3; */
999 *ul_pipe = 0;
1000 *dl_pipe = 1;
1001 break;
1002
1003 case ATH10K_HTC_SVC_ID_WMI_DATA_BK:
1004 case ATH10K_HTC_SVC_ID_WMI_DATA_BE:
1005 case ATH10K_HTC_SVC_ID_WMI_DATA_VI:
1006 case ATH10K_HTC_SVC_ID_WMI_DATA_VO:
1007 1120
1008 case ATH10K_HTC_SVC_ID_WMI_CONTROL: 1121 switch (__le32_to_cpu(entry->pipedir)) {
1009 *ul_pipe = 3; 1122 case PIPEDIR_NONE:
1010 *dl_pipe = 2; 1123 break;
1011 break; 1124 case PIPEDIR_IN:
1125 WARN_ON(dl_set);
1126 *dl_pipe = __le32_to_cpu(entry->pipenum);
1127 dl_set = true;
1128 break;
1129 case PIPEDIR_OUT:
1130 WARN_ON(ul_set);
1131 *ul_pipe = __le32_to_cpu(entry->pipenum);
1132 ul_set = true;
1133 break;
1134 case PIPEDIR_INOUT:
1135 WARN_ON(dl_set);
1136 WARN_ON(ul_set);
1137 *dl_pipe = __le32_to_cpu(entry->pipenum);
1138 *ul_pipe = __le32_to_cpu(entry->pipenum);
1139 dl_set = true;
1140 ul_set = true;
1141 break;
1142 }
1143 }
1012 1144
1013 /* pipe 5 unused */ 1145 if (WARN_ON(!ul_set || !dl_set))
1014 /* pipe 6 reserved */ 1146 return -ENOENT;
1015 /* pipe 7 reserved */
1016 1147
1017 default:
1018 ret = -1;
1019 break;
1020 }
1021 *ul_is_polled = 1148 *ul_is_polled =
1022 (host_ce_config_wlan[*ul_pipe].flags & CE_ATTR_DIS_INTR) != 0; 1149 (host_ce_config_wlan[*ul_pipe].flags & CE_ATTR_DIS_INTR) != 0;
1023 1150
1024 return ret; 1151 return 0;
1025} 1152}
1026 1153
1027static void ath10k_pci_hif_get_default_pipe(struct ath10k *ar, 1154static void ath10k_pci_hif_get_default_pipe(struct ath10k *ar,
@@ -1029,7 +1156,7 @@ static void ath10k_pci_hif_get_default_pipe(struct ath10k *ar,
1029{ 1156{
1030 int ul_is_polled, dl_is_polled; 1157 int ul_is_polled, dl_is_polled;
1031 1158
1032 ath10k_dbg(ATH10K_DBG_PCI, "pci hif get default pipe\n"); 1159 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get default pipe\n");
1033 1160
1034 (void)ath10k_pci_hif_map_service_to_pipe(ar, 1161 (void)ath10k_pci_hif_map_service_to_pipe(ar,
1035 ATH10K_HTC_SVC_ID_RSVD_CTRL, 1162 ATH10K_HTC_SVC_ID_RSVD_CTRL,
@@ -1039,141 +1166,48 @@ static void ath10k_pci_hif_get_default_pipe(struct ath10k *ar,
1039 &dl_is_polled); 1166 &dl_is_polled);
1040} 1167}
1041 1168
1042static int ath10k_pci_post_rx_pipe(struct ath10k_pci_pipe *pipe_info, 1169static void ath10k_pci_irq_disable(struct ath10k *ar)
1043 int num)
1044{ 1170{
1045 struct ath10k *ar = pipe_info->hif_ce_state;
1046 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1171 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1047 struct ath10k_ce_pipe *ce_state = pipe_info->ce_hdl; 1172 int i;
1048 struct sk_buff *skb;
1049 dma_addr_t ce_data;
1050 int i, ret = 0;
1051
1052 if (pipe_info->buf_sz == 0)
1053 return 0;
1054
1055 for (i = 0; i < num; i++) {
1056 skb = dev_alloc_skb(pipe_info->buf_sz);
1057 if (!skb) {
1058 ath10k_warn("failed to allocate skbuff for pipe %d\n",
1059 num);
1060 ret = -ENOMEM;
1061 goto err;
1062 }
1063
1064 WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb");
1065
1066 ce_data = dma_map_single(ar->dev, skb->data,
1067 skb->len + skb_tailroom(skb),
1068 DMA_FROM_DEVICE);
1069
1070 if (unlikely(dma_mapping_error(ar->dev, ce_data))) {
1071 ath10k_warn("failed to DMA map sk_buff\n");
1072 dev_kfree_skb_any(skb);
1073 ret = -EIO;
1074 goto err;
1075 }
1076
1077 ATH10K_SKB_CB(skb)->paddr = ce_data;
1078
1079 pci_dma_sync_single_for_device(ar_pci->pdev, ce_data,
1080 pipe_info->buf_sz,
1081 PCI_DMA_FROMDEVICE);
1082 1173
1083 ret = ath10k_ce_recv_buf_enqueue(ce_state, (void *)skb, 1174 ath10k_ce_disable_interrupts(ar);
1084 ce_data);
1085 if (ret) {
1086 ath10k_warn("failed to enqueue to pipe %d: %d\n",
1087 num, ret);
1088 goto err;
1089 }
1090 }
1091 1175
1092 return ret; 1176 /* Regardless how many interrupts were assigned for MSI the first one
1177 * is always used for firmware indications (crashes). There's no way to
1178 * mask the irq in the device so call disable_irq(). Legacy (shared)
1179 * interrupts can be masked on the device though.
1180 */
1181 if (ar_pci->num_msi_intrs > 0)
1182 disable_irq(ar_pci->pdev->irq);
1183 else
1184 ath10k_pci_disable_and_clear_legacy_irq(ar);
1093 1185
1094err: 1186 for (i = 0; i < max(1, ar_pci->num_msi_intrs); i++)
1095 ath10k_pci_rx_pipe_cleanup(pipe_info); 1187 synchronize_irq(ar_pci->pdev->irq + i);
1096 return ret;
1097} 1188}
1098 1189
1099static int ath10k_pci_post_rx(struct ath10k *ar) 1190static void ath10k_pci_irq_enable(struct ath10k *ar)
1100{ 1191{
1101 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1192 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1102 struct ath10k_pci_pipe *pipe_info;
1103 const struct ce_attr *attr;
1104 int pipe_num, ret = 0;
1105 1193
1106 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) { 1194 ath10k_ce_enable_interrupts(ar);
1107 pipe_info = &ar_pci->pipe_info[pipe_num];
1108 attr = &host_ce_config_wlan[pipe_num];
1109
1110 if (attr->dest_nentries == 0)
1111 continue;
1112
1113 ret = ath10k_pci_post_rx_pipe(pipe_info,
1114 attr->dest_nentries - 1);
1115 if (ret) {
1116 ath10k_warn("failed to post RX buffer for pipe %d: %d\n",
1117 pipe_num, ret);
1118
1119 for (; pipe_num >= 0; pipe_num--) {
1120 pipe_info = &ar_pci->pipe_info[pipe_num];
1121 ath10k_pci_rx_pipe_cleanup(pipe_info);
1122 }
1123 return ret;
1124 }
1125 }
1126 1195
1127 return 0; 1196 /* See comment in ath10k_pci_irq_disable() */
1197 if (ar_pci->num_msi_intrs > 0)
1198 enable_irq(ar_pci->pdev->irq);
1199 else
1200 ath10k_pci_enable_legacy_irq(ar);
1128} 1201}
1129 1202
1130static int ath10k_pci_hif_start(struct ath10k *ar) 1203static int ath10k_pci_hif_start(struct ath10k *ar)
1131{ 1204{
1132 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1205 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif start\n");
1133 int ret, ret_early;
1134
1135 ath10k_dbg(ATH10K_DBG_BOOT, "boot hif start\n");
1136
1137 ath10k_pci_free_early_irq(ar);
1138 ath10k_pci_kill_tasklet(ar);
1139
1140 ret = ath10k_pci_request_irq(ar);
1141 if (ret) {
1142 ath10k_warn("failed to post RX buffers for all pipes: %d\n",
1143 ret);
1144 goto err_early_irq;
1145 }
1146
1147 ret = ath10k_pci_setup_ce_irq(ar);
1148 if (ret) {
1149 ath10k_warn("failed to setup CE interrupts: %d\n", ret);
1150 goto err_stop;
1151 }
1152 1206
1153 /* Post buffers once to start things off. */ 1207 ath10k_pci_irq_enable(ar);
1154 ret = ath10k_pci_post_rx(ar); 1208 ath10k_pci_rx_post(ar);
1155 if (ret) {
1156 ath10k_warn("failed to post RX buffers for all pipes: %d\n",
1157 ret);
1158 goto err_stop;
1159 }
1160 1209
1161 ar_pci->started = 1;
1162 return 0; 1210 return 0;
1163
1164err_stop:
1165 ath10k_ce_disable_interrupts(ar);
1166 ath10k_pci_free_irq(ar);
1167 ath10k_pci_kill_tasklet(ar);
1168err_early_irq:
1169 /* Though there should be no interrupts (device was reset)
1170 * power_down() expects the early IRQ to be installed as per the
1171 * driver lifecycle. */
1172 ret_early = ath10k_pci_request_early_irq(ar);
1173 if (ret_early)
1174 ath10k_warn("failed to re-enable early irq: %d\n", ret_early);
1175
1176 return ret;
1177} 1211}
1178 1212
1179static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pipe_info) 1213static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pipe_info)
@@ -1193,10 +1227,6 @@ static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pipe_info)
1193 1227
1194 ar = pipe_info->hif_ce_state; 1228 ar = pipe_info->hif_ce_state;
1195 ar_pci = ath10k_pci_priv(ar); 1229 ar_pci = ath10k_pci_priv(ar);
1196
1197 if (!ar_pci->started)
1198 return;
1199
1200 ce_hdl = pipe_info->ce_hdl; 1230 ce_hdl = pipe_info->ce_hdl;
1201 1231
1202 while (ath10k_ce_revoke_recv_next(ce_hdl, (void **)&netbuf, 1232 while (ath10k_ce_revoke_recv_next(ce_hdl, (void **)&netbuf,
@@ -1227,10 +1257,6 @@ static void ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe *pipe_info)
1227 1257
1228 ar = pipe_info->hif_ce_state; 1258 ar = pipe_info->hif_ce_state;
1229 ar_pci = ath10k_pci_priv(ar); 1259 ar_pci = ath10k_pci_priv(ar);
1230
1231 if (!ar_pci->started)
1232 return;
1233
1234 ce_hdl = pipe_info->ce_hdl; 1260 ce_hdl = pipe_info->ce_hdl;
1235 1261
1236 while (ath10k_ce_cancel_send_next(ce_hdl, (void **)&netbuf, 1262 while (ath10k_ce_cancel_send_next(ce_hdl, (void **)&netbuf,
@@ -1275,41 +1301,24 @@ static void ath10k_pci_ce_deinit(struct ath10k *ar)
1275 ath10k_ce_deinit_pipe(ar, i); 1301 ath10k_ce_deinit_pipe(ar, i);
1276} 1302}
1277 1303
1278static void ath10k_pci_hif_stop(struct ath10k *ar) 1304static void ath10k_pci_flush(struct ath10k *ar)
1279{ 1305{
1280 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1281 int ret;
1282
1283 ath10k_dbg(ATH10K_DBG_BOOT, "boot hif stop\n");
1284
1285 if (WARN_ON(!ar_pci->started))
1286 return;
1287
1288 ret = ath10k_ce_disable_interrupts(ar);
1289 if (ret)
1290 ath10k_warn("failed to disable CE interrupts: %d\n", ret);
1291
1292 ath10k_pci_free_irq(ar);
1293 ath10k_pci_kill_tasklet(ar); 1306 ath10k_pci_kill_tasklet(ar);
1307 ath10k_pci_buffer_cleanup(ar);
1308}
1294 1309
1295 ret = ath10k_pci_request_early_irq(ar); 1310static void ath10k_pci_hif_stop(struct ath10k *ar)
1296 if (ret) 1311{
1297 ath10k_warn("failed to re-enable early irq: %d\n", ret); 1312 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif stop\n");
1298
1299 /* At this point, asynchronous threads are stopped, the target should
1300 * not DMA nor interrupt. We process the leftovers and then free
1301 * everything else up. */
1302 1313
1303 ath10k_pci_buffer_cleanup(ar); 1314 ath10k_pci_irq_disable(ar);
1315 ath10k_pci_flush(ar);
1304 1316
1305 /* Make the sure the device won't access any structures on the host by 1317 /* Most likely the device has HTT Rx ring configured. The only way to
1306 * resetting it. The device was fed with PCI CE ringbuffer 1318 * prevent the device from accessing (and possible corrupting) host
1307 * configuration during init. If ringbuffers are freed and the device 1319 * memory is to reset the chip now.
1308 * were to access them this could lead to memory corruption on the 1320 */
1309 * host. */
1310 ath10k_pci_warm_reset(ar); 1321 ath10k_pci_warm_reset(ar);
1311
1312 ar_pci->started = 0;
1313} 1322}
1314 1323
1315static int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar, 1324static int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar,
@@ -1360,7 +1369,7 @@ static int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar,
1360 xfer.wait_for_resp = true; 1369 xfer.wait_for_resp = true;
1361 xfer.resp_len = 0; 1370 xfer.resp_len = 0;
1362 1371
1363 ath10k_ce_recv_buf_enqueue(ce_rx, &xfer, resp_paddr); 1372 ath10k_ce_rx_post_buf(ce_rx, &xfer, resp_paddr);
1364 } 1373 }
1365 1374
1366 ret = ath10k_ce_send(ce_tx, &xfer, req_paddr, req_len, -1, 0); 1375 ret = ath10k_ce_send(ce_tx, &xfer, req_paddr, req_len, -1, 0);
@@ -1418,6 +1427,7 @@ static void ath10k_pci_bmi_send_done(struct ath10k_ce_pipe *ce_state)
1418 1427
1419static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe *ce_state) 1428static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe *ce_state)
1420{ 1429{
1430 struct ath10k *ar = ce_state->ar;
1421 struct bmi_xfer *xfer; 1431 struct bmi_xfer *xfer;
1422 u32 ce_data; 1432 u32 ce_data;
1423 unsigned int nbytes; 1433 unsigned int nbytes;
@@ -1429,7 +1439,7 @@ static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe *ce_state)
1429 return; 1439 return;
1430 1440
1431 if (!xfer->wait_for_resp) { 1441 if (!xfer->wait_for_resp) {
1432 ath10k_warn("unexpected: BMI data received; ignoring\n"); 1442 ath10k_warn(ar, "unexpected: BMI data received; ignoring\n");
1433 return; 1443 return;
1434 } 1444 }
1435 1445
@@ -1457,102 +1467,6 @@ static int ath10k_pci_bmi_wait(struct ath10k_ce_pipe *tx_pipe,
1457} 1467}
1458 1468
1459/* 1469/*
1460 * Map from service/endpoint to Copy Engine.
1461 * This table is derived from the CE_PCI TABLE, above.
1462 * It is passed to the Target at startup for use by firmware.
1463 */
1464static const struct service_to_pipe target_service_to_ce_map_wlan[] = {
1465 {
1466 ATH10K_HTC_SVC_ID_WMI_DATA_VO,
1467 PIPEDIR_OUT, /* out = UL = host -> target */
1468 3,
1469 },
1470 {
1471 ATH10K_HTC_SVC_ID_WMI_DATA_VO,
1472 PIPEDIR_IN, /* in = DL = target -> host */
1473 2,
1474 },
1475 {
1476 ATH10K_HTC_SVC_ID_WMI_DATA_BK,
1477 PIPEDIR_OUT, /* out = UL = host -> target */
1478 3,
1479 },
1480 {
1481 ATH10K_HTC_SVC_ID_WMI_DATA_BK,
1482 PIPEDIR_IN, /* in = DL = target -> host */
1483 2,
1484 },
1485 {
1486 ATH10K_HTC_SVC_ID_WMI_DATA_BE,
1487 PIPEDIR_OUT, /* out = UL = host -> target */
1488 3,
1489 },
1490 {
1491 ATH10K_HTC_SVC_ID_WMI_DATA_BE,
1492 PIPEDIR_IN, /* in = DL = target -> host */
1493 2,
1494 },
1495 {
1496 ATH10K_HTC_SVC_ID_WMI_DATA_VI,
1497 PIPEDIR_OUT, /* out = UL = host -> target */
1498 3,
1499 },
1500 {
1501 ATH10K_HTC_SVC_ID_WMI_DATA_VI,
1502 PIPEDIR_IN, /* in = DL = target -> host */
1503 2,
1504 },
1505 {
1506 ATH10K_HTC_SVC_ID_WMI_CONTROL,
1507 PIPEDIR_OUT, /* out = UL = host -> target */
1508 3,
1509 },
1510 {
1511 ATH10K_HTC_SVC_ID_WMI_CONTROL,
1512 PIPEDIR_IN, /* in = DL = target -> host */
1513 2,
1514 },
1515 {
1516 ATH10K_HTC_SVC_ID_RSVD_CTRL,
1517 PIPEDIR_OUT, /* out = UL = host -> target */
1518 0, /* could be moved to 3 (share with WMI) */
1519 },
1520 {
1521 ATH10K_HTC_SVC_ID_RSVD_CTRL,
1522 PIPEDIR_IN, /* in = DL = target -> host */
1523 1,
1524 },
1525 {
1526 ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS, /* not currently used */
1527 PIPEDIR_OUT, /* out = UL = host -> target */
1528 0,
1529 },
1530 {
1531 ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS, /* not currently used */
1532 PIPEDIR_IN, /* in = DL = target -> host */
1533 1,
1534 },
1535 {
1536 ATH10K_HTC_SVC_ID_HTT_DATA_MSG,
1537 PIPEDIR_OUT, /* out = UL = host -> target */
1538 4,
1539 },
1540 {
1541 ATH10K_HTC_SVC_ID_HTT_DATA_MSG,
1542 PIPEDIR_IN, /* in = DL = target -> host */
1543 1,
1544 },
1545
1546 /* (Additions here) */
1547
1548 { /* Must be last */
1549 0,
1550 0,
1551 0,
1552 },
1553};
1554
1555/*
1556 * Send an interrupt to the device to wake up the Target CPU 1470 * Send an interrupt to the device to wake up the Target CPU
1557 * so it has an opportunity to notice any changed state. 1471 * so it has an opportunity to notice any changed state.
1558 */ 1472 */
@@ -1565,7 +1479,7 @@ static int ath10k_pci_wake_target_cpu(struct ath10k *ar)
1565 CORE_CTRL_ADDRESS, 1479 CORE_CTRL_ADDRESS,
1566 &core_ctrl); 1480 &core_ctrl);
1567 if (ret) { 1481 if (ret) {
1568 ath10k_warn("failed to read core_ctrl: %d\n", ret); 1482 ath10k_warn(ar, "failed to read core_ctrl: %d\n", ret);
1569 return ret; 1483 return ret;
1570 } 1484 }
1571 1485
@@ -1576,7 +1490,7 @@ static int ath10k_pci_wake_target_cpu(struct ath10k *ar)
1576 CORE_CTRL_ADDRESS, 1490 CORE_CTRL_ADDRESS,
1577 core_ctrl); 1491 core_ctrl);
1578 if (ret) { 1492 if (ret) {
1579 ath10k_warn("failed to set target CPU interrupt mask: %d\n", 1493 ath10k_warn(ar, "failed to set target CPU interrupt mask: %d\n",
1580 ret); 1494 ret);
1581 return ret; 1495 return ret;
1582 } 1496 }
@@ -1605,13 +1519,13 @@ static int ath10k_pci_init_config(struct ath10k *ar)
1605 ret = ath10k_pci_diag_read_access(ar, interconnect_targ_addr, 1519 ret = ath10k_pci_diag_read_access(ar, interconnect_targ_addr,
1606 &pcie_state_targ_addr); 1520 &pcie_state_targ_addr);
1607 if (ret != 0) { 1521 if (ret != 0) {
1608 ath10k_err("Failed to get pcie state addr: %d\n", ret); 1522 ath10k_err(ar, "Failed to get pcie state addr: %d\n", ret);
1609 return ret; 1523 return ret;
1610 } 1524 }
1611 1525
1612 if (pcie_state_targ_addr == 0) { 1526 if (pcie_state_targ_addr == 0) {
1613 ret = -EIO; 1527 ret = -EIO;
1614 ath10k_err("Invalid pcie state addr\n"); 1528 ath10k_err(ar, "Invalid pcie state addr\n");
1615 return ret; 1529 return ret;
1616 } 1530 }
1617 1531
@@ -1620,13 +1534,13 @@ static int ath10k_pci_init_config(struct ath10k *ar)
1620 pipe_cfg_addr), 1534 pipe_cfg_addr),
1621 &pipe_cfg_targ_addr); 1535 &pipe_cfg_targ_addr);
1622 if (ret != 0) { 1536 if (ret != 0) {
1623 ath10k_err("Failed to get pipe cfg addr: %d\n", ret); 1537 ath10k_err(ar, "Failed to get pipe cfg addr: %d\n", ret);
1624 return ret; 1538 return ret;
1625 } 1539 }
1626 1540
1627 if (pipe_cfg_targ_addr == 0) { 1541 if (pipe_cfg_targ_addr == 0) {
1628 ret = -EIO; 1542 ret = -EIO;
1629 ath10k_err("Invalid pipe cfg addr\n"); 1543 ath10k_err(ar, "Invalid pipe cfg addr\n");
1630 return ret; 1544 return ret;
1631 } 1545 }
1632 1546
@@ -1635,7 +1549,7 @@ static int ath10k_pci_init_config(struct ath10k *ar)
1635 sizeof(target_ce_config_wlan)); 1549 sizeof(target_ce_config_wlan));
1636 1550
1637 if (ret != 0) { 1551 if (ret != 0) {
1638 ath10k_err("Failed to write pipe cfg: %d\n", ret); 1552 ath10k_err(ar, "Failed to write pipe cfg: %d\n", ret);
1639 return ret; 1553 return ret;
1640 } 1554 }
1641 1555
@@ -1644,13 +1558,13 @@ static int ath10k_pci_init_config(struct ath10k *ar)
1644 svc_to_pipe_map), 1558 svc_to_pipe_map),
1645 &svc_to_pipe_map); 1559 &svc_to_pipe_map);
1646 if (ret != 0) { 1560 if (ret != 0) {
1647 ath10k_err("Failed to get svc/pipe map: %d\n", ret); 1561 ath10k_err(ar, "Failed to get svc/pipe map: %d\n", ret);
1648 return ret; 1562 return ret;
1649 } 1563 }
1650 1564
1651 if (svc_to_pipe_map == 0) { 1565 if (svc_to_pipe_map == 0) {
1652 ret = -EIO; 1566 ret = -EIO;
1653 ath10k_err("Invalid svc_to_pipe map\n"); 1567 ath10k_err(ar, "Invalid svc_to_pipe map\n");
1654 return ret; 1568 return ret;
1655 } 1569 }
1656 1570
@@ -1658,7 +1572,7 @@ static int ath10k_pci_init_config(struct ath10k *ar)
1658 target_service_to_ce_map_wlan, 1572 target_service_to_ce_map_wlan,
1659 sizeof(target_service_to_ce_map_wlan)); 1573 sizeof(target_service_to_ce_map_wlan));
1660 if (ret != 0) { 1574 if (ret != 0) {
1661 ath10k_err("Failed to write svc/pipe map: %d\n", ret); 1575 ath10k_err(ar, "Failed to write svc/pipe map: %d\n", ret);
1662 return ret; 1576 return ret;
1663 } 1577 }
1664 1578
@@ -1667,18 +1581,17 @@ static int ath10k_pci_init_config(struct ath10k *ar)
1667 config_flags), 1581 config_flags),
1668 &pcie_config_flags); 1582 &pcie_config_flags);
1669 if (ret != 0) { 1583 if (ret != 0) {
1670 ath10k_err("Failed to get pcie config_flags: %d\n", ret); 1584 ath10k_err(ar, "Failed to get pcie config_flags: %d\n", ret);
1671 return ret; 1585 return ret;
1672 } 1586 }
1673 1587
1674 pcie_config_flags &= ~PCIE_CONFIG_FLAG_ENABLE_L1; 1588 pcie_config_flags &= ~PCIE_CONFIG_FLAG_ENABLE_L1;
1675 1589
1676 ret = ath10k_pci_diag_write_mem(ar, pcie_state_targ_addr + 1590 ret = ath10k_pci_diag_write_access(ar, pcie_state_targ_addr +
1677 offsetof(struct pcie_state, config_flags), 1591 offsetof(struct pcie_state, config_flags),
1678 &pcie_config_flags, 1592 pcie_config_flags);
1679 sizeof(pcie_config_flags));
1680 if (ret != 0) { 1593 if (ret != 0) {
1681 ath10k_err("Failed to write pcie config_flags: %d\n", ret); 1594 ath10k_err(ar, "Failed to write pcie config_flags: %d\n", ret);
1682 return ret; 1595 return ret;
1683 } 1596 }
1684 1597
@@ -1687,7 +1600,7 @@ static int ath10k_pci_init_config(struct ath10k *ar)
1687 1600
1688 ret = ath10k_pci_diag_read_access(ar, ealloc_targ_addr, &ealloc_value); 1601 ret = ath10k_pci_diag_read_access(ar, ealloc_targ_addr, &ealloc_value);
1689 if (ret != 0) { 1602 if (ret != 0) {
1690 ath10k_err("Faile to get early alloc val: %d\n", ret); 1603 ath10k_err(ar, "Faile to get early alloc val: %d\n", ret);
1691 return ret; 1604 return ret;
1692 } 1605 }
1693 1606
@@ -1699,7 +1612,7 @@ static int ath10k_pci_init_config(struct ath10k *ar)
1699 1612
1700 ret = ath10k_pci_diag_write_access(ar, ealloc_targ_addr, ealloc_value); 1613 ret = ath10k_pci_diag_write_access(ar, ealloc_targ_addr, ealloc_value);
1701 if (ret != 0) { 1614 if (ret != 0) {
1702 ath10k_err("Failed to set early alloc val: %d\n", ret); 1615 ath10k_err(ar, "Failed to set early alloc val: %d\n", ret);
1703 return ret; 1616 return ret;
1704 } 1617 }
1705 1618
@@ -1708,7 +1621,7 @@ static int ath10k_pci_init_config(struct ath10k *ar)
1708 1621
1709 ret = ath10k_pci_diag_read_access(ar, flag2_targ_addr, &flag2_value); 1622 ret = ath10k_pci_diag_read_access(ar, flag2_targ_addr, &flag2_value);
1710 if (ret != 0) { 1623 if (ret != 0) {
1711 ath10k_err("Failed to get option val: %d\n", ret); 1624 ath10k_err(ar, "Failed to get option val: %d\n", ret);
1712 return ret; 1625 return ret;
1713 } 1626 }
1714 1627
@@ -1716,7 +1629,7 @@ static int ath10k_pci_init_config(struct ath10k *ar)
1716 1629
1717 ret = ath10k_pci_diag_write_access(ar, flag2_targ_addr, flag2_value); 1630 ret = ath10k_pci_diag_write_access(ar, flag2_targ_addr, flag2_value);
1718 if (ret != 0) { 1631 if (ret != 0) {
1719 ath10k_err("Failed to set option val: %d\n", ret); 1632 ath10k_err(ar, "Failed to set option val: %d\n", ret);
1720 return ret; 1633 return ret;
1721 } 1634 }
1722 1635
@@ -1730,7 +1643,7 @@ static int ath10k_pci_alloc_ce(struct ath10k *ar)
1730 for (i = 0; i < CE_COUNT; i++) { 1643 for (i = 0; i < CE_COUNT; i++) {
1731 ret = ath10k_ce_alloc_pipe(ar, i, &host_ce_config_wlan[i]); 1644 ret = ath10k_ce_alloc_pipe(ar, i, &host_ce_config_wlan[i]);
1732 if (ret) { 1645 if (ret) {
1733 ath10k_err("failed to allocate copy engine pipe %d: %d\n", 1646 ath10k_err(ar, "failed to allocate copy engine pipe %d: %d\n",
1734 i, ret); 1647 i, ret);
1735 return ret; 1648 return ret;
1736 } 1649 }
@@ -1761,9 +1674,11 @@ static int ath10k_pci_ce_init(struct ath10k *ar)
1761 pipe_info->hif_ce_state = ar; 1674 pipe_info->hif_ce_state = ar;
1762 attr = &host_ce_config_wlan[pipe_num]; 1675 attr = &host_ce_config_wlan[pipe_num];
1763 1676
1764 ret = ath10k_ce_init_pipe(ar, pipe_num, attr); 1677 ret = ath10k_ce_init_pipe(ar, pipe_num, attr,
1678 ath10k_pci_ce_send_done,
1679 ath10k_pci_ce_recv_data);
1765 if (ret) { 1680 if (ret) {
1766 ath10k_err("failed to initialize copy engine pipe %d: %d\n", 1681 ath10k_err(ar, "failed to initialize copy engine pipe %d: %d\n",
1767 pipe_num, ret); 1682 pipe_num, ret);
1768 return ret; 1683 return ret;
1769 } 1684 }
@@ -1783,32 +1698,19 @@ static int ath10k_pci_ce_init(struct ath10k *ar)
1783 return 0; 1698 return 0;
1784} 1699}
1785 1700
1786static void ath10k_pci_fw_interrupt_handler(struct ath10k *ar) 1701static bool ath10k_pci_has_fw_crashed(struct ath10k *ar)
1787{ 1702{
1788 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1703 return ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS) &
1789 u32 fw_indicator; 1704 FW_IND_EVENT_PENDING;
1790 1705}
1791 ath10k_pci_wake(ar);
1792
1793 fw_indicator = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
1794
1795 if (fw_indicator & FW_IND_EVENT_PENDING) {
1796 /* ACK: clear Target-side pending event */
1797 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS,
1798 fw_indicator & ~FW_IND_EVENT_PENDING);
1799 1706
1800 if (ar_pci->started) { 1707static void ath10k_pci_fw_crashed_clear(struct ath10k *ar)
1801 ath10k_pci_hif_dump_area(ar); 1708{
1802 } else { 1709 u32 val;
1803 /*
1804 * Probable Target failure before we're prepared
1805 * to handle it. Generally unexpected.
1806 */
1807 ath10k_warn("early firmware event indicated\n");
1808 }
1809 }
1810 1710
1811 ath10k_pci_sleep(ar); 1711 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
1712 val &= ~FW_IND_EVENT_PENDING;
1713 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, val);
1812} 1714}
1813 1715
1814/* this function effectively clears target memory controller assert line */ 1716/* this function effectively clears target memory controller assert line */
@@ -1833,25 +1735,19 @@ static void ath10k_pci_warm_reset_si0(struct ath10k *ar)
1833 1735
1834static int ath10k_pci_warm_reset(struct ath10k *ar) 1736static int ath10k_pci_warm_reset(struct ath10k *ar)
1835{ 1737{
1836 int ret = 0;
1837 u32 val; 1738 u32 val;
1838 1739
1839 ath10k_dbg(ATH10K_DBG_BOOT, "boot warm reset\n"); 1740 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset\n");
1840
1841 ret = ath10k_do_pci_wake(ar);
1842 if (ret) {
1843 ath10k_err("failed to wake up target: %d\n", ret);
1844 return ret;
1845 }
1846 1741
1847 /* debug */ 1742 /* debug */
1848 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 1743 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1849 PCIE_INTR_CAUSE_ADDRESS); 1744 PCIE_INTR_CAUSE_ADDRESS);
1850 ath10k_dbg(ATH10K_DBG_BOOT, "boot host cpu intr cause: 0x%08x\n", val); 1745 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot host cpu intr cause: 0x%08x\n",
1746 val);
1851 1747
1852 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 1748 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1853 CPU_INTR_ADDRESS); 1749 CPU_INTR_ADDRESS);
1854 ath10k_dbg(ATH10K_DBG_BOOT, "boot target cpu intr cause: 0x%08x\n", 1750 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target cpu intr cause: 0x%08x\n",
1855 val); 1751 val);
1856 1752
1857 /* disable pending irqs */ 1753 /* disable pending irqs */
@@ -1894,11 +1790,12 @@ static int ath10k_pci_warm_reset(struct ath10k *ar)
1894 /* debug */ 1790 /* debug */
1895 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 1791 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1896 PCIE_INTR_CAUSE_ADDRESS); 1792 PCIE_INTR_CAUSE_ADDRESS);
1897 ath10k_dbg(ATH10K_DBG_BOOT, "boot host cpu intr cause: 0x%08x\n", val); 1793 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot host cpu intr cause: 0x%08x\n",
1794 val);
1898 1795
1899 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 1796 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1900 CPU_INTR_ADDRESS); 1797 CPU_INTR_ADDRESS);
1901 ath10k_dbg(ATH10K_DBG_BOOT, "boot target cpu intr cause: 0x%08x\n", 1798 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target cpu intr cause: 0x%08x\n",
1902 val); 1799 val);
1903 1800
1904 /* CPU warm reset */ 1801 /* CPU warm reset */
@@ -1909,20 +1806,18 @@ static int ath10k_pci_warm_reset(struct ath10k *ar)
1909 1806
1910 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + 1807 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
1911 SOC_RESET_CONTROL_ADDRESS); 1808 SOC_RESET_CONTROL_ADDRESS);
1912 ath10k_dbg(ATH10K_DBG_BOOT, "boot target reset state: 0x%08x\n", val); 1809 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target reset state: 0x%08x\n",
1810 val);
1913 1811
1914 msleep(100); 1812 msleep(100);
1915 1813
1916 ath10k_dbg(ATH10K_DBG_BOOT, "boot warm reset complete\n"); 1814 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset complete\n");
1917 1815
1918 ath10k_do_pci_sleep(ar); 1816 return 0;
1919 return ret;
1920} 1817}
1921 1818
1922static int __ath10k_pci_hif_power_up(struct ath10k *ar, bool cold_reset) 1819static int __ath10k_pci_hif_power_up(struct ath10k *ar, bool cold_reset)
1923{ 1820{
1924 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1925 const char *irq_mode;
1926 int ret; 1821 int ret;
1927 1822
1928 /* 1823 /*
@@ -1941,80 +1836,39 @@ static int __ath10k_pci_hif_power_up(struct ath10k *ar, bool cold_reset)
1941 ret = ath10k_pci_warm_reset(ar); 1836 ret = ath10k_pci_warm_reset(ar);
1942 1837
1943 if (ret) { 1838 if (ret) {
1944 ath10k_err("failed to reset target: %d\n", ret); 1839 ath10k_err(ar, "failed to reset target: %d\n", ret);
1945 goto err; 1840 goto err;
1946 } 1841 }
1947 1842
1948 if (!test_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features))
1949 /* Force AWAKE forever */
1950 ath10k_do_pci_wake(ar);
1951
1952 ret = ath10k_pci_ce_init(ar); 1843 ret = ath10k_pci_ce_init(ar);
1953 if (ret) { 1844 if (ret) {
1954 ath10k_err("failed to initialize CE: %d\n", ret); 1845 ath10k_err(ar, "failed to initialize CE: %d\n", ret);
1955 goto err_ps; 1846 goto err;
1956 }
1957
1958 ret = ath10k_ce_disable_interrupts(ar);
1959 if (ret) {
1960 ath10k_err("failed to disable CE interrupts: %d\n", ret);
1961 goto err_ce;
1962 }
1963
1964 ret = ath10k_pci_init_irq(ar);
1965 if (ret) {
1966 ath10k_err("failed to init irqs: %d\n", ret);
1967 goto err_ce;
1968 }
1969
1970 ret = ath10k_pci_request_early_irq(ar);
1971 if (ret) {
1972 ath10k_err("failed to request early irq: %d\n", ret);
1973 goto err_deinit_irq;
1974 } 1847 }
1975 1848
1976 ret = ath10k_pci_wait_for_target_init(ar); 1849 ret = ath10k_pci_wait_for_target_init(ar);
1977 if (ret) { 1850 if (ret) {
1978 ath10k_err("failed to wait for target to init: %d\n", ret); 1851 ath10k_err(ar, "failed to wait for target to init: %d\n", ret);
1979 goto err_free_early_irq; 1852 goto err_ce;
1980 } 1853 }
1981 1854
1982 ret = ath10k_pci_init_config(ar); 1855 ret = ath10k_pci_init_config(ar);
1983 if (ret) { 1856 if (ret) {
1984 ath10k_err("failed to setup init config: %d\n", ret); 1857 ath10k_err(ar, "failed to setup init config: %d\n", ret);
1985 goto err_free_early_irq; 1858 goto err_ce;
1986 } 1859 }
1987 1860
1988 ret = ath10k_pci_wake_target_cpu(ar); 1861 ret = ath10k_pci_wake_target_cpu(ar);
1989 if (ret) { 1862 if (ret) {
1990 ath10k_err("could not wake up target CPU: %d\n", ret); 1863 ath10k_err(ar, "could not wake up target CPU: %d\n", ret);
1991 goto err_free_early_irq; 1864 goto err_ce;
1992 } 1865 }
1993 1866
1994 if (ar_pci->num_msi_intrs > 1)
1995 irq_mode = "MSI-X";
1996 else if (ar_pci->num_msi_intrs == 1)
1997 irq_mode = "MSI";
1998 else
1999 irq_mode = "legacy";
2000
2001 if (!test_bit(ATH10K_FLAG_FIRST_BOOT_DONE, &ar->dev_flags))
2002 ath10k_info("pci irq %s irq_mode %d reset_mode %d\n",
2003 irq_mode, ath10k_pci_irq_mode,
2004 ath10k_pci_reset_mode);
2005
2006 return 0; 1867 return 0;
2007 1868
2008err_free_early_irq:
2009 ath10k_pci_free_early_irq(ar);
2010err_deinit_irq:
2011 ath10k_pci_deinit_irq(ar);
2012err_ce: 1869err_ce:
2013 ath10k_pci_ce_deinit(ar); 1870 ath10k_pci_ce_deinit(ar);
2014 ath10k_pci_warm_reset(ar); 1871 ath10k_pci_warm_reset(ar);
2015err_ps:
2016 if (!test_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features))
2017 ath10k_do_pci_sleep(ar);
2018err: 1872err:
2019 return ret; 1873 return ret;
2020} 1874}
@@ -2034,7 +1888,7 @@ static int ath10k_pci_hif_power_up_warm(struct ath10k *ar)
2034 if (ret == 0) 1888 if (ret == 0)
2035 break; 1889 break;
2036 1890
2037 ath10k_warn("failed to warm reset (attempt %d out of %d): %d\n", 1891 ath10k_warn(ar, "failed to warm reset (attempt %d out of %d): %d\n",
2038 i + 1, ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS, ret); 1892 i + 1, ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS, ret);
2039 } 1893 }
2040 1894
@@ -2045,7 +1899,7 @@ static int ath10k_pci_hif_power_up(struct ath10k *ar)
2045{ 1899{
2046 int ret; 1900 int ret;
2047 1901
2048 ath10k_dbg(ATH10K_DBG_BOOT, "boot hif power up\n"); 1902 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power up\n");
2049 1903
2050 /* 1904 /*
2051 * Hardware CUS232 version 2 has some issues with cold reset and the 1905 * Hardware CUS232 version 2 has some issues with cold reset and the
@@ -2057,17 +1911,17 @@ static int ath10k_pci_hif_power_up(struct ath10k *ar)
2057 */ 1911 */
2058 ret = ath10k_pci_hif_power_up_warm(ar); 1912 ret = ath10k_pci_hif_power_up_warm(ar);
2059 if (ret) { 1913 if (ret) {
2060 ath10k_warn("failed to power up target using warm reset: %d\n", 1914 ath10k_warn(ar, "failed to power up target using warm reset: %d\n",
2061 ret); 1915 ret);
2062 1916
2063 if (ath10k_pci_reset_mode == ATH10K_PCI_RESET_WARM_ONLY) 1917 if (ath10k_pci_reset_mode == ATH10K_PCI_RESET_WARM_ONLY)
2064 return ret; 1918 return ret;
2065 1919
2066 ath10k_warn("trying cold reset\n"); 1920 ath10k_warn(ar, "trying cold reset\n");
2067 1921
2068 ret = __ath10k_pci_hif_power_up(ar, true); 1922 ret = __ath10k_pci_hif_power_up(ar, true);
2069 if (ret) { 1923 if (ret) {
2070 ath10k_err("failed to power up target using cold reset too (%d)\n", 1924 ath10k_err(ar, "failed to power up target using cold reset too (%d)\n",
2071 ret); 1925 ret);
2072 return ret; 1926 return ret;
2073 } 1927 }
@@ -2078,18 +1932,9 @@ static int ath10k_pci_hif_power_up(struct ath10k *ar)
2078 1932
2079static void ath10k_pci_hif_power_down(struct ath10k *ar) 1933static void ath10k_pci_hif_power_down(struct ath10k *ar)
2080{ 1934{
2081 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1935 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power down\n");
2082
2083 ath10k_dbg(ATH10K_DBG_BOOT, "boot hif power down\n");
2084 1936
2085 ath10k_pci_free_early_irq(ar);
2086 ath10k_pci_kill_tasklet(ar);
2087 ath10k_pci_deinit_irq(ar);
2088 ath10k_pci_ce_deinit(ar);
2089 ath10k_pci_warm_reset(ar); 1937 ath10k_pci_warm_reset(ar);
2090
2091 if (!test_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features))
2092 ath10k_do_pci_sleep(ar);
2093} 1938}
2094 1939
2095#ifdef CONFIG_PM 1940#ifdef CONFIG_PM
@@ -2171,7 +2016,13 @@ static void ath10k_msi_err_tasklet(unsigned long data)
2171{ 2016{
2172 struct ath10k *ar = (struct ath10k *)data; 2017 struct ath10k *ar = (struct ath10k *)data;
2173 2018
2174 ath10k_pci_fw_interrupt_handler(ar); 2019 if (!ath10k_pci_has_fw_crashed(ar)) {
2020 ath10k_warn(ar, "received unsolicited fw crash interrupt\n");
2021 return;
2022 }
2023
2024 ath10k_pci_fw_crashed_clear(ar);
2025 ath10k_pci_fw_crashed_dump(ar);
2175} 2026}
2176 2027
2177/* 2028/*
@@ -2185,7 +2036,8 @@ static irqreturn_t ath10k_pci_per_engine_handler(int irq, void *arg)
2185 int ce_id = irq - ar_pci->pdev->irq - MSI_ASSIGN_CE_INITIAL; 2036 int ce_id = irq - ar_pci->pdev->irq - MSI_ASSIGN_CE_INITIAL;
2186 2037
2187 if (ce_id < 0 || ce_id >= ARRAY_SIZE(ar_pci->pipe_info)) { 2038 if (ce_id < 0 || ce_id >= ARRAY_SIZE(ar_pci->pipe_info)) {
2188 ath10k_warn("unexpected/invalid irq %d ce_id %d\n", irq, ce_id); 2039 ath10k_warn(ar, "unexpected/invalid irq %d ce_id %d\n", irq,
2040 ce_id);
2189 return IRQ_HANDLED; 2041 return IRQ_HANDLED;
2190 } 2042 }
2191 2043
@@ -2232,36 +2084,17 @@ static irqreturn_t ath10k_pci_interrupt_handler(int irq, void *arg)
2232 return IRQ_HANDLED; 2084 return IRQ_HANDLED;
2233} 2085}
2234 2086
2235static void ath10k_pci_early_irq_tasklet(unsigned long data) 2087static void ath10k_pci_tasklet(unsigned long data)
2236{ 2088{
2237 struct ath10k *ar = (struct ath10k *)data; 2089 struct ath10k *ar = (struct ath10k *)data;
2238 u32 fw_ind; 2090 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2239 int ret;
2240 2091
2241 ret = ath10k_pci_wake(ar); 2092 if (ath10k_pci_has_fw_crashed(ar)) {
2242 if (ret) { 2093 ath10k_pci_fw_crashed_clear(ar);
2243 ath10k_warn("failed to wake target in early irq tasklet: %d\n", 2094 ath10k_pci_fw_crashed_dump(ar);
2244 ret);
2245 return; 2095 return;
2246 } 2096 }
2247 2097
2248 fw_ind = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
2249 if (fw_ind & FW_IND_EVENT_PENDING) {
2250 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS,
2251 fw_ind & ~FW_IND_EVENT_PENDING);
2252 ath10k_pci_hif_dump_area(ar);
2253 }
2254
2255 ath10k_pci_sleep(ar);
2256 ath10k_pci_enable_legacy_irq(ar);
2257}
2258
2259static void ath10k_pci_tasklet(unsigned long data)
2260{
2261 struct ath10k *ar = (struct ath10k *)data;
2262 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2263
2264 ath10k_pci_fw_interrupt_handler(ar); /* FIXME: Handle FW error */
2265 ath10k_ce_per_engine_service_any(ar); 2098 ath10k_ce_per_engine_service_any(ar);
2266 2099
2267 /* Re-enable legacy irq that was disabled in the irq handler */ 2100 /* Re-enable legacy irq that was disabled in the irq handler */
@@ -2278,7 +2111,7 @@ static int ath10k_pci_request_irq_msix(struct ath10k *ar)
2278 ath10k_pci_msi_fw_handler, 2111 ath10k_pci_msi_fw_handler,
2279 IRQF_SHARED, "ath10k_pci", ar); 2112 IRQF_SHARED, "ath10k_pci", ar);
2280 if (ret) { 2113 if (ret) {
2281 ath10k_warn("failed to request MSI-X fw irq %d: %d\n", 2114 ath10k_warn(ar, "failed to request MSI-X fw irq %d: %d\n",
2282 ar_pci->pdev->irq + MSI_ASSIGN_FW, ret); 2115 ar_pci->pdev->irq + MSI_ASSIGN_FW, ret);
2283 return ret; 2116 return ret;
2284 } 2117 }
@@ -2288,7 +2121,7 @@ static int ath10k_pci_request_irq_msix(struct ath10k *ar)
2288 ath10k_pci_per_engine_handler, 2121 ath10k_pci_per_engine_handler,
2289 IRQF_SHARED, "ath10k_pci", ar); 2122 IRQF_SHARED, "ath10k_pci", ar);
2290 if (ret) { 2123 if (ret) {
2291 ath10k_warn("failed to request MSI-X ce irq %d: %d\n", 2124 ath10k_warn(ar, "failed to request MSI-X ce irq %d: %d\n",
2292 ar_pci->pdev->irq + i, ret); 2125 ar_pci->pdev->irq + i, ret);
2293 2126
2294 for (i--; i >= MSI_ASSIGN_CE_INITIAL; i--) 2127 for (i--; i >= MSI_ASSIGN_CE_INITIAL; i--)
@@ -2311,7 +2144,7 @@ static int ath10k_pci_request_irq_msi(struct ath10k *ar)
2311 ath10k_pci_interrupt_handler, 2144 ath10k_pci_interrupt_handler,
2312 IRQF_SHARED, "ath10k_pci", ar); 2145 IRQF_SHARED, "ath10k_pci", ar);
2313 if (ret) { 2146 if (ret) {
2314 ath10k_warn("failed to request MSI irq %d: %d\n", 2147 ath10k_warn(ar, "failed to request MSI irq %d: %d\n",
2315 ar_pci->pdev->irq, ret); 2148 ar_pci->pdev->irq, ret);
2316 return ret; 2149 return ret;
2317 } 2150 }
@@ -2328,7 +2161,7 @@ static int ath10k_pci_request_irq_legacy(struct ath10k *ar)
2328 ath10k_pci_interrupt_handler, 2161 ath10k_pci_interrupt_handler,
2329 IRQF_SHARED, "ath10k_pci", ar); 2162 IRQF_SHARED, "ath10k_pci", ar);
2330 if (ret) { 2163 if (ret) {
2331 ath10k_warn("failed to request legacy irq %d: %d\n", 2164 ath10k_warn(ar, "failed to request legacy irq %d: %d\n",
2332 ar_pci->pdev->irq, ret); 2165 ar_pci->pdev->irq, ret);
2333 return ret; 2166 return ret;
2334 } 2167 }
@@ -2349,7 +2182,7 @@ static int ath10k_pci_request_irq(struct ath10k *ar)
2349 return ath10k_pci_request_irq_msix(ar); 2182 return ath10k_pci_request_irq_msix(ar);
2350 } 2183 }
2351 2184
2352 ath10k_warn("unknown irq configuration upon request\n"); 2185 ath10k_warn(ar, "unknown irq configuration upon request\n");
2353 return -EINVAL; 2186 return -EINVAL;
2354} 2187}
2355 2188
@@ -2372,8 +2205,6 @@ static void ath10k_pci_init_irq_tasklets(struct ath10k *ar)
2372 tasklet_init(&ar_pci->intr_tq, ath10k_pci_tasklet, (unsigned long)ar); 2205 tasklet_init(&ar_pci->intr_tq, ath10k_pci_tasklet, (unsigned long)ar);
2373 tasklet_init(&ar_pci->msi_fw_err, ath10k_msi_err_tasklet, 2206 tasklet_init(&ar_pci->msi_fw_err, ath10k_msi_err_tasklet,
2374 (unsigned long)ar); 2207 (unsigned long)ar);
2375 tasklet_init(&ar_pci->early_irq_tasklet, ath10k_pci_early_irq_tasklet,
2376 (unsigned long)ar);
2377 2208
2378 for (i = 0; i < CE_COUNT; i++) { 2209 for (i = 0; i < CE_COUNT; i++) {
2379 ar_pci->pipe_info[i].ar_pci = ar_pci; 2210 ar_pci->pipe_info[i].ar_pci = ar_pci;
@@ -2385,18 +2216,16 @@ static void ath10k_pci_init_irq_tasklets(struct ath10k *ar)
2385static int ath10k_pci_init_irq(struct ath10k *ar) 2216static int ath10k_pci_init_irq(struct ath10k *ar)
2386{ 2217{
2387 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2218 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2388 bool msix_supported = test_bit(ATH10K_PCI_FEATURE_MSI_X,
2389 ar_pci->features);
2390 int ret; 2219 int ret;
2391 2220
2392 ath10k_pci_init_irq_tasklets(ar); 2221 ath10k_pci_init_irq_tasklets(ar);
2393 2222
2394 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_AUTO && 2223 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_AUTO)
2395 !test_bit(ATH10K_FLAG_FIRST_BOOT_DONE, &ar->dev_flags)) 2224 ath10k_info(ar, "limiting irq mode to: %d\n",
2396 ath10k_info("limiting irq mode to: %d\n", ath10k_pci_irq_mode); 2225 ath10k_pci_irq_mode);
2397 2226
2398 /* Try MSI-X */ 2227 /* Try MSI-X */
2399 if (ath10k_pci_irq_mode == ATH10K_PCI_IRQ_AUTO && msix_supported) { 2228 if (ath10k_pci_irq_mode == ATH10K_PCI_IRQ_AUTO) {
2400 ar_pci->num_msi_intrs = MSI_NUM_REQUEST; 2229 ar_pci->num_msi_intrs = MSI_NUM_REQUEST;
2401 ret = pci_enable_msi_range(ar_pci->pdev, ar_pci->num_msi_intrs, 2230 ret = pci_enable_msi_range(ar_pci->pdev, ar_pci->num_msi_intrs,
2402 ar_pci->num_msi_intrs); 2231 ar_pci->num_msi_intrs);
@@ -2426,34 +2255,16 @@ static int ath10k_pci_init_irq(struct ath10k *ar)
2426 * synchronization checking. */ 2255 * synchronization checking. */
2427 ar_pci->num_msi_intrs = 0; 2256 ar_pci->num_msi_intrs = 0;
2428 2257
2429 ret = ath10k_pci_wake(ar);
2430 if (ret) {
2431 ath10k_warn("failed to wake target: %d\n", ret);
2432 return ret;
2433 }
2434
2435 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS, 2258 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
2436 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); 2259 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
2437 ath10k_pci_sleep(ar);
2438 2260
2439 return 0; 2261 return 0;
2440} 2262}
2441 2263
2442static int ath10k_pci_deinit_irq_legacy(struct ath10k *ar) 2264static void ath10k_pci_deinit_irq_legacy(struct ath10k *ar)
2443{ 2265{
2444 int ret;
2445
2446 ret = ath10k_pci_wake(ar);
2447 if (ret) {
2448 ath10k_warn("failed to wake target: %d\n", ret);
2449 return ret;
2450 }
2451
2452 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS, 2266 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
2453 0); 2267 0);
2454 ath10k_pci_sleep(ar);
2455
2456 return 0;
2457} 2268}
2458 2269
2459static int ath10k_pci_deinit_irq(struct ath10k *ar) 2270static int ath10k_pci_deinit_irq(struct ath10k *ar)
@@ -2462,7 +2273,8 @@ static int ath10k_pci_deinit_irq(struct ath10k *ar)
2462 2273
2463 switch (ar_pci->num_msi_intrs) { 2274 switch (ar_pci->num_msi_intrs) {
2464 case 0: 2275 case 0:
2465 return ath10k_pci_deinit_irq_legacy(ar); 2276 ath10k_pci_deinit_irq_legacy(ar);
2277 return 0;
2466 case 1: 2278 case 1:
2467 /* fall-through */ 2279 /* fall-through */
2468 case MSI_NUM_REQUEST: 2280 case MSI_NUM_REQUEST:
@@ -2472,7 +2284,7 @@ static int ath10k_pci_deinit_irq(struct ath10k *ar)
2472 pci_disable_msi(ar_pci->pdev); 2284 pci_disable_msi(ar_pci->pdev);
2473 } 2285 }
2474 2286
2475 ath10k_warn("unknown irq configuration upon deinit\n"); 2287 ath10k_warn(ar, "unknown irq configuration upon deinit\n");
2476 return -EINVAL; 2288 return -EINVAL;
2477} 2289}
2478 2290
@@ -2480,23 +2292,17 @@ static int ath10k_pci_wait_for_target_init(struct ath10k *ar)
2480{ 2292{
2481 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2293 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2482 unsigned long timeout; 2294 unsigned long timeout;
2483 int ret;
2484 u32 val; 2295 u32 val;
2485 2296
2486 ath10k_dbg(ATH10K_DBG_BOOT, "boot waiting target to initialise\n"); 2297 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot waiting target to initialise\n");
2487
2488 ret = ath10k_pci_wake(ar);
2489 if (ret) {
2490 ath10k_err("failed to wake up target for init: %d\n", ret);
2491 return ret;
2492 }
2493 2298
2494 timeout = jiffies + msecs_to_jiffies(ATH10K_PCI_TARGET_WAIT); 2299 timeout = jiffies + msecs_to_jiffies(ATH10K_PCI_TARGET_WAIT);
2495 2300
2496 do { 2301 do {
2497 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS); 2302 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
2498 2303
2499 ath10k_dbg(ATH10K_DBG_BOOT, "boot target indicator %x\n", val); 2304 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target indicator %x\n",
2305 val);
2500 2306
2501 /* target should never return this */ 2307 /* target should never return this */
2502 if (val == 0xffffffff) 2308 if (val == 0xffffffff)
@@ -2511,55 +2317,42 @@ static int ath10k_pci_wait_for_target_init(struct ath10k *ar)
2511 2317
2512 if (ar_pci->num_msi_intrs == 0) 2318 if (ar_pci->num_msi_intrs == 0)
2513 /* Fix potential race by repeating CORE_BASE writes */ 2319 /* Fix potential race by repeating CORE_BASE writes */
2514 ath10k_pci_soc_write32(ar, PCIE_INTR_ENABLE_ADDRESS, 2320 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
2515 PCIE_INTR_FIRMWARE_MASK | 2321 PCIE_INTR_ENABLE_ADDRESS,
2516 PCIE_INTR_CE_MASK_ALL); 2322 PCIE_INTR_FIRMWARE_MASK |
2323 PCIE_INTR_CE_MASK_ALL);
2517 2324
2518 mdelay(10); 2325 mdelay(10);
2519 } while (time_before(jiffies, timeout)); 2326 } while (time_before(jiffies, timeout));
2520 2327
2521 if (val == 0xffffffff) { 2328 if (val == 0xffffffff) {
2522 ath10k_err("failed to read device register, device is gone\n"); 2329 ath10k_err(ar, "failed to read device register, device is gone\n");
2523 ret = -EIO; 2330 return -EIO;
2524 goto out;
2525 } 2331 }
2526 2332
2527 if (val & FW_IND_EVENT_PENDING) { 2333 if (val & FW_IND_EVENT_PENDING) {
2528 ath10k_warn("device has crashed during init\n"); 2334 ath10k_warn(ar, "device has crashed during init\n");
2529 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, 2335 ath10k_pci_fw_crashed_clear(ar);
2530 val & ~FW_IND_EVENT_PENDING); 2336 ath10k_pci_fw_crashed_dump(ar);
2531 ath10k_pci_hif_dump_area(ar); 2337 return -ECOMM;
2532 ret = -ECOMM;
2533 goto out;
2534 } 2338 }
2535 2339
2536 if (!(val & FW_IND_INITIALIZED)) { 2340 if (!(val & FW_IND_INITIALIZED)) {
2537 ath10k_err("failed to receive initialized event from target: %08x\n", 2341 ath10k_err(ar, "failed to receive initialized event from target: %08x\n",
2538 val); 2342 val);
2539 ret = -ETIMEDOUT; 2343 return -ETIMEDOUT;
2540 goto out;
2541 } 2344 }
2542 2345
2543 ath10k_dbg(ATH10K_DBG_BOOT, "boot target initialised\n"); 2346 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target initialised\n");
2544 2347 return 0;
2545out:
2546 ath10k_pci_sleep(ar);
2547 return ret;
2548} 2348}
2549 2349
2550static int ath10k_pci_cold_reset(struct ath10k *ar) 2350static int ath10k_pci_cold_reset(struct ath10k *ar)
2551{ 2351{
2552 int i, ret; 2352 int i;
2553 u32 val; 2353 u32 val;
2554 2354
2555 ath10k_dbg(ATH10K_DBG_BOOT, "boot cold reset\n"); 2355 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset\n");
2556
2557 ret = ath10k_do_pci_wake(ar);
2558 if (ret) {
2559 ath10k_err("failed to wake up target: %d\n",
2560 ret);
2561 return ret;
2562 }
2563 2356
2564 /* Put Target, including PCIe, into RESET. */ 2357 /* Put Target, including PCIe, into RESET. */
2565 val = ath10k_pci_reg_read32(ar, SOC_GLOBAL_RESET_ADDRESS); 2358 val = ath10k_pci_reg_read32(ar, SOC_GLOBAL_RESET_ADDRESS);
@@ -2584,169 +2377,198 @@ static int ath10k_pci_cold_reset(struct ath10k *ar)
2584 msleep(1); 2377 msleep(1);
2585 } 2378 }
2586 2379
2587 ath10k_do_pci_sleep(ar); 2380 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset complete\n");
2588
2589 ath10k_dbg(ATH10K_DBG_BOOT, "boot cold reset complete\n");
2590 2381
2591 return 0; 2382 return 0;
2592} 2383}
2593 2384
2594static void ath10k_pci_dump_features(struct ath10k_pci *ar_pci) 2385static int ath10k_pci_claim(struct ath10k *ar)
2595{
2596 int i;
2597
2598 for (i = 0; i < ATH10K_PCI_FEATURE_COUNT; i++) {
2599 if (!test_bit(i, ar_pci->features))
2600 continue;
2601
2602 switch (i) {
2603 case ATH10K_PCI_FEATURE_MSI_X:
2604 ath10k_dbg(ATH10K_DBG_BOOT, "device supports MSI-X\n");
2605 break;
2606 case ATH10K_PCI_FEATURE_SOC_POWER_SAVE:
2607 ath10k_dbg(ATH10K_DBG_BOOT, "QCA98XX SoC power save enabled\n");
2608 break;
2609 }
2610 }
2611}
2612
2613static int ath10k_pci_probe(struct pci_dev *pdev,
2614 const struct pci_device_id *pci_dev)
2615{ 2386{
2616 void __iomem *mem; 2387 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2617 int ret = 0; 2388 struct pci_dev *pdev = ar_pci->pdev;
2618 struct ath10k *ar; 2389 u32 lcr_val;
2619 struct ath10k_pci *ar_pci; 2390 int ret;
2620 u32 lcr_val, chip_id;
2621
2622 ath10k_dbg(ATH10K_DBG_PCI, "pci probe\n");
2623
2624 ar_pci = kzalloc(sizeof(*ar_pci), GFP_KERNEL);
2625 if (ar_pci == NULL)
2626 return -ENOMEM;
2627
2628 ar_pci->pdev = pdev;
2629 ar_pci->dev = &pdev->dev;
2630
2631 switch (pci_dev->device) {
2632 case QCA988X_2_0_DEVICE_ID:
2633 set_bit(ATH10K_PCI_FEATURE_MSI_X, ar_pci->features);
2634 break;
2635 default:
2636 ret = -ENODEV;
2637 ath10k_err("Unknown device ID: %d\n", pci_dev->device);
2638 goto err_ar_pci;
2639 }
2640
2641 if (ath10k_pci_target_ps)
2642 set_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features);
2643
2644 ath10k_pci_dump_features(ar_pci);
2645
2646 ar = ath10k_core_create(ar_pci, ar_pci->dev, &ath10k_pci_hif_ops);
2647 if (!ar) {
2648 ath10k_err("failed to create driver core\n");
2649 ret = -EINVAL;
2650 goto err_ar_pci;
2651 }
2652
2653 ar_pci->ar = ar;
2654 atomic_set(&ar_pci->keep_awake_count, 0);
2655 2391
2656 pci_set_drvdata(pdev, ar); 2392 pci_set_drvdata(pdev, ar);
2657 2393
2658 ret = pci_enable_device(pdev); 2394 ret = pci_enable_device(pdev);
2659 if (ret) { 2395 if (ret) {
2660 ath10k_err("failed to enable PCI device: %d\n", ret); 2396 ath10k_err(ar, "failed to enable pci device: %d\n", ret);
2661 goto err_ar; 2397 return ret;
2662 } 2398 }
2663 2399
2664 /* Request MMIO resources */
2665 ret = pci_request_region(pdev, BAR_NUM, "ath"); 2400 ret = pci_request_region(pdev, BAR_NUM, "ath");
2666 if (ret) { 2401 if (ret) {
2667 ath10k_err("failed to request MMIO region: %d\n", ret); 2402 ath10k_err(ar, "failed to request region BAR%d: %d\n", BAR_NUM,
2403 ret);
2668 goto err_device; 2404 goto err_device;
2669 } 2405 }
2670 2406
2671 /* 2407 /* Target expects 32 bit DMA. Enforce it. */
2672 * Target structures have a limit of 32 bit DMA pointers.
2673 * DMA pointers can be wider than 32 bits by default on some systems.
2674 */
2675 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 2408 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2676 if (ret) { 2409 if (ret) {
2677 ath10k_err("failed to set DMA mask to 32-bit: %d\n", ret); 2410 ath10k_err(ar, "failed to set dma mask to 32-bit: %d\n", ret);
2678 goto err_region; 2411 goto err_region;
2679 } 2412 }
2680 2413
2681 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 2414 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2682 if (ret) { 2415 if (ret) {
2683 ath10k_err("failed to set consistent DMA mask to 32-bit\n"); 2416 ath10k_err(ar, "failed to set consistent dma mask to 32-bit: %d\n",
2417 ret);
2684 goto err_region; 2418 goto err_region;
2685 } 2419 }
2686 2420
2687 /* Set bus master bit in PCI_COMMAND to enable DMA */
2688 pci_set_master(pdev); 2421 pci_set_master(pdev);
2689 2422
2690 /* 2423 /* Workaround: Disable ASPM */
2691 * Temporary FIX: disable ASPM
2692 * Will be removed after the OTP is programmed
2693 */
2694 pci_read_config_dword(pdev, 0x80, &lcr_val); 2424 pci_read_config_dword(pdev, 0x80, &lcr_val);
2695 pci_write_config_dword(pdev, 0x80, (lcr_val & 0xffffff00)); 2425 pci_write_config_dword(pdev, 0x80, (lcr_val & 0xffffff00));
2696 2426
2697 /* Arrange for access to Target SoC registers. */ 2427 /* Arrange for access to Target SoC registers. */
2698 mem = pci_iomap(pdev, BAR_NUM, 0); 2428 ar_pci->mem = pci_iomap(pdev, BAR_NUM, 0);
2699 if (!mem) { 2429 if (!ar_pci->mem) {
2700 ath10k_err("failed to perform IOMAP for BAR%d\n", BAR_NUM); 2430 ath10k_err(ar, "failed to iomap BAR%d\n", BAR_NUM);
2701 ret = -EIO; 2431 ret = -EIO;
2702 goto err_master; 2432 goto err_master;
2703 } 2433 }
2704 2434
2705 ar_pci->mem = mem; 2435 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot pci_mem 0x%p\n", ar_pci->mem);
2436 return 0;
2437
2438err_master:
2439 pci_clear_master(pdev);
2440
2441err_region:
2442 pci_release_region(pdev, BAR_NUM);
2443
2444err_device:
2445 pci_disable_device(pdev);
2446
2447 return ret;
2448}
2449
2450static void ath10k_pci_release(struct ath10k *ar)
2451{
2452 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2453 struct pci_dev *pdev = ar_pci->pdev;
2454
2455 pci_iounmap(pdev, ar_pci->mem);
2456 pci_release_region(pdev, BAR_NUM);
2457 pci_clear_master(pdev);
2458 pci_disable_device(pdev);
2459}
2460
2461static int ath10k_pci_probe(struct pci_dev *pdev,
2462 const struct pci_device_id *pci_dev)
2463{
2464 int ret = 0;
2465 struct ath10k *ar;
2466 struct ath10k_pci *ar_pci;
2467 u32 chip_id;
2468
2469 ar = ath10k_core_create(sizeof(*ar_pci), &pdev->dev,
2470 &ath10k_pci_hif_ops);
2471 if (!ar) {
2472 dev_err(&pdev->dev, "failed to allocate core\n");
2473 return -ENOMEM;
2474 }
2475
2476 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci probe\n");
2477
2478 ar_pci = ath10k_pci_priv(ar);
2479 ar_pci->pdev = pdev;
2480 ar_pci->dev = &pdev->dev;
2481 ar_pci->ar = ar;
2706 2482
2707 spin_lock_init(&ar_pci->ce_lock); 2483 spin_lock_init(&ar_pci->ce_lock);
2484 setup_timer(&ar_pci->rx_post_retry, ath10k_pci_rx_replenish_retry,
2485 (unsigned long)ar);
2708 2486
2709 ret = ath10k_do_pci_wake(ar); 2487 ret = ath10k_pci_claim(ar);
2710 if (ret) { 2488 if (ret) {
2711 ath10k_err("Failed to get chip id: %d\n", ret); 2489 ath10k_err(ar, "failed to claim device: %d\n", ret);
2712 goto err_iomap; 2490 goto err_core_destroy;
2713 } 2491 }
2714 2492
2715 chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS); 2493 ret = ath10k_pci_wake(ar);
2494 if (ret) {
2495 ath10k_err(ar, "failed to wake up: %d\n", ret);
2496 goto err_release;
2497 }
2716 2498
2717 ath10k_do_pci_sleep(ar); 2499 chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
2500 if (chip_id == 0xffffffff) {
2501 ath10k_err(ar, "failed to get chip id\n");
2502 goto err_sleep;
2503 }
2718 2504
2719 ret = ath10k_pci_alloc_ce(ar); 2505 ret = ath10k_pci_alloc_ce(ar);
2720 if (ret) { 2506 if (ret) {
2721 ath10k_err("failed to allocate copy engine pipes: %d\n", ret); 2507 ath10k_err(ar, "failed to allocate copy engine pipes: %d\n",
2722 goto err_iomap; 2508 ret);
2509 goto err_sleep;
2723 } 2510 }
2724 2511
2725 ath10k_dbg(ATH10K_DBG_BOOT, "boot pci_mem 0x%p\n", ar_pci->mem); 2512 ath10k_pci_ce_deinit(ar);
2726 2513
2727 ret = ath10k_core_register(ar, chip_id); 2514 ret = ath10k_ce_disable_interrupts(ar);
2515 if (ret) {
2516 ath10k_err(ar, "failed to disable copy engine interrupts: %d\n",
2517 ret);
2518 goto err_free_ce;
2519 }
2520
2521 /* Workaround: There's no known way to mask all possible interrupts via
2522 * device CSR. The only way to make sure device doesn't assert
2523 * interrupts is to reset it. Interrupts are then disabled on host
2524 * after handlers are registered.
2525 */
2526 ath10k_pci_warm_reset(ar);
2527
2528 ret = ath10k_pci_init_irq(ar);
2728 if (ret) { 2529 if (ret) {
2729 ath10k_err("failed to register driver core: %d\n", ret); 2530 ath10k_err(ar, "failed to init irqs: %d\n", ret);
2730 goto err_free_ce; 2531 goto err_free_ce;
2731 } 2532 }
2732 2533
2534 ath10k_info(ar, "pci irq %s interrupts %d irq_mode %d reset_mode %d\n",
2535 ath10k_pci_get_irq_method(ar), ar_pci->num_msi_intrs,
2536 ath10k_pci_irq_mode, ath10k_pci_reset_mode);
2537
2538 ret = ath10k_pci_request_irq(ar);
2539 if (ret) {
2540 ath10k_warn(ar, "failed to request irqs: %d\n", ret);
2541 goto err_deinit_irq;
2542 }
2543
2544 /* This shouldn't race as the device has been reset above. */
2545 ath10k_pci_irq_disable(ar);
2546
2547 ret = ath10k_core_register(ar, chip_id);
2548 if (ret) {
2549 ath10k_err(ar, "failed to register driver core: %d\n", ret);
2550 goto err_free_irq;
2551 }
2552
2733 return 0; 2553 return 0;
2734 2554
2555err_free_irq:
2556 ath10k_pci_free_irq(ar);
2557
2558err_deinit_irq:
2559 ath10k_pci_deinit_irq(ar);
2560
2735err_free_ce: 2561err_free_ce:
2736 ath10k_pci_free_ce(ar); 2562 ath10k_pci_free_ce(ar);
2737err_iomap: 2563
2738 pci_iounmap(pdev, mem); 2564err_sleep:
2739err_master: 2565 ath10k_pci_sleep(ar);
2740 pci_clear_master(pdev); 2566
2741err_region: 2567err_release:
2742 pci_release_region(pdev, BAR_NUM); 2568 ath10k_pci_release(ar);
2743err_device: 2569
2744 pci_disable_device(pdev); 2570err_core_destroy:
2745err_ar:
2746 ath10k_core_destroy(ar); 2571 ath10k_core_destroy(ar);
2747err_ar_pci:
2748 /* call HIF PCI free here */
2749 kfree(ar_pci);
2750 2572
2751 return ret; 2573 return ret;
2752} 2574}
@@ -2756,7 +2578,7 @@ static void ath10k_pci_remove(struct pci_dev *pdev)
2756 struct ath10k *ar = pci_get_drvdata(pdev); 2578 struct ath10k *ar = pci_get_drvdata(pdev);
2757 struct ath10k_pci *ar_pci; 2579 struct ath10k_pci *ar_pci;
2758 2580
2759 ath10k_dbg(ATH10K_DBG_PCI, "pci remove\n"); 2581 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci remove\n");
2760 2582
2761 if (!ar) 2583 if (!ar)
2762 return; 2584 return;
@@ -2767,15 +2589,13 @@ static void ath10k_pci_remove(struct pci_dev *pdev)
2767 return; 2589 return;
2768 2590
2769 ath10k_core_unregister(ar); 2591 ath10k_core_unregister(ar);
2592 ath10k_pci_free_irq(ar);
2593 ath10k_pci_deinit_irq(ar);
2594 ath10k_pci_ce_deinit(ar);
2770 ath10k_pci_free_ce(ar); 2595 ath10k_pci_free_ce(ar);
2771 2596 ath10k_pci_sleep(ar);
2772 pci_iounmap(pdev, ar_pci->mem); 2597 ath10k_pci_release(ar);
2773 pci_release_region(pdev, BAR_NUM);
2774 pci_clear_master(pdev);
2775 pci_disable_device(pdev);
2776
2777 ath10k_core_destroy(ar); 2598 ath10k_core_destroy(ar);
2778 kfree(ar_pci);
2779} 2599}
2780 2600
2781MODULE_DEVICE_TABLE(pci, ath10k_pci_id_table); 2601MODULE_DEVICE_TABLE(pci, ath10k_pci_id_table);
@@ -2793,7 +2613,8 @@ static int __init ath10k_pci_init(void)
2793 2613
2794 ret = pci_register_driver(&ath10k_pci_driver); 2614 ret = pci_register_driver(&ath10k_pci_driver);
2795 if (ret) 2615 if (ret)
2796 ath10k_err("failed to register PCI driver: %d\n", ret); 2616 printk(KERN_ERR "failed to register ath10k pci driver: %d\n",
2617 ret);
2797 2618
2798 return ret; 2619 return ret;
2799} 2620}
@@ -2809,5 +2630,5 @@ module_exit(ath10k_pci_exit);
2809MODULE_AUTHOR("Qualcomm Atheros"); 2630MODULE_AUTHOR("Qualcomm Atheros");
2810MODULE_DESCRIPTION("Driver support for Atheros QCA988X PCIe devices"); 2631MODULE_DESCRIPTION("Driver support for Atheros QCA988X PCIe devices");
2811MODULE_LICENSE("Dual BSD/GPL"); 2632MODULE_LICENSE("Dual BSD/GPL");
2812MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_FW_2_FILE); 2633MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_FW_3_FILE);
2813MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_BOARD_DATA_FILE); 2634MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_BOARD_DATA_FILE);
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-26 10:04:40 -0400