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path: root/drivers/net/vxge/vxge-traffic.c
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Diffstat (limited to 'drivers/net/vxge/vxge-traffic.c')
-rw-r--r--drivers/net/vxge/vxge-traffic.c28
1 files changed, 0 insertions, 28 deletions
diff --git a/drivers/net/vxge/vxge-traffic.c b/drivers/net/vxge/vxge-traffic.c
index f83e6aee3f6a..6cc1dd79b40b 100644
--- a/drivers/net/vxge/vxge-traffic.c
+++ b/drivers/net/vxge/vxge-traffic.c
@@ -233,8 +233,6 @@ void vxge_hw_channel_msix_mask(struct __vxge_hw_channel *channel, int msix_id)
233 __vxge_hw_pio_mem_write32_upper( 233 __vxge_hw_pio_mem_write32_upper(
234 (u32)vxge_bVALn(vxge_mBIT(msix_id >> 2), 0, 32), 234 (u32)vxge_bVALn(vxge_mBIT(msix_id >> 2), 0, 32),
235 &channel->common_reg->set_msix_mask_vect[msix_id%4]); 235 &channel->common_reg->set_msix_mask_vect[msix_id%4]);
236
237 return;
238} 236}
239 237
240/** 238/**
@@ -253,8 +251,6 @@ vxge_hw_channel_msix_unmask(struct __vxge_hw_channel *channel, int msix_id)
253 __vxge_hw_pio_mem_write32_upper( 251 __vxge_hw_pio_mem_write32_upper(
254 (u32)vxge_bVALn(vxge_mBIT(msix_id >> 2), 0, 32), 252 (u32)vxge_bVALn(vxge_mBIT(msix_id >> 2), 0, 32),
255 &channel->common_reg->clear_msix_mask_vect[msix_id%4]); 253 &channel->common_reg->clear_msix_mask_vect[msix_id%4]);
256
257 return;
258} 254}
259 255
260/** 256/**
@@ -329,8 +325,6 @@ void vxge_hw_device_intr_enable(struct __vxge_hw_device *hldev)
329 val64 = readq(&hldev->common_reg->titan_general_int_status); 325 val64 = readq(&hldev->common_reg->titan_general_int_status);
330 326
331 vxge_hw_device_unmask_all(hldev); 327 vxge_hw_device_unmask_all(hldev);
332
333 return;
334} 328}
335 329
336/** 330/**
@@ -362,8 +356,6 @@ void vxge_hw_device_intr_disable(struct __vxge_hw_device *hldev)
362 vxge_hw_vpath_intr_disable( 356 vxge_hw_vpath_intr_disable(
363 VXGE_HW_VIRTUAL_PATH_HANDLE(&hldev->virtual_paths[i])); 357 VXGE_HW_VIRTUAL_PATH_HANDLE(&hldev->virtual_paths[i]));
364 } 358 }
365
366 return;
367} 359}
368 360
369/** 361/**
@@ -383,8 +375,6 @@ void vxge_hw_device_mask_all(struct __vxge_hw_device *hldev)
383 375
384 __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32), 376 __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32),
385 &hldev->common_reg->titan_mask_all_int); 377 &hldev->common_reg->titan_mask_all_int);
386
387 return;
388} 378}
389 379
390/** 380/**
@@ -404,8 +394,6 @@ void vxge_hw_device_unmask_all(struct __vxge_hw_device *hldev)
404 394
405 __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32), 395 __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32),
406 &hldev->common_reg->titan_mask_all_int); 396 &hldev->common_reg->titan_mask_all_int);
407
408 return;
409} 397}
410 398
411/** 399/**
@@ -647,8 +635,6 @@ void vxge_hw_device_clear_tx_rx(struct __vxge_hw_device *hldev)
647 hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_RX]), 635 hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_RX]),
648 &hldev->common_reg->tim_int_status1); 636 &hldev->common_reg->tim_int_status1);
649 } 637 }
650
651 return;
652} 638}
653 639
654/* 640/*
@@ -2255,8 +2241,6 @@ vxge_hw_vpath_msix_set(struct __vxge_hw_vpath_handle *vp, int *tim_msix_id,
2255 VXGE_HW_ONE_SHOT_VECT3_EN_ONE_SHOT_VECT3_EN, 2241 VXGE_HW_ONE_SHOT_VECT3_EN_ONE_SHOT_VECT3_EN,
2256 0, 32), &vp_reg->one_shot_vect3_en); 2242 0, 32), &vp_reg->one_shot_vect3_en);
2257 } 2243 }
2258
2259 return;
2260} 2244}
2261 2245
2262/** 2246/**
@@ -2278,8 +2262,6 @@ vxge_hw_vpath_msix_mask(struct __vxge_hw_vpath_handle *vp, int msix_id)
2278 __vxge_hw_pio_mem_write32_upper( 2262 __vxge_hw_pio_mem_write32_upper(
2279 (u32) vxge_bVALn(vxge_mBIT(msix_id >> 2), 0, 32), 2263 (u32) vxge_bVALn(vxge_mBIT(msix_id >> 2), 0, 32),
2280 &hldev->common_reg->set_msix_mask_vect[msix_id % 4]); 2264 &hldev->common_reg->set_msix_mask_vect[msix_id % 4]);
2281
2282 return;
2283} 2265}
2284 2266
2285/** 2267/**
@@ -2310,8 +2292,6 @@ vxge_hw_vpath_msix_clear(struct __vxge_hw_vpath_handle *vp, int msix_id)
2310 &hldev->common_reg-> 2292 &hldev->common_reg->
2311 clear_msix_mask_vect[msix_id%4]); 2293 clear_msix_mask_vect[msix_id%4]);
2312 } 2294 }
2313
2314 return;
2315} 2295}
2316 2296
2317/** 2297/**
@@ -2333,8 +2313,6 @@ vxge_hw_vpath_msix_unmask(struct __vxge_hw_vpath_handle *vp, int msix_id)
2333 __vxge_hw_pio_mem_write32_upper( 2313 __vxge_hw_pio_mem_write32_upper(
2334 (u32)vxge_bVALn(vxge_mBIT(msix_id >> 2), 0, 32), 2314 (u32)vxge_bVALn(vxge_mBIT(msix_id >> 2), 0, 32),
2335 &hldev->common_reg->clear_msix_mask_vect[msix_id%4]); 2315 &hldev->common_reg->clear_msix_mask_vect[msix_id%4]);
2336
2337 return;
2338} 2316}
2339 2317
2340/** 2318/**
@@ -2351,8 +2329,6 @@ vxge_hw_vpath_msix_mask_all(struct __vxge_hw_vpath_handle *vp)
2351 __vxge_hw_pio_mem_write32_upper( 2329 __vxge_hw_pio_mem_write32_upper(
2352 (u32)vxge_bVALn(vxge_mBIT(vp->vpath->vp_id), 0, 32), 2330 (u32)vxge_bVALn(vxge_mBIT(vp->vpath->vp_id), 0, 32),
2353 &vp->vpath->hldev->common_reg->set_msix_mask_all_vect); 2331 &vp->vpath->hldev->common_reg->set_msix_mask_all_vect);
2354
2355 return;
2356} 2332}
2357 2333
2358/** 2334/**
@@ -2391,8 +2367,6 @@ void vxge_hw_vpath_inta_mask_tx_rx(struct __vxge_hw_vpath_handle *vp)
2391 tim_int_mask1[VXGE_HW_VPATH_INTR_RX] | val64), 2367 tim_int_mask1[VXGE_HW_VPATH_INTR_RX] | val64),
2392 &hldev->common_reg->tim_int_mask1); 2368 &hldev->common_reg->tim_int_mask1);
2393 } 2369 }
2394
2395 return;
2396} 2370}
2397 2371
2398/** 2372/**
@@ -2429,8 +2403,6 @@ void vxge_hw_vpath_inta_unmask_tx_rx(struct __vxge_hw_vpath_handle *vp)
2429 tim_int_mask1[VXGE_HW_VPATH_INTR_RX])) & val64, 2403 tim_int_mask1[VXGE_HW_VPATH_INTR_RX])) & val64,
2430 &hldev->common_reg->tim_int_mask1); 2404 &hldev->common_reg->tim_int_mask1);
2431 } 2405 }
2432
2433 return;
2434} 2406}
2435 2407
2436/** 2408/**