1 files changed, 10 insertions, 20 deletions

diff --git a/drivers/net/vxge/vxge-config.c b/drivers/net/vxge/vxge-config.c
index da35562ba48c..77097e383cf4 100644
--- a/drivers/net/vxge/vxge-config.c
+++ b/drivers/net/vxge/vxge-config.c
@@ -2868,6 +2868,8 @@ __vxge_hw_ring_create(struct __vxge_hw_vpath_handle *vp,
         ring->rxd_init = attr->rxd_init;
         ring->rxd_term = attr->rxd_term;
         ring->buffer_mode = config->buffer_mode;
+        ring->tim_rti_cfg1_saved = vp->vpath->tim_rti_cfg1_saved;
+        ring->tim_rti_cfg3_saved = vp->vpath->tim_rti_cfg3_saved;
         ring->rxds_limit = config->rxds_limit;
 
         ring->rxd_size = vxge_hw_ring_rxd_size_get(config->buffer_mode);
@@ -3511,6 +3513,8 @@ __vxge_hw_fifo_create(struct __vxge_hw_vpath_handle *vp,
 
         /* apply "interrupts per txdl" attribute */
         fifo->interrupt_type = VXGE_HW_FIFO_TXD_INT_TYPE_UTILZ;
+        fifo->tim_tti_cfg1_saved = vpath->tim_tti_cfg1_saved;
+        fifo->tim_tti_cfg3_saved = vpath->tim_tti_cfg3_saved;
 
         if (fifo->config->intr)
                 fifo->interrupt_type = VXGE_HW_FIFO_TXD_INT_TYPE_PER_LIST;
@@ -4377,6 +4381,8 @@ __vxge_hw_vpath_tim_configure(struct __vxge_hw_device *hldev, u32 vp_id)
                 }
 
                 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
+                vpath->tim_tti_cfg1_saved = val64;
+
                 val64 = readq(&vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_TX]);
 
                 if (config->tti.uec_a != VXGE_HW_USE_FLASH_DEFAULT) {
@@ -4433,6 +4439,7 @@ __vxge_hw_vpath_tim_configure(struct __vxge_hw_device *hldev, u32 vp_id)
                 }
 
                 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]);
+                vpath->tim_tti_cfg3_saved = val64;
         }
 
         if (config->ring.enable == VXGE_HW_RING_ENABLE) {
@@ -4481,6 +4488,8 @@ __vxge_hw_vpath_tim_configure(struct __vxge_hw_device *hldev, u32 vp_id)
                 }
 
                 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]);
+                vpath->tim_rti_cfg1_saved = val64;
+
                 val64 = readq(&vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_RX]);
 
                 if (config->rti.uec_a != VXGE_HW_USE_FLASH_DEFAULT) {
@@ -4537,6 +4546,7 @@ __vxge_hw_vpath_tim_configure(struct __vxge_hw_device *hldev, u32 vp_id)
                 }
 
                 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]);
+                vpath->tim_rti_cfg3_saved = val64;
         }
 
         val64 = 0;
@@ -4555,26 +4565,6 @@ __vxge_hw_vpath_tim_configure(struct __vxge_hw_device *hldev, u32 vp_id)
         return status;
 }
 
-void vxge_hw_vpath_tti_ci_set(struct __vxge_hw_device *hldev, u32 vp_id)
-{
-        struct __vxge_hw_virtualpath *vpath;
-        struct vxge_hw_vpath_reg __iomem *vp_reg;
-        struct vxge_hw_vp_config *config;
-        u64 val64;
-
-        vpath = &hldev->virtual_paths[vp_id];
-        vp_reg = vpath->vp_reg;
-        config = vpath->vp_config;
-
-        if (config->fifo.enable == VXGE_HW_FIFO_ENABLE &&
-            config->tti.timer_ci_en != VXGE_HW_TIM_TIMER_CI_ENABLE) {
-                config->tti.timer_ci_en = VXGE_HW_TIM_TIMER_CI_ENABLE;
-                val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
-                val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
-                writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
-        }
-}
-
 /*
  * __vxge_hw_vpath_initialize
  * This routine is the final phase of init which initializes the