diff options
Diffstat (limited to 'drivers/net/via-velocity.c')
-rw-r--r-- | drivers/net/via-velocity.c | 114 |
1 files changed, 57 insertions, 57 deletions
diff --git a/drivers/net/via-velocity.c b/drivers/net/via-velocity.c index 91f3b841288c..078903f10f02 100644 --- a/drivers/net/via-velocity.c +++ b/drivers/net/via-velocity.c | |||
@@ -719,30 +719,30 @@ static u32 mii_check_media_mode(struct mac_regs __iomem *regs) | |||
719 | u32 status = 0; | 719 | u32 status = 0; |
720 | u16 ANAR; | 720 | u16 ANAR; |
721 | 721 | ||
722 | if (!MII_REG_BITS_IS_ON(BMSR_LNK, MII_REG_BMSR, regs)) | 722 | if (!MII_REG_BITS_IS_ON(BMSR_LSTATUS, MII_BMSR, regs)) |
723 | status |= VELOCITY_LINK_FAIL; | 723 | status |= VELOCITY_LINK_FAIL; |
724 | 724 | ||
725 | if (MII_REG_BITS_IS_ON(G1000CR_1000FD, MII_REG_G1000CR, regs)) | 725 | if (MII_REG_BITS_IS_ON(ADVERTISE_1000FULL, MII_CTRL1000, regs)) |
726 | status |= VELOCITY_SPEED_1000 | VELOCITY_DUPLEX_FULL; | 726 | status |= VELOCITY_SPEED_1000 | VELOCITY_DUPLEX_FULL; |
727 | else if (MII_REG_BITS_IS_ON(G1000CR_1000, MII_REG_G1000CR, regs)) | 727 | else if (MII_REG_BITS_IS_ON(ADVERTISE_1000HALF, MII_CTRL1000, regs)) |
728 | status |= (VELOCITY_SPEED_1000); | 728 | status |= (VELOCITY_SPEED_1000); |
729 | else { | 729 | else { |
730 | velocity_mii_read(regs, MII_REG_ANAR, &ANAR); | 730 | velocity_mii_read(regs, MII_ADVERTISE, &ANAR); |
731 | if (ANAR & ANAR_TXFD) | 731 | if (ANAR & ADVERTISE_100FULL) |
732 | status |= (VELOCITY_SPEED_100 | VELOCITY_DUPLEX_FULL); | 732 | status |= (VELOCITY_SPEED_100 | VELOCITY_DUPLEX_FULL); |
733 | else if (ANAR & ANAR_TX) | 733 | else if (ANAR & ADVERTISE_100HALF) |
734 | status |= VELOCITY_SPEED_100; | 734 | status |= VELOCITY_SPEED_100; |
735 | else if (ANAR & ANAR_10FD) | 735 | else if (ANAR & ADVERTISE_10FULL) |
736 | status |= (VELOCITY_SPEED_10 | VELOCITY_DUPLEX_FULL); | 736 | status |= (VELOCITY_SPEED_10 | VELOCITY_DUPLEX_FULL); |
737 | else | 737 | else |
738 | status |= (VELOCITY_SPEED_10); | 738 | status |= (VELOCITY_SPEED_10); |
739 | } | 739 | } |
740 | 740 | ||
741 | if (MII_REG_BITS_IS_ON(BMCR_AUTO, MII_REG_BMCR, regs)) { | 741 | if (MII_REG_BITS_IS_ON(BMCR_ANENABLE, MII_BMCR, regs)) { |
742 | velocity_mii_read(regs, MII_REG_ANAR, &ANAR); | 742 | velocity_mii_read(regs, MII_ADVERTISE, &ANAR); |
743 | if ((ANAR & (ANAR_TXFD | ANAR_TX | ANAR_10FD | ANAR_10)) | 743 | if ((ANAR & (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF)) |
744 | == (ANAR_TXFD | ANAR_TX | ANAR_10FD | ANAR_10)) { | 744 | == (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF)) { |
745 | if (MII_REG_BITS_IS_ON(G1000CR_1000 | G1000CR_1000FD, MII_REG_G1000CR, regs)) | 745 | if (MII_REG_BITS_IS_ON(ADVERTISE_1000HALF | ADVERTISE_1000FULL, MII_CTRL1000, regs)) |
746 | status |= VELOCITY_AUTONEG_ENABLE; | 746 | status |= VELOCITY_AUTONEG_ENABLE; |
747 | } | 747 | } |
748 | } | 748 | } |
@@ -801,23 +801,23 @@ static void set_mii_flow_control(struct velocity_info *vptr) | |||
801 | /*Enable or Disable PAUSE in ANAR */ | 801 | /*Enable or Disable PAUSE in ANAR */ |
802 | switch (vptr->options.flow_cntl) { | 802 | switch (vptr->options.flow_cntl) { |
803 | case FLOW_CNTL_TX: | 803 | case FLOW_CNTL_TX: |
804 | MII_REG_BITS_OFF(ANAR_PAUSE, MII_REG_ANAR, vptr->mac_regs); | 804 | MII_REG_BITS_OFF(ADVERTISE_PAUSE_CAP, MII_ADVERTISE, vptr->mac_regs); |
805 | MII_REG_BITS_ON(ANAR_ASMDIR, MII_REG_ANAR, vptr->mac_regs); | 805 | MII_REG_BITS_ON(ADVERTISE_PAUSE_ASYM, MII_ADVERTISE, vptr->mac_regs); |
806 | break; | 806 | break; |
807 | 807 | ||
808 | case FLOW_CNTL_RX: | 808 | case FLOW_CNTL_RX: |
809 | MII_REG_BITS_ON(ANAR_PAUSE, MII_REG_ANAR, vptr->mac_regs); | 809 | MII_REG_BITS_ON(ADVERTISE_PAUSE_CAP, MII_ADVERTISE, vptr->mac_regs); |
810 | MII_REG_BITS_ON(ANAR_ASMDIR, MII_REG_ANAR, vptr->mac_regs); | 810 | MII_REG_BITS_ON(ADVERTISE_PAUSE_ASYM, MII_ADVERTISE, vptr->mac_regs); |
811 | break; | 811 | break; |
812 | 812 | ||
813 | case FLOW_CNTL_TX_RX: | 813 | case FLOW_CNTL_TX_RX: |
814 | MII_REG_BITS_ON(ANAR_PAUSE, MII_REG_ANAR, vptr->mac_regs); | 814 | MII_REG_BITS_ON(ADVERTISE_PAUSE_CAP, MII_ADVERTISE, vptr->mac_regs); |
815 | MII_REG_BITS_ON(ANAR_ASMDIR, MII_REG_ANAR, vptr->mac_regs); | 815 | MII_REG_BITS_ON(ADVERTISE_PAUSE_ASYM, MII_ADVERTISE, vptr->mac_regs); |
816 | break; | 816 | break; |
817 | 817 | ||
818 | case FLOW_CNTL_DISABLE: | 818 | case FLOW_CNTL_DISABLE: |
819 | MII_REG_BITS_OFF(ANAR_PAUSE, MII_REG_ANAR, vptr->mac_regs); | 819 | MII_REG_BITS_OFF(ADVERTISE_PAUSE_CAP, MII_ADVERTISE, vptr->mac_regs); |
820 | MII_REG_BITS_OFF(ANAR_ASMDIR, MII_REG_ANAR, vptr->mac_regs); | 820 | MII_REG_BITS_OFF(ADVERTISE_PAUSE_ASYM, MII_ADVERTISE, vptr->mac_regs); |
821 | break; | 821 | break; |
822 | default: | 822 | default: |
823 | break; | 823 | break; |
@@ -832,10 +832,10 @@ static void set_mii_flow_control(struct velocity_info *vptr) | |||
832 | */ | 832 | */ |
833 | static void mii_set_auto_on(struct velocity_info *vptr) | 833 | static void mii_set_auto_on(struct velocity_info *vptr) |
834 | { | 834 | { |
835 | if (MII_REG_BITS_IS_ON(BMCR_AUTO, MII_REG_BMCR, vptr->mac_regs)) | 835 | if (MII_REG_BITS_IS_ON(BMCR_ANENABLE, MII_BMCR, vptr->mac_regs)) |
836 | MII_REG_BITS_ON(BMCR_REAUTO, MII_REG_BMCR, vptr->mac_regs); | 836 | MII_REG_BITS_ON(BMCR_ANRESTART, MII_BMCR, vptr->mac_regs); |
837 | else | 837 | else |
838 | MII_REG_BITS_ON(BMCR_AUTO, MII_REG_BMCR, vptr->mac_regs); | 838 | MII_REG_BITS_ON(BMCR_ANENABLE, MII_BMCR, vptr->mac_regs); |
839 | } | 839 | } |
840 | 840 | ||
841 | static u32 check_connection_type(struct mac_regs __iomem *regs) | 841 | static u32 check_connection_type(struct mac_regs __iomem *regs) |
@@ -860,11 +860,11 @@ static u32 check_connection_type(struct mac_regs __iomem *regs) | |||
860 | else | 860 | else |
861 | status |= VELOCITY_SPEED_100; | 861 | status |= VELOCITY_SPEED_100; |
862 | 862 | ||
863 | if (MII_REG_BITS_IS_ON(BMCR_AUTO, MII_REG_BMCR, regs)) { | 863 | if (MII_REG_BITS_IS_ON(BMCR_ANENABLE, MII_BMCR, regs)) { |
864 | velocity_mii_read(regs, MII_REG_ANAR, &ANAR); | 864 | velocity_mii_read(regs, MII_ADVERTISE, &ANAR); |
865 | if ((ANAR & (ANAR_TXFD | ANAR_TX | ANAR_10FD | ANAR_10)) | 865 | if ((ANAR & (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF)) |
866 | == (ANAR_TXFD | ANAR_TX | ANAR_10FD | ANAR_10)) { | 866 | == (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF)) { |
867 | if (MII_REG_BITS_IS_ON(G1000CR_1000 | G1000CR_1000FD, MII_REG_G1000CR, regs)) | 867 | if (MII_REG_BITS_IS_ON(ADVERTISE_1000HALF | ADVERTISE_1000FULL, MII_CTRL1000, regs)) |
868 | status |= VELOCITY_AUTONEG_ENABLE; | 868 | status |= VELOCITY_AUTONEG_ENABLE; |
869 | } | 869 | } |
870 | } | 870 | } |
@@ -905,7 +905,7 @@ static int velocity_set_media_mode(struct velocity_info *vptr, u32 mii_status) | |||
905 | */ | 905 | */ |
906 | 906 | ||
907 | if (PHYID_GET_PHY_ID(vptr->phy_id) == PHYID_CICADA_CS8201) | 907 | if (PHYID_GET_PHY_ID(vptr->phy_id) == PHYID_CICADA_CS8201) |
908 | MII_REG_BITS_ON(AUXCR_MDPPS, MII_REG_AUXCR, vptr->mac_regs); | 908 | MII_REG_BITS_ON(AUXCR_MDPPS, MII_NCONFIG, vptr->mac_regs); |
909 | 909 | ||
910 | /* | 910 | /* |
911 | * If connection type is AUTO | 911 | * If connection type is AUTO |
@@ -915,9 +915,9 @@ static int velocity_set_media_mode(struct velocity_info *vptr, u32 mii_status) | |||
915 | /* clear force MAC mode bit */ | 915 | /* clear force MAC mode bit */ |
916 | BYTE_REG_BITS_OFF(CHIPGCR_FCMODE, ®s->CHIPGCR); | 916 | BYTE_REG_BITS_OFF(CHIPGCR_FCMODE, ®s->CHIPGCR); |
917 | /* set duplex mode of MAC according to duplex mode of MII */ | 917 | /* set duplex mode of MAC according to duplex mode of MII */ |
918 | MII_REG_BITS_ON(ANAR_TXFD | ANAR_TX | ANAR_10FD | ANAR_10, MII_REG_ANAR, vptr->mac_regs); | 918 | MII_REG_BITS_ON(ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF, MII_ADVERTISE, vptr->mac_regs); |
919 | MII_REG_BITS_ON(G1000CR_1000FD | G1000CR_1000, MII_REG_G1000CR, vptr->mac_regs); | 919 | MII_REG_BITS_ON(ADVERTISE_1000FULL | ADVERTISE_1000HALF, MII_CTRL1000, vptr->mac_regs); |
920 | MII_REG_BITS_ON(BMCR_SPEED1G, MII_REG_BMCR, vptr->mac_regs); | 920 | MII_REG_BITS_ON(BMCR_SPEED1000, MII_BMCR, vptr->mac_regs); |
921 | 921 | ||
922 | /* enable AUTO-NEGO mode */ | 922 | /* enable AUTO-NEGO mode */ |
923 | mii_set_auto_on(vptr); | 923 | mii_set_auto_on(vptr); |
@@ -952,31 +952,31 @@ static int velocity_set_media_mode(struct velocity_info *vptr, u32 mii_status) | |||
952 | BYTE_REG_BITS_ON(TCR_TB2BDIS, ®s->TCR); | 952 | BYTE_REG_BITS_ON(TCR_TB2BDIS, ®s->TCR); |
953 | } | 953 | } |
954 | 954 | ||
955 | MII_REG_BITS_OFF(G1000CR_1000FD | G1000CR_1000, MII_REG_G1000CR, vptr->mac_regs); | 955 | MII_REG_BITS_OFF(ADVERTISE_1000FULL | ADVERTISE_1000HALF, MII_CTRL1000, vptr->mac_regs); |
956 | 956 | ||
957 | if (!(mii_status & VELOCITY_DUPLEX_FULL) && (mii_status & VELOCITY_SPEED_10)) | 957 | if (!(mii_status & VELOCITY_DUPLEX_FULL) && (mii_status & VELOCITY_SPEED_10)) |
958 | BYTE_REG_BITS_OFF(TESTCFG_HBDIS, ®s->TESTCFG); | 958 | BYTE_REG_BITS_OFF(TESTCFG_HBDIS, ®s->TESTCFG); |
959 | else | 959 | else |
960 | BYTE_REG_BITS_ON(TESTCFG_HBDIS, ®s->TESTCFG); | 960 | BYTE_REG_BITS_ON(TESTCFG_HBDIS, ®s->TESTCFG); |
961 | 961 | ||
962 | /* MII_REG_BITS_OFF(BMCR_SPEED1G, MII_REG_BMCR, vptr->mac_regs); */ | 962 | /* MII_REG_BITS_OFF(BMCR_SPEED1000, MII_BMCR, vptr->mac_regs); */ |
963 | velocity_mii_read(vptr->mac_regs, MII_REG_ANAR, &ANAR); | 963 | velocity_mii_read(vptr->mac_regs, MII_ADVERTISE, &ANAR); |
964 | ANAR &= (~(ANAR_TXFD | ANAR_TX | ANAR_10FD | ANAR_10)); | 964 | ANAR &= (~(ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF)); |
965 | if (mii_status & VELOCITY_SPEED_100) { | 965 | if (mii_status & VELOCITY_SPEED_100) { |
966 | if (mii_status & VELOCITY_DUPLEX_FULL) | 966 | if (mii_status & VELOCITY_DUPLEX_FULL) |
967 | ANAR |= ANAR_TXFD; | 967 | ANAR |= ADVERTISE_100FULL; |
968 | else | 968 | else |
969 | ANAR |= ANAR_TX; | 969 | ANAR |= ADVERTISE_100HALF; |
970 | } else { | 970 | } else { |
971 | if (mii_status & VELOCITY_DUPLEX_FULL) | 971 | if (mii_status & VELOCITY_DUPLEX_FULL) |
972 | ANAR |= ANAR_10FD; | 972 | ANAR |= ADVERTISE_10FULL; |
973 | else | 973 | else |
974 | ANAR |= ANAR_10; | 974 | ANAR |= ADVERTISE_10HALF; |
975 | } | 975 | } |
976 | velocity_mii_write(vptr->mac_regs, MII_REG_ANAR, ANAR); | 976 | velocity_mii_write(vptr->mac_regs, MII_ADVERTISE, ANAR); |
977 | /* enable AUTO-NEGO mode */ | 977 | /* enable AUTO-NEGO mode */ |
978 | mii_set_auto_on(vptr); | 978 | mii_set_auto_on(vptr); |
979 | /* MII_REG_BITS_ON(BMCR_AUTO, MII_REG_BMCR, vptr->mac_regs); */ | 979 | /* MII_REG_BITS_ON(BMCR_ANENABLE, MII_BMCR, vptr->mac_regs); */ |
980 | } | 980 | } |
981 | /* vptr->mii_status=mii_check_media_mode(vptr->mac_regs); */ | 981 | /* vptr->mii_status=mii_check_media_mode(vptr->mac_regs); */ |
982 | /* vptr->mii_status=check_connection_type(vptr->mac_regs); */ | 982 | /* vptr->mii_status=check_connection_type(vptr->mac_regs); */ |
@@ -1178,36 +1178,36 @@ static void mii_init(struct velocity_info *vptr, u32 mii_status) | |||
1178 | /* | 1178 | /* |
1179 | * Reset to hardware default | 1179 | * Reset to hardware default |
1180 | */ | 1180 | */ |
1181 | MII_REG_BITS_OFF((ANAR_ASMDIR | ANAR_PAUSE), MII_REG_ANAR, vptr->mac_regs); | 1181 | MII_REG_BITS_OFF((ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP), MII_ADVERTISE, vptr->mac_regs); |
1182 | /* | 1182 | /* |
1183 | * Turn on ECHODIS bit in NWay-forced full mode and turn it | 1183 | * Turn on ECHODIS bit in NWay-forced full mode and turn it |
1184 | * off it in NWay-forced half mode for NWay-forced v.s. | 1184 | * off it in NWay-forced half mode for NWay-forced v.s. |
1185 | * legacy-forced issue. | 1185 | * legacy-forced issue. |
1186 | */ | 1186 | */ |
1187 | if (vptr->mii_status & VELOCITY_DUPLEX_FULL) | 1187 | if (vptr->mii_status & VELOCITY_DUPLEX_FULL) |
1188 | MII_REG_BITS_ON(TCSR_ECHODIS, MII_REG_TCSR, vptr->mac_regs); | 1188 | MII_REG_BITS_ON(TCSR_ECHODIS, MII_SREVISION, vptr->mac_regs); |
1189 | else | 1189 | else |
1190 | MII_REG_BITS_OFF(TCSR_ECHODIS, MII_REG_TCSR, vptr->mac_regs); | 1190 | MII_REG_BITS_OFF(TCSR_ECHODIS, MII_SREVISION, vptr->mac_regs); |
1191 | /* | 1191 | /* |
1192 | * Turn on Link/Activity LED enable bit for CIS8201 | 1192 | * Turn on Link/Activity LED enable bit for CIS8201 |
1193 | */ | 1193 | */ |
1194 | MII_REG_BITS_ON(PLED_LALBE, MII_REG_PLED, vptr->mac_regs); | 1194 | MII_REG_BITS_ON(PLED_LALBE, MII_TPISTATUS, vptr->mac_regs); |
1195 | break; | 1195 | break; |
1196 | case PHYID_VT3216_32BIT: | 1196 | case PHYID_VT3216_32BIT: |
1197 | case PHYID_VT3216_64BIT: | 1197 | case PHYID_VT3216_64BIT: |
1198 | /* | 1198 | /* |
1199 | * Reset to hardware default | 1199 | * Reset to hardware default |
1200 | */ | 1200 | */ |
1201 | MII_REG_BITS_ON((ANAR_ASMDIR | ANAR_PAUSE), MII_REG_ANAR, vptr->mac_regs); | 1201 | MII_REG_BITS_ON((ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP), MII_ADVERTISE, vptr->mac_regs); |
1202 | /* | 1202 | /* |
1203 | * Turn on ECHODIS bit in NWay-forced full mode and turn it | 1203 | * Turn on ECHODIS bit in NWay-forced full mode and turn it |
1204 | * off it in NWay-forced half mode for NWay-forced v.s. | 1204 | * off it in NWay-forced half mode for NWay-forced v.s. |
1205 | * legacy-forced issue | 1205 | * legacy-forced issue |
1206 | */ | 1206 | */ |
1207 | if (vptr->mii_status & VELOCITY_DUPLEX_FULL) | 1207 | if (vptr->mii_status & VELOCITY_DUPLEX_FULL) |
1208 | MII_REG_BITS_ON(TCSR_ECHODIS, MII_REG_TCSR, vptr->mac_regs); | 1208 | MII_REG_BITS_ON(TCSR_ECHODIS, MII_SREVISION, vptr->mac_regs); |
1209 | else | 1209 | else |
1210 | MII_REG_BITS_OFF(TCSR_ECHODIS, MII_REG_TCSR, vptr->mac_regs); | 1210 | MII_REG_BITS_OFF(TCSR_ECHODIS, MII_SREVISION, vptr->mac_regs); |
1211 | break; | 1211 | break; |
1212 | 1212 | ||
1213 | case PHYID_MARVELL_1000: | 1213 | case PHYID_MARVELL_1000: |
@@ -1219,15 +1219,15 @@ static void mii_init(struct velocity_info *vptr, u32 mii_status) | |||
1219 | /* | 1219 | /* |
1220 | * Reset to hardware default | 1220 | * Reset to hardware default |
1221 | */ | 1221 | */ |
1222 | MII_REG_BITS_ON((ANAR_ASMDIR | ANAR_PAUSE), MII_REG_ANAR, vptr->mac_regs); | 1222 | MII_REG_BITS_ON((ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP), MII_ADVERTISE, vptr->mac_regs); |
1223 | break; | 1223 | break; |
1224 | default: | 1224 | default: |
1225 | ; | 1225 | ; |
1226 | } | 1226 | } |
1227 | velocity_mii_read(vptr->mac_regs, MII_REG_BMCR, &BMCR); | 1227 | velocity_mii_read(vptr->mac_regs, MII_BMCR, &BMCR); |
1228 | if (BMCR & BMCR_ISO) { | 1228 | if (BMCR & BMCR_ISOLATE) { |
1229 | BMCR &= ~BMCR_ISO; | 1229 | BMCR &= ~BMCR_ISOLATE; |
1230 | velocity_mii_write(vptr->mac_regs, MII_REG_BMCR, BMCR); | 1230 | velocity_mii_write(vptr->mac_regs, MII_BMCR, BMCR); |
1231 | } | 1231 | } |
1232 | } | 1232 | } |
1233 | 1233 | ||
@@ -2953,13 +2953,13 @@ static int velocity_set_wol(struct velocity_info *vptr) | |||
2953 | 2953 | ||
2954 | if (vptr->mii_status & VELOCITY_AUTONEG_ENABLE) { | 2954 | if (vptr->mii_status & VELOCITY_AUTONEG_ENABLE) { |
2955 | if (PHYID_GET_PHY_ID(vptr->phy_id) == PHYID_CICADA_CS8201) | 2955 | if (PHYID_GET_PHY_ID(vptr->phy_id) == PHYID_CICADA_CS8201) |
2956 | MII_REG_BITS_ON(AUXCR_MDPPS, MII_REG_AUXCR, vptr->mac_regs); | 2956 | MII_REG_BITS_ON(AUXCR_MDPPS, MII_NCONFIG, vptr->mac_regs); |
2957 | 2957 | ||
2958 | MII_REG_BITS_OFF(G1000CR_1000FD | G1000CR_1000, MII_REG_G1000CR, vptr->mac_regs); | 2958 | MII_REG_BITS_OFF(ADVERTISE_1000FULL | ADVERTISE_1000HALF, MII_CTRL1000, vptr->mac_regs); |
2959 | } | 2959 | } |
2960 | 2960 | ||
2961 | if (vptr->mii_status & VELOCITY_SPEED_1000) | 2961 | if (vptr->mii_status & VELOCITY_SPEED_1000) |
2962 | MII_REG_BITS_ON(BMCR_REAUTO, MII_REG_BMCR, vptr->mac_regs); | 2962 | MII_REG_BITS_ON(BMCR_ANRESTART, MII_BMCR, vptr->mac_regs); |
2963 | 2963 | ||
2964 | BYTE_REG_BITS_ON(CHIPGCR_FCMODE, ®s->CHIPGCR); | 2964 | BYTE_REG_BITS_ON(CHIPGCR_FCMODE, ®s->CHIPGCR); |
2965 | 2965 | ||