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-rw-r--r--drivers/net/tokenring/3c359.c1830
-rw-r--r--drivers/net/tokenring/3c359.h290
-rw-r--r--drivers/net/tokenring/3c359_microcode.h1581
-rw-r--r--drivers/net/tokenring/Kconfig186
-rw-r--r--drivers/net/tokenring/Makefile15
-rw-r--r--drivers/net/tokenring/abyss.c481
-rw-r--r--drivers/net/tokenring/abyss.h58
-rw-r--r--drivers/net/tokenring/ibmtr.c1987
-rw-r--r--drivers/net/tokenring/lanstreamer.c2011
-rw-r--r--drivers/net/tokenring/lanstreamer.h358
-rw-r--r--drivers/net/tokenring/madgemc.c800
-rw-r--r--drivers/net/tokenring/madgemc.h70
-rw-r--r--drivers/net/tokenring/olympic.c1786
-rw-r--r--drivers/net/tokenring/olympic.h322
-rw-r--r--drivers/net/tokenring/proteon.c432
-rw-r--r--drivers/net/tokenring/skisa.c442
-rw-r--r--drivers/net/tokenring/smctr.c5742
-rw-r--r--drivers/net/tokenring/smctr.h1588
-rw-r--r--drivers/net/tokenring/smctr_firmware.h979
-rw-r--r--drivers/net/tokenring/tms380tr.c2410
-rw-r--r--drivers/net/tokenring/tms380tr.h1141
-rw-r--r--drivers/net/tokenring/tmspci.c267
22 files changed, 24776 insertions, 0 deletions
diff --git a/drivers/net/tokenring/3c359.c b/drivers/net/tokenring/3c359.c
new file mode 100644
index 000000000000..0d1dcf421771
--- /dev/null
+++ b/drivers/net/tokenring/3c359.c
@@ -0,0 +1,1830 @@
1/*
2 * 3c359.c (c) 2000 Mike Phillips (mikep@linuxtr.net) All Rights Reserved
3 *
4 * Linux driver for 3Com 3c359 Tokenlink Velocity XL PCI NIC
5 *
6 * Base Driver Olympic:
7 * Written 1999 Peter De Schrijver & Mike Phillips
8 *
9 * This software may be used and distributed according to the terms
10 * of the GNU General Public License, incorporated herein by reference.
11 *
12 * 7/17/00 - Clean up, version number 0.9.0. Ready to release to the world.
13 *
14 * 2/16/01 - Port up to kernel 2.4.2 ready for submission into the kernel.
15 * 3/05/01 - Last clean up stuff before submission.
16 * 2/15/01 - Finally, update to new pci api.
17 *
18 * To Do:
19 */
20
21/*
22 * Technical Card Details
23 *
24 * All access to data is done with 16/8 bit transfers. The transfer
25 * method really sucks. You can only read or write one location at a time.
26 *
27 * Also, the microcode for the card must be uploaded if the card does not have
28 * the flashrom on board. This is a 28K bloat in the driver when compiled
29 * as a module.
30 *
31 * Rx is very simple, status into a ring of descriptors, dma data transfer,
32 * interrupts to tell us when a packet is received.
33 *
34 * Tx is a little more interesting. Similar scenario, descriptor and dma data
35 * transfers, but we don't have to interrupt the card to tell it another packet
36 * is ready for transmission, we are just doing simple memory writes, not io or mmio
37 * writes. The card can be set up to simply poll on the next
38 * descriptor pointer and when this value is non-zero will automatically download
39 * the next packet. The card then interrupts us when the packet is done.
40 *
41 */
42
43#define XL_DEBUG 0
44
45#include <linux/config.h>
46#include <linux/module.h>
47#include <linux/kernel.h>
48#include <linux/errno.h>
49#include <linux/timer.h>
50#include <linux/in.h>
51#include <linux/ioport.h>
52#include <linux/string.h>
53#include <linux/proc_fs.h>
54#include <linux/ptrace.h>
55#include <linux/skbuff.h>
56#include <linux/interrupt.h>
57#include <linux/delay.h>
58#include <linux/netdevice.h>
59#include <linux/trdevice.h>
60#include <linux/stddef.h>
61#include <linux/init.h>
62#include <linux/pci.h>
63#include <linux/spinlock.h>
64#include <linux/bitops.h>
65
66#include <net/checksum.h>
67
68#include <asm/io.h>
69#include <asm/system.h>
70
71#include "3c359.h"
72
73static char version[] __devinitdata =
74"3c359.c v1.2.0 2/17/01 - Mike Phillips (mikep@linuxtr.net)" ;
75
76MODULE_AUTHOR("Mike Phillips <mikep@linuxtr.net>") ;
77MODULE_DESCRIPTION("3Com 3C359 Velocity XL Token Ring Adapter Driver \n") ;
78
79/* Module paramters */
80
81/* Ring Speed 0,4,16
82 * 0 = Autosense
83 * 4,16 = Selected speed only, no autosense
84 * This allows the card to be the first on the ring
85 * and become the active monitor.
86 *
87 * WARNING: Some hubs will allow you to insert
88 * at the wrong speed.
89 *
90 * The adapter will _not_ fail to open if there are no
91 * active monitors on the ring, it will simply open up in
92 * its last known ringspeed if no ringspeed is specified.
93 */
94
95static int ringspeed[XL_MAX_ADAPTERS] = {0,} ;
96
97module_param_array(ringspeed, int, NULL, 0);
98MODULE_PARM_DESC(ringspeed,"3c359: Ringspeed selection - 4,16 or 0") ;
99
100/* Packet buffer size */
101
102static int pkt_buf_sz[XL_MAX_ADAPTERS] = {0,} ;
103
104module_param_array(pkt_buf_sz, int, NULL, 0) ;
105MODULE_PARM_DESC(pkt_buf_sz,"3c359: Initial buffer size") ;
106/* Message Level */
107
108static int message_level[XL_MAX_ADAPTERS] = {0,} ;
109
110module_param_array(message_level, int, NULL, 0) ;
111MODULE_PARM_DESC(message_level, "3c359: Level of reported messages \n") ;
112/*
113 * This is a real nasty way of doing this, but otherwise you
114 * will be stuck with 1555 lines of hex #'s in the code.
115 */
116
117#include "3c359_microcode.h"
118
119static struct pci_device_id xl_pci_tbl[] =
120{
121 {PCI_VENDOR_ID_3COM,PCI_DEVICE_ID_3COM_3C359, PCI_ANY_ID, PCI_ANY_ID, },
122 { } /* terminate list */
123};
124MODULE_DEVICE_TABLE(pci,xl_pci_tbl) ;
125
126static int xl_init(struct net_device *dev);
127static int xl_open(struct net_device *dev);
128static int xl_open_hw(struct net_device *dev) ;
129static int xl_hw_reset(struct net_device *dev);
130static int xl_xmit(struct sk_buff *skb, struct net_device *dev);
131static void xl_dn_comp(struct net_device *dev);
132static int xl_close(struct net_device *dev);
133static void xl_set_rx_mode(struct net_device *dev);
134static irqreturn_t xl_interrupt(int irq, void *dev_id, struct pt_regs *regs);
135static struct net_device_stats * xl_get_stats(struct net_device *dev);
136static int xl_set_mac_address(struct net_device *dev, void *addr) ;
137static void xl_arb_cmd(struct net_device *dev);
138static void xl_asb_cmd(struct net_device *dev) ;
139static void xl_srb_cmd(struct net_device *dev, int srb_cmd) ;
140static void xl_wait_misr_flags(struct net_device *dev) ;
141static int xl_change_mtu(struct net_device *dev, int mtu);
142static void xl_srb_bh(struct net_device *dev) ;
143static void xl_asb_bh(struct net_device *dev) ;
144static void xl_reset(struct net_device *dev) ;
145static void xl_freemem(struct net_device *dev) ;
146
147
148/* EEProm Access Functions */
149static u16 xl_ee_read(struct net_device *dev, int ee_addr) ;
150static void xl_ee_write(struct net_device *dev, int ee_addr, u16 ee_value) ;
151
152/* Debugging functions */
153#if XL_DEBUG
154static void print_tx_state(struct net_device *dev) ;
155static void print_rx_state(struct net_device *dev) ;
156
157static void print_tx_state(struct net_device *dev)
158{
159
160 struct xl_private *xl_priv = (struct xl_private *)dev->priv ;
161 struct xl_tx_desc *txd ;
162 u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
163 int i ;
164
165 printk("tx_ring_head: %d, tx_ring_tail: %d, free_ent: %d \n",xl_priv->tx_ring_head,
166 xl_priv->tx_ring_tail, xl_priv->free_ring_entries) ;
167 printk("Ring , Address , FSH , DnNextPtr, Buffer, Buffer_Len \n");
168 for (i = 0; i < 16; i++) {
169 txd = &(xl_priv->xl_tx_ring[i]) ;
170 printk("%d, %08lx, %08x, %08x, %08x, %08x \n", i, virt_to_bus(txd),
171 txd->framestartheader, txd->dnnextptr, txd->buffer, txd->buffer_length ) ;
172 }
173
174 printk("DNLISTPTR = %04x \n", readl(xl_mmio + MMIO_DNLISTPTR) );
175
176 printk("DmaCtl = %04x \n", readl(xl_mmio + MMIO_DMA_CTRL) );
177 printk("Queue status = %0x \n",netif_running(dev) ) ;
178}
179
180static void print_rx_state(struct net_device *dev)
181{
182
183 struct xl_private *xl_priv = (struct xl_private *)dev->priv ;
184 struct xl_rx_desc *rxd ;
185 u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
186 int i ;
187
188 printk("rx_ring_tail: %d \n", xl_priv->rx_ring_tail) ;
189 printk("Ring , Address , FrameState , UPNextPtr, FragAddr, Frag_Len \n");
190 for (i = 0; i < 16; i++) {
191 /* rxd = (struct xl_rx_desc *)xl_priv->rx_ring_dma_addr + (i * sizeof(struct xl_rx_desc)) ; */
192 rxd = &(xl_priv->xl_rx_ring[i]) ;
193 printk("%d, %08lx, %08x, %08x, %08x, %08x \n", i, virt_to_bus(rxd),
194 rxd->framestatus, rxd->upnextptr, rxd->upfragaddr, rxd->upfraglen ) ;
195 }
196
197 printk("UPLISTPTR = %04x \n", readl(xl_mmio + MMIO_UPLISTPTR) );
198
199 printk("DmaCtl = %04x \n", readl(xl_mmio + MMIO_DMA_CTRL) );
200 printk("Queue status = %0x \n",netif_running(dev) ) ;
201}
202#endif
203
204/*
205 * Read values from the on-board EEProm. This looks very strange
206 * but you have to wait for the EEProm to get/set the value before
207 * passing/getting the next value from the nic. As with all requests
208 * on this nic it has to be done in two stages, a) tell the nic which
209 * memory address you want to access and b) pass/get the value from the nic.
210 * With the EEProm, you have to wait before and inbetween access a) and b).
211 * As this is only read at initialization time and the wait period is very
212 * small we shouldn't have to worry about scheduling issues.
213 */
214
215static u16 xl_ee_read(struct net_device *dev, int ee_addr)
216{
217 struct xl_private *xl_priv = (struct xl_private *)dev->priv ;
218 u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
219
220 /* Wait for EEProm to not be busy */
221 writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
222 while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
223
224 /* Tell EEProm what we want to do and where */
225 writel(IO_WORD_WRITE | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
226 writew(EEREAD + ee_addr, xl_mmio + MMIO_MACDATA) ;
227
228 /* Wait for EEProm to not be busy */
229 writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
230 while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
231
232 /* Tell EEProm what we want to do and where */
233 writel(IO_WORD_WRITE | EECONTROL , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
234 writew(EEREAD + ee_addr, xl_mmio + MMIO_MACDATA) ;
235
236 /* Finally read the value from the EEProm */
237 writel(IO_WORD_READ | EEDATA , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
238 return readw(xl_mmio + MMIO_MACDATA) ;
239}
240
241/*
242 * Write values to the onboard eeprom. As with eeprom read you need to
243 * set which location to write, wait, value to write, wait, with the
244 * added twist of having to enable eeprom writes as well.
245 */
246
247static void xl_ee_write(struct net_device *dev, int ee_addr, u16 ee_value)
248{
249 struct xl_private *xl_priv = (struct xl_private *)dev->priv ;
250 u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
251
252 /* Wait for EEProm to not be busy */
253 writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
254 while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
255
256 /* Enable write/erase */
257 writel(IO_WORD_WRITE | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
258 writew(EE_ENABLE_WRITE, xl_mmio + MMIO_MACDATA) ;
259
260 /* Wait for EEProm to not be busy */
261 writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
262 while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
263
264 /* Put the value we want to write into EEDATA */
265 writel(IO_WORD_WRITE | EEDATA, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
266 writew(ee_value, xl_mmio + MMIO_MACDATA) ;
267
268 /* Tell EEProm to write eevalue into ee_addr */
269 writel(IO_WORD_WRITE | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
270 writew(EEWRITE + ee_addr, xl_mmio + MMIO_MACDATA) ;
271
272 /* Wait for EEProm to not be busy, to ensure write gets done */
273 writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
274 while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
275
276 return ;
277}
278
279int __devinit xl_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
280{
281 struct net_device *dev ;
282 struct xl_private *xl_priv ;
283 static int card_no = -1 ;
284 int i ;
285
286 card_no++ ;
287
288 if (pci_enable_device(pdev)) {
289 return -ENODEV ;
290 }
291
292 pci_set_master(pdev);
293
294 if ((i = pci_request_regions(pdev,"3c359"))) {
295 return i ;
296 } ;
297
298 /*
299 * Allowing init_trdev to allocate the dev->priv structure will align xl_private
300 * on a 32 bytes boundary which we need for the rx/tx descriptors
301 */
302
303 dev = alloc_trdev(sizeof(struct xl_private)) ;
304 if (!dev) {
305 pci_release_regions(pdev) ;
306 return -ENOMEM ;
307 }
308 xl_priv = dev->priv ;
309
310#if XL_DEBUG
311 printk("pci_device: %p, dev:%p, dev->priv: %p, ba[0]: %10x, ba[1]:%10x\n",
312 pdev, dev, dev->priv, (unsigned int)pdev->resource[0].start, (unsigned int)pdev->resource[1].start) ;
313#endif
314
315 dev->irq=pdev->irq;
316 dev->base_addr=pci_resource_start(pdev,0) ;
317 xl_priv->xl_card_name = pci_name(pdev);
318 xl_priv->xl_mmio=ioremap(pci_resource_start(pdev,1), XL_IO_SPACE);
319 xl_priv->pdev = pdev ;
320
321 if ((pkt_buf_sz[card_no] < 100) || (pkt_buf_sz[card_no] > 18000) )
322 xl_priv->pkt_buf_sz = PKT_BUF_SZ ;
323 else
324 xl_priv->pkt_buf_sz = pkt_buf_sz[card_no] ;
325
326 dev->mtu = xl_priv->pkt_buf_sz - TR_HLEN ;
327 xl_priv->xl_ring_speed = ringspeed[card_no] ;
328 xl_priv->xl_message_level = message_level[card_no] ;
329 xl_priv->xl_functional_addr[0] = xl_priv->xl_functional_addr[1] = xl_priv->xl_functional_addr[2] = xl_priv->xl_functional_addr[3] = 0 ;
330 xl_priv->xl_copy_all_options = 0 ;
331
332 if((i = xl_init(dev))) {
333 iounmap(xl_priv->xl_mmio) ;
334 free_netdev(dev) ;
335 pci_release_regions(pdev) ;
336 return i ;
337 }
338
339 dev->open=&xl_open;
340 dev->hard_start_xmit=&xl_xmit;
341 dev->change_mtu=&xl_change_mtu;
342 dev->stop=&xl_close;
343 dev->do_ioctl=NULL;
344 dev->set_multicast_list=&xl_set_rx_mode;
345 dev->get_stats=&xl_get_stats ;
346 dev->set_mac_address=&xl_set_mac_address ;
347 SET_MODULE_OWNER(dev);
348 SET_NETDEV_DEV(dev, &pdev->dev);
349
350 pci_set_drvdata(pdev,dev) ;
351 if ((i = register_netdev(dev))) {
352 printk(KERN_ERR "3C359, register netdev failed\n") ;
353 pci_set_drvdata(pdev,NULL) ;
354 iounmap(xl_priv->xl_mmio) ;
355 free_netdev(dev) ;
356 pci_release_regions(pdev) ;
357 return i ;
358 }
359
360 printk(KERN_INFO "3C359: %s registered as: %s\n",xl_priv->xl_card_name,dev->name) ;
361
362 return 0;
363}
364
365
366static int __init xl_init(struct net_device *dev)
367{
368 struct xl_private *xl_priv = (struct xl_private *)dev->priv ;
369
370 printk(KERN_INFO "%s \n", version);
371 printk(KERN_INFO "%s: I/O at %hx, MMIO at %p, using irq %d\n",
372 xl_priv->xl_card_name, (unsigned int)dev->base_addr ,xl_priv->xl_mmio, dev->irq);
373
374 spin_lock_init(&xl_priv->xl_lock) ;
375
376 return xl_hw_reset(dev) ;
377
378}
379
380
381/*
382 * Hardware reset. This needs to be a separate entity as we need to reset the card
383 * when we change the EEProm settings.
384 */
385
386static int xl_hw_reset(struct net_device *dev)
387{
388 struct xl_private *xl_priv = (struct xl_private *)dev->priv ;
389 u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
390 unsigned long t ;
391 u16 i ;
392 u16 result_16 ;
393 u8 result_8 ;
394 u16 start ;
395 int j ;
396
397 /*
398 * Reset the card. If the card has got the microcode on board, we have
399 * missed the initialization interrupt, so we must always do this.
400 */
401
402 writew( GLOBAL_RESET, xl_mmio + MMIO_COMMAND ) ;
403
404 /*
405 * Must wait for cmdInProgress bit (12) to clear before continuing with
406 * card configuration.
407 */
408
409 t=jiffies;
410 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
411 schedule();
412 if(jiffies-t > 40*HZ) {
413 printk(KERN_ERR "%s: 3COM 3C359 Velocity XL card not responding to global reset.\n", dev->name);
414 return -ENODEV;
415 }
416 }
417
418 /*
419 * Enable pmbar by setting bit in CPAttention
420 */
421
422 writel( (IO_BYTE_READ | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
423 result_8 = readb(xl_mmio + MMIO_MACDATA) ;
424 result_8 = result_8 | CPA_PMBARVIS ;
425 writel( (IO_BYTE_WRITE | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
426 writeb(result_8, xl_mmio + MMIO_MACDATA) ;
427
428 /*
429 * Read cpHold bit in pmbar, if cleared we have got Flashrom on board.
430 * If not, we need to upload the microcode to the card
431 */
432
433 writel( (IO_WORD_READ | PMBAR),xl_mmio + MMIO_MAC_ACCESS_CMD);
434
435#if XL_DEBUG
436 printk(KERN_INFO "Read from PMBAR = %04x \n", readw(xl_mmio + MMIO_MACDATA)) ;
437#endif
438
439 if ( readw( (xl_mmio + MMIO_MACDATA)) & PMB_CPHOLD ) {
440
441 /* Set PmBar, privateMemoryBase bits (8:2) to 0 */
442
443 writel( (IO_WORD_READ | PMBAR),xl_mmio + MMIO_MAC_ACCESS_CMD);
444 result_16 = readw(xl_mmio + MMIO_MACDATA) ;
445 result_16 = result_16 & ~((0x7F) << 2) ;
446 writel( (IO_WORD_WRITE | PMBAR), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
447 writew(result_16,xl_mmio + MMIO_MACDATA) ;
448
449 /* Set CPAttention, memWrEn bit */
450
451 writel( (IO_BYTE_READ | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
452 result_8 = readb(xl_mmio + MMIO_MACDATA) ;
453 result_8 = result_8 | CPA_MEMWREN ;
454 writel( (IO_BYTE_WRITE | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
455 writeb(result_8, xl_mmio + MMIO_MACDATA) ;
456
457 /*
458 * Now to write the microcode into the shared ram
459 * The microcode must finish at position 0xFFFF, so we must subtract
460 * to get the start position for the code
461 */
462
463 start = (0xFFFF - (mc_size) + 1 ) ; /* Looks strange but ensures compiler only uses 16 bit unsigned int for this */
464
465 printk(KERN_INFO "3C359: Uploading Microcode: ");
466
467 for (i = start, j = 0; j < mc_size; i++, j++) {
468 writel(MEM_BYTE_WRITE | 0XD0000 | i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
469 writeb(microcode[j],xl_mmio + MMIO_MACDATA) ;
470 if (j % 1024 == 0)
471 printk(".");
472 }
473 printk("\n") ;
474
475 for (i=0;i < 16; i++) {
476 writel( (MEM_BYTE_WRITE | 0xDFFF0) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
477 writeb(microcode[mc_size - 16 + i], xl_mmio + MMIO_MACDATA) ;
478 }
479
480 /*
481 * Have to write the start address of the upload to FFF4, but
482 * the address must be >> 4. You do not want to know how long
483 * it took me to discover this.
484 */
485
486 writel(MEM_WORD_WRITE | 0xDFFF4, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
487 writew(start >> 4, xl_mmio + MMIO_MACDATA);
488
489 /* Clear the CPAttention, memWrEn Bit */
490
491 writel( (IO_BYTE_READ | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
492 result_8 = readb(xl_mmio + MMIO_MACDATA) ;
493 result_8 = result_8 & ~CPA_MEMWREN ;
494 writel( (IO_BYTE_WRITE | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
495 writeb(result_8, xl_mmio + MMIO_MACDATA) ;
496
497 /* Clear the cpHold bit in pmbar */
498
499 writel( (IO_WORD_READ | PMBAR),xl_mmio + MMIO_MAC_ACCESS_CMD);
500 result_16 = readw(xl_mmio + MMIO_MACDATA) ;
501 result_16 = result_16 & ~PMB_CPHOLD ;
502 writel( (IO_WORD_WRITE | PMBAR), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
503 writew(result_16,xl_mmio + MMIO_MACDATA) ;
504
505
506 } /* If microcode upload required */
507
508 /*
509 * The card should now go though a self test procedure and get itself ready
510 * to be opened, we must wait for an srb response with the initialization
511 * information.
512 */
513
514#if XL_DEBUG
515 printk(KERN_INFO "%s: Microcode uploaded, must wait for the self test to complete\n", dev->name);
516#endif
517
518 writew(SETINDENABLE | 0xFFF, xl_mmio + MMIO_COMMAND) ;
519
520 t=jiffies;
521 while ( !(readw(xl_mmio + MMIO_INTSTATUS_AUTO) & INTSTAT_SRB) ) {
522 schedule();
523 if(jiffies-t > 15*HZ) {
524 printk(KERN_ERR "3COM 3C359 Velocity XL card not responding.\n");
525 return -ENODEV;
526 }
527 }
528
529 /*
530 * Write the RxBufArea with D000, RxEarlyThresh, TxStartThresh,
531 * DnPriReqThresh, read the tech docs if you want to know what
532 * values they need to be.
533 */
534
535 writel(MMIO_WORD_WRITE | RXBUFAREA, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
536 writew(0xD000, xl_mmio + MMIO_MACDATA) ;
537
538 writel(MMIO_WORD_WRITE | RXEARLYTHRESH, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
539 writew(0X0020, xl_mmio + MMIO_MACDATA) ;
540
541 writew( SETTXSTARTTHRESH | 0x40 , xl_mmio + MMIO_COMMAND) ;
542
543 writeb(0x04, xl_mmio + MMIO_DNBURSTTHRESH) ;
544 writeb(0x04, xl_mmio + DNPRIREQTHRESH) ;
545
546 /*
547 * Read WRBR to provide the location of the srb block, have to use byte reads not word reads.
548 * Tech docs have this wrong !!!!
549 */
550
551 writel(MMIO_BYTE_READ | WRBR, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
552 xl_priv->srb = readb(xl_mmio + MMIO_MACDATA) << 8 ;
553 writel( (MMIO_BYTE_READ | WRBR) + 1, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
554 xl_priv->srb = xl_priv->srb | readb(xl_mmio + MMIO_MACDATA) ;
555
556#if XL_DEBUG
557 writel(IO_WORD_READ | SWITCHSETTINGS, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
558 if ( readw(xl_mmio + MMIO_MACDATA) & 2) {
559 printk(KERN_INFO "Default ring speed 4 mbps \n") ;
560 } else {
561 printk(KERN_INFO "Default ring speed 16 mbps \n") ;
562 }
563 printk(KERN_INFO "%s: xl_priv->srb = %04x\n",xl_priv->xl_card_name, xl_priv->srb);
564#endif
565
566 return 0;
567}
568
569static int xl_open(struct net_device *dev)
570{
571 struct xl_private *xl_priv=(struct xl_private *)dev->priv;
572 u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
573 u8 i ;
574 u16 hwaddr[3] ; /* Should be u8[6] but we get word return values */
575 int open_err ;
576
577 u16 switchsettings, switchsettings_eeprom ;
578
579 if(request_irq(dev->irq, &xl_interrupt, SA_SHIRQ , "3c359", dev)) {
580 return -EAGAIN;
581 }
582
583 /*
584 * Read the information from the EEPROM that we need. I know we
585 * should use ntohs, but the word gets stored reversed in the 16
586 * bit field anyway and it all works its self out when we memcpy
587 * it into dev->dev_addr.
588 */
589
590 hwaddr[0] = xl_ee_read(dev,0x10) ;
591 hwaddr[1] = xl_ee_read(dev,0x11) ;
592 hwaddr[2] = xl_ee_read(dev,0x12) ;
593
594 /* Ring speed */
595
596 switchsettings_eeprom = xl_ee_read(dev,0x08) ;
597 switchsettings = switchsettings_eeprom ;
598
599 if (xl_priv->xl_ring_speed != 0) {
600 if (xl_priv->xl_ring_speed == 4)
601 switchsettings = switchsettings | 0x02 ;
602 else
603 switchsettings = switchsettings & ~0x02 ;
604 }
605
606 /* Only write EEProm if there has been a change */
607 if (switchsettings != switchsettings_eeprom) {
608 xl_ee_write(dev,0x08,switchsettings) ;
609 /* Hardware reset after changing EEProm */
610 xl_hw_reset(dev) ;
611 }
612
613 memcpy(dev->dev_addr,hwaddr,dev->addr_len) ;
614
615 open_err = xl_open_hw(dev) ;
616
617 /*
618 * This really needs to be cleaned up with better error reporting.
619 */
620
621 if (open_err != 0) { /* Something went wrong with the open command */
622 if (open_err & 0x07) { /* Wrong speed, retry at different speed */
623 printk(KERN_WARNING "%s: Open Error, retrying at different ringspeed \n", dev->name) ;
624 switchsettings = switchsettings ^ 2 ;
625 xl_ee_write(dev,0x08,switchsettings) ;
626 xl_hw_reset(dev) ;
627 open_err = xl_open_hw(dev) ;
628 if (open_err != 0) {
629 printk(KERN_WARNING "%s: Open error returned a second time, we're bombing out now\n", dev->name);
630 free_irq(dev->irq,dev) ;
631 return -ENODEV ;
632 }
633 } else {
634 printk(KERN_WARNING "%s: Open Error = %04x\n", dev->name, open_err) ;
635 free_irq(dev->irq,dev) ;
636 return -ENODEV ;
637 }
638 }
639
640 /*
641 * Now to set up the Rx and Tx buffer structures
642 */
643 /* These MUST be on 8 byte boundaries */
644 xl_priv->xl_tx_ring = kmalloc((sizeof(struct xl_tx_desc) * XL_TX_RING_SIZE) + 7, GFP_DMA | GFP_KERNEL) ;
645 if (xl_priv->xl_tx_ring == NULL) {
646 printk(KERN_WARNING "%s: Not enough memory to allocate rx buffers.\n",
647 dev->name);
648 free_irq(dev->irq,dev);
649 return -ENOMEM;
650 }
651 xl_priv->xl_rx_ring = kmalloc((sizeof(struct xl_rx_desc) * XL_RX_RING_SIZE) +7, GFP_DMA | GFP_KERNEL) ;
652 if (xl_priv->xl_tx_ring == NULL) {
653 printk(KERN_WARNING "%s: Not enough memory to allocate rx buffers.\n",
654 dev->name);
655 free_irq(dev->irq,dev);
656 kfree(xl_priv->xl_tx_ring);
657 return -ENOMEM;
658 }
659 memset(xl_priv->xl_tx_ring,0,sizeof(struct xl_tx_desc) * XL_TX_RING_SIZE) ;
660 memset(xl_priv->xl_rx_ring,0,sizeof(struct xl_rx_desc) * XL_RX_RING_SIZE) ;
661
662 /* Setup Rx Ring */
663 for (i=0 ; i < XL_RX_RING_SIZE ; i++) {
664 struct sk_buff *skb ;
665
666 skb = dev_alloc_skb(xl_priv->pkt_buf_sz) ;
667 if (skb==NULL)
668 break ;
669
670 skb->dev = dev ;
671 xl_priv->xl_rx_ring[i].upfragaddr = pci_map_single(xl_priv->pdev, skb->data,xl_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE) ;
672 xl_priv->xl_rx_ring[i].upfraglen = xl_priv->pkt_buf_sz | RXUPLASTFRAG;
673 xl_priv->rx_ring_skb[i] = skb ;
674 }
675
676 if (i==0) {
677 printk(KERN_WARNING "%s: Not enough memory to allocate rx buffers. Adapter disabled \n",dev->name) ;
678 free_irq(dev->irq,dev) ;
679 return -EIO ;
680 }
681
682 xl_priv->rx_ring_no = i ;
683 xl_priv->rx_ring_tail = 0 ;
684 xl_priv->rx_ring_dma_addr = pci_map_single(xl_priv->pdev,xl_priv->xl_rx_ring, sizeof(struct xl_rx_desc) * XL_RX_RING_SIZE, PCI_DMA_TODEVICE) ;
685 for (i=0;i<(xl_priv->rx_ring_no-1);i++) {
686 xl_priv->xl_rx_ring[i].upnextptr = xl_priv->rx_ring_dma_addr + (sizeof (struct xl_rx_desc) * (i+1)) ;
687 }
688 xl_priv->xl_rx_ring[i].upnextptr = 0 ;
689
690 writel(xl_priv->rx_ring_dma_addr, xl_mmio + MMIO_UPLISTPTR) ;
691
692 /* Setup Tx Ring */
693
694 xl_priv->tx_ring_dma_addr = pci_map_single(xl_priv->pdev,xl_priv->xl_tx_ring, sizeof(struct xl_tx_desc) * XL_TX_RING_SIZE,PCI_DMA_TODEVICE) ;
695
696 xl_priv->tx_ring_head = 1 ;
697 xl_priv->tx_ring_tail = 255 ; /* Special marker for first packet */
698 xl_priv->free_ring_entries = XL_TX_RING_SIZE ;
699
700 /*
701 * Setup the first dummy DPD entry for polling to start working.
702 */
703
704 xl_priv->xl_tx_ring[0].framestartheader = TXDPDEMPTY ;
705 xl_priv->xl_tx_ring[0].buffer = 0 ;
706 xl_priv->xl_tx_ring[0].buffer_length = 0 ;
707 xl_priv->xl_tx_ring[0].dnnextptr = 0 ;
708
709 writel(xl_priv->tx_ring_dma_addr, xl_mmio + MMIO_DNLISTPTR) ;
710 writel(DNUNSTALL, xl_mmio + MMIO_COMMAND) ;
711 writel(UPUNSTALL, xl_mmio + MMIO_COMMAND) ;
712 writel(DNENABLE, xl_mmio + MMIO_COMMAND) ;
713 writeb(0x40, xl_mmio + MMIO_DNPOLL) ;
714
715 /*
716 * Enable interrupts on the card
717 */
718
719 writel(SETINTENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
720 writel(SETINDENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
721
722 netif_start_queue(dev) ;
723 return 0;
724
725}
726
727static int xl_open_hw(struct net_device *dev)
728{
729 struct xl_private *xl_priv=(struct xl_private *)dev->priv;
730 u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
731 u16 vsoff ;
732 char ver_str[33];
733 int open_err ;
734 int i ;
735 unsigned long t ;
736
737 /*
738 * Okay, let's build up the Open.NIC srb command
739 *
740 */
741
742 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
743 writeb(OPEN_NIC, xl_mmio + MMIO_MACDATA) ;
744
745 /*
746 * Use this as a test byte, if it comes back with the same value, the command didn't work
747 */
748
749 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb)+ 2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
750 writeb(0xff,xl_mmio + MMIO_MACDATA) ;
751
752 /* Open options */
753 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + 8, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
754 writeb(0x00, xl_mmio + MMIO_MACDATA) ;
755 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + 9, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
756 writeb(0x00, xl_mmio + MMIO_MACDATA) ;
757
758 /*
759 * Node address, be careful here, the docs say you can just put zeros here and it will use
760 * the hardware address, it doesn't, you must include the node address in the open command.
761 */
762
763 if (xl_priv->xl_laa[0]) { /* If using a LAA address */
764 for (i=10;i<16;i++) {
765 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
766 writeb(xl_priv->xl_laa[i],xl_mmio + MMIO_MACDATA) ;
767 }
768 memcpy(dev->dev_addr,xl_priv->xl_laa,dev->addr_len) ;
769 } else { /* Regular hardware address */
770 for (i=10;i<16;i++) {
771 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
772 writeb(dev->dev_addr[i-10], xl_mmio + MMIO_MACDATA) ;
773 }
774 }
775
776 /* Default everything else to 0 */
777 for (i = 16; i < 34; i++) {
778 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
779 writeb(0x00,xl_mmio + MMIO_MACDATA) ;
780 }
781
782 /*
783 * Set the csrb bit in the MISR register
784 */
785
786 xl_wait_misr_flags(dev) ;
787 writel(MEM_BYTE_WRITE | MF_CSRB, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
788 writeb(0xFF, xl_mmio + MMIO_MACDATA) ;
789 writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
790 writeb(MISR_CSRB , xl_mmio + MMIO_MACDATA) ;
791
792 /*
793 * Now wait for the command to run
794 */
795
796 t=jiffies;
797 while (! (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_SRB)) {
798 schedule();
799 if(jiffies-t > 40*HZ) {
800 printk(KERN_ERR "3COM 3C359 Velocity XL card not responding.\n");
801 break ;
802 }
803 }
804
805 /*
806 * Let's interpret the open response
807 */
808
809 writel( (MEM_BYTE_READ | 0xD0000 | xl_priv->srb)+2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
810 if (readb(xl_mmio + MMIO_MACDATA)!=0) {
811 open_err = readb(xl_mmio + MMIO_MACDATA) << 8 ;
812 writel( (MEM_BYTE_READ | 0xD0000 | xl_priv->srb) + 7, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
813 open_err |= readb(xl_mmio + MMIO_MACDATA) ;
814 return open_err ;
815 } else {
816 writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 8, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
817 xl_priv->asb = ntohs(readw(xl_mmio + MMIO_MACDATA)) ;
818 printk(KERN_INFO "%s: Adapter Opened Details: ",dev->name) ;
819 printk("ASB: %04x",xl_priv->asb ) ;
820 writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 10, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
821 printk(", SRB: %04x",ntohs(readw(xl_mmio + MMIO_MACDATA)) ) ;
822
823 writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 12, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
824 xl_priv->arb = ntohs(readw(xl_mmio + MMIO_MACDATA)) ;
825 printk(", ARB: %04x \n",xl_priv->arb ) ;
826 writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 14, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
827 vsoff = ntohs(readw(xl_mmio + MMIO_MACDATA)) ;
828
829 /*
830 * Interesting, sending the individual characters directly to printk was causing klogd to use
831 * use 100% of processor time, so we build up the string and print that instead.
832 */
833
834 for (i=0;i<0x20;i++) {
835 writel( (MEM_BYTE_READ | 0xD0000 | vsoff) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
836 ver_str[i] = readb(xl_mmio + MMIO_MACDATA) ;
837 }
838 ver_str[i] = '\0' ;
839 printk(KERN_INFO "%s: Microcode version String: %s \n",dev->name,ver_str);
840 }
841
842 /*
843 * Issue the AckInterrupt
844 */
845 writew(ACK_INTERRUPT | SRBRACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
846
847 return 0 ;
848}
849
850/*
851 * There are two ways of implementing rx on the 359 NIC, either
852 * interrupt driven or polling. We are going to uses interrupts,
853 * it is the easier way of doing things.
854 *
855 * The Rx works with a ring of Rx descriptors. At initialise time the ring
856 * entries point to the next entry except for the last entry in the ring
857 * which points to 0. The card is programmed with the location of the first
858 * available descriptor and keeps reading the next_ptr until next_ptr is set
859 * to 0. Hopefully with a ring size of 16 the card will never get to read a next_ptr
860 * of 0. As the Rx interrupt is received we copy the frame up to the protocol layers
861 * and then point the end of the ring to our current position and point our current
862 * position to 0, therefore making the current position the last position on the ring.
863 * The last position on the ring therefore loops continually loops around the rx ring.
864 *
865 * rx_ring_tail is the position on the ring to process next. (Think of a snake, the head
866 * expands as the card adds new packets and we go around eating the tail processing the
867 * packets.)
868 *
869 * Undoubtably it could be streamlined and improved upon, but at the moment it works
870 * and the fast path through the routine is fine.
871 *
872 * adv_rx_ring could be inlined to increase performance, but its called a *lot* of times
873 * in xl_rx so would increase the size of the function significantly.
874 */
875
876static void adv_rx_ring(struct net_device *dev) /* Advance rx_ring, cut down on bloat in xl_rx */
877{
878 struct xl_private *xl_priv=(struct xl_private *)dev->priv;
879 int prev_ring_loc ;
880
881 prev_ring_loc = (xl_priv->rx_ring_tail + XL_RX_RING_SIZE - 1) & (XL_RX_RING_SIZE - 1);
882 xl_priv->xl_rx_ring[prev_ring_loc].upnextptr = xl_priv->rx_ring_dma_addr + (sizeof (struct xl_rx_desc) * xl_priv->rx_ring_tail) ;
883 xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].framestatus = 0 ;
884 xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upnextptr = 0 ;
885 xl_priv->rx_ring_tail++ ;
886 xl_priv->rx_ring_tail &= (XL_RX_RING_SIZE-1) ;
887
888 return ;
889}
890
891static void xl_rx(struct net_device *dev)
892{
893 struct xl_private *xl_priv=(struct xl_private *)dev->priv;
894 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
895 struct sk_buff *skb, *skb2 ;
896 int frame_length = 0, copy_len = 0 ;
897 int temp_ring_loc ;
898
899 /*
900 * Receive the next frame, loop around the ring until all frames
901 * have been received.
902 */
903
904 while (xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].framestatus & (RXUPDCOMPLETE | RXUPDFULL) ) { /* Descriptor to process */
905
906 if (xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].framestatus & RXUPDFULL ) { /* UpdFull, Multiple Descriptors used for the frame */
907
908 /*
909 * This is a pain, you need to go through all the descriptors until the last one
910 * for this frame to find the framelength
911 */
912
913 temp_ring_loc = xl_priv->rx_ring_tail ;
914
915 while (xl_priv->xl_rx_ring[temp_ring_loc].framestatus & RXUPDFULL ) {
916 temp_ring_loc++ ;
917 temp_ring_loc &= (XL_RX_RING_SIZE-1) ;
918 }
919
920 frame_length = xl_priv->xl_rx_ring[temp_ring_loc].framestatus & 0x7FFF ;
921
922 skb = dev_alloc_skb(frame_length) ;
923
924 if (skb==NULL) { /* No memory for frame, still need to roll forward the rx ring */
925 printk(KERN_WARNING "%s: dev_alloc_skb failed - multi buffer !\n", dev->name) ;
926 while (xl_priv->rx_ring_tail != temp_ring_loc)
927 adv_rx_ring(dev) ;
928
929 adv_rx_ring(dev) ; /* One more time just for luck :) */
930 xl_priv->xl_stats.rx_dropped++ ;
931
932 writel(ACK_INTERRUPT | UPCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
933 return ;
934 }
935
936 skb->dev = dev ;
937
938 while (xl_priv->rx_ring_tail != temp_ring_loc) {
939 copy_len = xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfraglen & 0x7FFF ;
940 frame_length -= copy_len ;
941 pci_dma_sync_single_for_cpu(xl_priv->pdev,xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr,xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE) ;
942 memcpy(skb_put(skb,copy_len), xl_priv->rx_ring_skb[xl_priv->rx_ring_tail]->data, copy_len) ;
943 pci_dma_sync_single_for_device(xl_priv->pdev,xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr,xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE) ;
944 adv_rx_ring(dev) ;
945 }
946
947 /* Now we have found the last fragment */
948 pci_dma_sync_single_for_cpu(xl_priv->pdev,xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr,xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE) ;
949 memcpy(skb_put(skb,copy_len), xl_priv->rx_ring_skb[xl_priv->rx_ring_tail]->data, frame_length) ;
950/* memcpy(skb_put(skb,frame_length), bus_to_virt(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr), frame_length) ; */
951 pci_dma_sync_single_for_device(xl_priv->pdev,xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr,xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE) ;
952 adv_rx_ring(dev) ;
953 skb->protocol = tr_type_trans(skb,dev) ;
954 netif_rx(skb) ;
955
956 } else { /* Single Descriptor Used, simply swap buffers over, fast path */
957
958 frame_length = xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].framestatus & 0x7FFF ;
959
960 skb = dev_alloc_skb(xl_priv->pkt_buf_sz) ;
961
962 if (skb==NULL) { /* Still need to fix the rx ring */
963 printk(KERN_WARNING "%s: dev_alloc_skb failed in rx, single buffer \n",dev->name) ;
964 adv_rx_ring(dev) ;
965 xl_priv->xl_stats.rx_dropped++ ;
966 writel(ACK_INTERRUPT | UPCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
967 return ;
968 }
969
970 skb->dev = dev ;
971
972 skb2 = xl_priv->rx_ring_skb[xl_priv->rx_ring_tail] ;
973 pci_unmap_single(xl_priv->pdev, xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr, xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE) ;
974 skb_put(skb2, frame_length) ;
975 skb2->protocol = tr_type_trans(skb2,dev) ;
976
977 xl_priv->rx_ring_skb[xl_priv->rx_ring_tail] = skb ;
978 xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr = pci_map_single(xl_priv->pdev,skb->data,xl_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE) ;
979 xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfraglen = xl_priv->pkt_buf_sz | RXUPLASTFRAG ;
980 adv_rx_ring(dev) ;
981 xl_priv->xl_stats.rx_packets++ ;
982 xl_priv->xl_stats.rx_bytes += frame_length ;
983
984 netif_rx(skb2) ;
985 } /* if multiple buffers */
986 dev->last_rx = jiffies ;
987 } /* while packet to do */
988
989 /* Clear the updComplete interrupt */
990 writel(ACK_INTERRUPT | UPCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
991 return ;
992}
993
994/*
995 * This is ruthless, it doesn't care what state the card is in it will
996 * completely reset the adapter.
997 */
998
999static void xl_reset(struct net_device *dev)
1000{
1001 struct xl_private *xl_priv=(struct xl_private *)dev->priv;
1002 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1003 unsigned long t;
1004
1005 writew( GLOBAL_RESET, xl_mmio + MMIO_COMMAND ) ;
1006
1007 /*
1008 * Must wait for cmdInProgress bit (12) to clear before continuing with
1009 * card configuration.
1010 */
1011
1012 t=jiffies;
1013 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
1014 if(jiffies-t > 40*HZ) {
1015 printk(KERN_ERR "3COM 3C359 Velocity XL card not responding.\n");
1016 break ;
1017 }
1018 }
1019
1020}
1021
1022static void xl_freemem(struct net_device *dev)
1023{
1024 struct xl_private *xl_priv=(struct xl_private *)dev->priv ;
1025 int i ;
1026
1027 for (i=0;i<XL_RX_RING_SIZE;i++) {
1028 dev_kfree_skb_irq(xl_priv->rx_ring_skb[xl_priv->rx_ring_tail]) ;
1029 pci_unmap_single(xl_priv->pdev,xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr,xl_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE) ;
1030 xl_priv->rx_ring_tail++ ;
1031 xl_priv->rx_ring_tail &= XL_RX_RING_SIZE-1;
1032 }
1033
1034 /* unmap ring */
1035 pci_unmap_single(xl_priv->pdev,xl_priv->rx_ring_dma_addr, sizeof(struct xl_rx_desc) * XL_RX_RING_SIZE, PCI_DMA_FROMDEVICE) ;
1036
1037 pci_unmap_single(xl_priv->pdev,xl_priv->tx_ring_dma_addr, sizeof(struct xl_tx_desc) * XL_TX_RING_SIZE, PCI_DMA_TODEVICE) ;
1038
1039 kfree(xl_priv->xl_rx_ring) ;
1040 kfree(xl_priv->xl_tx_ring) ;
1041
1042 return ;
1043}
1044
1045static irqreturn_t xl_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1046{
1047 struct net_device *dev = (struct net_device *)dev_id;
1048 struct xl_private *xl_priv =(struct xl_private *)dev->priv;
1049 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1050 u16 intstatus, macstatus ;
1051
1052 if (!dev) {
1053 printk(KERN_WARNING "Device structure dead, aaahhhh !\n") ;
1054 return IRQ_NONE;
1055 }
1056
1057 intstatus = readw(xl_mmio + MMIO_INTSTATUS) ;
1058
1059 if (!(intstatus & 1)) /* We didn't generate the interrupt */
1060 return IRQ_NONE;
1061
1062 spin_lock(&xl_priv->xl_lock) ;
1063
1064 /*
1065 * Process the interrupt
1066 */
1067 /*
1068 * Something fishy going on here, we shouldn't get 0001 ints, not fatal though.
1069 */
1070 if (intstatus == 0x0001) {
1071 writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
1072 printk(KERN_INFO "%s: 00001 int received \n",dev->name) ;
1073 } else {
1074 if (intstatus & (HOSTERRINT | SRBRINT | ARBCINT | UPCOMPINT | DNCOMPINT | HARDERRINT | (1<<8) | TXUNDERRUN | ASBFINT)) {
1075
1076 /*
1077 * Host Error.
1078 * It may be possible to recover from this, but usually it means something
1079 * is seriously fubar, so we just close the adapter.
1080 */
1081
1082 if (intstatus & HOSTERRINT) {
1083 printk(KERN_WARNING "%s: Host Error, performing global reset, intstatus = %04x \n",dev->name,intstatus) ;
1084 writew( GLOBAL_RESET, xl_mmio + MMIO_COMMAND ) ;
1085 printk(KERN_WARNING "%s: Resetting hardware: \n", dev->name);
1086 netif_stop_queue(dev) ;
1087 xl_freemem(dev) ;
1088 free_irq(dev->irq,dev);
1089 xl_reset(dev) ;
1090 writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
1091 spin_unlock(&xl_priv->xl_lock) ;
1092 return IRQ_HANDLED;
1093 } /* Host Error */
1094
1095 if (intstatus & SRBRINT ) { /* Srbc interrupt */
1096 writel(ACK_INTERRUPT | SRBRACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
1097 if (xl_priv->srb_queued)
1098 xl_srb_bh(dev) ;
1099 } /* SRBR Interrupt */
1100
1101 if (intstatus & TXUNDERRUN) { /* Issue DnReset command */
1102 writel(DNRESET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1103 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) { /* Wait for command to run */
1104 /* !!! FIX-ME !!!!
1105 Must put a timeout check here ! */
1106 /* Empty Loop */
1107 }
1108 printk(KERN_WARNING "%s: TX Underrun received \n",dev->name) ;
1109 writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
1110 } /* TxUnderRun */
1111
1112 if (intstatus & ARBCINT ) { /* Arbc interrupt */
1113 xl_arb_cmd(dev) ;
1114 } /* Arbc */
1115
1116 if (intstatus & ASBFINT) {
1117 if (xl_priv->asb_queued == 1) {
1118 xl_asb_cmd(dev) ;
1119 } else if (xl_priv->asb_queued == 2) {
1120 xl_asb_bh(dev) ;
1121 } else {
1122 writel(ACK_INTERRUPT | LATCH_ACK | ASBFACK, xl_mmio + MMIO_COMMAND) ;
1123 }
1124 } /* Asbf */
1125
1126 if (intstatus & UPCOMPINT ) /* UpComplete */
1127 xl_rx(dev) ;
1128
1129 if (intstatus & DNCOMPINT ) /* DnComplete */
1130 xl_dn_comp(dev) ;
1131
1132 if (intstatus & HARDERRINT ) { /* Hardware error */
1133 writel(MMIO_WORD_READ | MACSTATUS, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1134 macstatus = readw(xl_mmio + MMIO_MACDATA) ;
1135 printk(KERN_WARNING "%s: MacStatusError, details: ", dev->name);
1136 if (macstatus & (1<<14))
1137 printk(KERN_WARNING "tchk error: Unrecoverable error \n") ;
1138 if (macstatus & (1<<3))
1139 printk(KERN_WARNING "eint error: Internal watchdog timer expired \n") ;
1140 if (macstatus & (1<<2))
1141 printk(KERN_WARNING "aint error: Host tried to perform invalid operation \n") ;
1142 printk(KERN_WARNING "Instatus = %02x, macstatus = %02x\n",intstatus,macstatus) ;
1143 printk(KERN_WARNING "%s: Resetting hardware: \n", dev->name);
1144 netif_stop_queue(dev) ;
1145 xl_freemem(dev) ;
1146 free_irq(dev->irq,dev);
1147 unregister_netdev(dev) ;
1148 free_netdev(dev) ;
1149 xl_reset(dev) ;
1150 writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
1151 spin_unlock(&xl_priv->xl_lock) ;
1152 return IRQ_HANDLED;
1153 }
1154 } else {
1155 printk(KERN_WARNING "%s: Received Unknown interrupt : %04x \n", dev->name, intstatus) ;
1156 writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
1157 }
1158 }
1159
1160 /* Turn interrupts back on */
1161
1162 writel( SETINDENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
1163 writel( SETINTENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
1164
1165 spin_unlock(&xl_priv->xl_lock) ;
1166 return IRQ_HANDLED;
1167}
1168
1169/*
1170 * Tx - Polling configuration
1171 */
1172
1173static int xl_xmit(struct sk_buff *skb, struct net_device *dev)
1174{
1175 struct xl_private *xl_priv=(struct xl_private *)dev->priv;
1176 struct xl_tx_desc *txd ;
1177 int tx_head, tx_tail, tx_prev ;
1178 unsigned long flags ;
1179
1180 spin_lock_irqsave(&xl_priv->xl_lock,flags) ;
1181
1182 netif_stop_queue(dev) ;
1183
1184 if (xl_priv->free_ring_entries > 1 ) {
1185 /*
1186 * Set up the descriptor for the packet
1187 */
1188 tx_head = xl_priv->tx_ring_head ;
1189 tx_tail = xl_priv->tx_ring_tail ;
1190
1191 txd = &(xl_priv->xl_tx_ring[tx_head]) ;
1192 txd->dnnextptr = 0 ;
1193 txd->framestartheader = skb->len | TXDNINDICATE ;
1194 txd->buffer = pci_map_single(xl_priv->pdev, skb->data, skb->len, PCI_DMA_TODEVICE) ;
1195 txd->buffer_length = skb->len | TXDNFRAGLAST ;
1196 xl_priv->tx_ring_skb[tx_head] = skb ;
1197 xl_priv->xl_stats.tx_packets++ ;
1198 xl_priv->xl_stats.tx_bytes += skb->len ;
1199
1200 /*
1201 * Set the nextptr of the previous descriptor equal to this descriptor, add XL_TX_RING_SIZE -1
1202 * to ensure no negative numbers in unsigned locations.
1203 */
1204
1205 tx_prev = (xl_priv->tx_ring_head + XL_TX_RING_SIZE - 1) & (XL_TX_RING_SIZE - 1) ;
1206
1207 xl_priv->tx_ring_head++ ;
1208 xl_priv->tx_ring_head &= (XL_TX_RING_SIZE - 1) ;
1209 xl_priv->free_ring_entries-- ;
1210
1211 xl_priv->xl_tx_ring[tx_prev].dnnextptr = xl_priv->tx_ring_dma_addr + (sizeof (struct xl_tx_desc) * tx_head) ;
1212
1213 /* Sneaky, by doing a read on DnListPtr we can force the card to poll on the DnNextPtr */
1214 /* readl(xl_mmio + MMIO_DNLISTPTR) ; */
1215
1216 netif_wake_queue(dev) ;
1217
1218 spin_unlock_irqrestore(&xl_priv->xl_lock,flags) ;
1219
1220 return 0;
1221 } else {
1222 spin_unlock_irqrestore(&xl_priv->xl_lock,flags) ;
1223 return 1;
1224 }
1225
1226}
1227
1228/*
1229 * The NIC has told us that a packet has been downloaded onto the card, we must
1230 * find out which packet it has done, clear the skb and information for the packet
1231 * then advance around the ring for all tranmitted packets
1232 */
1233
1234static void xl_dn_comp(struct net_device *dev)
1235{
1236 struct xl_private *xl_priv=(struct xl_private *)dev->priv;
1237 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1238 struct xl_tx_desc *txd ;
1239
1240
1241 if (xl_priv->tx_ring_tail == 255) {/* First time */
1242 xl_priv->xl_tx_ring[0].framestartheader = 0 ;
1243 xl_priv->xl_tx_ring[0].dnnextptr = 0 ;
1244 xl_priv->tx_ring_tail = 1 ;
1245 }
1246
1247 while (xl_priv->xl_tx_ring[xl_priv->tx_ring_tail].framestartheader & TXDNCOMPLETE ) {
1248 txd = &(xl_priv->xl_tx_ring[xl_priv->tx_ring_tail]) ;
1249 pci_unmap_single(xl_priv->pdev,txd->buffer, xl_priv->tx_ring_skb[xl_priv->tx_ring_tail]->len, PCI_DMA_TODEVICE) ;
1250 txd->framestartheader = 0 ;
1251 txd->buffer = 0xdeadbeef ;
1252 txd->buffer_length = 0 ;
1253 dev_kfree_skb_irq(xl_priv->tx_ring_skb[xl_priv->tx_ring_tail]) ;
1254 xl_priv->tx_ring_tail++ ;
1255 xl_priv->tx_ring_tail &= (XL_TX_RING_SIZE - 1) ;
1256 xl_priv->free_ring_entries++ ;
1257 }
1258
1259 netif_wake_queue(dev) ;
1260
1261 writel(ACK_INTERRUPT | DNCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
1262}
1263
1264/*
1265 * Close the adapter properly.
1266 * This srb reply cannot be handled from interrupt context as we have
1267 * to free the interrupt from the driver.
1268 */
1269
1270static int xl_close(struct net_device *dev)
1271{
1272 struct xl_private *xl_priv = (struct xl_private *) dev->priv ;
1273 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1274 unsigned long t ;
1275
1276 netif_stop_queue(dev) ;
1277
1278 /*
1279 * Close the adapter, need to stall the rx and tx queues.
1280 */
1281
1282 writew(DNSTALL, xl_mmio + MMIO_COMMAND) ;
1283 t=jiffies;
1284 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
1285 schedule();
1286 if(jiffies-t > 10*HZ) {
1287 printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-DNSTALL not responding.\n", dev->name);
1288 break ;
1289 }
1290 }
1291 writew(DNDISABLE, xl_mmio + MMIO_COMMAND) ;
1292 t=jiffies;
1293 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
1294 schedule();
1295 if(jiffies-t > 10*HZ) {
1296 printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-DNDISABLE not responding.\n", dev->name);
1297 break ;
1298 }
1299 }
1300 writew(UPSTALL, xl_mmio + MMIO_COMMAND) ;
1301 t=jiffies;
1302 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
1303 schedule();
1304 if(jiffies-t > 10*HZ) {
1305 printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-UPSTALL not responding.\n", dev->name);
1306 break ;
1307 }
1308 }
1309
1310 /* Turn off interrupts, we will still get the indication though
1311 * so we can trap it
1312 */
1313
1314 writel(SETINTENABLE, xl_mmio + MMIO_COMMAND) ;
1315
1316 xl_srb_cmd(dev,CLOSE_NIC) ;
1317
1318 t=jiffies;
1319 while (!(readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_SRB)) {
1320 schedule();
1321 if(jiffies-t > 10*HZ) {
1322 printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-CLOSENIC not responding.\n", dev->name);
1323 break ;
1324 }
1325 }
1326 /* Read the srb response from the adapter */
1327
1328 writel(MEM_BYTE_READ | 0xd0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD);
1329 if (readb(xl_mmio + MMIO_MACDATA) != CLOSE_NIC) {
1330 printk(KERN_INFO "%s: CLOSE_NIC did not get a CLOSE_NIC response \n",dev->name) ;
1331 } else {
1332 writel((MEM_BYTE_READ | 0xd0000 | xl_priv->srb) +2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1333 if (readb(xl_mmio + MMIO_MACDATA)==0) {
1334 printk(KERN_INFO "%s: Adapter has been closed \n",dev->name) ;
1335 writew(ACK_INTERRUPT | SRBRACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
1336
1337 xl_freemem(dev) ;
1338 free_irq(dev->irq,dev) ;
1339 } else {
1340 printk(KERN_INFO "%s: Close nic command returned error code %02x\n",dev->name, readb(xl_mmio + MMIO_MACDATA)) ;
1341 }
1342 }
1343
1344 /* Reset the upload and download logic */
1345
1346 writew(UPRESET, xl_mmio + MMIO_COMMAND) ;
1347 t=jiffies;
1348 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
1349 schedule();
1350 if(jiffies-t > 10*HZ) {
1351 printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-UPRESET not responding.\n", dev->name);
1352 break ;
1353 }
1354 }
1355 writew(DNRESET, xl_mmio + MMIO_COMMAND) ;
1356 t=jiffies;
1357 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
1358 schedule();
1359 if(jiffies-t > 10*HZ) {
1360 printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-DNRESET not responding.\n", dev->name);
1361 break ;
1362 }
1363 }
1364 xl_hw_reset(dev) ;
1365 return 0 ;
1366}
1367
1368static void xl_set_rx_mode(struct net_device *dev)
1369{
1370 struct xl_private *xl_priv = (struct xl_private *) dev->priv ;
1371 struct dev_mc_list *dmi ;
1372 unsigned char dev_mc_address[4] ;
1373 u16 options ;
1374 int i ;
1375
1376 if (dev->flags & IFF_PROMISC)
1377 options = 0x0004 ;
1378 else
1379 options = 0x0000 ;
1380
1381 if (options ^ xl_priv->xl_copy_all_options) { /* Changed, must send command */
1382 xl_priv->xl_copy_all_options = options ;
1383 xl_srb_cmd(dev, SET_RECEIVE_MODE) ;
1384 return ;
1385 }
1386
1387 dev_mc_address[0] = dev_mc_address[1] = dev_mc_address[2] = dev_mc_address[3] = 0 ;
1388
1389 for (i=0,dmi=dev->mc_list;i < dev->mc_count; i++,dmi = dmi->next) {
1390 dev_mc_address[0] |= dmi->dmi_addr[2] ;
1391 dev_mc_address[1] |= dmi->dmi_addr[3] ;
1392 dev_mc_address[2] |= dmi->dmi_addr[4] ;
1393 dev_mc_address[3] |= dmi->dmi_addr[5] ;
1394 }
1395
1396 if (memcmp(xl_priv->xl_functional_addr,dev_mc_address,4) != 0) { /* Options have changed, run the command */
1397 memcpy(xl_priv->xl_functional_addr, dev_mc_address,4) ;
1398 xl_srb_cmd(dev, SET_FUNC_ADDRESS) ;
1399 }
1400 return ;
1401}
1402
1403
1404/*
1405 * We issued an srb command and now we must read
1406 * the response from the completed command.
1407 */
1408
1409static void xl_srb_bh(struct net_device *dev)
1410{
1411 struct xl_private *xl_priv = (struct xl_private *) dev->priv ;
1412 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1413 u8 srb_cmd, ret_code ;
1414 int i ;
1415
1416 writel(MEM_BYTE_READ | 0xd0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1417 srb_cmd = readb(xl_mmio + MMIO_MACDATA) ;
1418 writel((MEM_BYTE_READ | 0xd0000 | xl_priv->srb) +2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1419 ret_code = readb(xl_mmio + MMIO_MACDATA) ;
1420
1421 /* Ret_code is standard across all commands */
1422
1423 switch (ret_code) {
1424 case 1:
1425 printk(KERN_INFO "%s: Command: %d - Invalid Command code\n",dev->name,srb_cmd) ;
1426 break ;
1427 case 4:
1428 printk(KERN_INFO "%s: Command: %d - Adapter is closed, must be open for this command \n",dev->name,srb_cmd) ;
1429 break ;
1430
1431 case 6:
1432 printk(KERN_INFO "%s: Command: %d - Options Invalid for command \n",dev->name,srb_cmd) ;
1433 break ;
1434
1435 case 0: /* Successful command execution */
1436 switch (srb_cmd) {
1437 case READ_LOG: /* Returns 14 bytes of data from the NIC */
1438 if(xl_priv->xl_message_level)
1439 printk(KERN_INFO "%s: READ.LOG 14 bytes of data ",dev->name) ;
1440 /*
1441 * We still have to read the log even if message_level = 0 and we don't want
1442 * to see it
1443 */
1444 for (i=0;i<14;i++) {
1445 writel(MEM_BYTE_READ | 0xd0000 | xl_priv->srb | i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1446 if(xl_priv->xl_message_level)
1447 printk("%02x:",readb(xl_mmio + MMIO_MACDATA)) ;
1448 }
1449 printk("\n") ;
1450 break ;
1451 case SET_FUNC_ADDRESS:
1452 if(xl_priv->xl_message_level)
1453 printk(KERN_INFO "%s: Functional Address Set \n",dev->name) ;
1454 break ;
1455 case CLOSE_NIC:
1456 if(xl_priv->xl_message_level)
1457 printk(KERN_INFO "%s: Received CLOSE_NIC interrupt in interrupt handler \n",dev->name) ;
1458 break ;
1459 case SET_MULTICAST_MODE:
1460 if(xl_priv->xl_message_level)
1461 printk(KERN_INFO "%s: Multicast options successfully changed\n",dev->name) ;
1462 break ;
1463 case SET_RECEIVE_MODE:
1464 if(xl_priv->xl_message_level) {
1465 if (xl_priv->xl_copy_all_options == 0x0004)
1466 printk(KERN_INFO "%s: Entering promiscuous mode \n", dev->name) ;
1467 else
1468 printk(KERN_INFO "%s: Entering normal receive mode \n",dev->name) ;
1469 }
1470 break ;
1471
1472 } /* switch */
1473 break ;
1474 } /* switch */
1475 return ;
1476}
1477
1478static struct net_device_stats * xl_get_stats(struct net_device *dev)
1479{
1480 struct xl_private *xl_priv = (struct xl_private *) dev->priv ;
1481 return (struct net_device_stats *) &xl_priv->xl_stats;
1482}
1483
1484static int xl_set_mac_address (struct net_device *dev, void *addr)
1485{
1486 struct sockaddr *saddr = addr ;
1487 struct xl_private *xl_priv = (struct xl_private *)dev->priv ;
1488
1489 if (netif_running(dev)) {
1490 printk(KERN_WARNING "%s: Cannot set mac/laa address while card is open\n", dev->name) ;
1491 return -EIO ;
1492 }
1493
1494 memcpy(xl_priv->xl_laa, saddr->sa_data,dev->addr_len) ;
1495
1496 if (xl_priv->xl_message_level) {
1497 printk(KERN_INFO "%s: MAC/LAA Set to = %x.%x.%x.%x.%x.%x\n",dev->name, xl_priv->xl_laa[0],
1498 xl_priv->xl_laa[1], xl_priv->xl_laa[2],
1499 xl_priv->xl_laa[3], xl_priv->xl_laa[4],
1500 xl_priv->xl_laa[5]);
1501 }
1502
1503 return 0 ;
1504}
1505
1506static void xl_arb_cmd(struct net_device *dev)
1507{
1508 struct xl_private *xl_priv = (struct xl_private *) dev->priv;
1509 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1510 u8 arb_cmd ;
1511 u16 lan_status, lan_status_diff ;
1512
1513 writel( ( MEM_BYTE_READ | 0xD0000 | xl_priv->arb), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1514 arb_cmd = readb(xl_mmio + MMIO_MACDATA) ;
1515
1516 if (arb_cmd == RING_STATUS_CHANGE) { /* Ring.Status.Change */
1517 writel( ( (MEM_WORD_READ | 0xD0000 | xl_priv->arb) + 6), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1518
1519 printk(KERN_INFO "%s: Ring Status Change: New Status = %04x\n", dev->name, ntohs(readw(xl_mmio + MMIO_MACDATA) )) ;
1520
1521 lan_status = ntohs(readw(xl_mmio + MMIO_MACDATA));
1522
1523 /* Acknowledge interrupt, this tells nic we are done with the arb */
1524 writel(ACK_INTERRUPT | ARBCACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
1525
1526 lan_status_diff = xl_priv->xl_lan_status ^ lan_status ;
1527
1528 if (lan_status_diff & (LSC_LWF | LSC_ARW | LSC_FPE | LSC_RR) ) {
1529 if (lan_status_diff & LSC_LWF)
1530 printk(KERN_WARNING "%s: Short circuit detected on the lobe\n",dev->name);
1531 if (lan_status_diff & LSC_ARW)
1532 printk(KERN_WARNING "%s: Auto removal error\n",dev->name);
1533 if (lan_status_diff & LSC_FPE)
1534 printk(KERN_WARNING "%s: FDX Protocol Error\n",dev->name);
1535 if (lan_status_diff & LSC_RR)
1536 printk(KERN_WARNING "%s: Force remove MAC frame received\n",dev->name);
1537
1538 /* Adapter has been closed by the hardware */
1539
1540 netif_stop_queue(dev);
1541 xl_freemem(dev) ;
1542 free_irq(dev->irq,dev);
1543
1544 printk(KERN_WARNING "%s: Adapter has been closed \n", dev->name) ;
1545 } /* If serious error */
1546
1547 if (xl_priv->xl_message_level) {
1548 if (lan_status_diff & LSC_SIG_LOSS)
1549 printk(KERN_WARNING "%s: No receive signal detected \n", dev->name) ;
1550 if (lan_status_diff & LSC_HARD_ERR)
1551 printk(KERN_INFO "%s: Beaconing \n",dev->name);
1552 if (lan_status_diff & LSC_SOFT_ERR)
1553 printk(KERN_WARNING "%s: Adapter transmitted Soft Error Report Mac Frame \n",dev->name);
1554 if (lan_status_diff & LSC_TRAN_BCN)
1555 printk(KERN_INFO "%s: We are tranmitting the beacon, aaah\n",dev->name);
1556 if (lan_status_diff & LSC_SS)
1557 printk(KERN_INFO "%s: Single Station on the ring \n", dev->name);
1558 if (lan_status_diff & LSC_RING_REC)
1559 printk(KERN_INFO "%s: Ring recovery ongoing\n",dev->name);
1560 if (lan_status_diff & LSC_FDX_MODE)
1561 printk(KERN_INFO "%s: Operating in FDX mode\n",dev->name);
1562 }
1563
1564 if (lan_status_diff & LSC_CO) {
1565 if (xl_priv->xl_message_level)
1566 printk(KERN_INFO "%s: Counter Overflow \n", dev->name);
1567 /* Issue READ.LOG command */
1568 xl_srb_cmd(dev, READ_LOG) ;
1569 }
1570
1571 /* There is no command in the tech docs to issue the read_sr_counters */
1572 if (lan_status_diff & LSC_SR_CO) {
1573 if (xl_priv->xl_message_level)
1574 printk(KERN_INFO "%s: Source routing counters overflow\n", dev->name);
1575 }
1576
1577 xl_priv->xl_lan_status = lan_status ;
1578
1579 } /* Lan.change.status */
1580 else if ( arb_cmd == RECEIVE_DATA) { /* Received.Data */
1581#if XL_DEBUG
1582 printk(KERN_INFO "Received.Data \n") ;
1583#endif
1584 writel( ((MEM_WORD_READ | 0xD0000 | xl_priv->arb) + 6), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1585 xl_priv->mac_buffer = ntohs(readw(xl_mmio + MMIO_MACDATA)) ;
1586
1587 /* Now we are going to be really basic here and not do anything
1588 * with the data at all. The tech docs do not give me enough
1589 * information to calculate the buffers properly so we're
1590 * just going to tell the nic that we've dealt with the frame
1591 * anyway.
1592 */
1593
1594 dev->last_rx = jiffies ;
1595 /* Acknowledge interrupt, this tells nic we are done with the arb */
1596 writel(ACK_INTERRUPT | ARBCACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
1597
1598 /* Is the ASB free ? */
1599
1600 xl_priv->asb_queued = 0 ;
1601 writel( ((MEM_BYTE_READ | 0xD0000 | xl_priv->asb) + 2), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1602 if (readb(xl_mmio + MMIO_MACDATA) != 0xff) {
1603 xl_priv->asb_queued = 1 ;
1604
1605 xl_wait_misr_flags(dev) ;
1606
1607 writel(MEM_BYTE_WRITE | MF_ASBFR, xl_mmio + MMIO_MAC_ACCESS_CMD);
1608 writeb(0xff, xl_mmio + MMIO_MACDATA) ;
1609 writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1610 writeb(MISR_ASBFR, xl_mmio + MMIO_MACDATA) ;
1611 return ;
1612 /* Drop out and wait for the bottom half to be run */
1613 }
1614
1615 xl_asb_cmd(dev) ;
1616
1617 } else {
1618 printk(KERN_WARNING "%s: Received unknown arb (xl_priv) command: %02x \n",dev->name,arb_cmd) ;
1619 }
1620
1621 /* Acknowledge the arb interrupt */
1622
1623 writel(ACK_INTERRUPT | ARBCACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
1624
1625 return ;
1626}
1627
1628
1629/*
1630 * There is only one asb command, but we can get called from different
1631 * places.
1632 */
1633
1634static void xl_asb_cmd(struct net_device *dev)
1635{
1636 struct xl_private *xl_priv = (struct xl_private *) dev->priv ;
1637 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1638
1639 if (xl_priv->asb_queued == 1)
1640 writel(ACK_INTERRUPT | LATCH_ACK | ASBFACK, xl_mmio + MMIO_COMMAND) ;
1641
1642 writel(MEM_BYTE_WRITE | 0xd0000 | xl_priv->asb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1643 writeb(0x81, xl_mmio + MMIO_MACDATA) ;
1644
1645 writel(MEM_WORD_WRITE | 0xd0000 | xl_priv->asb | 6, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1646 writew(ntohs(xl_priv->mac_buffer), xl_mmio + MMIO_MACDATA) ;
1647
1648 xl_wait_misr_flags(dev) ;
1649
1650 writel(MEM_BYTE_WRITE | MF_RASB, xl_mmio + MMIO_MAC_ACCESS_CMD);
1651 writeb(0xff, xl_mmio + MMIO_MACDATA) ;
1652
1653 writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1654 writeb(MISR_RASB, xl_mmio + MMIO_MACDATA) ;
1655
1656 xl_priv->asb_queued = 2 ;
1657
1658 return ;
1659}
1660
1661/*
1662 * This will only get called if there was an error
1663 * from the asb cmd.
1664 */
1665static void xl_asb_bh(struct net_device *dev)
1666{
1667 struct xl_private *xl_priv = (struct xl_private *) dev->priv ;
1668 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1669 u8 ret_code ;
1670
1671 writel(MMIO_BYTE_READ | 0xd0000 | xl_priv->asb | 2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1672 ret_code = readb(xl_mmio + MMIO_MACDATA) ;
1673 switch (ret_code) {
1674 case 0x01:
1675 printk(KERN_INFO "%s: ASB Command, unrecognized command code \n",dev->name) ;
1676 break ;
1677 case 0x26:
1678 printk(KERN_INFO "%s: ASB Command, unexpected receive buffer \n", dev->name) ;
1679 break ;
1680 case 0x40:
1681 printk(KERN_INFO "%s: ASB Command, Invalid Station ID \n", dev->name) ;
1682 break ;
1683 }
1684 xl_priv->asb_queued = 0 ;
1685 writel(ACK_INTERRUPT | LATCH_ACK | ASBFACK, xl_mmio + MMIO_COMMAND) ;
1686 return ;
1687}
1688
1689/*
1690 * Issue srb commands to the nic
1691 */
1692
1693static void xl_srb_cmd(struct net_device *dev, int srb_cmd)
1694{
1695 struct xl_private *xl_priv = (struct xl_private *) dev->priv ;
1696 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1697
1698 switch (srb_cmd) {
1699 case READ_LOG:
1700 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1701 writeb(READ_LOG, xl_mmio + MMIO_MACDATA) ;
1702 break;
1703
1704 case CLOSE_NIC:
1705 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1706 writeb(CLOSE_NIC, xl_mmio + MMIO_MACDATA) ;
1707 break ;
1708
1709 case SET_RECEIVE_MODE:
1710 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1711 writeb(SET_RECEIVE_MODE, xl_mmio + MMIO_MACDATA) ;
1712 writel(MEM_WORD_WRITE | 0xD0000 | xl_priv->srb | 4, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1713 writew(xl_priv->xl_copy_all_options, xl_mmio + MMIO_MACDATA) ;
1714 break ;
1715
1716 case SET_FUNC_ADDRESS:
1717 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1718 writeb(SET_FUNC_ADDRESS, xl_mmio + MMIO_MACDATA) ;
1719 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 6 , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1720 writeb(xl_priv->xl_functional_addr[0], xl_mmio + MMIO_MACDATA) ;
1721 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 7 , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1722 writeb(xl_priv->xl_functional_addr[1], xl_mmio + MMIO_MACDATA) ;
1723 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 8 , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1724 writeb(xl_priv->xl_functional_addr[2], xl_mmio + MMIO_MACDATA) ;
1725 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 9 , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1726 writeb(xl_priv->xl_functional_addr[3], xl_mmio + MMIO_MACDATA) ;
1727 break ;
1728 } /* switch */
1729
1730
1731 xl_wait_misr_flags(dev) ;
1732
1733 /* Write 0xff to the CSRB flag */
1734 writel(MEM_BYTE_WRITE | MF_CSRB , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1735 writeb(0xFF, xl_mmio + MMIO_MACDATA) ;
1736 /* Set csrb bit in MISR register to process command */
1737 writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1738 writeb(MISR_CSRB, xl_mmio + MMIO_MACDATA) ;
1739 xl_priv->srb_queued = 1 ;
1740
1741 return ;
1742}
1743
1744/*
1745 * This is nasty, to use the MISR command you have to wait for 6 memory locations
1746 * to be zero. This is the way the driver does on other OS'es so we should be ok with
1747 * the empty loop.
1748 */
1749
1750static void xl_wait_misr_flags(struct net_device *dev)
1751{
1752 struct xl_private *xl_priv = (struct xl_private *) dev->priv ;
1753 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1754
1755 int i ;
1756
1757 writel(MMIO_BYTE_READ | MISR_RW, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1758 if (readb(xl_mmio + MMIO_MACDATA) != 0) { /* Misr not clear */
1759 for (i=0; i<6; i++) {
1760 writel(MEM_BYTE_READ | 0xDFFE0 | i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1761 while (readb(xl_mmio + MMIO_MACDATA) != 0 ) {} ; /* Empty Loop */
1762 }
1763 }
1764
1765 writel(MMIO_BYTE_WRITE | MISR_AND, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1766 writeb(0x80, xl_mmio + MMIO_MACDATA) ;
1767
1768 return ;
1769}
1770
1771/*
1772 * Change mtu size, this should work the same as olympic
1773 */
1774
1775static int xl_change_mtu(struct net_device *dev, int mtu)
1776{
1777 struct xl_private *xl_priv = (struct xl_private *) dev->priv;
1778 u16 max_mtu ;
1779
1780 if (xl_priv->xl_ring_speed == 4)
1781 max_mtu = 4500 ;
1782 else
1783 max_mtu = 18000 ;
1784
1785 if (mtu > max_mtu)
1786 return -EINVAL ;
1787 if (mtu < 100)
1788 return -EINVAL ;
1789
1790 dev->mtu = mtu ;
1791 xl_priv->pkt_buf_sz = mtu + TR_HLEN ;
1792
1793 return 0 ;
1794}
1795
1796static void __devexit xl_remove_one (struct pci_dev *pdev)
1797{
1798 struct net_device *dev = pci_get_drvdata(pdev);
1799 struct xl_private *xl_priv=(struct xl_private *)dev->priv;
1800
1801 unregister_netdev(dev);
1802 iounmap(xl_priv->xl_mmio) ;
1803 pci_release_regions(pdev) ;
1804 pci_set_drvdata(pdev,NULL) ;
1805 free_netdev(dev);
1806 return ;
1807}
1808
1809static struct pci_driver xl_3c359_driver = {
1810 .name = "3c359",
1811 .id_table = xl_pci_tbl,
1812 .probe = xl_probe,
1813 .remove = __devexit_p(xl_remove_one),
1814};
1815
1816static int __init xl_pci_init (void)
1817{
1818 return pci_module_init (&xl_3c359_driver);
1819}
1820
1821
1822static void __exit xl_pci_cleanup (void)
1823{
1824 pci_unregister_driver (&xl_3c359_driver);
1825}
1826
1827module_init(xl_pci_init);
1828module_exit(xl_pci_cleanup);
1829
1830MODULE_LICENSE("GPL") ;
diff --git a/drivers/net/tokenring/3c359.h b/drivers/net/tokenring/3c359.h
new file mode 100644
index 000000000000..05c860368852
--- /dev/null
+++ b/drivers/net/tokenring/3c359.h
@@ -0,0 +1,290 @@
1/*
2 * 3c359.h (c) 2000 Mike Phillips (mikep@linuxtr.net) All Rights Reserved
3 *
4 * Linux driver for 3Com 3C359 Token Link PCI XL cards.
5 *
6 * This software may be used and distributed according to the terms
7 * of the GNU General Public License Version 2 or (at your option)
8 * any later verion, incorporated herein by reference.
9 */
10
11/* Memory Access Commands */
12#define IO_BYTE_READ 0x28 << 24
13#define IO_BYTE_WRITE 0x18 << 24
14#define IO_WORD_READ 0x20 << 24
15#define IO_WORD_WRITE 0x10 << 24
16#define MMIO_BYTE_READ 0x88 << 24
17#define MMIO_BYTE_WRITE 0x48 << 24
18#define MMIO_WORD_READ 0x80 << 24
19#define MMIO_WORD_WRITE 0x40 << 24
20#define MEM_BYTE_READ 0x8C << 24
21#define MEM_BYTE_WRITE 0x4C << 24
22#define MEM_WORD_READ 0x84 << 24
23#define MEM_WORD_WRITE 0x44 << 24
24
25#define PMBAR 0x1C80
26#define PMB_CPHOLD (1<<10)
27
28#define CPATTENTION 0x180D
29#define CPA_PMBARVIS (1<<7)
30#define CPA_MEMWREN (1<<6)
31
32#define SWITCHSETTINGS 0x1C88
33#define EECONTROL 0x1C8A
34#define EEDATA 0x1C8C
35#define EEREAD 0x0080
36#define EEWRITE 0x0040
37#define EEERASE 0x0060
38#define EE_ENABLE_WRITE 0x0030
39#define EEBUSY (1<<15)
40
41#define WRBR 0xCDE02
42#define WWOR 0xCDE04
43#define WWCR 0xCDE06
44#define MACSTATUS 0xCDE08
45#define MISR_RW 0xCDE0B
46#define MISR_AND 0xCDE2B
47#define MISR_SET 0xCDE4B
48#define RXBUFAREA 0xCDE10
49#define RXEARLYTHRESH 0xCDE12
50#define TXSTARTTHRESH 0x58
51#define DNPRIREQTHRESH 0x2C
52
53#define MISR_CSRB (1<<5)
54#define MISR_RASB (1<<4)
55#define MISR_SRBFR (1<<3)
56#define MISR_ASBFR (1<<2)
57#define MISR_ARBF (1<<1)
58
59/* MISR Flags memory locations */
60#define MF_SSBF 0xDFFE0
61#define MF_ARBF 0xDFFE1
62#define MF_ASBFR 0xDFFE2
63#define MF_SRBFR 0xDFFE3
64#define MF_RASB 0xDFFE4
65#define MF_CSRB 0xDFFE5
66
67#define MMIO_MACDATA 0x10
68#define MMIO_MAC_ACCESS_CMD 0x14
69#define MMIO_TIMER 0x1A
70#define MMIO_DMA_CTRL 0x20
71#define MMIO_DNLISTPTR 0x24
72#define MMIO_HASHFILTER 0x28
73#define MMIO_CONFIG 0x29
74#define MMIO_DNPRIREQTHRESH 0x2C
75#define MMIO_DNPOLL 0x2D
76#define MMIO_UPPKTSTATUS 0x30
77#define MMIO_FREETIMER 0x34
78#define MMIO_COUNTDOWN 0x36
79#define MMIO_UPLISTPTR 0x38
80#define MMIO_UPPOLL 0x3C
81#define MMIO_UPBURSTTHRESH 0x40
82#define MMIO_DNBURSTTHRESH 0x41
83#define MMIO_INTSTATUS_AUTO 0x56
84#define MMIO_TXSTARTTHRESH 0x58
85#define MMIO_INTERRUPTENABLE 0x5A
86#define MMIO_INDICATIONENABLE 0x5C
87#define MMIO_COMMAND 0x5E /* These two are meant to be the same */
88#define MMIO_INTSTATUS 0x5E /* Makes the code more readable this way */
89#define INTSTAT_CMD_IN_PROGRESS (1<<12)
90#define INTSTAT_SRB (1<<14)
91#define INTSTAT_INTLATCH (1<<0)
92
93/* Indication / Interrupt Mask
94 * Annoyingly the bits to be set in the indication and interrupt enable
95 * do not match with the actual bits received in the interrupt, although
96 * they are in the same order.
97 * The mapping for the indication / interrupt are:
98 * Bit Indication / Interrupt
99 * 0 HostError
100 * 1 txcomplete
101 * 2 updneeded
102 * 3 rxcomplete
103 * 4 intrequested
104 * 5 macerror
105 * 6 dncomplete
106 * 7 upcomplete
107 * 8 txunderrun
108 * 9 asbf
109 * 10 srbr
110 * 11 arbc
111 *
112 * The only ones we don't want to receive are txcomplete and rxcomplete
113 * we use dncomplete and upcomplete instead.
114 */
115
116#define INT_MASK 0xFF5
117
118/* Note the subtle difference here, IND and INT */
119
120#define SETINDENABLE (8<<12)
121#define SETINTENABLE (7<<12)
122#define SRBBIT (1<<10)
123#define ASBBIT (1<<9)
124#define ARBBIT (1<<11)
125
126#define SRB 0xDFE90
127#define ASB 0xDFED0
128#define ARB 0xD0000
129#define SCRATCH 0xDFEF0
130
131#define INT_REQUEST 0x6000 /* (6 << 12) */
132#define ACK_INTERRUPT 0x6800 /* (13 <<11) */
133#define GLOBAL_RESET 0x00
134#define DNDISABLE 0x5000
135#define DNENABLE 0x4800
136#define DNSTALL 0x3002
137#define DNRESET 0x5800
138#define DNUNSTALL 0x3003
139#define UPRESET 0x2800
140#define UPSTALL 0x3000
141#define UPUNSTALL 0x3001
142#define SETCONFIG 0x4000
143#define SETTXSTARTTHRESH 0x9800
144
145/* Received Interrupts */
146#define ASBFINT (1<<13)
147#define SRBRINT (1<<14)
148#define ARBCINT (1<<15)
149#define TXUNDERRUN (1<<11)
150
151#define UPCOMPINT (1<<10)
152#define DNCOMPINT (1<<9)
153#define HARDERRINT (1<<7)
154#define RXCOMPLETE (1<<4)
155#define TXCOMPINT (1<<2)
156#define HOSTERRINT (1<<1)
157
158/* Receive descriptor bits */
159#define RXOVERRUN (1<<19)
160#define RXFC (1<<21)
161#define RXAR (1<<22)
162#define RXUPDCOMPLETE (1<<23)
163#define RXUPDFULL (1<<24)
164#define RXUPLASTFRAG (1<<31)
165
166/* Transmit descriptor bits */
167#define TXDNCOMPLETE (1<<16)
168#define TXTXINDICATE (1<<27)
169#define TXDPDEMPTY (1<<29)
170#define TXDNINDICATE (1<<31)
171#define TXDNFRAGLAST (1<<31)
172
173/* Interrupts to Acknowledge */
174#define LATCH_ACK 1
175#define TXCOMPACK (1<<1)
176#define INTREQACK (1<<2)
177#define DNCOMPACK (1<<3)
178#define UPCOMPACK (1<<4)
179#define ASBFACK (1<<5)
180#define SRBRACK (1<<6)
181#define ARBCACK (1<<7)
182
183#define XL_IO_SPACE 128
184#define SRB_COMMAND_SIZE 50
185
186/* Adapter Commands */
187#define REQUEST_INT 0x00
188#define MODIFY_OPEN_PARMS 0x01
189#define RESTORE_OPEN_PARMS 0x02
190#define OPEN_NIC 0x03
191#define CLOSE_NIC 0x04
192#define SET_SLEEP_MODE 0x05
193#define SET_GROUP_ADDRESS 0x06
194#define SET_FUNC_ADDRESS 0x07
195#define READ_LOG 0x08
196#define SET_MULTICAST_MODE 0x0C
197#define CHANGE_WAKEUP_PATTERN 0x0D
198#define GET_STATISTICS 0x13
199#define SET_RECEIVE_MODE 0x1F
200
201/* ARB Commands */
202#define RECEIVE_DATA 0x81
203#define RING_STATUS_CHANGE 0x84
204
205/* ASB Commands */
206#define ASB_RECEIVE_DATE 0x81
207
208/* Defines for LAN STATUS CHANGE reports */
209#define LSC_SIG_LOSS 0x8000
210#define LSC_HARD_ERR 0x4000
211#define LSC_SOFT_ERR 0x2000
212#define LSC_TRAN_BCN 0x1000
213#define LSC_LWF 0x0800
214#define LSC_ARW 0x0400
215#define LSC_FPE 0x0200
216#define LSC_RR 0x0100
217#define LSC_CO 0x0080
218#define LSC_SS 0x0040
219#define LSC_RING_REC 0x0020
220#define LSC_SR_CO 0x0010
221#define LSC_FDX_MODE 0x0004
222
223#define XL_MAX_ADAPTERS 8 /* 0x08 __MODULE_STRING can't hand 0xnn */
224
225/* 3c359 defaults for buffers */
226
227#define XL_RX_RING_SIZE 16 /* must be a power of 2 */
228#define XL_TX_RING_SIZE 16 /* must be a power of 2 */
229
230#define PKT_BUF_SZ 4096 /* Default packet size */
231
232/* 3c359 data structures */
233
234struct xl_tx_desc {
235 u32 dnnextptr ;
236 u32 framestartheader ;
237 u32 buffer ;
238 u32 buffer_length ;
239};
240
241struct xl_rx_desc {
242 u32 upnextptr ;
243 u32 framestatus ;
244 u32 upfragaddr ;
245 u32 upfraglen ;
246};
247
248struct xl_private {
249
250
251 /* These two structures must be aligned on 8 byte boundaries */
252
253 /* struct xl_rx_desc xl_rx_ring[XL_RX_RING_SIZE]; */
254 /* struct xl_tx_desc xl_tx_ring[XL_TX_RING_SIZE]; */
255 struct xl_rx_desc *xl_rx_ring ;
256 struct xl_tx_desc *xl_tx_ring ;
257 struct sk_buff *tx_ring_skb[XL_TX_RING_SIZE], *rx_ring_skb[XL_RX_RING_SIZE];
258 int tx_ring_head, tx_ring_tail ;
259 int rx_ring_tail, rx_ring_no ;
260 int free_ring_entries ;
261
262 u16 srb;
263 u16 arb;
264 u16 asb;
265
266 u8 __iomem *xl_mmio;
267 char *xl_card_name;
268 struct pci_dev *pdev ;
269
270 spinlock_t xl_lock ;
271
272 volatile int srb_queued;
273 struct wait_queue *srb_wait;
274 volatile int asb_queued;
275
276 struct net_device_stats xl_stats ;
277
278 u16 mac_buffer ;
279 u16 xl_lan_status ;
280 u8 xl_ring_speed ;
281 u16 pkt_buf_sz ;
282 u8 xl_message_level;
283 u16 xl_copy_all_options ;
284 unsigned char xl_functional_addr[4] ;
285 u16 xl_addr_table_addr, xl_parms_addr ;
286 u8 xl_laa[6] ;
287 u32 rx_ring_dma_addr ;
288 u32 tx_ring_dma_addr ;
289};
290
diff --git a/drivers/net/tokenring/3c359_microcode.h b/drivers/net/tokenring/3c359_microcode.h
new file mode 100644
index 000000000000..81354afa3d34
--- /dev/null
+++ b/drivers/net/tokenring/3c359_microcode.h
@@ -0,0 +1,1581 @@
1
2/*
3 * The firmware this driver downloads into the tokenring card is a
4 * separate program and is not GPL'd source code, even though the Linux
5 * side driver and the routine that loads this data into the card are.
6 *
7 * This firmware is licensed to you strictly for use in conjunction
8 * with the use of 3Com 3C359 TokenRing adapters. There is no
9 * waranty expressed or implied about its fitness for any purpose.
10 */
11
12/* 3c359_microcode.mac: 3Com 3C359 Tokenring microcode.
13 *
14 * Notes:
15 * - Loaded from xl_init upon adapter initialization.
16 *
17 * Available from 3Com as part of their standard 3C359 driver.
18 *
19 * mc_size *must* must match the microcode being used, each version is a
20 * different length.
21 */
22
23static int mc_size = 24880 ;
24
25u8 microcode[] = {
26 0xfe,0x3a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
27,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
28,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
29,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
30,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x33,0x2f,0x30,0x32,0x2f,0x39,0x39,0x20,0x31
31,0x37,0x3a,0x31,0x33,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
32,0x30,0x31,0x32,0x33,0x34,0x35,0x36,0x37,0x38,0x39,0x41,0x42,0x43,0x44,0x45,0x46
33,0x00,0x00,0x07,0xff,0x02,0x00,0xfe,0x9f,0x06,0x00,0x00,0x7c,0x48,0x00,0x00,0x70
34,0x82,0x00,0xff,0xff,0x86,0x00,0xff,0xff,0x88,0x00,0xff,0xff,0x9a,0x00,0xff,0xff
35,0xff,0xff,0x11,0x00,0xc0,0x00,0xff,0xff,0xff,0xff,0x11,0x22,0x33,0x44,0x55,0x66
36,0x33,0x43,0x4f,0x4d,0x20,0x42,0x41,0x42,0x45,0x11,0x40,0xc0,0x00,0xff,0xff,0xff
37,0xff,0x11,0x22,0x33,0x44,0x55,0x66,0x53,0x74,0x61,0x72,0x74,0x20,0x6f,0x66,0x20
38,0x4c,0x4c,0x43,0x20,0x66,0x72,0x61,0x6d,0x65,0x2e,0x20,0x20,0x54,0x6f,0x74,0x61
39,0x6c,0x20,0x64,0x61,0x74,0x61,0x20,0x73,0x69,0x7a,0x65,0x20,0x69,0x73,0x20,0x78
40,0x78,0x78,0x20,0x20,0x20,0x42,0x41,0x42,0x45,0xe8,0xd2,0x01,0x83,0x3e,0xf7,0x34
41,0x00,0x75,0x21,0xe8,0x41,0x00,0x83,0x3e,0xf7,0x34,0x00,0x75,0x17,0xe8,0x82,0x00
42,0x83,0x3e,0xf7,0x34,0x00,0x75,0x0d,0xe8,0xbf,0x00,0x83,0x3e,0xf7,0x34,0x00,0x75
43,0x03,0xe8,0x41,0x02,0xc3,0x1e,0xb8,0x00,0xf0,0x8e,0xd8,0x33,0xf6,0xb9,0x00,0x80
44,0x33,0xdb,0xad,0x03,0xd8,0xe2,0xfb,0x1f,0xb8,0x00,0x00,0x83,0xfb,0x00,0x74,0x03
45,0xb8,0x22,0x00,0xa3,0xf7,0x34,0xc3,0xfa,0xba,0x56,0x00,0xb0,0xff,0xee,0x33,0xc0
46,0x8e,0xc0,0x33,0xf6,0xb9,0xff,0x7f,0x83,0x3e,0xff,0x34,0x00,0x74,0x08,0x8d,0x3e
47,0x30,0x61,0xd1,0xef,0x2b,0xcf,0x26,0x8b,0x1c,0x26,0xc7,0x04,0xff,0xff,0x26,0x83
48,0x3c,0xff,0x75,0x17,0x26,0xc7,0x04,0x00,0x00,0x26,0x83,0x3c,0x00,0x75,0x0c,0x26
49,0x89,0x1c,0x46,0x46,0xe2,0xe0,0xb8,0x00,0x00,0xeb,0x03,0xb8,0x24,0x00,0xa3,0xf7
50,0x34,0xc3,0xfa,0xb4,0xd7,0x9e,0x73,0x3a,0x75,0x38,0x79,0x36,0x7b,0x34,0x9f,0xb1
51,0x05,0xd2,0xec,0x73,0x2d,0xb0,0x40,0xd0,0xe0,0x71,0x27,0x79,0x25,0xd0,0xe0,0x73
52,0x21,0x7b,0x1f,0x32,0xc0,0x75,0x1b,0x32,0xe4,0x9e,0x72,0x16,0x74,0x14,0x78,0x12
53,0x7a,0x10,0x9f,0xd2,0xec,0x72,0x0b,0xd0,0xe4,0x70,0x07,0x75,0x05,0xb8,0x00,0x00
54,0xeb,0x03,0xb8,0x26,0x00,0xa3,0xf7,0x34,0xc3,0xfa,0xba,0x5a,0x00,0x33,0xc0,0xef
55,0xef,0xef,0xef,0xb0,0x00,0xe6,0x56,0xb0,0x00,0xe6,0x54,0xba,0x52,0x00,0xb8,0x01
56,0x01,0xef,0xe8,0xca,0x00,0x3c,0x01,0x75,0x7f,0xe8,0x83,0x00,0xba,0x52,0x00,0xb8
57,0x02,0x02,0xef,0xe8,0xb9,0x00,0x3c,0x02,0x75,0x6e,0xe8,0x7a,0x00,0xba,0x52,0x00
58,0xb8,0x04,0x04,0xef,0xe8,0xa8,0x00,0x3c,0x04,0x75,0x5d,0xe8,0x71,0x00,0xba,0x52
59,0x00,0xb8,0x08,0x08,0xef,0xe8,0x97,0x00,0x3c,0x08,0x75,0x4c,0xe8,0x68,0x00,0xba
60,0x52,0x00,0xb8,0x10,0x10,0xef,0xe8,0x86,0x00,0x3c,0x10,0x75,0x3b,0xe8,0x5f,0x00
61,0xba,0x52,0x00,0xb8,0x20,0x20,0xef,0xe8,0x75,0x00,0x3c,0x20,0x75,0x2a,0xe8,0x56
62,0x00,0xba,0x52,0x00,0xb8,0x40,0x40,0xef,0xe8,0x64,0x00,0x3c,0x40,0x75,0x19,0xe8
63,0x4d,0x00,0xba,0x52,0x00,0xb8,0x80,0x80,0xef,0xe8,0x53,0x00,0x3c,0x80,0x75,0x08
64,0xe8,0x44,0x00,0xb8,0x00,0x00,0xeb,0x03,0xb8,0x28,0x00,0xa3,0xf7,0x34,0xc3,0xba
65,0x5a,0x00,0xb8,0x00,0x80,0xef,0xc3,0xba,0x5a,0x00,0xb8,0x01,0x80,0xef,0xc3,0xba
66,0x5a,0x00,0xb8,0x02,0x80,0xef,0xc3,0xba,0x5a,0x00,0xb8,0x03,0x80,0xef,0xc3,0xba
67,0x5a,0x00,0xb8,0x04,0x80,0xef,0xc3,0xba,0x5a,0x00,0xb8,0x05,0x80,0xef,0xc3,0xba
68,0x5a,0x00,0xb8,0x06,0x80,0xef,0xc3,0xba,0x5a,0x00,0xb8,0x07,0x80,0xef,0xc3,0xb9
69,0xff,0xff,0xe4,0x58,0xe4,0x54,0x3c,0x00,0x75,0x03,0x49,0x75,0xf7,0xc3,0xfa,0x32
70,0xc0,0xe6,0x56,0xe4,0x56,0x3c,0x00,0x74,0x03,0xe9,0x82,0x00,0xb0,0xff,0xe6,0x56
71,0xe4,0x56,0x3c,0xff,0x75,0x78,0xba,0x52,0x00,0xb8,0xff,0xff,0xef,0xed,0x3c,0xff
72,0x75,0x6c,0xb8,0x00,0xff,0xef,0xed,0x3c,0x00,0x75,0x63,0xb0,0xff,0xe6,0x54,0xe4
73,0x54,0x3c,0xff,0x75,0x59,0x32,0xc0,0xe6,0x54,0xe4,0x54,0x3c,0x00,0x75,0x4f,0xb0
74,0x0f,0xe6,0x50,0xe4,0x50,0x24,0x0f,0x3c,0x0f,0x75,0x43,0xb0,0x00,0xe6,0x50,0xe4
75,0x50,0x24,0x0f,0x3c,0x00,0x75,0x37,0x8c,0xc8,0x8e,0xc0,0xbe,0x70,0x00,0x26,0x8b
76,0x14,0x26,0x8b,0x5c,0x02,0xb8,0x00,0x00,0xef,0xed,0x23,0xc3,0x3d,0x00,0x00,0x75
77,0x1d,0xb8,0xff,0xff,0x23,0xc3,0xef,0x8b,0xc8,0xed,0x23,0xc3,0x3b,0xc1,0x75,0x0e
78,0x83,0xc6,0x04,0x26,0x83,0x3c,0xff,0x75,0xd5,0xb8,0x00,0x00,0xeb,0x03,0xb8,0x2a
79,0x00,0xa3,0xf7,0x34,0xc3,0xfa,0x33,0xc0,0xbf,0x00,0x20,0xb9,0x17,0x00,0xf3,0xab
80,0xbf,0x00,0x30,0xb9,0x17,0x00,0xf3,0xab,0xbf,0x00,0x22,0xb9,0x40,0x00,0xf3,0xab
81,0xbf,0x00,0x32,0xb9,0x40,0x00,0xf3,0xab,0xfc,0x1e,0x8c,0xc8,0x8e,0xd8,0x33,0xc0
82,0x8e,0xc0,0xbe,0x92,0x00,0xbf,0x00,0x20,0xb9,0x17,0x00,0xf3,0xa4,0xbe,0xa9,0x00
83,0xbf,0x00,0x22,0xb9,0x40,0x00,0xf3,0xa4,0x1f,0xc7,0x06,0xfb,0x34,0x64,0x00,0xba
84,0x08,0x00,0xb8,0x0f,0x00,0xef,0xe8,0x82,0x01,0xe8,0x9b,0x01,0x72,0x0d,0xc7,0x06
85,0xf7,0x34,0x2c,0x00,0xc7,0x06,0xf9,0x34,0x04,0x00,0xc3,0xba,0x0a,0x00,0x33,0xc0
86,0xef,0xe8,0x98,0x01,0xe8,0xb5,0x01,0xb8,0x17,0x00,0xba,0x9c,0x00,0xef,0xb8,0x00
87,0x10,0xba,0x9a,0x00,0xef,0xb8,0x17,0x00,0xa9,0x01,0x00,0x74,0x01,0x40,0xba,0x8c
88,0x00,0xef,0xb8,0x00,0x18,0xba,0x86,0x00,0xef,0xb8,0x0c,0x00,0xba,0x82,0x00,0xef
89,0xba,0x02,0x00,0xed,0x25,0xf9,0xff,0x0d,0x02,0x00,0xef,0xba,0x06,0x00,0x33,0xc0
90,0xef,0xba,0x04,0x00,0xb8,0x60,0x00,0xef,0xba,0x00,0x00,0xb8,0x18,0x00,0xef,0xba
91,0x80,0x00,0xb9,0xff,0xff,0xed,0xa9,0x01,0x00,0x75,0x04,0xe2,0xf8,0xeb,0x3e,0xba
92,0x0a,0x00,0xed,0xa9,0x00,0x40,0x74,0x35,0xa9,0x00,0x20,0x74,0x30,0x33,0xc0,0xef
93,0x51,0xb9,0xc8,0x00,0xe2,0xfe,0x59,0x1e,0x06,0x1f,0x26,0x8b,0x0e,0x02,0x30,0x83
94,0xf9,0x17,0x75,0x18,0x49,0x49,0xbe,0x02,0x20,0xbf,0x06,0x30,0xf3,0xa6,0x1f,0x23
95,0xc9,0x75,0x0a,0xff,0x0e,0xfb,0x34,0x74,0x12,0xe9,0x4d,0xff,0x1f,0xb8,0x2c,0x00
96,0xbb,0x00,0x00,0xa3,0xf7,0x34,0x89,0x1e,0xf9,0x34,0xc3,0xc7,0x06,0xfb,0x34,0x64
97,0x00,0xe8,0xd3,0x00,0x72,0x0d,0xc7,0x06,0xf7,0x34,0x2c,0x00,0xc7,0x06,0xf9,0x34
98,0x04,0x00,0xc3,0xe8,0xd6,0x00,0xe8,0xf3,0x00,0xb8,0x03,0x00,0xba,0x82,0x00,0xef
99,0xb8,0x40,0x80,0xba,0x98,0x00,0xef,0xb8,0x00,0x11,0xba,0x96,0x00,0xef,0xb8,0x40
100,0x00,0xa9,0x01,0x00,0x74,0x01,0x40,0xba,0x92,0x00,0xef,0xb8,0x00,0x19,0xba,0x8e
101,0x00,0xef,0xba,0x02,0x00,0xed,0x25,0xf9,0xff,0x0d,0x06,0x00,0xef,0xba,0x06,0x00
102,0x33,0xc0,0xef,0xba,0x00,0x00,0xb8,0x18,0x00,0xef,0xba,0x80,0x00,0xb9,0xff,0xff
103,0xed,0xa9,0x20,0x00,0x75,0x04,0xe2,0xf8,0xeb,0x43,0xba,0x0a,0x00,0xed,0xa9,0x00
104,0x40,0x74,0x3a,0xa9,0x00,0x20,0x74,0x35,0x33,0xc0,0xef,0x51,0xb9,0xc8,0x00,0xe2
105,0xfe,0x59,0x1e,0x06,0x1f,0x26,0x8b,0x0e,0x02,0x32,0x83,0xf9,0x40,0x75,0x1d,0x49
106,0x49,0xbe,0x02,0x22,0xbf,0x06,0x32,0xf3,0xa6,0x1f,0x23,0xc9,0x75,0x0f,0xff,0x0e
107,0xfb,0x34,0x74,0x03,0xe9,0x5a,0xff,0xb8,0x00,0x00,0xeb,0x0b,0x1f,0xb8,0x2c,0x00
108,0xbb,0x02,0x00,0x89,0x1e,0xf9,0x34,0xa3,0xf7,0x34,0xc3,0xba,0x02,0x00,0xb8,0x00
109,0x9c,0xef,0xba,0x00,0x00,0xb8,0x00,0x84,0xef,0x33,0xc0,0xef,0xba,0x0a,0x00,0xef
110,0xba,0x0e,0x00,0x33,0xc0,0xef,0xc3,0xba,0x0a,0x00,0xb9,0xff,0xff,0xed,0x25,0x00
111,0x60,0x3d,0x00,0x60,0x74,0x04,0xe2,0xf5,0xf8,0xc3,0xf9,0xc3,0xb0,0x00,0xe6,0x56
112,0xb8,0x00,0xff,0xba,0x52,0x00,0xef,0xb9,0xff,0xff,0xba,0x58,0x00,0xed,0x25,0xef
113,0x00,0x74,0x08,0xba,0x5a,0x00,0x33,0xc0,0xef,0xe2,0xef,0xc3,0xba,0x80,0x00,0xed
114,0xba,0x84,0x00,0xef,0xba,0x80,0x00,0xed,0xc3,0x00,0x00,0x00,0x00,0x00,0x00,0x00
115,0xc6,0x06,0xec,0x34,0x15,0x33,0xc0,0x8e,0xd8,0x8e,0xc0,0x1e,0x8c,0xc8,0xbe,0x40
116,0x54,0xbf,0x60,0xfe,0x8e,0xd8,0xb9,0x10,0x00,0xf3,0xa4,0x1f,0xc7,0x06,0x80,0x36
117,0x10,0x35,0xc7,0x06,0x8c,0x36,0x30,0x35,0x8d,0x06,0x38,0x35,0xa3,0x30,0x35,0xa3
118,0x32,0x35,0x05,0x33,0x01,0xa3,0x34,0x35,0xc7,0x06,0x36,0x35,0x50,0x01,0xc7,0x06
119,0x84,0x36,0x80,0xfe,0xc7,0x06,0x88,0x36,0xc0,0xfe,0xc6,0x06,0xc2,0xfe,0xff,0xc6
120,0x06,0x93,0x36,0x80,0xc6,0x06,0x92,0x36,0x00,0xc6,0x06,0x80,0xfe,0x80,0xc7,0x06
121,0x82,0xfe,0x54,0x50,0xc7,0x06,0x84,0xfe,0x2b,0x4d,0xe5,0xce,0xa9,0x02,0x00,0x75
122,0x08,0xc6,0x06,0x81,0xfe,0x23,0xe9,0x05,0x00,0xc6,0x06,0x81,0xfe,0x22,0xa1,0xf7
123,0x34,0xa3,0x86,0xfe,0xb8,0x48,0x34,0x86,0xe0,0xa3,0x88,0xfe,0x8d,0x06,0x4e,0x34
124,0x86,0xe0,0xa3,0x8a,0xfe,0xb8,0x58,0x34,0x86,0xe0,0xa3,0x8c,0xfe,0xb8,0x9c,0x34
125,0x86,0xe0,0xa3,0x8e,0xfe,0x8d,0x06,0x20,0x03,0x86,0xe0,0xa3,0x90,0xfe,0x33,0xc0
126,0xba,0x72,0x00,0xef,0x33,0xc0,0xba,0x74,0x00,0xef,0xba,0x76,0x00,0xef,0xb8,0x80
127,0xfe,0x86,0xe0,0xba,0x72,0x00,0xef,0xe8,0xbf,0x07,0xba,0x0c,0x01,0xb8,0x40,0x40
128,0xef,0xed,0xba,0x6a,0x00,0xb8,0x03,0x00,0xc1,0xe0,0x08,0x0d,0x03,0x00,0xef,0xb9
129,0x0a,0x00,0xe8,0x94,0x00,0xba,0x6a,0x00,0xb8,0x03,0x00,0xc1,0xe0,0x08,0xef,0xa1
130,0x32,0x34,0xa3,0xa2,0x33,0xc7,0x06,0xa6,0x33,0x04,0x00,0x8d,0x06,0xa0,0x33,0xc1
131,0xe8,0x04,0xcd,0x39,0xc7,0x06,0x90,0x36,0xff,0xff,0xe9,0xe3,0x00,0x63,0x0d,0x66
132,0x0d,0x66,0x0d,0x8a,0x0d,0xe6,0x0e,0x75,0x12,0x2e,0x0f,0x03,0x0f,0x50,0x0f,0x60
133,0x0d,0x60,0x0d,0x60,0x0d,0xed,0x0f,0xe9,0x12,0x60,0x0d,0x60,0x0d,0x60,0x0d,0x60
134,0x0d,0x60,0x0d,0x22,0x10,0x60,0x0d,0x60,0x0d,0x60,0x0d,0x60,0x0d,0xfe,0x10,0x60
135,0x0d,0x60,0x0d,0x60,0x0d,0x60,0x0d,0x60,0x0d,0x60,0x0d,0xaf,0x0f,0x32,0x10,0x37
136,0x0d,0x60,0x0d,0x60,0x0d,0x60,0x0d,0x60,0x0d,0x60,0x0d,0x60,0x0d,0x60,0x0d,0x60
137,0x0d,0x60,0x0d,0x60,0x0d,0x60,0x0d,0x60,0x0d,0x60,0x0d,0x60,0x0d,0x60,0x0d,0x60
138,0x0d,0x64,0x0e,0x00,0x0f,0x95,0x09,0x60,0x0a,0x49,0xbb,0xff,0xff,0xba,0x6a,0x00
139,0xed,0xa9,0x00,0x20,0x74,0x38,0x80,0x3e,0x80,0xfe,0x12,0x75,0x31,0xe8,0x4a,0x00
140,0xa1,0x32,0x34,0xa3,0xa2,0x33,0xc7,0x06,0xa6,0x33,0x04,0x00,0x8d,0x06,0xa0,0x33
141,0xc1,0xe8,0x04,0xcd,0x39,0xe8,0x22,0x00,0xc7,0x06,0xf3,0x34,0x46,0x00,0xc7,0x06
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1581} ;
diff --git a/drivers/net/tokenring/Kconfig b/drivers/net/tokenring/Kconfig
new file mode 100644
index 000000000000..23d0fa4bbceb
--- /dev/null
+++ b/drivers/net/tokenring/Kconfig
@@ -0,0 +1,186 @@
1#
2# Token Ring driver configuration
3#
4
5menu "Token Ring devices"
6 depends on NETDEVICES
7
8# So far, we only have PCI, ISA, and MCA token ring devices
9config TR
10 bool "Token Ring driver support"
11 depends on (PCI || ISA || MCA || CCW)
12 select LLC
13 help
14 Token Ring is IBM's way of communication on a local network; the
15 rest of the world uses Ethernet. To participate on a Token Ring
16 network, you need a special Token ring network card. If you are
17 connected to such a Token Ring network and want to use your Token
18 Ring card under Linux, say Y here and to the driver for your
19 particular card below and read the Token-Ring mini-HOWTO, available
20 from <http://www.tldp.org/docs.html#howto>. Most people can
21 say N here.
22
23config IBMTR
24 tristate "IBM Tropic chipset based adapter support"
25 depends on TR && (ISA || MCA)
26 ---help---
27 This is support for all IBM Token Ring cards that don't use DMA. If
28 you have such a beast, say Y and read the Token-Ring mini-HOWTO,
29 available from <http://www.tldp.org/docs.html#howto>.
30
31 Warning: this driver will almost definitely fail if more than one
32 active Token Ring card is present.
33
34 To compile this driver as a module, choose M here: the module will be
35 called ibmtr.
36
37config IBMOL
38 tristate "IBM Olympic chipset PCI adapter support"
39 depends on TR && PCI
40 ---help---
41 This is support for all non-Lanstreamer IBM PCI Token Ring Cards.
42 Specifically this is all IBM PCI, PCI Wake On Lan, PCI II, PCI II
43 Wake On Lan, and PCI 100/16/4 adapters.
44
45 If you have such an adapter, say Y and read the Token-Ring
46 mini-HOWTO, available from <http://www.tldp.org/docs.html#howto>.
47
48 To compile this driver as a module, choose M here: the module will be
49 called olympic.
50
51 Also read <file:Documentation/networking/olympic.txt> or check the
52 Linux Token Ring Project site for the latest information at
53 <http://www.linuxtr.net/>.
54
55config IBMLS
56 tristate "IBM Lanstreamer chipset PCI adapter support"
57 depends on TR && PCI && !64BIT
58 help
59 This is support for IBM Lanstreamer PCI Token Ring Cards.
60
61 If you have such an adapter, say Y and read the Token-Ring
62 mini-HOWTO, available from <http://www.tldp.org/docs.html#howto>.
63
64 To compile this driver as a module, choose M here: the module will be
65 called lanstreamer.
66
67config 3C359
68 tristate "3Com 3C359 Token Link Velocity XL adapter support"
69 depends on TR && PCI
70 ---help---
71 This is support for the 3Com PCI Velocity XL cards, specifically
72 the 3Com 3C359, please note this is not for the 3C339 cards, you
73 should use the tms380 driver instead.
74
75 If you have such an adapter, say Y and read the Token-Ring
76 mini-HOWTO, available from <http://www.tldp.org/docs.html#howto>.
77
78 To compile this driver as a module, choose M here: the module will be
79 called 3c359.
80
81 Also read the file <file:Documentation/networking/3c359.txt> or check the
82 Linux Token Ring Project site for the latest information at
83 <http://www.linuxtr.net>
84
85config TMS380TR
86 tristate "Generic TMS380 Token Ring ISA/PCI adapter support"
87 depends on TR && (PCI || ISA)
88 select FW_LOADER
89 ---help---
90 This driver provides generic support for token ring adapters
91 based on the Texas Instruments TMS380 series chipsets. This
92 includes the SysKonnect TR4/16(+) ISA (SK-4190), SysKonnect
93 TR4/16(+) PCI (SK-4590), SysKonnect TR4/16 PCI (SK-4591),
94 Compaq 4/16 PCI, Thomas-Conrad TC4048 4/16 PCI, and several
95 Madge adapters. If you say Y here, you will be asked to select
96 which cards to support below. If you're using modules, each
97 class of card will be supported by a separate module.
98
99 If you have such an adapter and would like to use it, say Y and
100 read the Token-Ring mini-HOWTO, available from
101 <http://www.tldp.org/docs.html#howto>.
102
103 Also read the file <file:Documentation/networking/tms380tr.txt> or
104 check <http://www.auk.cx/tms380tr/>.
105
106 To compile this driver as a module, choose M here: the module will be
107 called tms380tr.
108
109config TMSPCI
110 tristate "Generic TMS380 PCI support"
111 depends on TR && TMS380TR && PCI
112 ---help---
113 This tms380 module supports generic TMS380-based PCI cards.
114
115 These cards are known to work:
116 - Compaq 4/16 TR PCI
117 - SysKonnect TR4/16 PCI (SK-4590/SK-4591)
118 - Thomas-Conrad TC4048 PCI 4/16
119 - 3Com Token Link Velocity
120
121 To compile this driver as a module, choose M here: the module will be
122 called tmspci.
123
124config SKISA
125 tristate "SysKonnect TR4/16 ISA support"
126 depends on TR && TMS380TR && ISA
127 help
128 This tms380 module supports SysKonnect TR4/16 ISA cards.
129
130 These cards are known to work:
131 - SysKonnect TR4/16 ISA (SK-4190)
132
133 To compile this driver as a module, choose M here: the module will be
134 called skisa.
135
136config PROTEON
137 tristate "Proteon ISA support"
138 depends on TR && TMS380TR && ISA
139 help
140 This tms380 module supports Proteon ISA cards.
141
142 These cards are known to work:
143 - Proteon 1392
144 - Proteon 1392 plus
145
146 To compile this driver as a module, choose M here: the module will be
147 called proteon.
148
149config ABYSS
150 tristate "Madge Smart 16/4 PCI Mk2 support"
151 depends on TR && TMS380TR && PCI
152 help
153 This tms380 module supports the Madge Smart 16/4 PCI Mk2
154 cards (51-02).
155
156 To compile this driver as a module, choose M here: the module will be
157 called abyss.
158
159config MADGEMC
160 tristate "Madge Smart 16/4 Ringnode MicroChannel"
161 depends on TR && TMS380TR && MCA_LEGACY
162 help
163 This tms380 module supports the Madge Smart 16/4 MC16 and MC32
164 MicroChannel adapters.
165
166 To compile this driver as a module, choose M here: the module will be
167 called madgemc.
168
169config SMCTR
170 tristate "SMC ISA/MCA adapter support"
171 depends on TR && (ISA || MCA_LEGACY) && (BROKEN || !64BIT)
172 ---help---
173 This is support for the ISA and MCA SMC Token Ring cards,
174 specifically SMC TokenCard Elite (8115T) and SMC TokenCard Elite/A
175 (8115T/A) adapters.
176
177 If you have such an adapter and would like to use it, say Y or M and
178 read the Token-Ring mini-HOWTO, available from
179 <http://www.tldp.org/docs.html#howto> and the file
180 <file:Documentation/networking/smctr.txt>.
181
182 To compile this driver as a module, choose M here: the module will be
183 called smctr.
184
185endmenu
186
diff --git a/drivers/net/tokenring/Makefile b/drivers/net/tokenring/Makefile
new file mode 100644
index 000000000000..c88b0a5e5380
--- /dev/null
+++ b/drivers/net/tokenring/Makefile
@@ -0,0 +1,15 @@
1#
2# Makefile for drivers/net/tokenring
3#
4
5obj-$(CONFIG_IBMTR) += ibmtr.o
6obj-$(CONFIG_IBMOL) += olympic.o
7obj-$(CONFIG_IBMLS) += lanstreamer.o
8obj-$(CONFIG_TMS380TR) += tms380tr.o
9obj-$(CONFIG_ABYSS) += abyss.o
10obj-$(CONFIG_MADGEMC) += madgemc.o
11obj-$(CONFIG_PROTEON) += proteon.o
12obj-$(CONFIG_TMSPCI) += tmspci.o
13obj-$(CONFIG_SKISA) += skisa.o
14obj-$(CONFIG_SMCTR) += smctr.o
15obj-$(CONFIG_3C359) += 3c359.o
diff --git a/drivers/net/tokenring/abyss.c b/drivers/net/tokenring/abyss.c
new file mode 100644
index 000000000000..bd4a2bccf867
--- /dev/null
+++ b/drivers/net/tokenring/abyss.c
@@ -0,0 +1,481 @@
1/*
2 * abyss.c: Network driver for the Madge Smart 16/4 PCI Mk2 token ring card.
3 *
4 * Written 1999-2000 by Adam Fritzler
5 *
6 * This software may be used and distributed according to the terms
7 * of the GNU General Public License, incorporated herein by reference.
8 *
9 * This driver module supports the following cards:
10 * - Madge Smart 16/4 PCI Mk2
11 *
12 * Maintainer(s):
13 * AF Adam Fritzler mid@auk.cx
14 *
15 * Modification History:
16 * 30-Dec-99 AF Split off from the tms380tr driver.
17 * 22-Jan-00 AF Updated to use indirect read/writes
18 * 23-Nov-00 JG New PCI API, cleanups
19 *
20 *
21 * TODO:
22 * 1. See if we can use MMIO instead of inb/outb/inw/outw
23 * 2. Add support for Mk1 (has AT24 attached to the PCI
24 * config registers)
25 *
26 */
27
28#include <linux/module.h>
29#include <linux/kernel.h>
30#include <linux/errno.h>
31#include <linux/pci.h>
32#include <linux/init.h>
33#include <linux/netdevice.h>
34#include <linux/trdevice.h>
35
36#include <asm/system.h>
37#include <asm/io.h>
38#include <asm/irq.h>
39
40#include "tms380tr.h"
41#include "abyss.h" /* Madge-specific constants */
42
43static char version[] __devinitdata =
44"abyss.c: v1.02 23/11/2000 by Adam Fritzler\n";
45
46#define ABYSS_IO_EXTENT 64
47
48static struct pci_device_id abyss_pci_tbl[] = {
49 { PCI_VENDOR_ID_MADGE, PCI_DEVICE_ID_MADGE_MK2,
50 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_TOKEN_RING << 8, 0x00ffffff, },
51 { } /* Terminating entry */
52};
53MODULE_DEVICE_TABLE(pci, abyss_pci_tbl);
54
55MODULE_LICENSE("GPL");
56
57static int abyss_open(struct net_device *dev);
58static int abyss_close(struct net_device *dev);
59static void abyss_enable(struct net_device *dev);
60static int abyss_chipset_init(struct net_device *dev);
61static void abyss_read_eeprom(struct net_device *dev);
62static unsigned short abyss_setnselout_pins(struct net_device *dev);
63
64static void at24_writedatabyte(unsigned long regaddr, unsigned char byte);
65static int at24_sendfullcmd(unsigned long regaddr, unsigned char cmd, unsigned char addr);
66static int at24_sendcmd(unsigned long regaddr, unsigned char cmd);
67static unsigned char at24_readdatabit(unsigned long regaddr);
68static unsigned char at24_readdatabyte(unsigned long regaddr);
69static int at24_waitforack(unsigned long regaddr);
70static int at24_waitfornack(unsigned long regaddr);
71static void at24_setlines(unsigned long regaddr, unsigned char clock, unsigned char data);
72static void at24_start(unsigned long regaddr);
73static unsigned char at24_readb(unsigned long regaddr, unsigned char addr);
74
75static unsigned short abyss_sifreadb(struct net_device *dev, unsigned short reg)
76{
77 return inb(dev->base_addr + reg);
78}
79
80static unsigned short abyss_sifreadw(struct net_device *dev, unsigned short reg)
81{
82 return inw(dev->base_addr + reg);
83}
84
85static void abyss_sifwriteb(struct net_device *dev, unsigned short val, unsigned short reg)
86{
87 outb(val, dev->base_addr + reg);
88}
89
90static void abyss_sifwritew(struct net_device *dev, unsigned short val, unsigned short reg)
91{
92 outw(val, dev->base_addr + reg);
93}
94
95static int __devinit abyss_attach(struct pci_dev *pdev, const struct pci_device_id *ent)
96{
97 static int versionprinted;
98 struct net_device *dev;
99 struct net_local *tp;
100 int i, ret, pci_irq_line;
101 unsigned long pci_ioaddr;
102
103 if (versionprinted++ == 0)
104 printk("%s", version);
105
106 if (pci_enable_device(pdev))
107 return -EIO;
108
109 /* Remove I/O space marker in bit 0. */
110 pci_irq_line = pdev->irq;
111 pci_ioaddr = pci_resource_start (pdev, 0);
112
113 /* At this point we have found a valid card. */
114
115 dev = alloc_trdev(sizeof(struct net_local));
116 if (!dev)
117 return -ENOMEM;
118
119 SET_MODULE_OWNER(dev);
120
121 if (!request_region(pci_ioaddr, ABYSS_IO_EXTENT, dev->name)) {
122 ret = -EBUSY;
123 goto err_out_trdev;
124 }
125
126 ret = request_irq(pdev->irq, tms380tr_interrupt, SA_SHIRQ,
127 dev->name, dev);
128 if (ret)
129 goto err_out_region;
130
131 dev->base_addr = pci_ioaddr;
132 dev->irq = pci_irq_line;
133
134 printk("%s: Madge Smart 16/4 PCI Mk2 (Abyss)\n", dev->name);
135 printk("%s: IO: %#4lx IRQ: %d\n",
136 dev->name, pci_ioaddr, dev->irq);
137 /*
138 * The TMS SIF registers lay 0x10 above the card base address.
139 */
140 dev->base_addr += 0x10;
141
142 ret = tmsdev_init(dev, PCI_MAX_ADDRESS, pdev);
143 if (ret) {
144 printk("%s: unable to get memory for dev->priv.\n",
145 dev->name);
146 goto err_out_irq;
147 }
148
149 abyss_read_eeprom(dev);
150
151 printk("%s: Ring Station Address: ", dev->name);
152 printk("%2.2x", dev->dev_addr[0]);
153 for (i = 1; i < 6; i++)
154 printk(":%2.2x", dev->dev_addr[i]);
155 printk("\n");
156
157 tp = netdev_priv(dev);
158 tp->setnselout = abyss_setnselout_pins;
159 tp->sifreadb = abyss_sifreadb;
160 tp->sifreadw = abyss_sifreadw;
161 tp->sifwriteb = abyss_sifwriteb;
162 tp->sifwritew = abyss_sifwritew;
163
164 memcpy(tp->ProductID, "Madge PCI 16/4 Mk2", PROD_ID_SIZE + 1);
165
166 dev->open = abyss_open;
167 dev->stop = abyss_close;
168
169 pci_set_drvdata(pdev, dev);
170 SET_NETDEV_DEV(dev, &pdev->dev);
171
172 ret = register_netdev(dev);
173 if (ret)
174 goto err_out_tmsdev;
175 return 0;
176
177err_out_tmsdev:
178 pci_set_drvdata(pdev, NULL);
179 tmsdev_term(dev);
180err_out_irq:
181 free_irq(pdev->irq, dev);
182err_out_region:
183 release_region(pci_ioaddr, ABYSS_IO_EXTENT);
184err_out_trdev:
185 free_netdev(dev);
186 return ret;
187}
188
189static unsigned short abyss_setnselout_pins(struct net_device *dev)
190{
191 unsigned short val = 0;
192 struct net_local *tp = netdev_priv(dev);
193
194 if(tp->DataRate == SPEED_4)
195 val |= 0x01; /* Set 4Mbps */
196 else
197 val |= 0x00; /* Set 16Mbps */
198
199 return val;
200}
201
202/*
203 * The following Madge boards should use this code:
204 * - Smart 16/4 PCI Mk2 (Abyss)
205 * - Smart 16/4 PCI Mk1 (PCI T)
206 * - Smart 16/4 Client Plus PnP (Big Apple)
207 * - Smart 16/4 Cardbus Mk2
208 *
209 * These access an Atmel AT24 SEEPROM using their glue chip registers.
210 *
211 */
212static void at24_writedatabyte(unsigned long regaddr, unsigned char byte)
213{
214 int i;
215
216 for (i = 0; i < 8; i++) {
217 at24_setlines(regaddr, 0, (byte >> (7-i))&0x01);
218 at24_setlines(regaddr, 1, (byte >> (7-i))&0x01);
219 at24_setlines(regaddr, 0, (byte >> (7-i))&0x01);
220 }
221}
222
223static int at24_sendfullcmd(unsigned long regaddr, unsigned char cmd, unsigned char addr)
224{
225 if (at24_sendcmd(regaddr, cmd)) {
226 at24_writedatabyte(regaddr, addr);
227 return at24_waitforack(regaddr);
228 }
229 return 0;
230}
231
232static int at24_sendcmd(unsigned long regaddr, unsigned char cmd)
233{
234 int i;
235
236 for (i = 0; i < 10; i++) {
237 at24_start(regaddr);
238 at24_writedatabyte(regaddr, cmd);
239 if (at24_waitforack(regaddr))
240 return 1;
241 }
242 return 0;
243}
244
245static unsigned char at24_readdatabit(unsigned long regaddr)
246{
247 unsigned char val;
248
249 at24_setlines(regaddr, 0, 1);
250 at24_setlines(regaddr, 1, 1);
251 val = (inb(regaddr) & AT24_DATA)?1:0;
252 at24_setlines(regaddr, 1, 1);
253 at24_setlines(regaddr, 0, 1);
254 return val;
255}
256
257static unsigned char at24_readdatabyte(unsigned long regaddr)
258{
259 unsigned char data = 0;
260 int i;
261
262 for (i = 0; i < 8; i++) {
263 data <<= 1;
264 data |= at24_readdatabit(regaddr);
265 }
266
267 return data;
268}
269
270static int at24_waitforack(unsigned long regaddr)
271{
272 int i;
273
274 for (i = 0; i < 10; i++) {
275 if ((at24_readdatabit(regaddr) & 0x01) == 0x00)
276 return 1;
277 }
278 return 0;
279}
280
281static int at24_waitfornack(unsigned long regaddr)
282{
283 int i;
284 for (i = 0; i < 10; i++) {
285 if ((at24_readdatabit(regaddr) & 0x01) == 0x01)
286 return 1;
287 }
288 return 0;
289}
290
291static void at24_setlines(unsigned long regaddr, unsigned char clock, unsigned char data)
292{
293 unsigned char val = AT24_ENABLE;
294 if (clock)
295 val |= AT24_CLOCK;
296 if (data)
297 val |= AT24_DATA;
298
299 outb(val, regaddr);
300 tms380tr_wait(20); /* Very necessary. */
301}
302
303static void at24_start(unsigned long regaddr)
304{
305 at24_setlines(regaddr, 0, 1);
306 at24_setlines(regaddr, 1, 1);
307 at24_setlines(regaddr, 1, 0);
308 at24_setlines(regaddr, 0, 1);
309}
310
311static unsigned char at24_readb(unsigned long regaddr, unsigned char addr)
312{
313 unsigned char data = 0xff;
314
315 if (at24_sendfullcmd(regaddr, AT24_WRITE, addr)) {
316 if (at24_sendcmd(regaddr, AT24_READ)) {
317 data = at24_readdatabyte(regaddr);
318 if (!at24_waitfornack(regaddr))
319 data = 0xff;
320 }
321 }
322 return data;
323}
324
325
326/*
327 * Enable basic functions of the Madge chipset needed
328 * for initialization.
329 */
330static void abyss_enable(struct net_device *dev)
331{
332 unsigned char reset_reg;
333 unsigned long ioaddr;
334
335 ioaddr = dev->base_addr;
336 reset_reg = inb(ioaddr + PCIBM2_RESET_REG);
337 reset_reg |= PCIBM2_RESET_REG_CHIP_NRES;
338 outb(reset_reg, ioaddr + PCIBM2_RESET_REG);
339 tms380tr_wait(100);
340}
341
342/*
343 * Enable the functions of the Madge chipset needed for
344 * full working order.
345 */
346static int abyss_chipset_init(struct net_device *dev)
347{
348 unsigned char reset_reg;
349 unsigned long ioaddr;
350
351 ioaddr = dev->base_addr;
352
353 reset_reg = inb(ioaddr + PCIBM2_RESET_REG);
354
355 reset_reg |= PCIBM2_RESET_REG_CHIP_NRES;
356 outb(reset_reg, ioaddr + PCIBM2_RESET_REG);
357
358 reset_reg &= ~(PCIBM2_RESET_REG_CHIP_NRES |
359 PCIBM2_RESET_REG_FIFO_NRES |
360 PCIBM2_RESET_REG_SIF_NRES);
361 outb(reset_reg, ioaddr + PCIBM2_RESET_REG);
362
363 tms380tr_wait(100);
364
365 reset_reg |= PCIBM2_RESET_REG_CHIP_NRES;
366 outb(reset_reg, ioaddr + PCIBM2_RESET_REG);
367
368 reset_reg |= PCIBM2_RESET_REG_SIF_NRES;
369 outb(reset_reg, ioaddr + PCIBM2_RESET_REG);
370
371 reset_reg |= PCIBM2_RESET_REG_FIFO_NRES;
372 outb(reset_reg, ioaddr + PCIBM2_RESET_REG);
373
374 outb(PCIBM2_INT_CONTROL_REG_SINTEN |
375 PCIBM2_INT_CONTROL_REG_PCI_ERR_ENABLE,
376 ioaddr + PCIBM2_INT_CONTROL_REG);
377
378 outb(30, ioaddr + PCIBM2_FIFO_THRESHOLD);
379
380 return 0;
381}
382
383static inline void abyss_chipset_close(struct net_device *dev)
384{
385 unsigned long ioaddr;
386
387 ioaddr = dev->base_addr;
388 outb(0, ioaddr + PCIBM2_RESET_REG);
389}
390
391/*
392 * Read configuration data from the AT24 SEEPROM on Madge cards.
393 *
394 */
395static void abyss_read_eeprom(struct net_device *dev)
396{
397 struct net_local *tp;
398 unsigned long ioaddr;
399 unsigned short val;
400 int i;
401
402 tp = netdev_priv(dev);
403 ioaddr = dev->base_addr;
404
405 /* Must enable glue chip first */
406 abyss_enable(dev);
407
408 val = at24_readb(ioaddr + PCIBM2_SEEPROM_REG,
409 PCIBM2_SEEPROM_RING_SPEED);
410 tp->DataRate = val?SPEED_4:SPEED_16; /* set open speed */
411 printk("%s: SEEPROM: ring speed: %dMb/sec\n", dev->name, tp->DataRate);
412
413 val = at24_readb(ioaddr + PCIBM2_SEEPROM_REG,
414 PCIBM2_SEEPROM_RAM_SIZE) * 128;
415 printk("%s: SEEPROM: adapter RAM: %dkb\n", dev->name, val);
416
417 dev->addr_len = 6;
418 for (i = 0; i < 6; i++)
419 dev->dev_addr[i] = at24_readb(ioaddr + PCIBM2_SEEPROM_REG,
420 PCIBM2_SEEPROM_BIA+i);
421}
422
423static int abyss_open(struct net_device *dev)
424{
425 abyss_chipset_init(dev);
426 tms380tr_open(dev);
427 return 0;
428}
429
430static int abyss_close(struct net_device *dev)
431{
432 tms380tr_close(dev);
433 abyss_chipset_close(dev);
434 return 0;
435}
436
437static void __devexit abyss_detach (struct pci_dev *pdev)
438{
439 struct net_device *dev = pci_get_drvdata(pdev);
440
441 if (!dev)
442 BUG();
443 unregister_netdev(dev);
444 release_region(dev->base_addr-0x10, ABYSS_IO_EXTENT);
445 free_irq(dev->irq, dev);
446 tmsdev_term(dev);
447 free_netdev(dev);
448 pci_set_drvdata(pdev, NULL);
449}
450
451static struct pci_driver abyss_driver = {
452 .name = "abyss",
453 .id_table = abyss_pci_tbl,
454 .probe = abyss_attach,
455 .remove = __devexit_p(abyss_detach),
456};
457
458static int __init abyss_init (void)
459{
460 return pci_register_driver(&abyss_driver);
461}
462
463static void __exit abyss_rmmod (void)
464{
465 pci_unregister_driver (&abyss_driver);
466}
467
468module_init(abyss_init);
469module_exit(abyss_rmmod);
470
471
472/*
473 * Local variables:
474 * compile-command: "gcc -DMODVERSIONS -DMODULE -D__KERNEL__ -Wall -Wstrict-prototypes -O6 -fomit-frame-pointer -I/usr/src/linux/drivers/net/tokenring/ -c abyss.c"
475 * alt-compile-command: "gcc -DMODULE -D__KERNEL__ -Wall -Wstrict-prototypes -O6 -fomit-frame-pointer -I/usr/src/linux/drivers/net/tokenring/ -c abyss.c"
476 * c-set-style "K&R"
477 * c-indent-level: 8
478 * c-basic-offset: 8
479 * tab-width: 8
480 * End:
481 */
diff --git a/drivers/net/tokenring/abyss.h b/drivers/net/tokenring/abyss.h
new file mode 100644
index 000000000000..0ee6e4f085b1
--- /dev/null
+++ b/drivers/net/tokenring/abyss.h
@@ -0,0 +1,58 @@
1/*
2 * abyss.h: Header for the abyss tms380tr module
3 *
4 * Authors:
5 * - Adam Fritzler <mid@auk.cx>
6 */
7
8#ifndef __LINUX_MADGETR_H
9#define __LINUX_MADGETR_H
10
11#ifdef __KERNEL__
12
13/*
14 * For Madge Smart 16/4 PCI Mk2. Since we increment the base address
15 * to get everything correct for the TMS SIF, we do these as negatives
16 * as they fall below the SIF in addressing.
17 */
18#define PCIBM2_INT_STATUS_REG ((short)-15)/* 0x01 */
19#define PCIBM2_INT_CONTROL_REG ((short)-14)/* 0x02 */
20#define PCIBM2_RESET_REG ((short)-12)/* 0x04 */
21#define PCIBM2_SEEPROM_REG ((short)-9) /* 0x07 */
22
23#define PCIBM2_INT_CONTROL_REG_SINTEN 0x02
24#define PCIBM2_INT_CONTROL_REG_PCI_ERR_ENABLE 0x80
25#define PCIBM2_INT_STATUS_REG_PCI_ERR 0x80
26
27#define PCIBM2_RESET_REG_CHIP_NRES 0x01
28#define PCIBM2_RESET_REG_FIFO_NRES 0x02
29#define PCIBM2_RESET_REG_SIF_NRES 0x04
30
31#define PCIBM2_FIFO_THRESHOLD 0x21
32#define PCIBM2_BURST_LENGTH 0x22
33
34/*
35 * Bits in PCIBM2_SEEPROM_REG.
36 */
37#define AT24_ENABLE 0x04
38#define AT24_DATA 0x02
39#define AT24_CLOCK 0x01
40
41/*
42 * AT24 Commands.
43 */
44#define AT24_WRITE 0xA0
45#define AT24_READ 0xA1
46
47/*
48 * Addresses in AT24 SEEPROM.
49 */
50#define PCIBM2_SEEPROM_BIA 0x12
51#define PCIBM2_SEEPROM_RING_SPEED 0x18
52#define PCIBM2_SEEPROM_RAM_SIZE 0x1A
53#define PCIBM2_SEEPROM_HWF1 0x1C
54#define PCIBM2_SEEPROM_HWF2 0x1E
55
56
57#endif /* __KERNEL__ */
58#endif /* __LINUX_MADGETR_H */
diff --git a/drivers/net/tokenring/ibmtr.c b/drivers/net/tokenring/ibmtr.c
new file mode 100644
index 000000000000..c098863bdd9d
--- /dev/null
+++ b/drivers/net/tokenring/ibmtr.c
@@ -0,0 +1,1987 @@
1/* ibmtr.c: A shared-memory IBM Token Ring 16/4 driver for linux
2 *
3 * Written 1993 by Mark Swanson and Peter De Schrijver.
4 * This software may be used and distributed according to the terms
5 * of the GNU General Public License, incorporated herein by reference.
6 *
7 * This device driver should work with Any IBM Token Ring Card that does
8 * not use DMA.
9 *
10 * I used Donald Becker's (becker@scyld.com) device driver work
11 * as a base for most of my initial work.
12 *
13 * Changes by Peter De Schrijver
14 * (Peter.Deschrijver@linux.cc.kuleuven.ac.be) :
15 *
16 * + changed name to ibmtr.c in anticipation of other tr boards.
17 * + changed reset code and adapter open code.
18 * + added SAP open code.
19 * + a first attempt to write interrupt, transmit and receive routines.
20 *
21 * Changes by David W. Morris (dwm@shell.portal.com) :
22 * 941003 dwm: - Restructure tok_probe for multiple adapters, devices.
23 * + Add comments, misc reorg for clarity.
24 * + Flatten interrupt handler levels.
25 *
26 * Changes by Farzad Farid (farzy@zen.via.ecp.fr)
27 * and Pascal Andre (andre@chimay.via.ecp.fr) (March 9 1995) :
28 * + multi ring support clean up.
29 * + RFC1042 compliance enhanced.
30 *
31 * Changes by Pascal Andre (andre@chimay.via.ecp.fr) (September 7 1995) :
32 * + bug correction in tr_tx
33 * + removed redundant information display
34 * + some code reworking
35 *
36 * Changes by Michel Lespinasse (walken@via.ecp.fr),
37 * Yann Doussot (doussot@via.ecp.fr) and Pascal Andre (andre@via.ecp.fr)
38 * (February 18, 1996) :
39 * + modified shared memory and mmio access port the driver to
40 * alpha platform (structure access -> readb/writeb)
41 *
42 * Changes by Steve Kipisz (bungy@ibm.net or kipisz@vnet.ibm.com)
43 * (January 18 1996):
44 * + swapped WWOR and WWCR in ibmtr.h
45 * + moved some init code from tok_probe into trdev_init. The
46 * PCMCIA code can call trdev_init to complete initializing
47 * the driver.
48 * + added -DPCMCIA to support PCMCIA
49 * + detecting PCMCIA Card Removal in interrupt handler. If
50 * ISRP is FF, then a PCMCIA card has been removed
51 * 10/2000 Burt needed a new method to avoid crashing the OS
52 *
53 * Changes by Paul Norton (pnorton@cts.com) :
54 * + restructured the READ.LOG logic to prevent the transmit SRB
55 * from being rudely overwritten before the transmit cycle is
56 * complete. (August 15 1996)
57 * + completed multiple adapter support. (November 20 1996)
58 * + implemented csum_partial_copy in tr_rx and increased receive
59 * buffer size and count. Minor fixes. (March 15, 1997)
60 *
61 * Changes by Christopher Turcksin <wabbit@rtfc.demon.co.uk>
62 * + Now compiles ok as a module again.
63 *
64 * Changes by Paul Norton (pnorton@ieee.org) :
65 * + moved the header manipulation code in tr_tx and tr_rx to
66 * net/802/tr.c. (July 12 1997)
67 * + add retry and timeout on open if cable disconnected. (May 5 1998)
68 * + lifted 2000 byte mtu limit. now depends on shared-RAM size.
69 * May 25 1998)
70 * + can't allocate 2k recv buff at 8k shared-RAM. (20 October 1998)
71 *
72 * Changes by Joel Sloan (jjs@c-me.com) :
73 * + disable verbose debug messages by default - to enable verbose
74 * debugging, edit the IBMTR_DEBUG_MESSAGES define below
75 *
76 * Changes by Mike Phillips <phillim@amtrak.com> :
77 * + Added extra #ifdef's to work with new PCMCIA Token Ring Code.
78 * The PCMCIA code now just sets up the card so it can be recognized
79 * by ibmtr_probe. Also checks allocated memory vs. on-board memory
80 * for correct figure to use.
81 *
82 * Changes by Tim Hockin (thockin@isunix.it.ilstu.edu) :
83 * + added spinlocks for SMP sanity (10 March 1999)
84 *
85 * Changes by Jochen Friedrich to enable RFC1469 Option 2 multicasting
86 * i.e. using functional address C0 00 00 04 00 00 to transmit and
87 * receive multicast packets.
88 *
89 * Changes by Mike Sullivan (based on original sram patch by Dave Grothe
90 * to support windowing into on adapter shared ram.
91 * i.e. Use LANAID to setup a PnP configuration with 16K RAM. Paging
92 * will shift this 16K window over the entire available shared RAM.
93 *
94 * Changes by Peter De Schrijver (p2@mind.be) :
95 * + fixed a problem with PCMCIA card removal
96 *
97 * Change by Mike Sullivan et al.:
98 * + added turbo card support. No need to use lanaid to configure
99 * the adapter into isa compatiblity mode.
100 *
101 * Changes by Burt Silverman to allow the computer to behave nicely when
102 * a cable is pulled or not in place, or a PCMCIA card is removed hot.
103 */
104
105/* change the define of IBMTR_DEBUG_MESSAGES to a nonzero value
106in the event that chatty debug messages are desired - jjs 12/30/98 */
107
108#define IBMTR_DEBUG_MESSAGES 0
109
110#include <linux/module.h>
111
112#ifdef PCMCIA /* required for ibmtr_cs.c to build */
113#undef MODULE /* yes, really */
114#undef ENABLE_PAGING
115#else
116#define ENABLE_PAGING 1
117#endif
118
119#define FALSE 0
120#define TRUE (!FALSE)
121
122/* changes the output format of driver initialization */
123#define TR_VERBOSE 0
124
125/* some 95 OS send many non UI frame; this allow removing the warning */
126#define TR_FILTERNONUI 1
127
128#include <linux/ioport.h>
129#include <linux/netdevice.h>
130#include <linux/ip.h>
131#include <linux/trdevice.h>
132#include <linux/ibmtr.h>
133
134#include <net/checksum.h>
135
136#include <asm/io.h>
137
138#define DPRINTK(format, args...) printk("%s: " format, dev->name , ## args)
139#define DPRINTD(format, args...) DummyCall("%s: " format, dev->name , ## args)
140
141/* version and credits */
142#ifndef PCMCIA
143static char version[] __initdata =
144 "\nibmtr.c: v1.3.57 8/ 7/94 Peter De Schrijver and Mark Swanson\n"
145 " v2.1.125 10/20/98 Paul Norton <pnorton@ieee.org>\n"
146 " v2.2.0 12/30/98 Joel Sloan <jjs@c-me.com>\n"
147 " v2.2.1 02/08/00 Mike Sullivan <sullivam@us.ibm.com>\n"
148 " v2.2.2 07/27/00 Burt Silverman <burts@us.ibm.com>\n"
149 " v2.4.0 03/01/01 Mike Sullivan <sullivan@us.ibm.com>\n";
150#endif
151
152/* this allows displaying full adapter information */
153
154char *channel_def[] __devinitdata = { "ISA", "MCA", "ISA P&P" };
155
156static char pcchannelid[] __devinitdata = {
157 0x05, 0x00, 0x04, 0x09,
158 0x04, 0x03, 0x04, 0x0f,
159 0x03, 0x06, 0x03, 0x01,
160 0x03, 0x01, 0x03, 0x00,
161 0x03, 0x09, 0x03, 0x09,
162 0x03, 0x00, 0x02, 0x00
163};
164
165static char mcchannelid[] __devinitdata = {
166 0x04, 0x0d, 0x04, 0x01,
167 0x05, 0x02, 0x05, 0x03,
168 0x03, 0x06, 0x03, 0x03,
169 0x05, 0x08, 0x03, 0x04,
170 0x03, 0x05, 0x03, 0x01,
171 0x03, 0x08, 0x02, 0x00
172};
173
174char __devinit *adapter_def(char type)
175{
176 switch (type) {
177 case 0xF: return "PC Adapter | PC Adapter II | Adapter/A";
178 case 0xE: return "16/4 Adapter | 16/4 Adapter/A (long)";
179 case 0xD: return "16/4 Adapter/A (short) | 16/4 ISA-16 Adapter";
180 case 0xC: return "Auto 16/4 Adapter";
181 default: return "adapter (unknown type)";
182 };
183};
184
185#define TRC_INIT 0x01 /* Trace initialization & PROBEs */
186#define TRC_INITV 0x02 /* verbose init trace points */
187unsigned char ibmtr_debug_trace = 0;
188
189static int ibmtr_probe(struct net_device *dev);
190static int ibmtr_probe1(struct net_device *dev, int ioaddr);
191static unsigned char get_sram_size(struct tok_info *adapt_info);
192static int trdev_init(struct net_device *dev);
193static int tok_open(struct net_device *dev);
194static int tok_init_card(struct net_device *dev);
195void tok_open_adapter(unsigned long dev_addr);
196static void open_sap(unsigned char type, struct net_device *dev);
197static void tok_set_multicast_list(struct net_device *dev);
198static int tok_send_packet(struct sk_buff *skb, struct net_device *dev);
199static int tok_close(struct net_device *dev);
200irqreturn_t tok_interrupt(int irq, void *dev_id, struct pt_regs *regs);
201static void initial_tok_int(struct net_device *dev);
202static void tr_tx(struct net_device *dev);
203static void tr_rx(struct net_device *dev);
204void ibmtr_reset_timer(struct timer_list*tmr,struct net_device *dev);
205static void tok_rerun(unsigned long dev_addr);
206void ibmtr_readlog(struct net_device *dev);
207static struct net_device_stats *tok_get_stats(struct net_device *dev);
208int ibmtr_change_mtu(struct net_device *dev, int mtu);
209static void find_turbo_adapters(int *iolist);
210
211static int ibmtr_portlist[IBMTR_MAX_ADAPTERS+1] __devinitdata = {
212 0xa20, 0xa24, 0, 0, 0
213};
214static int __devinitdata turbo_io[IBMTR_MAX_ADAPTERS] = {0};
215static int __devinitdata turbo_irq[IBMTR_MAX_ADAPTERS] = {0};
216static int __devinitdata turbo_searched = 0;
217
218#ifndef PCMCIA
219static __u32 ibmtr_mem_base __initdata = 0xd0000;
220#endif
221
222static void __devinit PrtChanID(char *pcid, short stride)
223{
224 short i, j;
225 for (i = 0, j = 0; i < 24; i++, j += stride)
226 printk("%1x", ((int) pcid[j]) & 0x0f);
227 printk("\n");
228}
229
230static void __devinit HWPrtChanID(void __iomem *pcid, short stride)
231{
232 short i, j;
233 for (i = 0, j = 0; i < 24; i++, j += stride)
234 printk("%1x", ((int) readb(pcid + j)) & 0x0f);
235 printk("\n");
236}
237
238/* We have to ioremap every checked address, because isa_readb is
239 * going away.
240 */
241
242static void __devinit find_turbo_adapters(int *iolist)
243{
244 int ram_addr;
245 int index=0;
246 void __iomem *chanid;
247 int found_turbo=0;
248 unsigned char *tchanid, ctemp;
249 int i, j;
250 unsigned long jif;
251 void __iomem *ram_mapped ;
252
253 if (turbo_searched == 1) return;
254 turbo_searched=1;
255 for (ram_addr=0xC0000; ram_addr < 0xE0000; ram_addr+=0x2000) {
256
257 __u32 intf_tbl=0;
258
259 found_turbo=1;
260 ram_mapped = ioremap((u32)ram_addr,0x1fff) ;
261 if (ram_mapped==NULL)
262 continue ;
263 chanid=(CHANNEL_ID + ram_mapped);
264 tchanid=pcchannelid;
265 ctemp=readb(chanid) & 0x0f;
266 if (ctemp != *tchanid) continue;
267 for (i=2,j=1; i<=46; i=i+2,j++) {
268 if ((readb(chanid+i) & 0x0f) != tchanid[j]){
269 found_turbo=0;
270 break;
271 }
272 }
273 if (!found_turbo) continue;
274
275 writeb(0x90, ram_mapped+0x1E01);
276 for(i=2; i<0x0f; i++) {
277 writeb(0x00, ram_mapped+0x1E01+i);
278 }
279 writeb(0x00, ram_mapped+0x1E01);
280 for(jif=jiffies+TR_BUSY_INTERVAL; time_before_eq(jiffies,jif););
281 intf_tbl=ntohs(readw(ram_mapped+ACA_OFFSET+ACA_RW+WRBR_EVEN));
282 if (intf_tbl) {
283#if IBMTR_DEBUG_MESSAGES
284 printk("ibmtr::find_turbo_adapters, Turbo found at "
285 "ram_addr %x\n",ram_addr);
286 printk("ibmtr::find_turbo_adapters, interface_table ");
287 for(i=0; i<6; i++) {
288 printk("%x:",readb(ram_addr+intf_tbl+i));
289 }
290 printk("\n");
291#endif
292 turbo_io[index]=ntohs(readw(ram_mapped+intf_tbl+4));
293 turbo_irq[index]=readb(ram_mapped+intf_tbl+3);
294 outb(0, turbo_io[index] + ADAPTRESET);
295 for(jif=jiffies+TR_RST_TIME;time_before_eq(jiffies,jif););
296 outb(0, turbo_io[index] + ADAPTRESETREL);
297 index++;
298 continue;
299 }
300#if IBMTR_DEBUG_MESSAGES
301 printk("ibmtr::find_turbo_adapters, ibmtr card found at"
302 " %x but not a Turbo model\n",ram_addr);
303#endif
304 iounmap(ram_mapped) ;
305 } /* for */
306 for(i=0; i<IBMTR_MAX_ADAPTERS; i++) {
307 if(!turbo_io[i]) break;
308 for (j=0; j<IBMTR_MAX_ADAPTERS; j++) {
309 if ( iolist[j] && iolist[j] != turbo_io[i]) continue;
310 iolist[j]=turbo_io[i];
311 break;
312 }
313 }
314}
315
316static void ibmtr_cleanup_card(struct net_device *dev)
317{
318 if (dev->base_addr) {
319 outb(0,dev->base_addr+ADAPTRESET);
320
321 schedule_timeout(TR_RST_TIME); /* wait 50ms */
322
323 outb(0,dev->base_addr+ADAPTRESETREL);
324 }
325
326#ifndef PCMCIA
327 free_irq(dev->irq, dev);
328 release_region(dev->base_addr, IBMTR_IO_EXTENT);
329
330 {
331 struct tok_info *ti = (struct tok_info *) dev->priv;
332 iounmap(ti->mmio);
333 iounmap(ti->sram_virt);
334 }
335#endif
336}
337
338int ibmtr_probe_card(struct net_device *dev)
339{
340 int err = ibmtr_probe(dev);
341 if (!err) {
342 err = register_netdev(dev);
343 if (err)
344 ibmtr_cleanup_card(dev);
345 }
346 return err;
347}
348
349/****************************************************************************
350 * ibmtr_probe(): Routine specified in the network device structure
351 * to probe for an IBM Token Ring Adapter. Routine outline:
352 * I. Interrogate hardware to determine if an adapter exists
353 * and what the speeds and feeds are
354 * II. Setup data structures to control execution based upon
355 * adapter characteristics.
356 *
357 * We expect ibmtr_probe to be called once for each device entry
358 * which references it.
359 ****************************************************************************/
360
361static int ibmtr_probe(struct net_device *dev)
362{
363 int i;
364 int base_addr = dev->base_addr;
365
366 if (base_addr && base_addr <= 0x1ff) /* Don't probe at all. */
367 return -ENXIO;
368 if (base_addr > 0x1ff) { /* Check a single specified location. */
369 if (!ibmtr_probe1(dev, base_addr)) return 0;
370 return -ENODEV;
371 }
372 find_turbo_adapters(ibmtr_portlist);
373 for (i = 0; ibmtr_portlist[i]; i++) {
374 int ioaddr = ibmtr_portlist[i];
375
376 if (!ibmtr_probe1(dev, ioaddr)) return 0;
377 }
378 return -ENODEV;
379}
380
381/*****************************************************************************/
382
383static int __devinit ibmtr_probe1(struct net_device *dev, int PIOaddr)
384{
385
386 unsigned char segment, intr=0, irq=0, i, j, cardpresent=NOTOK, temp=0;
387 void __iomem * t_mmio = NULL;
388 struct tok_info *ti = dev->priv;
389 void __iomem *cd_chanid;
390 unsigned char *tchanid, ctemp;
391#ifndef PCMCIA
392 unsigned char t_irq=0;
393 unsigned long timeout;
394 static int version_printed;
395#endif
396
397 /* Query the adapter PIO base port which will return
398 * indication of where MMIO was placed. We also have a
399 * coded interrupt number.
400 */
401 segment = inb(PIOaddr);
402 if (segment < 0x40 || segment > 0xe0) {
403 /* Out of range values so we'll assume non-existent IO device
404 * but this is not necessarily a problem, esp if a turbo
405 * adapter is being used. */
406#if IBMTR_DEBUG_MESSAGES
407 DPRINTK("ibmtr_probe1(): unhappy that inb(0x%X) == 0x%X, "
408 "Hardware Problem?\n",PIOaddr,segment);
409#endif
410 return -ENODEV;
411 }
412 /*
413 * Compute the linear base address of the MMIO area
414 * as LINUX doesn't care about segments
415 */
416 t_mmio = ioremap(((__u32) (segment & 0xfc) << 11) + 0x80000,2048);
417 if (!t_mmio) {
418 DPRINTK("Cannot remap mmiobase memory area") ;
419 return -ENODEV ;
420 }
421 intr = segment & 0x03; /* low bits is coded interrupt # */
422 if (ibmtr_debug_trace & TRC_INIT)
423 DPRINTK("PIOaddr: %4hx seg/intr: %2x mmio base: %p intr: %d\n"
424 , PIOaddr, (int) segment, t_mmio, (int) intr);
425
426 /*
427 * Now we will compare expected 'channelid' strings with
428 * what we is there to learn of ISA/MCA or not TR card
429 */
430#ifdef PCMCIA
431 iounmap(t_mmio);
432 t_mmio = ti->mmio; /*BMS to get virtual address */
433 irq = ti->irq; /*BMS to display the irq! */
434#endif
435 cd_chanid = (CHANNEL_ID + t_mmio); /* for efficiency */
436 tchanid = pcchannelid;
437 cardpresent = TR_ISA; /* try ISA */
438
439 /* Suboptimize knowing first byte different */
440 ctemp = readb(cd_chanid) & 0x0f;
441 if (ctemp != *tchanid) { /* NOT ISA card, try MCA */
442 tchanid = mcchannelid;
443 cardpresent = TR_MCA;
444 if (ctemp != *tchanid) /* Neither ISA nor MCA */
445 cardpresent = NOTOK;
446 }
447 if (cardpresent != NOTOK) {
448 /* Know presumed type, try rest of ID */
449 for (i = 2, j = 1; i <= 46; i = i + 2, j++) {
450 if( (readb(cd_chanid+i)&0x0f) == tchanid[j]) continue;
451 /* match failed, not TR card */
452 cardpresent = NOTOK;
453 break;
454 }
455 }
456 /*
457 * If we have an ISA board check for the ISA P&P version,
458 * as it has different IRQ settings
459 */
460 if (cardpresent == TR_ISA && (readb(AIPFID + t_mmio) == 0x0e))
461 cardpresent = TR_ISAPNP;
462 if (cardpresent == NOTOK) { /* "channel_id" did not match, report */
463 if (!(ibmtr_debug_trace & TRC_INIT)) {
464#ifndef PCMCIA
465 iounmap(t_mmio);
466#endif
467 return -ENODEV;
468 }
469 DPRINTK( "Channel ID string not found for PIOaddr: %4hx\n",
470 PIOaddr);
471 DPRINTK("Expected for ISA: ");
472 PrtChanID(pcchannelid, 1);
473 DPRINTK(" found: ");
474/* BMS Note that this can be misleading, when hardware is flaky, because you
475 are reading it a second time here. So with my flaky hardware, I'll see my-
476 self in this block, with the HW ID matching the ISA ID exactly! */
477 HWPrtChanID(cd_chanid, 2);
478 DPRINTK("Expected for MCA: ");
479 PrtChanID(mcchannelid, 1);
480 }
481 /* Now, setup some of the pl0 buffers for this driver.. */
482 /* If called from PCMCIA, it is already set up, so no need to
483 waste the memory, just use the existing structure */
484#ifndef PCMCIA
485 ti->mmio = t_mmio;
486 for (i = 0; i < IBMTR_MAX_ADAPTERS; i++) {
487 if (turbo_io[i] != PIOaddr)
488 continue;
489#if IBMTR_DEBUG_MESSAGES
490 printk("ibmtr::tr_probe1, setting PIOaddr %x to Turbo\n",
491 PIOaddr);
492#endif
493 ti->turbo = 1;
494 t_irq = turbo_irq[i];
495 }
496#endif /* !PCMCIA */
497 ti->readlog_pending = 0;
498 init_waitqueue_head(&ti->wait_for_reset);
499
500 /* if PCMCIA, the card can be recognized as either TR_ISA or TR_ISAPNP
501 * depending which card is inserted. */
502
503#ifndef PCMCIA
504 switch (cardpresent) {
505 case TR_ISA:
506 if (intr == 0) irq = 9; /* irq2 really is irq9 */
507 if (intr == 1) irq = 3;
508 if (intr == 2) irq = 6;
509 if (intr == 3) irq = 7;
510 ti->adapter_int_enable = PIOaddr + ADAPTINTREL;
511 break;
512 case TR_MCA:
513 if (intr == 0) irq = 9;
514 if (intr == 1) irq = 3;
515 if (intr == 2) irq = 10;
516 if (intr == 3) irq = 11;
517 ti->global_int_enable = 0;
518 ti->adapter_int_enable = 0;
519 ti->sram_phys=(__u32)(inb(PIOaddr+ADAPTRESETREL) & 0xfe) << 12;
520 break;
521 case TR_ISAPNP:
522 if (!t_irq) {
523 if (intr == 0) irq = 9;
524 if (intr == 1) irq = 3;
525 if (intr == 2) irq = 10;
526 if (intr == 3) irq = 11;
527 } else
528 irq=t_irq;
529 timeout = jiffies + TR_SPIN_INTERVAL;
530 while (!readb(ti->mmio + ACA_OFFSET + ACA_RW + RRR_EVEN)){
531 if (!time_after(jiffies, timeout)) continue;
532 DPRINTK( "Hardware timeout during initialization.\n");
533 iounmap(t_mmio);
534 kfree(ti);
535 return -ENODEV;
536 }
537 ti->sram_phys =
538 ((__u32)readb(ti->mmio+ACA_OFFSET+ACA_RW+RRR_EVEN)<<12);
539 ti->adapter_int_enable = PIOaddr + ADAPTINTREL;
540 break;
541 } /*end switch (cardpresent) */
542#endif /*not PCMCIA */
543
544 if (ibmtr_debug_trace & TRC_INIT) { /* just report int */
545 DPRINTK("irq=%d", irq);
546 printk(", sram_phys=0x%x", ti->sram_phys);
547 if(ibmtr_debug_trace&TRC_INITV){ /* full chat in verbose only */
548 DPRINTK(", ti->mmio=%p", ti->mmio);
549 printk(", segment=%02X", segment);
550 }
551 printk(".\n");
552 }
553
554 /* Get hw address of token ring card */
555 j = 0;
556 for (i = 0; i < 0x18; i = i + 2) {
557 /* technical reference states to do this */
558 temp = readb(ti->mmio + AIP + i) & 0x0f;
559 ti->hw_address[j] = temp;
560 if (j & 1)
561 dev->dev_addr[(j / 2)] =
562 ti->hw_address[j]+ (ti->hw_address[j - 1] << 4);
563 ++j;
564 }
565 /* get Adapter type: 'F' = Adapter/A, 'E' = 16/4 Adapter II,... */
566 ti->adapter_type = readb(ti->mmio + AIPADAPTYPE);
567
568 /* get Data Rate: F=4Mb, E=16Mb, D=4Mb & 16Mb ?? */
569 ti->data_rate = readb(ti->mmio + AIPDATARATE);
570
571 /* Get Early Token Release support?: F=no, E=4Mb, D=16Mb, C=4&16Mb */
572 ti->token_release = readb(ti->mmio + AIPEARLYTOKEN);
573
574 /* How much shared RAM is on adapter ? */
575 if (ti->turbo) {
576 ti->avail_shared_ram=127;
577 } else {
578 ti->avail_shared_ram = get_sram_size(ti);/*in 512 byte units */
579 }
580 /* We need to set or do a bunch of work here based on previous results*/
581 /* Support paging? What sizes?: F=no, E=16k, D=32k, C=16 & 32k */
582 ti->shared_ram_paging = readb(ti->mmio + AIPSHRAMPAGE);
583
584 /* Available DHB 4Mb size: F=2048, E=4096, D=4464 */
585 switch (readb(ti->mmio + AIP4MBDHB)) {
586 case 0xe: ti->dhb_size4mb = 4096; break;
587 case 0xd: ti->dhb_size4mb = 4464; break;
588 default: ti->dhb_size4mb = 2048; break;
589 }
590
591 /* Available DHB 16Mb size: F=2048, E=4096, D=8192, C=16384, B=17960 */
592 switch (readb(ti->mmio + AIP16MBDHB)) {
593 case 0xe: ti->dhb_size16mb = 4096; break;
594 case 0xd: ti->dhb_size16mb = 8192; break;
595 case 0xc: ti->dhb_size16mb = 16384; break;
596 case 0xb: ti->dhb_size16mb = 17960; break;
597 default: ti->dhb_size16mb = 2048; break;
598 }
599
600 /* We must figure out how much shared memory space this adapter
601 * will occupy so that if there are two adapters we can fit both
602 * in. Given a choice, we will limit this adapter to 32K. The
603 * maximum space will will use for two adapters is 64K so if the
604 * adapter we are working on demands 64K (it also doesn't support
605 * paging), then only one adapter can be supported.
606 */
607
608 /*
609 * determine how much of total RAM is mapped into PC space
610 */
611 ti->mapped_ram_size= /*sixteen to onehundredtwentyeight 512byte blocks*/
612 1<< ((readb(ti->mmio+ACA_OFFSET+ACA_RW+RRR_ODD) >> 2 & 0x03) + 4);
613 ti->page_mask = 0;
614 if (ti->turbo) ti->page_mask=0xf0;
615 else if (ti->shared_ram_paging == 0xf); /* No paging in adapter */
616 else {
617#ifdef ENABLE_PAGING
618 unsigned char pg_size = 0;
619 /* BMS: page size: PCMCIA, use configuration register;
620 ISAPNP, use LANAIDC config tool from www.ibm.com */
621 switch (ti->shared_ram_paging) {
622 case 0xf:
623 break;
624 case 0xe:
625 ti->page_mask = (ti->mapped_ram_size == 32) ? 0xc0 : 0;
626 pg_size = 32; /* 16KB page size */
627 break;
628 case 0xd:
629 ti->page_mask = (ti->mapped_ram_size == 64) ? 0x80 : 0;
630 pg_size = 64; /* 32KB page size */
631 break;
632 case 0xc:
633 switch (ti->mapped_ram_size) {
634 case 32:
635 ti->page_mask = 0xc0;
636 pg_size = 32;
637 break;
638 case 64:
639 ti->page_mask = 0x80;
640 pg_size = 64;
641 break;
642 }
643 break;
644 default:
645 DPRINTK("Unknown shared ram paging info %01X\n",
646 ti->shared_ram_paging);
647 iounmap(t_mmio);
648 kfree(ti);
649 return -ENODEV;
650 break;
651 } /*end switch shared_ram_paging */
652
653 if (ibmtr_debug_trace & TRC_INIT)
654 DPRINTK("Shared RAM paging code: %02X, "
655 "mapped RAM size: %dK, shared RAM size: %dK, "
656 "page mask: %02X\n:",
657 ti->shared_ram_paging, ti->mapped_ram_size / 2,
658 ti->avail_shared_ram / 2, ti->page_mask);
659#endif /*ENABLE_PAGING */
660 }
661
662#ifndef PCMCIA
663 /* finish figuring the shared RAM address */
664 if (cardpresent == TR_ISA) {
665 static __u32 ram_bndry_mask[] =
666 { 0xffffe000, 0xffffc000, 0xffff8000, 0xffff0000 };
667 __u32 new_base, rrr_32, chk_base, rbm;
668
669 rrr_32=readb(ti->mmio+ACA_OFFSET+ACA_RW+RRR_ODD) >> 2 & 0x03;
670 rbm = ram_bndry_mask[rrr_32];
671 new_base = (ibmtr_mem_base + (~rbm)) & rbm;/* up to boundary */
672 chk_base = new_base + (ti->mapped_ram_size << 9);
673 if (chk_base > (ibmtr_mem_base + IBMTR_SHARED_RAM_SIZE)) {
674 DPRINTK("Shared RAM for this adapter (%05x) exceeds "
675 "driver limit (%05x), adapter not started.\n",
676 chk_base, ibmtr_mem_base + IBMTR_SHARED_RAM_SIZE);
677 iounmap(t_mmio);
678 kfree(ti);
679 return -ENODEV;
680 } else { /* seems cool, record what we have figured out */
681 ti->sram_base = new_base >> 12;
682 ibmtr_mem_base = chk_base;
683 }
684 }
685 else ti->sram_base = ti->sram_phys >> 12;
686
687 /* The PCMCIA has already got the interrupt line and the io port,
688 so no chance of anybody else getting it - MLP */
689 if (request_irq(dev->irq = irq, &tok_interrupt, 0, "ibmtr", dev) != 0) {
690 DPRINTK("Could not grab irq %d. Halting Token Ring driver.\n",
691 irq);
692 iounmap(t_mmio);
693 kfree(ti);
694 return -ENODEV;
695 }
696 /*?? Now, allocate some of the PIO PORTs for this driver.. */
697 /* record PIOaddr range as busy */
698 if (!request_region(PIOaddr, IBMTR_IO_EXTENT, "ibmtr")) {
699 DPRINTK("Could not grab PIO range. Halting driver.\n");
700 free_irq(dev->irq, dev);
701 iounmap(t_mmio);
702 kfree(ti);
703 return -EBUSY;
704 }
705
706 if (!version_printed++) {
707 printk(version);
708 }
709#endif /* !PCMCIA */
710 DPRINTK("%s %s found\n",
711 channel_def[cardpresent - 1], adapter_def(ti->adapter_type));
712 DPRINTK("using irq %d, PIOaddr %hx, %dK shared RAM.\n",
713 irq, PIOaddr, ti->mapped_ram_size / 2);
714 DPRINTK("Hardware address : %02X:%02X:%02X:%02X:%02X:%02X\n",
715 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
716 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
717 if (ti->page_mask)
718 DPRINTK("Shared RAM paging enabled. "
719 "Page size: %uK Shared Ram size %dK\n",
720 ((ti->page_mask^0xff)+1) >>2, ti->avail_shared_ram / 2);
721 else
722 DPRINTK("Shared RAM paging disabled. ti->page_mask %x\n",
723 ti->page_mask);
724
725 /* Calculate the maximum DHB we can use */
726 /* two cases where avail_shared_ram doesn't equal mapped_ram_size:
727 1. avail_shared_ram is 127 but mapped_ram_size is 128 (typical)
728 2. user has configured adapter for less than avail_shared_ram
729 but is not using paging (she should use paging, I believe)
730 */
731 if (!ti->page_mask) {
732 ti->avail_shared_ram=
733 min(ti->mapped_ram_size,ti->avail_shared_ram);
734 }
735
736 switch (ti->avail_shared_ram) {
737 case 16: /* 8KB shared RAM */
738 ti->dhb_size4mb = min(ti->dhb_size4mb, (unsigned short)2048);
739 ti->rbuf_len4 = 1032;
740 ti->rbuf_cnt4=2;
741 ti->dhb_size16mb = min(ti->dhb_size16mb, (unsigned short)2048);
742 ti->rbuf_len16 = 1032;
743 ti->rbuf_cnt16=2;
744 break;
745 case 32: /* 16KB shared RAM */
746 ti->dhb_size4mb = min(ti->dhb_size4mb, (unsigned short)4464);
747 ti->rbuf_len4 = 1032;
748 ti->rbuf_cnt4=4;
749 ti->dhb_size16mb = min(ti->dhb_size16mb, (unsigned short)4096);
750 ti->rbuf_len16 = 1032; /*1024 usable */
751 ti->rbuf_cnt16=4;
752 break;
753 case 64: /* 32KB shared RAM */
754 ti->dhb_size4mb = min(ti->dhb_size4mb, (unsigned short)4464);
755 ti->rbuf_len4 = 1032;
756 ti->rbuf_cnt4=6;
757 ti->dhb_size16mb = min(ti->dhb_size16mb, (unsigned short)10240);
758 ti->rbuf_len16 = 1032;
759 ti->rbuf_cnt16=6;
760 break;
761 case 127: /* 63.5KB shared RAM */
762 ti->dhb_size4mb = min(ti->dhb_size4mb, (unsigned short)4464);
763 ti->rbuf_len4 = 1032;
764 ti->rbuf_cnt4=6;
765 ti->dhb_size16mb = min(ti->dhb_size16mb, (unsigned short)16384);
766 ti->rbuf_len16 = 1032;
767 ti->rbuf_cnt16=16;
768 break;
769 case 128: /* 64KB shared RAM */
770 ti->dhb_size4mb = min(ti->dhb_size4mb, (unsigned short)4464);
771 ti->rbuf_len4 = 1032;
772 ti->rbuf_cnt4=6;
773 ti->dhb_size16mb = min(ti->dhb_size16mb, (unsigned short)17960);
774 ti->rbuf_len16 = 1032;
775 ti->rbuf_cnt16=16;
776 break;
777 default:
778 ti->dhb_size4mb = 2048;
779 ti->rbuf_len4 = 1032;
780 ti->rbuf_cnt4=2;
781 ti->dhb_size16mb = 2048;
782 ti->rbuf_len16 = 1032;
783 ti->rbuf_cnt16=2;
784 break;
785 }
786 /* this formula is not smart enough for the paging case
787 ti->rbuf_cnt<x> = (ti->avail_shared_ram * BLOCKSZ - ADAPT_PRIVATE -
788 ARBLENGTH - SSBLENGTH - DLC_MAX_SAP * SAPLENGTH -
789 DLC_MAX_STA * STALENGTH - ti->dhb_size<x>mb * NUM_DHB -
790 SRBLENGTH - ASBLENGTH) / ti->rbuf_len<x>;
791 */
792 ti->maxmtu16 = (ti->rbuf_len16 - 8) * ti->rbuf_cnt16 - TR_HLEN;
793 ti->maxmtu4 = (ti->rbuf_len4 - 8) * ti->rbuf_cnt4 - TR_HLEN;
794 /*BMS assuming 18 bytes of Routing Information (usually works) */
795 DPRINTK("Maximum Receive Internet Protocol MTU 16Mbps: %d, 4Mbps: %d\n",
796 ti->maxmtu16, ti->maxmtu4);
797
798 dev->base_addr = PIOaddr; /* set the value for device */
799 dev->mem_start = ti->sram_base << 12;
800 dev->mem_end = dev->mem_start + (ti->mapped_ram_size << 9) - 1;
801 trdev_init(dev);
802 return 0; /* Return 0 to indicate we have found a Token Ring card. */
803} /*ibmtr_probe1() */
804
805/*****************************************************************************/
806
807/* query the adapter for the size of shared RAM */
808/* the function returns the RAM size in units of 512 bytes */
809
810static unsigned char __devinit get_sram_size(struct tok_info *adapt_info)
811{
812 unsigned char avail_sram_code;
813 static unsigned char size_code[] = { 0, 16, 32, 64, 127, 128 };
814 /* Adapter gives
815 'F' -- use RRR bits 3,2
816 'E' -- 8kb 'D' -- 16kb
817 'C' -- 32kb 'A' -- 64KB
818 'B' - 64KB less 512 bytes at top
819 (WARNING ... must zero top bytes in INIT */
820
821 avail_sram_code = 0xf - readb(adapt_info->mmio + AIPAVAILSHRAM);
822 if (avail_sram_code) return size_code[avail_sram_code];
823 else /* for code 'F', must compute size from RRR(3,2) bits */
824 return 1 <<
825 ((readb(adapt_info->mmio+ACA_OFFSET+ACA_RW+RRR_ODD)>>2&3)+4);
826}
827
828/*****************************************************************************/
829
830static int __devinit trdev_init(struct net_device *dev)
831{
832 struct tok_info *ti = (struct tok_info *) dev->priv;
833
834 SET_PAGE(ti->srb_page);
835 ti->open_failure = NO ;
836 dev->open = tok_open;
837 dev->stop = tok_close;
838 dev->hard_start_xmit = tok_send_packet;
839 dev->get_stats = tok_get_stats;
840 dev->set_multicast_list = tok_set_multicast_list;
841 dev->change_mtu = ibmtr_change_mtu;
842
843 return 0;
844}
845
846/*****************************************************************************/
847
848static int tok_init_card(struct net_device *dev)
849{
850 struct tok_info *ti;
851 short PIOaddr;
852 unsigned long i;
853
854 PIOaddr = dev->base_addr;
855 ti = (struct tok_info *) dev->priv;
856 /* Special processing for first interrupt after reset */
857 ti->do_tok_int = FIRST_INT;
858 /* Reset adapter */
859 writeb(~INT_ENABLE, ti->mmio + ACA_OFFSET + ACA_RESET + ISRP_EVEN);
860 outb(0, PIOaddr + ADAPTRESET);
861
862 current->state=TASK_UNINTERRUPTIBLE;
863 schedule_timeout(TR_RST_TIME); /* wait 50ms */
864
865 outb(0, PIOaddr + ADAPTRESETREL);
866#ifdef ENABLE_PAGING
867 if (ti->page_mask)
868 writeb(SRPR_ENABLE_PAGING,ti->mmio+ACA_OFFSET+ACA_RW+SRPR_EVEN);
869#endif
870 writeb(INT_ENABLE, ti->mmio + ACA_OFFSET + ACA_SET + ISRP_EVEN);
871 i = sleep_on_timeout(&ti->wait_for_reset, 4 * HZ);
872 return i? 0 : -EAGAIN;
873}
874
875/*****************************************************************************/
876static int tok_open(struct net_device *dev)
877{
878 struct tok_info *ti = (struct tok_info *) dev->priv;
879 int i;
880
881 /*the case we were left in a failure state during a previous open */
882 if (ti->open_failure == YES) {
883 DPRINTK("Last time you were disconnected, how about now?\n");
884 printk("You can't insert with an ICS connector half-cocked.\n");
885 }
886
887 ti->open_status = CLOSED; /* CLOSED or OPEN */
888 ti->sap_status = CLOSED; /* CLOSED or OPEN */
889 ti->open_failure = NO; /* NO or YES */
890 ti->open_mode = MANUAL; /* MANUAL or AUTOMATIC */
891 /* 12/2000 not typical Linux, but we can use RUNNING to let us know when
892 the network has crapped out or cables are disconnected. Useful because
893 the IFF_UP flag stays up the whole time, until ifconfig tr0 down.
894 */
895 dev->flags &= ~IFF_RUNNING;
896
897 ti->sram_phys &= ~1; /* to reverse what we do in tok_close */
898 /* init the spinlock */
899 spin_lock_init(&ti->lock);
900 init_timer(&ti->tr_timer);
901
902 i = tok_init_card(dev);
903 if (i) return i;
904
905 while (1){
906 tok_open_adapter((unsigned long) dev);
907 i= interruptible_sleep_on_timeout(&ti->wait_for_reset, 25 * HZ);
908 /* sig catch: estimate opening adapter takes more than .5 sec*/
909 if (i>(245*HZ)/10) break; /* fancier than if (i==25*HZ) */
910 if (i==0) break;
911 if (ti->open_status == OPEN && ti->sap_status==OPEN) {
912 netif_start_queue(dev);
913 DPRINTK("Adapter is up and running\n");
914 return 0;
915 }
916 current->state=TASK_INTERRUPTIBLE;
917 i=schedule_timeout(TR_RETRY_INTERVAL); /* wait 30 seconds */
918 if(i!=0) break; /*prob. a signal, like the i>24*HZ case above */
919 }
920 outb(0, dev->base_addr + ADAPTRESET);/* kill pending interrupts*/
921 DPRINTK("TERMINATED via signal\n"); /*BMS useful */
922 return -EAGAIN;
923}
924
925/*****************************************************************************/
926
927#define COMMAND_OFST 0
928#define OPEN_OPTIONS_OFST 8
929#define NUM_RCV_BUF_OFST 24
930#define RCV_BUF_LEN_OFST 26
931#define DHB_LENGTH_OFST 28
932#define NUM_DHB_OFST 30
933#define DLC_MAX_SAP_OFST 32
934#define DLC_MAX_STA_OFST 33
935
936void tok_open_adapter(unsigned long dev_addr)
937{
938 struct net_device *dev = (struct net_device *) dev_addr;
939 struct tok_info *ti;
940 int i;
941
942 ti = (struct tok_info *) dev->priv;
943 SET_PAGE(ti->init_srb_page);
944 writeb(~SRB_RESP_INT, ti->mmio + ACA_OFFSET + ACA_RESET + ISRP_ODD);
945 for (i = 0; i < sizeof(struct dir_open_adapter); i++)
946 writeb(0, ti->init_srb + i);
947 writeb(DIR_OPEN_ADAPTER, ti->init_srb + COMMAND_OFST);
948 writew(htons(OPEN_PASS_BCON_MAC), ti->init_srb + OPEN_OPTIONS_OFST);
949 if (ti->ring_speed == 16) {
950 writew(htons(ti->dhb_size16mb), ti->init_srb + DHB_LENGTH_OFST);
951 writew(htons(ti->rbuf_cnt16), ti->init_srb + NUM_RCV_BUF_OFST);
952 writew(htons(ti->rbuf_len16), ti->init_srb + RCV_BUF_LEN_OFST);
953 } else {
954 writew(htons(ti->dhb_size4mb), ti->init_srb + DHB_LENGTH_OFST);
955 writew(htons(ti->rbuf_cnt4), ti->init_srb + NUM_RCV_BUF_OFST);
956 writew(htons(ti->rbuf_len4), ti->init_srb + RCV_BUF_LEN_OFST);
957 }
958 writeb(NUM_DHB, /* always 2 */ ti->init_srb + NUM_DHB_OFST);
959 writeb(DLC_MAX_SAP, ti->init_srb + DLC_MAX_SAP_OFST);
960 writeb(DLC_MAX_STA, ti->init_srb + DLC_MAX_STA_OFST);
961 ti->srb = ti->init_srb; /* We use this one in the interrupt handler */
962 ti->srb_page = ti->init_srb_page;
963 DPRINTK("Opening adapter: Xmit bfrs: %d X %d, Rcv bfrs: %d X %d\n",
964 readb(ti->init_srb + NUM_DHB_OFST),
965 ntohs(readw(ti->init_srb + DHB_LENGTH_OFST)),
966 ntohs(readw(ti->init_srb + NUM_RCV_BUF_OFST)),
967 ntohs(readw(ti->init_srb + RCV_BUF_LEN_OFST)));
968 writeb(INT_ENABLE, ti->mmio + ACA_OFFSET + ACA_SET + ISRP_EVEN);
969 writeb(CMD_IN_SRB, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
970}
971
972/*****************************************************************************/
973
974static void open_sap(unsigned char type, struct net_device *dev)
975{
976 int i;
977 struct tok_info *ti = (struct tok_info *) dev->priv;
978
979 SET_PAGE(ti->srb_page);
980 for (i = 0; i < sizeof(struct dlc_open_sap); i++)
981 writeb(0, ti->srb + i);
982
983#define MAX_I_FIELD_OFST 14
984#define SAP_VALUE_OFST 16
985#define SAP_OPTIONS_OFST 17
986#define STATION_COUNT_OFST 18
987
988 writeb(DLC_OPEN_SAP, ti->srb + COMMAND_OFST);
989 writew(htons(MAX_I_FIELD), ti->srb + MAX_I_FIELD_OFST);
990 writeb(SAP_OPEN_IND_SAP | SAP_OPEN_PRIORITY, ti->srb+ SAP_OPTIONS_OFST);
991 writeb(SAP_OPEN_STATION_CNT, ti->srb + STATION_COUNT_OFST);
992 writeb(type, ti->srb + SAP_VALUE_OFST);
993 writeb(CMD_IN_SRB, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
994}
995
996
997/*****************************************************************************/
998
999static void tok_set_multicast_list(struct net_device *dev)
1000{
1001 struct tok_info *ti = (struct tok_info *) dev->priv;
1002 struct dev_mc_list *mclist;
1003 unsigned char address[4];
1004
1005 int i;
1006
1007 /*BMS the next line is CRUCIAL or you may be sad when you */
1008 /*BMS ifconfig tr down or hot unplug a PCMCIA card ??hownowbrowncow*/
1009 if (/*BMSHELPdev->start == 0 ||*/ ti->open_status != OPEN) return;
1010 address[0] = address[1] = address[2] = address[3] = 0;
1011 mclist = dev->mc_list;
1012 for (i = 0; i < dev->mc_count; i++) {
1013 address[0] |= mclist->dmi_addr[2];
1014 address[1] |= mclist->dmi_addr[3];
1015 address[2] |= mclist->dmi_addr[4];
1016 address[3] |= mclist->dmi_addr[5];
1017 mclist = mclist->next;
1018 }
1019 SET_PAGE(ti->srb_page);
1020 for (i = 0; i < sizeof(struct srb_set_funct_addr); i++)
1021 writeb(0, ti->srb + i);
1022
1023#define FUNCT_ADDRESS_OFST 6
1024
1025 writeb(DIR_SET_FUNC_ADDR, ti->srb + COMMAND_OFST);
1026 for (i = 0; i < 4; i++)
1027 writeb(address[i], ti->srb + FUNCT_ADDRESS_OFST + i);
1028 writeb(CMD_IN_SRB, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
1029#if TR_VERBOSE
1030 DPRINTK("Setting functional address: ");
1031 for (i=0;i<4;i++) printk("%02X ", address[i]);
1032 printk("\n");
1033#endif
1034}
1035
1036/*****************************************************************************/
1037
1038#define STATION_ID_OFST 4
1039
1040static int tok_send_packet(struct sk_buff *skb, struct net_device *dev)
1041{
1042 struct tok_info *ti;
1043 unsigned long flags;
1044 ti = (struct tok_info *) dev->priv;
1045
1046 netif_stop_queue(dev);
1047
1048 /* lock against other CPUs */
1049 spin_lock_irqsave(&(ti->lock), flags);
1050
1051 /* Save skb; we'll need it when the adapter asks for the data */
1052 ti->current_skb = skb;
1053 SET_PAGE(ti->srb_page);
1054 writeb(XMIT_UI_FRAME, ti->srb + COMMAND_OFST);
1055 writew(ti->exsap_station_id, ti->srb + STATION_ID_OFST);
1056 writeb(CMD_IN_SRB, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
1057 spin_unlock_irqrestore(&(ti->lock), flags);
1058 dev->trans_start = jiffies;
1059 return 0;
1060}
1061
1062/*****************************************************************************/
1063
1064static int tok_close(struct net_device *dev)
1065{
1066 struct tok_info *ti = (struct tok_info *) dev->priv;
1067
1068 /* Important for PCMCIA hot unplug, otherwise, we'll pull the card, */
1069 /* unloading the module from memory, and then if a timer pops, ouch */
1070 del_timer_sync(&ti->tr_timer);
1071 outb(0, dev->base_addr + ADAPTRESET);
1072 ti->sram_phys |= 1;
1073 ti->open_status = CLOSED;
1074
1075 netif_stop_queue(dev);
1076 DPRINTK("Adapter is closed.\n");
1077 return 0;
1078}
1079
1080/*****************************************************************************/
1081
1082#define RETCODE_OFST 2
1083#define OPEN_ERROR_CODE_OFST 6
1084#define ASB_ADDRESS_OFST 8
1085#define SRB_ADDRESS_OFST 10
1086#define ARB_ADDRESS_OFST 12
1087#define SSB_ADDRESS_OFST 14
1088
1089static char *printphase[]= {"Lobe media test","Physical insertion",
1090 "Address verification","Roll call poll","Request Parameters"};
1091static char *printerror[]={"Function failure","Signal loss","Reserved",
1092 "Frequency error","Timeout","Ring failure","Ring beaconing",
1093 "Duplicate node address",
1094 "Parameter request-retry count exceeded","Remove received",
1095 "IMPL force received","Duplicate modifier",
1096 "No monitor detected","Monitor contention failed for RPL"};
1097
1098static void __iomem *map_address(struct tok_info *ti, unsigned index, __u8 *page)
1099{
1100 if (ti->page_mask) {
1101 *page = (index >> 8) & ti->page_mask;
1102 index &= ~(ti->page_mask << 8);
1103 }
1104 return ti->sram_virt + index;
1105}
1106
1107void dir_open_adapter (struct net_device *dev)
1108{
1109 struct tok_info *ti = (struct tok_info *) dev->priv;
1110 unsigned char ret_code;
1111 __u16 err;
1112
1113 ti->srb = map_address(ti,
1114 ntohs(readw(ti->init_srb + SRB_ADDRESS_OFST)),
1115 &ti->srb_page);
1116 ti->ssb = map_address(ti,
1117 ntohs(readw(ti->init_srb + SSB_ADDRESS_OFST)),
1118 &ti->ssb_page);
1119 ti->arb = map_address(ti,
1120 ntohs(readw(ti->init_srb + ARB_ADDRESS_OFST)),
1121 &ti->arb_page);
1122 ti->asb = map_address(ti,
1123 ntohs(readw(ti->init_srb + ASB_ADDRESS_OFST)),
1124 &ti->asb_page);
1125 ti->current_skb = NULL;
1126 ret_code = readb(ti->init_srb + RETCODE_OFST);
1127 err = ntohs(readw(ti->init_srb + OPEN_ERROR_CODE_OFST));
1128 if (!ret_code) {
1129 ti->open_status = OPEN; /* TR adapter is now available */
1130 if (ti->open_mode == AUTOMATIC) {
1131 DPRINTK("Adapter reopened.\n");
1132 }
1133 writeb(~SRB_RESP_INT, ti->mmio+ACA_OFFSET+ACA_RESET+ISRP_ODD);
1134 open_sap(EXTENDED_SAP, dev);
1135 return;
1136 }
1137 ti->open_failure = YES;
1138 if (ret_code == 7){
1139 if (err == 0x24) {
1140 if (!ti->auto_speedsave) {
1141 DPRINTK("Open failed: Adapter speed must match "
1142 "ring speed if Automatic Ring Speed Save is "
1143 "disabled.\n");
1144 ti->open_action = FAIL;
1145 }else
1146 DPRINTK("Retrying open to adjust to "
1147 "ring speed, ");
1148 } else if (err == 0x2d) {
1149 DPRINTK("Physical Insertion: No Monitor Detected, ");
1150 printk("retrying after %ds delay...\n",
1151 TR_RETRY_INTERVAL/HZ);
1152 } else if (err == 0x11) {
1153 DPRINTK("Lobe Media Function Failure (0x11), ");
1154 printk(" retrying after %ds delay...\n",
1155 TR_RETRY_INTERVAL/HZ);
1156 } else {
1157 char **prphase = printphase;
1158 char **prerror = printerror;
1159 DPRINTK("TR Adapter misc open failure, error code = ");
1160 printk("0x%x, Phase: %s, Error: %s\n",
1161 err, prphase[err/16 -1], prerror[err%16 -1]);
1162 printk(" retrying after %ds delay...\n",
1163 TR_RETRY_INTERVAL/HZ);
1164 }
1165 } else DPRINTK("open failed: ret_code = %02X..., ", ret_code);
1166 if (ti->open_action != FAIL) {
1167 if (ti->open_mode==AUTOMATIC){
1168 ti->open_action = REOPEN;
1169 ibmtr_reset_timer(&(ti->tr_timer), dev);
1170 return;
1171 }
1172 wake_up(&ti->wait_for_reset);
1173 return;
1174 }
1175 DPRINTK("FAILURE, CAPUT\n");
1176}
1177
1178/******************************************************************************/
1179
1180irqreturn_t tok_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1181{
1182 unsigned char status;
1183 /* unsigned char status_even ; */
1184 struct tok_info *ti;
1185 struct net_device *dev;
1186#ifdef ENABLE_PAGING
1187 unsigned char save_srpr;
1188#endif
1189
1190 dev = dev_id;
1191#if TR_VERBOSE
1192 DPRINTK("Int from tok_driver, dev : %p irq%d regs=%p\n", dev,irq,regs);
1193#endif
1194 ti = (struct tok_info *) dev->priv;
1195 if (ti->sram_phys & 1)
1196 return IRQ_NONE; /* PCMCIA card extraction flag */
1197 spin_lock(&(ti->lock));
1198#ifdef ENABLE_PAGING
1199 save_srpr = readb(ti->mmio + ACA_OFFSET + ACA_RW + SRPR_EVEN);
1200#endif
1201
1202 /* Disable interrupts till processing is finished */
1203 writeb((~INT_ENABLE), ti->mmio + ACA_OFFSET + ACA_RESET + ISRP_EVEN);
1204
1205 /* Reset interrupt for ISA boards */
1206 if (ti->adapter_int_enable)
1207 outb(0, ti->adapter_int_enable);
1208 else /* used for PCMCIA cards */
1209 outb(0, ti->global_int_enable);
1210 if (ti->do_tok_int == FIRST_INT){
1211 initial_tok_int(dev);
1212#ifdef ENABLE_PAGING
1213 writeb(save_srpr, ti->mmio + ACA_OFFSET + ACA_RW + SRPR_EVEN);
1214#endif
1215 spin_unlock(&(ti->lock));
1216 return IRQ_HANDLED;
1217 }
1218 /* Begin interrupt handler HERE inline to avoid the extra
1219 levels of logic and call depth for the original solution. */
1220 status = readb(ti->mmio + ACA_OFFSET + ACA_RW + ISRP_ODD);
1221 /*BMSstatus_even = readb (ti->mmio + ACA_OFFSET + ACA_RW + ISRP_EVEN) */
1222 /*BMSdebugprintk("tok_interrupt: ISRP_ODD = 0x%x ISRP_EVEN = 0x%x\n", */
1223 /*BMS status,status_even); */
1224
1225 if (status & ADAP_CHK_INT) {
1226 int i;
1227 void __iomem *check_reason;
1228 __u8 check_reason_page = 0;
1229 check_reason = map_address(ti,
1230 ntohs(readw(ti->mmio+ ACA_OFFSET+ACA_RW + WWCR_EVEN)),
1231 &check_reason_page);
1232 SET_PAGE(check_reason_page);
1233
1234 DPRINTK("Adapter check interrupt\n");
1235 DPRINTK("8 reason bytes follow: ");
1236 for (i = 0; i < 8; i++, check_reason++)
1237 printk("%02X ", (int) readb(check_reason));
1238 printk("\n");
1239 writeb(~ADAP_CHK_INT, ti->mmio+ ACA_OFFSET+ACA_RESET+ ISRP_ODD);
1240 status = readb(ti->mmio + ACA_OFFSET + ACA_RW + ISRA_EVEN);
1241 DPRINTK("ISRA_EVEN == 0x02%x\n",status);
1242 ti->open_status = CLOSED;
1243 ti->sap_status = CLOSED;
1244 ti->open_mode = AUTOMATIC;
1245 dev->flags &= ~IFF_RUNNING;
1246 netif_stop_queue(dev);
1247 ti->open_action = RESTART;
1248 outb(0, dev->base_addr + ADAPTRESET);
1249 ibmtr_reset_timer(&(ti->tr_timer), dev);/*BMS try to reopen*/
1250 spin_unlock(&(ti->lock));
1251 return IRQ_HANDLED;
1252 }
1253 if (readb(ti->mmio + ACA_OFFSET + ACA_RW + ISRP_EVEN)
1254 & (TCR_INT | ERR_INT | ACCESS_INT)) {
1255 DPRINTK("adapter error: ISRP_EVEN : %02x\n",
1256 (int)readb(ti->mmio+ ACA_OFFSET + ACA_RW + ISRP_EVEN));
1257 writeb(~(TCR_INT | ERR_INT | ACCESS_INT),
1258 ti->mmio + ACA_OFFSET + ACA_RESET + ISRP_EVEN);
1259 status= readb(ti->mmio+ ACA_OFFSET + ACA_RW + ISRA_EVEN);/*BMS*/
1260 DPRINTK("ISRA_EVEN == 0x02%x\n",status);/*BMS*/
1261 writeb(INT_ENABLE, ti->mmio + ACA_OFFSET + ACA_SET + ISRP_EVEN);
1262#ifdef ENABLE_PAGING
1263 writeb(save_srpr, ti->mmio + ACA_OFFSET + ACA_RW + SRPR_EVEN);
1264#endif
1265 spin_unlock(&(ti->lock));
1266 return IRQ_HANDLED;
1267 }
1268 if (status & SRB_RESP_INT) { /* SRB response */
1269 SET_PAGE(ti->srb_page);
1270#if TR_VERBOSE
1271 DPRINTK("SRB resp: cmd=%02X rsp=%02X\n",
1272 readb(ti->srb), readb(ti->srb + RETCODE_OFST));
1273#endif
1274 switch (readb(ti->srb)) { /* SRB command check */
1275 case XMIT_DIR_FRAME:{
1276 unsigned char xmit_ret_code;
1277 xmit_ret_code = readb(ti->srb + RETCODE_OFST);
1278 if (xmit_ret_code == 0xff) break;
1279 DPRINTK("error on xmit_dir_frame request: %02X\n",
1280 xmit_ret_code);
1281 if (ti->current_skb) {
1282 dev_kfree_skb_irq(ti->current_skb);
1283 ti->current_skb = NULL;
1284 }
1285 /*dev->tbusy = 0;*/
1286 netif_wake_queue(dev);
1287 if (ti->readlog_pending)
1288 ibmtr_readlog(dev);
1289 break;
1290 }
1291 case XMIT_UI_FRAME:{
1292 unsigned char xmit_ret_code;
1293
1294 xmit_ret_code = readb(ti->srb + RETCODE_OFST);
1295 if (xmit_ret_code == 0xff) break;
1296 DPRINTK("error on xmit_ui_frame request: %02X\n",
1297 xmit_ret_code);
1298 if (ti->current_skb) {
1299 dev_kfree_skb_irq(ti->current_skb);
1300 ti->current_skb = NULL;
1301 }
1302 netif_wake_queue(dev);
1303 if (ti->readlog_pending)
1304 ibmtr_readlog(dev);
1305 break;
1306 }
1307 case DIR_OPEN_ADAPTER:
1308 dir_open_adapter(dev);
1309 break;
1310 case DLC_OPEN_SAP:
1311 if (readb(ti->srb + RETCODE_OFST)) {
1312 DPRINTK("open_sap failed: ret_code = %02X, "
1313 "retrying\n",
1314 (int) readb(ti->srb + RETCODE_OFST));
1315 ti->open_action = REOPEN;
1316 ibmtr_reset_timer(&(ti->tr_timer), dev);
1317 break;
1318 }
1319 ti->exsap_station_id = readw(ti->srb + STATION_ID_OFST);
1320 ti->sap_status = OPEN;/* TR adapter is now available */
1321 if (ti->open_mode==MANUAL){
1322 wake_up(&ti->wait_for_reset);
1323 break;
1324 }
1325 netif_wake_queue(dev);
1326 dev->flags |= IFF_RUNNING;/*BMS 12/2000*/
1327 break;
1328 case DIR_INTERRUPT:
1329 case DIR_MOD_OPEN_PARAMS:
1330 case DIR_SET_GRP_ADDR:
1331 case DIR_SET_FUNC_ADDR:
1332 case DLC_CLOSE_SAP:
1333 if (readb(ti->srb + RETCODE_OFST))
1334 DPRINTK("error on %02X: %02X\n",
1335 (int) readb(ti->srb + COMMAND_OFST),
1336 (int) readb(ti->srb + RETCODE_OFST));
1337 break;
1338 case DIR_READ_LOG:
1339 if (readb(ti->srb + RETCODE_OFST)){
1340 DPRINTK("error on dir_read_log: %02X\n",
1341 (int) readb(ti->srb + RETCODE_OFST));
1342 netif_wake_queue(dev);
1343 break;
1344 }
1345#if IBMTR_DEBUG_MESSAGES
1346
1347#define LINE_ERRORS_OFST 0
1348#define INTERNAL_ERRORS_OFST 1
1349#define BURST_ERRORS_OFST 2
1350#define AC_ERRORS_OFST 3
1351#define ABORT_DELIMITERS_OFST 4
1352#define LOST_FRAMES_OFST 6
1353#define RECV_CONGEST_COUNT_OFST 7
1354#define FRAME_COPIED_ERRORS_OFST 8
1355#define FREQUENCY_ERRORS_OFST 9
1356#define TOKEN_ERRORS_OFST 10
1357
1358 DPRINTK("Line errors %02X, Internal errors %02X, "
1359 "Burst errors %02X\n" "A/C errors %02X, "
1360 "Abort delimiters %02X, Lost frames %02X\n"
1361 "Receive congestion count %02X, "
1362 "Frame copied errors %02X\nFrequency errors %02X, "
1363 "Token errors %02X\n",
1364 (int) readb(ti->srb + LINE_ERRORS_OFST),
1365 (int) readb(ti->srb + INTERNAL_ERRORS_OFST),
1366 (int) readb(ti->srb + BURST_ERRORS_OFST),
1367 (int) readb(ti->srb + AC_ERRORS_OFST),
1368 (int) readb(ti->srb + ABORT_DELIMITERS_OFST),
1369 (int) readb(ti->srb + LOST_FRAMES_OFST),
1370 (int) readb(ti->srb + RECV_CONGEST_COUNT_OFST),
1371 (int) readb(ti->srb + FRAME_COPIED_ERRORS_OFST),
1372 (int) readb(ti->srb + FREQUENCY_ERRORS_OFST),
1373 (int) readb(ti->srb + TOKEN_ERRORS_OFST));
1374#endif
1375 netif_wake_queue(dev);
1376 break;
1377 default:
1378 DPRINTK("Unknown command %02X encountered\n",
1379 (int) readb(ti->srb));
1380 } /* end switch SRB command check */
1381 writeb(~SRB_RESP_INT, ti->mmio+ ACA_OFFSET+ACA_RESET+ ISRP_ODD);
1382 } /* if SRB response */
1383 if (status & ASB_FREE_INT) { /* ASB response */
1384 SET_PAGE(ti->asb_page);
1385#if TR_VERBOSE
1386 DPRINTK("ASB resp: cmd=%02X\n", readb(ti->asb));
1387#endif
1388
1389 switch (readb(ti->asb)) { /* ASB command check */
1390 case REC_DATA:
1391 case XMIT_UI_FRAME:
1392 case XMIT_DIR_FRAME:
1393 break;
1394 default:
1395 DPRINTK("unknown command in asb %02X\n",
1396 (int) readb(ti->asb));
1397 } /* switch ASB command check */
1398 if (readb(ti->asb + 2) != 0xff) /* checks ret_code */
1399 DPRINTK("ASB error %02X in cmd %02X\n",
1400 (int) readb(ti->asb + 2), (int) readb(ti->asb));
1401 writeb(~ASB_FREE_INT, ti->mmio+ ACA_OFFSET+ACA_RESET+ ISRP_ODD);
1402 } /* if ASB response */
1403
1404#define STATUS_OFST 6
1405#define NETW_STATUS_OFST 6
1406
1407 if (status & ARB_CMD_INT) { /* ARB response */
1408 SET_PAGE(ti->arb_page);
1409#if TR_VERBOSE
1410 DPRINTK("ARB resp: cmd=%02X\n", readb(ti->arb));
1411#endif
1412
1413 switch (readb(ti->arb)) { /* ARB command check */
1414 case DLC_STATUS:
1415 DPRINTK("DLC_STATUS new status: %02X on station %02X\n",
1416 ntohs(readw(ti->arb + STATUS_OFST)),
1417 ntohs(readw(ti->arb+ STATION_ID_OFST)));
1418 break;
1419 case REC_DATA:
1420 tr_rx(dev);
1421 break;
1422 case RING_STAT_CHANGE:{
1423 unsigned short ring_status;
1424 ring_status= ntohs(readw(ti->arb + NETW_STATUS_OFST));
1425 if (ibmtr_debug_trace & TRC_INIT)
1426 DPRINTK("Ring Status Change...(0x%x)\n",
1427 ring_status);
1428 if(ring_status& (REMOVE_RECV|AUTO_REMOVAL|LOBE_FAULT)){
1429 netif_stop_queue(dev);
1430 dev->flags &= ~IFF_RUNNING;/*not typical Linux*/
1431 DPRINTK("Remove received, or Auto-removal error"
1432 ", or Lobe fault\n");
1433 DPRINTK("We'll try to reopen the closed adapter"
1434 " after a %d second delay.\n",
1435 TR_RETRY_INTERVAL/HZ);
1436 /*I was confused: I saw the TR reopening but */
1437 /*forgot:with an RJ45 in an RJ45/ICS adapter */
1438 /*but adapter not in the ring, the TR will */
1439 /* open, and then soon close and come here. */
1440 ti->open_mode = AUTOMATIC;
1441 ti->open_status = CLOSED; /*12/2000 BMS*/
1442 ti->open_action = REOPEN;
1443 ibmtr_reset_timer(&(ti->tr_timer), dev);
1444 } else if (ring_status & LOG_OVERFLOW) {
1445 if(netif_queue_stopped(dev))
1446 ti->readlog_pending = 1;
1447 else
1448 ibmtr_readlog(dev);
1449 }
1450 break;
1451 }
1452 case XMIT_DATA_REQ:
1453 tr_tx(dev);
1454 break;
1455 default:
1456 DPRINTK("Unknown command %02X in arb\n",
1457 (int) readb(ti->arb));
1458 break;
1459 } /* switch ARB command check */
1460 writeb(~ARB_CMD_INT, ti->mmio+ ACA_OFFSET+ACA_RESET + ISRP_ODD);
1461 writeb(ARB_FREE, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
1462 } /* if ARB response */
1463 if (status & SSB_RESP_INT) { /* SSB response */
1464 unsigned char retcode;
1465 SET_PAGE(ti->ssb_page);
1466#if TR_VERBOSE
1467 DPRINTK("SSB resp: cmd=%02X rsp=%02X\n",
1468 readb(ti->ssb), readb(ti->ssb + 2));
1469#endif
1470
1471 switch (readb(ti->ssb)) { /* SSB command check */
1472 case XMIT_DIR_FRAME:
1473 case XMIT_UI_FRAME:
1474 retcode = readb(ti->ssb + 2);
1475 if (retcode && (retcode != 0x22))/* checks ret_code */
1476 DPRINTK("xmit ret_code: %02X xmit error code: "
1477 "%02X\n",
1478 (int)retcode, (int)readb(ti->ssb + 6));
1479 else
1480 ti->tr_stats.tx_packets++;
1481 break;
1482 case XMIT_XID_CMD:
1483 DPRINTK("xmit xid ret_code: %02X\n",
1484 (int) readb(ti->ssb + 2));
1485 default:
1486 DPRINTK("Unknown command %02X in ssb\n",
1487 (int) readb(ti->ssb));
1488 } /* SSB command check */
1489 writeb(~SSB_RESP_INT, ti->mmio+ ACA_OFFSET+ACA_RESET+ ISRP_ODD);
1490 writeb(SSB_FREE, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
1491 } /* if SSB response */
1492#ifdef ENABLE_PAGING
1493 writeb(save_srpr, ti->mmio + ACA_OFFSET + ACA_RW + SRPR_EVEN);
1494#endif
1495 writeb(INT_ENABLE, ti->mmio + ACA_OFFSET + ACA_SET + ISRP_EVEN);
1496 spin_unlock(&(ti->lock));
1497 return IRQ_HANDLED;
1498} /*tok_interrupt */
1499
1500/*****************************************************************************/
1501
1502#define INIT_STATUS_OFST 1
1503#define INIT_STATUS_2_OFST 2
1504#define ENCODED_ADDRESS_OFST 8
1505
1506static void initial_tok_int(struct net_device *dev)
1507{
1508
1509 __u32 encoded_addr, hw_encoded_addr;
1510 struct tok_info *ti;
1511 unsigned char init_status; /*BMS 12/2000*/
1512
1513 ti = (struct tok_info *) dev->priv;
1514
1515 ti->do_tok_int = NOT_FIRST;
1516
1517 /* we assign the shared-ram address for ISA devices */
1518 writeb(ti->sram_base, ti->mmio + ACA_OFFSET + ACA_RW + RRR_EVEN);
1519#ifndef PCMCIA
1520 ti->sram_virt = ioremap(((__u32)ti->sram_base << 12), ti->avail_shared_ram);
1521#endif
1522 ti->init_srb = map_address(ti,
1523 ntohs(readw(ti->mmio + ACA_OFFSET + WRBR_EVEN)),
1524 &ti->init_srb_page);
1525 if (ti->page_mask && ti->avail_shared_ram == 127) {
1526 void __iomem *last_512;
1527 __u8 last_512_page=0;
1528 int i;
1529 last_512 = map_address(ti, 0xfe00, &last_512_page);
1530 /* initialize high section of ram (if necessary) */
1531 SET_PAGE(last_512_page);
1532 for (i = 0; i < 512; i++)
1533 writeb(0, last_512 + i);
1534 }
1535 SET_PAGE(ti->init_srb_page);
1536
1537#if TR_VERBOSE
1538 {
1539 int i;
1540
1541 DPRINTK("ti->init_srb_page=0x%x\n", ti->init_srb_page);
1542 DPRINTK("init_srb(%p):", ti->init_srb );
1543 for (i = 0; i < 20; i++)
1544 printk("%02X ", (int) readb(ti->init_srb + i));
1545 printk("\n");
1546 }
1547#endif
1548
1549 hw_encoded_addr = readw(ti->init_srb + ENCODED_ADDRESS_OFST);
1550 encoded_addr = ntohs(hw_encoded_addr);
1551 init_status= /*BMS 12/2000 check for shallow mode possibility (Turbo)*/
1552 readb(ti->init_srb+offsetof(struct srb_init_response,init_status));
1553 /*printk("Initial interrupt: init_status= 0x%02x\n",init_status);*/
1554 ti->ring_speed = init_status & 0x01 ? 16 : 4;
1555 DPRINTK("Initial interrupt : %d Mbps, shared RAM base %08x.\n",
1556 ti->ring_speed, (unsigned int)dev->mem_start);
1557 ti->auto_speedsave=readb(ti->init_srb+INIT_STATUS_2_OFST)&4?TRUE:FALSE;
1558
1559 if (ti->open_mode == MANUAL) wake_up(&ti->wait_for_reset);
1560 else tok_open_adapter((unsigned long)dev);
1561
1562} /*initial_tok_int() */
1563
1564/*****************************************************************************/
1565
1566#define CMD_CORRELATE_OFST 1
1567#define DHB_ADDRESS_OFST 6
1568
1569#define FRAME_LENGTH_OFST 6
1570#define HEADER_LENGTH_OFST 8
1571#define RSAP_VALUE_OFST 9
1572
1573static void tr_tx(struct net_device *dev)
1574{
1575 struct tok_info *ti = (struct tok_info *) dev->priv;
1576 struct trh_hdr *trhdr = (struct trh_hdr *) ti->current_skb->data;
1577 unsigned int hdr_len;
1578 __u32 dhb=0,dhb_base;
1579 void __iomem *dhbuf = NULL;
1580 unsigned char xmit_command;
1581 int i,dhb_len=0x4000,src_len,src_offset;
1582 struct trllc *llc;
1583 struct srb_xmit xsrb;
1584 __u8 dhb_page = 0;
1585 __u8 llc_ssap;
1586
1587 SET_PAGE(ti->asb_page);
1588
1589 if (readb(ti->asb+RETCODE_OFST) != 0xFF) DPRINTK("ASB not free !!!\n");
1590
1591 /* in providing the transmit interrupts, is telling us it is ready for
1592 data and providing a shared memory address for us to stuff with data.
1593 Here we compute the effective address where we will place data.
1594 */
1595 SET_PAGE(ti->arb_page);
1596 dhb=dhb_base=ntohs(readw(ti->arb + DHB_ADDRESS_OFST));
1597 if (ti->page_mask) {
1598 dhb_page = (dhb_base >> 8) & ti->page_mask;
1599 dhb=dhb_base & ~(ti->page_mask << 8);
1600 }
1601 dhbuf = ti->sram_virt + dhb;
1602
1603 /* Figure out the size of the 802.5 header */
1604 if (!(trhdr->saddr[0] & 0x80)) /* RIF present? */
1605 hdr_len = sizeof(struct trh_hdr) - TR_MAXRIFLEN;
1606 else
1607 hdr_len = ((ntohs(trhdr->rcf) & TR_RCF_LEN_MASK) >> 8)
1608 + sizeof(struct trh_hdr) - TR_MAXRIFLEN;
1609
1610 llc = (struct trllc *) (ti->current_skb->data + hdr_len);
1611
1612 llc_ssap = llc->ssap;
1613 SET_PAGE(ti->srb_page);
1614 memcpy_fromio(&xsrb, ti->srb, sizeof(xsrb));
1615 SET_PAGE(ti->asb_page);
1616 xmit_command = xsrb.command;
1617
1618 writeb(xmit_command, ti->asb + COMMAND_OFST);
1619 writew(xsrb.station_id, ti->asb + STATION_ID_OFST);
1620 writeb(llc_ssap, ti->asb + RSAP_VALUE_OFST);
1621 writeb(xsrb.cmd_corr, ti->asb + CMD_CORRELATE_OFST);
1622 writeb(0, ti->asb + RETCODE_OFST);
1623 if ((xmit_command == XMIT_XID_CMD) || (xmit_command == XMIT_TEST_CMD)) {
1624 writew(htons(0x11), ti->asb + FRAME_LENGTH_OFST);
1625 writeb(0x0e, ti->asb + HEADER_LENGTH_OFST);
1626 SET_PAGE(dhb_page);
1627 writeb(AC, dhbuf);
1628 writeb(LLC_FRAME, dhbuf + 1);
1629 for (i = 0; i < TR_ALEN; i++)
1630 writeb((int) 0x0FF, dhbuf + i + 2);
1631 for (i = 0; i < TR_ALEN; i++)
1632 writeb(0, dhbuf + i + TR_ALEN + 2);
1633 writeb(RESP_IN_ASB, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
1634 return;
1635 }
1636 /*
1637 * the token ring packet is copied from sk_buff to the adapter
1638 * buffer identified in the command data received with the interrupt.
1639 */
1640 writeb(hdr_len, ti->asb + HEADER_LENGTH_OFST);
1641 writew(htons(ti->current_skb->len), ti->asb + FRAME_LENGTH_OFST);
1642 src_len=ti->current_skb->len;
1643 src_offset=0;
1644 dhb=dhb_base;
1645 while(1) {
1646 if (ti->page_mask) {
1647 dhb_page=(dhb >> 8) & ti->page_mask;
1648 dhb=dhb & ~(ti->page_mask << 8);
1649 dhb_len=0x4000-dhb; /* remaining size of this page */
1650 }
1651 dhbuf = ti->sram_virt + dhb;
1652 SET_PAGE(dhb_page);
1653 if (src_len > dhb_len) {
1654 memcpy_toio(dhbuf,&ti->current_skb->data[src_offset],
1655 dhb_len);
1656 src_len -= dhb_len;
1657 src_offset += dhb_len;
1658 dhb_base+=dhb_len;
1659 dhb=dhb_base;
1660 continue;
1661 }
1662 memcpy_toio(dhbuf, &ti->current_skb->data[src_offset], src_len);
1663 break;
1664 }
1665 writeb(RESP_IN_ASB, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
1666 ti->tr_stats.tx_bytes += ti->current_skb->len;
1667 dev_kfree_skb_irq(ti->current_skb);
1668 ti->current_skb = NULL;
1669 netif_wake_queue(dev);
1670 if (ti->readlog_pending)
1671 ibmtr_readlog(dev);
1672} /*tr_tx */
1673
1674/*****************************************************************************/
1675
1676
1677#define RECEIVE_BUFFER_OFST 6
1678#define LAN_HDR_LENGTH_OFST 8
1679#define DLC_HDR_LENGTH_OFST 9
1680
1681#define DSAP_OFST 0
1682#define SSAP_OFST 1
1683#define LLC_OFST 2
1684#define PROTID_OFST 3
1685#define ETHERTYPE_OFST 6
1686
1687static void tr_rx(struct net_device *dev)
1688{
1689 struct tok_info *ti = (struct tok_info *) dev->priv;
1690 __u32 rbuffer;
1691 void __iomem *rbuf, *rbufdata, *llc;
1692 __u8 rbuffer_page = 0;
1693 unsigned char *data;
1694 unsigned int rbuffer_len, lan_hdr_len, hdr_len, ip_len, length;
1695 unsigned char dlc_hdr_len;
1696 struct sk_buff *skb;
1697 unsigned int skb_size = 0;
1698 int IPv4_p = 0;
1699 unsigned int chksum = 0;
1700 struct iphdr *iph;
1701 struct arb_rec_req rarb;
1702
1703 SET_PAGE(ti->arb_page);
1704 memcpy_fromio(&rarb, ti->arb, sizeof(rarb));
1705 rbuffer = ntohs(rarb.rec_buf_addr) ;
1706 rbuf = map_address(ti, rbuffer, &rbuffer_page);
1707
1708 SET_PAGE(ti->asb_page);
1709
1710 if (readb(ti->asb + RETCODE_OFST) !=0xFF) DPRINTK("ASB not free !!!\n");
1711
1712 writeb(REC_DATA, ti->asb + COMMAND_OFST);
1713 writew(rarb.station_id, ti->asb + STATION_ID_OFST);
1714 writew(rarb.rec_buf_addr, ti->asb + RECEIVE_BUFFER_OFST);
1715
1716 lan_hdr_len = rarb.lan_hdr_len;
1717 if (lan_hdr_len > sizeof(struct trh_hdr)) {
1718 DPRINTK("Linux cannot handle greater than 18 bytes RIF\n");
1719 return;
1720 } /*BMS I added this above just to be very safe */
1721 dlc_hdr_len = readb(ti->arb + DLC_HDR_LENGTH_OFST);
1722 hdr_len = lan_hdr_len + sizeof(struct trllc) + sizeof(struct iphdr);
1723
1724 SET_PAGE(rbuffer_page);
1725 llc = rbuf + offsetof(struct rec_buf, data) + lan_hdr_len;
1726
1727#if TR_VERBOSE
1728 DPRINTK("offsetof data: %02X lan_hdr_len: %02X\n",
1729 (__u32) offsetof(struct rec_buf, data), (unsigned int) lan_hdr_len);
1730 DPRINTK("llc: %08X rec_buf_addr: %04X dev->mem_start: %lX\n",
1731 llc, ntohs(rarb.rec_buf_addr), dev->mem_start);
1732 DPRINTK("dsap: %02X, ssap: %02X, llc: %02X, protid: %02X%02X%02X, "
1733 "ethertype: %04X\n",
1734 (int) readb(llc + DSAP_OFST), (int) readb(llc + SSAP_OFST),
1735 (int) readb(llc + LLC_OFST), (int) readb(llc + PROTID_OFST),
1736 (int) readb(llc+PROTID_OFST+1),(int)readb(llc+PROTID_OFST + 2),
1737 (int) ntohs(readw(llc + ETHERTYPE_OFST)));
1738#endif
1739 if (readb(llc + offsetof(struct trllc, llc)) != UI_CMD) {
1740 SET_PAGE(ti->asb_page);
1741 writeb(DATA_LOST, ti->asb + RETCODE_OFST);
1742 ti->tr_stats.rx_dropped++;
1743 writeb(RESP_IN_ASB, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
1744 return;
1745 }
1746 length = ntohs(rarb.frame_len);
1747 if (readb(llc + DSAP_OFST) == EXTENDED_SAP &&
1748 readb(llc + SSAP_OFST) == EXTENDED_SAP &&
1749 length >= hdr_len) IPv4_p = 1;
1750#if TR_VERBOSE
1751#define SADDR_OFST 8
1752#define DADDR_OFST 2
1753
1754 if (!IPv4_p) {
1755
1756 void __iomem *trhhdr = rbuf + offsetof(struct rec_buf, data);
1757
1758 DPRINTK("Probably non-IP frame received.\n");
1759 DPRINTK("ssap: %02X dsap: %02X "
1760 "saddr: %02X:%02X:%02X:%02X:%02X:%02X "
1761 "daddr: %02X:%02X:%02X:%02X:%02X:%02X\n",
1762 readb(llc + SSAP_OFST), readb(llc + DSAP_OFST),
1763 readb(trhhdr+SADDR_OFST), readb(trhhdr+ SADDR_OFST+1),
1764 readb(trhhdr+SADDR_OFST+2), readb(trhhdr+SADDR_OFST+3),
1765 readb(trhhdr+SADDR_OFST+4), readb(trhhdr+SADDR_OFST+5),
1766 readb(trhhdr+DADDR_OFST), readb(trhhdr+DADDR_OFST + 1),
1767 readb(trhhdr+DADDR_OFST+2), readb(trhhdr+DADDR_OFST+3),
1768 readb(trhhdr+DADDR_OFST+4), readb(trhhdr+DADDR_OFST+5));
1769 }
1770#endif
1771
1772 /*BMS handle the case she comes in with few hops but leaves with many */
1773 skb_size=length-lan_hdr_len+sizeof(struct trh_hdr)+sizeof(struct trllc);
1774
1775 if (!(skb = dev_alloc_skb(skb_size))) {
1776 DPRINTK("out of memory. frame dropped.\n");
1777 ti->tr_stats.rx_dropped++;
1778 SET_PAGE(ti->asb_page);
1779 writeb(DATA_LOST, ti->asb + offsetof(struct asb_rec, ret_code));
1780 writeb(RESP_IN_ASB, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
1781 return;
1782 }
1783 /*BMS again, if she comes in with few but leaves with many */
1784 skb_reserve(skb, sizeof(struct trh_hdr) - lan_hdr_len);
1785 skb_put(skb, length);
1786 skb->dev = dev;
1787 data = skb->data;
1788 rbuffer_len = ntohs(readw(rbuf + offsetof(struct rec_buf, buf_len)));
1789 rbufdata = rbuf + offsetof(struct rec_buf, data);
1790
1791 if (IPv4_p) {
1792 /* Copy the headers without checksumming */
1793 memcpy_fromio(data, rbufdata, hdr_len);
1794
1795 /* Watch for padded packets and bogons */
1796 iph= (struct iphdr *)(data+ lan_hdr_len + sizeof(struct trllc));
1797 ip_len = ntohs(iph->tot_len) - sizeof(struct iphdr);
1798 length -= hdr_len;
1799 if ((ip_len <= length) && (ip_len > 7))
1800 length = ip_len;
1801 data += hdr_len;
1802 rbuffer_len -= hdr_len;
1803 rbufdata += hdr_len;
1804 }
1805 /* Copy the payload... */
1806#define BUFFER_POINTER_OFST 2
1807#define BUFFER_LENGTH_OFST 6
1808 for (;;) {
1809 if (ibmtr_debug_trace&TRC_INITV && length < rbuffer_len)
1810 DPRINTK("CURIOUS, length=%d < rbuffer_len=%d\n",
1811 length,rbuffer_len);
1812 if (IPv4_p)
1813 chksum=csum_partial_copy_nocheck((void*)rbufdata,
1814 data,length<rbuffer_len?length:rbuffer_len,chksum);
1815 else
1816 memcpy_fromio(data, rbufdata, rbuffer_len);
1817 rbuffer = ntohs(readw(rbuf+BUFFER_POINTER_OFST)) ;
1818 if (!rbuffer)
1819 break;
1820 rbuffer -= 2;
1821 length -= rbuffer_len;
1822 data += rbuffer_len;
1823 rbuf = map_address(ti, rbuffer, &rbuffer_page);
1824 SET_PAGE(rbuffer_page);
1825 rbuffer_len = ntohs(readw(rbuf + BUFFER_LENGTH_OFST));
1826 rbufdata = rbuf + offsetof(struct rec_buf, data);
1827 }
1828
1829 SET_PAGE(ti->asb_page);
1830 writeb(0, ti->asb + offsetof(struct asb_rec, ret_code));
1831
1832 writeb(RESP_IN_ASB, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
1833
1834 ti->tr_stats.rx_bytes += skb->len;
1835 ti->tr_stats.rx_packets++;
1836
1837 skb->protocol = tr_type_trans(skb, dev);
1838 if (IPv4_p) {
1839 skb->csum = chksum;
1840 skb->ip_summed = 1;
1841 }
1842 netif_rx(skb);
1843 dev->last_rx = jiffies;
1844} /*tr_rx */
1845
1846/*****************************************************************************/
1847
1848void ibmtr_reset_timer(struct timer_list *tmr, struct net_device *dev)
1849{
1850 tmr->expires = jiffies + TR_RETRY_INTERVAL;
1851 tmr->data = (unsigned long) dev;
1852 tmr->function = tok_rerun;
1853 init_timer(tmr);
1854 add_timer(tmr);
1855}
1856
1857/*****************************************************************************/
1858
1859void tok_rerun(unsigned long dev_addr){
1860
1861 struct net_device *dev = (struct net_device *)dev_addr;
1862 struct tok_info *ti = (struct tok_info *) dev->priv;
1863
1864 if ( ti->open_action == RESTART){
1865 ti->do_tok_int = FIRST_INT;
1866 outb(0, dev->base_addr + ADAPTRESETREL);
1867#ifdef ENABLE_PAGING
1868 if (ti->page_mask)
1869 writeb(SRPR_ENABLE_PAGING,
1870 ti->mmio + ACA_OFFSET + ACA_RW + SRPR_EVEN);
1871#endif
1872
1873 writeb(INT_ENABLE, ti->mmio + ACA_OFFSET + ACA_SET + ISRP_EVEN);
1874 } else
1875 tok_open_adapter(dev_addr);
1876}
1877
1878/*****************************************************************************/
1879
1880void ibmtr_readlog(struct net_device *dev)
1881{
1882 struct tok_info *ti;
1883
1884 ti = (struct tok_info *) dev->priv;
1885
1886 ti->readlog_pending = 0;
1887 SET_PAGE(ti->srb_page);
1888 writeb(DIR_READ_LOG, ti->srb);
1889 writeb(INT_ENABLE, ti->mmio + ACA_OFFSET + ACA_SET + ISRP_EVEN);
1890 writeb(CMD_IN_SRB, ti->mmio + ACA_OFFSET + ACA_SET + ISRA_ODD);
1891
1892 netif_stop_queue(dev);
1893
1894}
1895
1896/*****************************************************************************/
1897
1898/* tok_get_stats(): Basically a scaffold routine which will return
1899 the address of the tr_statistics structure associated with
1900 this device -- the tr.... structure is an ethnet look-alike
1901 so at least for this iteration may suffice. */
1902
1903static struct net_device_stats *tok_get_stats(struct net_device *dev)
1904{
1905
1906 struct tok_info *toki;
1907 toki = (struct tok_info *) dev->priv;
1908 return (struct net_device_stats *) &toki->tr_stats;
1909}
1910
1911/*****************************************************************************/
1912
1913int ibmtr_change_mtu(struct net_device *dev, int mtu)
1914{
1915 struct tok_info *ti = (struct tok_info *) dev->priv;
1916
1917 if (ti->ring_speed == 16 && mtu > ti->maxmtu16)
1918 return -EINVAL;
1919 if (ti->ring_speed == 4 && mtu > ti->maxmtu4)
1920 return -EINVAL;
1921 dev->mtu = mtu;
1922 return 0;
1923}
1924
1925/*****************************************************************************/
1926#ifdef MODULE
1927
1928/* 3COM 3C619C supports 8 interrupts, 32 I/O ports */
1929static struct net_device *dev_ibmtr[IBMTR_MAX_ADAPTERS];
1930static int io[IBMTR_MAX_ADAPTERS] = { 0xa20, 0xa24 };
1931static int irq[IBMTR_MAX_ADAPTERS];
1932static int mem[IBMTR_MAX_ADAPTERS];
1933
1934MODULE_LICENSE("GPL");
1935
1936module_param_array(io, int, NULL, 0);
1937module_param_array(irq, int, NULL, 0);
1938module_param_array(mem, int, NULL, 0);
1939
1940static int __init ibmtr_init(void)
1941{
1942 int i;
1943 int count=0;
1944
1945 find_turbo_adapters(io);
1946
1947 for (i = 0; io[i] && (i < IBMTR_MAX_ADAPTERS); i++) {
1948 struct net_device *dev;
1949 irq[i] = 0;
1950 mem[i] = 0;
1951 dev = alloc_trdev(sizeof(struct tok_info));
1952 if (dev == NULL) {
1953 if (i == 0)
1954 return -ENOMEM;
1955 break;
1956 }
1957 dev->base_addr = io[i];
1958 dev->irq = irq[i];
1959 dev->mem_start = mem[i];
1960
1961 if (ibmtr_probe_card(dev)) {
1962 free_netdev(dev);
1963 continue;
1964 }
1965 dev_ibmtr[i] = dev;
1966 count++;
1967 }
1968 if (count) return 0;
1969 printk("ibmtr: register_netdev() returned non-zero.\n");
1970 return -EIO;
1971}
1972module_init(ibmtr_init);
1973
1974static void __exit ibmtr_cleanup(void)
1975{
1976 int i;
1977
1978 for (i = 0; i < IBMTR_MAX_ADAPTERS; i++){
1979 if (!dev_ibmtr[i])
1980 continue;
1981 unregister_netdev(dev_ibmtr[i]);
1982 ibmtr_cleanup_card(dev_ibmtr[i]);
1983 free_netdev(dev_ibmtr[i]);
1984 }
1985}
1986module_exit(ibmtr_cleanup);
1987#endif
diff --git a/drivers/net/tokenring/lanstreamer.c b/drivers/net/tokenring/lanstreamer.c
new file mode 100644
index 000000000000..99e0b03b69a8
--- /dev/null
+++ b/drivers/net/tokenring/lanstreamer.c
@@ -0,0 +1,2011 @@
1/*
2 * lanstreamer.c -- driver for the IBM Auto LANStreamer PCI Adapter
3 *
4 * Written By: Mike Sullivan, IBM Corporation
5 *
6 * Copyright (C) 1999 IBM Corporation
7 *
8 * Linux driver for IBM PCI tokenring cards based on the LanStreamer MPC
9 * chipset.
10 *
11 * This driver is based on the olympic driver for IBM PCI TokenRing cards (Pit/Pit-Phy/Olympic
12 * chipsets) written by:
13 * 1999 Peter De Schrijver All Rights Reserved
14 * 1999 Mike Phillips (phillim@amtrak.com)
15 *
16 * Base Driver Skeleton:
17 * Written 1993-94 by Donald Becker.
18 *
19 * Copyright 1993 United States Government as represented by the
20 * Director, National Security Agency.
21 *
22 * This program is free software; you can redistribute it and/or modify
23 * it under the terms of the GNU General Public License as published by
24 * the Free Software Foundation; either version 2 of the License, or
25 * (at your option) any later version.
26 *
27 * This program is distributed in the hope that it will be useful,
28 * but WITHOUT ANY WARRANTY; without even the implied warranty of
29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30 * GNU General Public License for more details.
31 *
32 * NO WARRANTY
33 * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
34 * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
35 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
36 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
37 * solely responsible for determining the appropriateness of using and
38 * distributing the Program and assumes all risks associated with its
39 * exercise of rights under this Agreement, including but not limited to
40 * the risks and costs of program errors, damage to or loss of data,
41 * programs or equipment, and unavailability or interruption of operations.
42 *
43 * DISCLAIMER OF LIABILITY
44 * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
45 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
46 * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
47 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
48 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
49 * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
50 * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
51 *
52 * You should have received a copy of the GNU General Public License
53 * along with this program; if not, write to the Free Software
54 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
55 *
56 *
57 * 12/10/99 - Alpha Release 0.1.0
58 * First release to the public
59 * 03/03/00 - Merged to kernel, indented -kr -i8 -bri0, fixed some missing
60 * malloc free checks, reviewed code. <alan@redhat.com>
61 * 03/13/00 - Added spinlocks for smp
62 * 03/08/01 - Added support for module_init() and module_exit()
63 * 08/15/01 - Added ioctl() functionality for debugging, changed netif_*_queue
64 * calls and other incorrectness - Kent Yoder <yoder1@us.ibm.com>
65 * 11/05/01 - Restructured the interrupt function, added delays, reduced the
66 * the number of TX descriptors to 1, which together can prevent
67 * the card from locking up the box - <yoder1@us.ibm.com>
68 * 09/27/02 - New PCI interface + bug fix. - <yoder1@us.ibm.com>
69 * 11/13/02 - Removed free_irq calls which could cause a hang, added
70 * netif_carrier_{on|off} - <yoder1@us.ibm.com>
71 *
72 * To Do:
73 *
74 *
75 * If Problems do Occur
76 * Most problems can be rectified by either closing and opening the interface
77 * (ifconfig down and up) or rmmod and insmod'ing the driver (a bit difficult
78 * if compiled into the kernel).
79 */
80
81/* Change STREAMER_DEBUG to 1 to get verbose, and I mean really verbose, messages */
82
83#define STREAMER_DEBUG 0
84#define STREAMER_DEBUG_PACKETS 0
85
86/* Change STREAMER_NETWORK_MONITOR to receive mac frames through the arb channel.
87 * Will also create a /proc/net/streamer_tr entry if proc_fs is compiled into the
88 * kernel.
89 * Intended to be used to create a ring-error reporting network module
90 * i.e. it will give you the source address of beaconers on the ring
91 */
92
93#define STREAMER_NETWORK_MONITOR 0
94
95/* #define CONFIG_PROC_FS */
96
97/*
98 * Allow or disallow ioctl's for debugging
99 */
100
101#define STREAMER_IOCTL 0
102
103#include <linux/config.h>
104#include <linux/module.h>
105#include <linux/kernel.h>
106#include <linux/errno.h>
107#include <linux/timer.h>
108#include <linux/in.h>
109#include <linux/ioport.h>
110#include <linux/string.h>
111#include <linux/proc_fs.h>
112#include <linux/ptrace.h>
113#include <linux/skbuff.h>
114#include <linux/interrupt.h>
115#include <linux/delay.h>
116#include <linux/netdevice.h>
117#include <linux/trdevice.h>
118#include <linux/stddef.h>
119#include <linux/init.h>
120#include <linux/pci.h>
121#include <linux/spinlock.h>
122#include <linux/version.h>
123#include <linux/bitops.h>
124
125#include <net/checksum.h>
126
127#include <asm/io.h>
128#include <asm/system.h>
129
130#include "lanstreamer.h"
131
132#if (BITS_PER_LONG == 64)
133#error broken on 64-bit: stores pointer to rx_ring->buffer in 32-bit int
134#endif
135
136
137/* I've got to put some intelligence into the version number so that Peter and I know
138 * which version of the code somebody has got.
139 * Version Number = a.b.c.d where a.b.c is the level of code and d is the latest author.
140 * So 0.0.1.pds = Peter, 0.0.1.mlp = Mike
141 *
142 * Official releases will only have an a.b.c version number format.
143 */
144
145static char version[] = "LanStreamer.c v0.4.0 03/08/01 - Mike Sullivan\n"
146 " v0.5.3 11/13/02 - Kent Yoder";
147
148static struct pci_device_id streamer_pci_tbl[] = {
149 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_TR, PCI_ANY_ID, PCI_ANY_ID,},
150 {} /* terminating entry */
151};
152MODULE_DEVICE_TABLE(pci,streamer_pci_tbl);
153
154
155static char *open_maj_error[] = {
156 "No error", "Lobe Media Test", "Physical Insertion",
157 "Address Verification", "Neighbor Notification (Ring Poll)",
158 "Request Parameters", "FDX Registration Request",
159 "FDX Lobe Media Test", "FDX Duplicate Address Check",
160 "Unknown stage"
161};
162
163static char *open_min_error[] = {
164 "No error", "Function Failure", "Signal Lost", "Wire Fault",
165 "Ring Speed Mismatch", "Timeout", "Ring Failure", "Ring Beaconing",
166 "Duplicate Node Address", "Request Parameters", "Remove Received",
167 "Reserved", "Reserved", "No Monitor Detected for RPL",
168 "Monitor Contention failer for RPL", "FDX Protocol Error"
169};
170
171/* Module paramters */
172
173/* Ring Speed 0,4,16
174 * 0 = Autosense
175 * 4,16 = Selected speed only, no autosense
176 * This allows the card to be the first on the ring
177 * and become the active monitor.
178 *
179 * WARNING: Some hubs will allow you to insert
180 * at the wrong speed
181 */
182
183static int ringspeed[STREAMER_MAX_ADAPTERS] = { 0, };
184
185module_param_array(ringspeed, int, NULL, 0);
186
187/* Packet buffer size */
188
189static int pkt_buf_sz[STREAMER_MAX_ADAPTERS] = { 0, };
190
191module_param_array(pkt_buf_sz, int, NULL, 0);
192
193/* Message Level */
194
195static int message_level[STREAMER_MAX_ADAPTERS] = { 1, };
196
197module_param_array(message_level, int, NULL, 0);
198
199#if STREAMER_IOCTL
200static int streamer_ioctl(struct net_device *, struct ifreq *, int);
201#endif
202
203static int streamer_reset(struct net_device *dev);
204static int streamer_open(struct net_device *dev);
205static int streamer_xmit(struct sk_buff *skb, struct net_device *dev);
206static int streamer_close(struct net_device *dev);
207static void streamer_set_rx_mode(struct net_device *dev);
208static irqreturn_t streamer_interrupt(int irq, void *dev_id,
209 struct pt_regs *regs);
210static struct net_device_stats *streamer_get_stats(struct net_device *dev);
211static int streamer_set_mac_address(struct net_device *dev, void *addr);
212static void streamer_arb_cmd(struct net_device *dev);
213static int streamer_change_mtu(struct net_device *dev, int mtu);
214static void streamer_srb_bh(struct net_device *dev);
215static void streamer_asb_bh(struct net_device *dev);
216#if STREAMER_NETWORK_MONITOR
217#ifdef CONFIG_PROC_FS
218static int streamer_proc_info(char *buffer, char **start, off_t offset,
219 int length, int *eof, void *data);
220static int sprintf_info(char *buffer, struct net_device *dev);
221struct streamer_private *dev_streamer=NULL;
222#endif
223#endif
224
225static int __devinit streamer_init_one(struct pci_dev *pdev,
226 const struct pci_device_id *ent)
227{
228 struct net_device *dev;
229 struct streamer_private *streamer_priv;
230 unsigned long pio_start, pio_end, pio_flags, pio_len;
231 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
232 int rc = 0;
233 static int card_no=-1;
234 u16 pcr;
235
236#if STREAMER_DEBUG
237 printk("lanstreamer::streamer_init_one, entry pdev %p\n",pdev);
238#endif
239
240 card_no++;
241 dev = alloc_trdev(sizeof(*streamer_priv));
242 if (dev==NULL) {
243 printk(KERN_ERR "lanstreamer: out of memory.\n");
244 return -ENOMEM;
245 }
246
247 SET_MODULE_OWNER(dev);
248 streamer_priv = dev->priv;
249
250#if STREAMER_NETWORK_MONITOR
251#ifdef CONFIG_PROC_FS
252 if (!dev_streamer)
253 create_proc_read_entry("net/streamer_tr", 0, 0,
254 streamer_proc_info, NULL);
255 streamer_priv->next = dev_streamer;
256 dev_streamer = streamer_priv;
257#endif
258#endif
259
260 rc = pci_set_dma_mask(pdev, 0xFFFFFFFFULL);
261 if (rc) {
262 printk(KERN_ERR "%s: No suitable PCI mapping available.\n",
263 dev->name);
264 rc = -ENODEV;
265 goto err_out;
266 }
267
268 rc = pci_enable_device(pdev);
269 if (rc) {
270 printk(KERN_ERR "lanstreamer: unable to enable pci device\n");
271 rc=-EIO;
272 goto err_out;
273 }
274
275 pci_set_master(pdev);
276
277 rc = pci_set_mwi(pdev);
278 if (rc) {
279 printk(KERN_ERR "lanstreamer: unable to enable MWI on pci device\n");
280 goto err_out_disable;
281 }
282
283 pio_start = pci_resource_start(pdev, 0);
284 pio_end = pci_resource_end(pdev, 0);
285 pio_flags = pci_resource_flags(pdev, 0);
286 pio_len = pci_resource_len(pdev, 0);
287
288 mmio_start = pci_resource_start(pdev, 1);
289 mmio_end = pci_resource_end(pdev, 1);
290 mmio_flags = pci_resource_flags(pdev, 1);
291 mmio_len = pci_resource_len(pdev, 1);
292
293#if STREAMER_DEBUG
294 printk("lanstreamer: pio_start %x pio_end %x pio_len %x pio_flags %x\n",
295 pio_start, pio_end, pio_len, pio_flags);
296 printk("lanstreamer: mmio_start %x mmio_end %x mmio_len %x mmio_flags %x\n",
297 mmio_start, mmio_end, mmio_flags, mmio_len);
298#endif
299
300 if (!request_region(pio_start, pio_len, "lanstreamer")) {
301 printk(KERN_ERR "lanstreamer: unable to get pci io addr %lx\n",
302 pio_start);
303 rc= -EBUSY;
304 goto err_out_mwi;
305 }
306
307 if (!request_mem_region(mmio_start, mmio_len, "lanstreamer")) {
308 printk(KERN_ERR "lanstreamer: unable to get pci mmio addr %lx\n",
309 mmio_start);
310 rc= -EBUSY;
311 goto err_out_free_pio;
312 }
313
314 streamer_priv->streamer_mmio=ioremap(mmio_start, mmio_len);
315 if (streamer_priv->streamer_mmio == NULL) {
316 printk(KERN_ERR "lanstreamer: unable to remap MMIO %lx\n",
317 mmio_start);
318 rc= -EIO;
319 goto err_out_free_mmio;
320 }
321
322 init_waitqueue_head(&streamer_priv->srb_wait);
323 init_waitqueue_head(&streamer_priv->trb_wait);
324
325 dev->open = &streamer_open;
326 dev->hard_start_xmit = &streamer_xmit;
327 dev->change_mtu = &streamer_change_mtu;
328 dev->stop = &streamer_close;
329#if STREAMER_IOCTL
330 dev->do_ioctl = &streamer_ioctl;
331#else
332 dev->do_ioctl = NULL;
333#endif
334 dev->set_multicast_list = &streamer_set_rx_mode;
335 dev->get_stats = &streamer_get_stats;
336 dev->set_mac_address = &streamer_set_mac_address;
337 dev->irq = pdev->irq;
338 dev->base_addr=pio_start;
339 SET_NETDEV_DEV(dev, &pdev->dev);
340
341 streamer_priv->streamer_card_name = (char *)pdev->resource[0].name;
342 streamer_priv->pci_dev = pdev;
343
344 if ((pkt_buf_sz[card_no] < 100) || (pkt_buf_sz[card_no] > 18000))
345 streamer_priv->pkt_buf_sz = PKT_BUF_SZ;
346 else
347 streamer_priv->pkt_buf_sz = pkt_buf_sz[card_no];
348
349 streamer_priv->streamer_ring_speed = ringspeed[card_no];
350 streamer_priv->streamer_message_level = message_level[card_no];
351
352 pci_set_drvdata(pdev, dev);
353
354 spin_lock_init(&streamer_priv->streamer_lock);
355
356 pci_read_config_word (pdev, PCI_COMMAND, &pcr);
357 pcr |= PCI_COMMAND_SERR;
358 pci_write_config_word (pdev, PCI_COMMAND, pcr);
359
360 printk("%s \n", version);
361 printk("%s: %s. I/O at %hx, MMIO at %p, using irq %d\n",dev->name,
362 streamer_priv->streamer_card_name,
363 (unsigned int) dev->base_addr,
364 streamer_priv->streamer_mmio,
365 dev->irq);
366
367 if (streamer_reset(dev))
368 goto err_out_unmap;
369
370 rc = register_netdev(dev);
371 if (rc)
372 goto err_out_unmap;
373 return 0;
374
375err_out_unmap:
376 iounmap(streamer_priv->streamer_mmio);
377err_out_free_mmio:
378 release_mem_region(mmio_start, mmio_len);
379err_out_free_pio:
380 release_region(pio_start, pio_len);
381err_out_mwi:
382 pci_clear_mwi(pdev);
383err_out_disable:
384 pci_disable_device(pdev);
385err_out:
386 free_netdev(dev);
387#if STREAMER_DEBUG
388 printk("lanstreamer: Exit error %x\n",rc);
389#endif
390 return rc;
391}
392
393static void __devexit streamer_remove_one(struct pci_dev *pdev)
394{
395 struct net_device *dev=pci_get_drvdata(pdev);
396 struct streamer_private *streamer_priv;
397
398#if STREAMER_DEBUG
399 printk("lanstreamer::streamer_remove_one entry pdev %p\n",pdev);
400#endif
401
402 if (dev == NULL) {
403 printk(KERN_ERR "lanstreamer::streamer_remove_one, ERROR dev is NULL\n");
404 return;
405 }
406
407 streamer_priv=dev->priv;
408 if (streamer_priv == NULL) {
409 printk(KERN_ERR "lanstreamer::streamer_remove_one, ERROR dev->priv is NULL\n");
410 return;
411 }
412
413#if STREAMER_NETWORK_MONITOR
414#ifdef CONFIG_PROC_FS
415 {
416 struct streamer_private **p, **next;
417
418 for (p = &dev_streamer; *p; p = next) {
419 next = &(*p)->next;
420 if (*p == streamer_priv) {
421 *p = *next;
422 break;
423 }
424 }
425 if (!dev_streamer)
426 remove_proc_entry("net/streamer_tr", NULL);
427 }
428#endif
429#endif
430
431 unregister_netdev(dev);
432 iounmap(streamer_priv->streamer_mmio);
433 release_mem_region(pci_resource_start(pdev, 1), pci_resource_len(pdev,1));
434 release_region(pci_resource_start(pdev, 0), pci_resource_len(pdev,0));
435 pci_clear_mwi(pdev);
436 pci_disable_device(pdev);
437 free_netdev(dev);
438 pci_set_drvdata(pdev, NULL);
439}
440
441
442static int streamer_reset(struct net_device *dev)
443{
444 struct streamer_private *streamer_priv;
445 __u8 __iomem *streamer_mmio;
446 unsigned long t;
447 unsigned int uaa_addr;
448 struct sk_buff *skb = NULL;
449 __u16 misr;
450
451 streamer_priv = (struct streamer_private *) dev->priv;
452 streamer_mmio = streamer_priv->streamer_mmio;
453
454 writew(readw(streamer_mmio + BCTL) | BCTL_SOFTRESET, streamer_mmio + BCTL);
455 t = jiffies;
456 /* Hold soft reset bit for a while */
457 current->state = TASK_UNINTERRUPTIBLE;
458 schedule_timeout(HZ);
459
460 writew(readw(streamer_mmio + BCTL) & ~BCTL_SOFTRESET,
461 streamer_mmio + BCTL);
462
463#if STREAMER_DEBUG
464 printk("BCTL: %x\n", readw(streamer_mmio + BCTL));
465 printk("GPR: %x\n", readw(streamer_mmio + GPR));
466 printk("SISRMASK: %x\n", readw(streamer_mmio + SISR_MASK));
467#endif
468 writew(readw(streamer_mmio + BCTL) | (BCTL_RX_FIFO_8 | BCTL_TX_FIFO_8), streamer_mmio + BCTL );
469
470 if (streamer_priv->streamer_ring_speed == 0) { /* Autosense */
471 writew(readw(streamer_mmio + GPR) | GPR_AUTOSENSE,
472 streamer_mmio + GPR);
473 if (streamer_priv->streamer_message_level)
474 printk(KERN_INFO "%s: Ringspeed autosense mode on\n",
475 dev->name);
476 } else if (streamer_priv->streamer_ring_speed == 16) {
477 if (streamer_priv->streamer_message_level)
478 printk(KERN_INFO "%s: Trying to open at 16 Mbps as requested\n",
479 dev->name);
480 writew(GPR_16MBPS, streamer_mmio + GPR);
481 } else if (streamer_priv->streamer_ring_speed == 4) {
482 if (streamer_priv->streamer_message_level)
483 printk(KERN_INFO "%s: Trying to open at 4 Mbps as requested\n",
484 dev->name);
485 writew(0, streamer_mmio + GPR);
486 }
487
488 skb = dev_alloc_skb(streamer_priv->pkt_buf_sz);
489 if (!skb) {
490 printk(KERN_INFO "%s: skb allocation for diagnostics failed...proceeding\n",
491 dev->name);
492 } else {
493 struct streamer_rx_desc *rx_ring;
494 u8 *data;
495
496 rx_ring=(struct streamer_rx_desc *)skb->data;
497 data=((u8 *)skb->data)+sizeof(struct streamer_rx_desc);
498 rx_ring->forward=0;
499 rx_ring->status=0;
500 rx_ring->buffer=cpu_to_le32(pci_map_single(streamer_priv->pci_dev, data,
501 512, PCI_DMA_FROMDEVICE));
502 rx_ring->framelen_buflen=512;
503 writel(cpu_to_le32(pci_map_single(streamer_priv->pci_dev, rx_ring, 512, PCI_DMA_FROMDEVICE)),
504 streamer_mmio+RXBDA);
505 }
506
507#if STREAMER_DEBUG
508 printk("GPR = %x\n", readw(streamer_mmio + GPR));
509#endif
510 /* start solo init */
511 writew(SISR_MI, streamer_mmio + SISR_MASK_SUM);
512
513 while (!((readw(streamer_mmio + SISR)) & SISR_SRB_REPLY)) {
514 current->state = TASK_INTERRUPTIBLE;
515 schedule_timeout(HZ/10);
516 if (jiffies - t > 40 * HZ) {
517 printk(KERN_ERR
518 "IBM PCI tokenring card not responding\n");
519 release_region(dev->base_addr, STREAMER_IO_SPACE);
520 if (skb)
521 dev_kfree_skb(skb);
522 return -1;
523 }
524 }
525 writew(~SISR_SRB_REPLY, streamer_mmio + SISR_RUM);
526 misr = readw(streamer_mmio + MISR_RUM);
527 writew(~misr, streamer_mmio + MISR_RUM);
528
529 if (skb)
530 dev_kfree_skb(skb); /* release skb used for diagnostics */
531
532#if STREAMER_DEBUG
533 printk("LAPWWO: %x, LAPA: %x LAPE: %x\n",
534 readw(streamer_mmio + LAPWWO), readw(streamer_mmio + LAPA),
535 readw(streamer_mmio + LAPE));
536#endif
537
538#if STREAMER_DEBUG
539 {
540 int i;
541 writew(readw(streamer_mmio + LAPWWO),
542 streamer_mmio + LAPA);
543 printk("initialization response srb dump: ");
544 for (i = 0; i < 10; i++)
545 printk("%x:",
546 ntohs(readw(streamer_mmio + LAPDINC)));
547 printk("\n");
548 }
549#endif
550
551 writew(readw(streamer_mmio + LAPWWO) + 6, streamer_mmio + LAPA);
552 if (readw(streamer_mmio + LAPD)) {
553 printk(KERN_INFO "tokenring card initialization failed. errorcode : %x\n",
554 ntohs(readw(streamer_mmio + LAPD)));
555 release_region(dev->base_addr, STREAMER_IO_SPACE);
556 return -1;
557 }
558
559 writew(readw(streamer_mmio + LAPWWO) + 8, streamer_mmio + LAPA);
560 uaa_addr = ntohs(readw(streamer_mmio + LAPDINC));
561 readw(streamer_mmio + LAPDINC); /* skip over Level.Addr field */
562 streamer_priv->streamer_addr_table_addr = ntohs(readw(streamer_mmio + LAPDINC));
563 streamer_priv->streamer_parms_addr = ntohs(readw(streamer_mmio + LAPDINC));
564
565#if STREAMER_DEBUG
566 printk("UAA resides at %x\n", uaa_addr);
567#endif
568
569 /* setup uaa area for access with LAPD */
570 {
571 int i;
572 __u16 addr;
573 writew(uaa_addr, streamer_mmio + LAPA);
574 for (i = 0; i < 6; i += 2) {
575 addr=ntohs(readw(streamer_mmio+LAPDINC));
576 dev->dev_addr[i]= (addr >> 8) & 0xff;
577 dev->dev_addr[i+1]= addr & 0xff;
578 }
579#if STREAMER_DEBUG
580 printk("Adapter address: ");
581 for (i = 0; i < 6; i++) {
582 printk("%02x:", dev->dev_addr[i]);
583 }
584 printk("\n");
585#endif
586 }
587 return 0;
588}
589
590static int streamer_open(struct net_device *dev)
591{
592 struct streamer_private *streamer_priv = (struct streamer_private *) dev->priv;
593 __u8 __iomem *streamer_mmio = streamer_priv->streamer_mmio;
594 unsigned long flags;
595 char open_error[255];
596 int i, open_finished = 1;
597 __u16 srb_word;
598 __u16 srb_open;
599 int rc;
600
601 if (readw(streamer_mmio+BMCTL_SUM) & BMCTL_RX_ENABLED) {
602 rc=streamer_reset(dev);
603 }
604
605 if (request_irq(dev->irq, &streamer_interrupt, SA_SHIRQ, "lanstreamer", dev)) {
606 return -EAGAIN;
607 }
608#if STREAMER_DEBUG
609 printk("BMCTL: %x\n", readw(streamer_mmio + BMCTL_SUM));
610 printk("pending ints: %x\n", readw(streamer_mmio + SISR));
611#endif
612
613 writew(SISR_MI | SISR_SRB_REPLY, streamer_mmio + SISR_MASK); /* more ints later, doesn't stop arb cmd interrupt */
614 writew(LISR_LIE, streamer_mmio + LISR); /* more ints later */
615
616 /* adapter is closed, so SRB is pointed to by LAPWWO */
617 writew(readw(streamer_mmio + LAPWWO), streamer_mmio + LAPA);
618
619#if STREAMER_DEBUG
620 printk("LAPWWO: %x, LAPA: %x\n", readw(streamer_mmio + LAPWWO),
621 readw(streamer_mmio + LAPA));
622 printk("LAPE: %x\n", readw(streamer_mmio + LAPE));
623 printk("SISR Mask = %04x\n", readw(streamer_mmio + SISR_MASK));
624#endif
625 do {
626 int i;
627
628 for (i = 0; i < SRB_COMMAND_SIZE; i += 2) {
629 writew(0, streamer_mmio + LAPDINC);
630 }
631
632 writew(readw(streamer_mmio+LAPWWO),streamer_mmio+LAPA);
633 writew(htons(SRB_OPEN_ADAPTER<<8),streamer_mmio+LAPDINC) ; /* open */
634 writew(htons(STREAMER_CLEAR_RET_CODE<<8),streamer_mmio+LAPDINC);
635 writew(STREAMER_CLEAR_RET_CODE, streamer_mmio + LAPDINC);
636
637 writew(readw(streamer_mmio + LAPWWO) + 8, streamer_mmio + LAPA);
638#if STREAMER_NETWORK_MONITOR
639 /* If Network Monitor, instruct card to copy MAC frames through the ARB */
640 writew(htons(OPEN_ADAPTER_ENABLE_FDX | OPEN_ADAPTER_PASS_ADC_MAC | OPEN_ADAPTER_PASS_ATT_MAC | OPEN_ADAPTER_PASS_BEACON), streamer_mmio + LAPDINC); /* offset 8 word contains open options */
641#else
642 writew(htons(OPEN_ADAPTER_ENABLE_FDX), streamer_mmio + LAPDINC); /* Offset 8 word contains Open.Options */
643#endif
644
645 if (streamer_priv->streamer_laa[0]) {
646 writew(readw(streamer_mmio + LAPWWO) + 12, streamer_mmio + LAPA);
647 writew(htons((streamer_priv->streamer_laa[0] << 8) |
648 streamer_priv->streamer_laa[1]),streamer_mmio+LAPDINC);
649 writew(htons((streamer_priv->streamer_laa[2] << 8) |
650 streamer_priv->streamer_laa[3]),streamer_mmio+LAPDINC);
651 writew(htons((streamer_priv->streamer_laa[4] << 8) |
652 streamer_priv->streamer_laa[5]),streamer_mmio+LAPDINC);
653 memcpy(dev->dev_addr, streamer_priv->streamer_laa, dev->addr_len);
654 }
655
656 /* save off srb open offset */
657 srb_open = readw(streamer_mmio + LAPWWO);
658#if STREAMER_DEBUG
659 writew(readw(streamer_mmio + LAPWWO),
660 streamer_mmio + LAPA);
661 printk("srb open request: \n");
662 for (i = 0; i < 16; i++) {
663 printk("%x:", ntohs(readw(streamer_mmio + LAPDINC)));
664 }
665 printk("\n");
666#endif
667 spin_lock_irqsave(&streamer_priv->streamer_lock, flags);
668 streamer_priv->srb_queued = 1;
669
670 /* signal solo that SRB command has been issued */
671 writew(LISR_SRB_CMD, streamer_mmio + LISR_SUM);
672 spin_unlock_irqrestore(&streamer_priv->streamer_lock, flags);
673
674 while (streamer_priv->srb_queued) {
675 interruptible_sleep_on_timeout(&streamer_priv->srb_wait, 5 * HZ);
676 if (signal_pending(current)) {
677 printk(KERN_WARNING "%s: SRB timed out.\n", dev->name);
678 printk(KERN_WARNING "SISR=%x MISR=%x, LISR=%x\n",
679 readw(streamer_mmio + SISR),
680 readw(streamer_mmio + MISR_RUM),
681 readw(streamer_mmio + LISR));
682 streamer_priv->srb_queued = 0;
683 break;
684 }
685 }
686
687#if STREAMER_DEBUG
688 printk("SISR_MASK: %x\n", readw(streamer_mmio + SISR_MASK));
689 printk("srb open response:\n");
690 writew(srb_open, streamer_mmio + LAPA);
691 for (i = 0; i < 10; i++) {
692 printk("%x:",
693 ntohs(readw(streamer_mmio + LAPDINC)));
694 }
695#endif
696
697 /* If we get the same return response as we set, the interrupt wasn't raised and the open
698 * timed out.
699 */
700 writew(srb_open + 2, streamer_mmio + LAPA);
701 srb_word = ntohs(readw(streamer_mmio + LAPD)) >> 8;
702 if (srb_word == STREAMER_CLEAR_RET_CODE) {
703 printk(KERN_WARNING "%s: Adapter Open time out or error.\n",
704 dev->name);
705 return -EIO;
706 }
707
708 if (srb_word != 0) {
709 if (srb_word == 0x07) {
710 if (!streamer_priv->streamer_ring_speed && open_finished) { /* Autosense , first time around */
711 printk(KERN_WARNING "%s: Retrying at different ring speed \n",
712 dev->name);
713 open_finished = 0;
714 } else {
715 __u16 error_code;
716
717 writew(srb_open + 6, streamer_mmio + LAPA);
718 error_code = ntohs(readw(streamer_mmio + LAPD));
719 strcpy(open_error, open_maj_error[(error_code & 0xf0) >> 4]);
720 strcat(open_error, " - ");
721 strcat(open_error, open_min_error[(error_code & 0x0f)]);
722
723 if (!streamer_priv->streamer_ring_speed
724 && ((error_code & 0x0f) == 0x0d))
725 {
726 printk(KERN_WARNING "%s: Tried to autosense ring speed with no monitors present\n", dev->name);
727 printk(KERN_WARNING "%s: Please try again with a specified ring speed \n", dev->name);
728 free_irq(dev->irq, dev);
729 return -EIO;
730 }
731
732 printk(KERN_WARNING "%s: %s\n",
733 dev->name, open_error);
734 free_irq(dev->irq, dev);
735 return -EIO;
736
737 } /* if autosense && open_finished */
738 } else {
739 printk(KERN_WARNING "%s: Bad OPEN response: %x\n",
740 dev->name, srb_word);
741 free_irq(dev->irq, dev);
742 return -EIO;
743 }
744 } else
745 open_finished = 1;
746 } while (!(open_finished)); /* Will only loop if ring speed mismatch re-open attempted && autosense is on */
747
748 writew(srb_open + 18, streamer_mmio + LAPA);
749 srb_word=ntohs(readw(streamer_mmio+LAPD)) >> 8;
750 if (srb_word & (1 << 3))
751 if (streamer_priv->streamer_message_level)
752 printk(KERN_INFO "%s: Opened in FDX Mode\n", dev->name);
753
754 if (srb_word & 1)
755 streamer_priv->streamer_ring_speed = 16;
756 else
757 streamer_priv->streamer_ring_speed = 4;
758
759 if (streamer_priv->streamer_message_level)
760 printk(KERN_INFO "%s: Opened in %d Mbps mode\n",
761 dev->name,
762 streamer_priv->streamer_ring_speed);
763
764 writew(srb_open + 8, streamer_mmio + LAPA);
765 streamer_priv->asb = ntohs(readw(streamer_mmio + LAPDINC));
766 streamer_priv->srb = ntohs(readw(streamer_mmio + LAPDINC));
767 streamer_priv->arb = ntohs(readw(streamer_mmio + LAPDINC));
768 readw(streamer_mmio + LAPDINC); /* offset 14 word is rsvd */
769 streamer_priv->trb = ntohs(readw(streamer_mmio + LAPDINC));
770
771 streamer_priv->streamer_receive_options = 0x00;
772 streamer_priv->streamer_copy_all_options = 0;
773
774 /* setup rx ring */
775 /* enable rx channel */
776 writew(~BMCTL_RX_DIS, streamer_mmio + BMCTL_RUM);
777
778 /* setup rx descriptors */
779 streamer_priv->streamer_rx_ring=
780 kmalloc( sizeof(struct streamer_rx_desc)*
781 STREAMER_RX_RING_SIZE,GFP_KERNEL);
782 if (!streamer_priv->streamer_rx_ring) {
783 printk(KERN_WARNING "%s ALLOC of streamer rx ring FAILED!!\n",dev->name);
784 return -EIO;
785 }
786
787 for (i = 0; i < STREAMER_RX_RING_SIZE; i++) {
788 struct sk_buff *skb;
789
790 skb = dev_alloc_skb(streamer_priv->pkt_buf_sz);
791 if (skb == NULL)
792 break;
793
794 skb->dev = dev;
795
796 streamer_priv->streamer_rx_ring[i].forward =
797 cpu_to_le32(pci_map_single(streamer_priv->pci_dev, &streamer_priv->streamer_rx_ring[i + 1],
798 sizeof(struct streamer_rx_desc), PCI_DMA_FROMDEVICE));
799 streamer_priv->streamer_rx_ring[i].status = 0;
800 streamer_priv->streamer_rx_ring[i].buffer =
801 cpu_to_le32(pci_map_single(streamer_priv->pci_dev, skb->data,
802 streamer_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE));
803 streamer_priv->streamer_rx_ring[i].framelen_buflen = streamer_priv->pkt_buf_sz;
804 streamer_priv->rx_ring_skb[i] = skb;
805 }
806 streamer_priv->streamer_rx_ring[STREAMER_RX_RING_SIZE - 1].forward =
807 cpu_to_le32(pci_map_single(streamer_priv->pci_dev, &streamer_priv->streamer_rx_ring[0],
808 sizeof(struct streamer_rx_desc), PCI_DMA_FROMDEVICE));
809
810 if (i == 0) {
811 printk(KERN_WARNING "%s: Not enough memory to allocate rx buffers. Adapter disabled\n", dev->name);
812 free_irq(dev->irq, dev);
813 return -EIO;
814 }
815
816 streamer_priv->rx_ring_last_received = STREAMER_RX_RING_SIZE - 1; /* last processed rx status */
817
818 writel(cpu_to_le32(pci_map_single(streamer_priv->pci_dev, &streamer_priv->streamer_rx_ring[0],
819 sizeof(struct streamer_rx_desc), PCI_DMA_TODEVICE)),
820 streamer_mmio + RXBDA);
821 writel(cpu_to_le32(pci_map_single(streamer_priv->pci_dev, &streamer_priv->streamer_rx_ring[STREAMER_RX_RING_SIZE - 1],
822 sizeof(struct streamer_rx_desc), PCI_DMA_TODEVICE)),
823 streamer_mmio + RXLBDA);
824
825 /* set bus master interrupt event mask */
826 writew(MISR_RX_NOBUF | MISR_RX_EOF, streamer_mmio + MISR_MASK);
827
828
829 /* setup tx ring */
830 streamer_priv->streamer_tx_ring=kmalloc(sizeof(struct streamer_tx_desc)*
831 STREAMER_TX_RING_SIZE,GFP_KERNEL);
832 if (!streamer_priv->streamer_tx_ring) {
833 printk(KERN_WARNING "%s ALLOC of streamer_tx_ring FAILED\n",dev->name);
834 return -EIO;
835 }
836
837 writew(~BMCTL_TX2_DIS, streamer_mmio + BMCTL_RUM); /* Enables TX channel 2 */
838 for (i = 0; i < STREAMER_TX_RING_SIZE; i++) {
839 streamer_priv->streamer_tx_ring[i].forward = cpu_to_le32(pci_map_single(streamer_priv->pci_dev,
840 &streamer_priv->streamer_tx_ring[i + 1],
841 sizeof(struct streamer_tx_desc),
842 PCI_DMA_TODEVICE));
843 streamer_priv->streamer_tx_ring[i].status = 0;
844 streamer_priv->streamer_tx_ring[i].bufcnt_framelen = 0;
845 streamer_priv->streamer_tx_ring[i].buffer = 0;
846 streamer_priv->streamer_tx_ring[i].buflen = 0;
847 streamer_priv->streamer_tx_ring[i].rsvd1 = 0;
848 streamer_priv->streamer_tx_ring[i].rsvd2 = 0;
849 streamer_priv->streamer_tx_ring[i].rsvd3 = 0;
850 }
851 streamer_priv->streamer_tx_ring[STREAMER_TX_RING_SIZE - 1].forward =
852 cpu_to_le32(pci_map_single(streamer_priv->pci_dev, &streamer_priv->streamer_tx_ring[0],
853 sizeof(struct streamer_tx_desc), PCI_DMA_TODEVICE));
854
855 streamer_priv->free_tx_ring_entries = STREAMER_TX_RING_SIZE;
856 streamer_priv->tx_ring_free = 0; /* next entry in tx ring to use */
857 streamer_priv->tx_ring_last_status = STREAMER_TX_RING_SIZE - 1;
858
859 /* set Busmaster interrupt event mask (handle receives on interrupt only */
860 writew(MISR_TX2_EOF | MISR_RX_NOBUF | MISR_RX_EOF, streamer_mmio + MISR_MASK);
861 /* set system event interrupt mask */
862 writew(SISR_ADAPTER_CHECK | SISR_ARB_CMD | SISR_TRB_REPLY | SISR_ASB_FREE, streamer_mmio + SISR_MASK_SUM);
863
864#if STREAMER_DEBUG
865 printk("BMCTL: %x\n", readw(streamer_mmio + BMCTL_SUM));
866 printk("SISR MASK: %x\n", readw(streamer_mmio + SISR_MASK));
867#endif
868
869#if STREAMER_NETWORK_MONITOR
870
871 writew(streamer_priv->streamer_addr_table_addr, streamer_mmio + LAPA);
872 printk("%s: Node Address: %04x:%04x:%04x\n", dev->name,
873 ntohs(readw(streamer_mmio + LAPDINC)),
874 ntohs(readw(streamer_mmio + LAPDINC)),
875 ntohs(readw(streamer_mmio + LAPDINC)));
876 readw(streamer_mmio + LAPDINC);
877 readw(streamer_mmio + LAPDINC);
878 printk("%s: Functional Address: %04x:%04x\n", dev->name,
879 ntohs(readw(streamer_mmio + LAPDINC)),
880 ntohs(readw(streamer_mmio + LAPDINC)));
881
882 writew(streamer_priv->streamer_parms_addr + 4,
883 streamer_mmio + LAPA);
884 printk("%s: NAUN Address: %04x:%04x:%04x\n", dev->name,
885 ntohs(readw(streamer_mmio + LAPDINC)),
886 ntohs(readw(streamer_mmio + LAPDINC)),
887 ntohs(readw(streamer_mmio + LAPDINC)));
888#endif
889
890 netif_start_queue(dev);
891 netif_carrier_on(dev);
892 return 0;
893}
894
895/*
896 * When we enter the rx routine we do not know how many frames have been
897 * queued on the rx channel. Therefore we start at the next rx status
898 * position and travel around the receive ring until we have completed
899 * all the frames.
900 *
901 * This means that we may process the frame before we receive the end
902 * of frame interrupt. This is why we always test the status instead
903 * of blindly processing the next frame.
904 *
905 */
906static void streamer_rx(struct net_device *dev)
907{
908 struct streamer_private *streamer_priv =
909 (struct streamer_private *) dev->priv;
910 __u8 __iomem *streamer_mmio = streamer_priv->streamer_mmio;
911 struct streamer_rx_desc *rx_desc;
912 int rx_ring_last_received, length, frame_length, buffer_cnt = 0;
913 struct sk_buff *skb, *skb2;
914
915 /* setup the next rx descriptor to be received */
916 rx_desc = &streamer_priv->streamer_rx_ring[(streamer_priv->rx_ring_last_received + 1) & (STREAMER_RX_RING_SIZE - 1)];
917 rx_ring_last_received = streamer_priv->rx_ring_last_received;
918
919 while (rx_desc->status & 0x01000000) { /* While processed descriptors are available */
920 if (rx_ring_last_received != streamer_priv->rx_ring_last_received)
921 {
922 printk(KERN_WARNING "RX Error 1 rx_ring_last_received not the same %x %x\n",
923 rx_ring_last_received, streamer_priv->rx_ring_last_received);
924 }
925 streamer_priv->rx_ring_last_received = (streamer_priv->rx_ring_last_received + 1) & (STREAMER_RX_RING_SIZE - 1);
926 rx_ring_last_received = streamer_priv->rx_ring_last_received;
927
928 length = rx_desc->framelen_buflen & 0xffff; /* buffer length */
929 frame_length = (rx_desc->framelen_buflen >> 16) & 0xffff;
930
931 if (rx_desc->status & 0x7E830000) { /* errors */
932 if (streamer_priv->streamer_message_level) {
933 printk(KERN_WARNING "%s: Rx Error %x \n",
934 dev->name, rx_desc->status);
935 }
936 } else { /* received without errors */
937 if (rx_desc->status & 0x80000000) { /* frame complete */
938 buffer_cnt = 1;
939 skb = dev_alloc_skb(streamer_priv->pkt_buf_sz);
940 } else {
941 skb = dev_alloc_skb(frame_length);
942 }
943
944 if (skb == NULL)
945 {
946 printk(KERN_WARNING "%s: Not enough memory to copy packet to upper layers. \n", dev->name);
947 streamer_priv->streamer_stats.rx_dropped++;
948 } else { /* we allocated an skb OK */
949 skb->dev = dev;
950
951 if (buffer_cnt == 1) {
952 /* release the DMA mapping */
953 pci_unmap_single(streamer_priv->pci_dev,
954 le32_to_cpu(streamer_priv->streamer_rx_ring[rx_ring_last_received].buffer),
955 streamer_priv->pkt_buf_sz,
956 PCI_DMA_FROMDEVICE);
957 skb2 = streamer_priv->rx_ring_skb[rx_ring_last_received];
958#if STREAMER_DEBUG_PACKETS
959 {
960 int i;
961 printk("streamer_rx packet print: skb->data2 %p skb->head %p\n", skb2->data, skb2->head);
962 for (i = 0; i < frame_length; i++)
963 {
964 printk("%x:", skb2->data[i]);
965 if (((i + 1) % 16) == 0)
966 printk("\n");
967 }
968 printk("\n");
969 }
970#endif
971 skb_put(skb2, length);
972 skb2->protocol = tr_type_trans(skb2, dev);
973 /* recycle this descriptor */
974 streamer_priv->streamer_rx_ring[rx_ring_last_received].status = 0;
975 streamer_priv->streamer_rx_ring[rx_ring_last_received].framelen_buflen = streamer_priv->pkt_buf_sz;
976 streamer_priv->streamer_rx_ring[rx_ring_last_received].buffer =
977 cpu_to_le32(pci_map_single(streamer_priv->pci_dev, skb->data, streamer_priv->pkt_buf_sz,
978 PCI_DMA_FROMDEVICE));
979 streamer_priv->rx_ring_skb[rx_ring_last_received] = skb;
980 /* place recycled descriptor back on the adapter */
981 writel(cpu_to_le32(pci_map_single(streamer_priv->pci_dev,
982 &streamer_priv->streamer_rx_ring[rx_ring_last_received],
983 sizeof(struct streamer_rx_desc), PCI_DMA_FROMDEVICE)),
984 streamer_mmio + RXLBDA);
985 /* pass the received skb up to the protocol */
986 netif_rx(skb2);
987 } else {
988 do { /* Walk the buffers */
989 pci_unmap_single(streamer_priv->pci_dev, le32_to_cpu(rx_desc->buffer), length, PCI_DMA_FROMDEVICE),
990 memcpy(skb_put(skb, length), (void *)rx_desc->buffer, length); /* copy this fragment */
991 streamer_priv->streamer_rx_ring[rx_ring_last_received].status = 0;
992 streamer_priv->streamer_rx_ring[rx_ring_last_received].framelen_buflen = streamer_priv->pkt_buf_sz;
993
994 /* give descriptor back to the adapter */
995 writel(cpu_to_le32(pci_map_single(streamer_priv->pci_dev,
996 &streamer_priv->streamer_rx_ring[rx_ring_last_received],
997 length, PCI_DMA_FROMDEVICE)),
998 streamer_mmio + RXLBDA);
999
1000 if (rx_desc->status & 0x80000000)
1001 break; /* this descriptor completes the frame */
1002
1003 /* else get the next pending descriptor */
1004 if (rx_ring_last_received!= streamer_priv->rx_ring_last_received)
1005 {
1006 printk("RX Error rx_ring_last_received not the same %x %x\n",
1007 rx_ring_last_received,
1008 streamer_priv->rx_ring_last_received);
1009 }
1010 rx_desc = &streamer_priv->streamer_rx_ring[(streamer_priv->rx_ring_last_received+1) & (STREAMER_RX_RING_SIZE-1)];
1011
1012 length = rx_desc->framelen_buflen & 0xffff; /* buffer length */
1013 streamer_priv->rx_ring_last_received = (streamer_priv->rx_ring_last_received+1) & (STREAMER_RX_RING_SIZE - 1);
1014 rx_ring_last_received = streamer_priv->rx_ring_last_received;
1015 } while (1);
1016
1017 skb->protocol = tr_type_trans(skb, dev);
1018 /* send up to the protocol */
1019 netif_rx(skb);
1020 }
1021 dev->last_rx = jiffies;
1022 streamer_priv->streamer_stats.rx_packets++;
1023 streamer_priv->streamer_stats.rx_bytes += length;
1024 } /* if skb == null */
1025 } /* end received without errors */
1026
1027 /* try the next one */
1028 rx_desc = &streamer_priv->streamer_rx_ring[(rx_ring_last_received + 1) & (STREAMER_RX_RING_SIZE - 1)];
1029 } /* end for all completed rx descriptors */
1030}
1031
1032static irqreturn_t streamer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1033{
1034 struct net_device *dev = (struct net_device *) dev_id;
1035 struct streamer_private *streamer_priv =
1036 (struct streamer_private *) dev->priv;
1037 __u8 __iomem *streamer_mmio = streamer_priv->streamer_mmio;
1038 __u16 sisr;
1039 __u16 misr;
1040 u8 max_intr = MAX_INTR;
1041
1042 spin_lock(&streamer_priv->streamer_lock);
1043 sisr = readw(streamer_mmio + SISR);
1044
1045 while((sisr & (SISR_MI | SISR_SRB_REPLY | SISR_ADAPTER_CHECK | SISR_ASB_FREE |
1046 SISR_ARB_CMD | SISR_TRB_REPLY | SISR_PAR_ERR | SISR_SERR_ERR))
1047 && (max_intr > 0)) {
1048
1049 if(sisr & SISR_PAR_ERR) {
1050 writew(~SISR_PAR_ERR, streamer_mmio + SISR_RUM);
1051 (void)readw(streamer_mmio + SISR_RUM);
1052 }
1053
1054 else if(sisr & SISR_SERR_ERR) {
1055 writew(~SISR_SERR_ERR, streamer_mmio + SISR_RUM);
1056 (void)readw(streamer_mmio + SISR_RUM);
1057 }
1058
1059 else if(sisr & SISR_MI) {
1060 misr = readw(streamer_mmio + MISR_RUM);
1061
1062 if (misr & MISR_TX2_EOF) {
1063 while(streamer_priv->streamer_tx_ring[(streamer_priv->tx_ring_last_status + 1) & (STREAMER_TX_RING_SIZE - 1)].status) {
1064 streamer_priv->tx_ring_last_status = (streamer_priv->tx_ring_last_status + 1) & (STREAMER_TX_RING_SIZE - 1);
1065 streamer_priv->free_tx_ring_entries++;
1066 streamer_priv->streamer_stats.tx_bytes += streamer_priv->tx_ring_skb[streamer_priv->tx_ring_last_status]->len;
1067 streamer_priv->streamer_stats.tx_packets++;
1068 dev_kfree_skb_irq(streamer_priv->tx_ring_skb[streamer_priv->tx_ring_last_status]);
1069 streamer_priv->streamer_tx_ring[streamer_priv->tx_ring_last_status].buffer = 0xdeadbeef;
1070 streamer_priv->streamer_tx_ring[streamer_priv->tx_ring_last_status].status = 0;
1071 streamer_priv->streamer_tx_ring[streamer_priv->tx_ring_last_status].bufcnt_framelen = 0;
1072 streamer_priv->streamer_tx_ring[streamer_priv->tx_ring_last_status].buflen = 0;
1073 streamer_priv->streamer_tx_ring[streamer_priv->tx_ring_last_status].rsvd1 = 0;
1074 streamer_priv->streamer_tx_ring[streamer_priv->tx_ring_last_status].rsvd2 = 0;
1075 streamer_priv->streamer_tx_ring[streamer_priv->tx_ring_last_status].rsvd3 = 0;
1076 }
1077 netif_wake_queue(dev);
1078 }
1079
1080 if (misr & MISR_RX_EOF) {
1081 streamer_rx(dev);
1082 }
1083 /* MISR_RX_EOF */
1084
1085 if (misr & MISR_RX_NOBUF) {
1086 /* According to the documentation, we don't have to do anything,
1087 * but trapping it keeps it out of /var/log/messages.
1088 */
1089 } /* SISR_RX_NOBUF */
1090
1091 writew(~misr, streamer_mmio + MISR_RUM);
1092 (void)readw(streamer_mmio + MISR_RUM);
1093 }
1094
1095 else if (sisr & SISR_SRB_REPLY) {
1096 if (streamer_priv->srb_queued == 1) {
1097 wake_up_interruptible(&streamer_priv->srb_wait);
1098 } else if (streamer_priv->srb_queued == 2) {
1099 streamer_srb_bh(dev);
1100 }
1101 streamer_priv->srb_queued = 0;
1102
1103 writew(~SISR_SRB_REPLY, streamer_mmio + SISR_RUM);
1104 (void)readw(streamer_mmio + SISR_RUM);
1105 }
1106
1107 else if (sisr & SISR_ADAPTER_CHECK) {
1108 printk(KERN_WARNING "%s: Adapter Check Interrupt Raised, 8 bytes of information follow:\n", dev->name);
1109 writel(readl(streamer_mmio + LAPWWO), streamer_mmio + LAPA);
1110 printk(KERN_WARNING "%s: Words %x:%x:%x:%x:\n",
1111 dev->name, readw(streamer_mmio + LAPDINC),
1112 ntohs(readw(streamer_mmio + LAPDINC)),
1113 ntohs(readw(streamer_mmio + LAPDINC)),
1114 ntohs(readw(streamer_mmio + LAPDINC)));
1115 netif_stop_queue(dev);
1116 netif_carrier_off(dev);
1117 printk(KERN_WARNING "%s: Adapter must be manually reset.\n", dev->name);
1118 }
1119
1120 /* SISR_ADAPTER_CHECK */
1121 else if (sisr & SISR_ASB_FREE) {
1122 /* Wake up anything that is waiting for the asb response */
1123 if (streamer_priv->asb_queued) {
1124 streamer_asb_bh(dev);
1125 }
1126 writew(~SISR_ASB_FREE, streamer_mmio + SISR_RUM);
1127 (void)readw(streamer_mmio + SISR_RUM);
1128 }
1129 /* SISR_ASB_FREE */
1130 else if (sisr & SISR_ARB_CMD) {
1131 streamer_arb_cmd(dev);
1132 writew(~SISR_ARB_CMD, streamer_mmio + SISR_RUM);
1133 (void)readw(streamer_mmio + SISR_RUM);
1134 }
1135 /* SISR_ARB_CMD */
1136 else if (sisr & SISR_TRB_REPLY) {
1137 /* Wake up anything that is waiting for the trb response */
1138 if (streamer_priv->trb_queued) {
1139 wake_up_interruptible(&streamer_priv->
1140 trb_wait);
1141 }
1142 streamer_priv->trb_queued = 0;
1143 writew(~SISR_TRB_REPLY, streamer_mmio + SISR_RUM);
1144 (void)readw(streamer_mmio + SISR_RUM);
1145 }
1146 /* SISR_TRB_REPLY */
1147
1148 sisr = readw(streamer_mmio + SISR);
1149 max_intr--;
1150 } /* while() */
1151
1152 spin_unlock(&streamer_priv->streamer_lock) ;
1153 return IRQ_HANDLED;
1154}
1155
1156static int streamer_xmit(struct sk_buff *skb, struct net_device *dev)
1157{
1158 struct streamer_private *streamer_priv =
1159 (struct streamer_private *) dev->priv;
1160 __u8 __iomem *streamer_mmio = streamer_priv->streamer_mmio;
1161 unsigned long flags ;
1162
1163 spin_lock_irqsave(&streamer_priv->streamer_lock, flags);
1164
1165 if (streamer_priv->free_tx_ring_entries) {
1166 streamer_priv->streamer_tx_ring[streamer_priv->tx_ring_free].status = 0;
1167 streamer_priv->streamer_tx_ring[streamer_priv->tx_ring_free].bufcnt_framelen = 0x00020000 | skb->len;
1168 streamer_priv->streamer_tx_ring[streamer_priv->tx_ring_free].buffer =
1169 cpu_to_le32(pci_map_single(streamer_priv->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE));
1170 streamer_priv->streamer_tx_ring[streamer_priv->tx_ring_free].rsvd1 = skb->len;
1171 streamer_priv->streamer_tx_ring[streamer_priv->tx_ring_free].rsvd2 = 0;
1172 streamer_priv->streamer_tx_ring[streamer_priv->tx_ring_free].rsvd3 = 0;
1173 streamer_priv->streamer_tx_ring[streamer_priv->tx_ring_free].buflen = skb->len;
1174
1175 streamer_priv->tx_ring_skb[streamer_priv->tx_ring_free] = skb;
1176 streamer_priv->free_tx_ring_entries--;
1177#if STREAMER_DEBUG_PACKETS
1178 {
1179 int i;
1180 printk("streamer_xmit packet print:\n");
1181 for (i = 0; i < skb->len; i++) {
1182 printk("%x:", skb->data[i]);
1183 if (((i + 1) % 16) == 0)
1184 printk("\n");
1185 }
1186 printk("\n");
1187 }
1188#endif
1189
1190 writel(cpu_to_le32(pci_map_single(streamer_priv->pci_dev,
1191 &streamer_priv->streamer_tx_ring[streamer_priv->tx_ring_free],
1192 sizeof(struct streamer_tx_desc), PCI_DMA_TODEVICE)),
1193 streamer_mmio + TX2LFDA);
1194 (void)readl(streamer_mmio + TX2LFDA);
1195
1196 streamer_priv->tx_ring_free = (streamer_priv->tx_ring_free + 1) & (STREAMER_TX_RING_SIZE - 1);
1197 spin_unlock_irqrestore(&streamer_priv->streamer_lock,flags);
1198 return 0;
1199 } else {
1200 netif_stop_queue(dev);
1201 spin_unlock_irqrestore(&streamer_priv->streamer_lock,flags);
1202 return 1;
1203 }
1204}
1205
1206
1207static int streamer_close(struct net_device *dev)
1208{
1209 struct streamer_private *streamer_priv =
1210 (struct streamer_private *) dev->priv;
1211 __u8 __iomem *streamer_mmio = streamer_priv->streamer_mmio;
1212 unsigned long flags;
1213 int i;
1214
1215 netif_stop_queue(dev);
1216 netif_carrier_off(dev);
1217 writew(streamer_priv->srb, streamer_mmio + LAPA);
1218 writew(htons(SRB_CLOSE_ADAPTER << 8),streamer_mmio+LAPDINC);
1219 writew(htons(STREAMER_CLEAR_RET_CODE << 8), streamer_mmio+LAPDINC);
1220
1221 spin_lock_irqsave(&streamer_priv->streamer_lock, flags);
1222
1223 streamer_priv->srb_queued = 1;
1224 writew(LISR_SRB_CMD, streamer_mmio + LISR_SUM);
1225
1226 spin_unlock_irqrestore(&streamer_priv->streamer_lock, flags);
1227
1228 while (streamer_priv->srb_queued)
1229 {
1230 interruptible_sleep_on_timeout(&streamer_priv->srb_wait,
1231 jiffies + 60 * HZ);
1232 if (signal_pending(current))
1233 {
1234 printk(KERN_WARNING "%s: SRB timed out.\n", dev->name);
1235 printk(KERN_WARNING "SISR=%x MISR=%x LISR=%x\n",
1236 readw(streamer_mmio + SISR),
1237 readw(streamer_mmio + MISR_RUM),
1238 readw(streamer_mmio + LISR));
1239 streamer_priv->srb_queued = 0;
1240 break;
1241 }
1242 }
1243
1244 streamer_priv->rx_ring_last_received = (streamer_priv->rx_ring_last_received + 1) & (STREAMER_RX_RING_SIZE - 1);
1245
1246 for (i = 0; i < STREAMER_RX_RING_SIZE; i++) {
1247 if (streamer_priv->rx_ring_skb[streamer_priv->rx_ring_last_received]) {
1248 dev_kfree_skb(streamer_priv->rx_ring_skb[streamer_priv->rx_ring_last_received]);
1249 }
1250 streamer_priv->rx_ring_last_received = (streamer_priv->rx_ring_last_received + 1) & (STREAMER_RX_RING_SIZE - 1);
1251 }
1252
1253 /* reset tx/rx fifo's and busmaster logic */
1254
1255 /* TBD. Add graceful way to reset the LLC channel without doing a soft reset.
1256 writel(readl(streamer_mmio+BCTL)|(3<<13),streamer_mmio+BCTL);
1257 udelay(1);
1258 writel(readl(streamer_mmio+BCTL)&~(3<<13),streamer_mmio+BCTL);
1259 */
1260
1261#if STREAMER_DEBUG
1262 writew(streamer_priv->srb, streamer_mmio + LAPA);
1263 printk("srb): ");
1264 for (i = 0; i < 2; i++) {
1265 printk("%x ", ntohs(readw(streamer_mmio + LAPDINC)));
1266 }
1267 printk("\n");
1268#endif
1269 free_irq(dev->irq, dev);
1270 return 0;
1271}
1272
1273static void streamer_set_rx_mode(struct net_device *dev)
1274{
1275 struct streamer_private *streamer_priv =
1276 (struct streamer_private *) dev->priv;
1277 __u8 __iomem *streamer_mmio = streamer_priv->streamer_mmio;
1278 __u8 options = 0;
1279 struct dev_mc_list *dmi;
1280 unsigned char dev_mc_address[5];
1281 int i;
1282
1283 writel(streamer_priv->srb, streamer_mmio + LAPA);
1284 options = streamer_priv->streamer_copy_all_options;
1285
1286 if (dev->flags & IFF_PROMISC)
1287 options |= (3 << 5); /* All LLC and MAC frames, all through the main rx channel */
1288 else
1289 options &= ~(3 << 5);
1290
1291 /* Only issue the srb if there is a change in options */
1292
1293 if ((options ^ streamer_priv->streamer_copy_all_options))
1294 {
1295 /* Now to issue the srb command to alter the copy.all.options */
1296 writew(htons(SRB_MODIFY_RECEIVE_OPTIONS << 8), streamer_mmio+LAPDINC);
1297 writew(htons(STREAMER_CLEAR_RET_CODE << 8), streamer_mmio+LAPDINC);
1298 writew(htons((streamer_priv->streamer_receive_options << 8) | options),streamer_mmio+LAPDINC);
1299 writew(htons(0x4a41),streamer_mmio+LAPDINC);
1300 writew(htons(0x4d45),streamer_mmio+LAPDINC);
1301 writew(htons(0x5320),streamer_mmio+LAPDINC);
1302 writew(0x2020, streamer_mmio + LAPDINC);
1303
1304 streamer_priv->srb_queued = 2; /* Can't sleep, use srb_bh */
1305
1306 writel(LISR_SRB_CMD, streamer_mmio + LISR_SUM);
1307
1308 streamer_priv->streamer_copy_all_options = options;
1309 return;
1310 }
1311
1312 /* Set the functional addresses we need for multicast */
1313 writel(streamer_priv->srb,streamer_mmio+LAPA);
1314 dev_mc_address[0] = dev_mc_address[1] = dev_mc_address[2] = dev_mc_address[3] = 0 ;
1315
1316 for (i=0,dmi=dev->mc_list;i < dev->mc_count; i++,dmi = dmi->next)
1317 {
1318 dev_mc_address[0] |= dmi->dmi_addr[2] ;
1319 dev_mc_address[1] |= dmi->dmi_addr[3] ;
1320 dev_mc_address[2] |= dmi->dmi_addr[4] ;
1321 dev_mc_address[3] |= dmi->dmi_addr[5] ;
1322 }
1323
1324 writew(htons(SRB_SET_FUNC_ADDRESS << 8),streamer_mmio+LAPDINC);
1325 writew(htons(STREAMER_CLEAR_RET_CODE << 8), streamer_mmio+LAPDINC);
1326 writew(0,streamer_mmio+LAPDINC);
1327 writew(htons( (dev_mc_address[0] << 8) | dev_mc_address[1]),streamer_mmio+LAPDINC);
1328 writew(htons( (dev_mc_address[2] << 8) | dev_mc_address[3]),streamer_mmio+LAPDINC);
1329 streamer_priv->srb_queued = 2 ;
1330 writel(LISR_SRB_CMD,streamer_mmio+LISR_SUM);
1331}
1332
1333static void streamer_srb_bh(struct net_device *dev)
1334{
1335 struct streamer_private *streamer_priv = (struct streamer_private *) dev->priv;
1336 __u8 __iomem *streamer_mmio = streamer_priv->streamer_mmio;
1337 __u16 srb_word;
1338
1339 writew(streamer_priv->srb, streamer_mmio + LAPA);
1340 srb_word=ntohs(readw(streamer_mmio+LAPDINC)) >> 8;
1341
1342 switch (srb_word) {
1343
1344 /* SRB_MODIFY_RECEIVE_OPTIONS i.e. set_multicast_list options (promiscuous)
1345 * At some point we should do something if we get an error, such as
1346 * resetting the IFF_PROMISC flag in dev
1347 */
1348
1349 case SRB_MODIFY_RECEIVE_OPTIONS:
1350 srb_word=ntohs(readw(streamer_mmio+LAPDINC)) >> 8;
1351
1352 switch (srb_word) {
1353 case 0x01:
1354 printk(KERN_WARNING "%s: Unrecognized srb command\n", dev->name);
1355 break;
1356 case 0x04:
1357 printk(KERN_WARNING "%s: Adapter must be open for this operation, doh!!\n", dev->name);
1358 break;
1359 default:
1360 if (streamer_priv->streamer_message_level)
1361 printk(KERN_WARNING "%s: Receive Options Modified to %x,%x\n",
1362 dev->name,
1363 streamer_priv->streamer_copy_all_options,
1364 streamer_priv->streamer_receive_options);
1365 break;
1366 } /* switch srb[2] */
1367 break;
1368
1369
1370 /* SRB_SET_GROUP_ADDRESS - Multicast group setting
1371 */
1372 case SRB_SET_GROUP_ADDRESS:
1373 srb_word=ntohs(readw(streamer_mmio+LAPDINC)) >> 8;
1374 switch (srb_word) {
1375 case 0x00:
1376 break;
1377 case 0x01:
1378 printk(KERN_WARNING "%s: Unrecognized srb command \n",dev->name);
1379 break;
1380 case 0x04:
1381 printk(KERN_WARNING "%s: Adapter must be open for this operation, doh!!\n", dev->name);
1382 break;
1383 case 0x3c:
1384 printk(KERN_WARNING "%s: Group/Functional address indicator bits not set correctly\n", dev->name);
1385 break;
1386 case 0x3e: /* If we ever implement individual multicast addresses, will need to deal with this */
1387 printk(KERN_WARNING "%s: Group address registers full\n", dev->name);
1388 break;
1389 case 0x55:
1390 printk(KERN_INFO "%s: Group Address already set.\n", dev->name);
1391 break;
1392 default:
1393 break;
1394 } /* switch srb[2] */
1395 break;
1396
1397
1398 /* SRB_RESET_GROUP_ADDRESS - Remove a multicast address from group list
1399 */
1400 case SRB_RESET_GROUP_ADDRESS:
1401 srb_word=ntohs(readw(streamer_mmio+LAPDINC)) >> 8;
1402 switch (srb_word) {
1403 case 0x00:
1404 break;
1405 case 0x01:
1406 printk(KERN_WARNING "%s: Unrecognized srb command \n", dev->name);
1407 break;
1408 case 0x04:
1409 printk(KERN_WARNING "%s: Adapter must be open for this operation, doh!!\n", dev->name);
1410 break;
1411 case 0x39: /* Must deal with this if individual multicast addresses used */
1412 printk(KERN_INFO "%s: Group address not found \n", dev->name);
1413 break;
1414 default:
1415 break;
1416 } /* switch srb[2] */
1417 break;
1418
1419
1420 /* SRB_SET_FUNC_ADDRESS - Called by the set_rx_mode
1421 */
1422
1423 case SRB_SET_FUNC_ADDRESS:
1424 srb_word=ntohs(readw(streamer_mmio+LAPDINC)) >> 8;
1425 switch (srb_word) {
1426 case 0x00:
1427 if (streamer_priv->streamer_message_level)
1428 printk(KERN_INFO "%s: Functional Address Mask Set \n", dev->name);
1429 break;
1430 case 0x01:
1431 printk(KERN_WARNING "%s: Unrecognized srb command \n", dev->name);
1432 break;
1433 case 0x04:
1434 printk(KERN_WARNING "%s: Adapter must be open for this operation, doh!!\n", dev->name);
1435 break;
1436 default:
1437 break;
1438 } /* switch srb[2] */
1439 break;
1440
1441 /* SRB_READ_LOG - Read and reset the adapter error counters
1442 */
1443
1444 case SRB_READ_LOG:
1445 srb_word=ntohs(readw(streamer_mmio+LAPDINC)) >> 8;
1446 switch (srb_word) {
1447 case 0x00:
1448 {
1449 int i;
1450 if (streamer_priv->streamer_message_level)
1451 printk(KERN_INFO "%s: Read Log command complete\n", dev->name);
1452 printk("Read Log statistics: ");
1453 writew(streamer_priv->srb + 6,
1454 streamer_mmio + LAPA);
1455 for (i = 0; i < 5; i++) {
1456 printk("%x:", ntohs(readw(streamer_mmio + LAPDINC)));
1457 }
1458 printk("\n");
1459 }
1460 break;
1461 case 0x01:
1462 printk(KERN_WARNING "%s: Unrecognized srb command \n", dev->name);
1463 break;
1464 case 0x04:
1465 printk(KERN_WARNING "%s: Adapter must be open for this operation, doh!!\n", dev->name);
1466 break;
1467
1468 } /* switch srb[2] */
1469 break;
1470
1471 /* SRB_READ_SR_COUNTERS - Read and reset the source routing bridge related counters */
1472
1473 case SRB_READ_SR_COUNTERS:
1474 srb_word=ntohs(readw(streamer_mmio+LAPDINC)) >> 8;
1475 switch (srb_word) {
1476 case 0x00:
1477 if (streamer_priv->streamer_message_level)
1478 printk(KERN_INFO "%s: Read Source Routing Counters issued\n", dev->name);
1479 break;
1480 case 0x01:
1481 printk(KERN_WARNING "%s: Unrecognized srb command \n", dev->name);
1482 break;
1483 case 0x04:
1484 printk(KERN_WARNING "%s: Adapter must be open for this operation, doh!!\n", dev->name);
1485 break;
1486 default:
1487 break;
1488 } /* switch srb[2] */
1489 break;
1490
1491 default:
1492 printk(KERN_WARNING "%s: Unrecognized srb bh return value.\n", dev->name);
1493 break;
1494 } /* switch srb[0] */
1495}
1496
1497static struct net_device_stats *streamer_get_stats(struct net_device *dev)
1498{
1499 struct streamer_private *streamer_priv;
1500 streamer_priv = (struct streamer_private *) dev->priv;
1501 return (struct net_device_stats *) &streamer_priv->streamer_stats;
1502}
1503
1504static int streamer_set_mac_address(struct net_device *dev, void *addr)
1505{
1506 struct sockaddr *saddr = addr;
1507 struct streamer_private *streamer_priv = (struct streamer_private *) dev->priv;
1508
1509 if (netif_running(dev))
1510 {
1511 printk(KERN_WARNING "%s: Cannot set mac/laa address while card is open\n", dev->name);
1512 return -EIO;
1513 }
1514
1515 memcpy(streamer_priv->streamer_laa, saddr->sa_data, dev->addr_len);
1516
1517 if (streamer_priv->streamer_message_level) {
1518 printk(KERN_INFO "%s: MAC/LAA Set to = %x.%x.%x.%x.%x.%x\n",
1519 dev->name, streamer_priv->streamer_laa[0],
1520 streamer_priv->streamer_laa[1],
1521 streamer_priv->streamer_laa[2],
1522 streamer_priv->streamer_laa[3],
1523 streamer_priv->streamer_laa[4],
1524 streamer_priv->streamer_laa[5]);
1525 }
1526 return 0;
1527}
1528
1529static void streamer_arb_cmd(struct net_device *dev)
1530{
1531 struct streamer_private *streamer_priv =
1532 (struct streamer_private *) dev->priv;
1533 __u8 __iomem *streamer_mmio = streamer_priv->streamer_mmio;
1534 __u8 header_len;
1535 __u16 frame_len, buffer_len;
1536 struct sk_buff *mac_frame;
1537 __u8 frame_data[256];
1538 __u16 buff_off;
1539 __u16 lan_status = 0, lan_status_diff; /* Initialize to stop compiler warning */
1540 __u8 fdx_prot_error;
1541 __u16 next_ptr;
1542 __u16 arb_word;
1543
1544#if STREAMER_NETWORK_MONITOR
1545 struct trh_hdr *mac_hdr;
1546#endif
1547
1548 writew(streamer_priv->arb, streamer_mmio + LAPA);
1549 arb_word=ntohs(readw(streamer_mmio+LAPD)) >> 8;
1550
1551 if (arb_word == ARB_RECEIVE_DATA) { /* Receive.data, MAC frames */
1552 writew(streamer_priv->arb + 6, streamer_mmio + LAPA);
1553 streamer_priv->mac_rx_buffer = buff_off = ntohs(readw(streamer_mmio + LAPDINC));
1554 header_len=ntohs(readw(streamer_mmio+LAPDINC)) >> 8; /* 802.5 Token-Ring Header Length */
1555 frame_len = ntohs(readw(streamer_mmio + LAPDINC));
1556
1557#if STREAMER_DEBUG
1558 {
1559 int i;
1560 __u16 next;
1561 __u8 status;
1562 __u16 len;
1563
1564 writew(ntohs(buff_off), streamer_mmio + LAPA); /*setup window to frame data */
1565 next = htons(readw(streamer_mmio + LAPDINC));
1566 status =
1567 ntohs(readw(streamer_mmio + LAPDINC)) & 0xff;
1568 len = ntohs(readw(streamer_mmio + LAPDINC));
1569
1570 /* print out 1st 14 bytes of frame data */
1571 for (i = 0; i < 7; i++) {
1572 printk("Loc %d = %04x\n", i,
1573 ntohs(readw
1574 (streamer_mmio + LAPDINC)));
1575 }
1576
1577 printk("next %04x, fs %02x, len %04x \n", next,
1578 status, len);
1579 }
1580#endif
1581 if (!(mac_frame = dev_alloc_skb(frame_len))) {
1582 printk(KERN_WARNING "%s: Memory squeeze, dropping frame.\n",
1583 dev->name);
1584 goto drop_frame;
1585 }
1586 /* Walk the buffer chain, creating the frame */
1587
1588 do {
1589 int i;
1590 __u16 rx_word;
1591
1592 writew(htons(buff_off), streamer_mmio + LAPA); /* setup window to frame data */
1593 next_ptr = ntohs(readw(streamer_mmio + LAPDINC));
1594 readw(streamer_mmio + LAPDINC); /* read thru status word */
1595 buffer_len = ntohs(readw(streamer_mmio + LAPDINC));
1596
1597 if (buffer_len > 256)
1598 break;
1599
1600 i = 0;
1601 while (i < buffer_len) {
1602 rx_word=ntohs(readw(streamer_mmio+LAPDINC));
1603 frame_data[i]=rx_word >> 8;
1604 frame_data[i+1]=rx_word & 0xff;
1605 i += 2;
1606 }
1607
1608 memcpy(skb_put(mac_frame, buffer_len),
1609 frame_data, buffer_len);
1610 } while (next_ptr && (buff_off = next_ptr));
1611
1612#if STREAMER_NETWORK_MONITOR
1613 printk(KERN_WARNING "%s: Received MAC Frame, details: \n",
1614 dev->name);
1615 mac_hdr = (struct trh_hdr *) mac_frame->data;
1616 printk(KERN_WARNING
1617 "%s: MAC Frame Dest. Addr: %02x:%02x:%02x:%02x:%02x:%02x \n",
1618 dev->name, mac_hdr->daddr[0], mac_hdr->daddr[1],
1619 mac_hdr->daddr[2], mac_hdr->daddr[3],
1620 mac_hdr->daddr[4], mac_hdr->daddr[5]);
1621 printk(KERN_WARNING
1622 "%s: MAC Frame Srce. Addr: %02x:%02x:%02x:%02x:%02x:%02x \n",
1623 dev->name, mac_hdr->saddr[0], mac_hdr->saddr[1],
1624 mac_hdr->saddr[2], mac_hdr->saddr[3],
1625 mac_hdr->saddr[4], mac_hdr->saddr[5]);
1626#endif
1627 mac_frame->dev = dev;
1628 mac_frame->protocol = tr_type_trans(mac_frame, dev);
1629 netif_rx(mac_frame);
1630
1631 /* Now tell the card we have dealt with the received frame */
1632drop_frame:
1633 /* Set LISR Bit 1 */
1634 writel(LISR_ARB_FREE, streamer_priv->streamer_mmio + LISR_SUM);
1635
1636 /* Is the ASB free ? */
1637
1638 if (!(readl(streamer_priv->streamer_mmio + SISR) & SISR_ASB_FREE))
1639 {
1640 streamer_priv->asb_queued = 1;
1641 writel(LISR_ASB_FREE_REQ, streamer_priv->streamer_mmio + LISR_SUM);
1642 return;
1643 /* Drop out and wait for the bottom half to be run */
1644 }
1645
1646
1647 writew(streamer_priv->asb, streamer_mmio + LAPA);
1648 writew(htons(ASB_RECEIVE_DATA << 8), streamer_mmio+LAPDINC);
1649 writew(htons(STREAMER_CLEAR_RET_CODE << 8), streamer_mmio+LAPDINC);
1650 writew(0, streamer_mmio + LAPDINC);
1651 writew(htons(streamer_priv->mac_rx_buffer), streamer_mmio + LAPD);
1652
1653 writel(LISR_ASB_REPLY | LISR_ASB_FREE_REQ, streamer_priv->streamer_mmio + LISR_SUM);
1654
1655 streamer_priv->asb_queued = 2;
1656 return;
1657
1658 } else if (arb_word == ARB_LAN_CHANGE_STATUS) { /* Lan.change.status */
1659 writew(streamer_priv->arb + 6, streamer_mmio + LAPA);
1660 lan_status = ntohs(readw(streamer_mmio + LAPDINC));
1661 fdx_prot_error = ntohs(readw(streamer_mmio+LAPD)) >> 8;
1662
1663 /* Issue ARB Free */
1664 writew(LISR_ARB_FREE, streamer_priv->streamer_mmio + LISR_SUM);
1665
1666 lan_status_diff = (streamer_priv->streamer_lan_status ^ lan_status) &
1667 lan_status;
1668
1669 if (lan_status_diff & (LSC_LWF | LSC_ARW | LSC_FPE | LSC_RR))
1670 {
1671 if (lan_status_diff & LSC_LWF)
1672 printk(KERN_WARNING "%s: Short circuit detected on the lobe\n", dev->name);
1673 if (lan_status_diff & LSC_ARW)
1674 printk(KERN_WARNING "%s: Auto removal error\n", dev->name);
1675 if (lan_status_diff & LSC_FPE)
1676 printk(KERN_WARNING "%s: FDX Protocol Error\n", dev->name);
1677 if (lan_status_diff & LSC_RR)
1678 printk(KERN_WARNING "%s: Force remove MAC frame received\n", dev->name);
1679
1680 /* Adapter has been closed by the hardware */
1681
1682 /* reset tx/rx fifo's and busmaster logic */
1683
1684 /* @TBD. no llc reset on autostreamer writel(readl(streamer_mmio+BCTL)|(3<<13),streamer_mmio+BCTL);
1685 udelay(1);
1686 writel(readl(streamer_mmio+BCTL)&~(3<<13),streamer_mmio+BCTL); */
1687
1688 netif_stop_queue(dev);
1689 netif_carrier_off(dev);
1690 printk(KERN_WARNING "%s: Adapter must be manually reset.\n", dev->name);
1691 }
1692 /* If serious error */
1693 if (streamer_priv->streamer_message_level) {
1694 if (lan_status_diff & LSC_SIG_LOSS)
1695 printk(KERN_WARNING "%s: No receive signal detected \n", dev->name);
1696 if (lan_status_diff & LSC_HARD_ERR)
1697 printk(KERN_INFO "%s: Beaconing \n", dev->name);
1698 if (lan_status_diff & LSC_SOFT_ERR)
1699 printk(KERN_WARNING "%s: Adapter transmitted Soft Error Report Mac Frame \n", dev->name);
1700 if (lan_status_diff & LSC_TRAN_BCN)
1701 printk(KERN_INFO "%s: We are tranmitting the beacon, aaah\n", dev->name);
1702 if (lan_status_diff & LSC_SS)
1703 printk(KERN_INFO "%s: Single Station on the ring \n", dev->name);
1704 if (lan_status_diff & LSC_RING_REC)
1705 printk(KERN_INFO "%s: Ring recovery ongoing\n", dev->name);
1706 if (lan_status_diff & LSC_FDX_MODE)
1707 printk(KERN_INFO "%s: Operating in FDX mode\n", dev->name);
1708 }
1709
1710 if (lan_status_diff & LSC_CO) {
1711 if (streamer_priv->streamer_message_level)
1712 printk(KERN_INFO "%s: Counter Overflow \n", dev->name);
1713
1714 /* Issue READ.LOG command */
1715
1716 writew(streamer_priv->srb, streamer_mmio + LAPA);
1717 writew(htons(SRB_READ_LOG << 8),streamer_mmio+LAPDINC);
1718 writew(htons(STREAMER_CLEAR_RET_CODE << 8), streamer_mmio+LAPDINC);
1719 writew(0, streamer_mmio + LAPDINC);
1720 streamer_priv->srb_queued = 2; /* Can't sleep, use srb_bh */
1721
1722 writew(LISR_SRB_CMD, streamer_mmio + LISR_SUM);
1723 }
1724
1725 if (lan_status_diff & LSC_SR_CO) {
1726 if (streamer_priv->streamer_message_level)
1727 printk(KERN_INFO "%s: Source routing counters overflow\n", dev->name);
1728
1729 /* Issue a READ.SR.COUNTERS */
1730 writew(streamer_priv->srb, streamer_mmio + LAPA);
1731 writew(htons(SRB_READ_SR_COUNTERS << 8),
1732 streamer_mmio+LAPDINC);
1733 writew(htons(STREAMER_CLEAR_RET_CODE << 8),
1734 streamer_mmio+LAPDINC);
1735 streamer_priv->srb_queued = 2; /* Can't sleep, use srb_bh */
1736 writew(LISR_SRB_CMD, streamer_mmio + LISR_SUM);
1737
1738 }
1739 streamer_priv->streamer_lan_status = lan_status;
1740 } /* Lan.change.status */
1741 else
1742 printk(KERN_WARNING "%s: Unknown arb command \n", dev->name);
1743}
1744
1745static void streamer_asb_bh(struct net_device *dev)
1746{
1747 struct streamer_private *streamer_priv =
1748 (struct streamer_private *) dev->priv;
1749 __u8 __iomem *streamer_mmio = streamer_priv->streamer_mmio;
1750
1751 if (streamer_priv->asb_queued == 1)
1752 {
1753 /* Dropped through the first time */
1754
1755 writew(streamer_priv->asb, streamer_mmio + LAPA);
1756 writew(htons(ASB_RECEIVE_DATA << 8),streamer_mmio+LAPDINC);
1757 writew(htons(STREAMER_CLEAR_RET_CODE << 8), streamer_mmio+LAPDINC);
1758 writew(0, streamer_mmio + LAPDINC);
1759 writew(htons(streamer_priv->mac_rx_buffer), streamer_mmio + LAPD);
1760
1761 writel(LISR_ASB_REPLY | LISR_ASB_FREE_REQ, streamer_priv->streamer_mmio + LISR_SUM);
1762 streamer_priv->asb_queued = 2;
1763
1764 return;
1765 }
1766
1767 if (streamer_priv->asb_queued == 2) {
1768 __u8 rc;
1769 writew(streamer_priv->asb + 2, streamer_mmio + LAPA);
1770 rc=ntohs(readw(streamer_mmio+LAPD)) >> 8;
1771 switch (rc) {
1772 case 0x01:
1773 printk(KERN_WARNING "%s: Unrecognized command code \n", dev->name);
1774 break;
1775 case 0x26:
1776 printk(KERN_WARNING "%s: Unrecognized buffer address \n", dev->name);
1777 break;
1778 case 0xFF:
1779 /* Valid response, everything should be ok again */
1780 break;
1781 default:
1782 printk(KERN_WARNING "%s: Invalid return code in asb\n", dev->name);
1783 break;
1784 }
1785 }
1786 streamer_priv->asb_queued = 0;
1787}
1788
1789static int streamer_change_mtu(struct net_device *dev, int mtu)
1790{
1791 struct streamer_private *streamer_priv =
1792 (struct streamer_private *) dev->priv;
1793 __u16 max_mtu;
1794
1795 if (streamer_priv->streamer_ring_speed == 4)
1796 max_mtu = 4500;
1797 else
1798 max_mtu = 18000;
1799
1800 if (mtu > max_mtu)
1801 return -EINVAL;
1802 if (mtu < 100)
1803 return -EINVAL;
1804
1805 dev->mtu = mtu;
1806 streamer_priv->pkt_buf_sz = mtu + TR_HLEN;
1807
1808 return 0;
1809}
1810
1811#if STREAMER_NETWORK_MONITOR
1812#ifdef CONFIG_PROC_FS
1813static int streamer_proc_info(char *buffer, char **start, off_t offset,
1814 int length, int *eof, void *data)
1815{
1816 struct streamer_private *sdev=NULL;
1817 struct pci_dev *pci_device = NULL;
1818 int len = 0;
1819 off_t begin = 0;
1820 off_t pos = 0;
1821 int size;
1822
1823 struct net_device *dev;
1824
1825 size = sprintf(buffer, "IBM LanStreamer/MPC Chipset Token Ring Adapters\n");
1826
1827 pos += size;
1828 len += size;
1829
1830 for(sdev=dev_streamer; sdev; sdev=sdev->next) {
1831 pci_device=sdev->pci_dev;
1832 dev=pci_get_drvdata(pci_device);
1833
1834 size = sprintf_info(buffer + len, dev);
1835 len += size;
1836 pos = begin + len;
1837
1838 if (pos < offset) {
1839 len = 0;
1840 begin = pos;
1841 }
1842 if (pos > offset + length)
1843 break;
1844 } /* for */
1845
1846 *start = buffer + (offset - begin); /* Start of wanted data */
1847 len -= (offset - begin); /* Start slop */
1848 if (len > length)
1849 len = length; /* Ending slop */
1850 return len;
1851}
1852
1853static int sprintf_info(char *buffer, struct net_device *dev)
1854{
1855 struct streamer_private *streamer_priv =
1856 (struct streamer_private *) dev->priv;
1857 __u8 __iomem *streamer_mmio = streamer_priv->streamer_mmio;
1858 struct streamer_adapter_addr_table sat;
1859 struct streamer_parameters_table spt;
1860 int size = 0;
1861 int i;
1862
1863 writew(streamer_priv->streamer_addr_table_addr, streamer_mmio + LAPA);
1864 for (i = 0; i < 14; i += 2) {
1865 __u16 io_word;
1866 __u8 *datap = (__u8 *) & sat;
1867 io_word=ntohs(readw(streamer_mmio+LAPDINC));
1868 datap[size]=io_word >> 8;
1869 datap[size+1]=io_word & 0xff;
1870 }
1871 writew(streamer_priv->streamer_parms_addr, streamer_mmio + LAPA);
1872 for (i = 0; i < 68; i += 2) {
1873 __u16 io_word;
1874 __u8 *datap = (__u8 *) & spt;
1875 io_word=ntohs(readw(streamer_mmio+LAPDINC));
1876 datap[size]=io_word >> 8;
1877 datap[size+1]=io_word & 0xff;
1878 }
1879
1880
1881 size = sprintf(buffer, "\n%6s: Adapter Address : Node Address : Functional Addr\n", dev->name);
1882
1883 size += sprintf(buffer + size,
1884 "%6s: %02x:%02x:%02x:%02x:%02x:%02x : %02x:%02x:%02x:%02x:%02x:%02x : %02x:%02x:%02x:%02x\n",
1885 dev->name, dev->dev_addr[0], dev->dev_addr[1],
1886 dev->dev_addr[2], dev->dev_addr[3], dev->dev_addr[4],
1887 dev->dev_addr[5], sat.node_addr[0], sat.node_addr[1],
1888 sat.node_addr[2], sat.node_addr[3], sat.node_addr[4],
1889 sat.node_addr[5], sat.func_addr[0], sat.func_addr[1],
1890 sat.func_addr[2], sat.func_addr[3]);
1891
1892 size += sprintf(buffer + size, "\n%6s: Token Ring Parameters Table:\n", dev->name);
1893
1894 size += sprintf(buffer + size, "%6s: Physical Addr : Up Node Address : Poll Address : AccPri : Auth Src : Att Code :\n", dev->name);
1895
1896 size += sprintf(buffer + size,
1897 "%6s: %02x:%02x:%02x:%02x : %02x:%02x:%02x:%02x:%02x:%02x : %02x:%02x:%02x:%02x:%02x:%02x : %04x : %04x : %04x :\n",
1898 dev->name, spt.phys_addr[0], spt.phys_addr[1],
1899 spt.phys_addr[2], spt.phys_addr[3],
1900 spt.up_node_addr[0], spt.up_node_addr[1],
1901 spt.up_node_addr[2], spt.up_node_addr[3],
1902 spt.up_node_addr[4], spt.up_node_addr[4],
1903 spt.poll_addr[0], spt.poll_addr[1], spt.poll_addr[2],
1904 spt.poll_addr[3], spt.poll_addr[4], spt.poll_addr[5],
1905 ntohs(spt.acc_priority), ntohs(spt.auth_source_class),
1906 ntohs(spt.att_code));
1907
1908 size += sprintf(buffer + size, "%6s: Source Address : Bcn T : Maj. V : Lan St : Lcl Rg : Mon Err : Frame Correl : \n", dev->name);
1909
1910 size += sprintf(buffer + size,
1911 "%6s: %02x:%02x:%02x:%02x:%02x:%02x : %04x : %04x : %04x : %04x : %04x : %04x : \n",
1912 dev->name, spt.source_addr[0], spt.source_addr[1],
1913 spt.source_addr[2], spt.source_addr[3],
1914 spt.source_addr[4], spt.source_addr[5],
1915 ntohs(spt.beacon_type), ntohs(spt.major_vector),
1916 ntohs(spt.lan_status), ntohs(spt.local_ring),
1917 ntohs(spt.mon_error), ntohs(spt.frame_correl));
1918
1919 size += sprintf(buffer + size, "%6s: Beacon Details : Tx : Rx : NAUN Node Address : NAUN Node Phys : \n",
1920 dev->name);
1921
1922 size += sprintf(buffer + size,
1923 "%6s: : %02x : %02x : %02x:%02x:%02x:%02x:%02x:%02x : %02x:%02x:%02x:%02x : \n",
1924 dev->name, ntohs(spt.beacon_transmit),
1925 ntohs(spt.beacon_receive), spt.beacon_naun[0],
1926 spt.beacon_naun[1], spt.beacon_naun[2],
1927 spt.beacon_naun[3], spt.beacon_naun[4],
1928 spt.beacon_naun[5], spt.beacon_phys[0],
1929 spt.beacon_phys[1], spt.beacon_phys[2],
1930 spt.beacon_phys[3]);
1931 return size;
1932}
1933#endif
1934#endif
1935
1936#if STREAMER_IOCTL && (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0))
1937static int streamer_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1938{
1939 int i;
1940 struct streamer_private *streamer_priv = (struct streamer_private *) dev->priv;
1941 u8 __iomem *streamer_mmio = streamer_priv->streamer_mmio;
1942
1943 switch(cmd) {
1944 case IOCTL_SISR_MASK:
1945 writew(SISR_MI, streamer_mmio + SISR_MASK_SUM);
1946 break;
1947 case IOCTL_SPIN_LOCK_TEST:
1948 printk(KERN_INFO "spin_lock() called.\n");
1949 spin_lock(&streamer_priv->streamer_lock);
1950 spin_unlock(&streamer_priv->streamer_lock);
1951 printk(KERN_INFO "spin_unlock() finished.\n");
1952 break;
1953 case IOCTL_PRINT_BDAS:
1954 printk(KERN_INFO "bdas: RXBDA: %x RXLBDA: %x TX2FDA: %x TX2LFDA: %x\n",
1955 readw(streamer_mmio + RXBDA),
1956 readw(streamer_mmio + RXLBDA),
1957 readw(streamer_mmio + TX2FDA),
1958 readw(streamer_mmio + TX2LFDA));
1959 break;
1960 case IOCTL_PRINT_REGISTERS:
1961 printk(KERN_INFO "registers:\n");
1962 printk(KERN_INFO "SISR: %04x MISR: %04x LISR: %04x BCTL: %04x BMCTL: %04x\nmask %04x mask %04x\n",
1963 readw(streamer_mmio + SISR),
1964 readw(streamer_mmio + MISR_RUM),
1965 readw(streamer_mmio + LISR),
1966 readw(streamer_mmio + BCTL),
1967 readw(streamer_mmio + BMCTL_SUM),
1968 readw(streamer_mmio + SISR_MASK),
1969 readw(streamer_mmio + MISR_MASK));
1970 break;
1971 case IOCTL_PRINT_RX_BUFS:
1972 printk(KERN_INFO "Print rx bufs:\n");
1973 for(i=0; i<STREAMER_RX_RING_SIZE; i++)
1974 printk(KERN_INFO "rx_ring %d status: 0x%x\n", i,
1975 streamer_priv->streamer_rx_ring[i].status);
1976 break;
1977 case IOCTL_PRINT_TX_BUFS:
1978 printk(KERN_INFO "Print tx bufs:\n");
1979 for(i=0; i<STREAMER_TX_RING_SIZE; i++)
1980 printk(KERN_INFO "tx_ring %d status: 0x%x\n", i,
1981 streamer_priv->streamer_tx_ring[i].status);
1982 break;
1983 case IOCTL_RX_CMD:
1984 streamer_rx(dev);
1985 printk(KERN_INFO "Sent rx command.\n");
1986 break;
1987 default:
1988 printk(KERN_INFO "Bad ioctl!\n");
1989 }
1990 return 0;
1991}
1992#endif
1993
1994static struct pci_driver streamer_pci_driver = {
1995 .name = "lanstreamer",
1996 .id_table = streamer_pci_tbl,
1997 .probe = streamer_init_one,
1998 .remove = __devexit_p(streamer_remove_one),
1999};
2000
2001static int __init streamer_init_module(void) {
2002 return pci_module_init(&streamer_pci_driver);
2003}
2004
2005static void __exit streamer_cleanup_module(void) {
2006 pci_unregister_driver(&streamer_pci_driver);
2007}
2008
2009module_init(streamer_init_module);
2010module_exit(streamer_cleanup_module);
2011MODULE_LICENSE("GPL");
diff --git a/drivers/net/tokenring/lanstreamer.h b/drivers/net/tokenring/lanstreamer.h
new file mode 100644
index 000000000000..5557d8e1e22d
--- /dev/null
+++ b/drivers/net/tokenring/lanstreamer.h
@@ -0,0 +1,358 @@
1/*
2 * lanstreamer.h -- driver for the IBM Auto LANStreamer PCI Adapter
3 *
4 * Written By: Mike Sullivan, IBM Corporation
5 *
6 * Copyright (C) 1999 IBM Corporation
7 *
8 * Linux driver for IBM PCI tokenring cards based on the LanStreamer MPC
9 * chipset.
10 *
11 * This driver is based on the olympic driver for IBM PCI TokenRing cards (Pit/Pit-Phy/Olympic
12 * chipsets) written by:
13 * 1999 Peter De Schrijver All Rights Reserved
14 * 1999 Mike Phillips (phillim@amtrak.com)
15 *
16 * Base Driver Skeleton:
17 * Written 1993-94 by Donald Becker.
18 *
19 * Copyright 1993 United States Government as represented by the
20 * Director, National Security Agency.
21 *
22 * This program is free software; you can redistribute it and/or modify
23 * it under the terms of the GNU General Public License as published by
24 * the Free Software Foundation; either version 2 of the License, or
25 * (at your option) any later version.
26 *
27 * This program is distributed in the hope that it will be useful,
28 * but WITHOUT ANY WARRANTY; without even the implied warranty of
29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30 * GNU General Public License for more details.
31 *
32 * NO WARRANTY
33 * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
34 * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
35 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
36 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
37 * solely responsible for determining the appropriateness of using and
38 * distributing the Program and assumes all risks associated with its
39 * exercise of rights under this Agreement, including but not limited to
40 * the risks and costs of program errors, damage to or loss of data,
41 * programs or equipment, and unavailability or interruption of operations.
42 *
43 * DISCLAIMER OF LIABILITY
44 * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
45 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
46 * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
47 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
48 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
49 * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
50 * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
51 *
52 * You should have received a copy of the GNU General Public License
53 * along with this program; if not, write to the Free Software
54 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
55 *
56 *
57 * 12/10/99 - Alpha Release 0.1.0
58 * First release to the public
59 * 08/15/01 - Added ioctl() definitions and others - Kent Yoder <yoder1@us.ibm.com>
60 *
61 */
62
63#include <linux/version.h>
64
65#if STREAMER_IOCTL && (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0))
66#include <asm/ioctl.h>
67#define IOCTL_PRINT_RX_BUFS SIOCDEVPRIVATE
68#define IOCTL_PRINT_TX_BUFS SIOCDEVPRIVATE+1
69#define IOCTL_RX_CMD SIOCDEVPRIVATE+2
70#define IOCTL_TX_CMD SIOCDEVPRIVATE+3
71#define IOCTL_PRINT_REGISTERS SIOCDEVPRIVATE+4
72#define IOCTL_PRINT_BDAS SIOCDEVPRIVATE+5
73#define IOCTL_SPIN_LOCK_TEST SIOCDEVPRIVATE+6
74#define IOCTL_SISR_MASK SIOCDEVPRIVATE+7
75#endif
76
77/* MAX_INTR - the maximum number of times we can loop
78 * inside the interrupt function before returning
79 * control to the OS (maximum value is 256)
80 */
81#define MAX_INTR 5
82
83#define CLS 0x0C
84#define MLR 0x86
85#define LTR 0x0D
86
87#define BCTL 0x60
88#define BCTL_SOFTRESET (1<<15)
89#define BCTL_RX_FIFO_8 (1<<1)
90#define BCTL_TX_FIFO_8 (1<<3)
91
92#define GPR 0x4a
93#define GPR_AUTOSENSE (1<<2)
94#define GPR_16MBPS (1<<3)
95
96#define LISR 0x10
97#define LISR_SUM 0x12
98#define LISR_RUM 0x14
99
100#define LISR_LIE (1<<15)
101#define LISR_SLIM (1<<13)
102#define LISR_SLI (1<<12)
103#define LISR_BPEI (1<<9)
104#define LISR_BPE (1<<8)
105#define LISR_SRB_CMD (1<<5)
106#define LISR_ASB_REPLY (1<<4)
107#define LISR_ASB_FREE_REQ (1<<2)
108#define LISR_ARB_FREE (1<<1)
109#define LISR_TRB_FRAME (1<<0)
110
111#define SISR 0x16
112#define SISR_SUM 0x18
113#define SISR_RUM 0x1A
114#define SISR_MASK 0x54
115#define SISR_MASK_SUM 0x56
116#define SISR_MASK_RUM 0x58
117
118#define SISR_MI (1<<15)
119#define SISR_SERR_ERR (1<<14)
120#define SISR_TIMER (1<<11)
121#define SISR_LAP_PAR_ERR (1<<10)
122#define SISR_LAP_ACC_ERR (1<<9)
123#define SISR_PAR_ERR (1<<8)
124#define SISR_ADAPTER_CHECK (1<<6)
125#define SISR_SRB_REPLY (1<<5)
126#define SISR_ASB_FREE (1<<4)
127#define SISR_ARB_CMD (1<<3)
128#define SISR_TRB_REPLY (1<<2)
129
130#define MISR_RUM 0x5A
131#define MISR_MASK 0x5C
132#define MISR_MASK_RUM 0x5E
133
134#define MISR_TX2_IDLE (1<<15)
135#define MISR_TX2_NO_STATUS (1<<14)
136#define MISR_TX2_HALT (1<<13)
137#define MISR_TX2_EOF (1<<12)
138#define MISR_TX1_IDLE (1<<11)
139#define MISR_TX1_NO_STATUS (1<<10)
140#define MISR_TX1_HALT (1<<9)
141#define MISR_TX1_EOF (1<<8)
142#define MISR_RX_NOBUF (1<<5)
143#define MISR_RX_EOB (1<<4)
144#define MISR_RX_NO_STATUS (1<<2)
145#define MISR_RX_HALT (1<<1)
146#define MISR_RX_EOF (1<<0)
147
148#define LAPA 0x62
149#define LAPE 0x64
150#define LAPD 0x66
151#define LAPDINC 0x68
152#define LAPWWO 0x6A
153#define LAPWWC 0x6C
154#define LAPCTL 0x6E
155
156#define TIMER 0x4E4
157
158#define BMCTL_SUM 0x50
159#define BMCTL_RUM 0x52
160#define BMCTL_TX1_DIS (1<<14)
161#define BMCTL_TX2_DIS (1<<10)
162#define BMCTL_RX_DIS (1<<6)
163#define BMCTL_RX_ENABLED (1<<5)
164
165#define RXLBDA 0x90
166#define RXBDA 0x94
167#define RXSTAT 0x98
168#define RXDBA 0x9C
169
170#define TX1LFDA 0xA0
171#define TX1FDA 0xA4
172#define TX1STAT 0xA8
173#define TX1DBA 0xAC
174#define TX2LFDA 0xB0
175#define TX2FDA 0xB4
176#define TX2STAT 0xB8
177#define TX2DBA 0xBC
178
179#define STREAMER_IO_SPACE 256
180
181#define SRB_COMMAND_SIZE 50
182
183#define STREAMER_MAX_ADAPTERS 8 /* 0x08 __MODULE_STRING can't hand 0xnn */
184
185/* Defines for LAN STATUS CHANGE reports */
186#define LSC_SIG_LOSS 0x8000
187#define LSC_HARD_ERR 0x4000
188#define LSC_SOFT_ERR 0x2000
189#define LSC_TRAN_BCN 0x1000
190#define LSC_LWF 0x0800
191#define LSC_ARW 0x0400
192#define LSC_FPE 0x0200
193#define LSC_RR 0x0100
194#define LSC_CO 0x0080
195#define LSC_SS 0x0040
196#define LSC_RING_REC 0x0020
197#define LSC_SR_CO 0x0010
198#define LSC_FDX_MODE 0x0004
199
200/* Defines for OPEN ADAPTER command */
201
202#define OPEN_ADAPTER_EXT_WRAP (1<<15)
203#define OPEN_ADAPTER_DIS_HARDEE (1<<14)
204#define OPEN_ADAPTER_DIS_SOFTERR (1<<13)
205#define OPEN_ADAPTER_PASS_ADC_MAC (1<<12)
206#define OPEN_ADAPTER_PASS_ATT_MAC (1<<11)
207#define OPEN_ADAPTER_ENABLE_EC (1<<10)
208#define OPEN_ADAPTER_CONTENDER (1<<8)
209#define OPEN_ADAPTER_PASS_BEACON (1<<7)
210#define OPEN_ADAPTER_ENABLE_FDX (1<<6)
211#define OPEN_ADAPTER_ENABLE_RPL (1<<5)
212#define OPEN_ADAPTER_INHIBIT_ETR (1<<4)
213#define OPEN_ADAPTER_INTERNAL_WRAP (1<<3)
214
215
216/* Defines for SRB Commands */
217#define SRB_CLOSE_ADAPTER 0x04
218#define SRB_CONFIGURE_BRIDGE 0x0c
219#define SRB_CONFIGURE_HP_CHANNEL 0x13
220#define SRB_MODIFY_BRIDGE_PARMS 0x15
221#define SRB_MODIFY_OPEN_OPTIONS 0x01
222#define SRB_MODIFY_RECEIVE_OPTIONS 0x17
223#define SRB_NO_OPERATION 0x00
224#define SRB_OPEN_ADAPTER 0x03
225#define SRB_READ_LOG 0x08
226#define SRB_READ_SR_COUNTERS 0x16
227#define SRB_RESET_GROUP_ADDRESS 0x02
228#define SRB_RESET_TARGET_SEGMETN 0x14
229#define SRB_SAVE_CONFIGURATION 0x1b
230#define SRB_SET_BRIDGE_PARMS 0x09
231#define SRB_SET_FUNC_ADDRESS 0x07
232#define SRB_SET_GROUP_ADDRESS 0x06
233#define SRB_SET_TARGET_SEGMENT 0x05
234
235/* Clear return code */
236#define STREAMER_CLEAR_RET_CODE 0xfe
237
238/* ARB Commands */
239#define ARB_RECEIVE_DATA 0x81
240#define ARB_LAN_CHANGE_STATUS 0x84
241
242/* ASB Response commands */
243#define ASB_RECEIVE_DATA 0x81
244
245
246/* Streamer defaults for buffers */
247
248#define STREAMER_RX_RING_SIZE 16 /* should be a power of 2 */
249/* Setting the number of TX descriptors to 1 is a workaround for an
250 * undocumented hardware problem with the lanstreamer board. Setting
251 * this to something higher may slightly increase the throughput you
252 * can get from the card, but at the risk of locking up the box. -
253 * <yoder1@us.ibm.com>
254 */
255#define STREAMER_TX_RING_SIZE 1 /* should be a power of 2 */
256
257#define PKT_BUF_SZ 4096 /* Default packet size */
258
259/* Streamer data structures */
260
261struct streamer_tx_desc {
262 __u32 forward;
263 __u32 status;
264 __u32 bufcnt_framelen;
265 __u32 buffer;
266 __u32 buflen;
267 __u32 rsvd1;
268 __u32 rsvd2;
269 __u32 rsvd3;
270};
271
272struct streamer_rx_desc {
273 __u32 forward;
274 __u32 status;
275 __u32 buffer;
276 __u32 framelen_buflen;
277};
278
279struct mac_receive_buffer {
280 __u16 next;
281 __u8 padding;
282 __u8 frame_status;
283 __u16 buffer_length;
284 __u8 frame_data;
285};
286
287struct streamer_private {
288
289 __u16 srb;
290 __u16 trb;
291 __u16 arb;
292 __u16 asb;
293
294 struct streamer_private *next;
295 struct pci_dev *pci_dev;
296 __u8 __iomem *streamer_mmio;
297 char *streamer_card_name;
298
299 spinlock_t streamer_lock;
300
301 volatile int srb_queued; /* True if an SRB is still posted */
302 wait_queue_head_t srb_wait;
303
304 volatile int asb_queued; /* True if an ASB is posted */
305
306 volatile int trb_queued; /* True if a TRB is posted */
307 wait_queue_head_t trb_wait;
308
309 struct streamer_rx_desc *streamer_rx_ring;
310 struct streamer_tx_desc *streamer_tx_ring;
311 struct sk_buff *tx_ring_skb[STREAMER_TX_RING_SIZE],
312 *rx_ring_skb[STREAMER_RX_RING_SIZE];
313 int tx_ring_free, tx_ring_last_status, rx_ring_last_received,
314 free_tx_ring_entries;
315
316 struct net_device_stats streamer_stats;
317 __u16 streamer_lan_status;
318 __u8 streamer_ring_speed;
319 __u16 pkt_buf_sz;
320 __u8 streamer_receive_options, streamer_copy_all_options,
321 streamer_message_level;
322 __u16 streamer_addr_table_addr, streamer_parms_addr;
323 __u16 mac_rx_buffer;
324 __u8 streamer_laa[6];
325};
326
327struct streamer_adapter_addr_table {
328
329 __u8 node_addr[6];
330 __u8 reserved[4];
331 __u8 func_addr[4];
332};
333
334struct streamer_parameters_table {
335
336 __u8 phys_addr[4];
337 __u8 up_node_addr[6];
338 __u8 up_phys_addr[4];
339 __u8 poll_addr[6];
340 __u16 reserved;
341 __u16 acc_priority;
342 __u16 auth_source_class;
343 __u16 att_code;
344 __u8 source_addr[6];
345 __u16 beacon_type;
346 __u16 major_vector;
347 __u16 lan_status;
348 __u16 soft_error_time;
349 __u16 reserved1;
350 __u16 local_ring;
351 __u16 mon_error;
352 __u16 beacon_transmit;
353 __u16 beacon_receive;
354 __u16 frame_correl;
355 __u8 beacon_naun[6];
356 __u32 reserved2;
357 __u8 beacon_phys[4];
358};
diff --git a/drivers/net/tokenring/madgemc.c b/drivers/net/tokenring/madgemc.c
new file mode 100644
index 000000000000..cfae2bbf2167
--- /dev/null
+++ b/drivers/net/tokenring/madgemc.c
@@ -0,0 +1,800 @@
1/*
2 * madgemc.c: Driver for the Madge Smart 16/4 MC16 MCA token ring card.
3 *
4 * Written 2000 by Adam Fritzler
5 *
6 * This software may be used and distributed according to the terms
7 * of the GNU General Public License, incorporated herein by reference.
8 *
9 * This driver module supports the following cards:
10 * - Madge Smart 16/4 Ringnode MC16
11 * - Madge Smart 16/4 Ringnode MC32 (??)
12 *
13 * Maintainer(s):
14 * AF Adam Fritzler mid@auk.cx
15 *
16 * Modification History:
17 * 16-Jan-00 AF Created
18 *
19 */
20static const char version[] = "madgemc.c: v0.91 23/01/2000 by Adam Fritzler\n";
21
22#include <linux/module.h>
23#include <linux/mca-legacy.h>
24#include <linux/kernel.h>
25#include <linux/errno.h>
26#include <linux/pci.h>
27#include <linux/init.h>
28#include <linux/netdevice.h>
29#include <linux/trdevice.h>
30
31#include <asm/system.h>
32#include <asm/io.h>
33#include <asm/irq.h>
34
35#include "tms380tr.h"
36#include "madgemc.h" /* Madge-specific constants */
37
38#define MADGEMC_IO_EXTENT 32
39#define MADGEMC_SIF_OFFSET 0x08
40
41struct madgemc_card {
42 struct net_device *dev;
43
44 /*
45 * These are read from the BIA ROM.
46 */
47 unsigned int manid;
48 unsigned int cardtype;
49 unsigned int cardrev;
50 unsigned int ramsize;
51
52 /*
53 * These are read from the MCA POS registers.
54 */
55 unsigned int burstmode:2;
56 unsigned int fairness:1; /* 0 = Fair, 1 = Unfair */
57 unsigned int arblevel:4;
58 unsigned int ringspeed:2; /* 0 = 4mb, 1 = 16, 2 = Auto/none */
59 unsigned int cabletype:1; /* 0 = RJ45, 1 = DB9 */
60
61 struct madgemc_card *next;
62};
63static struct madgemc_card *madgemc_card_list;
64
65
66static int madgemc_open(struct net_device *dev);
67static int madgemc_close(struct net_device *dev);
68static int madgemc_chipset_init(struct net_device *dev);
69static void madgemc_read_rom(struct madgemc_card *card);
70static unsigned short madgemc_setnselout_pins(struct net_device *dev);
71static void madgemc_setcabletype(struct net_device *dev, int type);
72
73static int madgemc_mcaproc(char *buf, int slot, void *d);
74
75static void madgemc_setregpage(struct net_device *dev, int page);
76static void madgemc_setsifsel(struct net_device *dev, int val);
77static void madgemc_setint(struct net_device *dev, int val);
78
79static irqreturn_t madgemc_interrupt(int irq, void *dev_id, struct pt_regs *regs);
80
81/*
82 * These work around paging, however they don't guarentee you're on the
83 * right page.
84 */
85#define SIFREADB(reg) (inb(dev->base_addr + ((reg<0x8)?reg:reg-0x8)))
86#define SIFWRITEB(val, reg) (outb(val, dev->base_addr + ((reg<0x8)?reg:reg-0x8)))
87#define SIFREADW(reg) (inw(dev->base_addr + ((reg<0x8)?reg:reg-0x8)))
88#define SIFWRITEW(val, reg) (outw(val, dev->base_addr + ((reg<0x8)?reg:reg-0x8)))
89
90/*
91 * Read a byte-length value from the register.
92 */
93static unsigned short madgemc_sifreadb(struct net_device *dev, unsigned short reg)
94{
95 unsigned short ret;
96 if (reg<0x8)
97 ret = SIFREADB(reg);
98 else {
99 madgemc_setregpage(dev, 1);
100 ret = SIFREADB(reg);
101 madgemc_setregpage(dev, 0);
102 }
103 return ret;
104}
105
106/*
107 * Write a byte-length value to a register.
108 */
109static void madgemc_sifwriteb(struct net_device *dev, unsigned short val, unsigned short reg)
110{
111 if (reg<0x8)
112 SIFWRITEB(val, reg);
113 else {
114 madgemc_setregpage(dev, 1);
115 SIFWRITEB(val, reg);
116 madgemc_setregpage(dev, 0);
117 }
118 return;
119}
120
121/*
122 * Read a word-length value from a register
123 */
124static unsigned short madgemc_sifreadw(struct net_device *dev, unsigned short reg)
125{
126 unsigned short ret;
127 if (reg<0x8)
128 ret = SIFREADW(reg);
129 else {
130 madgemc_setregpage(dev, 1);
131 ret = SIFREADW(reg);
132 madgemc_setregpage(dev, 0);
133 }
134 return ret;
135}
136
137/*
138 * Write a word-length value to a register.
139 */
140static void madgemc_sifwritew(struct net_device *dev, unsigned short val, unsigned short reg)
141{
142 if (reg<0x8)
143 SIFWRITEW(val, reg);
144 else {
145 madgemc_setregpage(dev, 1);
146 SIFWRITEW(val, reg);
147 madgemc_setregpage(dev, 0);
148 }
149 return;
150}
151
152
153
154static int __init madgemc_probe(void)
155{
156 static int versionprinted;
157 struct net_device *dev;
158 struct net_local *tp;
159 struct madgemc_card *card;
160 int i,slot = 0;
161 __u8 posreg[4];
162
163 if (!MCA_bus)
164 return -1;
165
166 while (slot != MCA_NOTFOUND) {
167 /*
168 * Currently we only support the MC16/32 (MCA ID 002d)
169 */
170 slot = mca_find_unused_adapter(0x002d, slot);
171 if (slot == MCA_NOTFOUND)
172 break;
173
174 /*
175 * If we get here, we have an adapter.
176 */
177 if (versionprinted++ == 0)
178 printk("%s", version);
179
180 dev = alloc_trdev(sizeof(struct net_local));
181 if (dev == NULL) {
182 printk("madgemc: unable to allocate dev space\n");
183 if (madgemc_card_list)
184 return 0;
185 return -1;
186 }
187
188 SET_MODULE_OWNER(dev);
189 dev->dma = 0;
190
191 /*
192 * Fetch MCA config registers
193 */
194 for(i=0;i<4;i++)
195 posreg[i] = mca_read_stored_pos(slot, i+2);
196
197 card = kmalloc(sizeof(struct madgemc_card), GFP_KERNEL);
198 if (card==NULL) {
199 printk("madgemc: unable to allocate card struct\n");
200 free_netdev(dev);
201 if (madgemc_card_list)
202 return 0;
203 return -1;
204 }
205 card->dev = dev;
206
207 /*
208 * Parse configuration information. This all comes
209 * directly from the publicly available @002d.ADF.
210 * Get it from Madge or your local ADF library.
211 */
212
213 /*
214 * Base address
215 */
216 dev->base_addr = 0x0a20 +
217 ((posreg[2] & MC16_POS2_ADDR2)?0x0400:0) +
218 ((posreg[0] & MC16_POS0_ADDR1)?0x1000:0) +
219 ((posreg[3] & MC16_POS3_ADDR3)?0x2000:0);
220
221 /*
222 * Interrupt line
223 */
224 switch(posreg[0] >> 6) { /* upper two bits */
225 case 0x1: dev->irq = 3; break;
226 case 0x2: dev->irq = 9; break; /* IRQ 2 = IRQ 9 */
227 case 0x3: dev->irq = 10; break;
228 default: dev->irq = 0; break;
229 }
230
231 if (dev->irq == 0) {
232 printk("%s: invalid IRQ\n", dev->name);
233 goto getout1;
234 }
235
236 if (!request_region(dev->base_addr, MADGEMC_IO_EXTENT,
237 "madgemc")) {
238 printk(KERN_INFO "madgemc: unable to setup Smart MC in slot %d because of I/O base conflict at 0x%04lx\n", slot, dev->base_addr);
239 dev->base_addr += MADGEMC_SIF_OFFSET;
240 goto getout1;
241 }
242 dev->base_addr += MADGEMC_SIF_OFFSET;
243
244 /*
245 * Arbitration Level
246 */
247 card->arblevel = ((posreg[0] >> 1) & 0x7) + 8;
248
249 /*
250 * Burst mode and Fairness
251 */
252 card->burstmode = ((posreg[2] >> 6) & 0x3);
253 card->fairness = ((posreg[2] >> 4) & 0x1);
254
255 /*
256 * Ring Speed
257 */
258 if ((posreg[1] >> 2)&0x1)
259 card->ringspeed = 2; /* not selected */
260 else if ((posreg[2] >> 5) & 0x1)
261 card->ringspeed = 1; /* 16Mb */
262 else
263 card->ringspeed = 0; /* 4Mb */
264
265 /*
266 * Cable type
267 */
268 if ((posreg[1] >> 6)&0x1)
269 card->cabletype = 1; /* STP/DB9 */
270 else
271 card->cabletype = 0; /* UTP/RJ-45 */
272
273
274 /*
275 * ROM Info. This requires us to actually twiddle
276 * bits on the card, so we must ensure above that
277 * the base address is free of conflict (request_region above).
278 */
279 madgemc_read_rom(card);
280
281 if (card->manid != 0x4d) { /* something went wrong */
282 printk(KERN_INFO "%s: Madge MC ROM read failed (unknown manufacturer ID %02x)\n", dev->name, card->manid);
283 goto getout;
284 }
285
286 if ((card->cardtype != 0x08) && (card->cardtype != 0x0d)) {
287 printk(KERN_INFO "%s: Madge MC ROM read failed (unknown card ID %02x)\n", dev->name, card->cardtype);
288 goto getout;
289 }
290
291 /* All cards except Rev 0 and 1 MC16's have 256kb of RAM */
292 if ((card->cardtype == 0x08) && (card->cardrev <= 0x01))
293 card->ramsize = 128;
294 else
295 card->ramsize = 256;
296
297 printk("%s: %s Rev %d at 0x%04lx IRQ %d\n",
298 dev->name,
299 (card->cardtype == 0x08)?MADGEMC16_CARDNAME:
300 MADGEMC32_CARDNAME, card->cardrev,
301 dev->base_addr, dev->irq);
302
303 if (card->cardtype == 0x0d)
304 printk("%s: Warning: MC32 support is experimental and highly untested\n", dev->name);
305
306 if (card->ringspeed==2) { /* Unknown */
307 printk("%s: Warning: Ring speed not set in POS -- Please run the reference disk and set it!\n", dev->name);
308 card->ringspeed = 1; /* default to 16mb */
309 }
310
311 printk("%s: RAM Size: %dKB\n", dev->name, card->ramsize);
312
313 printk("%s: Ring Speed: %dMb/sec on %s\n", dev->name,
314 (card->ringspeed)?16:4,
315 card->cabletype?"STP/DB9":"UTP/RJ-45");
316 printk("%s: Arbitration Level: %d\n", dev->name,
317 card->arblevel);
318
319 printk("%s: Burst Mode: ", dev->name);
320 switch(card->burstmode) {
321 case 0: printk("Cycle steal"); break;
322 case 1: printk("Limited burst"); break;
323 case 2: printk("Delayed release"); break;
324 case 3: printk("Immediate release"); break;
325 }
326 printk(" (%s)\n", (card->fairness)?"Unfair":"Fair");
327
328
329 /*
330 * Enable SIF before we assign the interrupt handler,
331 * just in case we get spurious interrupts that need
332 * handling.
333 */
334 outb(0, dev->base_addr + MC_CONTROL_REG0); /* sanity */
335 madgemc_setsifsel(dev, 1);
336 if (request_irq(dev->irq, madgemc_interrupt, SA_SHIRQ,
337 "madgemc", dev))
338 goto getout;
339
340 madgemc_chipset_init(dev); /* enables interrupts! */
341 madgemc_setcabletype(dev, card->cabletype);
342
343 /* Setup MCA structures */
344 mca_set_adapter_name(slot, (card->cardtype == 0x08)?MADGEMC16_CARDNAME:MADGEMC32_CARDNAME);
345 mca_set_adapter_procfn(slot, madgemc_mcaproc, dev);
346 mca_mark_as_used(slot);
347
348 printk("%s: Ring Station Address: ", dev->name);
349 printk("%2.2x", dev->dev_addr[0]);
350 for (i = 1; i < 6; i++)
351 printk(":%2.2x", dev->dev_addr[i]);
352 printk("\n");
353
354 /* XXX is ISA_MAX_ADDRESS correct here? */
355 if (tmsdev_init(dev, ISA_MAX_ADDRESS, NULL)) {
356 printk("%s: unable to get memory for dev->priv.\n",
357 dev->name);
358 release_region(dev->base_addr-MADGEMC_SIF_OFFSET,
359 MADGEMC_IO_EXTENT);
360
361 kfree(card);
362 tmsdev_term(dev);
363 free_netdev(dev);
364 if (madgemc_card_list)
365 return 0;
366 return -1;
367 }
368 tp = netdev_priv(dev);
369
370 /*
371 * The MC16 is physically a 32bit card. However, Madge
372 * insists on calling it 16bit, so I'll assume here that
373 * they know what they're talking about. Cut off DMA
374 * at 16mb.
375 */
376 tp->setnselout = madgemc_setnselout_pins;
377 tp->sifwriteb = madgemc_sifwriteb;
378 tp->sifreadb = madgemc_sifreadb;
379 tp->sifwritew = madgemc_sifwritew;
380 tp->sifreadw = madgemc_sifreadw;
381 tp->DataRate = (card->ringspeed)?SPEED_16:SPEED_4;
382
383 memcpy(tp->ProductID, "Madge MCA 16/4 ", PROD_ID_SIZE + 1);
384
385 dev->open = madgemc_open;
386 dev->stop = madgemc_close;
387
388 if (register_netdev(dev) == 0) {
389 /* Enlist in the card list */
390 card->next = madgemc_card_list;
391 madgemc_card_list = card;
392 slot++;
393 continue; /* successful, try to find another */
394 }
395
396 free_irq(dev->irq, dev);
397 getout:
398 release_region(dev->base_addr-MADGEMC_SIF_OFFSET,
399 MADGEMC_IO_EXTENT);
400 getout1:
401 kfree(card);
402 free_netdev(dev);
403 slot++;
404 }
405
406 if (madgemc_card_list)
407 return 0;
408 return -1;
409}
410
411/*
412 * Handle interrupts generated by the card
413 *
414 * The MicroChannel Madge cards need slightly more handling
415 * after an interrupt than other TMS380 cards do.
416 *
417 * First we must make sure it was this card that generated the
418 * interrupt (since interrupt sharing is allowed). Then,
419 * because we're using level-triggered interrupts (as is
420 * standard on MCA), we must toggle the interrupt line
421 * on the card in order to claim and acknowledge the interrupt.
422 * Once that is done, the interrupt should be handlable in
423 * the normal tms380tr_interrupt() routine.
424 *
425 * There's two ways we can check to see if the interrupt is ours,
426 * both with their own disadvantages...
427 *
428 * 1) Read in the SIFSTS register from the TMS controller. This
429 * is guarenteed to be accurate, however, there's a fairly
430 * large performance penalty for doing so: the Madge chips
431 * must request the register from the Eagle, the Eagle must
432 * read them from its internal bus, and then take the route
433 * back out again, for a 16bit read.
434 *
435 * 2) Use the MC_CONTROL_REG0_SINTR bit from the Madge ASICs.
436 * The major disadvantage here is that the accuracy of the
437 * bit is in question. However, it cuts out the extra read
438 * cycles it takes to read the Eagle's SIF, as its only an
439 * 8bit read, and theoretically the Madge bit is directly
440 * connected to the interrupt latch coming out of the Eagle
441 * hardware (that statement is not verified).
442 *
443 * I can't determine which of these methods has the best win. For now,
444 * we make a compromise. Use the Madge way for the first interrupt,
445 * which should be the fast-path, and then once we hit the first
446 * interrupt, keep on trying using the SIF method until we've
447 * exhausted all contiguous interrupts.
448 *
449 */
450static irqreturn_t madgemc_interrupt(int irq, void *dev_id, struct pt_regs *regs)
451{
452 int pending,reg1;
453 struct net_device *dev;
454
455 if (!dev_id) {
456 printk("madgemc_interrupt: was not passed a dev_id!\n");
457 return IRQ_NONE;
458 }
459
460 dev = (struct net_device *)dev_id;
461
462 /* Make sure its really us. -- the Madge way */
463 pending = inb(dev->base_addr + MC_CONTROL_REG0);
464 if (!(pending & MC_CONTROL_REG0_SINTR))
465 return IRQ_NONE; /* not our interrupt */
466
467 /*
468 * Since we're level-triggered, we may miss the rising edge
469 * of the next interrupt while we're off handling this one,
470 * so keep checking until the SIF verifies that it has nothing
471 * left for us to do.
472 */
473 pending = STS_SYSTEM_IRQ;
474 do {
475 if (pending & STS_SYSTEM_IRQ) {
476
477 /* Toggle the interrupt to reset the latch on card */
478 reg1 = inb(dev->base_addr + MC_CONTROL_REG1);
479 outb(reg1 ^ MC_CONTROL_REG1_SINTEN,
480 dev->base_addr + MC_CONTROL_REG1);
481 outb(reg1, dev->base_addr + MC_CONTROL_REG1);
482
483 /* Continue handling as normal */
484 tms380tr_interrupt(irq, dev_id, regs);
485
486 pending = SIFREADW(SIFSTS); /* restart - the SIF way */
487
488 } else
489 return IRQ_HANDLED;
490 } while (1);
491
492 return IRQ_HANDLED; /* not reachable */
493}
494
495/*
496 * Set the card to the prefered ring speed.
497 *
498 * Unlike newer cards, the MC16/32 have their speed selection
499 * circuit connected to the Madge ASICs and not to the TMS380
500 * NSELOUT pins. Set the ASIC bits correctly here, and return
501 * zero to leave the TMS NSELOUT bits unaffected.
502 *
503 */
504unsigned short madgemc_setnselout_pins(struct net_device *dev)
505{
506 unsigned char reg1;
507 struct net_local *tp = netdev_priv(dev);
508
509 reg1 = inb(dev->base_addr + MC_CONTROL_REG1);
510
511 if(tp->DataRate == SPEED_16)
512 reg1 |= MC_CONTROL_REG1_SPEED_SEL; /* add for 16mb */
513 else if (reg1 & MC_CONTROL_REG1_SPEED_SEL)
514 reg1 ^= MC_CONTROL_REG1_SPEED_SEL; /* remove for 4mb */
515 outb(reg1, dev->base_addr + MC_CONTROL_REG1);
516
517 return 0; /* no change */
518}
519
520/*
521 * Set the register page. This equates to the SRSX line
522 * on the TMS380Cx6.
523 *
524 * Register selection is normally done via three contiguous
525 * bits. However, some boards (such as the MC16/32) use only
526 * two bits, plus a separate bit in the glue chip. This
527 * sets the SRSX bit (the top bit). See page 4-17 in the
528 * Yellow Book for which registers are affected.
529 *
530 */
531static void madgemc_setregpage(struct net_device *dev, int page)
532{
533 static int reg1;
534
535 reg1 = inb(dev->base_addr + MC_CONTROL_REG1);
536 if ((page == 0) && (reg1 & MC_CONTROL_REG1_SRSX)) {
537 outb(reg1 ^ MC_CONTROL_REG1_SRSX,
538 dev->base_addr + MC_CONTROL_REG1);
539 }
540 else if (page == 1) {
541 outb(reg1 | MC_CONTROL_REG1_SRSX,
542 dev->base_addr + MC_CONTROL_REG1);
543 }
544 reg1 = inb(dev->base_addr + MC_CONTROL_REG1);
545
546 return;
547}
548
549/*
550 * The SIF registers are not mapped into register space by default
551 * Set this to 1 to map them, 0 to map the BIA ROM.
552 *
553 */
554static void madgemc_setsifsel(struct net_device *dev, int val)
555{
556 unsigned int reg0;
557
558 reg0 = inb(dev->base_addr + MC_CONTROL_REG0);
559 if ((val == 0) && (reg0 & MC_CONTROL_REG0_SIFSEL)) {
560 outb(reg0 ^ MC_CONTROL_REG0_SIFSEL,
561 dev->base_addr + MC_CONTROL_REG0);
562 } else if (val == 1) {
563 outb(reg0 | MC_CONTROL_REG0_SIFSEL,
564 dev->base_addr + MC_CONTROL_REG0);
565 }
566 reg0 = inb(dev->base_addr + MC_CONTROL_REG0);
567
568 return;
569}
570
571/*
572 * Enable SIF interrupts
573 *
574 * This does not enable interrupts in the SIF, but rather
575 * enables SIF interrupts to be passed onto the host.
576 *
577 */
578static void madgemc_setint(struct net_device *dev, int val)
579{
580 unsigned int reg1;
581
582 reg1 = inb(dev->base_addr + MC_CONTROL_REG1);
583 if ((val == 0) && (reg1 & MC_CONTROL_REG1_SINTEN)) {
584 outb(reg1 ^ MC_CONTROL_REG1_SINTEN,
585 dev->base_addr + MC_CONTROL_REG1);
586 } else if (val == 1) {
587 outb(reg1 | MC_CONTROL_REG1_SINTEN,
588 dev->base_addr + MC_CONTROL_REG1);
589 }
590
591 return;
592}
593
594/*
595 * Cable type is set via control register 7. Bit zero high
596 * for UTP, low for STP.
597 */
598static void madgemc_setcabletype(struct net_device *dev, int type)
599{
600 outb((type==0)?MC_CONTROL_REG7_CABLEUTP:MC_CONTROL_REG7_CABLESTP,
601 dev->base_addr + MC_CONTROL_REG7);
602}
603
604/*
605 * Enable the functions of the Madge chipset needed for
606 * full working order.
607 */
608static int madgemc_chipset_init(struct net_device *dev)
609{
610 outb(0, dev->base_addr + MC_CONTROL_REG1); /* pull SRESET low */
611 tms380tr_wait(100); /* wait for card to reset */
612
613 /* bring back into normal operating mode */
614 outb(MC_CONTROL_REG1_NSRESET, dev->base_addr + MC_CONTROL_REG1);
615
616 /* map SIF registers */
617 madgemc_setsifsel(dev, 1);
618
619 /* enable SIF interrupts */
620 madgemc_setint(dev, 1);
621
622 return 0;
623}
624
625/*
626 * Disable the board, and put back into power-up state.
627 */
628void madgemc_chipset_close(struct net_device *dev)
629{
630 /* disable interrupts */
631 madgemc_setint(dev, 0);
632 /* unmap SIF registers */
633 madgemc_setsifsel(dev, 0);
634
635 return;
636}
637
638/*
639 * Read the card type (MC16 or MC32) from the card.
640 *
641 * The configuration registers are stored in two separate
642 * pages. Pages are flipped by clearing bit 3 of CONTROL_REG0 (PAGE)
643 * for page zero, or setting bit 3 for page one.
644 *
645 * Page zero contains the following data:
646 * Byte 0: Manufacturer ID (0x4D -- ASCII "M")
647 * Byte 1: Card type:
648 * 0x08 for MC16
649 * 0x0D for MC32
650 * Byte 2: Card revision
651 * Byte 3: Mirror of POS config register 0
652 * Byte 4: Mirror of POS 1
653 * Byte 5: Mirror of POS 2
654 *
655 * Page one contains the following data:
656 * Byte 0: Unused
657 * Byte 1-6: BIA, MSB to LSB.
658 *
659 * Note that to read the BIA, we must unmap the SIF registers
660 * by clearing bit 2 of CONTROL_REG0 (SIFSEL), as the data
661 * will reside in the same logical location. For this reason,
662 * _never_ read the BIA while the Eagle processor is running!
663 * The SIF will be completely inaccessible until the BIA operation
664 * is complete.
665 *
666 */
667static void madgemc_read_rom(struct madgemc_card *card)
668{
669 unsigned long ioaddr;
670 unsigned char reg0, reg1, tmpreg0, i;
671
672 ioaddr = card->dev->base_addr;
673
674 reg0 = inb(ioaddr + MC_CONTROL_REG0);
675 reg1 = inb(ioaddr + MC_CONTROL_REG1);
676
677 /* Switch to page zero and unmap SIF */
678 tmpreg0 = reg0 & ~(MC_CONTROL_REG0_PAGE + MC_CONTROL_REG0_SIFSEL);
679 outb(tmpreg0, ioaddr + MC_CONTROL_REG0);
680
681 card->manid = inb(ioaddr + MC_ROM_MANUFACTURERID);
682 card->cardtype = inb(ioaddr + MC_ROM_ADAPTERID);
683 card->cardrev = inb(ioaddr + MC_ROM_REVISION);
684
685 /* Switch to rom page one */
686 outb(tmpreg0 | MC_CONTROL_REG0_PAGE, ioaddr + MC_CONTROL_REG0);
687
688 /* Read BIA */
689 card->dev->addr_len = 6;
690 for (i = 0; i < 6; i++)
691 card->dev->dev_addr[i] = inb(ioaddr + MC_ROM_BIA_START + i);
692
693 /* Restore original register values */
694 outb(reg0, ioaddr + MC_CONTROL_REG0);
695 outb(reg1, ioaddr + MC_CONTROL_REG1);
696
697 return;
698}
699
700static int madgemc_open(struct net_device *dev)
701{
702 /*
703 * Go ahead and reinitialize the chipset again, just to
704 * make sure we didn't get left in a bad state.
705 */
706 madgemc_chipset_init(dev);
707 tms380tr_open(dev);
708 return 0;
709}
710
711static int madgemc_close(struct net_device *dev)
712{
713 tms380tr_close(dev);
714 madgemc_chipset_close(dev);
715 return 0;
716}
717
718/*
719 * Give some details available from /proc/mca/slotX
720 */
721static int madgemc_mcaproc(char *buf, int slot, void *d)
722{
723 struct net_device *dev = (struct net_device *)d;
724 struct madgemc_card *curcard = madgemc_card_list;
725 int len = 0;
726
727 while (curcard) { /* search for card struct */
728 if (curcard->dev == dev)
729 break;
730 curcard = curcard->next;
731 }
732 len += sprintf(buf+len, "-------\n");
733 if (curcard) {
734 struct net_local *tp = netdev_priv(dev);
735 int i;
736
737 len += sprintf(buf+len, "Card Revision: %d\n", curcard->cardrev);
738 len += sprintf(buf+len, "RAM Size: %dkb\n", curcard->ramsize);
739 len += sprintf(buf+len, "Cable type: %s\n", (curcard->cabletype)?"STP/DB9":"UTP/RJ-45");
740 len += sprintf(buf+len, "Configured ring speed: %dMb/sec\n", (curcard->ringspeed)?16:4);
741 len += sprintf(buf+len, "Running ring speed: %dMb/sec\n", (tp->DataRate==SPEED_16)?16:4);
742 len += sprintf(buf+len, "Device: %s\n", dev->name);
743 len += sprintf(buf+len, "IO Port: 0x%04lx\n", dev->base_addr);
744 len += sprintf(buf+len, "IRQ: %d\n", dev->irq);
745 len += sprintf(buf+len, "Arbitration Level: %d\n", curcard->arblevel);
746 len += sprintf(buf+len, "Burst Mode: ");
747 switch(curcard->burstmode) {
748 case 0: len += sprintf(buf+len, "Cycle steal"); break;
749 case 1: len += sprintf(buf+len, "Limited burst"); break;
750 case 2: len += sprintf(buf+len, "Delayed release"); break;
751 case 3: len += sprintf(buf+len, "Immediate release"); break;
752 }
753 len += sprintf(buf+len, " (%s)\n", (curcard->fairness)?"Unfair":"Fair");
754
755 len += sprintf(buf+len, "Ring Station Address: ");
756 len += sprintf(buf+len, "%2.2x", dev->dev_addr[0]);
757 for (i = 1; i < 6; i++)
758 len += sprintf(buf+len, " %2.2x", dev->dev_addr[i]);
759 len += sprintf(buf+len, "\n");
760 } else
761 len += sprintf(buf+len, "Card not configured\n");
762
763 return len;
764}
765
766static void __exit madgemc_exit(void)
767{
768 struct net_device *dev;
769 struct madgemc_card *this_card;
770
771 while (madgemc_card_list) {
772 dev = madgemc_card_list->dev;
773 unregister_netdev(dev);
774 release_region(dev->base_addr-MADGEMC_SIF_OFFSET, MADGEMC_IO_EXTENT);
775 free_irq(dev->irq, dev);
776 tmsdev_term(dev);
777 free_netdev(dev);
778 this_card = madgemc_card_list;
779 madgemc_card_list = this_card->next;
780 kfree(this_card);
781 }
782}
783
784module_init(madgemc_probe);
785module_exit(madgemc_exit);
786
787MODULE_LICENSE("GPL");
788
789
790/*
791 * Local variables:
792 * compile-command: "gcc -DMODVERSIONS -DMODULE -D__KERNEL__ -Wall -Wstrict-prototypes -O6 -fomit-frame-pointer -I/usr/src/linux/drivers/net/tokenring/ -c madgemc.c"
793 * alt-compile-command: "gcc -DMODULE -D__KERNEL__ -Wall -Wstrict-prototypes -O6 -fomit-frame-pointer -I/usr/src/linux/drivers/net/tokenring/ -c madgemc.c"
794 * c-set-style "K&R"
795 * c-indent-level: 8
796 * c-basic-offset: 8
797 * tab-width: 8
798 * End:
799 */
800
diff --git a/drivers/net/tokenring/madgemc.h b/drivers/net/tokenring/madgemc.h
new file mode 100644
index 000000000000..2dd822203809
--- /dev/null
+++ b/drivers/net/tokenring/madgemc.h
@@ -0,0 +1,70 @@
1/*
2 * madgemc.h: Header for the madgemc tms380tr module
3 *
4 * Authors:
5 * - Adam Fritzler <mid@auk.cx>
6 */
7
8#ifndef __LINUX_MADGEMC_H
9#define __LINUX_MADGEMC_H
10
11#ifdef __KERNEL__
12
13#define MADGEMC16_CARDNAME "Madge Smart 16/4 MC16 Ringnode"
14#define MADGEMC32_CARDNAME "Madge Smart 16/4 MC32 Ringnode"
15
16/*
17 * Bit definitions for the POS config registers
18 */
19#define MC16_POS0_ADDR1 0x20
20#define MC16_POS2_ADDR2 0x04
21#define MC16_POS3_ADDR3 0x20
22
23#define MC_CONTROL_REG0 ((long)-8) /* 0x00 */
24#define MC_CONTROL_REG1 ((long)-7) /* 0x01 */
25#define MC_ADAPTER_POS_REG0 ((long)-6) /* 0x02 */
26#define MC_ADAPTER_POS_REG1 ((long)-5) /* 0x03 */
27#define MC_ADAPTER_POS_REG2 ((long)-4) /* 0x04 */
28#define MC_ADAPTER_REG5_UNUSED ((long)-3) /* 0x05 */
29#define MC_ADAPTER_REG6_UNUSED ((long)-2) /* 0x06 */
30#define MC_CONTROL_REG7 ((long)-1) /* 0x07 */
31
32#define MC_CONTROL_REG0_UNKNOWN1 0x01
33#define MC_CONTROL_REG0_UNKNOWN2 0x02
34#define MC_CONTROL_REG0_SIFSEL 0x04
35#define MC_CONTROL_REG0_PAGE 0x08
36#define MC_CONTROL_REG0_TESTINTERRUPT 0x10
37#define MC_CONTROL_REG0_UNKNOWN20 0x20
38#define MC_CONTROL_REG0_SINTR 0x40
39#define MC_CONTROL_REG0_UNKNOWN80 0x80
40
41#define MC_CONTROL_REG1_SINTEN 0x01
42#define MC_CONTROL_REG1_BITOFDEATH 0x02
43#define MC_CONTROL_REG1_NSRESET 0x04
44#define MC_CONTROL_REG1_UNKNOWN8 0x08
45#define MC_CONTROL_REG1_UNKNOWN10 0x10
46#define MC_CONTROL_REG1_UNKNOWN20 0x20
47#define MC_CONTROL_REG1_SRSX 0x40
48#define MC_CONTROL_REG1_SPEED_SEL 0x80
49
50#define MC_CONTROL_REG7_CABLESTP 0x00
51#define MC_CONTROL_REG7_CABLEUTP 0x01
52
53/*
54 * ROM Page Zero
55 */
56#define MC_ROM_MANUFACTURERID 0x00
57#define MC_ROM_ADAPTERID 0x01
58#define MC_ROM_REVISION 0x02
59#define MC_ROM_CONFIG0 0x03
60#define MC_ROM_CONFIG1 0x04
61#define MC_ROM_CONFIG2 0x05
62
63/*
64 * ROM Page One
65 */
66#define MC_ROM_UNUSED_BYTE 0x00
67#define MC_ROM_BIA_START 0x01
68
69#endif /* __KERNEL__ */
70#endif /* __LINUX_MADGEMC_H */
diff --git a/drivers/net/tokenring/olympic.c b/drivers/net/tokenring/olympic.c
new file mode 100644
index 000000000000..9e7923192a49
--- /dev/null
+++ b/drivers/net/tokenring/olympic.c
@@ -0,0 +1,1786 @@
1/*
2 * olympic.c (c) 1999 Peter De Schrijver All Rights Reserved
3 * 1999/2000 Mike Phillips (mikep@linuxtr.net)
4 *
5 * Linux driver for IBM PCI tokenring cards based on the Pit/Pit-Phy/Olympic
6 * chipset.
7 *
8 * Base Driver Skeleton:
9 * Written 1993-94 by Donald Becker.
10 *
11 * Copyright 1993 United States Government as represented by the
12 * Director, National Security Agency.
13 *
14 * Thanks to Erik De Cock, Adrian Bridgett and Frank Fiene for their
15 * assistance and perserverance with the testing of this driver.
16 *
17 * This software may be used and distributed according to the terms
18 * of the GNU General Public License, incorporated herein by reference.
19 *
20 * 4/27/99 - Alpha Release 0.1.0
21 * First release to the public
22 *
23 * 6/8/99 - Official Release 0.2.0
24 * Merged into the kernel code
25 * 8/18/99 - Updated driver for 2.3.13 kernel to use new pci
26 * resource. Driver also reports the card name returned by
27 * the pci resource.
28 * 1/11/00 - Added spinlocks for smp
29 * 2/23/00 - Updated to dev_kfree_irq
30 * 3/10/00 - Fixed FDX enable which triggered other bugs also
31 * squashed.
32 * 5/20/00 - Changes to handle Olympic on LinuxPPC. Endian changes.
33 * The odd thing about the changes is that the fix for
34 * endian issues with the big-endian data in the arb, asb...
35 * was to always swab() the bytes, no matter what CPU.
36 * That's because the read[wl]() functions always swap the
37 * bytes on the way in on PPC.
38 * Fixing the hardware descriptors was another matter,
39 * because they weren't going through read[wl](), there all
40 * the results had to be in memory in le32 values. kdaaker
41 *
42 * 12/23/00 - Added minimal Cardbus support (Thanks Donald).
43 *
44 * 03/09/01 - Add new pci api, dev_base_lock, general clean up.
45 *
46 * 03/27/01 - Add new dma pci (Thanks to Kyle Lucke) and alloc_trdev
47 * Change proc_fs behaviour, now one entry per adapter.
48 *
49 * 04/09/01 - Couple of bug fixes to the dma unmaps and ejecting the
50 * adapter when live does not take the system down with it.
51 *
52 * 06/02/01 - Clean up, copy skb for small packets
53 *
54 * 06/22/01 - Add EISR error handling routines
55 *
56 * 07/19/01 - Improve bad LAA reporting, strip out freemem
57 * into a separate function, its called from 3
58 * different places now.
59 * 02/09/02 - Replaced sleep_on.
60 * 03/01/02 - Replace access to several registers from 32 bit to
61 * 16 bit. Fixes alignment errors on PPC 64 bit machines.
62 * Thanks to Al Trautman for this one.
63 * 03/10/02 - Fix BUG in arb_cmd. Bug was there all along but was
64 * silently ignored until the error checking code
65 * went into version 1.0.0
66 * 06/04/02 - Add correct start up sequence for the cardbus adapters.
67 * Required for strict compliance with pci power mgmt specs.
68 * To Do:
69 *
70 * Wake on lan
71 *
72 * If Problems do Occur
73 * Most problems can be rectified by either closing and opening the interface
74 * (ifconfig down and up) or rmmod and insmod'ing the driver (a bit difficult
75 * if compiled into the kernel).
76 */
77
78/* Change OLYMPIC_DEBUG to 1 to get verbose, and I mean really verbose, messages */
79
80#define OLYMPIC_DEBUG 0
81
82
83#include <linux/config.h>
84#include <linux/module.h>
85#include <linux/kernel.h>
86#include <linux/errno.h>
87#include <linux/timer.h>
88#include <linux/in.h>
89#include <linux/ioport.h>
90#include <linux/string.h>
91#include <linux/proc_fs.h>
92#include <linux/ptrace.h>
93#include <linux/skbuff.h>
94#include <linux/interrupt.h>
95#include <linux/delay.h>
96#include <linux/netdevice.h>
97#include <linux/trdevice.h>
98#include <linux/stddef.h>
99#include <linux/init.h>
100#include <linux/pci.h>
101#include <linux/spinlock.h>
102#include <linux/bitops.h>
103
104#include <net/checksum.h>
105
106#include <asm/io.h>
107#include <asm/system.h>
108
109#include "olympic.h"
110
111/* I've got to put some intelligence into the version number so that Peter and I know
112 * which version of the code somebody has got.
113 * Version Number = a.b.c.d where a.b.c is the level of code and d is the latest author.
114 * So 0.0.1.pds = Peter, 0.0.1.mlp = Mike
115 *
116 * Official releases will only have an a.b.c version number format.
117 */
118
119static char version[] __devinitdata =
120"Olympic.c v1.0.5 6/04/02 - Peter De Schrijver & Mike Phillips" ;
121
122static char *open_maj_error[] = {"No error", "Lobe Media Test", "Physical Insertion",
123 "Address Verification", "Neighbor Notification (Ring Poll)",
124 "Request Parameters","FDX Registration Request",
125 "FDX Duplicate Address Check", "Station registration Query Wait",
126 "Unknown stage"};
127
128static char *open_min_error[] = {"No error", "Function Failure", "Signal Lost", "Wire Fault",
129 "Ring Speed Mismatch", "Timeout","Ring Failure","Ring Beaconing",
130 "Duplicate Node Address","Request Parameters","Remove Received",
131 "Reserved", "Reserved", "No Monitor Detected for RPL",
132 "Monitor Contention failer for RPL", "FDX Protocol Error"};
133
134/* Module paramters */
135
136MODULE_AUTHOR("Mike Phillips <mikep@linuxtr.net>") ;
137MODULE_DESCRIPTION("Olympic PCI/Cardbus Chipset Driver") ;
138
139/* Ring Speed 0,4,16,100
140 * 0 = Autosense
141 * 4,16 = Selected speed only, no autosense
142 * This allows the card to be the first on the ring
143 * and become the active monitor.
144 * 100 = Nothing at present, 100mbps is autodetected
145 * if FDX is turned on. May be implemented in the future to
146 * fail if 100mpbs is not detected.
147 *
148 * WARNING: Some hubs will allow you to insert
149 * at the wrong speed
150 */
151
152static int ringspeed[OLYMPIC_MAX_ADAPTERS] = {0,} ;
153module_param_array(ringspeed, int, NULL, 0);
154
155/* Packet buffer size */
156
157static int pkt_buf_sz[OLYMPIC_MAX_ADAPTERS] = {0,} ;
158module_param_array(pkt_buf_sz, int, NULL, 0) ;
159
160/* Message Level */
161
162static int message_level[OLYMPIC_MAX_ADAPTERS] = {0,} ;
163module_param_array(message_level, int, NULL, 0) ;
164
165/* Change network_monitor to receive mac frames through the arb channel.
166 * Will also create a /proc/net/olympic_tr%d entry, where %d is the tr
167 * device, i.e. tr0, tr1 etc.
168 * Intended to be used to create a ring-error reporting network module
169 * i.e. it will give you the source address of beaconers on the ring
170 */
171static int network_monitor[OLYMPIC_MAX_ADAPTERS] = {0,};
172module_param_array(network_monitor, int, NULL, 0);
173
174static struct pci_device_id olympic_pci_tbl[] = {
175 {PCI_VENDOR_ID_IBM,PCI_DEVICE_ID_IBM_TR_WAKE,PCI_ANY_ID,PCI_ANY_ID,},
176 { } /* Terminating Entry */
177};
178MODULE_DEVICE_TABLE(pci,olympic_pci_tbl) ;
179
180
181static int olympic_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
182static int olympic_init(struct net_device *dev);
183static int olympic_open(struct net_device *dev);
184static int olympic_xmit(struct sk_buff *skb, struct net_device *dev);
185static int olympic_close(struct net_device *dev);
186static void olympic_set_rx_mode(struct net_device *dev);
187static void olympic_freemem(struct net_device *dev) ;
188static irqreturn_t olympic_interrupt(int irq, void *dev_id, struct pt_regs *regs);
189static struct net_device_stats * olympic_get_stats(struct net_device *dev);
190static int olympic_set_mac_address(struct net_device *dev, void *addr) ;
191static void olympic_arb_cmd(struct net_device *dev);
192static int olympic_change_mtu(struct net_device *dev, int mtu);
193static void olympic_srb_bh(struct net_device *dev) ;
194static void olympic_asb_bh(struct net_device *dev) ;
195static int olympic_proc_info(char *buffer, char **start, off_t offset, int length, int *eof, void *data) ;
196
197static int __devinit olympic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
198{
199 struct net_device *dev ;
200 struct olympic_private *olympic_priv;
201 static int card_no = -1 ;
202 int i ;
203
204 card_no++ ;
205
206 if ((i = pci_enable_device(pdev))) {
207 return i ;
208 }
209
210 pci_set_master(pdev);
211
212 if ((i = pci_request_regions(pdev,"olympic"))) {
213 goto op_disable_dev;
214 }
215
216 dev = alloc_trdev(sizeof(struct olympic_private)) ;
217 if (!dev) {
218 i = -ENOMEM;
219 goto op_free_dev;
220 }
221
222 olympic_priv = dev->priv ;
223
224 spin_lock_init(&olympic_priv->olympic_lock) ;
225
226 init_waitqueue_head(&olympic_priv->srb_wait);
227 init_waitqueue_head(&olympic_priv->trb_wait);
228#if OLYMPIC_DEBUG
229 printk(KERN_INFO "pci_device: %p, dev:%p, dev->priv: %p\n", pdev, dev, dev->priv);
230#endif
231 dev->irq=pdev->irq;
232 dev->base_addr=pci_resource_start(pdev, 0);
233 olympic_priv->olympic_card_name = pci_name(pdev);
234 olympic_priv->pdev = pdev;
235 olympic_priv->olympic_mmio = ioremap(pci_resource_start(pdev,1),256);
236 olympic_priv->olympic_lap = ioremap(pci_resource_start(pdev,2),2048);
237 if (!olympic_priv->olympic_mmio || !olympic_priv->olympic_lap) {
238 goto op_free_iomap;
239 }
240
241 if ((pkt_buf_sz[card_no] < 100) || (pkt_buf_sz[card_no] > 18000) )
242 olympic_priv->pkt_buf_sz = PKT_BUF_SZ ;
243 else
244 olympic_priv->pkt_buf_sz = pkt_buf_sz[card_no] ;
245
246 dev->mtu = olympic_priv->pkt_buf_sz - TR_HLEN ;
247 olympic_priv->olympic_ring_speed = ringspeed[card_no] ;
248 olympic_priv->olympic_message_level = message_level[card_no] ;
249 olympic_priv->olympic_network_monitor = network_monitor[card_no];
250
251 if ((i = olympic_init(dev))) {
252 goto op_free_iomap;
253 }
254
255 dev->open=&olympic_open;
256 dev->hard_start_xmit=&olympic_xmit;
257 dev->change_mtu=&olympic_change_mtu;
258 dev->stop=&olympic_close;
259 dev->do_ioctl=NULL;
260 dev->set_multicast_list=&olympic_set_rx_mode;
261 dev->get_stats=&olympic_get_stats ;
262 dev->set_mac_address=&olympic_set_mac_address ;
263 SET_MODULE_OWNER(dev) ;
264 SET_NETDEV_DEV(dev, &pdev->dev);
265
266 pci_set_drvdata(pdev,dev) ;
267 register_netdev(dev) ;
268 printk("Olympic: %s registered as: %s\n",olympic_priv->olympic_card_name,dev->name);
269 if (olympic_priv->olympic_network_monitor) { /* Must go after register_netdev as we need the device name */
270 char proc_name[20] ;
271 strcpy(proc_name,"net/olympic_") ;
272 strcat(proc_name,dev->name) ;
273 create_proc_read_entry(proc_name,0,NULL,olympic_proc_info,(void *)dev) ;
274 printk("Olympic: Network Monitor information: /proc/%s\n",proc_name);
275 }
276 return 0 ;
277
278op_free_iomap:
279 if (olympic_priv->olympic_mmio)
280 iounmap(olympic_priv->olympic_mmio);
281 if (olympic_priv->olympic_lap)
282 iounmap(olympic_priv->olympic_lap);
283
284op_free_dev:
285 free_netdev(dev);
286 pci_release_regions(pdev);
287
288op_disable_dev:
289 pci_disable_device(pdev);
290 return i;
291}
292
293static int __devinit olympic_init(struct net_device *dev)
294{
295 struct olympic_private *olympic_priv;
296 u8 __iomem *olympic_mmio, *init_srb,*adapter_addr;
297 unsigned long t;
298 unsigned int uaa_addr;
299
300 olympic_priv=(struct olympic_private *)dev->priv;
301 olympic_mmio=olympic_priv->olympic_mmio;
302
303 printk("%s \n", version);
304 printk("%s. I/O at %hx, MMIO at %p, LAP at %p, using irq %d\n", olympic_priv->olympic_card_name, (unsigned int) dev->base_addr,olympic_priv->olympic_mmio, olympic_priv->olympic_lap, dev->irq);
305
306 writel(readl(olympic_mmio+BCTL) | BCTL_SOFTRESET,olympic_mmio+BCTL);
307 t=jiffies;
308 while((readl(olympic_mmio+BCTL)) & BCTL_SOFTRESET) {
309 schedule();
310 if(jiffies-t > 40*HZ) {
311 printk(KERN_ERR "IBM PCI tokenring card not responding.\n");
312 return -ENODEV;
313 }
314 }
315
316
317 /* Needed for cardbus */
318 if(!(readl(olympic_mmio+BCTL) & BCTL_MODE_INDICATOR)) {
319 writel(readl(olympic_priv->olympic_mmio+FERMASK)|FERMASK_INT_BIT, olympic_mmio+FERMASK);
320 }
321
322#if OLYMPIC_DEBUG
323 printk("BCTL: %x\n",readl(olympic_mmio+BCTL));
324 printk("GPR: %x\n",readw(olympic_mmio+GPR));
325 printk("SISRMASK: %x\n",readl(olympic_mmio+SISR_MASK));
326#endif
327 /* Aaaahhh, You have got to be real careful setting GPR, the card
328 holds the previous values from flash memory, including autosense
329 and ring speed */
330
331 writel(readl(olympic_mmio+BCTL)|BCTL_MIMREB,olympic_mmio+BCTL);
332
333 if (olympic_priv->olympic_ring_speed == 0) { /* Autosense */
334 writew(readw(olympic_mmio+GPR)|GPR_AUTOSENSE,olympic_mmio+GPR);
335 if (olympic_priv->olympic_message_level)
336 printk(KERN_INFO "%s: Ringspeed autosense mode on\n",olympic_priv->olympic_card_name);
337 } else if (olympic_priv->olympic_ring_speed == 16) {
338 if (olympic_priv->olympic_message_level)
339 printk(KERN_INFO "%s: Trying to open at 16 Mbps as requested\n", olympic_priv->olympic_card_name);
340 writew(GPR_16MBPS, olympic_mmio+GPR);
341 } else if (olympic_priv->olympic_ring_speed == 4) {
342 if (olympic_priv->olympic_message_level)
343 printk(KERN_INFO "%s: Trying to open at 4 Mbps as requested\n", olympic_priv->olympic_card_name) ;
344 writew(0, olympic_mmio+GPR);
345 }
346
347 writew(readw(olympic_mmio+GPR)|GPR_NEPTUNE_BF,olympic_mmio+GPR);
348
349#if OLYMPIC_DEBUG
350 printk("GPR = %x\n",readw(olympic_mmio + GPR) ) ;
351#endif
352 /* Solo has been paused to meet the Cardbus power
353 * specs if the adapter is cardbus. Check to
354 * see its been paused and then restart solo. The
355 * adapter should set the pause bit within 1 second.
356 */
357
358 if(!(readl(olympic_mmio+BCTL) & BCTL_MODE_INDICATOR)) {
359 t=jiffies;
360 while (!readl(olympic_mmio+CLKCTL) & CLKCTL_PAUSE) {
361 schedule() ;
362 if(jiffies-t > 2*HZ) {
363 printk(KERN_ERR "IBM Cardbus tokenring adapter not responsing.\n") ;
364 return -ENODEV;
365 }
366 }
367 writel(readl(olympic_mmio+CLKCTL) & ~CLKCTL_PAUSE, olympic_mmio+CLKCTL) ;
368 }
369
370 /* start solo init */
371 writel((1<<15),olympic_mmio+SISR_MASK_SUM);
372
373 t=jiffies;
374 while(!((readl(olympic_mmio+SISR_RR)) & SISR_SRB_REPLY)) {
375 schedule();
376 if(jiffies-t > 15*HZ) {
377 printk(KERN_ERR "IBM PCI tokenring card not responding.\n");
378 return -ENODEV;
379 }
380 }
381
382 writel(readw(olympic_mmio+LAPWWO),olympic_mmio+LAPA);
383
384#if OLYMPIC_DEBUG
385 printk("LAPWWO: %x, LAPA: %x\n",readl(olympic_mmio+LAPWWO), readl(olympic_mmio+LAPA));
386#endif
387
388 init_srb=olympic_priv->olympic_lap + ((readw(olympic_mmio+LAPWWO)) & (~0xf800));
389
390#if OLYMPIC_DEBUG
391{
392 int i;
393 printk("init_srb(%p): ",init_srb);
394 for(i=0;i<20;i++)
395 printk("%x ",readb(init_srb+i));
396 printk("\n");
397}
398#endif
399 if(readw(init_srb+6)) {
400 printk(KERN_INFO "tokenring card initialization failed. errorcode : %x\n",readw(init_srb+6));
401 return -ENODEV;
402 }
403
404 if (olympic_priv->olympic_message_level) {
405 if ( readb(init_srb +2) & 0x40) {
406 printk(KERN_INFO "Olympic: Adapter is FDX capable.\n") ;
407 } else {
408 printk(KERN_INFO "Olympic: Adapter cannot do FDX.\n");
409 }
410 }
411
412 uaa_addr=swab16(readw(init_srb+8));
413
414#if OLYMPIC_DEBUG
415 printk("UAA resides at %x\n",uaa_addr);
416#endif
417
418 writel(uaa_addr,olympic_mmio+LAPA);
419 adapter_addr=olympic_priv->olympic_lap + (uaa_addr & (~0xf800));
420
421#if OLYMPIC_DEBUG
422 printk("adapter address: %02x:%02x:%02x:%02x:%02x:%02x\n",
423 readb(adapter_addr), readb(adapter_addr+1),readb(adapter_addr+2),
424 readb(adapter_addr+3),readb(adapter_addr+4),readb(adapter_addr+5));
425#endif
426
427 memcpy_fromio(&dev->dev_addr[0], adapter_addr,6);
428
429 olympic_priv->olympic_addr_table_addr = swab16(readw(init_srb + 12));
430 olympic_priv->olympic_parms_addr = swab16(readw(init_srb + 14));
431
432 return 0;
433
434}
435
436static int olympic_open(struct net_device *dev)
437{
438 struct olympic_private *olympic_priv=(struct olympic_private *)dev->priv;
439 u8 __iomem *olympic_mmio=olympic_priv->olympic_mmio,*init_srb;
440 unsigned long flags, t;
441 int i, open_finished = 1 ;
442 u8 resp, err;
443
444 DECLARE_WAITQUEUE(wait,current) ;
445
446 olympic_init(dev);
447
448 if(request_irq(dev->irq, &olympic_interrupt, SA_SHIRQ , "olympic", dev)) {
449 return -EAGAIN;
450 }
451
452#if OLYMPIC_DEBUG
453 printk("BMCTL: %x\n",readl(olympic_mmio+BMCTL_SUM));
454 printk("pending ints: %x\n",readl(olympic_mmio+SISR_RR));
455#endif
456
457 writel(SISR_MI,olympic_mmio+SISR_MASK_SUM);
458
459 writel(SISR_MI | SISR_SRB_REPLY, olympic_mmio+SISR_MASK); /* more ints later, doesn't stop arb cmd interrupt */
460
461 writel(LISR_LIE,olympic_mmio+LISR); /* more ints later */
462
463 /* adapter is closed, so SRB is pointed to by LAPWWO */
464
465 writel(readw(olympic_mmio+LAPWWO),olympic_mmio+LAPA);
466 init_srb=olympic_priv->olympic_lap + ((readw(olympic_mmio+LAPWWO)) & (~0xf800));
467
468#if OLYMPIC_DEBUG
469 printk("LAPWWO: %x, LAPA: %x\n",readw(olympic_mmio+LAPWWO), readl(olympic_mmio+LAPA));
470 printk("SISR Mask = %04x\n", readl(olympic_mmio+SISR_MASK));
471 printk("Before the open command \n");
472#endif
473 do {
474 memset_io(init_srb,0,SRB_COMMAND_SIZE);
475
476 writeb(SRB_OPEN_ADAPTER,init_srb) ; /* open */
477 writeb(OLYMPIC_CLEAR_RET_CODE,init_srb+2);
478
479 /* If Network Monitor, instruct card to copy MAC frames through the ARB */
480 if (olympic_priv->olympic_network_monitor)
481 writew(swab16(OPEN_ADAPTER_ENABLE_FDX | OPEN_ADAPTER_PASS_ADC_MAC | OPEN_ADAPTER_PASS_ATT_MAC | OPEN_ADAPTER_PASS_BEACON), init_srb+8);
482 else
483 writew(swab16(OPEN_ADAPTER_ENABLE_FDX), init_srb+8);
484
485 /* Test OR of first 3 bytes as its totally possible for
486 * someone to set the first 2 bytes to be zero, although this
487 * is an error, the first byte must have bit 6 set to 1 */
488
489 if (olympic_priv->olympic_laa[0] | olympic_priv->olympic_laa[1] | olympic_priv->olympic_laa[2]) {
490 writeb(olympic_priv->olympic_laa[0],init_srb+12);
491 writeb(olympic_priv->olympic_laa[1],init_srb+13);
492 writeb(olympic_priv->olympic_laa[2],init_srb+14);
493 writeb(olympic_priv->olympic_laa[3],init_srb+15);
494 writeb(olympic_priv->olympic_laa[4],init_srb+16);
495 writeb(olympic_priv->olympic_laa[5],init_srb+17);
496 memcpy(dev->dev_addr,olympic_priv->olympic_laa,dev->addr_len) ;
497 }
498 writeb(1,init_srb+30);
499
500 spin_lock_irqsave(&olympic_priv->olympic_lock,flags);
501 olympic_priv->srb_queued=1;
502
503 writel(LISR_SRB_CMD,olympic_mmio+LISR_SUM);
504 spin_unlock_irqrestore(&olympic_priv->olympic_lock,flags);
505
506 t = jiffies ;
507
508 add_wait_queue(&olympic_priv->srb_wait,&wait) ;
509 set_current_state(TASK_INTERRUPTIBLE) ;
510
511 while(olympic_priv->srb_queued) {
512 schedule() ;
513 if(signal_pending(current)) {
514 printk(KERN_WARNING "%s: Signal received in open.\n",
515 dev->name);
516 printk(KERN_WARNING "SISR=%x LISR=%x\n",
517 readl(olympic_mmio+SISR),
518 readl(olympic_mmio+LISR));
519 olympic_priv->srb_queued=0;
520 break;
521 }
522 if ((jiffies-t) > 10*HZ) {
523 printk(KERN_WARNING "%s: SRB timed out. \n",dev->name) ;
524 olympic_priv->srb_queued=0;
525 break ;
526 }
527 set_current_state(TASK_INTERRUPTIBLE) ;
528 }
529 remove_wait_queue(&olympic_priv->srb_wait,&wait) ;
530 set_current_state(TASK_RUNNING) ;
531 olympic_priv->srb_queued = 0 ;
532#if OLYMPIC_DEBUG
533 printk("init_srb(%p): ",init_srb);
534 for(i=0;i<20;i++)
535 printk("%02x ",readb(init_srb+i));
536 printk("\n");
537#endif
538
539 /* If we get the same return response as we set, the interrupt wasn't raised and the open
540 * timed out.
541 */
542
543 switch (resp = readb(init_srb+2)) {
544 case OLYMPIC_CLEAR_RET_CODE:
545 printk(KERN_WARNING "%s: Adapter Open time out or error.\n", dev->name) ;
546 goto out;
547 case 0:
548 open_finished = 1;
549 break;
550 case 0x07:
551 if (!olympic_priv->olympic_ring_speed && open_finished) { /* Autosense , first time around */
552 printk(KERN_WARNING "%s: Retrying at different ring speed \n", dev->name);
553 open_finished = 0 ;
554 continue;
555 }
556
557 err = readb(init_srb+7);
558
559 if (!olympic_priv->olympic_ring_speed && ((err & 0x0f) == 0x0d)) {
560 printk(KERN_WARNING "%s: Tried to autosense ring speed with no monitors present\n",dev->name);
561 printk(KERN_WARNING "%s: Please try again with a specified ring speed \n",dev->name);
562 } else {
563 printk(KERN_WARNING "%s: %s - %s\n", dev->name,
564 open_maj_error[(err & 0xf0) >> 4],
565 open_min_error[(err & 0x0f)]);
566 }
567 goto out;
568
569 case 0x32:
570 printk(KERN_WARNING "%s: Invalid LAA: %02x:%02x:%02x:%02x:%02x:%02x\n",
571 dev->name,
572 olympic_priv->olympic_laa[0],
573 olympic_priv->olympic_laa[1],
574 olympic_priv->olympic_laa[2],
575 olympic_priv->olympic_laa[3],
576 olympic_priv->olympic_laa[4],
577 olympic_priv->olympic_laa[5]) ;
578 goto out;
579
580 default:
581 printk(KERN_WARNING "%s: Bad OPEN response: %x\n", dev->name, resp);
582 goto out;
583
584 }
585 } while (!(open_finished)) ; /* Will only loop if ring speed mismatch re-open attempted && autosense is on */
586
587 if (readb(init_srb+18) & (1<<3))
588 if (olympic_priv->olympic_message_level)
589 printk(KERN_INFO "%s: Opened in FDX Mode\n",dev->name);
590
591 if (readb(init_srb+18) & (1<<1))
592 olympic_priv->olympic_ring_speed = 100 ;
593 else if (readb(init_srb+18) & 1)
594 olympic_priv->olympic_ring_speed = 16 ;
595 else
596 olympic_priv->olympic_ring_speed = 4 ;
597
598 if (olympic_priv->olympic_message_level)
599 printk(KERN_INFO "%s: Opened in %d Mbps mode\n",dev->name, olympic_priv->olympic_ring_speed);
600
601 olympic_priv->asb = swab16(readw(init_srb+8));
602 olympic_priv->srb = swab16(readw(init_srb+10));
603 olympic_priv->arb = swab16(readw(init_srb+12));
604 olympic_priv->trb = swab16(readw(init_srb+16));
605
606 olympic_priv->olympic_receive_options = 0x01 ;
607 olympic_priv->olympic_copy_all_options = 0 ;
608
609 /* setup rx ring */
610
611 writel((3<<16),olympic_mmio+BMCTL_RWM); /* Ensure end of frame generated interrupts */
612
613 writel(BMCTL_RX_DIS|3,olympic_mmio+BMCTL_RWM); /* Yes, this the enables RX channel */
614
615 for(i=0;i<OLYMPIC_RX_RING_SIZE;i++) {
616
617 struct sk_buff *skb;
618
619 skb=dev_alloc_skb(olympic_priv->pkt_buf_sz);
620 if(skb == NULL)
621 break;
622
623 skb->dev = dev;
624
625 olympic_priv->olympic_rx_ring[i].buffer = cpu_to_le32(pci_map_single(olympic_priv->pdev,
626 skb->data,olympic_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE)) ;
627 olympic_priv->olympic_rx_ring[i].res_length = cpu_to_le32(olympic_priv->pkt_buf_sz);
628 olympic_priv->rx_ring_skb[i]=skb;
629 }
630
631 if (i==0) {
632 printk(KERN_WARNING "%s: Not enough memory to allocate rx buffers. Adapter disabled\n",dev->name);
633 goto out;
634 }
635
636 olympic_priv->rx_ring_dma_addr = pci_map_single(olympic_priv->pdev,olympic_priv->olympic_rx_ring,
637 sizeof(struct olympic_rx_desc) * OLYMPIC_RX_RING_SIZE, PCI_DMA_TODEVICE);
638 writel(olympic_priv->rx_ring_dma_addr, olympic_mmio+RXDESCQ);
639 writel(olympic_priv->rx_ring_dma_addr, olympic_mmio+RXCDA);
640 writew(i, olympic_mmio+RXDESCQCNT);
641
642 olympic_priv->rx_status_ring_dma_addr = pci_map_single(olympic_priv->pdev, olympic_priv->olympic_rx_status_ring,
643 sizeof(struct olympic_rx_status) * OLYMPIC_RX_RING_SIZE, PCI_DMA_FROMDEVICE);
644 writel(olympic_priv->rx_status_ring_dma_addr, olympic_mmio+RXSTATQ);
645 writel(olympic_priv->rx_status_ring_dma_addr, olympic_mmio+RXCSA);
646
647 olympic_priv->rx_ring_last_received = OLYMPIC_RX_RING_SIZE - 1; /* last processed rx status */
648 olympic_priv->rx_status_last_received = OLYMPIC_RX_RING_SIZE - 1;
649
650 writew(i, olympic_mmio+RXSTATQCNT);
651
652#if OLYMPIC_DEBUG
653 printk("# of rx buffers: %d, RXENQ: %x\n",i, readw(olympic_mmio+RXENQ));
654 printk("RXCSA: %x, rx_status_ring[0]: %p\n",readl(olympic_mmio+RXCSA),&olympic_priv->olympic_rx_status_ring[0]);
655 printk(" stat_ring[1]: %p, stat_ring[2]: %p, stat_ring[3]: %p\n", &(olympic_priv->olympic_rx_status_ring[1]), &(olympic_priv->olympic_rx_status_ring[2]), &(olympic_priv->olympic_rx_status_ring[3]) );
656 printk(" stat_ring[4]: %p, stat_ring[5]: %p, stat_ring[6]: %p\n", &(olympic_priv->olympic_rx_status_ring[4]), &(olympic_priv->olympic_rx_status_ring[5]), &(olympic_priv->olympic_rx_status_ring[6]) );
657 printk(" stat_ring[7]: %p\n", &(olympic_priv->olympic_rx_status_ring[7]) );
658
659 printk("RXCDA: %x, rx_ring[0]: %p\n",readl(olympic_mmio+RXCDA),&olympic_priv->olympic_rx_ring[0]);
660 printk("Rx_ring_dma_addr = %08x, rx_status_dma_addr = %08x\n",
661 olympic_priv->rx_ring_dma_addr,olympic_priv->rx_status_ring_dma_addr) ;
662#endif
663
664 writew((((readw(olympic_mmio+RXENQ)) & 0x8000) ^ 0x8000) | i,olympic_mmio+RXENQ);
665
666#if OLYMPIC_DEBUG
667 printk("# of rx buffers: %d, RXENQ: %x\n",i, readw(olympic_mmio+RXENQ));
668 printk("RXCSA: %x, rx_ring[0]: %p\n",readl(olympic_mmio+RXCSA),&olympic_priv->olympic_rx_status_ring[0]);
669 printk("RXCDA: %x, rx_ring[0]: %p\n",readl(olympic_mmio+RXCDA),&olympic_priv->olympic_rx_ring[0]);
670#endif
671
672 writel(SISR_RX_STATUS | SISR_RX_NOBUF,olympic_mmio+SISR_MASK_SUM);
673
674 /* setup tx ring */
675
676 writel(BMCTL_TX1_DIS,olympic_mmio+BMCTL_RWM); /* Yes, this enables TX channel 1 */
677 for(i=0;i<OLYMPIC_TX_RING_SIZE;i++)
678 olympic_priv->olympic_tx_ring[i].buffer=0xdeadbeef;
679
680 olympic_priv->free_tx_ring_entries=OLYMPIC_TX_RING_SIZE;
681 olympic_priv->tx_ring_dma_addr = pci_map_single(olympic_priv->pdev,olympic_priv->olympic_tx_ring,
682 sizeof(struct olympic_tx_desc) * OLYMPIC_TX_RING_SIZE,PCI_DMA_TODEVICE) ;
683 writel(olympic_priv->tx_ring_dma_addr, olympic_mmio+TXDESCQ_1);
684 writel(olympic_priv->tx_ring_dma_addr, olympic_mmio+TXCDA_1);
685 writew(OLYMPIC_TX_RING_SIZE, olympic_mmio+TXDESCQCNT_1);
686
687 olympic_priv->tx_status_ring_dma_addr = pci_map_single(olympic_priv->pdev, olympic_priv->olympic_tx_status_ring,
688 sizeof(struct olympic_tx_status) * OLYMPIC_TX_RING_SIZE, PCI_DMA_FROMDEVICE);
689 writel(olympic_priv->tx_status_ring_dma_addr,olympic_mmio+TXSTATQ_1);
690 writel(olympic_priv->tx_status_ring_dma_addr,olympic_mmio+TXCSA_1);
691 writew(OLYMPIC_TX_RING_SIZE,olympic_mmio+TXSTATQCNT_1);
692
693 olympic_priv->tx_ring_free=0; /* next entry in tx ring to use */
694 olympic_priv->tx_ring_last_status=OLYMPIC_TX_RING_SIZE-1; /* last processed tx status */
695
696 writel(0xffffffff, olympic_mmio+EISR_RWM) ; /* clean the eisr */
697 writel(0,olympic_mmio+EISR) ;
698 writel(EISR_MASK_OPTIONS,olympic_mmio+EISR_MASK) ; /* enables most of the TX error interrupts */
699 writel(SISR_TX1_EOF | SISR_ADAPTER_CHECK | SISR_ARB_CMD | SISR_TRB_REPLY | SISR_ASB_FREE | SISR_ERR,olympic_mmio+SISR_MASK_SUM);
700
701#if OLYMPIC_DEBUG
702 printk("BMCTL: %x\n",readl(olympic_mmio+BMCTL_SUM));
703 printk("SISR MASK: %x\n",readl(olympic_mmio+SISR_MASK));
704#endif
705
706 if (olympic_priv->olympic_network_monitor) {
707 u8 __iomem *oat ;
708 u8 __iomem *opt ;
709 oat = (olympic_priv->olympic_lap + olympic_priv->olympic_addr_table_addr) ;
710 opt = (olympic_priv->olympic_lap + olympic_priv->olympic_parms_addr) ;
711
712 printk("%s: Node Address: %02x:%02x:%02x:%02x:%02x:%02x\n",dev->name,
713 readb(oat+offsetof(struct olympic_adapter_addr_table,node_addr)),
714 readb(oat+offsetof(struct olympic_adapter_addr_table,node_addr)+1),
715 readb(oat+offsetof(struct olympic_adapter_addr_table,node_addr)+2),
716 readb(oat+offsetof(struct olympic_adapter_addr_table,node_addr)+3),
717 readb(oat+offsetof(struct olympic_adapter_addr_table,node_addr)+4),
718 readb(oat+offsetof(struct olympic_adapter_addr_table,node_addr)+5));
719 printk("%s: Functional Address: %02x:%02x:%02x:%02x\n",dev->name,
720 readb(oat+offsetof(struct olympic_adapter_addr_table,func_addr)),
721 readb(oat+offsetof(struct olympic_adapter_addr_table,func_addr)+1),
722 readb(oat+offsetof(struct olympic_adapter_addr_table,func_addr)+2),
723 readb(oat+offsetof(struct olympic_adapter_addr_table,func_addr)+3));
724 printk("%s: NAUN Address: %02x:%02x:%02x:%02x:%02x:%02x\n",dev->name,
725 readb(opt+offsetof(struct olympic_parameters_table, up_node_addr)),
726 readb(opt+offsetof(struct olympic_parameters_table, up_node_addr)+1),
727 readb(opt+offsetof(struct olympic_parameters_table, up_node_addr)+2),
728 readb(opt+offsetof(struct olympic_parameters_table, up_node_addr)+3),
729 readb(opt+offsetof(struct olympic_parameters_table, up_node_addr)+4),
730 readb(opt+offsetof(struct olympic_parameters_table, up_node_addr)+5));
731 }
732
733 netif_start_queue(dev);
734 return 0;
735
736out:
737 free_irq(dev->irq, dev);
738 return -EIO;
739}
740
741/*
742 * When we enter the rx routine we do not know how many frames have been
743 * queued on the rx channel. Therefore we start at the next rx status
744 * position and travel around the receive ring until we have completed
745 * all the frames.
746 *
747 * This means that we may process the frame before we receive the end
748 * of frame interrupt. This is why we always test the status instead
749 * of blindly processing the next frame.
750 *
751 * We also remove the last 4 bytes from the packet as well, these are
752 * just token ring trailer info and upset protocols that don't check
753 * their own length, i.e. SNA.
754 *
755 */
756static void olympic_rx(struct net_device *dev)
757{
758 struct olympic_private *olympic_priv=(struct olympic_private *)dev->priv;
759 u8 __iomem *olympic_mmio=olympic_priv->olympic_mmio;
760 struct olympic_rx_status *rx_status;
761 struct olympic_rx_desc *rx_desc ;
762 int rx_ring_last_received,length, buffer_cnt, cpy_length, frag_len;
763 struct sk_buff *skb, *skb2;
764 int i;
765
766 rx_status=&(olympic_priv->olympic_rx_status_ring[(olympic_priv->rx_status_last_received + 1) & (OLYMPIC_RX_RING_SIZE - 1)]) ;
767
768 while (rx_status->status_buffercnt) {
769 u32 l_status_buffercnt;
770
771 olympic_priv->rx_status_last_received++ ;
772 olympic_priv->rx_status_last_received &= (OLYMPIC_RX_RING_SIZE -1);
773#if OLYMPIC_DEBUG
774 printk("rx status: %x rx len: %x \n", le32_to_cpu(rx_status->status_buffercnt), le32_to_cpu(rx_status->fragmentcnt_framelen));
775#endif
776 length = le32_to_cpu(rx_status->fragmentcnt_framelen) & 0xffff;
777 buffer_cnt = le32_to_cpu(rx_status->status_buffercnt) & 0xffff;
778 i = buffer_cnt ; /* Need buffer_cnt later for rxenq update */
779 frag_len = le32_to_cpu(rx_status->fragmentcnt_framelen) >> 16;
780
781#if OLYMPIC_DEBUG
782 printk("length: %x, frag_len: %x, buffer_cnt: %x\n", length, frag_len, buffer_cnt);
783#endif
784 l_status_buffercnt = le32_to_cpu(rx_status->status_buffercnt);
785 if(l_status_buffercnt & 0xC0000000) {
786 if (l_status_buffercnt & 0x3B000000) {
787 if (olympic_priv->olympic_message_level) {
788 if (l_status_buffercnt & (1<<29)) /* Rx Frame Truncated */
789 printk(KERN_WARNING "%s: Rx Frame Truncated \n",dev->name);
790 if (l_status_buffercnt & (1<<28)) /*Rx receive overrun */
791 printk(KERN_WARNING "%s: Rx Frame Receive overrun \n",dev->name);
792 if (l_status_buffercnt & (1<<27)) /* No receive buffers */
793 printk(KERN_WARNING "%s: No receive buffers \n",dev->name);
794 if (l_status_buffercnt & (1<<25)) /* Receive frame error detect */
795 printk(KERN_WARNING "%s: Receive frame error detect \n",dev->name);
796 if (l_status_buffercnt & (1<<24)) /* Received Error Detect */
797 printk(KERN_WARNING "%s: Received Error Detect \n",dev->name);
798 }
799 olympic_priv->rx_ring_last_received += i ;
800 olympic_priv->rx_ring_last_received &= (OLYMPIC_RX_RING_SIZE -1) ;
801 olympic_priv->olympic_stats.rx_errors++;
802 } else {
803
804 if (buffer_cnt == 1) {
805 skb = dev_alloc_skb(max_t(int, olympic_priv->pkt_buf_sz,length)) ;
806 } else {
807 skb = dev_alloc_skb(length) ;
808 }
809
810 if (skb == NULL) {
811 printk(KERN_WARNING "%s: Not enough memory to copy packet to upper layers. \n",dev->name) ;
812 olympic_priv->olympic_stats.rx_dropped++ ;
813 /* Update counters even though we don't transfer the frame */
814 olympic_priv->rx_ring_last_received += i ;
815 olympic_priv->rx_ring_last_received &= (OLYMPIC_RX_RING_SIZE -1) ;
816 } else {
817 skb->dev = dev ;
818
819 /* Optimise based upon number of buffers used.
820 If only one buffer is used we can simply swap the buffers around.
821 If more than one then we must use the new buffer and copy the information
822 first. Ideally all frames would be in a single buffer, this can be tuned by
823 altering the buffer size. If the length of the packet is less than
824 1500 bytes we're going to copy it over anyway to stop packets getting
825 dropped from sockets with buffers smaller than our pkt_buf_sz. */
826
827 if (buffer_cnt==1) {
828 olympic_priv->rx_ring_last_received++ ;
829 olympic_priv->rx_ring_last_received &= (OLYMPIC_RX_RING_SIZE -1);
830 rx_ring_last_received = olympic_priv->rx_ring_last_received ;
831 if (length > 1500) {
832 skb2=olympic_priv->rx_ring_skb[rx_ring_last_received] ;
833 /* unmap buffer */
834 pci_unmap_single(olympic_priv->pdev,
835 le32_to_cpu(olympic_priv->olympic_rx_ring[rx_ring_last_received].buffer),
836 olympic_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE) ;
837 skb_put(skb2,length-4);
838 skb2->protocol = tr_type_trans(skb2,dev);
839 olympic_priv->olympic_rx_ring[rx_ring_last_received].buffer =
840 cpu_to_le32(pci_map_single(olympic_priv->pdev, skb->data,
841 olympic_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE));
842 olympic_priv->olympic_rx_ring[rx_ring_last_received].res_length =
843 cpu_to_le32(olympic_priv->pkt_buf_sz);
844 olympic_priv->rx_ring_skb[rx_ring_last_received] = skb ;
845 netif_rx(skb2) ;
846 } else {
847 pci_dma_sync_single_for_cpu(olympic_priv->pdev,
848 le32_to_cpu(olympic_priv->olympic_rx_ring[rx_ring_last_received].buffer),
849 olympic_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE) ;
850 memcpy(skb_put(skb,length-4),olympic_priv->rx_ring_skb[rx_ring_last_received]->data,length-4) ;
851 pci_dma_sync_single_for_device(olympic_priv->pdev,
852 le32_to_cpu(olympic_priv->olympic_rx_ring[rx_ring_last_received].buffer),
853 olympic_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE) ;
854 skb->protocol = tr_type_trans(skb,dev) ;
855 netif_rx(skb) ;
856 }
857 } else {
858 do { /* Walk the buffers */
859 olympic_priv->rx_ring_last_received++ ;
860 olympic_priv->rx_ring_last_received &= (OLYMPIC_RX_RING_SIZE -1);
861 rx_ring_last_received = olympic_priv->rx_ring_last_received ;
862 pci_dma_sync_single_for_cpu(olympic_priv->pdev,
863 le32_to_cpu(olympic_priv->olympic_rx_ring[rx_ring_last_received].buffer),
864 olympic_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE) ;
865 rx_desc = &(olympic_priv->olympic_rx_ring[rx_ring_last_received]);
866 cpy_length = (i == 1 ? frag_len : le32_to_cpu(rx_desc->res_length));
867 memcpy(skb_put(skb, cpy_length), olympic_priv->rx_ring_skb[rx_ring_last_received]->data, cpy_length) ;
868 pci_dma_sync_single_for_device(olympic_priv->pdev,
869 le32_to_cpu(olympic_priv->olympic_rx_ring[rx_ring_last_received].buffer),
870 olympic_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE) ;
871 } while (--i) ;
872 skb_trim(skb,skb->len-4) ;
873 skb->protocol = tr_type_trans(skb,dev);
874 netif_rx(skb) ;
875 }
876 dev->last_rx = jiffies ;
877 olympic_priv->olympic_stats.rx_packets++ ;
878 olympic_priv->olympic_stats.rx_bytes += length ;
879 } /* if skb == null */
880 } /* If status & 0x3b */
881
882 } else { /*if buffercnt & 0xC */
883 olympic_priv->rx_ring_last_received += i ;
884 olympic_priv->rx_ring_last_received &= (OLYMPIC_RX_RING_SIZE - 1) ;
885 }
886
887 rx_status->fragmentcnt_framelen = 0 ;
888 rx_status->status_buffercnt = 0 ;
889 rx_status = &(olympic_priv->olympic_rx_status_ring[(olympic_priv->rx_status_last_received+1) & (OLYMPIC_RX_RING_SIZE -1) ]);
890
891 writew((((readw(olympic_mmio+RXENQ)) & 0x8000) ^ 0x8000) | buffer_cnt , olympic_mmio+RXENQ);
892 } /* while */
893
894}
895
896static void olympic_freemem(struct net_device *dev)
897{
898 struct olympic_private *olympic_priv=(struct olympic_private *)dev->priv;
899 int i;
900
901 for(i=0;i<OLYMPIC_RX_RING_SIZE;i++) {
902 if (olympic_priv->rx_ring_skb[olympic_priv->rx_status_last_received] != NULL) {
903 dev_kfree_skb_irq(olympic_priv->rx_ring_skb[olympic_priv->rx_status_last_received]);
904 olympic_priv->rx_ring_skb[olympic_priv->rx_status_last_received] = NULL;
905 }
906 if (olympic_priv->olympic_rx_ring[olympic_priv->rx_status_last_received].buffer != 0xdeadbeef) {
907 pci_unmap_single(olympic_priv->pdev,
908 le32_to_cpu(olympic_priv->olympic_rx_ring[olympic_priv->rx_status_last_received].buffer),
909 olympic_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE);
910 }
911 olympic_priv->rx_status_last_received++;
912 olympic_priv->rx_status_last_received&=OLYMPIC_RX_RING_SIZE-1;
913 }
914 /* unmap rings */
915 pci_unmap_single(olympic_priv->pdev, olympic_priv->rx_status_ring_dma_addr,
916 sizeof(struct olympic_rx_status) * OLYMPIC_RX_RING_SIZE, PCI_DMA_FROMDEVICE);
917 pci_unmap_single(olympic_priv->pdev, olympic_priv->rx_ring_dma_addr,
918 sizeof(struct olympic_rx_desc) * OLYMPIC_RX_RING_SIZE, PCI_DMA_TODEVICE);
919
920 pci_unmap_single(olympic_priv->pdev, olympic_priv->tx_status_ring_dma_addr,
921 sizeof(struct olympic_tx_status) * OLYMPIC_TX_RING_SIZE, PCI_DMA_FROMDEVICE);
922 pci_unmap_single(olympic_priv->pdev, olympic_priv->tx_ring_dma_addr,
923 sizeof(struct olympic_tx_desc) * OLYMPIC_TX_RING_SIZE, PCI_DMA_TODEVICE);
924
925 return ;
926}
927
928static irqreturn_t olympic_interrupt(int irq, void *dev_id, struct pt_regs *regs)
929{
930 struct net_device *dev= (struct net_device *)dev_id;
931 struct olympic_private *olympic_priv=(struct olympic_private *)dev->priv;
932 u8 __iomem *olympic_mmio=olympic_priv->olympic_mmio;
933 u32 sisr;
934 u8 __iomem *adapter_check_area ;
935
936 /*
937 * Read sisr but don't reset it yet.
938 * The indication bit may have been set but the interrupt latch
939 * bit may not be set, so we'd lose the interrupt later.
940 */
941 sisr=readl(olympic_mmio+SISR) ;
942 if (!(sisr & SISR_MI)) /* Interrupt isn't for us */
943 return IRQ_NONE;
944 sisr=readl(olympic_mmio+SISR_RR) ; /* Read & Reset sisr */
945
946 spin_lock(&olympic_priv->olympic_lock);
947
948 /* Hotswap gives us this on removal */
949 if (sisr == 0xffffffff) {
950 printk(KERN_WARNING "%s: Hotswap adapter removal.\n",dev->name) ;
951 spin_unlock(&olympic_priv->olympic_lock) ;
952 return IRQ_NONE;
953 }
954
955 if (sisr & (SISR_SRB_REPLY | SISR_TX1_EOF | SISR_RX_STATUS | SISR_ADAPTER_CHECK |
956 SISR_ASB_FREE | SISR_ARB_CMD | SISR_TRB_REPLY | SISR_RX_NOBUF | SISR_ERR)) {
957
958 /* If we ever get this the adapter is seriously dead. Only a reset is going to
959 * bring it back to life. We're talking pci bus errors and such like :( */
960 if((sisr & SISR_ERR) && (readl(olympic_mmio+EISR) & EISR_MASK_OPTIONS)) {
961 printk(KERN_ERR "Olympic: EISR Error, EISR=%08x\n",readl(olympic_mmio+EISR)) ;
962 printk(KERN_ERR "The adapter must be reset to clear this condition.\n") ;
963 printk(KERN_ERR "Please report this error to the driver maintainer and/\n") ;
964 printk(KERN_ERR "or the linux-tr mailing list.\n") ;
965 wake_up_interruptible(&olympic_priv->srb_wait);
966 spin_unlock(&olympic_priv->olympic_lock) ;
967 return IRQ_HANDLED;
968 } /* SISR_ERR */
969
970 if(sisr & SISR_SRB_REPLY) {
971 if(olympic_priv->srb_queued==1) {
972 wake_up_interruptible(&olympic_priv->srb_wait);
973 } else if (olympic_priv->srb_queued==2) {
974 olympic_srb_bh(dev) ;
975 }
976 olympic_priv->srb_queued=0;
977 } /* SISR_SRB_REPLY */
978
979 /* We shouldn't ever miss the Tx interrupt, but the you never know, hence the loop to ensure
980 we get all tx completions. */
981 if (sisr & SISR_TX1_EOF) {
982 while(olympic_priv->olympic_tx_status_ring[(olympic_priv->tx_ring_last_status + 1) & (OLYMPIC_TX_RING_SIZE-1)].status) {
983 olympic_priv->tx_ring_last_status++;
984 olympic_priv->tx_ring_last_status &= (OLYMPIC_TX_RING_SIZE-1);
985 olympic_priv->free_tx_ring_entries++;
986 olympic_priv->olympic_stats.tx_bytes += olympic_priv->tx_ring_skb[olympic_priv->tx_ring_last_status]->len;
987 olympic_priv->olympic_stats.tx_packets++ ;
988 pci_unmap_single(olympic_priv->pdev,
989 le32_to_cpu(olympic_priv->olympic_tx_ring[olympic_priv->tx_ring_last_status].buffer),
990 olympic_priv->tx_ring_skb[olympic_priv->tx_ring_last_status]->len,PCI_DMA_TODEVICE);
991 dev_kfree_skb_irq(olympic_priv->tx_ring_skb[olympic_priv->tx_ring_last_status]);
992 olympic_priv->olympic_tx_ring[olympic_priv->tx_ring_last_status].buffer=0xdeadbeef;
993 olympic_priv->olympic_tx_status_ring[olympic_priv->tx_ring_last_status].status=0;
994 }
995 netif_wake_queue(dev);
996 } /* SISR_TX1_EOF */
997
998 if (sisr & SISR_RX_STATUS) {
999 olympic_rx(dev);
1000 } /* SISR_RX_STATUS */
1001
1002 if (sisr & SISR_ADAPTER_CHECK) {
1003 netif_stop_queue(dev);
1004 printk(KERN_WARNING "%s: Adapter Check Interrupt Raised, 8 bytes of information follow:\n", dev->name);
1005 writel(readl(olympic_mmio+LAPWWC),olympic_mmio+LAPA);
1006 adapter_check_area = olympic_priv->olympic_lap + ((readl(olympic_mmio+LAPWWC)) & (~0xf800)) ;
1007 printk(KERN_WARNING "%s: Bytes %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",dev->name, readb(adapter_check_area+0), readb(adapter_check_area+1), readb(adapter_check_area+2), readb(adapter_check_area+3), readb(adapter_check_area+4), readb(adapter_check_area+5), readb(adapter_check_area+6), readb(adapter_check_area+7)) ;
1008 spin_unlock(&olympic_priv->olympic_lock) ;
1009 return IRQ_HANDLED;
1010 } /* SISR_ADAPTER_CHECK */
1011
1012 if (sisr & SISR_ASB_FREE) {
1013 /* Wake up anything that is waiting for the asb response */
1014 if (olympic_priv->asb_queued) {
1015 olympic_asb_bh(dev) ;
1016 }
1017 } /* SISR_ASB_FREE */
1018
1019 if (sisr & SISR_ARB_CMD) {
1020 olympic_arb_cmd(dev) ;
1021 } /* SISR_ARB_CMD */
1022
1023 if (sisr & SISR_TRB_REPLY) {
1024 /* Wake up anything that is waiting for the trb response */
1025 if (olympic_priv->trb_queued) {
1026 wake_up_interruptible(&olympic_priv->trb_wait);
1027 }
1028 olympic_priv->trb_queued = 0 ;
1029 } /* SISR_TRB_REPLY */
1030
1031 if (sisr & SISR_RX_NOBUF) {
1032 /* According to the documentation, we don't have to do anything, but trapping it keeps it out of
1033 /var/log/messages. */
1034 } /* SISR_RX_NOBUF */
1035 } else {
1036 printk(KERN_WARNING "%s: Unexpected interrupt: %x\n",dev->name, sisr);
1037 printk(KERN_WARNING "%s: SISR_MASK: %x\n",dev->name, readl(olympic_mmio+SISR_MASK)) ;
1038 } /* One if the interrupts we want */
1039 writel(SISR_MI,olympic_mmio+SISR_MASK_SUM);
1040
1041 spin_unlock(&olympic_priv->olympic_lock) ;
1042 return IRQ_HANDLED;
1043}
1044
1045static int olympic_xmit(struct sk_buff *skb, struct net_device *dev)
1046{
1047 struct olympic_private *olympic_priv=(struct olympic_private *)dev->priv;
1048 u8 __iomem *olympic_mmio=olympic_priv->olympic_mmio;
1049 unsigned long flags ;
1050
1051 spin_lock_irqsave(&olympic_priv->olympic_lock, flags);
1052
1053 netif_stop_queue(dev);
1054
1055 if(olympic_priv->free_tx_ring_entries) {
1056 olympic_priv->olympic_tx_ring[olympic_priv->tx_ring_free].buffer =
1057 cpu_to_le32(pci_map_single(olympic_priv->pdev, skb->data, skb->len,PCI_DMA_TODEVICE));
1058 olympic_priv->olympic_tx_ring[olympic_priv->tx_ring_free].status_length = cpu_to_le32(skb->len | (0x80000000));
1059 olympic_priv->tx_ring_skb[olympic_priv->tx_ring_free]=skb;
1060 olympic_priv->free_tx_ring_entries--;
1061
1062 olympic_priv->tx_ring_free++;
1063 olympic_priv->tx_ring_free &= (OLYMPIC_TX_RING_SIZE-1);
1064 writew((((readw(olympic_mmio+TXENQ_1)) & 0x8000) ^ 0x8000) | 1,olympic_mmio+TXENQ_1);
1065 netif_wake_queue(dev);
1066 spin_unlock_irqrestore(&olympic_priv->olympic_lock,flags);
1067 return 0;
1068 } else {
1069 spin_unlock_irqrestore(&olympic_priv->olympic_lock,flags);
1070 return 1;
1071 }
1072
1073}
1074
1075
1076static int olympic_close(struct net_device *dev)
1077{
1078 struct olympic_private *olympic_priv=(struct olympic_private *)dev->priv;
1079 u8 __iomem *olympic_mmio=olympic_priv->olympic_mmio,*srb;
1080 unsigned long t,flags;
1081
1082 DECLARE_WAITQUEUE(wait,current) ;
1083
1084 netif_stop_queue(dev);
1085
1086 writel(olympic_priv->srb,olympic_mmio+LAPA);
1087 srb=olympic_priv->olympic_lap + (olympic_priv->srb & (~0xf800));
1088
1089 writeb(SRB_CLOSE_ADAPTER,srb+0);
1090 writeb(0,srb+1);
1091 writeb(OLYMPIC_CLEAR_RET_CODE,srb+2);
1092
1093 add_wait_queue(&olympic_priv->srb_wait,&wait) ;
1094 set_current_state(TASK_INTERRUPTIBLE) ;
1095
1096 spin_lock_irqsave(&olympic_priv->olympic_lock,flags);
1097 olympic_priv->srb_queued=1;
1098
1099 writel(LISR_SRB_CMD,olympic_mmio+LISR_SUM);
1100 spin_unlock_irqrestore(&olympic_priv->olympic_lock,flags);
1101
1102 while(olympic_priv->srb_queued) {
1103
1104 t = schedule_timeout(60*HZ);
1105
1106 if(signal_pending(current)) {
1107 printk(KERN_WARNING "%s: SRB timed out.\n",dev->name);
1108 printk(KERN_WARNING "SISR=%x MISR=%x\n",readl(olympic_mmio+SISR),readl(olympic_mmio+LISR));
1109 olympic_priv->srb_queued=0;
1110 break;
1111 }
1112
1113 if (t == 0) {
1114 printk(KERN_WARNING "%s: SRB timed out. May not be fatal. \n",dev->name) ;
1115 }
1116 olympic_priv->srb_queued=0;
1117 }
1118 remove_wait_queue(&olympic_priv->srb_wait,&wait) ;
1119
1120 olympic_priv->rx_status_last_received++;
1121 olympic_priv->rx_status_last_received&=OLYMPIC_RX_RING_SIZE-1;
1122
1123 olympic_freemem(dev) ;
1124
1125 /* reset tx/rx fifo's and busmaster logic */
1126
1127 writel(readl(olympic_mmio+BCTL)|(3<<13),olympic_mmio+BCTL);
1128 udelay(1);
1129 writel(readl(olympic_mmio+BCTL)&~(3<<13),olympic_mmio+BCTL);
1130
1131#if OLYMPIC_DEBUG
1132 {
1133 int i ;
1134 printk("srb(%p): ",srb);
1135 for(i=0;i<4;i++)
1136 printk("%x ",readb(srb+i));
1137 printk("\n");
1138 }
1139#endif
1140 free_irq(dev->irq,dev);
1141
1142 return 0;
1143
1144}
1145
1146static void olympic_set_rx_mode(struct net_device *dev)
1147{
1148 struct olympic_private *olympic_priv = (struct olympic_private *) dev->priv ;
1149 u8 __iomem *olympic_mmio = olympic_priv->olympic_mmio ;
1150 u8 options = 0;
1151 u8 __iomem *srb;
1152 struct dev_mc_list *dmi ;
1153 unsigned char dev_mc_address[4] ;
1154 int i ;
1155
1156 writel(olympic_priv->srb,olympic_mmio+LAPA);
1157 srb=olympic_priv->olympic_lap + (olympic_priv->srb & (~0xf800));
1158 options = olympic_priv->olympic_copy_all_options;
1159
1160 if (dev->flags&IFF_PROMISC)
1161 options |= 0x61 ;
1162 else
1163 options &= ~0x61 ;
1164
1165 /* Only issue the srb if there is a change in options */
1166
1167 if ((options ^ olympic_priv->olympic_copy_all_options)) {
1168
1169 /* Now to issue the srb command to alter the copy.all.options */
1170
1171 writeb(SRB_MODIFY_RECEIVE_OPTIONS,srb);
1172 writeb(0,srb+1);
1173 writeb(OLYMPIC_CLEAR_RET_CODE,srb+2);
1174 writeb(0,srb+3);
1175 writeb(olympic_priv->olympic_receive_options,srb+4);
1176 writeb(options,srb+5);
1177
1178 olympic_priv->srb_queued=2; /* Can't sleep, use srb_bh */
1179
1180 writel(LISR_SRB_CMD,olympic_mmio+LISR_SUM);
1181
1182 olympic_priv->olympic_copy_all_options = options ;
1183
1184 return ;
1185 }
1186
1187 /* Set the functional addresses we need for multicast */
1188
1189 dev_mc_address[0] = dev_mc_address[1] = dev_mc_address[2] = dev_mc_address[3] = 0 ;
1190
1191 for (i=0,dmi=dev->mc_list;i < dev->mc_count; i++,dmi = dmi->next) {
1192 dev_mc_address[0] |= dmi->dmi_addr[2] ;
1193 dev_mc_address[1] |= dmi->dmi_addr[3] ;
1194 dev_mc_address[2] |= dmi->dmi_addr[4] ;
1195 dev_mc_address[3] |= dmi->dmi_addr[5] ;
1196 }
1197
1198 writeb(SRB_SET_FUNC_ADDRESS,srb+0);
1199 writeb(0,srb+1);
1200 writeb(OLYMPIC_CLEAR_RET_CODE,srb+2);
1201 writeb(0,srb+3);
1202 writeb(0,srb+4);
1203 writeb(0,srb+5);
1204 writeb(dev_mc_address[0],srb+6);
1205 writeb(dev_mc_address[1],srb+7);
1206 writeb(dev_mc_address[2],srb+8);
1207 writeb(dev_mc_address[3],srb+9);
1208
1209 olympic_priv->srb_queued = 2 ;
1210 writel(LISR_SRB_CMD,olympic_mmio+LISR_SUM);
1211
1212}
1213
1214static void olympic_srb_bh(struct net_device *dev)
1215{
1216 struct olympic_private *olympic_priv = (struct olympic_private *) dev->priv ;
1217 u8 __iomem *olympic_mmio = olympic_priv->olympic_mmio ;
1218 u8 __iomem *srb;
1219
1220 writel(olympic_priv->srb,olympic_mmio+LAPA);
1221 srb=olympic_priv->olympic_lap + (olympic_priv->srb & (~0xf800));
1222
1223 switch (readb(srb)) {
1224
1225 /* SRB_MODIFY_RECEIVE_OPTIONS i.e. set_multicast_list options (promiscuous)
1226 * At some point we should do something if we get an error, such as
1227 * resetting the IFF_PROMISC flag in dev
1228 */
1229
1230 case SRB_MODIFY_RECEIVE_OPTIONS:
1231 switch (readb(srb+2)) {
1232 case 0x01:
1233 printk(KERN_WARNING "%s: Unrecognized srb command\n",dev->name) ;
1234 break ;
1235 case 0x04:
1236 printk(KERN_WARNING "%s: Adapter must be open for this operation, doh!!\n",dev->name);
1237 break ;
1238 default:
1239 if (olympic_priv->olympic_message_level)
1240 printk(KERN_WARNING "%s: Receive Options Modified to %x,%x\n",dev->name,olympic_priv->olympic_copy_all_options, olympic_priv->olympic_receive_options) ;
1241 break ;
1242 } /* switch srb[2] */
1243 break ;
1244
1245 /* SRB_SET_GROUP_ADDRESS - Multicast group setting
1246 */
1247
1248 case SRB_SET_GROUP_ADDRESS:
1249 switch (readb(srb+2)) {
1250 case 0x00:
1251 break ;
1252 case 0x01:
1253 printk(KERN_WARNING "%s: Unrecognized srb command \n",dev->name) ;
1254 break ;
1255 case 0x04:
1256 printk(KERN_WARNING "%s: Adapter must be open for this operation, doh!!\n",dev->name);
1257 break ;
1258 case 0x3c:
1259 printk(KERN_WARNING "%s: Group/Functional address indicator bits not set correctly\n",dev->name) ;
1260 break ;
1261 case 0x3e: /* If we ever implement individual multicast addresses, will need to deal with this */
1262 printk(KERN_WARNING "%s: Group address registers full\n",dev->name) ;
1263 break ;
1264 case 0x55:
1265 printk(KERN_INFO "%s: Group Address already set.\n",dev->name) ;
1266 break ;
1267 default:
1268 break ;
1269 } /* switch srb[2] */
1270 break ;
1271
1272 /* SRB_RESET_GROUP_ADDRESS - Remove a multicast address from group list
1273 */
1274
1275 case SRB_RESET_GROUP_ADDRESS:
1276 switch (readb(srb+2)) {
1277 case 0x00:
1278 break ;
1279 case 0x01:
1280 printk(KERN_WARNING "%s: Unrecognized srb command \n",dev->name) ;
1281 break ;
1282 case 0x04:
1283 printk(KERN_WARNING "%s: Adapter must be open for this operation, doh!!\n",dev->name) ;
1284 break ;
1285 case 0x39: /* Must deal with this if individual multicast addresses used */
1286 printk(KERN_INFO "%s: Group address not found \n",dev->name);
1287 break ;
1288 default:
1289 break ;
1290 } /* switch srb[2] */
1291 break ;
1292
1293
1294 /* SRB_SET_FUNC_ADDRESS - Called by the set_rx_mode
1295 */
1296
1297 case SRB_SET_FUNC_ADDRESS:
1298 switch (readb(srb+2)) {
1299 case 0x00:
1300 if (olympic_priv->olympic_message_level)
1301 printk(KERN_INFO "%s: Functional Address Mask Set \n",dev->name) ;
1302 break ;
1303 case 0x01:
1304 printk(KERN_WARNING "%s: Unrecognized srb command \n",dev->name) ;
1305 break ;
1306 case 0x04:
1307 printk(KERN_WARNING "%s: Adapter must be open for this operation, doh!!\n",dev->name) ;
1308 break ;
1309 default:
1310 break ;
1311 } /* switch srb[2] */
1312 break ;
1313
1314 /* SRB_READ_LOG - Read and reset the adapter error counters
1315 */
1316
1317 case SRB_READ_LOG:
1318 switch (readb(srb+2)) {
1319 case 0x00:
1320 if (olympic_priv->olympic_message_level)
1321 printk(KERN_INFO "%s: Read Log issued\n",dev->name) ;
1322 break ;
1323 case 0x01:
1324 printk(KERN_WARNING "%s: Unrecognized srb command \n",dev->name) ;
1325 break ;
1326 case 0x04:
1327 printk(KERN_WARNING "%s: Adapter must be open for this operation, doh!!\n",dev->name) ;
1328 break ;
1329
1330 } /* switch srb[2] */
1331 break ;
1332
1333 /* SRB_READ_SR_COUNTERS - Read and reset the source routing bridge related counters */
1334
1335 case SRB_READ_SR_COUNTERS:
1336 switch (readb(srb+2)) {
1337 case 0x00:
1338 if (olympic_priv->olympic_message_level)
1339 printk(KERN_INFO "%s: Read Source Routing Counters issued\n",dev->name) ;
1340 break ;
1341 case 0x01:
1342 printk(KERN_WARNING "%s: Unrecognized srb command \n",dev->name) ;
1343 break ;
1344 case 0x04:
1345 printk(KERN_WARNING "%s: Adapter must be open for this operation, doh!!\n",dev->name) ;
1346 break ;
1347 default:
1348 break ;
1349 } /* switch srb[2] */
1350 break ;
1351
1352 default:
1353 printk(KERN_WARNING "%s: Unrecognized srb bh return value.\n",dev->name);
1354 break ;
1355 } /* switch srb[0] */
1356
1357}
1358
1359static struct net_device_stats * olympic_get_stats(struct net_device *dev)
1360{
1361 struct olympic_private *olympic_priv ;
1362 olympic_priv=(struct olympic_private *) dev->priv;
1363 return (struct net_device_stats *) &olympic_priv->olympic_stats;
1364}
1365
1366static int olympic_set_mac_address (struct net_device *dev, void *addr)
1367{
1368 struct sockaddr *saddr = addr ;
1369 struct olympic_private *olympic_priv = (struct olympic_private *)dev->priv ;
1370
1371 if (netif_running(dev)) {
1372 printk(KERN_WARNING "%s: Cannot set mac/laa address while card is open\n", dev->name) ;
1373 return -EIO ;
1374 }
1375
1376 memcpy(olympic_priv->olympic_laa, saddr->sa_data,dev->addr_len) ;
1377
1378 if (olympic_priv->olympic_message_level) {
1379 printk(KERN_INFO "%s: MAC/LAA Set to = %x.%x.%x.%x.%x.%x\n",dev->name, olympic_priv->olympic_laa[0],
1380 olympic_priv->olympic_laa[1], olympic_priv->olympic_laa[2],
1381 olympic_priv->olympic_laa[3], olympic_priv->olympic_laa[4],
1382 olympic_priv->olympic_laa[5]);
1383 }
1384
1385 return 0 ;
1386}
1387
1388static void olympic_arb_cmd(struct net_device *dev)
1389{
1390 struct olympic_private *olympic_priv = (struct olympic_private *) dev->priv;
1391 u8 __iomem *olympic_mmio=olympic_priv->olympic_mmio;
1392 u8 __iomem *arb_block, *asb_block, *srb ;
1393 u8 header_len ;
1394 u16 frame_len, buffer_len ;
1395 struct sk_buff *mac_frame ;
1396 u8 __iomem *buf_ptr ;
1397 u8 __iomem *frame_data ;
1398 u16 buff_off ;
1399 u16 lan_status = 0, lan_status_diff ; /* Initialize to stop compiler warning */
1400 u8 fdx_prot_error ;
1401 u16 next_ptr;
1402
1403 arb_block = (olympic_priv->olympic_lap + olympic_priv->arb) ;
1404 asb_block = (olympic_priv->olympic_lap + olympic_priv->asb) ;
1405 srb = (olympic_priv->olympic_lap + olympic_priv->srb) ;
1406
1407 if (readb(arb_block+0) == ARB_RECEIVE_DATA) { /* Receive.data, MAC frames */
1408
1409 header_len = readb(arb_block+8) ; /* 802.5 Token-Ring Header Length */
1410 frame_len = swab16(readw(arb_block + 10)) ;
1411
1412 buff_off = swab16(readw(arb_block + 6)) ;
1413
1414 buf_ptr = olympic_priv->olympic_lap + buff_off ;
1415
1416#if OLYMPIC_DEBUG
1417{
1418 int i;
1419 frame_data = buf_ptr+offsetof(struct mac_receive_buffer,frame_data) ;
1420
1421 for (i=0 ; i < 14 ; i++) {
1422 printk("Loc %d = %02x\n",i,readb(frame_data + i));
1423 }
1424
1425 printk("next %04x, fs %02x, len %04x \n",readw(buf_ptr+offsetof(struct mac_receive_buffer,next)), readb(buf_ptr+offsetof(struct mac_receive_buffer,frame_status)), readw(buf_ptr+offsetof(struct mac_receive_buffer,buffer_length)));
1426}
1427#endif
1428 mac_frame = dev_alloc_skb(frame_len) ;
1429 if (!mac_frame) {
1430 printk(KERN_WARNING "%s: Memory squeeze, dropping frame.\n", dev->name);
1431 goto drop_frame;
1432 }
1433
1434 /* Walk the buffer chain, creating the frame */
1435
1436 do {
1437 frame_data = buf_ptr+offsetof(struct mac_receive_buffer,frame_data) ;
1438 buffer_len = swab16(readw(buf_ptr+offsetof(struct mac_receive_buffer,buffer_length)));
1439 memcpy_fromio(skb_put(mac_frame, buffer_len), frame_data , buffer_len ) ;
1440 next_ptr=readw(buf_ptr+offsetof(struct mac_receive_buffer,next));
1441 } while (next_ptr && (buf_ptr=olympic_priv->olympic_lap + ntohs(next_ptr)));
1442
1443 if (olympic_priv->olympic_network_monitor) {
1444 struct trh_hdr *mac_hdr ;
1445 printk(KERN_WARNING "%s: Received MAC Frame, details: \n",dev->name) ;
1446 mac_hdr = (struct trh_hdr *)mac_frame->data ;
1447 printk(KERN_WARNING "%s: MAC Frame Dest. Addr: %02x:%02x:%02x:%02x:%02x:%02x \n", dev->name , mac_hdr->daddr[0], mac_hdr->daddr[1], mac_hdr->daddr[2], mac_hdr->daddr[3], mac_hdr->daddr[4], mac_hdr->daddr[5]) ;
1448 printk(KERN_WARNING "%s: MAC Frame Srce. Addr: %02x:%02x:%02x:%02x:%02x:%02x \n", dev->name , mac_hdr->saddr[0], mac_hdr->saddr[1], mac_hdr->saddr[2], mac_hdr->saddr[3], mac_hdr->saddr[4], mac_hdr->saddr[5]) ;
1449 }
1450 mac_frame->dev = dev ;
1451 mac_frame->protocol = tr_type_trans(mac_frame,dev);
1452 netif_rx(mac_frame) ;
1453 dev->last_rx = jiffies;
1454
1455drop_frame:
1456 /* Now tell the card we have dealt with the received frame */
1457
1458 /* Set LISR Bit 1 */
1459 writel(LISR_ARB_FREE,olympic_priv->olympic_mmio + LISR_SUM);
1460
1461 /* Is the ASB free ? */
1462
1463 if (readb(asb_block + 2) != 0xff) {
1464 olympic_priv->asb_queued = 1 ;
1465 writel(LISR_ASB_FREE_REQ,olympic_priv->olympic_mmio+LISR_SUM);
1466 return ;
1467 /* Drop out and wait for the bottom half to be run */
1468 }
1469
1470 writeb(ASB_RECEIVE_DATA,asb_block); /* Receive data */
1471 writeb(OLYMPIC_CLEAR_RET_CODE,asb_block+2); /* Necessary ?? */
1472 writeb(readb(arb_block+6),asb_block+6); /* Must send the address back to the adapter */
1473 writeb(readb(arb_block+7),asb_block+7); /* To let it know we have dealt with the data */
1474
1475 writel(LISR_ASB_REPLY | LISR_ASB_FREE_REQ,olympic_priv->olympic_mmio+LISR_SUM);
1476
1477 olympic_priv->asb_queued = 2 ;
1478
1479 return ;
1480
1481 } else if (readb(arb_block) == ARB_LAN_CHANGE_STATUS) { /* Lan.change.status */
1482 lan_status = swab16(readw(arb_block+6));
1483 fdx_prot_error = readb(arb_block+8) ;
1484
1485 /* Issue ARB Free */
1486 writel(LISR_ARB_FREE,olympic_priv->olympic_mmio+LISR_SUM);
1487
1488 lan_status_diff = olympic_priv->olympic_lan_status ^ lan_status ;
1489
1490 if (lan_status_diff & (LSC_LWF | LSC_ARW | LSC_FPE | LSC_RR) ) {
1491 if (lan_status_diff & LSC_LWF)
1492 printk(KERN_WARNING "%s: Short circuit detected on the lobe\n",dev->name);
1493 if (lan_status_diff & LSC_ARW)
1494 printk(KERN_WARNING "%s: Auto removal error\n",dev->name);
1495 if (lan_status_diff & LSC_FPE)
1496 printk(KERN_WARNING "%s: FDX Protocol Error\n",dev->name);
1497 if (lan_status_diff & LSC_RR)
1498 printk(KERN_WARNING "%s: Force remove MAC frame received\n",dev->name);
1499
1500 /* Adapter has been closed by the hardware */
1501
1502 /* reset tx/rx fifo's and busmaster logic */
1503
1504 writel(readl(olympic_mmio+BCTL)|(3<<13),olympic_mmio+BCTL);
1505 udelay(1);
1506 writel(readl(olympic_mmio+BCTL)&~(3<<13),olympic_mmio+BCTL);
1507 netif_stop_queue(dev);
1508 olympic_priv->srb = readw(olympic_priv->olympic_lap + LAPWWO) ;
1509 printk(KERN_WARNING "%s: Adapter has been closed \n", dev->name) ;
1510 } /* If serious error */
1511
1512 if (olympic_priv->olympic_message_level) {
1513 if (lan_status_diff & LSC_SIG_LOSS)
1514 printk(KERN_WARNING "%s: No receive signal detected \n", dev->name) ;
1515 if (lan_status_diff & LSC_HARD_ERR)
1516 printk(KERN_INFO "%s: Beaconing \n",dev->name);
1517 if (lan_status_diff & LSC_SOFT_ERR)
1518 printk(KERN_WARNING "%s: Adapter transmitted Soft Error Report Mac Frame \n",dev->name);
1519 if (lan_status_diff & LSC_TRAN_BCN)
1520 printk(KERN_INFO "%s: We are tranmitting the beacon, aaah\n",dev->name);
1521 if (lan_status_diff & LSC_SS)
1522 printk(KERN_INFO "%s: Single Station on the ring \n", dev->name);
1523 if (lan_status_diff & LSC_RING_REC)
1524 printk(KERN_INFO "%s: Ring recovery ongoing\n",dev->name);
1525 if (lan_status_diff & LSC_FDX_MODE)
1526 printk(KERN_INFO "%s: Operating in FDX mode\n",dev->name);
1527 }
1528
1529 if (lan_status_diff & LSC_CO) {
1530
1531 if (olympic_priv->olympic_message_level)
1532 printk(KERN_INFO "%s: Counter Overflow \n", dev->name);
1533
1534 /* Issue READ.LOG command */
1535
1536 writeb(SRB_READ_LOG, srb);
1537 writeb(0,srb+1);
1538 writeb(OLYMPIC_CLEAR_RET_CODE,srb+2);
1539 writeb(0,srb+3);
1540 writeb(0,srb+4);
1541 writeb(0,srb+5);
1542
1543 olympic_priv->srb_queued=2; /* Can't sleep, use srb_bh */
1544
1545 writel(LISR_SRB_CMD,olympic_mmio+LISR_SUM);
1546
1547 }
1548
1549 if (lan_status_diff & LSC_SR_CO) {
1550
1551 if (olympic_priv->olympic_message_level)
1552 printk(KERN_INFO "%s: Source routing counters overflow\n", dev->name);
1553
1554 /* Issue a READ.SR.COUNTERS */
1555
1556 writeb(SRB_READ_SR_COUNTERS,srb);
1557 writeb(0,srb+1);
1558 writeb(OLYMPIC_CLEAR_RET_CODE,srb+2);
1559 writeb(0,srb+3);
1560
1561 olympic_priv->srb_queued=2; /* Can't sleep, use srb_bh */
1562
1563 writel(LISR_SRB_CMD,olympic_mmio+LISR_SUM);
1564
1565 }
1566
1567 olympic_priv->olympic_lan_status = lan_status ;
1568
1569 } /* Lan.change.status */
1570 else
1571 printk(KERN_WARNING "%s: Unknown arb command \n", dev->name);
1572}
1573
1574static void olympic_asb_bh(struct net_device *dev)
1575{
1576 struct olympic_private *olympic_priv = (struct olympic_private *) dev->priv ;
1577 u8 __iomem *arb_block, *asb_block ;
1578
1579 arb_block = (olympic_priv->olympic_lap + olympic_priv->arb) ;
1580 asb_block = (olympic_priv->olympic_lap + olympic_priv->asb) ;
1581
1582 if (olympic_priv->asb_queued == 1) { /* Dropped through the first time */
1583
1584 writeb(ASB_RECEIVE_DATA,asb_block); /* Receive data */
1585 writeb(OLYMPIC_CLEAR_RET_CODE,asb_block+2); /* Necessary ?? */
1586 writeb(readb(arb_block+6),asb_block+6); /* Must send the address back to the adapter */
1587 writeb(readb(arb_block+7),asb_block+7); /* To let it know we have dealt with the data */
1588
1589 writel(LISR_ASB_REPLY | LISR_ASB_FREE_REQ,olympic_priv->olympic_mmio+LISR_SUM);
1590 olympic_priv->asb_queued = 2 ;
1591
1592 return ;
1593 }
1594
1595 if (olympic_priv->asb_queued == 2) {
1596 switch (readb(asb_block+2)) {
1597 case 0x01:
1598 printk(KERN_WARNING "%s: Unrecognized command code \n", dev->name);
1599 break ;
1600 case 0x26:
1601 printk(KERN_WARNING "%s: Unrecognized buffer address \n", dev->name);
1602 break ;
1603 case 0xFF:
1604 /* Valid response, everything should be ok again */
1605 break ;
1606 default:
1607 printk(KERN_WARNING "%s: Invalid return code in asb\n",dev->name);
1608 break ;
1609 }
1610 }
1611 olympic_priv->asb_queued = 0 ;
1612}
1613
1614static int olympic_change_mtu(struct net_device *dev, int mtu)
1615{
1616 struct olympic_private *olympic_priv = (struct olympic_private *) dev->priv;
1617 u16 max_mtu ;
1618
1619 if (olympic_priv->olympic_ring_speed == 4)
1620 max_mtu = 4500 ;
1621 else
1622 max_mtu = 18000 ;
1623
1624 if (mtu > max_mtu)
1625 return -EINVAL ;
1626 if (mtu < 100)
1627 return -EINVAL ;
1628
1629 dev->mtu = mtu ;
1630 olympic_priv->pkt_buf_sz = mtu + TR_HLEN ;
1631
1632 return 0 ;
1633}
1634
1635static int olympic_proc_info(char *buffer, char **start, off_t offset, int length, int *eof, void *data)
1636{
1637 struct net_device *dev = (struct net_device *)data ;
1638 struct olympic_private *olympic_priv=(struct olympic_private *)dev->priv;
1639 u8 __iomem *oat = (olympic_priv->olympic_lap + olympic_priv->olympic_addr_table_addr) ;
1640 u8 __iomem *opt = (olympic_priv->olympic_lap + olympic_priv->olympic_parms_addr) ;
1641 int size = 0 ;
1642 int len=0;
1643 off_t begin=0;
1644 off_t pos=0;
1645
1646 size = sprintf(buffer,
1647 "IBM Pit/Pit-Phy/Olympic Chipset Token Ring Adapter %s\n",dev->name);
1648 size += sprintf(buffer+size, "\n%6s: Adapter Address : Node Address : Functional Addr\n",
1649 dev->name);
1650
1651 size += sprintf(buffer+size, "%6s: %02x:%02x:%02x:%02x:%02x:%02x : %02x:%02x:%02x:%02x:%02x:%02x : %02x:%02x:%02x:%02x\n",
1652 dev->name,
1653 dev->dev_addr[0],
1654 dev->dev_addr[1],
1655 dev->dev_addr[2],
1656 dev->dev_addr[3],
1657 dev->dev_addr[4],
1658 dev->dev_addr[5],
1659 readb(oat+offsetof(struct olympic_adapter_addr_table,node_addr)),
1660 readb(oat+offsetof(struct olympic_adapter_addr_table,node_addr)+1),
1661 readb(oat+offsetof(struct olympic_adapter_addr_table,node_addr)+2),
1662 readb(oat+offsetof(struct olympic_adapter_addr_table,node_addr)+3),
1663 readb(oat+offsetof(struct olympic_adapter_addr_table,node_addr)+4),
1664 readb(oat+offsetof(struct olympic_adapter_addr_table,node_addr)+5),
1665 readb(oat+offsetof(struct olympic_adapter_addr_table,func_addr)),
1666 readb(oat+offsetof(struct olympic_adapter_addr_table,func_addr)+1),
1667 readb(oat+offsetof(struct olympic_adapter_addr_table,func_addr)+2),
1668 readb(oat+offsetof(struct olympic_adapter_addr_table,func_addr)+3));
1669
1670 size += sprintf(buffer+size, "\n%6s: Token Ring Parameters Table:\n", dev->name);
1671
1672 size += sprintf(buffer+size, "%6s: Physical Addr : Up Node Address : Poll Address : AccPri : Auth Src : Att Code :\n",
1673 dev->name) ;
1674
1675 size += sprintf(buffer+size, "%6s: %02x:%02x:%02x:%02x : %02x:%02x:%02x:%02x:%02x:%02x : %02x:%02x:%02x:%02x:%02x:%02x : %04x : %04x : %04x :\n",
1676 dev->name,
1677 readb(opt+offsetof(struct olympic_parameters_table, phys_addr)),
1678 readb(opt+offsetof(struct olympic_parameters_table, phys_addr)+1),
1679 readb(opt+offsetof(struct olympic_parameters_table, phys_addr)+2),
1680 readb(opt+offsetof(struct olympic_parameters_table, phys_addr)+3),
1681 readb(opt+offsetof(struct olympic_parameters_table, up_node_addr)),
1682 readb(opt+offsetof(struct olympic_parameters_table, up_node_addr)+1),
1683 readb(opt+offsetof(struct olympic_parameters_table, up_node_addr)+2),
1684 readb(opt+offsetof(struct olympic_parameters_table, up_node_addr)+3),
1685 readb(opt+offsetof(struct olympic_parameters_table, up_node_addr)+4),
1686 readb(opt+offsetof(struct olympic_parameters_table, up_node_addr)+5),
1687 readb(opt+offsetof(struct olympic_parameters_table, poll_addr)),
1688 readb(opt+offsetof(struct olympic_parameters_table, poll_addr)+1),
1689 readb(opt+offsetof(struct olympic_parameters_table, poll_addr)+2),
1690 readb(opt+offsetof(struct olympic_parameters_table, poll_addr)+3),
1691 readb(opt+offsetof(struct olympic_parameters_table, poll_addr)+4),
1692 readb(opt+offsetof(struct olympic_parameters_table, poll_addr)+5),
1693 swab16(readw(opt+offsetof(struct olympic_parameters_table, acc_priority))),
1694 swab16(readw(opt+offsetof(struct olympic_parameters_table, auth_source_class))),
1695 swab16(readw(opt+offsetof(struct olympic_parameters_table, att_code))));
1696
1697 size += sprintf(buffer+size, "%6s: Source Address : Bcn T : Maj. V : Lan St : Lcl Rg : Mon Err : Frame Correl : \n",
1698 dev->name) ;
1699
1700 size += sprintf(buffer+size, "%6s: %02x:%02x:%02x:%02x:%02x:%02x : %04x : %04x : %04x : %04x : %04x : %04x : \n",
1701 dev->name,
1702 readb(opt+offsetof(struct olympic_parameters_table, source_addr)),
1703 readb(opt+offsetof(struct olympic_parameters_table, source_addr)+1),
1704 readb(opt+offsetof(struct olympic_parameters_table, source_addr)+2),
1705 readb(opt+offsetof(struct olympic_parameters_table, source_addr)+3),
1706 readb(opt+offsetof(struct olympic_parameters_table, source_addr)+4),
1707 readb(opt+offsetof(struct olympic_parameters_table, source_addr)+5),
1708 swab16(readw(opt+offsetof(struct olympic_parameters_table, beacon_type))),
1709 swab16(readw(opt+offsetof(struct olympic_parameters_table, major_vector))),
1710 swab16(readw(opt+offsetof(struct olympic_parameters_table, lan_status))),
1711 swab16(readw(opt+offsetof(struct olympic_parameters_table, local_ring))),
1712 swab16(readw(opt+offsetof(struct olympic_parameters_table, mon_error))),
1713 swab16(readw(opt+offsetof(struct olympic_parameters_table, frame_correl))));
1714
1715 size += sprintf(buffer+size, "%6s: Beacon Details : Tx : Rx : NAUN Node Address : NAUN Node Phys : \n",
1716 dev->name) ;
1717
1718 size += sprintf(buffer+size, "%6s: : %02x : %02x : %02x:%02x:%02x:%02x:%02x:%02x : %02x:%02x:%02x:%02x : \n",
1719 dev->name,
1720 swab16(readw(opt+offsetof(struct olympic_parameters_table, beacon_transmit))),
1721 swab16(readw(opt+offsetof(struct olympic_parameters_table, beacon_receive))),
1722 readb(opt+offsetof(struct olympic_parameters_table, beacon_naun)),
1723 readb(opt+offsetof(struct olympic_parameters_table, beacon_naun)+1),
1724 readb(opt+offsetof(struct olympic_parameters_table, beacon_naun)+2),
1725 readb(opt+offsetof(struct olympic_parameters_table, beacon_naun)+3),
1726 readb(opt+offsetof(struct olympic_parameters_table, beacon_naun)+4),
1727 readb(opt+offsetof(struct olympic_parameters_table, beacon_naun)+5),
1728 readb(opt+offsetof(struct olympic_parameters_table, beacon_phys)),
1729 readb(opt+offsetof(struct olympic_parameters_table, beacon_phys)+1),
1730 readb(opt+offsetof(struct olympic_parameters_table, beacon_phys)+2),
1731 readb(opt+offsetof(struct olympic_parameters_table, beacon_phys)+3));
1732
1733 len=size;
1734 pos=begin+size;
1735 if (pos<offset) {
1736 len=0;
1737 begin=pos;
1738 }
1739 *start=buffer+(offset-begin); /* Start of wanted data */
1740 len-=(offset-begin); /* Start slop */
1741 if(len>length)
1742 len=length; /* Ending slop */
1743 return len;
1744}
1745
1746static void __devexit olympic_remove_one(struct pci_dev *pdev)
1747{
1748 struct net_device *dev = pci_get_drvdata(pdev) ;
1749 struct olympic_private *olympic_priv=(struct olympic_private *)dev->priv;
1750
1751 if (olympic_priv->olympic_network_monitor) {
1752 char proc_name[20] ;
1753 strcpy(proc_name,"net/olympic_") ;
1754 strcat(proc_name,dev->name) ;
1755 remove_proc_entry(proc_name,NULL);
1756 }
1757 unregister_netdev(dev) ;
1758 iounmap(olympic_priv->olympic_mmio) ;
1759 iounmap(olympic_priv->olympic_lap) ;
1760 pci_release_regions(pdev) ;
1761 pci_set_drvdata(pdev,NULL) ;
1762 free_netdev(dev) ;
1763}
1764
1765static struct pci_driver olympic_driver = {
1766 .name = "olympic",
1767 .id_table = olympic_pci_tbl,
1768 .probe = olympic_probe,
1769 .remove = __devexit_p(olympic_remove_one),
1770};
1771
1772static int __init olympic_pci_init(void)
1773{
1774 return pci_module_init (&olympic_driver) ;
1775}
1776
1777static void __exit olympic_pci_cleanup(void)
1778{
1779 pci_unregister_driver(&olympic_driver) ;
1780}
1781
1782
1783module_init(olympic_pci_init) ;
1784module_exit(olympic_pci_cleanup) ;
1785
1786MODULE_LICENSE("GPL");
diff --git a/drivers/net/tokenring/olympic.h b/drivers/net/tokenring/olympic.h
new file mode 100644
index 000000000000..2fc59c997468
--- /dev/null
+++ b/drivers/net/tokenring/olympic.h
@@ -0,0 +1,322 @@
1/*
2 * olympic.h (c) 1999 Peter De Schrijver All Rights Reserved
3 * 1999,2000 Mike Phillips (mikep@linuxtr.net)
4 *
5 * Linux driver for IBM PCI tokenring cards based on the olympic and the PIT/PHY chipset.
6 *
7 * Base Driver Skeleton:
8 * Written 1993-94 by Donald Becker.
9 *
10 * Copyright 1993 United States Government as represented by the
11 * Director, National Security Agency.
12 *
13 * This software may be used and distributed according to the terms
14 * of the GNU General Public License, incorporated herein by reference.
15 */
16
17#define CID 0x4e
18
19#define BCTL 0x70
20#define BCTL_SOFTRESET (1<<15)
21#define BCTL_MIMREB (1<<6)
22#define BCTL_MODE_INDICATOR (1<<5)
23
24#define GPR 0x4a
25#define GPR_OPTI_BF (1<<6)
26#define GPR_NEPTUNE_BF (1<<4)
27#define GPR_AUTOSENSE (1<<2)
28#define GPR_16MBPS (1<<3)
29
30#define PAG 0x85
31#define LBC 0x8e
32
33#define LISR 0x10
34#define LISR_SUM 0x14
35#define LISR_RWM 0x18
36
37#define LISR_LIE (1<<15)
38#define LISR_SLIM (1<<13)
39#define LISR_SLI (1<<12)
40#define LISR_PCMSRMASK (1<<11)
41#define LISR_PCMSRINT (1<<10)
42#define LISR_WOLMASK (1<<9)
43#define LISR_WOL (1<<8)
44#define LISR_SRB_CMD (1<<5)
45#define LISR_ASB_REPLY (1<<4)
46#define LISR_ASB_FREE_REQ (1<<2)
47#define LISR_ARB_FREE (1<<1)
48#define LISR_TRB_FRAME (1<<0)
49
50#define SISR 0x20
51#define SISR_SUM 0x24
52#define SISR_RWM 0x28
53#define SISR_RR 0x2C
54#define SISR_RESMASK 0x30
55#define SISR_MASK 0x54
56#define SISR_MASK_SUM 0x58
57#define SISR_MASK_RWM 0x5C
58
59#define SISR_TX2_IDLE (1<<31)
60#define SISR_TX2_HALT (1<<29)
61#define SISR_TX2_EOF (1<<28)
62#define SISR_TX1_IDLE (1<<27)
63#define SISR_TX1_HALT (1<<25)
64#define SISR_TX1_EOF (1<<24)
65#define SISR_TIMEOUT (1<<23)
66#define SISR_RX_NOBUF (1<<22)
67#define SISR_RX_STATUS (1<<21)
68#define SISR_RX_HALT (1<<18)
69#define SISR_RX_EOF_EARLY (1<<16)
70#define SISR_MI (1<<15)
71#define SISR_PI (1<<13)
72#define SISR_ERR (1<<9)
73#define SISR_ADAPTER_CHECK (1<<6)
74#define SISR_SRB_REPLY (1<<5)
75#define SISR_ASB_FREE (1<<4)
76#define SISR_ARB_CMD (1<<3)
77#define SISR_TRB_REPLY (1<<2)
78
79#define EISR 0x34
80#define EISR_RWM 0x38
81#define EISR_MASK 0x3c
82#define EISR_MASK_OPTIONS 0x001FFF7F
83
84#define LAPA 0x60
85#define LAPWWO 0x64
86#define LAPWWC 0x68
87#define LAPCTL 0x6C
88#define LAIPD 0x78
89#define LAIPDDINC 0x7C
90
91#define TIMER 0x50
92
93#define CLKCTL 0x74
94#define CLKCTL_PAUSE (1<<15)
95
96#define PM_CON 0x4
97
98#define BMCTL_SUM 0x40
99#define BMCTL_RWM 0x44
100#define BMCTL_TX2_DIS (1<<30)
101#define BMCTL_TX1_DIS (1<<26)
102#define BMCTL_RX_DIS (1<<22)
103
104#define BMASR 0xcc
105
106#define RXDESCQ 0x90
107#define RXDESCQCNT 0x94
108#define RXCDA 0x98
109#define RXENQ 0x9C
110#define RXSTATQ 0xA0
111#define RXSTATQCNT 0xA4
112#define RXCSA 0xA8
113#define RXCLEN 0xAC
114#define RXHLEN 0xAE
115
116#define TXDESCQ_1 0xb0
117#define TXDESCQ_2 0xd0
118#define TXDESCQCNT_1 0xb4
119#define TXDESCQCNT_2 0xd4
120#define TXCDA_1 0xb8
121#define TXCDA_2 0xd8
122#define TXENQ_1 0xbc
123#define TXENQ_2 0xdc
124#define TXSTATQ_1 0xc0
125#define TXSTATQ_2 0xe0
126#define TXSTATQCNT_1 0xc4
127#define TXSTATQCNT_2 0xe4
128#define TXCSA_1 0xc8
129#define TXCSA_2 0xe8
130/* Cardbus */
131#define FERMASK 0xf4
132#define FERMASK_INT_BIT (1<<15)
133
134#define OLYMPIC_IO_SPACE 256
135
136#define SRB_COMMAND_SIZE 50
137
138#define OLYMPIC_MAX_ADAPTERS 8 /* 0x08 __MODULE_STRING can't hand 0xnn */
139
140/* Defines for LAN STATUS CHANGE reports */
141#define LSC_SIG_LOSS 0x8000
142#define LSC_HARD_ERR 0x4000
143#define LSC_SOFT_ERR 0x2000
144#define LSC_TRAN_BCN 0x1000
145#define LSC_LWF 0x0800
146#define LSC_ARW 0x0400
147#define LSC_FPE 0x0200
148#define LSC_RR 0x0100
149#define LSC_CO 0x0080
150#define LSC_SS 0x0040
151#define LSC_RING_REC 0x0020
152#define LSC_SR_CO 0x0010
153#define LSC_FDX_MODE 0x0004
154
155/* Defines for OPEN ADAPTER command */
156
157#define OPEN_ADAPTER_EXT_WRAP (1<<15)
158#define OPEN_ADAPTER_DIS_HARDEE (1<<14)
159#define OPEN_ADAPTER_DIS_SOFTERR (1<<13)
160#define OPEN_ADAPTER_PASS_ADC_MAC (1<<12)
161#define OPEN_ADAPTER_PASS_ATT_MAC (1<<11)
162#define OPEN_ADAPTER_ENABLE_EC (1<<10)
163#define OPEN_ADAPTER_CONTENDER (1<<8)
164#define OPEN_ADAPTER_PASS_BEACON (1<<7)
165#define OPEN_ADAPTER_ENABLE_FDX (1<<6)
166#define OPEN_ADAPTER_ENABLE_RPL (1<<5)
167#define OPEN_ADAPTER_INHIBIT_ETR (1<<4)
168#define OPEN_ADAPTER_INTERNAL_WRAP (1<<3)
169#define OPEN_ADAPTER_USE_OPTS2 (1<<0)
170
171#define OPEN_ADAPTER_2_ENABLE_ONNOW (1<<15)
172
173/* Defines for SRB Commands */
174
175#define SRB_ACCESS_REGISTER 0x1f
176#define SRB_CLOSE_ADAPTER 0x04
177#define SRB_CONFIGURE_BRIDGE 0x0c
178#define SRB_CONFIGURE_WAKEUP_EVENT 0x1a
179#define SRB_MODIFY_BRIDGE_PARMS 0x15
180#define SRB_MODIFY_OPEN_OPTIONS 0x01
181#define SRB_MODIFY_RECEIVE_OPTIONS 0x17
182#define SRB_NO_OPERATION 0x00
183#define SRB_OPEN_ADAPTER 0x03
184#define SRB_READ_LOG 0x08
185#define SRB_READ_SR_COUNTERS 0x16
186#define SRB_RESET_GROUP_ADDRESS 0x02
187#define SRB_SAVE_CONFIGURATION 0x1b
188#define SRB_SET_BRIDGE_PARMS 0x09
189#define SRB_SET_BRIDGE_TARGETS 0x10
190#define SRB_SET_FUNC_ADDRESS 0x07
191#define SRB_SET_GROUP_ADDRESS 0x06
192#define SRB_SET_GROUP_ADDR_OPTIONS 0x11
193#define SRB_UPDATE_WAKEUP_PATTERN 0x19
194
195/* Clear return code */
196
197#define OLYMPIC_CLEAR_RET_CODE 0xfe
198
199/* ARB Commands */
200#define ARB_RECEIVE_DATA 0x81
201#define ARB_LAN_CHANGE_STATUS 0x84
202/* ASB Response commands */
203
204#define ASB_RECEIVE_DATA 0x81
205
206
207/* Olympic defaults for buffers */
208
209#define OLYMPIC_RX_RING_SIZE 16 /* should be a power of 2 */
210#define OLYMPIC_TX_RING_SIZE 8 /* should be a power of 2 */
211
212#define PKT_BUF_SZ 4096 /* Default packet size */
213
214/* Olympic data structures */
215
216/* xxxx These structures are all little endian in hardware. */
217
218struct olympic_tx_desc {
219 u32 buffer;
220 u32 status_length;
221};
222
223struct olympic_tx_status {
224 u32 status;
225};
226
227struct olympic_rx_desc {
228 u32 buffer;
229 u32 res_length;
230};
231
232struct olympic_rx_status {
233 u32 fragmentcnt_framelen;
234 u32 status_buffercnt;
235};
236/* xxxx END These structures are all little endian in hardware. */
237/* xxxx There may be more, but I'm pretty sure about these */
238
239struct mac_receive_buffer {
240 u16 next ;
241 u8 padding ;
242 u8 frame_status ;
243 u16 buffer_length ;
244 u8 frame_data ;
245};
246
247struct olympic_private {
248
249 u16 srb; /* be16 */
250 u16 trb; /* be16 */
251 u16 arb; /* be16 */
252 u16 asb; /* be16 */
253
254 u8 __iomem *olympic_mmio;
255 u8 __iomem *olympic_lap;
256 struct pci_dev *pdev ;
257 char *olympic_card_name ;
258
259 spinlock_t olympic_lock ;
260
261 volatile int srb_queued; /* True if an SRB is still posted */
262 wait_queue_head_t srb_wait;
263
264 volatile int asb_queued; /* True if an ASB is posted */
265
266 volatile int trb_queued; /* True if a TRB is posted */
267 wait_queue_head_t trb_wait ;
268
269 /* These must be on a 4 byte boundary. */
270 struct olympic_rx_desc olympic_rx_ring[OLYMPIC_RX_RING_SIZE];
271 struct olympic_tx_desc olympic_tx_ring[OLYMPIC_TX_RING_SIZE];
272 struct olympic_rx_status olympic_rx_status_ring[OLYMPIC_RX_RING_SIZE];
273 struct olympic_tx_status olympic_tx_status_ring[OLYMPIC_TX_RING_SIZE];
274
275 struct sk_buff *tx_ring_skb[OLYMPIC_TX_RING_SIZE], *rx_ring_skb[OLYMPIC_RX_RING_SIZE];
276 int tx_ring_free, tx_ring_last_status, rx_ring_last_received,rx_status_last_received, free_tx_ring_entries;
277
278 struct net_device_stats olympic_stats ;
279 u16 olympic_lan_status ;
280 u8 olympic_ring_speed ;
281 u16 pkt_buf_sz ;
282 u8 olympic_receive_options, olympic_copy_all_options,olympic_message_level, olympic_network_monitor;
283 u16 olympic_addr_table_addr, olympic_parms_addr ;
284 u8 olympic_laa[6] ;
285 u32 rx_ring_dma_addr;
286 u32 rx_status_ring_dma_addr;
287 u32 tx_ring_dma_addr;
288 u32 tx_status_ring_dma_addr;
289};
290
291struct olympic_adapter_addr_table {
292
293 u8 node_addr[6] ;
294 u8 reserved[4] ;
295 u8 func_addr[4] ;
296} ;
297
298struct olympic_parameters_table {
299
300 u8 phys_addr[4] ;
301 u8 up_node_addr[6] ;
302 u8 up_phys_addr[4] ;
303 u8 poll_addr[6] ;
304 u16 reserved ;
305 u16 acc_priority ;
306 u16 auth_source_class ;
307 u16 att_code ;
308 u8 source_addr[6] ;
309 u16 beacon_type ;
310 u16 major_vector ;
311 u16 lan_status ;
312 u16 soft_error_time ;
313 u16 reserved1 ;
314 u16 local_ring ;
315 u16 mon_error ;
316 u16 beacon_transmit ;
317 u16 beacon_receive ;
318 u16 frame_correl ;
319 u8 beacon_naun[6] ;
320 u32 reserved2 ;
321 u8 beacon_phys[4] ;
322};
diff --git a/drivers/net/tokenring/proteon.c b/drivers/net/tokenring/proteon.c
new file mode 100644
index 000000000000..675b063508e3
--- /dev/null
+++ b/drivers/net/tokenring/proteon.c
@@ -0,0 +1,432 @@
1/*
2 * proteon.c: A network driver for Proteon ISA token ring cards.
3 *
4 * Based on tmspci written 1999 by Adam Fritzler
5 *
6 * Written 2003 by Jochen Friedrich
7 *
8 * This software may be used and distributed according to the terms
9 * of the GNU General Public License, incorporated herein by reference.
10 *
11 * This driver module supports the following cards:
12 * - Proteon 1392, 1392+
13 *
14 * Maintainer(s):
15 * AF Adam Fritzler mid@auk.cx
16 * JF Jochen Friedrich jochen@scram.de
17 *
18 * Modification History:
19 * 02-Jan-03 JF Created
20 *
21 */
22static const char version[] = "proteon.c: v1.00 02/01/2003 by Jochen Friedrich\n";
23
24#include <linux/module.h>
25#include <linux/kernel.h>
26#include <linux/delay.h>
27#include <linux/errno.h>
28#include <linux/pci.h>
29#include <linux/init.h>
30#include <linux/netdevice.h>
31#include <linux/trdevice.h>
32
33#include <asm/system.h>
34#include <asm/io.h>
35#include <asm/irq.h>
36#include <asm/pci.h>
37#include <asm/dma.h>
38
39#include "tms380tr.h"
40
41#define PROTEON_IO_EXTENT 32
42
43/* A zero-terminated list of I/O addresses to be probed. */
44static unsigned int portlist[] __initdata = {
45 0x0A20, 0x0E20, 0x1A20, 0x1E20, 0x2A20, 0x2E20, 0x3A20, 0x3E20,// Prot.
46 0x4A20, 0x4E20, 0x5A20, 0x5E20, 0x6A20, 0x6E20, 0x7A20, 0x7E20,// Prot.
47 0x8A20, 0x8E20, 0x9A20, 0x9E20, 0xAA20, 0xAE20, 0xBA20, 0xBE20,// Prot.
48 0xCA20, 0xCE20, 0xDA20, 0xDE20, 0xEA20, 0xEE20, 0xFA20, 0xFE20,// Prot.
49 0
50};
51
52/* A zero-terminated list of IRQs to be probed. */
53static unsigned short irqlist[] = {
54 7, 6, 5, 4, 3, 12, 11, 10, 9,
55 0
56};
57
58/* A zero-terminated list of DMAs to be probed. */
59static int dmalist[] __initdata = {
60 5, 6, 7,
61 0
62};
63
64static char cardname[] = "Proteon 1392\0";
65
66struct net_device *proteon_probe(int unit);
67static int proteon_open(struct net_device *dev);
68static void proteon_read_eeprom(struct net_device *dev);
69static unsigned short proteon_setnselout_pins(struct net_device *dev);
70
71static unsigned short proteon_sifreadb(struct net_device *dev, unsigned short reg)
72{
73 return inb(dev->base_addr + reg);
74}
75
76static unsigned short proteon_sifreadw(struct net_device *dev, unsigned short reg)
77{
78 return inw(dev->base_addr + reg);
79}
80
81static void proteon_sifwriteb(struct net_device *dev, unsigned short val, unsigned short reg)
82{
83 outb(val, dev->base_addr + reg);
84}
85
86static void proteon_sifwritew(struct net_device *dev, unsigned short val, unsigned short reg)
87{
88 outw(val, dev->base_addr + reg);
89}
90
91static int __init proteon_probe1(struct net_device *dev, int ioaddr)
92{
93 unsigned char chk1, chk2;
94 int i;
95
96 if (!request_region(ioaddr, PROTEON_IO_EXTENT, cardname))
97 return -ENODEV;
98
99
100 chk1 = inb(ioaddr + 0x1f); /* Get Proteon ID reg 1 */
101 if (chk1 != 0x1f)
102 goto nodev;
103
104 chk1 = inb(ioaddr + 0x1e) & 0x07; /* Get Proteon ID reg 0 */
105 for (i=0; i<16; i++) {
106 chk2 = inb(ioaddr + 0x1e) & 0x07;
107 if (((chk1 + 1) & 0x07) != chk2)
108 goto nodev;
109 chk1 = chk2;
110 }
111
112 dev->base_addr = ioaddr;
113 return (0);
114nodev:
115 release_region(ioaddr, PROTEON_IO_EXTENT);
116 return -ENODEV;
117}
118
119static int __init setup_card(struct net_device *dev)
120{
121 struct net_local *tp;
122 static int versionprinted;
123 const unsigned *port;
124 int j,err = 0;
125
126 if (!dev)
127 return -ENOMEM;
128
129 SET_MODULE_OWNER(dev);
130 if (dev->base_addr) /* probe specific location */
131 err = proteon_probe1(dev, dev->base_addr);
132 else {
133 for (port = portlist; *port; port++) {
134 err = proteon_probe1(dev, *port);
135 if (!err)
136 break;
137 }
138 }
139 if (err)
140 goto out4;
141
142 /* At this point we have found a valid card. */
143
144 if (versionprinted++ == 0)
145 printk(KERN_DEBUG "%s", version);
146
147 err = -EIO;
148 if (tmsdev_init(dev, ISA_MAX_ADDRESS, NULL))
149 goto out4;
150
151 dev->base_addr &= ~3;
152
153 proteon_read_eeprom(dev);
154
155 printk(KERN_DEBUG "%s: Ring Station Address: ", dev->name);
156 printk("%2.2x", dev->dev_addr[0]);
157 for (j = 1; j < 6; j++)
158 printk(":%2.2x", dev->dev_addr[j]);
159 printk("\n");
160
161 tp = netdev_priv(dev);
162 tp->setnselout = proteon_setnselout_pins;
163
164 tp->sifreadb = proteon_sifreadb;
165 tp->sifreadw = proteon_sifreadw;
166 tp->sifwriteb = proteon_sifwriteb;
167 tp->sifwritew = proteon_sifwritew;
168
169 memcpy(tp->ProductID, cardname, PROD_ID_SIZE + 1);
170
171 tp->tmspriv = NULL;
172
173 dev->open = proteon_open;
174 dev->stop = tms380tr_close;
175
176 if (dev->irq == 0)
177 {
178 for(j = 0; irqlist[j] != 0; j++)
179 {
180 dev->irq = irqlist[j];
181 if (!request_irq(dev->irq, tms380tr_interrupt, 0,
182 cardname, dev))
183 break;
184 }
185
186 if(irqlist[j] == 0)
187 {
188 printk(KERN_INFO "%s: AutoSelect no IRQ available\n", dev->name);
189 goto out3;
190 }
191 }
192 else
193 {
194 for(j = 0; irqlist[j] != 0; j++)
195 if (irqlist[j] == dev->irq)
196 break;
197 if (irqlist[j] == 0)
198 {
199 printk(KERN_INFO "%s: Illegal IRQ %d specified\n",
200 dev->name, dev->irq);
201 goto out3;
202 }
203 if (request_irq(dev->irq, tms380tr_interrupt, 0,
204 cardname, dev))
205 {
206 printk(KERN_INFO "%s: Selected IRQ %d not available\n",
207 dev->name, dev->irq);
208 goto out3;
209 }
210 }
211
212 if (dev->dma == 0)
213 {
214 for(j = 0; dmalist[j] != 0; j++)
215 {
216 dev->dma = dmalist[j];
217 if (!request_dma(dev->dma, cardname))
218 break;
219 }
220
221 if(dmalist[j] == 0)
222 {
223 printk(KERN_INFO "%s: AutoSelect no DMA available\n", dev->name);
224 goto out2;
225 }
226 }
227 else
228 {
229 for(j = 0; dmalist[j] != 0; j++)
230 if (dmalist[j] == dev->dma)
231 break;
232 if (dmalist[j] == 0)
233 {
234 printk(KERN_INFO "%s: Illegal DMA %d specified\n",
235 dev->name, dev->dma);
236 goto out2;
237 }
238 if (request_dma(dev->dma, cardname))
239 {
240 printk(KERN_INFO "%s: Selected DMA %d not available\n",
241 dev->name, dev->dma);
242 goto out2;
243 }
244 }
245
246 printk(KERN_DEBUG "%s: IO: %#4lx IRQ: %d DMA: %d\n",
247 dev->name, dev->base_addr, dev->irq, dev->dma);
248
249 err = register_netdev(dev);
250 if (err)
251 goto out;
252
253 return 0;
254out:
255 free_dma(dev->dma);
256out2:
257 free_irq(dev->irq, dev);
258out3:
259 tmsdev_term(dev);
260out4:
261 release_region(dev->base_addr, PROTEON_IO_EXTENT);
262 return err;
263}
264
265struct net_device * __init proteon_probe(int unit)
266{
267 struct net_device *dev = alloc_trdev(sizeof(struct net_local));
268 int err = 0;
269
270 if (!dev)
271 return ERR_PTR(-ENOMEM);
272
273 if (unit >= 0) {
274 sprintf(dev->name, "tr%d", unit);
275 netdev_boot_setup_check(dev);
276 }
277
278 err = setup_card(dev);
279 if (err)
280 goto out;
281
282 return dev;
283
284out:
285 free_netdev(dev);
286 return ERR_PTR(err);
287}
288
289/*
290 * Reads MAC address from adapter RAM, which should've read it from
291 * the onboard ROM.
292 *
293 * Calling this on a board that does not support it can be a very
294 * dangerous thing. The Madge board, for instance, will lock your
295 * machine hard when this is called. Luckily, its supported in a
296 * separate driver. --ASF
297 */
298static void proteon_read_eeprom(struct net_device *dev)
299{
300 int i;
301
302 /* Address: 0000:0000 */
303 proteon_sifwritew(dev, 0, SIFADX);
304 proteon_sifwritew(dev, 0, SIFADR);
305
306 /* Read six byte MAC address data */
307 dev->addr_len = 6;
308 for(i = 0; i < 6; i++)
309 dev->dev_addr[i] = proteon_sifreadw(dev, SIFINC) >> 8;
310}
311
312unsigned short proteon_setnselout_pins(struct net_device *dev)
313{
314 return 0;
315}
316
317static int proteon_open(struct net_device *dev)
318{
319 struct net_local *tp = netdev_priv(dev);
320 unsigned short val = 0;
321 int i;
322
323 /* Proteon reset sequence */
324 outb(0, dev->base_addr + 0x11);
325 mdelay(20);
326 outb(0x04, dev->base_addr + 0x11);
327 mdelay(20);
328 outb(0, dev->base_addr + 0x11);
329 mdelay(100);
330
331 /* set control/status reg */
332 val = inb(dev->base_addr + 0x11);
333 val |= 0x78;
334 val &= 0xf9;
335 if(tp->DataRate == SPEED_4)
336 val |= 0x20;
337 else
338 val &= ~0x20;
339
340 outb(val, dev->base_addr + 0x11);
341 outb(0xff, dev->base_addr + 0x12);
342 for(i = 0; irqlist[i] != 0; i++)
343 {
344 if(irqlist[i] == dev->irq)
345 break;
346 }
347 val = i;
348 i = (7 - dev->dma) << 4;
349 val |= i;
350 outb(val, dev->base_addr + 0x13);
351
352 return tms380tr_open(dev);
353}
354
355#ifdef MODULE
356
357#define ISATR_MAX_ADAPTERS 3
358
359static int io[ISATR_MAX_ADAPTERS];
360static int irq[ISATR_MAX_ADAPTERS];
361static int dma[ISATR_MAX_ADAPTERS];
362
363MODULE_LICENSE("GPL");
364
365module_param_array(io, int, NULL, 0);
366module_param_array(irq, int, NULL, 0);
367module_param_array(dma, int, NULL, 0);
368
369static struct net_device *proteon_dev[ISATR_MAX_ADAPTERS];
370
371int init_module(void)
372{
373 struct net_device *dev;
374 int i, num = 0, err = 0;
375
376 for (i = 0; i < ISATR_MAX_ADAPTERS ; i++) {
377 dev = alloc_trdev(sizeof(struct net_local));
378 if (!dev)
379 continue;
380
381 dev->base_addr = io[i];
382 dev->irq = irq[i];
383 dev->dma = dma[i];
384 err = setup_card(dev);
385 if (!err) {
386 proteon_dev[i] = dev;
387 ++num;
388 } else {
389 free_netdev(dev);
390 }
391 }
392
393 printk(KERN_NOTICE "proteon.c: %d cards found.\n", num);
394 /* Probe for cards. */
395 if (num == 0) {
396 printk(KERN_NOTICE "proteon.c: No cards found.\n");
397 return (-ENODEV);
398 }
399 return (0);
400}
401
402void cleanup_module(void)
403{
404 int i;
405
406 for (i = 0; i < ISATR_MAX_ADAPTERS ; i++) {
407 struct net_device *dev = proteon_dev[i];
408
409 if (!dev)
410 continue;
411
412 unregister_netdev(dev);
413 release_region(dev->base_addr, PROTEON_IO_EXTENT);
414 free_irq(dev->irq, dev);
415 free_dma(dev->dma);
416 tmsdev_term(dev);
417 free_netdev(dev);
418 }
419}
420#endif /* MODULE */
421
422
423/*
424 * Local variables:
425 * compile-command: "gcc -DMODVERSIONS -DMODULE -D__KERNEL__ -Wall -Wstrict-prototypes -O6 -fomit-frame-pointer -I/usr/src/linux/drivers/net/tokenring/ -c proteon.c"
426 * alt-compile-command: "gcc -DMODULE -D__KERNEL__ -Wall -Wstrict-prototypes -O6 -fomit-frame-pointer -I/usr/src/linux/drivers/net/tokenring/ -c proteon.c"
427 * c-set-style "K&R"
428 * c-indent-level: 8
429 * c-basic-offset: 8
430 * tab-width: 8
431 * End:
432 */
diff --git a/drivers/net/tokenring/skisa.c b/drivers/net/tokenring/skisa.c
new file mode 100644
index 000000000000..3fab54a26466
--- /dev/null
+++ b/drivers/net/tokenring/skisa.c
@@ -0,0 +1,442 @@
1/*
2 * skisa.c: A network driver for SK-NET TMS380-based ISA token ring cards.
3 *
4 * Based on tmspci written 1999 by Adam Fritzler
5 *
6 * Written 2000 by Jochen Friedrich
7 * Dedicated to my girlfriend Steffi Bopp
8 *
9 * This software may be used and distributed according to the terms
10 * of the GNU General Public License, incorporated herein by reference.
11 *
12 * This driver module supports the following cards:
13 * - SysKonnect TR4/16(+) ISA (SK-4190)
14 *
15 * Maintainer(s):
16 * AF Adam Fritzler mid@auk.cx
17 * JF Jochen Friedrich jochen@scram.de
18 *
19 * Modification History:
20 * 14-Jan-01 JF Created
21 * 28-Oct-02 JF Fixed probe of card for static compilation.
22 * Fixed module init to not make hotplug go wild.
23 * 09-Nov-02 JF Fixed early bail out on out of memory
24 * situations if multiple cards are found.
25 * Cleaned up some unnecessary console SPAM.
26 * 09-Dec-02 JF Fixed module reference counting.
27 * 02-Jan-03 JF Renamed to skisa.c
28 *
29 */
30static const char version[] = "skisa.c: v1.03 09/12/2002 by Jochen Friedrich\n";
31
32#include <linux/module.h>
33#include <linux/kernel.h>
34#include <linux/errno.h>
35#include <linux/pci.h>
36#include <linux/init.h>
37#include <linux/netdevice.h>
38#include <linux/trdevice.h>
39
40#include <asm/system.h>
41#include <asm/io.h>
42#include <asm/irq.h>
43#include <asm/pci.h>
44#include <asm/dma.h>
45
46#include "tms380tr.h"
47
48#define SK_ISA_IO_EXTENT 32
49
50/* A zero-terminated list of I/O addresses to be probed. */
51static unsigned int portlist[] __initdata = {
52 0x0A20, 0x1A20, 0x0B20, 0x1B20, 0x0980, 0x1980, 0x0900, 0x1900,// SK
53 0
54};
55
56/* A zero-terminated list of IRQs to be probed.
57 * Used again after initial probe for sktr_chipset_init, called from sktr_open.
58 */
59static const unsigned short irqlist[] = {
60 3, 5, 9, 10, 11, 12, 15,
61 0
62};
63
64/* A zero-terminated list of DMAs to be probed. */
65static int dmalist[] __initdata = {
66 5, 6, 7,
67 0
68};
69
70static char isa_cardname[] = "SK NET TR 4/16 ISA\0";
71
72struct net_device *sk_isa_probe(int unit);
73static int sk_isa_open(struct net_device *dev);
74static void sk_isa_read_eeprom(struct net_device *dev);
75static unsigned short sk_isa_setnselout_pins(struct net_device *dev);
76
77static unsigned short sk_isa_sifreadb(struct net_device *dev, unsigned short reg)
78{
79 return inb(dev->base_addr + reg);
80}
81
82static unsigned short sk_isa_sifreadw(struct net_device *dev, unsigned short reg)
83{
84 return inw(dev->base_addr + reg);
85}
86
87static void sk_isa_sifwriteb(struct net_device *dev, unsigned short val, unsigned short reg)
88{
89 outb(val, dev->base_addr + reg);
90}
91
92static void sk_isa_sifwritew(struct net_device *dev, unsigned short val, unsigned short reg)
93{
94 outw(val, dev->base_addr + reg);
95}
96
97
98static int __init sk_isa_probe1(struct net_device *dev, int ioaddr)
99{
100 unsigned char old, chk1, chk2;
101
102 if (!request_region(ioaddr, SK_ISA_IO_EXTENT, isa_cardname))
103 return -ENODEV;
104
105 old = inb(ioaddr + SIFADR); /* Get the old SIFADR value */
106
107 chk1 = 0; /* Begin with check value 0 */
108 do {
109 /* Write new SIFADR value */
110 outb(chk1, ioaddr + SIFADR);
111
112 /* Read, invert and write */
113 chk2 = inb(ioaddr + SIFADD);
114 chk2 ^= 0x0FE;
115 outb(chk2, ioaddr + SIFADR);
116
117 /* Read, invert and compare */
118 chk2 = inb(ioaddr + SIFADD);
119 chk2 ^= 0x0FE;
120
121 if(chk1 != chk2) {
122 release_region(ioaddr, SK_ISA_IO_EXTENT);
123 return -ENODEV;
124 }
125
126 chk1 -= 2;
127 } while(chk1 != 0); /* Repeat 128 times (all byte values) */
128
129 /* Restore the SIFADR value */
130 outb(old, ioaddr + SIFADR);
131
132 dev->base_addr = ioaddr;
133 return 0;
134}
135
136static int __init setup_card(struct net_device *dev)
137{
138 struct net_local *tp;
139 static int versionprinted;
140 const unsigned *port;
141 int j, err = 0;
142
143 if (!dev)
144 return -ENOMEM;
145
146 SET_MODULE_OWNER(dev);
147 if (dev->base_addr) /* probe specific location */
148 err = sk_isa_probe1(dev, dev->base_addr);
149 else {
150 for (port = portlist; *port; port++) {
151 err = sk_isa_probe1(dev, *port);
152 if (!err)
153 break;
154 }
155 }
156 if (err)
157 goto out4;
158
159 /* At this point we have found a valid card. */
160
161 if (versionprinted++ == 0)
162 printk(KERN_DEBUG "%s", version);
163
164 err = -EIO;
165 if (tmsdev_init(dev, ISA_MAX_ADDRESS, NULL))
166 goto out4;
167
168 dev->base_addr &= ~3;
169
170 sk_isa_read_eeprom(dev);
171
172 printk(KERN_DEBUG "%s: Ring Station Address: ", dev->name);
173 printk("%2.2x", dev->dev_addr[0]);
174 for (j = 1; j < 6; j++)
175 printk(":%2.2x", dev->dev_addr[j]);
176 printk("\n");
177
178 tp = netdev_priv(dev);
179 tp->setnselout = sk_isa_setnselout_pins;
180
181 tp->sifreadb = sk_isa_sifreadb;
182 tp->sifreadw = sk_isa_sifreadw;
183 tp->sifwriteb = sk_isa_sifwriteb;
184 tp->sifwritew = sk_isa_sifwritew;
185
186 memcpy(tp->ProductID, isa_cardname, PROD_ID_SIZE + 1);
187
188 tp->tmspriv = NULL;
189
190 dev->open = sk_isa_open;
191 dev->stop = tms380tr_close;
192
193 if (dev->irq == 0)
194 {
195 for(j = 0; irqlist[j] != 0; j++)
196 {
197 dev->irq = irqlist[j];
198 if (!request_irq(dev->irq, tms380tr_interrupt, 0,
199 isa_cardname, dev))
200 break;
201 }
202
203 if(irqlist[j] == 0)
204 {
205 printk(KERN_INFO "%s: AutoSelect no IRQ available\n", dev->name);
206 goto out3;
207 }
208 }
209 else
210 {
211 for(j = 0; irqlist[j] != 0; j++)
212 if (irqlist[j] == dev->irq)
213 break;
214 if (irqlist[j] == 0)
215 {
216 printk(KERN_INFO "%s: Illegal IRQ %d specified\n",
217 dev->name, dev->irq);
218 goto out3;
219 }
220 if (request_irq(dev->irq, tms380tr_interrupt, 0,
221 isa_cardname, dev))
222 {
223 printk(KERN_INFO "%s: Selected IRQ %d not available\n",
224 dev->name, dev->irq);
225 goto out3;
226 }
227 }
228
229 if (dev->dma == 0)
230 {
231 for(j = 0; dmalist[j] != 0; j++)
232 {
233 dev->dma = dmalist[j];
234 if (!request_dma(dev->dma, isa_cardname))
235 break;
236 }
237
238 if(dmalist[j] == 0)
239 {
240 printk(KERN_INFO "%s: AutoSelect no DMA available\n", dev->name);
241 goto out2;
242 }
243 }
244 else
245 {
246 for(j = 0; dmalist[j] != 0; j++)
247 if (dmalist[j] == dev->dma)
248 break;
249 if (dmalist[j] == 0)
250 {
251 printk(KERN_INFO "%s: Illegal DMA %d specified\n",
252 dev->name, dev->dma);
253 goto out2;
254 }
255 if (request_dma(dev->dma, isa_cardname))
256 {
257 printk(KERN_INFO "%s: Selected DMA %d not available\n",
258 dev->name, dev->dma);
259 goto out2;
260 }
261 }
262
263 printk(KERN_DEBUG "%s: IO: %#4lx IRQ: %d DMA: %d\n",
264 dev->name, dev->base_addr, dev->irq, dev->dma);
265
266 err = register_netdev(dev);
267 if (err)
268 goto out;
269
270 return 0;
271out:
272 free_dma(dev->dma);
273out2:
274 free_irq(dev->irq, dev);
275out3:
276 tmsdev_term(dev);
277out4:
278 release_region(dev->base_addr, SK_ISA_IO_EXTENT);
279 return err;
280}
281
282struct net_device * __init sk_isa_probe(int unit)
283{
284 struct net_device *dev = alloc_trdev(sizeof(struct net_local));
285 int err = 0;
286
287 if (!dev)
288 return ERR_PTR(-ENOMEM);
289
290 if (unit >= 0) {
291 sprintf(dev->name, "tr%d", unit);
292 netdev_boot_setup_check(dev);
293 }
294
295 err = setup_card(dev);
296 if (err)
297 goto out;
298
299 return dev;
300out:
301 free_netdev(dev);
302 return ERR_PTR(err);
303}
304
305/*
306 * Reads MAC address from adapter RAM, which should've read it from
307 * the onboard ROM.
308 *
309 * Calling this on a board that does not support it can be a very
310 * dangerous thing. The Madge board, for instance, will lock your
311 * machine hard when this is called. Luckily, its supported in a
312 * separate driver. --ASF
313 */
314static void sk_isa_read_eeprom(struct net_device *dev)
315{
316 int i;
317
318 /* Address: 0000:0000 */
319 sk_isa_sifwritew(dev, 0, SIFADX);
320 sk_isa_sifwritew(dev, 0, SIFADR);
321
322 /* Read six byte MAC address data */
323 dev->addr_len = 6;
324 for(i = 0; i < 6; i++)
325 dev->dev_addr[i] = sk_isa_sifreadw(dev, SIFINC) >> 8;
326}
327
328unsigned short sk_isa_setnselout_pins(struct net_device *dev)
329{
330 return 0;
331}
332
333static int sk_isa_open(struct net_device *dev)
334{
335 struct net_local *tp = netdev_priv(dev);
336 unsigned short val = 0;
337 unsigned short oldval;
338 int i;
339
340 val = 0;
341 for(i = 0; irqlist[i] != 0; i++)
342 {
343 if(irqlist[i] == dev->irq)
344 break;
345 }
346
347 val |= CYCLE_TIME << 2;
348 val |= i << 4;
349 i = dev->dma - 5;
350 val |= i;
351 if(tp->DataRate == SPEED_4)
352 val |= LINE_SPEED_BIT;
353 else
354 val &= ~LINE_SPEED_BIT;
355 oldval = sk_isa_sifreadb(dev, POSREG);
356 /* Leave cycle bits alone */
357 oldval |= 0xf3;
358 val &= oldval;
359 sk_isa_sifwriteb(dev, val, POSREG);
360
361 return tms380tr_open(dev);
362}
363
364#ifdef MODULE
365
366#define ISATR_MAX_ADAPTERS 3
367
368static int io[ISATR_MAX_ADAPTERS];
369static int irq[ISATR_MAX_ADAPTERS];
370static int dma[ISATR_MAX_ADAPTERS];
371
372MODULE_LICENSE("GPL");
373
374module_param_array(io, int, NULL, 0);
375module_param_array(irq, int, NULL, 0);
376module_param_array(dma, int, NULL, 0);
377
378static struct net_device *sk_isa_dev[ISATR_MAX_ADAPTERS];
379
380int init_module(void)
381{
382 struct net_device *dev;
383 int i, num = 0, err = 0;
384
385 for (i = 0; i < ISATR_MAX_ADAPTERS ; i++) {
386 dev = alloc_trdev(sizeof(struct net_local));
387 if (!dev)
388 continue;
389
390 dev->base_addr = io[i];
391 dev->irq = irq[i];
392 dev->dma = dma[i];
393 err = setup_card(dev);
394
395 if (!err) {
396 sk_isa_dev[i] = dev;
397 ++num;
398 } else {
399 free_netdev(dev);
400 }
401 }
402
403 printk(KERN_NOTICE "skisa.c: %d cards found.\n", num);
404 /* Probe for cards. */
405 if (num == 0) {
406 printk(KERN_NOTICE "skisa.c: No cards found.\n");
407 return (-ENODEV);
408 }
409 return (0);
410}
411
412void cleanup_module(void)
413{
414 int i;
415
416 for (i = 0; i < ISATR_MAX_ADAPTERS ; i++) {
417 struct net_device *dev = sk_isa_dev[i];
418
419 if (!dev)
420 continue;
421
422 unregister_netdev(dev);
423 release_region(dev->base_addr, SK_ISA_IO_EXTENT);
424 free_irq(dev->irq, dev);
425 free_dma(dev->dma);
426 tmsdev_term(dev);
427 free_netdev(dev);
428 }
429}
430#endif /* MODULE */
431
432
433/*
434 * Local variables:
435 * compile-command: "gcc -DMODVERSIONS -DMODULE -D__KERNEL__ -Wall -Wstrict-prototypes -O6 -fomit-frame-pointer -I/usr/src/linux/drivers/net/tokenring/ -c skisa.c"
436 * alt-compile-command: "gcc -DMODULE -D__KERNEL__ -Wall -Wstrict-prototypes -O6 -fomit-frame-pointer -I/usr/src/linux/drivers/net/tokenring/ -c skisa.c"
437 * c-set-style "K&R"
438 * c-indent-level: 8
439 * c-basic-offset: 8
440 * tab-width: 8
441 * End:
442 */
diff --git a/drivers/net/tokenring/smctr.c b/drivers/net/tokenring/smctr.c
new file mode 100644
index 000000000000..5c8aeacb8318
--- /dev/null
+++ b/drivers/net/tokenring/smctr.c
@@ -0,0 +1,5742 @@
1/*
2 * smctr.c: A network driver for the SMC Token Ring Adapters.
3 *
4 * Written by Jay Schulist <jschlst@samba.org>
5 *
6 * This software may be used and distributed according to the terms
7 * of the GNU General Public License, incorporated herein by reference.
8 *
9 * This device driver works with the following SMC adapters:
10 * - SMC TokenCard Elite (8115T, chips 825/584)
11 * - SMC TokenCard Elite/A MCA (8115T/A, chips 825/594)
12 *
13 * Source(s):
14 * - SMC TokenCard SDK.
15 *
16 * Maintainer(s):
17 * JS Jay Schulist <jschlst@samba.org>
18 *
19 * Changes:
20 * 07102000 JS Fixed a timing problem in smctr_wait_cmd();
21 * Also added a bit more discriptive error msgs.
22 * 07122000 JS Fixed problem with detecting a card with
23 * module io/irq/mem specified.
24 *
25 * To do:
26 * 1. Multicast support.
27 *
28 * Initial 2.5 cleanup Alan Cox <alan@redhat.com> 2002/10/28
29 */
30
31#include <linux/module.h>
32#include <linux/config.h>
33#include <linux/kernel.h>
34#include <linux/types.h>
35#include <linux/fcntl.h>
36#include <linux/interrupt.h>
37#include <linux/ptrace.h>
38#include <linux/ioport.h>
39#include <linux/in.h>
40#include <linux/slab.h>
41#include <linux/string.h>
42#include <linux/time.h>
43#include <linux/errno.h>
44#include <linux/init.h>
45#include <linux/pci.h>
46#include <linux/mca-legacy.h>
47#include <linux/delay.h>
48#include <linux/netdevice.h>
49#include <linux/etherdevice.h>
50#include <linux/skbuff.h>
51#include <linux/trdevice.h>
52#include <linux/bitops.h>
53
54#include <asm/system.h>
55#include <asm/io.h>
56#include <asm/dma.h>
57#include <asm/irq.h>
58
59#if BITS_PER_LONG == 64
60#error FIXME: driver does not support 64-bit platforms
61#endif
62
63#include "smctr.h" /* Our Stuff */
64#include "smctr_firmware.h" /* SMC adapter firmware */
65
66static char version[] __initdata = KERN_INFO "smctr.c: v1.4 7/12/00 by jschlst@samba.org\n";
67static const char cardname[] = "smctr";
68
69
70#define SMCTR_IO_EXTENT 20
71
72#ifdef CONFIG_MCA_LEGACY
73static unsigned int smctr_posid = 0x6ec6;
74#endif
75
76static int ringspeed;
77
78/* SMC Name of the Adapter. */
79static char smctr_name[] = "SMC TokenCard";
80char *smctr_model = "Unknown";
81
82/* Use 0 for production, 1 for verification, 2 for debug, and
83 * 3 for very verbose debug.
84 */
85#ifndef SMCTR_DEBUG
86#define SMCTR_DEBUG 1
87#endif
88static unsigned int smctr_debug = SMCTR_DEBUG;
89
90/* smctr.c prototypes and functions are arranged alphabeticly
91 * for clearity, maintainability and pure old fashion fun.
92 */
93/* A */
94static int smctr_alloc_shared_memory(struct net_device *dev);
95
96/* B */
97static int smctr_bypass_state(struct net_device *dev);
98
99/* C */
100static int smctr_checksum_firmware(struct net_device *dev);
101static int __init smctr_chk_isa(struct net_device *dev);
102static int smctr_chg_rx_mask(struct net_device *dev);
103static int smctr_clear_int(struct net_device *dev);
104static int smctr_clear_trc_reset(int ioaddr);
105static int smctr_close(struct net_device *dev);
106
107/* D */
108static int smctr_decode_firmware(struct net_device *dev);
109static int smctr_disable_16bit(struct net_device *dev);
110static int smctr_disable_adapter_ctrl_store(struct net_device *dev);
111static int smctr_disable_bic_int(struct net_device *dev);
112
113/* E */
114static int smctr_enable_16bit(struct net_device *dev);
115static int smctr_enable_adapter_ctrl_store(struct net_device *dev);
116static int smctr_enable_adapter_ram(struct net_device *dev);
117static int smctr_enable_bic_int(struct net_device *dev);
118
119/* G */
120static int __init smctr_get_boardid(struct net_device *dev, int mca);
121static int smctr_get_group_address(struct net_device *dev);
122static int smctr_get_functional_address(struct net_device *dev);
123static unsigned int smctr_get_num_rx_bdbs(struct net_device *dev);
124static int smctr_get_physical_drop_number(struct net_device *dev);
125static __u8 *smctr_get_rx_pointer(struct net_device *dev, short queue);
126static int smctr_get_station_id(struct net_device *dev);
127static struct net_device_stats *smctr_get_stats(struct net_device *dev);
128static FCBlock *smctr_get_tx_fcb(struct net_device *dev, __u16 queue,
129 __u16 bytes_count);
130static int smctr_get_upstream_neighbor_addr(struct net_device *dev);
131
132/* H */
133static int smctr_hardware_send_packet(struct net_device *dev,
134 struct net_local *tp);
135/* I */
136static int smctr_init_acbs(struct net_device *dev);
137static int smctr_init_adapter(struct net_device *dev);
138static int smctr_init_card_real(struct net_device *dev);
139static int smctr_init_rx_bdbs(struct net_device *dev);
140static int smctr_init_rx_fcbs(struct net_device *dev);
141static int smctr_init_shared_memory(struct net_device *dev);
142static int smctr_init_tx_bdbs(struct net_device *dev);
143static int smctr_init_tx_fcbs(struct net_device *dev);
144static int smctr_internal_self_test(struct net_device *dev);
145static irqreturn_t smctr_interrupt(int irq, void *dev_id, struct pt_regs *regs);
146static int smctr_issue_enable_int_cmd(struct net_device *dev,
147 __u16 interrupt_enable_mask);
148static int smctr_issue_int_ack(struct net_device *dev, __u16 iack_code,
149 __u16 ibits);
150static int smctr_issue_init_timers_cmd(struct net_device *dev);
151static int smctr_issue_init_txrx_cmd(struct net_device *dev);
152static int smctr_issue_insert_cmd(struct net_device *dev);
153static int smctr_issue_read_ring_status_cmd(struct net_device *dev);
154static int smctr_issue_read_word_cmd(struct net_device *dev, __u16 aword_cnt);
155static int smctr_issue_remove_cmd(struct net_device *dev);
156static int smctr_issue_resume_acb_cmd(struct net_device *dev);
157static int smctr_issue_resume_rx_bdb_cmd(struct net_device *dev, __u16 queue);
158static int smctr_issue_resume_rx_fcb_cmd(struct net_device *dev, __u16 queue);
159static int smctr_issue_resume_tx_fcb_cmd(struct net_device *dev, __u16 queue);
160static int smctr_issue_test_internal_rom_cmd(struct net_device *dev);
161static int smctr_issue_test_hic_cmd(struct net_device *dev);
162static int smctr_issue_test_mac_reg_cmd(struct net_device *dev);
163static int smctr_issue_trc_loopback_cmd(struct net_device *dev);
164static int smctr_issue_tri_loopback_cmd(struct net_device *dev);
165static int smctr_issue_write_byte_cmd(struct net_device *dev,
166 short aword_cnt, void *byte);
167static int smctr_issue_write_word_cmd(struct net_device *dev,
168 short aword_cnt, void *word);
169
170/* J */
171static int smctr_join_complete_state(struct net_device *dev);
172
173/* L */
174static int smctr_link_tx_fcbs_to_bdbs(struct net_device *dev);
175static int smctr_load_firmware(struct net_device *dev);
176static int smctr_load_node_addr(struct net_device *dev);
177static int smctr_lobe_media_test(struct net_device *dev);
178static int smctr_lobe_media_test_cmd(struct net_device *dev);
179static int smctr_lobe_media_test_state(struct net_device *dev);
180
181/* M */
182static int smctr_make_8025_hdr(struct net_device *dev,
183 MAC_HEADER *rmf, MAC_HEADER *tmf, __u16 ac_fc);
184static int smctr_make_access_pri(struct net_device *dev,
185 MAC_SUB_VECTOR *tsv);
186static int smctr_make_addr_mod(struct net_device *dev, MAC_SUB_VECTOR *tsv);
187static int smctr_make_auth_funct_class(struct net_device *dev,
188 MAC_SUB_VECTOR *tsv);
189static int smctr_make_corr(struct net_device *dev,
190 MAC_SUB_VECTOR *tsv, __u16 correlator);
191static int smctr_make_funct_addr(struct net_device *dev,
192 MAC_SUB_VECTOR *tsv);
193static int smctr_make_group_addr(struct net_device *dev,
194 MAC_SUB_VECTOR *tsv);
195static int smctr_make_phy_drop_num(struct net_device *dev,
196 MAC_SUB_VECTOR *tsv);
197static int smctr_make_product_id(struct net_device *dev, MAC_SUB_VECTOR *tsv);
198static int smctr_make_station_id(struct net_device *dev, MAC_SUB_VECTOR *tsv);
199static int smctr_make_ring_station_status(struct net_device *dev,
200 MAC_SUB_VECTOR *tsv);
201static int smctr_make_ring_station_version(struct net_device *dev,
202 MAC_SUB_VECTOR *tsv);
203static int smctr_make_tx_status_code(struct net_device *dev,
204 MAC_SUB_VECTOR *tsv, __u16 tx_fstatus);
205static int smctr_make_upstream_neighbor_addr(struct net_device *dev,
206 MAC_SUB_VECTOR *tsv);
207static int smctr_make_wrap_data(struct net_device *dev,
208 MAC_SUB_VECTOR *tsv);
209
210/* O */
211static int smctr_open(struct net_device *dev);
212static int smctr_open_tr(struct net_device *dev);
213
214/* P */
215struct net_device *smctr_probe(int unit);
216static int __init smctr_probe1(struct net_device *dev, int ioaddr);
217static int smctr_process_rx_packet(MAC_HEADER *rmf, __u16 size,
218 struct net_device *dev, __u16 rx_status);
219
220/* R */
221static int smctr_ram_memory_test(struct net_device *dev);
222static int smctr_rcv_chg_param(struct net_device *dev, MAC_HEADER *rmf,
223 __u16 *correlator);
224static int smctr_rcv_init(struct net_device *dev, MAC_HEADER *rmf,
225 __u16 *correlator);
226static int smctr_rcv_tx_forward(struct net_device *dev, MAC_HEADER *rmf);
227static int smctr_rcv_rq_addr_state_attch(struct net_device *dev,
228 MAC_HEADER *rmf, __u16 *correlator);
229static int smctr_rcv_unknown(struct net_device *dev, MAC_HEADER *rmf,
230 __u16 *correlator);
231static int smctr_reset_adapter(struct net_device *dev);
232static int smctr_restart_tx_chain(struct net_device *dev, short queue);
233static int smctr_ring_status_chg(struct net_device *dev);
234static int smctr_rx_frame(struct net_device *dev);
235
236/* S */
237static int smctr_send_dat(struct net_device *dev);
238static int smctr_send_packet(struct sk_buff *skb, struct net_device *dev);
239static int smctr_send_lobe_media_test(struct net_device *dev);
240static int smctr_send_rpt_addr(struct net_device *dev, MAC_HEADER *rmf,
241 __u16 correlator);
242static int smctr_send_rpt_attch(struct net_device *dev, MAC_HEADER *rmf,
243 __u16 correlator);
244static int smctr_send_rpt_state(struct net_device *dev, MAC_HEADER *rmf,
245 __u16 correlator);
246static int smctr_send_rpt_tx_forward(struct net_device *dev,
247 MAC_HEADER *rmf, __u16 tx_fstatus);
248static int smctr_send_rsp(struct net_device *dev, MAC_HEADER *rmf,
249 __u16 rcode, __u16 correlator);
250static int smctr_send_rq_init(struct net_device *dev);
251static int smctr_send_tx_forward(struct net_device *dev, MAC_HEADER *rmf,
252 __u16 *tx_fstatus);
253static int smctr_set_auth_access_pri(struct net_device *dev,
254 MAC_SUB_VECTOR *rsv);
255static int smctr_set_auth_funct_class(struct net_device *dev,
256 MAC_SUB_VECTOR *rsv);
257static int smctr_set_corr(struct net_device *dev, MAC_SUB_VECTOR *rsv,
258 __u16 *correlator);
259static int smctr_set_error_timer_value(struct net_device *dev,
260 MAC_SUB_VECTOR *rsv);
261static int smctr_set_frame_forward(struct net_device *dev,
262 MAC_SUB_VECTOR *rsv, __u8 dc_sc);
263static int smctr_set_local_ring_num(struct net_device *dev,
264 MAC_SUB_VECTOR *rsv);
265static unsigned short smctr_set_ctrl_attention(struct net_device *dev);
266static void smctr_set_multicast_list(struct net_device *dev);
267static int smctr_set_page(struct net_device *dev, __u8 *buf);
268static int smctr_set_phy_drop(struct net_device *dev,
269 MAC_SUB_VECTOR *rsv);
270static int smctr_set_ring_speed(struct net_device *dev);
271static int smctr_set_rx_look_ahead(struct net_device *dev);
272static int smctr_set_trc_reset(int ioaddr);
273static int smctr_setup_single_cmd(struct net_device *dev,
274 __u16 command, __u16 subcommand);
275static int smctr_setup_single_cmd_w_data(struct net_device *dev,
276 __u16 command, __u16 subcommand);
277static char *smctr_malloc(struct net_device *dev, __u16 size);
278static int smctr_status_chg(struct net_device *dev);
279
280/* T */
281static void smctr_timeout(struct net_device *dev);
282static int smctr_trc_send_packet(struct net_device *dev, FCBlock *fcb,
283 __u16 queue);
284static __u16 smctr_tx_complete(struct net_device *dev, __u16 queue);
285static unsigned short smctr_tx_move_frame(struct net_device *dev,
286 struct sk_buff *skb, __u8 *pbuff, unsigned int bytes);
287
288/* U */
289static int smctr_update_err_stats(struct net_device *dev);
290static int smctr_update_rx_chain(struct net_device *dev, __u16 queue);
291static int smctr_update_tx_chain(struct net_device *dev, FCBlock *fcb,
292 __u16 queue);
293
294/* W */
295static int smctr_wait_cmd(struct net_device *dev);
296static int smctr_wait_while_cbusy(struct net_device *dev);
297
298#define TO_256_BYTE_BOUNDRY(X) (((X + 0xff) & 0xff00) - X)
299#define TO_PARAGRAPH_BOUNDRY(X) (((X + 0x0f) & 0xfff0) - X)
300#define PARAGRAPH_BOUNDRY(X) smctr_malloc(dev, TO_PARAGRAPH_BOUNDRY(X))
301
302/* Allocate Adapter Shared Memory.
303 * IMPORTANT NOTE: Any changes to this function MUST be mirrored in the
304 * function "get_num_rx_bdbs" below!!!
305 *
306 * Order of memory allocation:
307 *
308 * 0. Initial System Configuration Block Pointer
309 * 1. System Configuration Block
310 * 2. System Control Block
311 * 3. Action Command Block
312 * 4. Interrupt Status Block
313 *
314 * 5. MAC TX FCB'S
315 * 6. NON-MAC TX FCB'S
316 * 7. MAC TX BDB'S
317 * 8. NON-MAC TX BDB'S
318 * 9. MAC RX FCB'S
319 * 10. NON-MAC RX FCB'S
320 * 11. MAC RX BDB'S
321 * 12. NON-MAC RX BDB'S
322 * 13. MAC TX Data Buffer( 1, 256 byte buffer)
323 * 14. MAC RX Data Buffer( 1, 256 byte buffer)
324 *
325 * 15. NON-MAC TX Data Buffer
326 * 16. NON-MAC RX Data Buffer
327 */
328static int smctr_alloc_shared_memory(struct net_device *dev)
329{
330 struct net_local *tp = netdev_priv(dev);
331
332 if(smctr_debug > 10)
333 printk(KERN_DEBUG "%s: smctr_alloc_shared_memory\n", dev->name);
334
335 /* Allocate initial System Control Block pointer.
336 * This pointer is located in the last page, last offset - 4.
337 */
338 tp->iscpb_ptr = (ISCPBlock *)(tp->ram_access + ((__u32)64 * 0x400)
339 - (long)ISCP_BLOCK_SIZE);
340
341 /* Allocate System Control Blocks. */
342 tp->scgb_ptr = (SCGBlock *)smctr_malloc(dev, sizeof(SCGBlock));
343 PARAGRAPH_BOUNDRY(tp->sh_mem_used);
344
345 tp->sclb_ptr = (SCLBlock *)smctr_malloc(dev, sizeof(SCLBlock));
346 PARAGRAPH_BOUNDRY(tp->sh_mem_used);
347
348 tp->acb_head = (ACBlock *)smctr_malloc(dev,
349 sizeof(ACBlock)*tp->num_acbs);
350 PARAGRAPH_BOUNDRY(tp->sh_mem_used);
351
352 tp->isb_ptr = (ISBlock *)smctr_malloc(dev, sizeof(ISBlock));
353 PARAGRAPH_BOUNDRY(tp->sh_mem_used);
354
355 tp->misc_command_data = (__u16 *)smctr_malloc(dev, MISC_DATA_SIZE);
356 PARAGRAPH_BOUNDRY(tp->sh_mem_used);
357
358 /* Allocate transmit FCBs. */
359 tp->tx_fcb_head[MAC_QUEUE] = (FCBlock *)smctr_malloc(dev,
360 sizeof(FCBlock) * tp->num_tx_fcbs[MAC_QUEUE]);
361
362 tp->tx_fcb_head[NON_MAC_QUEUE] = (FCBlock *)smctr_malloc(dev,
363 sizeof(FCBlock) * tp->num_tx_fcbs[NON_MAC_QUEUE]);
364
365 tp->tx_fcb_head[BUG_QUEUE] = (FCBlock *)smctr_malloc(dev,
366 sizeof(FCBlock) * tp->num_tx_fcbs[BUG_QUEUE]);
367
368 /* Allocate transmit BDBs. */
369 tp->tx_bdb_head[MAC_QUEUE] = (BDBlock *)smctr_malloc(dev,
370 sizeof(BDBlock) * tp->num_tx_bdbs[MAC_QUEUE]);
371
372 tp->tx_bdb_head[NON_MAC_QUEUE] = (BDBlock *)smctr_malloc(dev,
373 sizeof(BDBlock) * tp->num_tx_bdbs[NON_MAC_QUEUE]);
374
375 tp->tx_bdb_head[BUG_QUEUE] = (BDBlock *)smctr_malloc(dev,
376 sizeof(BDBlock) * tp->num_tx_bdbs[BUG_QUEUE]);
377
378 /* Allocate receive FCBs. */
379 tp->rx_fcb_head[MAC_QUEUE] = (FCBlock *)smctr_malloc(dev,
380 sizeof(FCBlock) * tp->num_rx_fcbs[MAC_QUEUE]);
381
382 tp->rx_fcb_head[NON_MAC_QUEUE] = (FCBlock *)smctr_malloc(dev,
383 sizeof(FCBlock) * tp->num_rx_fcbs[NON_MAC_QUEUE]);
384
385 /* Allocate receive BDBs. */
386 tp->rx_bdb_head[MAC_QUEUE] = (BDBlock *)smctr_malloc(dev,
387 sizeof(BDBlock) * tp->num_rx_bdbs[MAC_QUEUE]);
388
389 tp->rx_bdb_end[MAC_QUEUE] = (BDBlock *)smctr_malloc(dev, 0);
390
391 tp->rx_bdb_head[NON_MAC_QUEUE] = (BDBlock *)smctr_malloc(dev,
392 sizeof(BDBlock) * tp->num_rx_bdbs[NON_MAC_QUEUE]);
393
394 tp->rx_bdb_end[NON_MAC_QUEUE] = (BDBlock *)smctr_malloc(dev, 0);
395
396 /* Allocate MAC transmit buffers.
397 * MAC Tx Buffers doen't have to be on an ODD Boundry.
398 */
399 tp->tx_buff_head[MAC_QUEUE]
400 = (__u16 *)smctr_malloc(dev, tp->tx_buff_size[MAC_QUEUE]);
401 tp->tx_buff_curr[MAC_QUEUE] = tp->tx_buff_head[MAC_QUEUE];
402 tp->tx_buff_end [MAC_QUEUE] = (__u16 *)smctr_malloc(dev, 0);
403
404 /* Allocate BUG transmit buffers. */
405 tp->tx_buff_head[BUG_QUEUE]
406 = (__u16 *)smctr_malloc(dev, tp->tx_buff_size[BUG_QUEUE]);
407 tp->tx_buff_curr[BUG_QUEUE] = tp->tx_buff_head[BUG_QUEUE];
408 tp->tx_buff_end[BUG_QUEUE] = (__u16 *)smctr_malloc(dev, 0);
409
410 /* Allocate MAC receive data buffers.
411 * MAC Rx buffer doesn't have to be on a 256 byte boundary.
412 */
413 tp->rx_buff_head[MAC_QUEUE] = (__u16 *)smctr_malloc(dev,
414 RX_DATA_BUFFER_SIZE * tp->num_rx_bdbs[MAC_QUEUE]);
415 tp->rx_buff_end[MAC_QUEUE] = (__u16 *)smctr_malloc(dev, 0);
416
417 /* Allocate Non-MAC transmit buffers.
418 * ?? For maximum Netware performance, put Tx Buffers on
419 * ODD Boundry and then restore malloc to Even Boundrys.
420 */
421 smctr_malloc(dev, 1L);
422 tp->tx_buff_head[NON_MAC_QUEUE]
423 = (__u16 *)smctr_malloc(dev, tp->tx_buff_size[NON_MAC_QUEUE]);
424 tp->tx_buff_curr[NON_MAC_QUEUE] = tp->tx_buff_head[NON_MAC_QUEUE];
425 tp->tx_buff_end [NON_MAC_QUEUE] = (__u16 *)smctr_malloc(dev, 0);
426 smctr_malloc(dev, 1L);
427
428 /* Allocate Non-MAC receive data buffers.
429 * To guarantee a minimum of 256 contigous memory to
430 * UM_Receive_Packet's lookahead pointer, before a page
431 * change or ring end is encountered, place each rx buffer on
432 * a 256 byte boundary.
433 */
434 smctr_malloc(dev, TO_256_BYTE_BOUNDRY(tp->sh_mem_used));
435 tp->rx_buff_head[NON_MAC_QUEUE] = (__u16 *)smctr_malloc(dev,
436 RX_DATA_BUFFER_SIZE * tp->num_rx_bdbs[NON_MAC_QUEUE]);
437 tp->rx_buff_end[NON_MAC_QUEUE] = (__u16 *)smctr_malloc(dev, 0);
438
439 return (0);
440}
441
442/* Enter Bypass state. */
443static int smctr_bypass_state(struct net_device *dev)
444{
445 int err;
446
447 if(smctr_debug > 10)
448 printk(KERN_DEBUG "%s: smctr_bypass_state\n", dev->name);
449
450 err = smctr_setup_single_cmd(dev, ACB_CMD_CHANGE_JOIN_STATE, JS_BYPASS_STATE);
451
452 return (err);
453}
454
455static int smctr_checksum_firmware(struct net_device *dev)
456{
457 struct net_local *tp = netdev_priv(dev);
458 __u16 i, checksum = 0;
459
460 if(smctr_debug > 10)
461 printk(KERN_DEBUG "%s: smctr_checksum_firmware\n", dev->name);
462
463 smctr_enable_adapter_ctrl_store(dev);
464
465 for(i = 0; i < CS_RAM_SIZE; i += 2)
466 checksum += *((__u16 *)(tp->ram_access + i));
467
468 tp->microcode_version = *(__u16 *)(tp->ram_access
469 + CS_RAM_VERSION_OFFSET);
470 tp->microcode_version >>= 8;
471
472 smctr_disable_adapter_ctrl_store(dev);
473
474 if(checksum)
475 return (checksum);
476
477 return (0);
478}
479
480static int __init smctr_chk_mca(struct net_device *dev)
481{
482#ifdef CONFIG_MCA_LEGACY
483 struct net_local *tp = netdev_priv(dev);
484 int current_slot;
485 __u8 r1, r2, r3, r4, r5;
486
487 current_slot = mca_find_unused_adapter(smctr_posid, 0);
488 if(current_slot == MCA_NOTFOUND)
489 return (-ENODEV);
490
491 mca_set_adapter_name(current_slot, smctr_name);
492 mca_mark_as_used(current_slot);
493 tp->slot_num = current_slot;
494
495 r1 = mca_read_stored_pos(tp->slot_num, 2);
496 r2 = mca_read_stored_pos(tp->slot_num, 3);
497
498 if(tp->slot_num)
499 outb(CNFG_POS_CONTROL_REG, (__u8)((tp->slot_num - 1) | CNFG_SLOT_ENABLE_BIT));
500 else
501 outb(CNFG_POS_CONTROL_REG, (__u8)((tp->slot_num) | CNFG_SLOT_ENABLE_BIT));
502
503 r1 = inb(CNFG_POS_REG1);
504 r2 = inb(CNFG_POS_REG0);
505
506 tp->bic_type = BIC_594_CHIP;
507
508 /* IO */
509 r2 = mca_read_stored_pos(tp->slot_num, 2);
510 r2 &= 0xF0;
511 dev->base_addr = ((__u16)r2 << 8) + (__u16)0x800;
512 request_region(dev->base_addr, SMCTR_IO_EXTENT, smctr_name);
513
514 /* IRQ */
515 r5 = mca_read_stored_pos(tp->slot_num, 5);
516 r5 &= 0xC;
517 switch(r5)
518 {
519 case 0:
520 dev->irq = 3;
521 break;
522
523 case 0x4:
524 dev->irq = 4;
525 break;
526
527 case 0x8:
528 dev->irq = 10;
529 break;
530
531 default:
532 dev->irq = 15;
533 break;
534 }
535 if (request_irq(dev->irq, smctr_interrupt, SA_SHIRQ, smctr_name, dev)) {
536 release_region(dev->base_addr, SMCTR_IO_EXTENT);
537 return -ENODEV;
538 }
539
540 /* Get RAM base */
541 r3 = mca_read_stored_pos(tp->slot_num, 3);
542 tp->ram_base = ((__u32)(r3 & 0x7) << 13) + 0x0C0000;
543 if (r3 & 0x8)
544 tp->ram_base += 0x010000;
545 if (r3 & 0x80)
546 tp->ram_base += 0xF00000;
547
548 /* Get Ram Size */
549 r3 &= 0x30;
550 r3 >>= 4;
551
552 tp->ram_usable = (__u16)CNFG_SIZE_8KB << r3;
553 tp->ram_size = (__u16)CNFG_SIZE_64KB;
554 tp->board_id |= TOKEN_MEDIA;
555
556 r4 = mca_read_stored_pos(tp->slot_num, 4);
557 tp->rom_base = ((__u32)(r4 & 0x7) << 13) + 0x0C0000;
558 if (r4 & 0x8)
559 tp->rom_base += 0x010000;
560
561 /* Get ROM size. */
562 r4 >>= 4;
563 switch (r4) {
564 case 0:
565 tp->rom_size = CNFG_SIZE_8KB;
566 break;
567 case 1:
568 tp->rom_size = CNFG_SIZE_16KB;
569 break;
570 case 2:
571 tp->rom_size = CNFG_SIZE_32KB;
572 break;
573 default:
574 tp->rom_size = ROM_DISABLE;
575 }
576
577 /* Get Media Type. */
578 r5 = mca_read_stored_pos(tp->slot_num, 5);
579 r5 &= CNFG_MEDIA_TYPE_MASK;
580 switch(r5)
581 {
582 case (0):
583 tp->media_type = MEDIA_STP_4;
584 break;
585
586 case (1):
587 tp->media_type = MEDIA_STP_16;
588 break;
589
590 case (3):
591 tp->media_type = MEDIA_UTP_16;
592 break;
593
594 default:
595 tp->media_type = MEDIA_UTP_4;
596 break;
597 }
598 tp->media_menu = 14;
599
600 r2 = mca_read_stored_pos(tp->slot_num, 2);
601 if(!(r2 & 0x02))
602 tp->mode_bits |= EARLY_TOKEN_REL;
603
604 /* Disable slot */
605 outb(CNFG_POS_CONTROL_REG, 0);
606
607 tp->board_id = smctr_get_boardid(dev, 1);
608 switch(tp->board_id & 0xffff)
609 {
610 case WD8115TA:
611 smctr_model = "8115T/A";
612 break;
613
614 case WD8115T:
615 if(tp->extra_info & CHIP_REV_MASK)
616 smctr_model = "8115T rev XE";
617 else
618 smctr_model = "8115T rev XD";
619 break;
620
621 default:
622 smctr_model = "Unknown";
623 break;
624 }
625
626 return (0);
627#else
628 return (-1);
629#endif /* CONFIG_MCA_LEGACY */
630}
631
632static int smctr_chg_rx_mask(struct net_device *dev)
633{
634 struct net_local *tp = netdev_priv(dev);
635 int err = 0;
636
637 if(smctr_debug > 10)
638 printk(KERN_DEBUG "%s: smctr_chg_rx_mask\n", dev->name);
639
640 smctr_enable_16bit(dev);
641 smctr_set_page(dev, (__u8 *)tp->ram_access);
642
643 if(tp->mode_bits & LOOPING_MODE_MASK)
644 tp->config_word0 |= RX_OWN_BIT;
645 else
646 tp->config_word0 &= ~RX_OWN_BIT;
647
648 if(tp->receive_mask & PROMISCUOUS_MODE)
649 tp->config_word0 |= PROMISCUOUS_BIT;
650 else
651 tp->config_word0 &= ~PROMISCUOUS_BIT;
652
653 if(tp->receive_mask & ACCEPT_ERR_PACKETS)
654 tp->config_word0 |= SAVBAD_BIT;
655 else
656 tp->config_word0 &= ~SAVBAD_BIT;
657
658 if(tp->receive_mask & ACCEPT_ATT_MAC_FRAMES)
659 tp->config_word0 |= RXATMAC;
660 else
661 tp->config_word0 &= ~RXATMAC;
662
663 if(tp->receive_mask & ACCEPT_MULTI_PROM)
664 tp->config_word1 |= MULTICAST_ADDRESS_BIT;
665 else
666 tp->config_word1 &= ~MULTICAST_ADDRESS_BIT;
667
668 if(tp->receive_mask & ACCEPT_SOURCE_ROUTING_SPANNING)
669 tp->config_word1 |= SOURCE_ROUTING_SPANNING_BITS;
670 else
671 {
672 if(tp->receive_mask & ACCEPT_SOURCE_ROUTING)
673 tp->config_word1 |= SOURCE_ROUTING_EXPLORER_BIT;
674 else
675 tp->config_word1 &= ~SOURCE_ROUTING_SPANNING_BITS;
676 }
677
678 if((err = smctr_issue_write_word_cmd(dev, RW_CONFIG_REGISTER_0,
679 &tp->config_word0)))
680 {
681 return (err);
682 }
683
684 if((err = smctr_issue_write_word_cmd(dev, RW_CONFIG_REGISTER_1,
685 &tp->config_word1)))
686 {
687 return (err);
688 }
689
690 smctr_disable_16bit(dev);
691
692 return (0);
693}
694
695static int smctr_clear_int(struct net_device *dev)
696{
697 struct net_local *tp = netdev_priv(dev);
698
699 outb((tp->trc_mask | CSR_CLRTINT), dev->base_addr + CSR);
700
701 return (0);
702}
703
704static int smctr_clear_trc_reset(int ioaddr)
705{
706 __u8 r;
707
708 r = inb(ioaddr + MSR);
709 outb(~MSR_RST & r, ioaddr + MSR);
710
711 return (0);
712}
713
714/*
715 * The inverse routine to smctr_open().
716 */
717static int smctr_close(struct net_device *dev)
718{
719 struct net_local *tp = netdev_priv(dev);
720 struct sk_buff *skb;
721 int err;
722
723 netif_stop_queue(dev);
724
725 tp->cleanup = 1;
726
727 /* Check to see if adapter is already in a closed state. */
728 if(tp->status != OPEN)
729 return (0);
730
731 smctr_enable_16bit(dev);
732 smctr_set_page(dev, (__u8 *)tp->ram_access);
733
734 if((err = smctr_issue_remove_cmd(dev)))
735 {
736 smctr_disable_16bit(dev);
737 return (err);
738 }
739
740 for(;;)
741 {
742 skb = skb_dequeue(&tp->SendSkbQueue);
743 if(skb == NULL)
744 break;
745 tp->QueueSkb++;
746 dev_kfree_skb(skb);
747 }
748
749
750 return (0);
751}
752
753static int smctr_decode_firmware(struct net_device *dev)
754{
755 struct net_local *tp = netdev_priv(dev);
756 short bit = 0x80, shift = 12;
757 DECODE_TREE_NODE *tree;
758 short branch, tsize;
759 __u16 buff = 0;
760 long weight;
761 __u8 *ucode;
762 __u16 *mem;
763
764 if(smctr_debug > 10)
765 printk(KERN_DEBUG "%s: smctr_decode_firmware\n", dev->name);
766
767 weight = *(long *)(tp->ptr_ucode + WEIGHT_OFFSET);
768 tsize = *(__u8 *)(tp->ptr_ucode + TREE_SIZE_OFFSET);
769 tree = (DECODE_TREE_NODE *)(tp->ptr_ucode + TREE_OFFSET);
770 ucode = (__u8 *)(tp->ptr_ucode + TREE_OFFSET
771 + (tsize * sizeof(DECODE_TREE_NODE)));
772 mem = (__u16 *)(tp->ram_access);
773
774 while(weight)
775 {
776 branch = ROOT;
777 while((tree + branch)->tag != LEAF && weight)
778 {
779 branch = *ucode & bit ? (tree + branch)->llink
780 : (tree + branch)->rlink;
781
782 bit >>= 1;
783 weight--;
784
785 if(bit == 0)
786 {
787 bit = 0x80;
788 ucode++;
789 }
790 }
791
792 buff |= (tree + branch)->info << shift;
793 shift -= 4;
794
795 if(shift < 0)
796 {
797 *(mem++) = SWAP_BYTES(buff);
798 buff = 0;
799 shift = 12;
800 }
801 }
802
803 /* The following assumes the Control Store Memory has
804 * been initialized to zero. If the last partial word
805 * is zero, it will not be written.
806 */
807 if(buff)
808 *(mem++) = SWAP_BYTES(buff);
809
810 return (0);
811}
812
813static int smctr_disable_16bit(struct net_device *dev)
814{
815 return (0);
816}
817
818/*
819 * On Exit, Adapter is:
820 * 1. TRC is in a reset state and un-initialized.
821 * 2. Adapter memory is enabled.
822 * 3. Control Store memory is out of context (-WCSS is 1).
823 */
824static int smctr_disable_adapter_ctrl_store(struct net_device *dev)
825{
826 struct net_local *tp = netdev_priv(dev);
827 int ioaddr = dev->base_addr;
828
829 if(smctr_debug > 10)
830 printk(KERN_DEBUG "%s: smctr_disable_adapter_ctrl_store\n", dev->name);
831
832 tp->trc_mask |= CSR_WCSS;
833 outb(tp->trc_mask, ioaddr + CSR);
834
835 return (0);
836}
837
838static int smctr_disable_bic_int(struct net_device *dev)
839{
840 struct net_local *tp = netdev_priv(dev);
841 int ioaddr = dev->base_addr;
842
843 tp->trc_mask = CSR_MSK_ALL | CSR_MSKCBUSY
844 | CSR_MSKTINT | CSR_WCSS;
845 outb(tp->trc_mask, ioaddr + CSR);
846
847 return (0);
848}
849
850static int smctr_enable_16bit(struct net_device *dev)
851{
852 struct net_local *tp = netdev_priv(dev);
853 __u8 r;
854
855 if(tp->adapter_bus == BUS_ISA16_TYPE)
856 {
857 r = inb(dev->base_addr + LAAR);
858 outb((r | LAAR_MEM16ENB), dev->base_addr + LAAR);
859 }
860
861 return (0);
862}
863
864/*
865 * To enable the adapter control store memory:
866 * 1. Adapter must be in a RESET state.
867 * 2. Adapter memory must be enabled.
868 * 3. Control Store Memory is in context (-WCSS is 0).
869 */
870static int smctr_enable_adapter_ctrl_store(struct net_device *dev)
871{
872 struct net_local *tp = netdev_priv(dev);
873 int ioaddr = dev->base_addr;
874
875 if(smctr_debug > 10)
876 printk(KERN_DEBUG "%s: smctr_enable_adapter_ctrl_store\n", dev->name);
877
878 smctr_set_trc_reset(ioaddr);
879 smctr_enable_adapter_ram(dev);
880
881 tp->trc_mask &= ~CSR_WCSS;
882 outb(tp->trc_mask, ioaddr + CSR);
883
884 return (0);
885}
886
887static int smctr_enable_adapter_ram(struct net_device *dev)
888{
889 int ioaddr = dev->base_addr;
890 __u8 r;
891
892 if(smctr_debug > 10)
893 printk(KERN_DEBUG "%s: smctr_enable_adapter_ram\n", dev->name);
894
895 r = inb(ioaddr + MSR);
896 outb(MSR_MEMB | r, ioaddr + MSR);
897
898 return (0);
899}
900
901static int smctr_enable_bic_int(struct net_device *dev)
902{
903 struct net_local *tp = netdev_priv(dev);
904 int ioaddr = dev->base_addr;
905 __u8 r;
906
907 switch(tp->bic_type)
908 {
909 case (BIC_584_CHIP):
910 tp->trc_mask = CSR_MSKCBUSY | CSR_WCSS;
911 outb(tp->trc_mask, ioaddr + CSR);
912 r = inb(ioaddr + IRR);
913 outb(r | IRR_IEN, ioaddr + IRR);
914 break;
915
916 case (BIC_594_CHIP):
917 tp->trc_mask = CSR_MSKCBUSY | CSR_WCSS;
918 outb(tp->trc_mask, ioaddr + CSR);
919 r = inb(ioaddr + IMCCR);
920 outb(r | IMCCR_EIL, ioaddr + IMCCR);
921 break;
922 }
923
924 return (0);
925}
926
927static int __init smctr_chk_isa(struct net_device *dev)
928{
929 struct net_local *tp = netdev_priv(dev);
930 int ioaddr = dev->base_addr;
931 __u8 r1, r2, b, chksum = 0;
932 __u16 r;
933 int i;
934 int err = -ENODEV;
935
936 if(smctr_debug > 10)
937 printk(KERN_DEBUG "%s: smctr_chk_isa %#4x\n", dev->name, ioaddr);
938
939 if((ioaddr & 0x1F) != 0)
940 goto out;
941
942 /* Grab the region so that no one else tries to probe our ioports. */
943 if (!request_region(ioaddr, SMCTR_IO_EXTENT, smctr_name)) {
944 err = -EBUSY;
945 goto out;
946 }
947
948 /* Checksum SMC node address */
949 for(i = 0; i < 8; i++)
950 {
951 b = inb(ioaddr + LAR0 + i);
952 chksum += b;
953 }
954
955 if (chksum != NODE_ADDR_CKSUM)
956 goto out2;
957
958 b = inb(ioaddr + BDID);
959 if(b != BRD_ID_8115T)
960 {
961 printk(KERN_ERR "%s: The adapter found is not supported\n", dev->name);
962 goto out2;
963 }
964
965 /* Check for 8115T Board ID */
966 r2 = 0;
967 for(r = 0; r < 8; r++)
968 {
969 r1 = inb(ioaddr + 0x8 + r);
970 r2 += r1;
971 }
972
973 /* value of RegF adds up the sum to 0xFF */
974 if((r2 != 0xFF) && (r2 != 0xEE))
975 goto out2;
976
977 /* Get adapter ID */
978 tp->board_id = smctr_get_boardid(dev, 0);
979 switch(tp->board_id & 0xffff)
980 {
981 case WD8115TA:
982 smctr_model = "8115T/A";
983 break;
984
985 case WD8115T:
986 if(tp->extra_info & CHIP_REV_MASK)
987 smctr_model = "8115T rev XE";
988 else
989 smctr_model = "8115T rev XD";
990 break;
991
992 default:
993 smctr_model = "Unknown";
994 break;
995 }
996
997 /* Store BIC type. */
998 tp->bic_type = BIC_584_CHIP;
999 tp->nic_type = NIC_825_CHIP;
1000
1001 /* Copy Ram Size */
1002 tp->ram_usable = CNFG_SIZE_16KB;
1003 tp->ram_size = CNFG_SIZE_64KB;
1004
1005 /* Get 58x Ram Base */
1006 r1 = inb(ioaddr);
1007 r1 &= 0x3F;
1008
1009 r2 = inb(ioaddr + CNFG_LAAR_584);
1010 r2 &= CNFG_LAAR_MASK;
1011 r2 <<= 3;
1012 r2 |= ((r1 & 0x38) >> 3);
1013
1014 tp->ram_base = ((__u32)r2 << 16) + (((__u32)(r1 & 0x7)) << 13);
1015
1016 /* Get 584 Irq */
1017 r1 = 0;
1018 r1 = inb(ioaddr + CNFG_ICR_583);
1019 r1 &= CNFG_ICR_IR2_584;
1020
1021 r2 = inb(ioaddr + CNFG_IRR_583);
1022 r2 &= CNFG_IRR_IRQS; /* 0x60 */
1023 r2 >>= 5;
1024
1025 switch(r2)
1026 {
1027 case 0:
1028 if(r1 == 0)
1029 dev->irq = 2;
1030 else
1031 dev->irq = 10;
1032 break;
1033
1034 case 1:
1035 if(r1 == 0)
1036 dev->irq = 3;
1037 else
1038 dev->irq = 11;
1039 break;
1040
1041 case 2:
1042 if(r1 == 0)
1043 {
1044 if(tp->extra_info & ALTERNATE_IRQ_BIT)
1045 dev->irq = 5;
1046 else
1047 dev->irq = 4;
1048 }
1049 else
1050 dev->irq = 15;
1051 break;
1052
1053 case 3:
1054 if(r1 == 0)
1055 dev->irq = 7;
1056 else
1057 dev->irq = 4;
1058 break;
1059
1060 default:
1061 printk(KERN_ERR "%s: No IRQ found aborting\n", dev->name);
1062 goto out2;
1063 }
1064
1065 if (request_irq(dev->irq, smctr_interrupt, SA_SHIRQ, smctr_name, dev))
1066 goto out2;
1067
1068 /* Get 58x Rom Base */
1069 r1 = inb(ioaddr + CNFG_BIO_583);
1070 r1 &= 0x3E;
1071 r1 |= 0x40;
1072
1073 tp->rom_base = (__u32)r1 << 13;
1074
1075 /* Get 58x Rom Size */
1076 r1 = inb(ioaddr + CNFG_BIO_583);
1077 r1 &= 0xC0;
1078 if(r1 == 0)
1079 tp->rom_size = ROM_DISABLE;
1080 else
1081 {
1082 r1 >>= 6;
1083 tp->rom_size = (__u16)CNFG_SIZE_8KB << r1;
1084 }
1085
1086 /* Get 58x Boot Status */
1087 r1 = inb(ioaddr + CNFG_GP2);
1088
1089 tp->mode_bits &= (~BOOT_STATUS_MASK);
1090
1091 if(r1 & CNFG_GP2_BOOT_NIBBLE)
1092 tp->mode_bits |= BOOT_TYPE_1;
1093
1094 /* Get 58x Zero Wait State */
1095 tp->mode_bits &= (~ZERO_WAIT_STATE_MASK);
1096
1097 r1 = inb(ioaddr + CNFG_IRR_583);
1098
1099 if(r1 & CNFG_IRR_ZWS)
1100 tp->mode_bits |= ZERO_WAIT_STATE_8_BIT;
1101
1102 if(tp->board_id & BOARD_16BIT)
1103 {
1104 r1 = inb(ioaddr + CNFG_LAAR_584);
1105
1106 if(r1 & CNFG_LAAR_ZWS)
1107 tp->mode_bits |= ZERO_WAIT_STATE_16_BIT;
1108 }
1109
1110 /* Get 584 Media Menu */
1111 tp->media_menu = 14;
1112 r1 = inb(ioaddr + CNFG_IRR_583);
1113
1114 tp->mode_bits &= 0xf8ff; /* (~CNFG_INTERFACE_TYPE_MASK) */
1115 if((tp->board_id & TOKEN_MEDIA) == TOKEN_MEDIA)
1116 {
1117 /* Get Advanced Features */
1118 if(((r1 & 0x6) >> 1) == 0x3)
1119 tp->media_type |= MEDIA_UTP_16;
1120 else
1121 {
1122 if(((r1 & 0x6) >> 1) == 0x2)
1123 tp->media_type |= MEDIA_STP_16;
1124 else
1125 {
1126 if(((r1 & 0x6) >> 1) == 0x1)
1127 tp->media_type |= MEDIA_UTP_4;
1128
1129 else
1130 tp->media_type |= MEDIA_STP_4;
1131 }
1132 }
1133
1134 r1 = inb(ioaddr + CNFG_GP2);
1135 if(!(r1 & 0x2) ) /* GP2_ETRD */
1136 tp->mode_bits |= EARLY_TOKEN_REL;
1137
1138 /* see if the chip is corrupted
1139 if(smctr_read_584_chksum(ioaddr))
1140 {
1141 printk(KERN_ERR "%s: EEPROM Checksum Failure\n", dev->name);
1142 free_irq(dev->irq, dev);
1143 goto out2;
1144 }
1145 */
1146 }
1147
1148 return (0);
1149
1150out2:
1151 release_region(ioaddr, SMCTR_IO_EXTENT);
1152out:
1153 return err;
1154}
1155
1156static int __init smctr_get_boardid(struct net_device *dev, int mca)
1157{
1158 struct net_local *tp = netdev_priv(dev);
1159 int ioaddr = dev->base_addr;
1160 __u8 r, r1, IdByte;
1161 __u16 BoardIdMask;
1162
1163 tp->board_id = BoardIdMask = 0;
1164
1165 if(mca)
1166 {
1167 BoardIdMask |= (MICROCHANNEL+INTERFACE_CHIP+TOKEN_MEDIA+PAGED_RAM+BOARD_16BIT);
1168 tp->extra_info |= (INTERFACE_594_CHIP+RAM_SIZE_64K+NIC_825_BIT+ALTERNATE_IRQ_BIT+SLOT_16BIT);
1169 }
1170 else
1171 {
1172 BoardIdMask|=(INTERFACE_CHIP+TOKEN_MEDIA+PAGED_RAM+BOARD_16BIT);
1173 tp->extra_info |= (INTERFACE_584_CHIP + RAM_SIZE_64K
1174 + NIC_825_BIT + ALTERNATE_IRQ_BIT);
1175 }
1176
1177 if(!mca)
1178 {
1179 r = inb(ioaddr + BID_REG_1);
1180 r &= 0x0c;
1181 outb(r, ioaddr + BID_REG_1);
1182 r = inb(ioaddr + BID_REG_1);
1183
1184 if(r & BID_SIXTEEN_BIT_BIT)
1185 {
1186 tp->extra_info |= SLOT_16BIT;
1187 tp->adapter_bus = BUS_ISA16_TYPE;
1188 }
1189 else
1190 tp->adapter_bus = BUS_ISA8_TYPE;
1191 }
1192 else
1193 tp->adapter_bus = BUS_MCA_TYPE;
1194
1195 /* Get Board Id Byte */
1196 IdByte = inb(ioaddr + BID_BOARD_ID_BYTE);
1197
1198 /* if Major version > 1.0 then
1199 * return;
1200 */
1201 if(IdByte & 0xF8)
1202 return (-1);
1203
1204 r1 = inb(ioaddr + BID_REG_1);
1205 r1 &= BID_ICR_MASK;
1206 r1 |= BID_OTHER_BIT;
1207
1208 outb(r1, ioaddr + BID_REG_1);
1209 r1 = inb(ioaddr + BID_REG_3);
1210
1211 r1 &= BID_EAR_MASK;
1212 r1 |= BID_ENGR_PAGE;
1213
1214 outb(r1, ioaddr + BID_REG_3);
1215 r1 = inb(ioaddr + BID_REG_1);
1216 r1 &= BID_ICR_MASK;
1217 r1 |= (BID_RLA | BID_OTHER_BIT);
1218
1219 outb(r1, ioaddr + BID_REG_1);
1220
1221 r1 = inb(ioaddr + BID_REG_1);
1222 while(r1 & BID_RECALL_DONE_MASK)
1223 r1 = inb(ioaddr + BID_REG_1);
1224
1225 r = inb(ioaddr + BID_LAR_0 + BID_REG_6);
1226
1227 /* clear chip rev bits */
1228 tp->extra_info &= ~CHIP_REV_MASK;
1229 tp->extra_info |= ((r & BID_EEPROM_CHIP_REV_MASK) << 6);
1230
1231 r1 = inb(ioaddr + BID_REG_1);
1232 r1 &= BID_ICR_MASK;
1233 r1 |= BID_OTHER_BIT;
1234
1235 outb(r1, ioaddr + BID_REG_1);
1236 r1 = inb(ioaddr + BID_REG_3);
1237
1238 r1 &= BID_EAR_MASK;
1239 r1 |= BID_EA6;
1240
1241 outb(r1, ioaddr + BID_REG_3);
1242 r1 = inb(ioaddr + BID_REG_1);
1243
1244 r1 &= BID_ICR_MASK;
1245 r1 |= BID_RLA;
1246
1247 outb(r1, ioaddr + BID_REG_1);
1248 r1 = inb(ioaddr + BID_REG_1);
1249
1250 while(r1 & BID_RECALL_DONE_MASK)
1251 r1 = inb(ioaddr + BID_REG_1);
1252
1253 return (BoardIdMask);
1254}
1255
1256static int smctr_get_group_address(struct net_device *dev)
1257{
1258 smctr_issue_read_word_cmd(dev, RW_INDIVIDUAL_GROUP_ADDR);
1259
1260 return(smctr_wait_cmd(dev));
1261}
1262
1263static int smctr_get_functional_address(struct net_device *dev)
1264{
1265 smctr_issue_read_word_cmd(dev, RW_FUNCTIONAL_ADDR);
1266
1267 return(smctr_wait_cmd(dev));
1268}
1269
1270/* Calculate number of Non-MAC receive BDB's and data buffers.
1271 * This function must simulate allocateing shared memory exactly
1272 * as the allocate_shared_memory function above.
1273 */
1274static unsigned int smctr_get_num_rx_bdbs(struct net_device *dev)
1275{
1276 struct net_local *tp = netdev_priv(dev);
1277 unsigned int mem_used = 0;
1278
1279 /* Allocate System Control Blocks. */
1280 mem_used += sizeof(SCGBlock);
1281
1282 mem_used += TO_PARAGRAPH_BOUNDRY(mem_used);
1283 mem_used += sizeof(SCLBlock);
1284
1285 mem_used += TO_PARAGRAPH_BOUNDRY(mem_used);
1286 mem_used += sizeof(ACBlock) * tp->num_acbs;
1287
1288 mem_used += TO_PARAGRAPH_BOUNDRY(mem_used);
1289 mem_used += sizeof(ISBlock);
1290
1291 mem_used += TO_PARAGRAPH_BOUNDRY(mem_used);
1292 mem_used += MISC_DATA_SIZE;
1293
1294 /* Allocate transmit FCB's. */
1295 mem_used += TO_PARAGRAPH_BOUNDRY(mem_used);
1296
1297 mem_used += sizeof(FCBlock) * tp->num_tx_fcbs[MAC_QUEUE];
1298 mem_used += sizeof(FCBlock) * tp->num_tx_fcbs[NON_MAC_QUEUE];
1299 mem_used += sizeof(FCBlock) * tp->num_tx_fcbs[BUG_QUEUE];
1300
1301 /* Allocate transmit BDBs. */
1302 mem_used += sizeof(BDBlock) * tp->num_tx_bdbs[MAC_QUEUE];
1303 mem_used += sizeof(BDBlock) * tp->num_tx_bdbs[NON_MAC_QUEUE];
1304 mem_used += sizeof(BDBlock) * tp->num_tx_bdbs[BUG_QUEUE];
1305
1306 /* Allocate receive FCBs. */
1307 mem_used += sizeof(FCBlock) * tp->num_rx_fcbs[MAC_QUEUE];
1308 mem_used += sizeof(FCBlock) * tp->num_rx_fcbs[NON_MAC_QUEUE];
1309
1310 /* Allocate receive BDBs. */
1311 mem_used += sizeof(BDBlock) * tp->num_rx_bdbs[MAC_QUEUE];
1312
1313 /* Allocate MAC transmit buffers.
1314 * MAC transmit buffers don't have to be on an ODD Boundry.
1315 */
1316 mem_used += tp->tx_buff_size[MAC_QUEUE];
1317
1318 /* Allocate BUG transmit buffers. */
1319 mem_used += tp->tx_buff_size[BUG_QUEUE];
1320
1321 /* Allocate MAC receive data buffers.
1322 * MAC receive buffers don't have to be on a 256 byte boundary.
1323 */
1324 mem_used += RX_DATA_BUFFER_SIZE * tp->num_rx_bdbs[MAC_QUEUE];
1325
1326 /* Allocate Non-MAC transmit buffers.
1327 * For maximum Netware performance, put Tx Buffers on
1328 * ODD Boundry,and then restore malloc to Even Boundrys.
1329 */
1330 mem_used += 1L;
1331 mem_used += tp->tx_buff_size[NON_MAC_QUEUE];
1332 mem_used += 1L;
1333
1334 /* CALCULATE NUMBER OF NON-MAC RX BDB'S
1335 * AND NON-MAC RX DATA BUFFERS
1336 *
1337 * Make sure the mem_used offset at this point is the
1338 * same as in allocate_shared memory or the following
1339 * boundary adjustment will be incorrect (i.e. not allocating
1340 * the non-mac receive buffers above cannot change the 256
1341 * byte offset).
1342 *
1343 * Since this cannot be guaranteed, adding the full 256 bytes
1344 * to the amount of shared memory used at this point will guaranteed
1345 * that the rx data buffers do not overflow shared memory.
1346 */
1347 mem_used += 0x100;
1348
1349 return((0xffff - mem_used) / (RX_DATA_BUFFER_SIZE + sizeof(BDBlock)));
1350}
1351
1352static int smctr_get_physical_drop_number(struct net_device *dev)
1353{
1354 smctr_issue_read_word_cmd(dev, RW_PHYSICAL_DROP_NUMBER);
1355
1356 return(smctr_wait_cmd(dev));
1357}
1358
1359static __u8 * smctr_get_rx_pointer(struct net_device *dev, short queue)
1360{
1361 struct net_local *tp = netdev_priv(dev);
1362 BDBlock *bdb;
1363
1364 bdb = (BDBlock *)((__u32)tp->ram_access
1365 + (__u32)(tp->rx_fcb_curr[queue]->trc_bdb_ptr));
1366
1367 tp->rx_fcb_curr[queue]->bdb_ptr = bdb;
1368
1369 return ((__u8 *)bdb->data_block_ptr);
1370}
1371
1372static int smctr_get_station_id(struct net_device *dev)
1373{
1374 smctr_issue_read_word_cmd(dev, RW_INDIVIDUAL_MAC_ADDRESS);
1375
1376 return(smctr_wait_cmd(dev));
1377}
1378
1379/*
1380 * Get the current statistics. This may be called with the card open
1381 * or closed.
1382 */
1383static struct net_device_stats *smctr_get_stats(struct net_device *dev)
1384{
1385 struct net_local *tp = netdev_priv(dev);
1386
1387 return ((struct net_device_stats *)&tp->MacStat);
1388}
1389
1390static FCBlock *smctr_get_tx_fcb(struct net_device *dev, __u16 queue,
1391 __u16 bytes_count)
1392{
1393 struct net_local *tp = netdev_priv(dev);
1394 FCBlock *pFCB;
1395 BDBlock *pbdb;
1396 unsigned short alloc_size;
1397 unsigned short *temp;
1398
1399 if(smctr_debug > 20)
1400 printk(KERN_DEBUG "smctr_get_tx_fcb\n");
1401
1402 /* check if there is enough FCB blocks */
1403 if(tp->num_tx_fcbs_used[queue] >= tp->num_tx_fcbs[queue])
1404 return ((FCBlock *)(-1L));
1405
1406 /* round off the input pkt size to the nearest even number */
1407 alloc_size = (bytes_count + 1) & 0xfffe;
1408
1409 /* check if enough mem */
1410 if((tp->tx_buff_used[queue] + alloc_size) > tp->tx_buff_size[queue])
1411 return ((FCBlock *)(-1L));
1412
1413 /* check if past the end ;
1414 * if exactly enough mem to end of ring, alloc from front.
1415 * this avoids update of curr when curr = end
1416 */
1417 if(((unsigned long)(tp->tx_buff_curr[queue]) + alloc_size)
1418 >= (unsigned long)(tp->tx_buff_end[queue]))
1419 {
1420 /* check if enough memory from ring head */
1421 alloc_size = alloc_size +
1422 (__u16)((__u32)tp->tx_buff_end[queue]
1423 - (__u32)tp->tx_buff_curr[queue]);
1424
1425 if((tp->tx_buff_used[queue] + alloc_size)
1426 > tp->tx_buff_size[queue])
1427 {
1428 return ((FCBlock *)(-1L));
1429 }
1430
1431 /* ring wrap */
1432 tp->tx_buff_curr[queue] = tp->tx_buff_head[queue];
1433 }
1434
1435 tp->tx_buff_used[queue] += alloc_size;
1436 tp->num_tx_fcbs_used[queue]++;
1437 tp->tx_fcb_curr[queue]->frame_length = bytes_count;
1438 tp->tx_fcb_curr[queue]->memory_alloc = alloc_size;
1439 temp = tp->tx_buff_curr[queue];
1440 tp->tx_buff_curr[queue]
1441 = (__u16 *)((__u32)temp + (__u32)((bytes_count + 1) & 0xfffe));
1442
1443 pbdb = tp->tx_fcb_curr[queue]->bdb_ptr;
1444 pbdb->buffer_length = bytes_count;
1445 pbdb->data_block_ptr = temp;
1446 pbdb->trc_data_block_ptr = TRC_POINTER(temp);
1447
1448 pFCB = tp->tx_fcb_curr[queue];
1449 tp->tx_fcb_curr[queue] = tp->tx_fcb_curr[queue]->next_ptr;
1450
1451 return (pFCB);
1452}
1453
1454static int smctr_get_upstream_neighbor_addr(struct net_device *dev)
1455{
1456 smctr_issue_read_word_cmd(dev, RW_UPSTREAM_NEIGHBOR_ADDRESS);
1457
1458 return(smctr_wait_cmd(dev));
1459}
1460
1461static int smctr_hardware_send_packet(struct net_device *dev,
1462 struct net_local *tp)
1463{
1464 struct tr_statistics *tstat = &tp->MacStat;
1465 struct sk_buff *skb;
1466 FCBlock *fcb;
1467
1468 if(smctr_debug > 10)
1469 printk(KERN_DEBUG"%s: smctr_hardware_send_packet\n", dev->name);
1470
1471 if(tp->status != OPEN)
1472 return (-1);
1473
1474 if(tp->monitor_state_ready != 1)
1475 return (-1);
1476
1477 for(;;)
1478 {
1479 /* Send first buffer from queue */
1480 skb = skb_dequeue(&tp->SendSkbQueue);
1481 if(skb == NULL)
1482 return (-1);
1483
1484 tp->QueueSkb++;
1485
1486 if(skb->len < SMC_HEADER_SIZE || skb->len > tp->max_packet_size) return (-1);
1487
1488 smctr_enable_16bit(dev);
1489 smctr_set_page(dev, (__u8 *)tp->ram_access);
1490
1491 if((fcb = smctr_get_tx_fcb(dev, NON_MAC_QUEUE, skb->len))
1492 == (FCBlock *)(-1L))
1493 {
1494 smctr_disable_16bit(dev);
1495 return (-1);
1496 }
1497
1498 smctr_tx_move_frame(dev, skb,
1499 (__u8 *)fcb->bdb_ptr->data_block_ptr, skb->len);
1500
1501 smctr_set_page(dev, (__u8 *)fcb);
1502
1503 smctr_trc_send_packet(dev, fcb, NON_MAC_QUEUE);
1504 dev_kfree_skb(skb);
1505
1506 tstat->tx_packets++;
1507
1508 smctr_disable_16bit(dev);
1509 }
1510
1511 return (0);
1512}
1513
1514static int smctr_init_acbs(struct net_device *dev)
1515{
1516 struct net_local *tp = netdev_priv(dev);
1517 unsigned int i;
1518 ACBlock *acb;
1519
1520 if(smctr_debug > 10)
1521 printk(KERN_DEBUG "%s: smctr_init_acbs\n", dev->name);
1522
1523 acb = tp->acb_head;
1524 acb->cmd_done_status = (ACB_COMMAND_DONE | ACB_COMMAND_SUCCESSFUL);
1525 acb->cmd_info = ACB_CHAIN_END;
1526 acb->cmd = 0;
1527 acb->subcmd = 0;
1528 acb->data_offset_lo = 0;
1529 acb->data_offset_hi = 0;
1530 acb->next_ptr
1531 = (ACBlock *)(((char *)acb) + sizeof(ACBlock));
1532 acb->trc_next_ptr = TRC_POINTER(acb->next_ptr);
1533
1534 for(i = 1; i < tp->num_acbs; i++)
1535 {
1536 acb = acb->next_ptr;
1537 acb->cmd_done_status
1538 = (ACB_COMMAND_DONE | ACB_COMMAND_SUCCESSFUL);
1539 acb->cmd_info = ACB_CHAIN_END;
1540 acb->cmd = 0;
1541 acb->subcmd = 0;
1542 acb->data_offset_lo = 0;
1543 acb->data_offset_hi = 0;
1544 acb->next_ptr
1545 = (ACBlock *)(((char *)acb) + sizeof(ACBlock));
1546 acb->trc_next_ptr = TRC_POINTER(acb->next_ptr);
1547 }
1548
1549 acb->next_ptr = tp->acb_head;
1550 acb->trc_next_ptr = TRC_POINTER(tp->acb_head);
1551 tp->acb_next = tp->acb_head->next_ptr;
1552 tp->acb_curr = tp->acb_head->next_ptr;
1553 tp->num_acbs_used = 0;
1554
1555 return (0);
1556}
1557
1558static int smctr_init_adapter(struct net_device *dev)
1559{
1560 struct net_local *tp = netdev_priv(dev);
1561 int err;
1562
1563 if(smctr_debug > 10)
1564 printk(KERN_DEBUG "%s: smctr_init_adapter\n", dev->name);
1565
1566 tp->status = CLOSED;
1567 tp->page_offset_mask = (tp->ram_usable * 1024) - 1;
1568 skb_queue_head_init(&tp->SendSkbQueue);
1569 tp->QueueSkb = MAX_TX_QUEUE;
1570
1571 if(!(tp->group_address_0 & 0x0080))
1572 tp->group_address_0 |= 0x00C0;
1573
1574 if(!(tp->functional_address_0 & 0x00C0))
1575 tp->functional_address_0 |= 0x00C0;
1576
1577 tp->functional_address[0] &= 0xFF7F;
1578
1579 if(tp->authorized_function_classes == 0)
1580 tp->authorized_function_classes = 0x7FFF;
1581
1582 if(tp->authorized_access_priority == 0)
1583 tp->authorized_access_priority = 0x06;
1584
1585 smctr_disable_bic_int(dev);
1586 smctr_set_trc_reset(dev->base_addr);
1587
1588 smctr_enable_16bit(dev);
1589 smctr_set_page(dev, (__u8 *)tp->ram_access);
1590
1591 if(smctr_checksum_firmware(dev))
1592 {
1593 printk(KERN_ERR "%s: Previously loaded firmware is missing\n",dev->name); return (-ENOENT);
1594 }
1595
1596 if((err = smctr_ram_memory_test(dev)))
1597 {
1598 printk(KERN_ERR "%s: RAM memory test failed.\n", dev->name);
1599 return (-EIO);
1600 }
1601
1602 smctr_set_rx_look_ahead(dev);
1603 smctr_load_node_addr(dev);
1604
1605 /* Initialize adapter for Internal Self Test. */
1606 smctr_reset_adapter(dev);
1607 if((err = smctr_init_card_real(dev)))
1608 {
1609 printk(KERN_ERR "%s: Initialization of card failed (%d)\n",
1610 dev->name, err);
1611 return (-EINVAL);
1612 }
1613
1614 /* This routine clobbers the TRC's internal registers. */
1615 if((err = smctr_internal_self_test(dev)))
1616 {
1617 printk(KERN_ERR "%s: Card failed internal self test (%d)\n",
1618 dev->name, err);
1619 return (-EINVAL);
1620 }
1621
1622 /* Re-Initialize adapter's internal registers */
1623 smctr_reset_adapter(dev);
1624 if((err = smctr_init_card_real(dev)))
1625 {
1626 printk(KERN_ERR "%s: Initialization of card failed (%d)\n",
1627 dev->name, err);
1628 return (-EINVAL);
1629 }
1630
1631 smctr_enable_bic_int(dev);
1632
1633 if((err = smctr_issue_enable_int_cmd(dev, TRC_INTERRUPT_ENABLE_MASK)))
1634 return (err);
1635
1636 smctr_disable_16bit(dev);
1637
1638 return (0);
1639}
1640
1641static int smctr_init_card_real(struct net_device *dev)
1642{
1643 struct net_local *tp = netdev_priv(dev);
1644 int err = 0;
1645
1646 if(smctr_debug > 10)
1647 printk(KERN_DEBUG "%s: smctr_init_card_real\n", dev->name);
1648
1649 tp->sh_mem_used = 0;
1650 tp->num_acbs = NUM_OF_ACBS;
1651
1652 /* Range Check Max Packet Size */
1653 if(tp->max_packet_size < 256)
1654 tp->max_packet_size = 256;
1655 else
1656 {
1657 if(tp->max_packet_size > NON_MAC_TX_BUFFER_MEMORY)
1658 tp->max_packet_size = NON_MAC_TX_BUFFER_MEMORY;
1659 }
1660
1661 tp->num_of_tx_buffs = (NON_MAC_TX_BUFFER_MEMORY
1662 / tp->max_packet_size) - 1;
1663
1664 if(tp->num_of_tx_buffs > NUM_NON_MAC_TX_FCBS)
1665 tp->num_of_tx_buffs = NUM_NON_MAC_TX_FCBS;
1666 else
1667 {
1668 if(tp->num_of_tx_buffs == 0)
1669 tp->num_of_tx_buffs = 1;
1670 }
1671
1672 /* Tx queue constants */
1673 tp->num_tx_fcbs [BUG_QUEUE] = NUM_BUG_TX_FCBS;
1674 tp->num_tx_bdbs [BUG_QUEUE] = NUM_BUG_TX_BDBS;
1675 tp->tx_buff_size [BUG_QUEUE] = BUG_TX_BUFFER_MEMORY;
1676 tp->tx_buff_used [BUG_QUEUE] = 0;
1677 tp->tx_queue_status [BUG_QUEUE] = NOT_TRANSMITING;
1678
1679 tp->num_tx_fcbs [MAC_QUEUE] = NUM_MAC_TX_FCBS;
1680 tp->num_tx_bdbs [MAC_QUEUE] = NUM_MAC_TX_BDBS;
1681 tp->tx_buff_size [MAC_QUEUE] = MAC_TX_BUFFER_MEMORY;
1682 tp->tx_buff_used [MAC_QUEUE] = 0;
1683 tp->tx_queue_status [MAC_QUEUE] = NOT_TRANSMITING;
1684
1685 tp->num_tx_fcbs [NON_MAC_QUEUE] = NUM_NON_MAC_TX_FCBS;
1686 tp->num_tx_bdbs [NON_MAC_QUEUE] = NUM_NON_MAC_TX_BDBS;
1687 tp->tx_buff_size [NON_MAC_QUEUE] = NON_MAC_TX_BUFFER_MEMORY;
1688 tp->tx_buff_used [NON_MAC_QUEUE] = 0;
1689 tp->tx_queue_status [NON_MAC_QUEUE] = NOT_TRANSMITING;
1690
1691 /* Receive Queue Constants */
1692 tp->num_rx_fcbs[MAC_QUEUE] = NUM_MAC_RX_FCBS;
1693 tp->num_rx_bdbs[MAC_QUEUE] = NUM_MAC_RX_BDBS;
1694
1695 if(tp->extra_info & CHIP_REV_MASK)
1696 tp->num_rx_fcbs[NON_MAC_QUEUE] = 78; /* 825 Rev. XE */
1697 else
1698 tp->num_rx_fcbs[NON_MAC_QUEUE] = 7; /* 825 Rev. XD */
1699
1700 tp->num_rx_bdbs[NON_MAC_QUEUE] = smctr_get_num_rx_bdbs(dev);
1701
1702 smctr_alloc_shared_memory(dev);
1703 smctr_init_shared_memory(dev);
1704
1705 if((err = smctr_issue_init_timers_cmd(dev)))
1706 return (err);
1707
1708 if((err = smctr_issue_init_txrx_cmd(dev)))
1709 {
1710 printk(KERN_ERR "%s: Hardware failure\n", dev->name);
1711 return (err);
1712 }
1713
1714 return (0);
1715}
1716
1717static int smctr_init_rx_bdbs(struct net_device *dev)
1718{
1719 struct net_local *tp = netdev_priv(dev);
1720 unsigned int i, j;
1721 BDBlock *bdb;
1722 __u16 *buf;
1723
1724 if(smctr_debug > 10)
1725 printk(KERN_DEBUG "%s: smctr_init_rx_bdbs\n", dev->name);
1726
1727 for(i = 0; i < NUM_RX_QS_USED; i++)
1728 {
1729 bdb = tp->rx_bdb_head[i];
1730 buf = tp->rx_buff_head[i];
1731 bdb->info = (BDB_CHAIN_END | BDB_NO_WARNING);
1732 bdb->buffer_length = RX_DATA_BUFFER_SIZE;
1733 bdb->next_ptr = (BDBlock *)(((char *)bdb) + sizeof(BDBlock));
1734 bdb->data_block_ptr = buf;
1735 bdb->trc_next_ptr = TRC_POINTER(bdb->next_ptr);
1736
1737 if(i == NON_MAC_QUEUE)
1738 bdb->trc_data_block_ptr = RX_BUFF_TRC_POINTER(buf);
1739 else
1740 bdb->trc_data_block_ptr = TRC_POINTER(buf);
1741
1742 for(j = 1; j < tp->num_rx_bdbs[i]; j++)
1743 {
1744 bdb->next_ptr->back_ptr = bdb;
1745 bdb = bdb->next_ptr;
1746 buf = (__u16 *)((char *)buf + RX_DATA_BUFFER_SIZE);
1747 bdb->info = (BDB_NOT_CHAIN_END | BDB_NO_WARNING);
1748 bdb->buffer_length = RX_DATA_BUFFER_SIZE;
1749 bdb->next_ptr = (BDBlock *)(((char *)bdb) + sizeof(BDBlock));
1750 bdb->data_block_ptr = buf;
1751 bdb->trc_next_ptr = TRC_POINTER(bdb->next_ptr);
1752
1753 if(i == NON_MAC_QUEUE)
1754 bdb->trc_data_block_ptr = RX_BUFF_TRC_POINTER(buf);
1755 else
1756 bdb->trc_data_block_ptr = TRC_POINTER(buf);
1757 }
1758
1759 bdb->next_ptr = tp->rx_bdb_head[i];
1760 bdb->trc_next_ptr = TRC_POINTER(tp->rx_bdb_head[i]);
1761
1762 tp->rx_bdb_head[i]->back_ptr = bdb;
1763 tp->rx_bdb_curr[i] = tp->rx_bdb_head[i]->next_ptr;
1764 }
1765
1766 return (0);
1767}
1768
1769static int smctr_init_rx_fcbs(struct net_device *dev)
1770{
1771 struct net_local *tp = netdev_priv(dev);
1772 unsigned int i, j;
1773 FCBlock *fcb;
1774
1775 for(i = 0; i < NUM_RX_QS_USED; i++)
1776 {
1777 fcb = tp->rx_fcb_head[i];
1778 fcb->frame_status = 0;
1779 fcb->frame_length = 0;
1780 fcb->info = FCB_CHAIN_END;
1781 fcb->next_ptr = (FCBlock *)(((char*)fcb) + sizeof(FCBlock));
1782 if(i == NON_MAC_QUEUE)
1783 fcb->trc_next_ptr = RX_FCB_TRC_POINTER(fcb->next_ptr);
1784 else
1785 fcb->trc_next_ptr = TRC_POINTER(fcb->next_ptr);
1786
1787 for(j = 1; j < tp->num_rx_fcbs[i]; j++)
1788 {
1789 fcb->next_ptr->back_ptr = fcb;
1790 fcb = fcb->next_ptr;
1791 fcb->frame_status = 0;
1792 fcb->frame_length = 0;
1793 fcb->info = FCB_WARNING;
1794 fcb->next_ptr
1795 = (FCBlock *)(((char *)fcb) + sizeof(FCBlock));
1796
1797 if(i == NON_MAC_QUEUE)
1798 fcb->trc_next_ptr
1799 = RX_FCB_TRC_POINTER(fcb->next_ptr);
1800 else
1801 fcb->trc_next_ptr
1802 = TRC_POINTER(fcb->next_ptr);
1803 }
1804
1805 fcb->next_ptr = tp->rx_fcb_head[i];
1806
1807 if(i == NON_MAC_QUEUE)
1808 fcb->trc_next_ptr = RX_FCB_TRC_POINTER(fcb->next_ptr);
1809 else
1810 fcb->trc_next_ptr = TRC_POINTER(fcb->next_ptr);
1811
1812 tp->rx_fcb_head[i]->back_ptr = fcb;
1813 tp->rx_fcb_curr[i] = tp->rx_fcb_head[i]->next_ptr;
1814 }
1815
1816 return(0);
1817}
1818
1819static int smctr_init_shared_memory(struct net_device *dev)
1820{
1821 struct net_local *tp = netdev_priv(dev);
1822 unsigned int i;
1823 __u32 *iscpb;
1824
1825 if(smctr_debug > 10)
1826 printk(KERN_DEBUG "%s: smctr_init_shared_memory\n", dev->name);
1827
1828 smctr_set_page(dev, (__u8 *)(unsigned int)tp->iscpb_ptr);
1829
1830 /* Initialize Initial System Configuration Point. (ISCP) */
1831 iscpb = (__u32 *)PAGE_POINTER(&tp->iscpb_ptr->trc_scgb_ptr);
1832 *iscpb = (__u32)(SWAP_WORDS(TRC_POINTER(tp->scgb_ptr)));
1833
1834 smctr_set_page(dev, (__u8 *)tp->ram_access);
1835
1836 /* Initialize System Configuration Pointers. (SCP) */
1837 tp->scgb_ptr->config = (SCGB_ADDRESS_POINTER_FORMAT
1838 | SCGB_MULTI_WORD_CONTROL | SCGB_DATA_FORMAT
1839 | SCGB_BURST_LENGTH);
1840
1841 tp->scgb_ptr->trc_sclb_ptr = TRC_POINTER(tp->sclb_ptr);
1842 tp->scgb_ptr->trc_acb_ptr = TRC_POINTER(tp->acb_head);
1843 tp->scgb_ptr->trc_isb_ptr = TRC_POINTER(tp->isb_ptr);
1844 tp->scgb_ptr->isbsiz = (sizeof(ISBlock)) - 2;
1845
1846 /* Initialize System Control Block. (SCB) */
1847 tp->sclb_ptr->valid_command = SCLB_VALID | SCLB_CMD_NOP;
1848 tp->sclb_ptr->iack_code = 0;
1849 tp->sclb_ptr->resume_control = 0;
1850 tp->sclb_ptr->int_mask_control = 0;
1851 tp->sclb_ptr->int_mask_state = 0;
1852
1853 /* Initialize Interrupt Status Block. (ISB) */
1854 for(i = 0; i < NUM_OF_INTERRUPTS; i++)
1855 {
1856 tp->isb_ptr->IStatus[i].IType = 0xf0;
1857 tp->isb_ptr->IStatus[i].ISubtype = 0;
1858 }
1859
1860 tp->current_isb_index = 0;
1861
1862 /* Initialize Action Command Block. (ACB) */
1863 smctr_init_acbs(dev);
1864
1865 /* Initialize transmit FCB's and BDB's. */
1866 smctr_link_tx_fcbs_to_bdbs(dev);
1867 smctr_init_tx_bdbs(dev);
1868 smctr_init_tx_fcbs(dev);
1869
1870 /* Initialize receive FCB's and BDB's. */
1871 smctr_init_rx_bdbs(dev);
1872 smctr_init_rx_fcbs(dev);
1873
1874 return (0);
1875}
1876
1877static int smctr_init_tx_bdbs(struct net_device *dev)
1878{
1879 struct net_local *tp = netdev_priv(dev);
1880 unsigned int i, j;
1881 BDBlock *bdb;
1882
1883 for(i = 0; i < NUM_TX_QS_USED; i++)
1884 {
1885 bdb = tp->tx_bdb_head[i];
1886 bdb->info = (BDB_NOT_CHAIN_END | BDB_NO_WARNING);
1887 bdb->next_ptr = (BDBlock *)(((char *)bdb) + sizeof(BDBlock));
1888 bdb->trc_next_ptr = TRC_POINTER(bdb->next_ptr);
1889
1890 for(j = 1; j < tp->num_tx_bdbs[i]; j++)
1891 {
1892 bdb->next_ptr->back_ptr = bdb;
1893 bdb = bdb->next_ptr;
1894 bdb->info = (BDB_NOT_CHAIN_END | BDB_NO_WARNING);
1895 bdb->next_ptr
1896 = (BDBlock *)(((char *)bdb) + sizeof( BDBlock)); bdb->trc_next_ptr = TRC_POINTER(bdb->next_ptr);
1897 }
1898
1899 bdb->next_ptr = tp->tx_bdb_head[i];
1900 bdb->trc_next_ptr = TRC_POINTER(tp->tx_bdb_head[i]);
1901 tp->tx_bdb_head[i]->back_ptr = bdb;
1902 }
1903
1904 return (0);
1905}
1906
1907static int smctr_init_tx_fcbs(struct net_device *dev)
1908{
1909 struct net_local *tp = netdev_priv(dev);
1910 unsigned int i, j;
1911 FCBlock *fcb;
1912
1913 for(i = 0; i < NUM_TX_QS_USED; i++)
1914 {
1915 fcb = tp->tx_fcb_head[i];
1916 fcb->frame_status = 0;
1917 fcb->frame_length = 0;
1918 fcb->info = FCB_CHAIN_END;
1919 fcb->next_ptr = (FCBlock *)(((char *)fcb) + sizeof(FCBlock));
1920 fcb->trc_next_ptr = TRC_POINTER(fcb->next_ptr);
1921
1922 for(j = 1; j < tp->num_tx_fcbs[i]; j++)
1923 {
1924 fcb->next_ptr->back_ptr = fcb;
1925 fcb = fcb->next_ptr;
1926 fcb->frame_status = 0;
1927 fcb->frame_length = 0;
1928 fcb->info = FCB_CHAIN_END;
1929 fcb->next_ptr
1930 = (FCBlock *)(((char *)fcb) + sizeof(FCBlock));
1931 fcb->trc_next_ptr = TRC_POINTER(fcb->next_ptr);
1932 }
1933
1934 fcb->next_ptr = tp->tx_fcb_head[i];
1935 fcb->trc_next_ptr = TRC_POINTER(tp->tx_fcb_head[i]);
1936
1937 tp->tx_fcb_head[i]->back_ptr = fcb;
1938 tp->tx_fcb_end[i] = tp->tx_fcb_head[i]->next_ptr;
1939 tp->tx_fcb_curr[i] = tp->tx_fcb_head[i]->next_ptr;
1940 tp->num_tx_fcbs_used[i] = 0;
1941 }
1942
1943 return (0);
1944}
1945
1946static int smctr_internal_self_test(struct net_device *dev)
1947{
1948 struct net_local *tp = netdev_priv(dev);
1949 int err;
1950
1951 if((err = smctr_issue_test_internal_rom_cmd(dev)))
1952 return (err);
1953
1954 if((err = smctr_wait_cmd(dev)))
1955 return (err);
1956
1957 if(tp->acb_head->cmd_done_status & 0xff)
1958 return (-1);
1959
1960 if((err = smctr_issue_test_hic_cmd(dev)))
1961 return (err);
1962
1963 if((err = smctr_wait_cmd(dev)))
1964 return (err);
1965
1966 if(tp->acb_head->cmd_done_status & 0xff)
1967 return (-1);
1968
1969 if((err = smctr_issue_test_mac_reg_cmd(dev)))
1970 return (err);
1971
1972 if((err = smctr_wait_cmd(dev)))
1973 return (err);
1974
1975 if(tp->acb_head->cmd_done_status & 0xff)
1976 return (-1);
1977
1978 return (0);
1979}
1980
1981/*
1982 * The typical workload of the driver: Handle the network interface interrupts.
1983 */
1984static irqreturn_t smctr_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1985{
1986 struct net_device *dev = dev_id;
1987 struct net_local *tp;
1988 int ioaddr;
1989 __u16 interrupt_unmask_bits = 0, interrupt_ack_code = 0xff00;
1990 __u16 err1, err = NOT_MY_INTERRUPT;
1991 __u8 isb_type, isb_subtype;
1992 __u16 isb_index;
1993
1994 if(dev == NULL)
1995 {
1996 printk(KERN_CRIT "%s: irq %d for unknown device.\n", dev->name, irq);
1997 return IRQ_NONE;
1998 }
1999
2000 ioaddr = dev->base_addr;
2001 tp = netdev_priv(dev);
2002
2003
2004 if(tp->status == NOT_INITIALIZED)
2005 return IRQ_NONE;
2006
2007 spin_lock(&tp->lock);
2008
2009 smctr_disable_bic_int(dev);
2010 smctr_enable_16bit(dev);
2011
2012 smctr_clear_int(dev);
2013
2014 /* First read the LSB */
2015 while((tp->isb_ptr->IStatus[tp->current_isb_index].IType & 0xf0) == 0)
2016 {
2017 isb_index = tp->current_isb_index;
2018 isb_type = tp->isb_ptr->IStatus[isb_index].IType;
2019 isb_subtype = tp->isb_ptr->IStatus[isb_index].ISubtype;
2020
2021 (tp->current_isb_index)++;
2022 if(tp->current_isb_index == NUM_OF_INTERRUPTS)
2023 tp->current_isb_index = 0;
2024
2025 if(isb_type >= 0x10)
2026 {
2027 smctr_disable_16bit(dev);
2028 spin_unlock(&tp->lock);
2029 return IRQ_HANDLED;
2030 }
2031
2032 err = HARDWARE_FAILED;
2033 interrupt_ack_code = isb_index;
2034 tp->isb_ptr->IStatus[isb_index].IType |= 0xf0;
2035
2036 interrupt_unmask_bits |= (1 << (__u16)isb_type);
2037
2038 switch(isb_type)
2039 {
2040 case ISB_IMC_MAC_TYPE_3:
2041 smctr_disable_16bit(dev);
2042
2043 switch(isb_subtype)
2044 {
2045 case 0:
2046 tp->monitor_state = MS_MONITOR_FSM_INACTIVE;
2047 break;
2048
2049 case 1:
2050 tp->monitor_state = MS_REPEAT_BEACON_STATE;
2051 break;
2052
2053 case 2:
2054 tp->monitor_state = MS_REPEAT_CLAIM_TOKEN_STATE;
2055 break;
2056
2057 case 3:
2058 tp->monitor_state = MS_TRANSMIT_CLAIM_TOKEN_STATE; break;
2059
2060 case 4:
2061 tp->monitor_state = MS_STANDBY_MONITOR_STATE;
2062 break;
2063
2064 case 5:
2065 tp->monitor_state = MS_TRANSMIT_BEACON_STATE;
2066 break;
2067
2068 case 6:
2069 tp->monitor_state = MS_ACTIVE_MONITOR_STATE;
2070 break;
2071
2072 case 7:
2073 tp->monitor_state = MS_TRANSMIT_RING_PURGE_STATE;
2074 break;
2075
2076 case 8: /* diagnostic state */
2077 break;
2078
2079 case 9:
2080 tp->monitor_state = MS_BEACON_TEST_STATE;
2081 if(smctr_lobe_media_test(dev))
2082 {
2083 tp->ring_status_flags = RING_STATUS_CHANGED;
2084 tp->ring_status = AUTO_REMOVAL_ERROR;
2085 smctr_ring_status_chg(dev);
2086 smctr_bypass_state(dev);
2087 }
2088 else
2089 smctr_issue_insert_cmd(dev);
2090 break;
2091
2092 /* case 0x0a-0xff, illegal states */
2093 default:
2094 break;
2095 }
2096
2097 tp->ring_status_flags = MONITOR_STATE_CHANGED;
2098 err = smctr_ring_status_chg(dev);
2099
2100 smctr_enable_16bit(dev);
2101 break;
2102
2103 /* Type 0x02 - MAC Error Counters Interrupt
2104 * One or more MAC Error Counter is half full
2105 * MAC Error Counters
2106 * Lost_FR_Error_Counter
2107 * RCV_Congestion_Counter
2108 * FR_copied_Error_Counter
2109 * FREQ_Error_Counter
2110 * Token_Error_Counter
2111 * Line_Error_Counter
2112 * Internal_Error_Count
2113 */
2114 case ISB_IMC_MAC_ERROR_COUNTERS:
2115 /* Read 802.5 Error Counters */
2116 err = smctr_issue_read_ring_status_cmd(dev);
2117 break;
2118
2119 /* Type 0x04 - MAC Type 2 Interrupt
2120 * HOST needs to enqueue MAC Frame for transmission
2121 * SubType Bit 15 - RQ_INIT_PDU( Request Initialization) * Changed from RQ_INIT_PDU to
2122 * TRC_Status_Changed_Indicate
2123 */
2124 case ISB_IMC_MAC_TYPE_2:
2125 err = smctr_issue_read_ring_status_cmd(dev);
2126 break;
2127
2128
2129 /* Type 0x05 - TX Frame Interrupt (FI). */
2130 case ISB_IMC_TX_FRAME:
2131 /* BUG QUEUE for TRC stuck receive BUG */
2132 if(isb_subtype & TX_PENDING_PRIORITY_2)
2133 {
2134 if((err = smctr_tx_complete(dev, BUG_QUEUE)) != SUCCESS)
2135 break;
2136 }
2137
2138 /* NON-MAC frames only */
2139 if(isb_subtype & TX_PENDING_PRIORITY_1)
2140 {
2141 if((err = smctr_tx_complete(dev, NON_MAC_QUEUE)) != SUCCESS)
2142 break;
2143 }
2144
2145 /* MAC frames only */
2146 if(isb_subtype & TX_PENDING_PRIORITY_0)
2147 err = smctr_tx_complete(dev, MAC_QUEUE); break;
2148
2149 /* Type 0x06 - TX END OF QUEUE (FE) */
2150 case ISB_IMC_END_OF_TX_QUEUE:
2151 /* BUG queue */
2152 if(isb_subtype & TX_PENDING_PRIORITY_2)
2153 {
2154 /* ok to clear Receive FIFO overrun
2155 * imask send_BUG now completes.
2156 */
2157 interrupt_unmask_bits |= 0x800;
2158
2159 tp->tx_queue_status[BUG_QUEUE] = NOT_TRANSMITING;
2160 if((err = smctr_tx_complete(dev, BUG_QUEUE)) != SUCCESS)
2161 break;
2162 if((err = smctr_restart_tx_chain(dev, BUG_QUEUE)) != SUCCESS)
2163 break;
2164 }
2165
2166 /* NON-MAC queue only */
2167 if(isb_subtype & TX_PENDING_PRIORITY_1)
2168 {
2169 tp->tx_queue_status[NON_MAC_QUEUE] = NOT_TRANSMITING;
2170 if((err = smctr_tx_complete(dev, NON_MAC_QUEUE)) != SUCCESS)
2171 break;
2172 if((err = smctr_restart_tx_chain(dev, NON_MAC_QUEUE)) != SUCCESS)
2173 break;
2174 }
2175
2176 /* MAC queue only */
2177 if(isb_subtype & TX_PENDING_PRIORITY_0)
2178 {
2179 tp->tx_queue_status[MAC_QUEUE] = NOT_TRANSMITING;
2180 if((err = smctr_tx_complete(dev, MAC_QUEUE)) != SUCCESS)
2181 break;
2182
2183 err = smctr_restart_tx_chain(dev, MAC_QUEUE);
2184 }
2185 break;
2186
2187 /* Type 0x07 - NON-MAC RX Resource Interrupt
2188 * Subtype bit 12 - (BW) BDB warning
2189 * Subtype bit 13 - (FW) FCB warning
2190 * Subtype bit 14 - (BE) BDB End of chain
2191 * Subtype bit 15 - (FE) FCB End of chain
2192 */
2193 case ISB_IMC_NON_MAC_RX_RESOURCE:
2194 tp->rx_fifo_overrun_count = 0;
2195 tp->receive_queue_number = NON_MAC_QUEUE;
2196 err1 = smctr_rx_frame(dev);
2197
2198 if(isb_subtype & NON_MAC_RX_RESOURCE_FE)
2199 {
2200 if((err = smctr_issue_resume_rx_fcb_cmd( dev, NON_MAC_QUEUE)) != SUCCESS) break;
2201
2202 if(tp->ptr_rx_fcb_overruns)
2203 (*tp->ptr_rx_fcb_overruns)++;
2204 }
2205
2206 if(isb_subtype & NON_MAC_RX_RESOURCE_BE)
2207 {
2208 if((err = smctr_issue_resume_rx_bdb_cmd( dev, NON_MAC_QUEUE)) != SUCCESS) break;
2209
2210 if(tp->ptr_rx_bdb_overruns)
2211 (*tp->ptr_rx_bdb_overruns)++;
2212 }
2213 err = err1;
2214 break;
2215
2216 /* Type 0x08 - MAC RX Resource Interrupt
2217 * Subtype bit 12 - (BW) BDB warning
2218 * Subtype bit 13 - (FW) FCB warning
2219 * Subtype bit 14 - (BE) BDB End of chain
2220 * Subtype bit 15 - (FE) FCB End of chain
2221 */
2222 case ISB_IMC_MAC_RX_RESOURCE:
2223 tp->receive_queue_number = MAC_QUEUE;
2224 err1 = smctr_rx_frame(dev);
2225
2226 if(isb_subtype & MAC_RX_RESOURCE_FE)
2227 {
2228 if((err = smctr_issue_resume_rx_fcb_cmd( dev, MAC_QUEUE)) != SUCCESS)
2229 break;
2230
2231 if(tp->ptr_rx_fcb_overruns)
2232 (*tp->ptr_rx_fcb_overruns)++;
2233 }
2234
2235 if(isb_subtype & MAC_RX_RESOURCE_BE)
2236 {
2237 if((err = smctr_issue_resume_rx_bdb_cmd( dev, MAC_QUEUE)) != SUCCESS)
2238 break;
2239
2240 if(tp->ptr_rx_bdb_overruns)
2241 (*tp->ptr_rx_bdb_overruns)++;
2242 }
2243 err = err1;
2244 break;
2245
2246 /* Type 0x09 - NON_MAC RX Frame Interrupt */
2247 case ISB_IMC_NON_MAC_RX_FRAME:
2248 tp->rx_fifo_overrun_count = 0;
2249 tp->receive_queue_number = NON_MAC_QUEUE;
2250 err = smctr_rx_frame(dev);
2251 break;
2252
2253 /* Type 0x0A - MAC RX Frame Interrupt */
2254 case ISB_IMC_MAC_RX_FRAME:
2255 tp->receive_queue_number = MAC_QUEUE;
2256 err = smctr_rx_frame(dev);
2257 break;
2258
2259 /* Type 0x0B - TRC status
2260 * TRC has encountered an error condition
2261 * subtype bit 14 - transmit FIFO underrun
2262 * subtype bit 15 - receive FIFO overrun
2263 */
2264 case ISB_IMC_TRC_FIFO_STATUS:
2265 if(isb_subtype & TRC_FIFO_STATUS_TX_UNDERRUN)
2266 {
2267 if(tp->ptr_tx_fifo_underruns)
2268 (*tp->ptr_tx_fifo_underruns)++;
2269 }
2270
2271 if(isb_subtype & TRC_FIFO_STATUS_RX_OVERRUN)
2272 {
2273 /* update overrun stuck receive counter
2274 * if >= 3, has to clear it by sending
2275 * back to back frames. We pick
2276 * DAT(duplicate address MAC frame)
2277 */
2278 tp->rx_fifo_overrun_count++;
2279
2280 if(tp->rx_fifo_overrun_count >= 3)
2281 {
2282 tp->rx_fifo_overrun_count = 0;
2283
2284 /* delay clearing fifo overrun
2285 * imask till send_BUG tx
2286 * complete posted
2287 */
2288 interrupt_unmask_bits &= (~0x800);
2289 printk(KERN_CRIT "Jay please send bug\n");// smctr_send_bug(dev);
2290 }
2291
2292 if(tp->ptr_rx_fifo_overruns)
2293 (*tp->ptr_rx_fifo_overruns)++;
2294 }
2295
2296 err = SUCCESS;
2297 break;
2298
2299 /* Type 0x0C - Action Command Status Interrupt
2300 * Subtype bit 14 - CB end of command chain (CE)
2301 * Subtype bit 15 - CB command interrupt (CI)
2302 */
2303 case ISB_IMC_COMMAND_STATUS:
2304 err = SUCCESS;
2305 if(tp->acb_head->cmd == ACB_CMD_HIC_NOP)
2306 {
2307 printk(KERN_ERR "i1\n");
2308 smctr_disable_16bit(dev);
2309
2310 /* XXXXXXXXXXXXXXXXX */
2311 /* err = UM_Interrupt(dev); */
2312
2313 smctr_enable_16bit(dev);
2314 }
2315 else
2316 {
2317 if((tp->acb_head->cmd
2318 == ACB_CMD_READ_TRC_STATUS)
2319 && (tp->acb_head->subcmd
2320 == RW_TRC_STATUS_BLOCK))
2321 {
2322 if(tp->ptr_bcn_type != 0)
2323 {
2324 *(tp->ptr_bcn_type)
2325 = (__u32)((SBlock *)tp->misc_command_data)->BCN_Type;
2326 }
2327
2328 if(((SBlock *)tp->misc_command_data)->Status_CHG_Indicate & ERROR_COUNTERS_CHANGED)
2329 {
2330 smctr_update_err_stats(dev);
2331 }
2332
2333 if(((SBlock *)tp->misc_command_data)->Status_CHG_Indicate & TI_NDIS_RING_STATUS_CHANGED)
2334 {
2335 tp->ring_status
2336 = ((SBlock*)tp->misc_command_data)->TI_NDIS_Ring_Status;
2337 smctr_disable_16bit(dev);
2338 err = smctr_ring_status_chg(dev);
2339 smctr_enable_16bit(dev);
2340 if((tp->ring_status & REMOVE_RECEIVED)
2341 && (tp->config_word0 & NO_AUTOREMOVE))
2342 {
2343 smctr_issue_remove_cmd(dev);
2344 }
2345
2346 if(err != SUCCESS)
2347 {
2348 tp->acb_pending = 0;
2349 break;
2350 }
2351 }
2352
2353 if(((SBlock *)tp->misc_command_data)->Status_CHG_Indicate & UNA_CHANGED)
2354 {
2355 if(tp->ptr_una)
2356 {
2357 tp->ptr_una[0] = SWAP_BYTES(((SBlock *)tp->misc_command_data)->UNA[0]);
2358 tp->ptr_una[1] = SWAP_BYTES(((SBlock *)tp->misc_command_data)->UNA[1]);
2359 tp->ptr_una[2] = SWAP_BYTES(((SBlock *)tp->misc_command_data)->UNA[2]);
2360 }
2361
2362 }
2363
2364 if(((SBlock *)tp->misc_command_data)->Status_CHG_Indicate & READY_TO_SEND_RQ_INIT) {
2365 err = smctr_send_rq_init(dev);
2366 }
2367 }
2368 }
2369
2370 tp->acb_pending = 0;
2371 break;
2372
2373 /* Type 0x0D - MAC Type 1 interrupt
2374 * Subtype -- 00 FR_BCN received at S12
2375 * 01 FR_BCN received at S21
2376 * 02 FR_DAT(DA=MA, A<>0) received at S21
2377 * 03 TSM_EXP at S21
2378 * 04 FR_REMOVE received at S42
2379 * 05 TBR_EXP, BR_FLAG_SET at S42
2380 * 06 TBT_EXP at S53
2381 */
2382 case ISB_IMC_MAC_TYPE_1:
2383 if(isb_subtype > 8)
2384 {
2385 err = HARDWARE_FAILED;
2386 break;
2387 }
2388
2389 err = SUCCESS;
2390 switch(isb_subtype)
2391 {
2392 case 0:
2393 tp->join_state = JS_BYPASS_STATE;
2394 if(tp->status != CLOSED)
2395 {
2396 tp->status = CLOSED;
2397 err = smctr_status_chg(dev);
2398 }
2399 break;
2400
2401 case 1:
2402 tp->join_state = JS_LOBE_TEST_STATE;
2403 break;
2404
2405 case 2:
2406 tp->join_state = JS_DETECT_MONITOR_PRESENT_STATE;
2407 break;
2408
2409 case 3:
2410 tp->join_state = JS_AWAIT_NEW_MONITOR_STATE;
2411 break;
2412
2413 case 4:
2414 tp->join_state = JS_DUPLICATE_ADDRESS_TEST_STATE;
2415 break;
2416
2417 case 5:
2418 tp->join_state = JS_NEIGHBOR_NOTIFICATION_STATE;
2419 break;
2420
2421 case 6:
2422 tp->join_state = JS_REQUEST_INITIALIZATION_STATE;
2423 break;
2424
2425 case 7:
2426 tp->join_state = JS_JOIN_COMPLETE_STATE;
2427 tp->status = OPEN;
2428 err = smctr_status_chg(dev);
2429 break;
2430
2431 case 8:
2432 tp->join_state = JS_BYPASS_WAIT_STATE;
2433 break;
2434 }
2435 break ;
2436
2437 /* Type 0x0E - TRC Initialization Sequence Interrupt
2438 * Subtype -- 00-FF Initializatin sequence complete
2439 */
2440 case ISB_IMC_TRC_INTRNL_TST_STATUS:
2441 tp->status = INITIALIZED;
2442 smctr_disable_16bit(dev);
2443 err = smctr_status_chg(dev);
2444 smctr_enable_16bit(dev);
2445 break;
2446
2447 /* other interrupt types, illegal */
2448 default:
2449 break;
2450 }
2451
2452 if(err != SUCCESS)
2453 break;
2454 }
2455
2456 /* Checking the ack code instead of the unmask bits here is because :
2457 * while fixing the stuck receive, DAT frame are sent and mask off
2458 * FIFO overrun interrupt temporarily (interrupt_unmask_bits = 0)
2459 * but we still want to issue ack to ISB
2460 */
2461 if(!(interrupt_ack_code & 0xff00))
2462 smctr_issue_int_ack(dev, interrupt_ack_code, interrupt_unmask_bits);
2463
2464 smctr_disable_16bit(dev);
2465 smctr_enable_bic_int(dev);
2466 spin_unlock(&tp->lock);
2467
2468 return IRQ_HANDLED;
2469}
2470
2471static int smctr_issue_enable_int_cmd(struct net_device *dev,
2472 __u16 interrupt_enable_mask)
2473{
2474 struct net_local *tp = netdev_priv(dev);
2475 int err;
2476
2477 if((err = smctr_wait_while_cbusy(dev)))
2478 return (err);
2479
2480 tp->sclb_ptr->int_mask_control = interrupt_enable_mask;
2481 tp->sclb_ptr->valid_command = SCLB_VALID | SCLB_CMD_CLEAR_INTERRUPT_MASK;
2482
2483 smctr_set_ctrl_attention(dev);
2484
2485 return (0);
2486}
2487
2488static int smctr_issue_int_ack(struct net_device *dev, __u16 iack_code, __u16 ibits)
2489{
2490 struct net_local *tp = netdev_priv(dev);
2491
2492 if(smctr_wait_while_cbusy(dev))
2493 return (-1);
2494
2495 tp->sclb_ptr->int_mask_control = ibits;
2496 tp->sclb_ptr->iack_code = iack_code << 1; /* use the offset from base */ tp->sclb_ptr->resume_control = 0;
2497 tp->sclb_ptr->valid_command = SCLB_VALID | SCLB_IACK_CODE_VALID | SCLB_CMD_CLEAR_INTERRUPT_MASK;
2498
2499 smctr_set_ctrl_attention(dev);
2500
2501 return (0);
2502}
2503
2504static int smctr_issue_init_timers_cmd(struct net_device *dev)
2505{
2506 struct net_local *tp = netdev_priv(dev);
2507 unsigned int i;
2508 int err;
2509 __u16 *pTimer_Struc = (__u16 *)tp->misc_command_data;
2510
2511 if((err = smctr_wait_while_cbusy(dev)))
2512 return (err);
2513
2514 if((err = smctr_wait_cmd(dev)))
2515 return (err);
2516
2517 tp->config_word0 = THDREN | DMA_TRIGGER | USETPT | NO_AUTOREMOVE;
2518 tp->config_word1 = 0;
2519
2520 if((tp->media_type == MEDIA_STP_16)
2521 || (tp->media_type == MEDIA_UTP_16)
2522 || (tp->media_type == MEDIA_STP_16_UTP_16))
2523 {
2524 tp->config_word0 |= FREQ_16MB_BIT;
2525 }
2526
2527 if(tp->mode_bits & EARLY_TOKEN_REL)
2528 tp->config_word0 |= ETREN;
2529
2530 if(tp->mode_bits & LOOPING_MODE_MASK)
2531 tp->config_word0 |= RX_OWN_BIT;
2532 else
2533 tp->config_word0 &= ~RX_OWN_BIT;
2534
2535 if(tp->receive_mask & PROMISCUOUS_MODE)
2536 tp->config_word0 |= PROMISCUOUS_BIT;
2537 else
2538 tp->config_word0 &= ~PROMISCUOUS_BIT;
2539
2540 if(tp->receive_mask & ACCEPT_ERR_PACKETS)
2541 tp->config_word0 |= SAVBAD_BIT;
2542 else
2543 tp->config_word0 &= ~SAVBAD_BIT;
2544
2545 if(tp->receive_mask & ACCEPT_ATT_MAC_FRAMES)
2546 tp->config_word0 |= RXATMAC;
2547 else
2548 tp->config_word0 &= ~RXATMAC;
2549
2550 if(tp->receive_mask & ACCEPT_MULTI_PROM)
2551 tp->config_word1 |= MULTICAST_ADDRESS_BIT;
2552 else
2553 tp->config_word1 &= ~MULTICAST_ADDRESS_BIT;
2554
2555 if(tp->receive_mask & ACCEPT_SOURCE_ROUTING_SPANNING)
2556 tp->config_word1 |= SOURCE_ROUTING_SPANNING_BITS;
2557 else
2558 {
2559 if(tp->receive_mask & ACCEPT_SOURCE_ROUTING)
2560 tp->config_word1 |= SOURCE_ROUTING_EXPLORER_BIT;
2561 else
2562 tp->config_word1 &= ~SOURCE_ROUTING_SPANNING_BITS;
2563 }
2564
2565 if((tp->media_type == MEDIA_STP_16)
2566 || (tp->media_type == MEDIA_UTP_16)
2567 || (tp->media_type == MEDIA_STP_16_UTP_16))
2568 {
2569 tp->config_word1 |= INTERFRAME_SPACING_16;
2570 }
2571 else
2572 tp->config_word1 |= INTERFRAME_SPACING_4;
2573
2574 *pTimer_Struc++ = tp->config_word0;
2575 *pTimer_Struc++ = tp->config_word1;
2576
2577 if((tp->media_type == MEDIA_STP_4)
2578 || (tp->media_type == MEDIA_UTP_4)
2579 || (tp->media_type == MEDIA_STP_4_UTP_4))
2580 {
2581 *pTimer_Struc++ = 0x00FA; /* prescale */
2582 *pTimer_Struc++ = 0x2710; /* TPT_limit */
2583 *pTimer_Struc++ = 0x2710; /* TQP_limit */
2584 *pTimer_Struc++ = 0x0A28; /* TNT_limit */
2585 *pTimer_Struc++ = 0x3E80; /* TBT_limit */
2586 *pTimer_Struc++ = 0x3A98; /* TSM_limit */
2587 *pTimer_Struc++ = 0x1B58; /* TAM_limit */
2588 *pTimer_Struc++ = 0x00C8; /* TBR_limit */
2589 *pTimer_Struc++ = 0x07D0; /* TER_limit */
2590 *pTimer_Struc++ = 0x000A; /* TGT_limit */
2591 *pTimer_Struc++ = 0x1162; /* THT_limit */
2592 *pTimer_Struc++ = 0x07D0; /* TRR_limit */
2593 *pTimer_Struc++ = 0x1388; /* TVX_limit */
2594 *pTimer_Struc++ = 0x0000; /* reserved */
2595 }
2596 else
2597 {
2598 *pTimer_Struc++ = 0x03E8; /* prescale */
2599 *pTimer_Struc++ = 0x9C40; /* TPT_limit */
2600 *pTimer_Struc++ = 0x9C40; /* TQP_limit */
2601 *pTimer_Struc++ = 0x0A28; /* TNT_limit */
2602 *pTimer_Struc++ = 0x3E80; /* TBT_limit */
2603 *pTimer_Struc++ = 0x3A98; /* TSM_limit */
2604 *pTimer_Struc++ = 0x1B58; /* TAM_limit */
2605 *pTimer_Struc++ = 0x00C8; /* TBR_limit */
2606 *pTimer_Struc++ = 0x07D0; /* TER_limit */
2607 *pTimer_Struc++ = 0x000A; /* TGT_limit */
2608 *pTimer_Struc++ = 0x4588; /* THT_limit */
2609 *pTimer_Struc++ = 0x1F40; /* TRR_limit */
2610 *pTimer_Struc++ = 0x4E20; /* TVX_limit */
2611 *pTimer_Struc++ = 0x0000; /* reserved */
2612 }
2613
2614 /* Set node address. */
2615 *pTimer_Struc++ = dev->dev_addr[0] << 8
2616 | (dev->dev_addr[1] & 0xFF);
2617 *pTimer_Struc++ = dev->dev_addr[2] << 8
2618 | (dev->dev_addr[3] & 0xFF);
2619 *pTimer_Struc++ = dev->dev_addr[4] << 8
2620 | (dev->dev_addr[5] & 0xFF);
2621
2622 /* Set group address. */
2623 *pTimer_Struc++ = tp->group_address_0 << 8
2624 | tp->group_address_0 >> 8;
2625 *pTimer_Struc++ = tp->group_address[0] << 8
2626 | tp->group_address[0] >> 8;
2627 *pTimer_Struc++ = tp->group_address[1] << 8
2628 | tp->group_address[1] >> 8;
2629
2630 /* Set functional address. */
2631 *pTimer_Struc++ = tp->functional_address_0 << 8
2632 | tp->functional_address_0 >> 8;
2633 *pTimer_Struc++ = tp->functional_address[0] << 8
2634 | tp->functional_address[0] >> 8;
2635 *pTimer_Struc++ = tp->functional_address[1] << 8
2636 | tp->functional_address[1] >> 8;
2637
2638 /* Set Bit-Wise group address. */
2639 *pTimer_Struc++ = tp->bitwise_group_address[0] << 8
2640 | tp->bitwise_group_address[0] >> 8;
2641 *pTimer_Struc++ = tp->bitwise_group_address[1] << 8
2642 | tp->bitwise_group_address[1] >> 8;
2643
2644 /* Set ring number address. */
2645 *pTimer_Struc++ = tp->source_ring_number;
2646 *pTimer_Struc++ = tp->target_ring_number;
2647
2648 /* Physical drop number. */
2649 *pTimer_Struc++ = (unsigned short)0;
2650 *pTimer_Struc++ = (unsigned short)0;
2651
2652 /* Product instance ID. */
2653 for(i = 0; i < 9; i++)
2654 *pTimer_Struc++ = (unsigned short)0;
2655
2656 err = smctr_setup_single_cmd_w_data(dev, ACB_CMD_INIT_TRC_TIMERS, 0);
2657
2658 return (err);
2659}
2660
2661static int smctr_issue_init_txrx_cmd(struct net_device *dev)
2662{
2663 struct net_local *tp = netdev_priv(dev);
2664 unsigned int i;
2665 int err;
2666 void **txrx_ptrs = (void *)tp->misc_command_data;
2667
2668 if((err = smctr_wait_while_cbusy(dev)))
2669 return (err);
2670
2671 if((err = smctr_wait_cmd(dev)))
2672 {
2673 printk(KERN_ERR "%s: Hardware failure\n", dev->name);
2674 return (err);
2675 }
2676
2677 /* Initialize Transmit Queue Pointers that are used, to point to
2678 * a single FCB.
2679 */
2680 for(i = 0; i < NUM_TX_QS_USED; i++)
2681 *txrx_ptrs++ = (void *)TRC_POINTER(tp->tx_fcb_head[i]);
2682
2683 /* Initialize Transmit Queue Pointers that are NOT used to ZERO. */
2684 for(; i < MAX_TX_QS; i++)
2685 *txrx_ptrs++ = (void *)0;
2686
2687 /* Initialize Receive Queue Pointers (MAC and Non-MAC) that are
2688 * used, to point to a single FCB and a BDB chain of buffers.
2689 */
2690 for(i = 0; i < NUM_RX_QS_USED; i++)
2691 {
2692 *txrx_ptrs++ = (void *)TRC_POINTER(tp->rx_fcb_head[i]);
2693 *txrx_ptrs++ = (void *)TRC_POINTER(tp->rx_bdb_head[i]);
2694 }
2695
2696 /* Initialize Receive Queue Pointers that are NOT used to ZERO. */
2697 for(; i < MAX_RX_QS; i++)
2698 {
2699 *txrx_ptrs++ = (void *)0;
2700 *txrx_ptrs++ = (void *)0;
2701 }
2702
2703 err = smctr_setup_single_cmd_w_data(dev, ACB_CMD_INIT_TX_RX, 0);
2704
2705 return (err);
2706}
2707
2708static int smctr_issue_insert_cmd(struct net_device *dev)
2709{
2710 int err;
2711
2712 err = smctr_setup_single_cmd(dev, ACB_CMD_INSERT, ACB_SUB_CMD_NOP);
2713
2714 return (err);
2715}
2716
2717static int smctr_issue_read_ring_status_cmd(struct net_device *dev)
2718{
2719 int err;
2720
2721 if((err = smctr_wait_while_cbusy(dev)))
2722 return (err);
2723
2724 if((err = smctr_wait_cmd(dev)))
2725 return (err);
2726
2727 err = smctr_setup_single_cmd_w_data(dev, ACB_CMD_READ_TRC_STATUS,
2728 RW_TRC_STATUS_BLOCK);
2729
2730 return (err);
2731}
2732
2733static int smctr_issue_read_word_cmd(struct net_device *dev, __u16 aword_cnt)
2734{
2735 int err;
2736
2737 if((err = smctr_wait_while_cbusy(dev)))
2738 return (err);
2739
2740 if((err = smctr_wait_cmd(dev)))
2741 return (err);
2742
2743 err = smctr_setup_single_cmd_w_data(dev, ACB_CMD_MCT_READ_VALUE,
2744 aword_cnt);
2745
2746 return (err);
2747}
2748
2749static int smctr_issue_remove_cmd(struct net_device *dev)
2750{
2751 struct net_local *tp = netdev_priv(dev);
2752 int err;
2753
2754 if((err = smctr_wait_while_cbusy(dev)))
2755 return (err);
2756
2757 tp->sclb_ptr->resume_control = 0;
2758 tp->sclb_ptr->valid_command = SCLB_VALID | SCLB_CMD_REMOVE;
2759
2760 smctr_set_ctrl_attention(dev);
2761
2762 return (0);
2763}
2764
2765static int smctr_issue_resume_acb_cmd(struct net_device *dev)
2766{
2767 struct net_local *tp = netdev_priv(dev);
2768 int err;
2769
2770 if((err = smctr_wait_while_cbusy(dev)))
2771 return (err);
2772
2773 tp->sclb_ptr->resume_control = SCLB_RC_ACB;
2774 tp->sclb_ptr->valid_command = SCLB_VALID | SCLB_RESUME_CONTROL_VALID;
2775
2776 tp->acb_pending = 1;
2777
2778 smctr_set_ctrl_attention(dev);
2779
2780 return (0);
2781}
2782
2783static int smctr_issue_resume_rx_bdb_cmd(struct net_device *dev, __u16 queue)
2784{
2785 struct net_local *tp = netdev_priv(dev);
2786 int err;
2787
2788 if((err = smctr_wait_while_cbusy(dev)))
2789 return (err);
2790
2791 if(queue == MAC_QUEUE)
2792 tp->sclb_ptr->resume_control = SCLB_RC_RX_MAC_BDB;
2793 else
2794 tp->sclb_ptr->resume_control = SCLB_RC_RX_NON_MAC_BDB;
2795
2796 tp->sclb_ptr->valid_command = SCLB_VALID | SCLB_RESUME_CONTROL_VALID;
2797
2798 smctr_set_ctrl_attention(dev);
2799
2800 return (0);
2801}
2802
2803static int smctr_issue_resume_rx_fcb_cmd(struct net_device *dev, __u16 queue)
2804{
2805 struct net_local *tp = netdev_priv(dev);
2806
2807 if(smctr_debug > 10)
2808 printk(KERN_DEBUG "%s: smctr_issue_resume_rx_fcb_cmd\n", dev->name);
2809
2810 if(smctr_wait_while_cbusy(dev))
2811 return (-1);
2812
2813 if(queue == MAC_QUEUE)
2814 tp->sclb_ptr->resume_control = SCLB_RC_RX_MAC_FCB;
2815 else
2816 tp->sclb_ptr->resume_control = SCLB_RC_RX_NON_MAC_FCB;
2817
2818 tp->sclb_ptr->valid_command = SCLB_VALID | SCLB_RESUME_CONTROL_VALID;
2819
2820 smctr_set_ctrl_attention(dev);
2821
2822 return (0);
2823}
2824
2825static int smctr_issue_resume_tx_fcb_cmd(struct net_device *dev, __u16 queue)
2826{
2827 struct net_local *tp = netdev_priv(dev);
2828
2829 if(smctr_debug > 10)
2830 printk(KERN_DEBUG "%s: smctr_issue_resume_tx_fcb_cmd\n", dev->name);
2831
2832 if(smctr_wait_while_cbusy(dev))
2833 return (-1);
2834
2835 tp->sclb_ptr->resume_control = (SCLB_RC_TFCB0 << queue);
2836 tp->sclb_ptr->valid_command = SCLB_RESUME_CONTROL_VALID | SCLB_VALID;
2837
2838 smctr_set_ctrl_attention(dev);
2839
2840 return (0);
2841}
2842
2843static int smctr_issue_test_internal_rom_cmd(struct net_device *dev)
2844{
2845 int err;
2846
2847 err = smctr_setup_single_cmd(dev, ACB_CMD_MCT_TEST,
2848 TRC_INTERNAL_ROM_TEST);
2849
2850 return (err);
2851}
2852
2853static int smctr_issue_test_hic_cmd(struct net_device *dev)
2854{
2855 int err;
2856
2857 err = smctr_setup_single_cmd(dev, ACB_CMD_HIC_TEST,
2858 TRC_HOST_INTERFACE_REG_TEST);
2859
2860 return (err);
2861}
2862
2863static int smctr_issue_test_mac_reg_cmd(struct net_device *dev)
2864{
2865 int err;
2866
2867 err = smctr_setup_single_cmd(dev, ACB_CMD_MCT_TEST,
2868 TRC_MAC_REGISTERS_TEST);
2869
2870 return (err);
2871}
2872
2873static int smctr_issue_trc_loopback_cmd(struct net_device *dev)
2874{
2875 int err;
2876
2877 err = smctr_setup_single_cmd(dev, ACB_CMD_MCT_TEST,
2878 TRC_INTERNAL_LOOPBACK);
2879
2880 return (err);
2881}
2882
2883static int smctr_issue_tri_loopback_cmd(struct net_device *dev)
2884{
2885 int err;
2886
2887 err = smctr_setup_single_cmd(dev, ACB_CMD_MCT_TEST,
2888 TRC_TRI_LOOPBACK);
2889
2890 return (err);
2891}
2892
2893static int smctr_issue_write_byte_cmd(struct net_device *dev,
2894 short aword_cnt, void *byte)
2895{
2896 struct net_local *tp = netdev_priv(dev);
2897 unsigned int iword, ibyte;
2898 int err;
2899
2900 if((err = smctr_wait_while_cbusy(dev)))
2901 return (err);
2902
2903 if((err = smctr_wait_cmd(dev)))
2904 return (err);
2905
2906 for(iword = 0, ibyte = 0; iword < (unsigned int)(aword_cnt & 0xff);
2907 iword++, ibyte += 2)
2908 {
2909 tp->misc_command_data[iword] = (*((__u8 *)byte + ibyte) << 8)
2910 | (*((__u8 *)byte + ibyte + 1));
2911 }
2912
2913 return (smctr_setup_single_cmd_w_data(dev, ACB_CMD_MCT_WRITE_VALUE,
2914 aword_cnt));
2915}
2916
2917static int smctr_issue_write_word_cmd(struct net_device *dev,
2918 short aword_cnt, void *word)
2919{
2920 struct net_local *tp = netdev_priv(dev);
2921 unsigned int i, err;
2922
2923 if((err = smctr_wait_while_cbusy(dev)))
2924 return (err);
2925
2926 if((err = smctr_wait_cmd(dev)))
2927 return (err);
2928
2929 for(i = 0; i < (unsigned int)(aword_cnt & 0xff); i++)
2930 tp->misc_command_data[i] = *((__u16 *)word + i);
2931
2932 err = smctr_setup_single_cmd_w_data(dev, ACB_CMD_MCT_WRITE_VALUE,
2933 aword_cnt);
2934
2935 return (err);
2936}
2937
2938static int smctr_join_complete_state(struct net_device *dev)
2939{
2940 int err;
2941
2942 err = smctr_setup_single_cmd(dev, ACB_CMD_CHANGE_JOIN_STATE,
2943 JS_JOIN_COMPLETE_STATE);
2944
2945 return (err);
2946}
2947
2948static int smctr_link_tx_fcbs_to_bdbs(struct net_device *dev)
2949{
2950 struct net_local *tp = netdev_priv(dev);
2951 unsigned int i, j;
2952 FCBlock *fcb;
2953 BDBlock *bdb;
2954
2955 for(i = 0; i < NUM_TX_QS_USED; i++)
2956 {
2957 fcb = tp->tx_fcb_head[i];
2958 bdb = tp->tx_bdb_head[i];
2959
2960 for(j = 0; j < tp->num_tx_fcbs[i]; j++)
2961 {
2962 fcb->bdb_ptr = bdb;
2963 fcb->trc_bdb_ptr = TRC_POINTER(bdb);
2964 fcb = (FCBlock *)((char *)fcb + sizeof(FCBlock));
2965 bdb = (BDBlock *)((char *)bdb + sizeof(BDBlock));
2966 }
2967 }
2968
2969 return (0);
2970}
2971
2972static int smctr_load_firmware(struct net_device *dev)
2973{
2974 struct net_local *tp = netdev_priv(dev);
2975 __u16 i, checksum = 0;
2976 int err = 0;
2977
2978 if(smctr_debug > 10)
2979 printk(KERN_DEBUG "%s: smctr_load_firmware\n", dev->name);
2980
2981 tp->ptr_ucode = smctr_code;
2982 tp->num_of_tx_buffs = 4;
2983 tp->mode_bits |= UMAC;
2984 tp->receive_mask = 0;
2985 tp->max_packet_size = 4177;
2986
2987 /* Can only upload the firmware once per adapter reset. */
2988 if(tp->microcode_version != 0)
2989 return (UCODE_PRESENT);
2990
2991 /* Verify the firmware exists and is there in the right amount. */
2992 if((tp->ptr_ucode == 0L)
2993 || (*(tp->ptr_ucode + UCODE_VERSION_OFFSET) < UCODE_VERSION))
2994 {
2995 return (UCODE_NOT_PRESENT);
2996 }
2997
2998 /* UCODE_SIZE is not included in Checksum. */
2999 for(i = 0; i < *((__u16 *)(tp->ptr_ucode + UCODE_SIZE_OFFSET)); i += 2)
3000 checksum += *((__u16 *)(tp->ptr_ucode + 2 + i));
3001 if(checksum)
3002 return (UCODE_NOT_PRESENT);
3003
3004 /* At this point we have a valid firmware image, lets kick it on up. */
3005 smctr_enable_adapter_ram(dev);
3006 smctr_enable_16bit(dev);
3007 smctr_set_page(dev, (__u8 *)tp->ram_access);
3008
3009 if((smctr_checksum_firmware(dev))
3010 || (*(tp->ptr_ucode + UCODE_VERSION_OFFSET)
3011 > tp->microcode_version))
3012 {
3013 smctr_enable_adapter_ctrl_store(dev);
3014
3015 /* Zero out ram space for firmware. */
3016 for(i = 0; i < CS_RAM_SIZE; i += 2)
3017 *((__u16 *)(tp->ram_access + i)) = 0;
3018
3019 smctr_decode_firmware(dev);
3020
3021 tp->microcode_version = *(tp->ptr_ucode + UCODE_VERSION_OFFSET); *((__u16 *)(tp->ram_access + CS_RAM_VERSION_OFFSET))
3022 = (tp->microcode_version << 8);
3023 *((__u16 *)(tp->ram_access + CS_RAM_CHECKSUM_OFFSET))
3024 = ~(tp->microcode_version << 8) + 1;
3025
3026 smctr_disable_adapter_ctrl_store(dev);
3027
3028 if(smctr_checksum_firmware(dev))
3029 err = HARDWARE_FAILED;
3030 }
3031 else
3032 err = UCODE_PRESENT;
3033
3034 smctr_disable_16bit(dev);
3035
3036 return (err);
3037}
3038
3039static int smctr_load_node_addr(struct net_device *dev)
3040{
3041 int ioaddr = dev->base_addr;
3042 unsigned int i;
3043 __u8 r;
3044
3045 for(i = 0; i < 6; i++)
3046 {
3047 r = inb(ioaddr + LAR0 + i);
3048 dev->dev_addr[i] = (char)r;
3049 }
3050 dev->addr_len = 6;
3051
3052 return (0);
3053}
3054
3055/* Lobe Media Test.
3056 * During the transmission of the initial 1500 lobe media MAC frames,
3057 * the phase lock loop in the 805 chip may lock, and then un-lock, causing
3058 * the 825 to go into a PURGE state. When performing a PURGE, the MCT
3059 * microcode will not transmit any frames given to it by the host, and
3060 * will consequently cause a timeout.
3061 *
3062 * NOTE 1: If the monitor_state is MS_BEACON_TEST_STATE, all transmit
3063 * queues other then the one used for the lobe_media_test should be
3064 * disabled.!?
3065 *
3066 * NOTE 2: If the monitor_state is MS_BEACON_TEST_STATE and the receive_mask
3067 * has any multi-cast or promiscous bits set, the receive_mask needs to
3068 * be changed to clear the multi-cast or promiscous mode bits, the lobe_test
3069 * run, and then the receive mask set back to its original value if the test
3070 * is successful.
3071 */
3072static int smctr_lobe_media_test(struct net_device *dev)
3073{
3074 struct net_local *tp = netdev_priv(dev);
3075 unsigned int i, perror = 0;
3076 unsigned short saved_rcv_mask;
3077
3078 if(smctr_debug > 10)
3079 printk(KERN_DEBUG "%s: smctr_lobe_media_test\n", dev->name);
3080
3081 /* Clear receive mask for lobe test. */
3082 saved_rcv_mask = tp->receive_mask;
3083 tp->receive_mask = 0;
3084
3085 smctr_chg_rx_mask(dev);
3086
3087 /* Setup the lobe media test. */
3088 smctr_lobe_media_test_cmd(dev);
3089 if(smctr_wait_cmd(dev))
3090 {
3091 smctr_reset_adapter(dev);
3092 tp->status = CLOSED;
3093 return (LOBE_MEDIA_TEST_FAILED);
3094 }
3095
3096 /* Tx lobe media test frames. */
3097 for(i = 0; i < 1500; ++i)
3098 {
3099 if(smctr_send_lobe_media_test(dev))
3100 {
3101 if(perror)
3102 {
3103 smctr_reset_adapter(dev);
3104 tp->state = CLOSED;
3105 return (LOBE_MEDIA_TEST_FAILED);
3106 }
3107 else
3108 {
3109 perror = 1;
3110 if(smctr_lobe_media_test_cmd(dev))
3111 {
3112 smctr_reset_adapter(dev);
3113 tp->state = CLOSED;
3114 return (LOBE_MEDIA_TEST_FAILED);
3115 }
3116 }
3117 }
3118 }
3119
3120 if(smctr_send_dat(dev))
3121 {
3122 if(smctr_send_dat(dev))
3123 {
3124 smctr_reset_adapter(dev);
3125 tp->state = CLOSED;
3126 return (LOBE_MEDIA_TEST_FAILED);
3127 }
3128 }
3129
3130 /* Check if any frames received during test. */
3131 if((tp->rx_fcb_curr[MAC_QUEUE]->frame_status)
3132 || (tp->rx_fcb_curr[NON_MAC_QUEUE]->frame_status))
3133 {
3134 smctr_reset_adapter(dev);
3135 tp->state = CLOSED;
3136 return (LOBE_MEDIA_TEST_FAILED);
3137 }
3138
3139 /* Set receive mask to "Promisc" mode. */
3140 tp->receive_mask = saved_rcv_mask;
3141
3142 smctr_chg_rx_mask(dev);
3143
3144 return (0);
3145}
3146
3147static int smctr_lobe_media_test_cmd(struct net_device *dev)
3148{
3149 struct net_local *tp = netdev_priv(dev);
3150 int err;
3151
3152 if(smctr_debug > 10)
3153 printk(KERN_DEBUG "%s: smctr_lobe_media_test_cmd\n", dev->name);
3154
3155 /* Change to lobe media test state. */
3156 if(tp->monitor_state != MS_BEACON_TEST_STATE)
3157 {
3158 smctr_lobe_media_test_state(dev);
3159 if(smctr_wait_cmd(dev))
3160 {
3161 printk(KERN_ERR "Lobe Failed test state\n");
3162 return (LOBE_MEDIA_TEST_FAILED);
3163 }
3164 }
3165
3166 err = smctr_setup_single_cmd(dev, ACB_CMD_MCT_TEST,
3167 TRC_LOBE_MEDIA_TEST);
3168
3169 return (err);
3170}
3171
3172static int smctr_lobe_media_test_state(struct net_device *dev)
3173{
3174 int err;
3175
3176 err = smctr_setup_single_cmd(dev, ACB_CMD_CHANGE_JOIN_STATE,
3177 JS_LOBE_TEST_STATE);
3178
3179 return (err);
3180}
3181
3182static int smctr_make_8025_hdr(struct net_device *dev,
3183 MAC_HEADER *rmf, MAC_HEADER *tmf, __u16 ac_fc)
3184{
3185 tmf->ac = MSB(ac_fc); /* msb is access control */
3186 tmf->fc = LSB(ac_fc); /* lsb is frame control */
3187
3188 tmf->sa[0] = dev->dev_addr[0];
3189 tmf->sa[1] = dev->dev_addr[1];
3190 tmf->sa[2] = dev->dev_addr[2];
3191 tmf->sa[3] = dev->dev_addr[3];
3192 tmf->sa[4] = dev->dev_addr[4];
3193 tmf->sa[5] = dev->dev_addr[5];
3194
3195 switch(tmf->vc)
3196 {
3197 /* Send RQ_INIT to RPS */
3198 case RQ_INIT:
3199 tmf->da[0] = 0xc0;
3200 tmf->da[1] = 0x00;
3201 tmf->da[2] = 0x00;
3202 tmf->da[3] = 0x00;
3203 tmf->da[4] = 0x00;
3204 tmf->da[5] = 0x02;
3205 break;
3206
3207 /* Send RPT_TX_FORWARD to CRS */
3208 case RPT_TX_FORWARD:
3209 tmf->da[0] = 0xc0;
3210 tmf->da[1] = 0x00;
3211 tmf->da[2] = 0x00;
3212 tmf->da[3] = 0x00;
3213 tmf->da[4] = 0x00;
3214 tmf->da[5] = 0x10;
3215 break;
3216
3217 /* Everything else goes to sender */
3218 default:
3219 tmf->da[0] = rmf->sa[0];
3220 tmf->da[1] = rmf->sa[1];
3221 tmf->da[2] = rmf->sa[2];
3222 tmf->da[3] = rmf->sa[3];
3223 tmf->da[4] = rmf->sa[4];
3224 tmf->da[5] = rmf->sa[5];
3225 break;
3226 }
3227
3228 return (0);
3229}
3230
3231static int smctr_make_access_pri(struct net_device *dev, MAC_SUB_VECTOR *tsv)
3232{
3233 struct net_local *tp = netdev_priv(dev);
3234
3235 tsv->svi = AUTHORIZED_ACCESS_PRIORITY;
3236 tsv->svl = S_AUTHORIZED_ACCESS_PRIORITY;
3237
3238 tsv->svv[0] = MSB(tp->authorized_access_priority);
3239 tsv->svv[1] = LSB(tp->authorized_access_priority);
3240
3241 return (0);
3242}
3243
3244static int smctr_make_addr_mod(struct net_device *dev, MAC_SUB_VECTOR *tsv)
3245{
3246 tsv->svi = ADDRESS_MODIFER;
3247 tsv->svl = S_ADDRESS_MODIFER;
3248
3249 tsv->svv[0] = 0;
3250 tsv->svv[1] = 0;
3251
3252 return (0);
3253}
3254
3255static int smctr_make_auth_funct_class(struct net_device *dev,
3256 MAC_SUB_VECTOR *tsv)
3257{
3258 struct net_local *tp = netdev_priv(dev);
3259
3260 tsv->svi = AUTHORIZED_FUNCTION_CLASS;
3261 tsv->svl = S_AUTHORIZED_FUNCTION_CLASS;
3262
3263 tsv->svv[0] = MSB(tp->authorized_function_classes);
3264 tsv->svv[1] = LSB(tp->authorized_function_classes);
3265
3266 return (0);
3267}
3268
3269static int smctr_make_corr(struct net_device *dev,
3270 MAC_SUB_VECTOR *tsv, __u16 correlator)
3271{
3272 tsv->svi = CORRELATOR;
3273 tsv->svl = S_CORRELATOR;
3274
3275 tsv->svv[0] = MSB(correlator);
3276 tsv->svv[1] = LSB(correlator);
3277
3278 return (0);
3279}
3280
3281static int smctr_make_funct_addr(struct net_device *dev, MAC_SUB_VECTOR *tsv)
3282{
3283 struct net_local *tp = netdev_priv(dev);
3284
3285 smctr_get_functional_address(dev);
3286
3287 tsv->svi = FUNCTIONAL_ADDRESS;
3288 tsv->svl = S_FUNCTIONAL_ADDRESS;
3289
3290 tsv->svv[0] = MSB(tp->misc_command_data[0]);
3291 tsv->svv[1] = LSB(tp->misc_command_data[0]);
3292
3293 tsv->svv[2] = MSB(tp->misc_command_data[1]);
3294 tsv->svv[3] = LSB(tp->misc_command_data[1]);
3295
3296 return (0);
3297}
3298
3299static int smctr_make_group_addr(struct net_device *dev, MAC_SUB_VECTOR *tsv)
3300{
3301 struct net_local *tp = netdev_priv(dev);
3302
3303 smctr_get_group_address(dev);
3304
3305 tsv->svi = GROUP_ADDRESS;
3306 tsv->svl = S_GROUP_ADDRESS;
3307
3308 tsv->svv[0] = MSB(tp->misc_command_data[0]);
3309 tsv->svv[1] = LSB(tp->misc_command_data[0]);
3310
3311 tsv->svv[2] = MSB(tp->misc_command_data[1]);
3312 tsv->svv[3] = LSB(tp->misc_command_data[1]);
3313
3314 /* Set Group Address Sub-vector to all zeros if only the
3315 * Group Address/Functional Address Indicator is set.
3316 */
3317 if(tsv->svv[0] == 0x80 && tsv->svv[1] == 0x00
3318 && tsv->svv[2] == 0x00 && tsv->svv[3] == 0x00)
3319 tsv->svv[0] = 0x00;
3320
3321 return (0);
3322}
3323
3324static int smctr_make_phy_drop_num(struct net_device *dev,
3325 MAC_SUB_VECTOR *tsv)
3326{
3327 struct net_local *tp = netdev_priv(dev);
3328
3329 smctr_get_physical_drop_number(dev);
3330
3331 tsv->svi = PHYSICAL_DROP;
3332 tsv->svl = S_PHYSICAL_DROP;
3333
3334 tsv->svv[0] = MSB(tp->misc_command_data[0]);
3335 tsv->svv[1] = LSB(tp->misc_command_data[0]);
3336
3337 tsv->svv[2] = MSB(tp->misc_command_data[1]);
3338 tsv->svv[3] = LSB(tp->misc_command_data[1]);
3339
3340 return (0);
3341}
3342
3343static int smctr_make_product_id(struct net_device *dev, MAC_SUB_VECTOR *tsv)
3344{
3345 int i;
3346
3347 tsv->svi = PRODUCT_INSTANCE_ID;
3348 tsv->svl = S_PRODUCT_INSTANCE_ID;
3349
3350 for(i = 0; i < 18; i++)
3351 tsv->svv[i] = 0xF0;
3352
3353 return (0);
3354}
3355
3356static int smctr_make_station_id(struct net_device *dev, MAC_SUB_VECTOR *tsv)
3357{
3358 struct net_local *tp = netdev_priv(dev);
3359
3360 smctr_get_station_id(dev);
3361
3362 tsv->svi = STATION_IDENTIFER;
3363 tsv->svl = S_STATION_IDENTIFER;
3364
3365 tsv->svv[0] = MSB(tp->misc_command_data[0]);
3366 tsv->svv[1] = LSB(tp->misc_command_data[0]);
3367
3368 tsv->svv[2] = MSB(tp->misc_command_data[1]);
3369 tsv->svv[3] = LSB(tp->misc_command_data[1]);
3370
3371 tsv->svv[4] = MSB(tp->misc_command_data[2]);
3372 tsv->svv[5] = LSB(tp->misc_command_data[2]);
3373
3374 return (0);
3375}
3376
3377static int smctr_make_ring_station_status(struct net_device *dev,
3378 MAC_SUB_VECTOR * tsv)
3379{
3380 tsv->svi = RING_STATION_STATUS;
3381 tsv->svl = S_RING_STATION_STATUS;
3382
3383 tsv->svv[0] = 0;
3384 tsv->svv[1] = 0;
3385 tsv->svv[2] = 0;
3386 tsv->svv[3] = 0;
3387 tsv->svv[4] = 0;
3388 tsv->svv[5] = 0;
3389
3390 return (0);
3391}
3392
3393static int smctr_make_ring_station_version(struct net_device *dev,
3394 MAC_SUB_VECTOR *tsv)
3395{
3396 struct net_local *tp = netdev_priv(dev);
3397
3398 tsv->svi = RING_STATION_VERSION_NUMBER;
3399 tsv->svl = S_RING_STATION_VERSION_NUMBER;
3400
3401 tsv->svv[0] = 0xe2; /* EBCDIC - S */
3402 tsv->svv[1] = 0xd4; /* EBCDIC - M */
3403 tsv->svv[2] = 0xc3; /* EBCDIC - C */
3404 tsv->svv[3] = 0x40; /* EBCDIC - */
3405 tsv->svv[4] = 0xe5; /* EBCDIC - V */
3406 tsv->svv[5] = 0xF0 + (tp->microcode_version >> 4);
3407 tsv->svv[6] = 0xF0 + (tp->microcode_version & 0x0f);
3408 tsv->svv[7] = 0x40; /* EBCDIC - */
3409 tsv->svv[8] = 0xe7; /* EBCDIC - X */
3410
3411 if(tp->extra_info & CHIP_REV_MASK)
3412 tsv->svv[9] = 0xc5; /* EBCDIC - E */
3413 else
3414 tsv->svv[9] = 0xc4; /* EBCDIC - D */
3415
3416 return (0);
3417}
3418
3419static int smctr_make_tx_status_code(struct net_device *dev,
3420 MAC_SUB_VECTOR *tsv, __u16 tx_fstatus)
3421{
3422 tsv->svi = TRANSMIT_STATUS_CODE;
3423 tsv->svl = S_TRANSMIT_STATUS_CODE;
3424
3425 tsv->svv[0] = ((tx_fstatus & 0x0100 >> 6) || IBM_PASS_SOURCE_ADDR);
3426
3427 /* Stripped frame status of Transmitted Frame */
3428 tsv->svv[1] = tx_fstatus & 0xff;
3429
3430 return (0);
3431}
3432
3433static int smctr_make_upstream_neighbor_addr(struct net_device *dev,
3434 MAC_SUB_VECTOR *tsv)
3435{
3436 struct net_local *tp = netdev_priv(dev);
3437
3438 smctr_get_upstream_neighbor_addr(dev);
3439
3440 tsv->svi = UPSTREAM_NEIGHBOR_ADDRESS;
3441 tsv->svl = S_UPSTREAM_NEIGHBOR_ADDRESS;
3442
3443 tsv->svv[0] = MSB(tp->misc_command_data[0]);
3444 tsv->svv[1] = LSB(tp->misc_command_data[0]);
3445
3446 tsv->svv[2] = MSB(tp->misc_command_data[1]);
3447 tsv->svv[3] = LSB(tp->misc_command_data[1]);
3448
3449 tsv->svv[4] = MSB(tp->misc_command_data[2]);
3450 tsv->svv[5] = LSB(tp->misc_command_data[2]);
3451
3452 return (0);
3453}
3454
3455static int smctr_make_wrap_data(struct net_device *dev, MAC_SUB_VECTOR *tsv)
3456{
3457 tsv->svi = WRAP_DATA;
3458 tsv->svl = S_WRAP_DATA;
3459
3460 return (0);
3461}
3462
3463/*
3464 * Open/initialize the board. This is called sometime after
3465 * booting when the 'ifconfig' program is run.
3466 *
3467 * This routine should set everything up anew at each open, even
3468 * registers that "should" only need to be set once at boot, so that
3469 * there is non-reboot way to recover if something goes wrong.
3470 */
3471static int smctr_open(struct net_device *dev)
3472{
3473 int err;
3474
3475 if(smctr_debug > 10)
3476 printk(KERN_DEBUG "%s: smctr_open\n", dev->name);
3477
3478 err = smctr_init_adapter(dev);
3479 if(err < 0)
3480 return (err);
3481
3482 return (err);
3483}
3484
3485/* Interrupt driven open of Token card. */
3486static int smctr_open_tr(struct net_device *dev)
3487{
3488 struct net_local *tp = netdev_priv(dev);
3489 unsigned long flags;
3490 int err;
3491
3492 if(smctr_debug > 10)
3493 printk(KERN_DEBUG "%s: smctr_open_tr\n", dev->name);
3494
3495 /* Now we can actually open the adapter. */
3496 if(tp->status == OPEN)
3497 return (0);
3498 if(tp->status != INITIALIZED)
3499 return (-1);
3500
3501 /* FIXME: it would work a lot better if we masked the irq sources
3502 on the card here, then we could skip the locking and poll nicely */
3503 spin_lock_irqsave(&tp->lock, flags);
3504
3505 smctr_set_page(dev, (__u8 *)tp->ram_access);
3506
3507 if((err = smctr_issue_resume_rx_fcb_cmd(dev, (short)MAC_QUEUE)))
3508 goto out;
3509
3510 if((err = smctr_issue_resume_rx_bdb_cmd(dev, (short)MAC_QUEUE)))
3511 goto out;
3512
3513 if((err = smctr_issue_resume_rx_fcb_cmd(dev, (short)NON_MAC_QUEUE)))
3514 goto out;
3515
3516 if((err = smctr_issue_resume_rx_bdb_cmd(dev, (short)NON_MAC_QUEUE)))
3517 goto out;
3518
3519 tp->status = CLOSED;
3520
3521 /* Insert into the Ring or Enter Loopback Mode. */
3522 if((tp->mode_bits & LOOPING_MODE_MASK) == LOOPBACK_MODE_1)
3523 {
3524 tp->status = CLOSED;
3525
3526 if(!(err = smctr_issue_trc_loopback_cmd(dev)))
3527 {
3528 if(!(err = smctr_wait_cmd(dev)))
3529 tp->status = OPEN;
3530 }
3531
3532 smctr_status_chg(dev);
3533 }
3534 else
3535 {
3536 if((tp->mode_bits & LOOPING_MODE_MASK) == LOOPBACK_MODE_2)
3537 {
3538 tp->status = CLOSED;
3539 if(!(err = smctr_issue_tri_loopback_cmd(dev)))
3540 {
3541 if(!(err = smctr_wait_cmd(dev)))
3542 tp->status = OPEN;
3543 }
3544
3545 smctr_status_chg(dev);
3546 }
3547 else
3548 {
3549 if((tp->mode_bits & LOOPING_MODE_MASK)
3550 == LOOPBACK_MODE_3)
3551 {
3552 tp->status = CLOSED;
3553 if(!(err = smctr_lobe_media_test_cmd(dev)))
3554 {
3555 if(!(err = smctr_wait_cmd(dev)))
3556 tp->status = OPEN;
3557 }
3558 smctr_status_chg(dev);
3559 }
3560 else
3561 {
3562 if(!(err = smctr_lobe_media_test(dev)))
3563 err = smctr_issue_insert_cmd(dev);
3564 else
3565 {
3566 if(err == LOBE_MEDIA_TEST_FAILED)
3567 printk(KERN_WARNING "%s: Lobe Media Test Failure - Check cable?\n", dev->name);
3568 }
3569 }
3570 }
3571 }
3572
3573out:
3574 spin_unlock_irqrestore(&tp->lock, flags);
3575
3576 return (err);
3577}
3578
3579/* Check for a network adapter of this type,
3580 * and return device structure if one exists.
3581 */
3582struct net_device __init *smctr_probe(int unit)
3583{
3584 struct net_device *dev = alloc_trdev(sizeof(struct net_local));
3585 static const unsigned ports[] = {
3586 0x200, 0x220, 0x240, 0x260, 0x280, 0x2A0, 0x2C0, 0x2E0, 0x300,
3587 0x320, 0x340, 0x360, 0x380, 0
3588 };
3589 const unsigned *port;
3590 int err = 0;
3591
3592 if (!dev)
3593 return ERR_PTR(-ENOMEM);
3594
3595 SET_MODULE_OWNER(dev);
3596
3597 if (unit >= 0) {
3598 sprintf(dev->name, "tr%d", unit);
3599 netdev_boot_setup_check(dev);
3600 }
3601
3602 if (dev->base_addr > 0x1ff) /* Check a single specified location. */
3603 err = smctr_probe1(dev, dev->base_addr);
3604 else if(dev->base_addr != 0) /* Don't probe at all. */
3605 err =-ENXIO;
3606 else {
3607 for (port = ports; *port; port++) {
3608 err = smctr_probe1(dev, *port);
3609 if (!err)
3610 break;
3611 }
3612 }
3613 if (err)
3614 goto out;
3615 err = register_netdev(dev);
3616 if (err)
3617 goto out1;
3618 return dev;
3619out1:
3620#ifdef CONFIG_MCA_LEGACY
3621 { struct net_local *tp = netdev_priv(dev);
3622 if (tp->slot_num)
3623 mca_mark_as_unused(tp->slot_num);
3624 }
3625#endif
3626 release_region(dev->base_addr, SMCTR_IO_EXTENT);
3627 free_irq(dev->irq, dev);
3628out:
3629 free_netdev(dev);
3630 return ERR_PTR(err);
3631}
3632
3633
3634static int __init smctr_probe1(struct net_device *dev, int ioaddr)
3635{
3636 static unsigned version_printed;
3637 struct net_local *tp = netdev_priv(dev);
3638 int err;
3639 __u32 *ram;
3640
3641 if(smctr_debug && version_printed++ == 0)
3642 printk(version);
3643
3644 spin_lock_init(&tp->lock);
3645 dev->base_addr = ioaddr;
3646
3647 /* Actually detect an adapter now. */
3648 err = smctr_chk_isa(dev);
3649 if(err < 0)
3650 {
3651 if ((err = smctr_chk_mca(dev)) < 0) {
3652 err = -ENODEV;
3653 goto out;
3654 }
3655 }
3656
3657 tp = netdev_priv(dev);
3658 dev->mem_start = tp->ram_base;
3659 dev->mem_end = dev->mem_start + 0x10000;
3660 ram = (__u32 *)phys_to_virt(dev->mem_start);
3661 tp->ram_access = *(__u32 *)&ram;
3662 tp->status = NOT_INITIALIZED;
3663
3664 err = smctr_load_firmware(dev);
3665 if(err != UCODE_PRESENT && err != SUCCESS)
3666 {
3667 printk(KERN_ERR "%s: Firmware load failed (%d)\n", dev->name, err);
3668 err = -EIO;
3669 goto out;
3670 }
3671
3672 /* Allow user to specify ring speed on module insert. */
3673 if(ringspeed == 4)
3674 tp->media_type = MEDIA_UTP_4;
3675 else
3676 tp->media_type = MEDIA_UTP_16;
3677
3678 printk(KERN_INFO "%s: %s %s at Io %#4x, Irq %d, Rom %#4x, Ram %#4x.\n",
3679 dev->name, smctr_name, smctr_model,
3680 (unsigned int)dev->base_addr,
3681 dev->irq, tp->rom_base, tp->ram_base);
3682
3683 dev->open = smctr_open;
3684 dev->stop = smctr_close;
3685 dev->hard_start_xmit = smctr_send_packet;
3686 dev->tx_timeout = smctr_timeout;
3687 dev->watchdog_timeo = HZ;
3688 dev->get_stats = smctr_get_stats;
3689 dev->set_multicast_list = &smctr_set_multicast_list;
3690 return (0);
3691
3692out:
3693 return err;
3694}
3695
3696static int smctr_process_rx_packet(MAC_HEADER *rmf, __u16 size,
3697 struct net_device *dev, __u16 rx_status)
3698{
3699 struct net_local *tp = netdev_priv(dev);
3700 struct sk_buff *skb;
3701 __u16 rcode, correlator;
3702 int err = 0;
3703 __u8 xframe = 1;
3704 __u16 tx_fstatus;
3705
3706 rmf->vl = SWAP_BYTES(rmf->vl);
3707 if(rx_status & FCB_RX_STATUS_DA_MATCHED)
3708 {
3709 switch(rmf->vc)
3710 {
3711 /* Received MAC Frames Processed by RS. */
3712 case INIT:
3713 if((rcode = smctr_rcv_init(dev, rmf, &correlator)) == HARDWARE_FAILED)
3714 {
3715 return (rcode);
3716 }
3717
3718 if((err = smctr_send_rsp(dev, rmf, rcode,
3719 correlator)))
3720 {
3721 return (err);
3722 }
3723 break;
3724
3725 case CHG_PARM:
3726 if((rcode = smctr_rcv_chg_param(dev, rmf,
3727 &correlator)) ==HARDWARE_FAILED)
3728 {
3729 return (rcode);
3730 }
3731
3732 if((err = smctr_send_rsp(dev, rmf, rcode,
3733 correlator)))
3734 {
3735 return (err);
3736 }
3737 break;
3738
3739 case RQ_ADDR:
3740 if((rcode = smctr_rcv_rq_addr_state_attch(dev,
3741 rmf, &correlator)) != POSITIVE_ACK)
3742 {
3743 if(rcode == HARDWARE_FAILED)
3744 return (rcode);
3745 else
3746 return (smctr_send_rsp(dev, rmf,
3747 rcode, correlator));
3748 }
3749
3750 if((err = smctr_send_rpt_addr(dev, rmf,
3751 correlator)))
3752 {
3753 return (err);
3754 }
3755 break;
3756
3757 case RQ_ATTCH:
3758 if((rcode = smctr_rcv_rq_addr_state_attch(dev,
3759 rmf, &correlator)) != POSITIVE_ACK)
3760 {
3761 if(rcode == HARDWARE_FAILED)
3762 return (rcode);
3763 else
3764 return (smctr_send_rsp(dev, rmf,
3765 rcode,
3766 correlator));
3767 }
3768
3769 if((err = smctr_send_rpt_attch(dev, rmf,
3770 correlator)))
3771 {
3772 return (err);
3773 }
3774 break;
3775
3776 case RQ_STATE:
3777 if((rcode = smctr_rcv_rq_addr_state_attch(dev,
3778 rmf, &correlator)) != POSITIVE_ACK)
3779 {
3780 if(rcode == HARDWARE_FAILED)
3781 return (rcode);
3782 else
3783 return (smctr_send_rsp(dev, rmf,
3784 rcode,
3785 correlator));
3786 }
3787
3788 if((err = smctr_send_rpt_state(dev, rmf,
3789 correlator)))
3790 {
3791 return (err);
3792 }
3793 break;
3794
3795 case TX_FORWARD:
3796 if((rcode = smctr_rcv_tx_forward(dev, rmf))
3797 != POSITIVE_ACK)
3798 {
3799 if(rcode == HARDWARE_FAILED)
3800 return (rcode);
3801 else
3802 return (smctr_send_rsp(dev, rmf,
3803 rcode,
3804 correlator));
3805 }
3806
3807 if((err = smctr_send_tx_forward(dev, rmf,
3808 &tx_fstatus)) == HARDWARE_FAILED)
3809 {
3810 return (err);
3811 }
3812
3813 if(err == A_FRAME_WAS_FORWARDED)
3814 {
3815 if((err = smctr_send_rpt_tx_forward(dev,
3816 rmf, tx_fstatus))
3817 == HARDWARE_FAILED)
3818 {
3819 return (err);
3820 }
3821 }
3822 break;
3823
3824 /* Received MAC Frames Processed by CRS/REM/RPS. */
3825 case RSP:
3826 case RQ_INIT:
3827 case RPT_NEW_MON:
3828 case RPT_SUA_CHG:
3829 case RPT_ACTIVE_ERR:
3830 case RPT_NN_INCMP:
3831 case RPT_ERROR:
3832 case RPT_ATTCH:
3833 case RPT_STATE:
3834 case RPT_ADDR:
3835 break;
3836
3837 /* Rcvd Att. MAC Frame (if RXATMAC set) or UNKNOWN */
3838 default:
3839 xframe = 0;
3840 if(!(tp->receive_mask & ACCEPT_ATT_MAC_FRAMES))
3841 {
3842 rcode = smctr_rcv_unknown(dev, rmf,
3843 &correlator);
3844 if((err = smctr_send_rsp(dev, rmf,rcode,
3845 correlator)))
3846 {
3847 return (err);
3848 }
3849 }
3850
3851 break;
3852 }
3853 }
3854 else
3855 {
3856 /* 1. DA doesn't match (Promiscuous Mode).
3857 * 2. Parse for Extended MAC Frame Type.
3858 */
3859 switch(rmf->vc)
3860 {
3861 case RSP:
3862 case INIT:
3863 case RQ_INIT:
3864 case RQ_ADDR:
3865 case RQ_ATTCH:
3866 case RQ_STATE:
3867 case CHG_PARM:
3868 case RPT_ADDR:
3869 case RPT_ERROR:
3870 case RPT_ATTCH:
3871 case RPT_STATE:
3872 case RPT_NEW_MON:
3873 case RPT_SUA_CHG:
3874 case RPT_NN_INCMP:
3875 case RPT_ACTIVE_ERR:
3876 break;
3877
3878 default:
3879 xframe = 0;
3880 break;
3881 }
3882 }
3883
3884 /* NOTE: UNKNOWN MAC frames will NOT be passed up unless
3885 * ACCEPT_ATT_MAC_FRAMES is set.
3886 */
3887 if(((tp->receive_mask & ACCEPT_ATT_MAC_FRAMES)
3888 && (xframe == (__u8)0))
3889 || ((tp->receive_mask & ACCEPT_EXT_MAC_FRAMES)
3890 && (xframe == (__u8)1)))
3891 {
3892 rmf->vl = SWAP_BYTES(rmf->vl);
3893
3894 if (!(skb = dev_alloc_skb(size)))
3895 return -ENOMEM;
3896 skb->len = size;
3897
3898 /* Slide data into a sleek skb. */
3899 skb_put(skb, skb->len);
3900 memcpy(skb->data, rmf, skb->len);
3901
3902 /* Update Counters */
3903 tp->MacStat.rx_packets++;
3904 tp->MacStat.rx_bytes += skb->len;
3905
3906 /* Kick the packet on up. */
3907 skb->dev = dev;
3908 skb->protocol = tr_type_trans(skb, dev);
3909 netif_rx(skb);
3910 dev->last_rx = jiffies;
3911 err = 0;
3912 }
3913
3914 return (err);
3915}
3916
3917/* Adapter RAM test. Incremental word ODD boundary data test. */
3918static int smctr_ram_memory_test(struct net_device *dev)
3919{
3920 struct net_local *tp = netdev_priv(dev);
3921 __u16 page, pages_of_ram, start_pattern = 0, word_pattern = 0,
3922 word_read = 0, err_word = 0, err_pattern = 0;
3923 unsigned int err_offset;
3924 __u32 j, pword;
3925 __u8 err = 0;
3926
3927 if(smctr_debug > 10)
3928 printk(KERN_DEBUG "%s: smctr_ram_memory_test\n", dev->name);
3929
3930 start_pattern = 0x0001;
3931 pages_of_ram = tp->ram_size / tp->ram_usable;
3932 pword = tp->ram_access;
3933
3934 /* Incremental word ODD boundary test. */
3935 for(page = 0; (page < pages_of_ram) && (~err);
3936 page++, start_pattern += 0x8000)
3937 {
3938 smctr_set_page(dev, (__u8 *)(tp->ram_access
3939 + (page * tp->ram_usable * 1024) + 1));
3940 word_pattern = start_pattern;
3941
3942 for(j = 1; j < (__u32)(tp->ram_usable * 1024) - 1; j += 2)
3943 *(__u16 *)(pword + j) = word_pattern++;
3944
3945 word_pattern = start_pattern;
3946
3947 for(j = 1; j < (__u32)(tp->ram_usable * 1024) - 1
3948 && (~err); j += 2, word_pattern++)
3949 {
3950 word_read = *(__u16 *)(pword + j);
3951 if(word_read != word_pattern)
3952 {
3953 err = (__u8)1;
3954 err_offset = j;
3955 err_word = word_read;
3956 err_pattern = word_pattern;
3957 return (RAM_TEST_FAILED);
3958 }
3959 }
3960 }
3961
3962 /* Zero out memory. */
3963 for(page = 0; page < pages_of_ram && (~err); page++)
3964 {
3965 smctr_set_page(dev, (__u8 *)(tp->ram_access
3966 + (page * tp->ram_usable * 1024)));
3967 word_pattern = 0;
3968
3969 for(j = 0; j < (__u32)tp->ram_usable * 1024; j +=2)
3970 *(__u16 *)(pword + j) = word_pattern;
3971
3972 for(j =0; j < (__u32)tp->ram_usable * 1024
3973 && (~err); j += 2)
3974 {
3975 word_read = *(__u16 *)(pword + j);
3976 if(word_read != word_pattern)
3977 {
3978 err = (__u8)1;
3979 err_offset = j;
3980 err_word = word_read;
3981 err_pattern = word_pattern;
3982 return (RAM_TEST_FAILED);
3983 }
3984 }
3985 }
3986
3987 smctr_set_page(dev, (__u8 *)tp->ram_access);
3988
3989 return (0);
3990}
3991
3992static int smctr_rcv_chg_param(struct net_device *dev, MAC_HEADER *rmf,
3993 __u16 *correlator)
3994{
3995 MAC_SUB_VECTOR *rsv;
3996 signed short vlen;
3997 __u16 rcode = POSITIVE_ACK;
3998 unsigned int svectors = F_NO_SUB_VECTORS_FOUND;
3999
4000 /* This Frame can only come from a CRS */
4001 if((rmf->dc_sc & SC_MASK) != SC_CRS)
4002 return(E_INAPPROPRIATE_SOURCE_CLASS);
4003
4004 /* Remove MVID Length from total length. */
4005 vlen = (signed short)rmf->vl - 4;
4006
4007 /* Point to First SVID */
4008 rsv = (MAC_SUB_VECTOR *)((__u32)rmf + sizeof(MAC_HEADER));
4009
4010 /* Search for Appropriate SVID's. */
4011 while((vlen > 0) && (rcode == POSITIVE_ACK))
4012 {
4013 switch(rsv->svi)
4014 {
4015 case CORRELATOR:
4016 svectors |= F_CORRELATOR;
4017 rcode = smctr_set_corr(dev, rsv, correlator);
4018 break;
4019
4020 case LOCAL_RING_NUMBER:
4021 svectors |= F_LOCAL_RING_NUMBER;
4022 rcode = smctr_set_local_ring_num(dev, rsv);
4023 break;
4024
4025 case ASSIGN_PHYSICAL_DROP:
4026 svectors |= F_ASSIGN_PHYSICAL_DROP;
4027 rcode = smctr_set_phy_drop(dev, rsv);
4028 break;
4029
4030 case ERROR_TIMER_VALUE:
4031 svectors |= F_ERROR_TIMER_VALUE;
4032 rcode = smctr_set_error_timer_value(dev, rsv);
4033 break;
4034
4035 case AUTHORIZED_FUNCTION_CLASS:
4036 svectors |= F_AUTHORIZED_FUNCTION_CLASS;
4037 rcode = smctr_set_auth_funct_class(dev, rsv);
4038 break;
4039
4040 case AUTHORIZED_ACCESS_PRIORITY:
4041 svectors |= F_AUTHORIZED_ACCESS_PRIORITY;
4042 rcode = smctr_set_auth_access_pri(dev, rsv);
4043 break;
4044
4045 default:
4046 rcode = E_SUB_VECTOR_UNKNOWN;
4047 break;
4048 }
4049
4050 /* Let Sender Know if SUM of SV length's is
4051 * larger then length in MVID length field
4052 */
4053 if((vlen -= rsv->svl) < 0)
4054 rcode = E_VECTOR_LENGTH_ERROR;
4055
4056 rsv = (MAC_SUB_VECTOR *)((__u32)rsv + rsv->svl);
4057 }
4058
4059 if(rcode == POSITIVE_ACK)
4060 {
4061 /* Let Sender Know if MVID length field
4062 * is larger then SUM of SV length's
4063 */
4064 if(vlen != 0)
4065 rcode = E_VECTOR_LENGTH_ERROR;
4066 else
4067 {
4068 /* Let Sender Know if Expected SVID Missing */
4069 if((svectors & R_CHG_PARM) ^ R_CHG_PARM)
4070 rcode = E_MISSING_SUB_VECTOR;
4071 }
4072 }
4073
4074 return (rcode);
4075}
4076
4077static int smctr_rcv_init(struct net_device *dev, MAC_HEADER *rmf,
4078 __u16 *correlator)
4079{
4080 MAC_SUB_VECTOR *rsv;
4081 signed short vlen;
4082 __u16 rcode = POSITIVE_ACK;
4083 unsigned int svectors = F_NO_SUB_VECTORS_FOUND;
4084
4085 /* This Frame can only come from a RPS */
4086 if((rmf->dc_sc & SC_MASK) != SC_RPS)
4087 return (E_INAPPROPRIATE_SOURCE_CLASS);
4088
4089 /* Remove MVID Length from total length. */
4090 vlen = (signed short)rmf->vl - 4;
4091
4092 /* Point to First SVID */
4093 rsv = (MAC_SUB_VECTOR *)((__u32)rmf + sizeof(MAC_HEADER));
4094
4095 /* Search for Appropriate SVID's */
4096 while((vlen > 0) && (rcode == POSITIVE_ACK))
4097 {
4098 switch(rsv->svi)
4099 {
4100 case CORRELATOR:
4101 svectors |= F_CORRELATOR;
4102 rcode = smctr_set_corr(dev, rsv, correlator);
4103 break;
4104
4105 case LOCAL_RING_NUMBER:
4106 svectors |= F_LOCAL_RING_NUMBER;
4107 rcode = smctr_set_local_ring_num(dev, rsv);
4108 break;
4109
4110 case ASSIGN_PHYSICAL_DROP:
4111 svectors |= F_ASSIGN_PHYSICAL_DROP;
4112 rcode = smctr_set_phy_drop(dev, rsv);
4113 break;
4114
4115 case ERROR_TIMER_VALUE:
4116 svectors |= F_ERROR_TIMER_VALUE;
4117 rcode = smctr_set_error_timer_value(dev, rsv);
4118 break;
4119
4120 default:
4121 rcode = E_SUB_VECTOR_UNKNOWN;
4122 break;
4123 }
4124
4125 /* Let Sender Know if SUM of SV length's is
4126 * larger then length in MVID length field
4127 */
4128 if((vlen -= rsv->svl) < 0)
4129 rcode = E_VECTOR_LENGTH_ERROR;
4130
4131 rsv = (MAC_SUB_VECTOR *)((__u32)rsv + rsv->svl);
4132 }
4133
4134 if(rcode == POSITIVE_ACK)
4135 {
4136 /* Let Sender Know if MVID length field
4137 * is larger then SUM of SV length's
4138 */
4139 if(vlen != 0)
4140 rcode = E_VECTOR_LENGTH_ERROR;
4141 else
4142 {
4143 /* Let Sender Know if Expected SV Missing */
4144 if((svectors & R_INIT) ^ R_INIT)
4145 rcode = E_MISSING_SUB_VECTOR;
4146 }
4147 }
4148
4149 return (rcode);
4150}
4151
4152static int smctr_rcv_tx_forward(struct net_device *dev, MAC_HEADER *rmf)
4153{
4154 MAC_SUB_VECTOR *rsv;
4155 signed short vlen;
4156 __u16 rcode = POSITIVE_ACK;
4157 unsigned int svectors = F_NO_SUB_VECTORS_FOUND;
4158
4159 /* This Frame can only come from a CRS */
4160 if((rmf->dc_sc & SC_MASK) != SC_CRS)
4161 return (E_INAPPROPRIATE_SOURCE_CLASS);
4162
4163 /* Remove MVID Length from total length */
4164 vlen = (signed short)rmf->vl - 4;
4165
4166 /* Point to First SVID */
4167 rsv = (MAC_SUB_VECTOR *)((__u32)rmf + sizeof(MAC_HEADER));
4168
4169 /* Search for Appropriate SVID's */
4170 while((vlen > 0) && (rcode == POSITIVE_ACK))
4171 {
4172 switch(rsv->svi)
4173 {
4174 case FRAME_FORWARD:
4175 svectors |= F_FRAME_FORWARD;
4176 rcode = smctr_set_frame_forward(dev, rsv,
4177 rmf->dc_sc);
4178 break;
4179
4180 default:
4181 rcode = E_SUB_VECTOR_UNKNOWN;
4182 break;
4183 }
4184
4185 /* Let Sender Know if SUM of SV length's is
4186 * larger then length in MVID length field
4187 */
4188 if((vlen -= rsv->svl) < 0)
4189 rcode = E_VECTOR_LENGTH_ERROR;
4190
4191 rsv = (MAC_SUB_VECTOR *)((__u32)rsv + rsv->svl);
4192 }
4193
4194 if(rcode == POSITIVE_ACK)
4195 {
4196 /* Let Sender Know if MVID length field
4197 * is larger then SUM of SV length's
4198 */
4199 if(vlen != 0)
4200 rcode = E_VECTOR_LENGTH_ERROR;
4201 else
4202 {
4203 /* Let Sender Know if Expected SV Missing */
4204 if((svectors & R_TX_FORWARD) ^ R_TX_FORWARD)
4205 rcode = E_MISSING_SUB_VECTOR;
4206 }
4207 }
4208
4209 return (rcode);
4210}
4211
4212static int smctr_rcv_rq_addr_state_attch(struct net_device *dev,
4213 MAC_HEADER *rmf, __u16 *correlator)
4214{
4215 MAC_SUB_VECTOR *rsv;
4216 signed short vlen;
4217 __u16 rcode = POSITIVE_ACK;
4218 unsigned int svectors = F_NO_SUB_VECTORS_FOUND;
4219
4220 /* Remove MVID Length from total length */
4221 vlen = (signed short)rmf->vl - 4;
4222
4223 /* Point to First SVID */
4224 rsv = (MAC_SUB_VECTOR *)((__u32)rmf + sizeof(MAC_HEADER));
4225
4226 /* Search for Appropriate SVID's */
4227 while((vlen > 0) && (rcode == POSITIVE_ACK))
4228 {
4229 switch(rsv->svi)
4230 {
4231 case CORRELATOR:
4232 svectors |= F_CORRELATOR;
4233 rcode = smctr_set_corr(dev, rsv, correlator);
4234 break;
4235
4236 default:
4237 rcode = E_SUB_VECTOR_UNKNOWN;
4238 break;
4239 }
4240
4241 /* Let Sender Know if SUM of SV length's is
4242 * larger then length in MVID length field
4243 */
4244 if((vlen -= rsv->svl) < 0)
4245 rcode = E_VECTOR_LENGTH_ERROR;
4246
4247 rsv = (MAC_SUB_VECTOR *)((__u32)rsv + rsv->svl);
4248 }
4249
4250 if(rcode == POSITIVE_ACK)
4251 {
4252 /* Let Sender Know if MVID length field
4253 * is larger then SUM of SV length's
4254 */
4255 if(vlen != 0)
4256 rcode = E_VECTOR_LENGTH_ERROR;
4257 else
4258 {
4259 /* Let Sender Know if Expected SVID Missing */
4260 if((svectors & R_RQ_ATTCH_STATE_ADDR)
4261 ^ R_RQ_ATTCH_STATE_ADDR)
4262 rcode = E_MISSING_SUB_VECTOR;
4263 }
4264 }
4265
4266 return (rcode);
4267}
4268
4269static int smctr_rcv_unknown(struct net_device *dev, MAC_HEADER *rmf,
4270 __u16 *correlator)
4271{
4272 MAC_SUB_VECTOR *rsv;
4273 signed short vlen;
4274
4275 *correlator = 0;
4276
4277 /* Remove MVID Length from total length */
4278 vlen = (signed short)rmf->vl - 4;
4279
4280 /* Point to First SVID */
4281 rsv = (MAC_SUB_VECTOR *)((__u32)rmf + sizeof(MAC_HEADER));
4282
4283 /* Search for CORRELATOR for RSP to UNKNOWN */
4284 while((vlen > 0) && (*correlator == 0))
4285 {
4286 switch(rsv->svi)
4287 {
4288 case CORRELATOR:
4289 smctr_set_corr(dev, rsv, correlator);
4290 break;
4291
4292 default:
4293 break;
4294 }
4295
4296 vlen -= rsv->svl;
4297 rsv = (MAC_SUB_VECTOR *)((__u32)rsv + rsv->svl);
4298 }
4299
4300 return (E_UNRECOGNIZED_VECTOR_ID);
4301}
4302
4303/*
4304 * Reset the 825 NIC and exit w:
4305 * 1. The NIC reset cleared (non-reset state), halted and un-initialized.
4306 * 2. TINT masked.
4307 * 3. CBUSY masked.
4308 * 4. TINT clear.
4309 * 5. CBUSY clear.
4310 */
4311static int smctr_reset_adapter(struct net_device *dev)
4312{
4313 struct net_local *tp = netdev_priv(dev);
4314 int ioaddr = dev->base_addr;
4315
4316 /* Reseting the NIC will put it in a halted and un-initialized state. */ smctr_set_trc_reset(ioaddr);
4317 mdelay(200); /* ~2 ms */
4318
4319 smctr_clear_trc_reset(ioaddr);
4320 mdelay(200); /* ~2 ms */
4321
4322 /* Remove any latched interrupts that occurred prior to reseting the
4323 * adapter or possibily caused by line glitches due to the reset.
4324 */
4325 outb(tp->trc_mask | CSR_CLRTINT | CSR_CLRCBUSY, ioaddr + CSR);
4326
4327 return (0);
4328}
4329
4330static int smctr_restart_tx_chain(struct net_device *dev, short queue)
4331{
4332 struct net_local *tp = netdev_priv(dev);
4333 int err = 0;
4334
4335 if(smctr_debug > 10)
4336 printk(KERN_DEBUG "%s: smctr_restart_tx_chain\n", dev->name);
4337
4338 if(tp->num_tx_fcbs_used[queue] != 0
4339 && tp->tx_queue_status[queue] == NOT_TRANSMITING)
4340 {
4341 tp->tx_queue_status[queue] = TRANSMITING;
4342 err = smctr_issue_resume_tx_fcb_cmd(dev, queue);
4343 }
4344
4345 return (err);
4346}
4347
4348static int smctr_ring_status_chg(struct net_device *dev)
4349{
4350 struct net_local *tp = netdev_priv(dev);
4351
4352 if(smctr_debug > 10)
4353 printk(KERN_DEBUG "%s: smctr_ring_status_chg\n", dev->name);
4354
4355 /* Check for ring_status_flag: whenever MONITOR_STATE_BIT
4356 * Bit is set, check value of monitor_state, only then we
4357 * enable and start transmit/receive timeout (if and only
4358 * if it is MS_ACTIVE_MONITOR_STATE or MS_STANDBY_MONITOR_STATE)
4359 */
4360 if(tp->ring_status_flags == MONITOR_STATE_CHANGED)
4361 {
4362 if((tp->monitor_state == MS_ACTIVE_MONITOR_STATE)
4363 || (tp->monitor_state == MS_STANDBY_MONITOR_STATE))
4364 {
4365 tp->monitor_state_ready = 1;
4366 }
4367 else
4368 {
4369 /* if adapter is NOT in either active monitor
4370 * or standby monitor state => Disable
4371 * transmit/receive timeout.
4372 */
4373 tp->monitor_state_ready = 0;
4374
4375 /* Ring speed problem, switching to auto mode. */
4376 if(tp->monitor_state == MS_MONITOR_FSM_INACTIVE
4377 && !tp->cleanup)
4378 {
4379 printk(KERN_INFO "%s: Incorrect ring speed switching.\n",
4380 dev->name);
4381 smctr_set_ring_speed(dev);
4382 }
4383 }
4384 }
4385
4386 if(!(tp->ring_status_flags & RING_STATUS_CHANGED))
4387 return (0);
4388
4389 switch(tp->ring_status)
4390 {
4391 case RING_RECOVERY:
4392 printk(KERN_INFO "%s: Ring Recovery\n", dev->name);
4393 tp->current_ring_status |= RING_RECOVERY;
4394 break;
4395
4396 case SINGLE_STATION:
4397 printk(KERN_INFO "%s: Single Statinon\n", dev->name);
4398 tp->current_ring_status |= SINGLE_STATION;
4399 break;
4400
4401 case COUNTER_OVERFLOW:
4402 printk(KERN_INFO "%s: Counter Overflow\n", dev->name);
4403 tp->current_ring_status |= COUNTER_OVERFLOW;
4404 break;
4405
4406 case REMOVE_RECEIVED:
4407 printk(KERN_INFO "%s: Remove Received\n", dev->name);
4408 tp->current_ring_status |= REMOVE_RECEIVED;
4409 break;
4410
4411 case AUTO_REMOVAL_ERROR:
4412 printk(KERN_INFO "%s: Auto Remove Error\n", dev->name);
4413 tp->current_ring_status |= AUTO_REMOVAL_ERROR;
4414 break;
4415
4416 case LOBE_WIRE_FAULT:
4417 printk(KERN_INFO "%s: Lobe Wire Fault\n", dev->name);
4418 tp->current_ring_status |= LOBE_WIRE_FAULT;
4419 break;
4420
4421 case TRANSMIT_BEACON:
4422 printk(KERN_INFO "%s: Transmit Beacon\n", dev->name);
4423 tp->current_ring_status |= TRANSMIT_BEACON;
4424 break;
4425
4426 case SOFT_ERROR:
4427 printk(KERN_INFO "%s: Soft Error\n", dev->name);
4428 tp->current_ring_status |= SOFT_ERROR;
4429 break;
4430
4431 case HARD_ERROR:
4432 printk(KERN_INFO "%s: Hard Error\n", dev->name);
4433 tp->current_ring_status |= HARD_ERROR;
4434 break;
4435
4436 case SIGNAL_LOSS:
4437 printk(KERN_INFO "%s: Signal Loss\n", dev->name);
4438 tp->current_ring_status |= SIGNAL_LOSS;
4439 break;
4440
4441 default:
4442 printk(KERN_INFO "%s: Unknown ring status change\n",
4443 dev->name);
4444 break;
4445 }
4446
4447 return (0);
4448}
4449
4450static int smctr_rx_frame(struct net_device *dev)
4451{
4452 struct net_local *tp = netdev_priv(dev);
4453 __u16 queue, status, rx_size, err = 0;
4454 __u8 *pbuff;
4455
4456 if(smctr_debug > 10)
4457 printk(KERN_DEBUG "%s: smctr_rx_frame\n", dev->name);
4458
4459 queue = tp->receive_queue_number;
4460
4461 while((status = tp->rx_fcb_curr[queue]->frame_status) != SUCCESS)
4462 {
4463 err = HARDWARE_FAILED;
4464
4465 if(((status & 0x007f) == 0)
4466 || ((tp->receive_mask & ACCEPT_ERR_PACKETS) != 0))
4467 {
4468 /* frame length less the CRC (4 bytes) + FS (1 byte) */
4469 rx_size = tp->rx_fcb_curr[queue]->frame_length - 5;
4470
4471 pbuff = smctr_get_rx_pointer(dev, queue);
4472
4473 smctr_set_page(dev, pbuff);
4474 smctr_disable_16bit(dev);
4475
4476 /* pbuff points to addr within one page */
4477 pbuff = (__u8 *)PAGE_POINTER(pbuff);
4478
4479 if(queue == NON_MAC_QUEUE)
4480 {
4481 struct sk_buff *skb;
4482
4483 skb = dev_alloc_skb(rx_size);
4484 if (skb) {
4485 skb_put(skb, rx_size);
4486
4487 memcpy(skb->data, pbuff, rx_size);
4488
4489 /* Update Counters */
4490 tp->MacStat.rx_packets++;
4491 tp->MacStat.rx_bytes += skb->len;
4492
4493 /* Kick the packet on up. */
4494 skb->dev = dev;
4495 skb->protocol = tr_type_trans(skb, dev);
4496 netif_rx(skb);
4497 dev->last_rx = jiffies;
4498 } else {
4499 }
4500 }
4501 else
4502 smctr_process_rx_packet((MAC_HEADER *)pbuff,
4503 rx_size, dev, status);
4504 }
4505
4506 smctr_enable_16bit(dev);
4507 smctr_set_page(dev, (__u8 *)tp->ram_access);
4508 smctr_update_rx_chain(dev, queue);
4509
4510 if(err != SUCCESS)
4511 break;
4512 }
4513
4514 return (err);
4515}
4516
4517static int smctr_send_dat(struct net_device *dev)
4518{
4519 struct net_local *tp = netdev_priv(dev);
4520 unsigned int i, err;
4521 MAC_HEADER *tmf;
4522 FCBlock *fcb;
4523
4524 if(smctr_debug > 10)
4525 printk(KERN_DEBUG "%s: smctr_send_dat\n", dev->name);
4526
4527 if((fcb = smctr_get_tx_fcb(dev, MAC_QUEUE,
4528 sizeof(MAC_HEADER))) == (FCBlock *)(-1L))
4529 {
4530 return (OUT_OF_RESOURCES);
4531 }
4532
4533 /* Initialize DAT Data Fields. */
4534 tmf = (MAC_HEADER *)fcb->bdb_ptr->data_block_ptr;
4535 tmf->ac = MSB(AC_FC_DAT);
4536 tmf->fc = LSB(AC_FC_DAT);
4537
4538 for(i = 0; i < 6; i++)
4539 {
4540 tmf->sa[i] = dev->dev_addr[i];
4541 tmf->da[i] = dev->dev_addr[i];
4542
4543 }
4544
4545 tmf->vc = DAT;
4546 tmf->dc_sc = DC_RS | SC_RS;
4547 tmf->vl = 4;
4548 tmf->vl = SWAP_BYTES(tmf->vl);
4549
4550 /* Start Transmit. */
4551 if((err = smctr_trc_send_packet(dev, fcb, MAC_QUEUE)))
4552 return (err);
4553
4554 /* Wait for Transmit to Complete */
4555 for(i = 0; i < 10000; i++)
4556 {
4557 if(fcb->frame_status & FCB_COMMAND_DONE)
4558 break;
4559 mdelay(1);
4560 }
4561
4562 /* Check if GOOD frame Tx'ed. */
4563 if(!(fcb->frame_status & FCB_COMMAND_DONE)
4564 || fcb->frame_status & (FCB_TX_STATUS_E | FCB_TX_AC_BITS))
4565 {
4566 return (INITIALIZE_FAILED);
4567 }
4568
4569 /* De-allocated Tx FCB and Frame Buffer
4570 * The FCB must be de-allocated manually if executing with
4571 * interrupts disabled, other wise the ISR (LM_Service_Events)
4572 * will de-allocate it when the interrupt occurs.
4573 */
4574 tp->tx_queue_status[MAC_QUEUE] = NOT_TRANSMITING;
4575 smctr_update_tx_chain(dev, fcb, MAC_QUEUE);
4576
4577 return (0);
4578}
4579
4580static void smctr_timeout(struct net_device *dev)
4581{
4582 /*
4583 * If we get here, some higher level has decided we are broken.
4584 * There should really be a "kick me" function call instead.
4585 *
4586 * Resetting the token ring adapter takes a long time so just
4587 * fake transmission time and go on trying. Our own timeout
4588 * routine is in sktr_timer_chk()
4589 */
4590 dev->trans_start = jiffies;
4591 netif_wake_queue(dev);
4592}
4593
4594/*
4595 * Gets skb from system, queues it and checks if it can be sent
4596 */
4597static int smctr_send_packet(struct sk_buff *skb, struct net_device *dev)
4598{
4599 struct net_local *tp = netdev_priv(dev);
4600
4601 if(smctr_debug > 10)
4602 printk(KERN_DEBUG "%s: smctr_send_packet\n", dev->name);
4603
4604 /*
4605 * Block a transmit overlap
4606 */
4607
4608 netif_stop_queue(dev);
4609
4610 if(tp->QueueSkb == 0)
4611 return (1); /* Return with tbusy set: queue full */
4612
4613 tp->QueueSkb--;
4614 skb_queue_tail(&tp->SendSkbQueue, skb);
4615 smctr_hardware_send_packet(dev, tp);
4616 if(tp->QueueSkb > 0)
4617 netif_wake_queue(dev);
4618
4619 return (0);
4620}
4621
4622static int smctr_send_lobe_media_test(struct net_device *dev)
4623{
4624 struct net_local *tp = netdev_priv(dev);
4625 MAC_SUB_VECTOR *tsv;
4626 MAC_HEADER *tmf;
4627 FCBlock *fcb;
4628 __u32 i;
4629 int err;
4630
4631 if(smctr_debug > 15)
4632 printk(KERN_DEBUG "%s: smctr_send_lobe_media_test\n", dev->name);
4633
4634 if((fcb = smctr_get_tx_fcb(dev, MAC_QUEUE, sizeof(struct trh_hdr)
4635 + S_WRAP_DATA + S_WRAP_DATA)) == (FCBlock *)(-1L))
4636 {
4637 return (OUT_OF_RESOURCES);
4638 }
4639
4640 /* Initialize DAT Data Fields. */
4641 tmf = (MAC_HEADER *)fcb->bdb_ptr->data_block_ptr;
4642 tmf->ac = MSB(AC_FC_LOBE_MEDIA_TEST);
4643 tmf->fc = LSB(AC_FC_LOBE_MEDIA_TEST);
4644
4645 for(i = 0; i < 6; i++)
4646 {
4647 tmf->da[i] = 0;
4648 tmf->sa[i] = dev->dev_addr[i];
4649 }
4650
4651 tmf->vc = LOBE_MEDIA_TEST;
4652 tmf->dc_sc = DC_RS | SC_RS;
4653 tmf->vl = 4;
4654
4655 tsv = (MAC_SUB_VECTOR *)((__u32)tmf + sizeof(MAC_HEADER));
4656 smctr_make_wrap_data(dev, tsv);
4657 tmf->vl += tsv->svl;
4658
4659 tsv = (MAC_SUB_VECTOR *)((__u32)tsv + tsv->svl);
4660 smctr_make_wrap_data(dev, tsv);
4661 tmf->vl += tsv->svl;
4662
4663 /* Start Transmit. */
4664 tmf->vl = SWAP_BYTES(tmf->vl);
4665 if((err = smctr_trc_send_packet(dev, fcb, MAC_QUEUE)))
4666 return (err);
4667
4668 /* Wait for Transmit to Complete. (10 ms). */
4669 for(i=0; i < 10000; i++)
4670 {
4671 if(fcb->frame_status & FCB_COMMAND_DONE)
4672 break;
4673 mdelay(1);
4674 }
4675
4676 /* Check if GOOD frame Tx'ed */
4677 if(!(fcb->frame_status & FCB_COMMAND_DONE)
4678 || fcb->frame_status & (FCB_TX_STATUS_E | FCB_TX_AC_BITS))
4679 {
4680 return (LOBE_MEDIA_TEST_FAILED);
4681 }
4682
4683 /* De-allocated Tx FCB and Frame Buffer
4684 * The FCB must be de-allocated manually if executing with
4685 * interrupts disabled, other wise the ISR (LM_Service_Events)
4686 * will de-allocate it when the interrupt occurs.
4687 */
4688 tp->tx_queue_status[MAC_QUEUE] = NOT_TRANSMITING;
4689 smctr_update_tx_chain(dev, fcb, MAC_QUEUE);
4690
4691 return (0);
4692}
4693
4694static int smctr_send_rpt_addr(struct net_device *dev, MAC_HEADER *rmf,
4695 __u16 correlator)
4696{
4697 MAC_HEADER *tmf;
4698 MAC_SUB_VECTOR *tsv;
4699 FCBlock *fcb;
4700
4701 if((fcb = smctr_get_tx_fcb(dev, MAC_QUEUE, sizeof(MAC_HEADER)
4702 + S_CORRELATOR + S_PHYSICAL_DROP + S_UPSTREAM_NEIGHBOR_ADDRESS
4703 + S_ADDRESS_MODIFER + S_GROUP_ADDRESS + S_FUNCTIONAL_ADDRESS))
4704 == (FCBlock *)(-1L))
4705 {
4706 return (0);
4707 }
4708
4709 tmf = (MAC_HEADER *)fcb->bdb_ptr->data_block_ptr;
4710 tmf->vc = RPT_ADDR;
4711 tmf->dc_sc = (rmf->dc_sc & SC_MASK) << 4;
4712 tmf->vl = 4;
4713
4714 smctr_make_8025_hdr(dev, rmf, tmf, AC_FC_RPT_ADDR);
4715
4716 tsv = (MAC_SUB_VECTOR *)((__u32)tmf + sizeof(MAC_HEADER));
4717 smctr_make_corr(dev, tsv, correlator);
4718
4719 tmf->vl += tsv->svl;
4720 tsv = (MAC_SUB_VECTOR *)((__u32)tsv + tsv->svl);
4721 smctr_make_phy_drop_num(dev, tsv);
4722
4723 tmf->vl += tsv->svl;
4724 tsv = (MAC_SUB_VECTOR *)((__u32)tsv + tsv->svl);
4725 smctr_make_upstream_neighbor_addr(dev, tsv);
4726
4727 tmf->vl += tsv->svl;
4728 tsv = (MAC_SUB_VECTOR *)((__u32)tsv + tsv->svl);
4729 smctr_make_addr_mod(dev, tsv);
4730
4731 tmf->vl += tsv->svl;
4732 tsv = (MAC_SUB_VECTOR *)((__u32)tsv + tsv->svl);
4733 smctr_make_group_addr(dev, tsv);
4734
4735 tmf->vl += tsv->svl;
4736 tsv = (MAC_SUB_VECTOR *)((__u32)tsv + tsv->svl);
4737 smctr_make_funct_addr(dev, tsv);
4738
4739 tmf->vl += tsv->svl;
4740
4741 /* Subtract out MVID and MVL which is
4742 * include in both vl and MAC_HEADER
4743 */
4744/* fcb->frame_length = tmf->vl + sizeof(MAC_HEADER) - 4;
4745 fcb->bdb_ptr->buffer_length = tmf->vl + sizeof(MAC_HEADER) - 4;
4746*/
4747 tmf->vl = SWAP_BYTES(tmf->vl);
4748
4749 return (smctr_trc_send_packet(dev, fcb, MAC_QUEUE));
4750}
4751
4752static int smctr_send_rpt_attch(struct net_device *dev, MAC_HEADER *rmf,
4753 __u16 correlator)
4754{
4755 MAC_HEADER *tmf;
4756 MAC_SUB_VECTOR *tsv;
4757 FCBlock *fcb;
4758
4759 if((fcb = smctr_get_tx_fcb(dev, MAC_QUEUE, sizeof(MAC_HEADER)
4760 + S_CORRELATOR + S_PRODUCT_INSTANCE_ID + S_FUNCTIONAL_ADDRESS
4761 + S_AUTHORIZED_FUNCTION_CLASS + S_AUTHORIZED_ACCESS_PRIORITY))
4762 == (FCBlock *)(-1L))
4763 {
4764 return (0);
4765 }
4766
4767 tmf = (MAC_HEADER *)fcb->bdb_ptr->data_block_ptr;
4768 tmf->vc = RPT_ATTCH;
4769 tmf->dc_sc = (rmf->dc_sc & SC_MASK) << 4;
4770 tmf->vl = 4;
4771
4772 smctr_make_8025_hdr(dev, rmf, tmf, AC_FC_RPT_ATTCH);
4773
4774 tsv = (MAC_SUB_VECTOR *)((__u32)tmf + sizeof(MAC_HEADER));
4775 smctr_make_corr(dev, tsv, correlator);
4776
4777 tmf->vl += tsv->svl;
4778 tsv = (MAC_SUB_VECTOR *)((__u32)tsv + tsv->svl);
4779 smctr_make_product_id(dev, tsv);
4780
4781 tmf->vl += tsv->svl;
4782 tsv = (MAC_SUB_VECTOR *)((__u32)tsv + tsv->svl);
4783 smctr_make_funct_addr(dev, tsv);
4784
4785 tmf->vl += tsv->svl;
4786 tsv = (MAC_SUB_VECTOR *)((__u32)tsv + tsv->svl);
4787 smctr_make_auth_funct_class(dev, tsv);
4788
4789 tmf->vl += tsv->svl;
4790 tsv = (MAC_SUB_VECTOR *)((__u32)tsv + tsv->svl);
4791 smctr_make_access_pri(dev, tsv);
4792
4793 tmf->vl += tsv->svl;
4794
4795 /* Subtract out MVID and MVL which is
4796 * include in both vl and MAC_HEADER
4797 */
4798/* fcb->frame_length = tmf->vl + sizeof(MAC_HEADER) - 4;
4799 fcb->bdb_ptr->buffer_length = tmf->vl + sizeof(MAC_HEADER) - 4;
4800*/
4801 tmf->vl = SWAP_BYTES(tmf->vl);
4802
4803 return (smctr_trc_send_packet(dev, fcb, MAC_QUEUE));
4804}
4805
4806static int smctr_send_rpt_state(struct net_device *dev, MAC_HEADER *rmf,
4807 __u16 correlator)
4808{
4809 MAC_HEADER *tmf;
4810 MAC_SUB_VECTOR *tsv;
4811 FCBlock *fcb;
4812
4813 if((fcb = smctr_get_tx_fcb(dev, MAC_QUEUE, sizeof(MAC_HEADER)
4814 + S_CORRELATOR + S_RING_STATION_VERSION_NUMBER
4815 + S_RING_STATION_STATUS + S_STATION_IDENTIFER))
4816 == (FCBlock *)(-1L))
4817 {
4818 return (0);
4819 }
4820
4821 tmf = (MAC_HEADER *)fcb->bdb_ptr->data_block_ptr;
4822 tmf->vc = RPT_STATE;
4823 tmf->dc_sc = (rmf->dc_sc & SC_MASK) << 4;
4824 tmf->vl = 4;
4825
4826 smctr_make_8025_hdr(dev, rmf, tmf, AC_FC_RPT_STATE);
4827
4828 tsv = (MAC_SUB_VECTOR *)((__u32)tmf + sizeof(MAC_HEADER));
4829 smctr_make_corr(dev, tsv, correlator);
4830
4831 tmf->vl += tsv->svl;
4832 tsv = (MAC_SUB_VECTOR *)((__u32)tsv + tsv->svl);
4833 smctr_make_ring_station_version(dev, tsv);
4834
4835 tmf->vl += tsv->svl;
4836 tsv = (MAC_SUB_VECTOR *)((__u32)tsv + tsv->svl);
4837 smctr_make_ring_station_status(dev, tsv);
4838
4839 tmf->vl += tsv->svl;
4840 tsv = (MAC_SUB_VECTOR *)((__u32)tsv + tsv->svl);
4841 smctr_make_station_id(dev, tsv);
4842
4843 tmf->vl += tsv->svl;
4844
4845 /* Subtract out MVID and MVL which is
4846 * include in both vl and MAC_HEADER
4847 */
4848/* fcb->frame_length = tmf->vl + sizeof(MAC_HEADER) - 4;
4849 fcb->bdb_ptr->buffer_length = tmf->vl + sizeof(MAC_HEADER) - 4;
4850*/
4851 tmf->vl = SWAP_BYTES(tmf->vl);
4852
4853 return (smctr_trc_send_packet(dev, fcb, MAC_QUEUE));
4854}
4855
4856static int smctr_send_rpt_tx_forward(struct net_device *dev,
4857 MAC_HEADER *rmf, __u16 tx_fstatus)
4858{
4859 MAC_HEADER *tmf;
4860 MAC_SUB_VECTOR *tsv;
4861 FCBlock *fcb;
4862
4863 if((fcb = smctr_get_tx_fcb(dev, MAC_QUEUE, sizeof(MAC_HEADER)
4864 + S_TRANSMIT_STATUS_CODE)) == (FCBlock *)(-1L))
4865 {
4866 return (0);
4867 }
4868
4869 tmf = (MAC_HEADER *)fcb->bdb_ptr->data_block_ptr;
4870 tmf->vc = RPT_TX_FORWARD;
4871 tmf->dc_sc = (rmf->dc_sc & SC_MASK) << 4;
4872 tmf->vl = 4;
4873
4874 smctr_make_8025_hdr(dev, rmf, tmf, AC_FC_RPT_TX_FORWARD);
4875
4876 tsv = (MAC_SUB_VECTOR *)((__u32)tmf + sizeof(MAC_HEADER));
4877 smctr_make_tx_status_code(dev, tsv, tx_fstatus);
4878
4879 tmf->vl += tsv->svl;
4880
4881 /* Subtract out MVID and MVL which is
4882 * include in both vl and MAC_HEADER
4883 */
4884/* fcb->frame_length = tmf->vl + sizeof(MAC_HEADER) - 4;
4885 fcb->bdb_ptr->buffer_length = tmf->vl + sizeof(MAC_HEADER) - 4;
4886*/
4887 tmf->vl = SWAP_BYTES(tmf->vl);
4888
4889 return(smctr_trc_send_packet(dev, fcb, MAC_QUEUE));
4890}
4891
4892static int smctr_send_rsp(struct net_device *dev, MAC_HEADER *rmf,
4893 __u16 rcode, __u16 correlator)
4894{
4895 MAC_HEADER *tmf;
4896 MAC_SUB_VECTOR *tsv;
4897 FCBlock *fcb;
4898
4899 if((fcb = smctr_get_tx_fcb(dev, MAC_QUEUE, sizeof(MAC_HEADER)
4900 + S_CORRELATOR + S_RESPONSE_CODE)) == (FCBlock *)(-1L))
4901 {
4902 return (0);
4903 }
4904
4905 tmf = (MAC_HEADER *)fcb->bdb_ptr->data_block_ptr;
4906 tmf->vc = RSP;
4907 tmf->dc_sc = (rmf->dc_sc & SC_MASK) << 4;
4908 tmf->vl = 4;
4909
4910 smctr_make_8025_hdr(dev, rmf, tmf, AC_FC_RSP);
4911
4912 tsv = (MAC_SUB_VECTOR *)((__u32)tmf + sizeof(MAC_HEADER));
4913 smctr_make_corr(dev, tsv, correlator);
4914
4915 return (0);
4916}
4917
4918static int smctr_send_rq_init(struct net_device *dev)
4919{
4920 struct net_local *tp = netdev_priv(dev);
4921 MAC_HEADER *tmf;
4922 MAC_SUB_VECTOR *tsv;
4923 FCBlock *fcb;
4924 unsigned int i, count = 0;
4925 __u16 fstatus;
4926 int err;
4927
4928 do {
4929 if(((fcb = smctr_get_tx_fcb(dev, MAC_QUEUE, sizeof(MAC_HEADER)
4930 + S_PRODUCT_INSTANCE_ID + S_UPSTREAM_NEIGHBOR_ADDRESS
4931 + S_RING_STATION_VERSION_NUMBER + S_ADDRESS_MODIFER))
4932 == (FCBlock *)(-1L)))
4933 {
4934 return (0);
4935 }
4936
4937 tmf = (MAC_HEADER *)fcb->bdb_ptr->data_block_ptr;
4938 tmf->vc = RQ_INIT;
4939 tmf->dc_sc = DC_RPS | SC_RS;
4940 tmf->vl = 4;
4941
4942 smctr_make_8025_hdr(dev, NULL, tmf, AC_FC_RQ_INIT);
4943
4944 tsv = (MAC_SUB_VECTOR *)((__u32)tmf + sizeof(MAC_HEADER));
4945 smctr_make_product_id(dev, tsv);
4946
4947 tmf->vl += tsv->svl;
4948 tsv = (MAC_SUB_VECTOR *)((__u32)tsv + tsv->svl);
4949 smctr_make_upstream_neighbor_addr(dev, tsv);
4950
4951 tmf->vl += tsv->svl;
4952 tsv = (MAC_SUB_VECTOR *)((__u32)tsv + tsv->svl);
4953 smctr_make_ring_station_version(dev, tsv);
4954
4955 tmf->vl += tsv->svl;
4956 tsv = (MAC_SUB_VECTOR *)((__u32)tsv + tsv->svl);
4957 smctr_make_addr_mod(dev, tsv);
4958
4959 tmf->vl += tsv->svl;
4960
4961 /* Subtract out MVID and MVL which is
4962 * include in both vl and MAC_HEADER
4963 */
4964/* fcb->frame_length = tmf->vl + sizeof(MAC_HEADER) - 4;
4965 fcb->bdb_ptr->buffer_length = tmf->vl + sizeof(MAC_HEADER) - 4;
4966*/
4967 tmf->vl = SWAP_BYTES(tmf->vl);
4968
4969 if((err = smctr_trc_send_packet(dev, fcb, MAC_QUEUE)))
4970 return (err);
4971
4972 /* Wait for Transmit to Complete */
4973 for(i = 0; i < 10000; i++)
4974 {
4975 if(fcb->frame_status & FCB_COMMAND_DONE)
4976 break;
4977 mdelay(1);
4978 }
4979
4980 /* Check if GOOD frame Tx'ed */
4981 fstatus = fcb->frame_status;
4982
4983 if(!(fstatus & FCB_COMMAND_DONE))
4984 return (HARDWARE_FAILED);
4985
4986 if(!(fstatus & FCB_TX_STATUS_E))
4987 count++;
4988
4989 /* De-allocated Tx FCB and Frame Buffer
4990 * The FCB must be de-allocated manually if executing with
4991 * interrupts disabled, other wise the ISR (LM_Service_Events)
4992 * will de-allocate it when the interrupt occurs.
4993 */
4994 tp->tx_queue_status[MAC_QUEUE] = NOT_TRANSMITING;
4995 smctr_update_tx_chain(dev, fcb, MAC_QUEUE);
4996 } while(count < 4 && ((fstatus & FCB_TX_AC_BITS) ^ FCB_TX_AC_BITS));
4997
4998 return (smctr_join_complete_state(dev));
4999}
5000
5001static int smctr_send_tx_forward(struct net_device *dev, MAC_HEADER *rmf,
5002 __u16 *tx_fstatus)
5003{
5004 struct net_local *tp = netdev_priv(dev);
5005 FCBlock *fcb;
5006 unsigned int i;
5007 int err;
5008
5009 /* Check if this is the END POINT of the Transmit Forward Chain. */
5010 if(rmf->vl <= 18)
5011 return (0);
5012
5013 /* Allocate Transmit FCB only by requesting 0 bytes
5014 * of data buffer.
5015 */
5016 if((fcb = smctr_get_tx_fcb(dev, MAC_QUEUE, 0)) == (FCBlock *)(-1L))
5017 return (0);
5018
5019 /* Set pointer to Transmit Frame Buffer to the data
5020 * portion of the received TX Forward frame, making
5021 * sure to skip over the Vector Code (vc) and Vector
5022 * length (vl).
5023 */
5024 fcb->bdb_ptr->trc_data_block_ptr = TRC_POINTER((__u32)rmf
5025 + sizeof(MAC_HEADER) + 2);
5026 fcb->bdb_ptr->data_block_ptr = (__u16 *)((__u32)rmf
5027 + sizeof(MAC_HEADER) + 2);
5028
5029 fcb->frame_length = rmf->vl - 4 - 2;
5030 fcb->bdb_ptr->buffer_length = rmf->vl - 4 - 2;
5031
5032 if((err = smctr_trc_send_packet(dev, fcb, MAC_QUEUE)))
5033 return (err);
5034
5035 /* Wait for Transmit to Complete */
5036 for(i = 0; i < 10000; i++)
5037 {
5038 if(fcb->frame_status & FCB_COMMAND_DONE)
5039 break;
5040 mdelay(1);
5041 }
5042
5043 /* Check if GOOD frame Tx'ed */
5044 if(!(fcb->frame_status & FCB_COMMAND_DONE))
5045 {
5046 if((err = smctr_issue_resume_tx_fcb_cmd(dev, MAC_QUEUE)))
5047 return (err);
5048
5049 for(i = 0; i < 10000; i++)
5050 {
5051 if(fcb->frame_status & FCB_COMMAND_DONE)
5052 break;
5053 mdelay(1);
5054 }
5055
5056 if(!(fcb->frame_status & FCB_COMMAND_DONE))
5057 return (HARDWARE_FAILED);
5058 }
5059
5060 *tx_fstatus = fcb->frame_status;
5061
5062 return (A_FRAME_WAS_FORWARDED);
5063}
5064
5065static int smctr_set_auth_access_pri(struct net_device *dev,
5066 MAC_SUB_VECTOR *rsv)
5067{
5068 struct net_local *tp = netdev_priv(dev);
5069
5070 if(rsv->svl != S_AUTHORIZED_ACCESS_PRIORITY)
5071 return (E_SUB_VECTOR_LENGTH_ERROR);
5072
5073 tp->authorized_access_priority = (rsv->svv[0] << 8 | rsv->svv[1]);
5074
5075 return (POSITIVE_ACK);
5076}
5077
5078static int smctr_set_auth_funct_class(struct net_device *dev,
5079 MAC_SUB_VECTOR *rsv)
5080{
5081 struct net_local *tp = netdev_priv(dev);
5082
5083 if(rsv->svl != S_AUTHORIZED_FUNCTION_CLASS)
5084 return (E_SUB_VECTOR_LENGTH_ERROR);
5085
5086 tp->authorized_function_classes = (rsv->svv[0] << 8 | rsv->svv[1]);
5087
5088 return (POSITIVE_ACK);
5089}
5090
5091static int smctr_set_corr(struct net_device *dev, MAC_SUB_VECTOR *rsv,
5092 __u16 *correlator)
5093{
5094 if(rsv->svl != S_CORRELATOR)
5095 return (E_SUB_VECTOR_LENGTH_ERROR);
5096
5097 *correlator = (rsv->svv[0] << 8 | rsv->svv[1]);
5098
5099 return (POSITIVE_ACK);
5100}
5101
5102static int smctr_set_error_timer_value(struct net_device *dev,
5103 MAC_SUB_VECTOR *rsv)
5104{
5105 __u16 err_tval;
5106 int err;
5107
5108 if(rsv->svl != S_ERROR_TIMER_VALUE)
5109 return (E_SUB_VECTOR_LENGTH_ERROR);
5110
5111 err_tval = (rsv->svv[0] << 8 | rsv->svv[1])*10;
5112
5113 smctr_issue_write_word_cmd(dev, RW_TER_THRESHOLD, &err_tval);
5114
5115 if((err = smctr_wait_cmd(dev)))
5116 return (err);
5117
5118 return (POSITIVE_ACK);
5119}
5120
5121static int smctr_set_frame_forward(struct net_device *dev,
5122 MAC_SUB_VECTOR *rsv, __u8 dc_sc)
5123{
5124 if((rsv->svl < 2) || (rsv->svl > S_FRAME_FORWARD))
5125 return (E_SUB_VECTOR_LENGTH_ERROR);
5126
5127 if((dc_sc & DC_MASK) != DC_CRS)
5128 {
5129 if(rsv->svl >= 2 && rsv->svl < 20)
5130 return (E_TRANSMIT_FORWARD_INVALID);
5131
5132 if((rsv->svv[0] != 0) || (rsv->svv[1] != 0))
5133 return (E_TRANSMIT_FORWARD_INVALID);
5134 }
5135
5136 return (POSITIVE_ACK);
5137}
5138
5139static int smctr_set_local_ring_num(struct net_device *dev,
5140 MAC_SUB_VECTOR *rsv)
5141{
5142 struct net_local *tp = netdev_priv(dev);
5143
5144 if(rsv->svl != S_LOCAL_RING_NUMBER)
5145 return (E_SUB_VECTOR_LENGTH_ERROR);
5146
5147 if(tp->ptr_local_ring_num)
5148 *(__u16 *)(tp->ptr_local_ring_num)
5149 = (rsv->svv[0] << 8 | rsv->svv[1]);
5150
5151 return (POSITIVE_ACK);
5152}
5153
5154static unsigned short smctr_set_ctrl_attention(struct net_device *dev)
5155{
5156 struct net_local *tp = netdev_priv(dev);
5157 int ioaddr = dev->base_addr;
5158
5159 if(tp->bic_type == BIC_585_CHIP)
5160 outb((tp->trc_mask | HWR_CA), ioaddr + HWR);
5161 else
5162 {
5163 outb((tp->trc_mask | CSR_CA), ioaddr + CSR);
5164 outb(tp->trc_mask, ioaddr + CSR);
5165 }
5166
5167 return (0);
5168}
5169
5170static void smctr_set_multicast_list(struct net_device *dev)
5171{
5172 if(smctr_debug > 10)
5173 printk(KERN_DEBUG "%s: smctr_set_multicast_list\n", dev->name);
5174
5175 return;
5176}
5177
5178static int smctr_set_page(struct net_device *dev, __u8 *buf)
5179{
5180 struct net_local *tp = netdev_priv(dev);
5181 __u8 amask;
5182 __u32 tptr;
5183
5184 tptr = (__u32)buf - (__u32)tp->ram_access;
5185 amask = (__u8)((tptr & PR_PAGE_MASK) >> 8);
5186 outb(amask, dev->base_addr + PR);
5187
5188 return (0);
5189}
5190
5191static int smctr_set_phy_drop(struct net_device *dev, MAC_SUB_VECTOR *rsv)
5192{
5193 int err;
5194
5195 if(rsv->svl != S_PHYSICAL_DROP)
5196 return (E_SUB_VECTOR_LENGTH_ERROR);
5197
5198 smctr_issue_write_byte_cmd(dev, RW_PHYSICAL_DROP_NUMBER, &rsv->svv[0]);
5199 if((err = smctr_wait_cmd(dev)))
5200 return (err);
5201
5202 return (POSITIVE_ACK);
5203}
5204
5205/* Reset the ring speed to the opposite of what it was. This auto-pilot
5206 * mode requires a complete reset and re-init of the adapter.
5207 */
5208static int smctr_set_ring_speed(struct net_device *dev)
5209{
5210 struct net_local *tp = netdev_priv(dev);
5211 int err;
5212
5213 if(tp->media_type == MEDIA_UTP_16)
5214 tp->media_type = MEDIA_UTP_4;
5215 else
5216 tp->media_type = MEDIA_UTP_16;
5217
5218 smctr_enable_16bit(dev);
5219
5220 /* Re-Initialize adapter's internal registers */
5221 smctr_reset_adapter(dev);
5222
5223 if((err = smctr_init_card_real(dev)))
5224 return (err);
5225
5226 smctr_enable_bic_int(dev);
5227
5228 if((err = smctr_issue_enable_int_cmd(dev, TRC_INTERRUPT_ENABLE_MASK)))
5229 return (err);
5230
5231 smctr_disable_16bit(dev);
5232
5233 return (0);
5234}
5235
5236static int smctr_set_rx_look_ahead(struct net_device *dev)
5237{
5238 struct net_local *tp = netdev_priv(dev);
5239 __u16 sword, rword;
5240
5241 if(smctr_debug > 10)
5242 printk(KERN_DEBUG "%s: smctr_set_rx_look_ahead_flag\n", dev->name);
5243
5244 tp->adapter_flags &= ~(FORCED_16BIT_MODE);
5245 tp->adapter_flags |= RX_VALID_LOOKAHEAD;
5246
5247 if(tp->adapter_bus == BUS_ISA16_TYPE)
5248 {
5249 sword = *((__u16 *)(tp->ram_access));
5250 *((__u16 *)(tp->ram_access)) = 0x1234;
5251
5252 smctr_disable_16bit(dev);
5253 rword = *((__u16 *)(tp->ram_access));
5254 smctr_enable_16bit(dev);
5255
5256 if(rword != 0x1234)
5257 tp->adapter_flags |= FORCED_16BIT_MODE;
5258
5259 *((__u16 *)(tp->ram_access)) = sword;
5260 }
5261
5262 return (0);
5263}
5264
5265static int smctr_set_trc_reset(int ioaddr)
5266{
5267 __u8 r;
5268
5269 r = inb(ioaddr + MSR);
5270 outb(MSR_RST | r, ioaddr + MSR);
5271
5272 return (0);
5273}
5274
5275/*
5276 * This function can be called if the adapter is busy or not.
5277 */
5278static int smctr_setup_single_cmd(struct net_device *dev,
5279 __u16 command, __u16 subcommand)
5280{
5281 struct net_local *tp = netdev_priv(dev);
5282 unsigned int err;
5283
5284 if(smctr_debug > 10)
5285 printk(KERN_DEBUG "%s: smctr_setup_single_cmd\n", dev->name);
5286
5287 if((err = smctr_wait_while_cbusy(dev)))
5288 return (err);
5289
5290 if((err = (unsigned int)smctr_wait_cmd(dev)))
5291 return (err);
5292
5293 tp->acb_head->cmd_done_status = 0;
5294 tp->acb_head->cmd = command;
5295 tp->acb_head->subcmd = subcommand;
5296
5297 err = smctr_issue_resume_acb_cmd(dev);
5298
5299 return (err);
5300}
5301
5302/*
5303 * This function can not be called with the adapter busy.
5304 */
5305static int smctr_setup_single_cmd_w_data(struct net_device *dev,
5306 __u16 command, __u16 subcommand)
5307{
5308 struct net_local *tp = netdev_priv(dev);
5309
5310 tp->acb_head->cmd_done_status = ACB_COMMAND_NOT_DONE;
5311 tp->acb_head->cmd = command;
5312 tp->acb_head->subcmd = subcommand;
5313 tp->acb_head->data_offset_lo
5314 = (__u16)TRC_POINTER(tp->misc_command_data);
5315
5316 return(smctr_issue_resume_acb_cmd(dev));
5317}
5318
5319static char *smctr_malloc(struct net_device *dev, __u16 size)
5320{
5321 struct net_local *tp = netdev_priv(dev);
5322 char *m;
5323
5324 m = (char *)(tp->ram_access + tp->sh_mem_used);
5325 tp->sh_mem_used += (__u32)size;
5326
5327 return (m);
5328}
5329
5330static int smctr_status_chg(struct net_device *dev)
5331{
5332 struct net_local *tp = netdev_priv(dev);
5333
5334 if(smctr_debug > 10)
5335 printk(KERN_DEBUG "%s: smctr_status_chg\n", dev->name);
5336
5337 switch(tp->status)
5338 {
5339 case OPEN:
5340 break;
5341
5342 case CLOSED:
5343 break;
5344
5345 /* Interrupt driven open() completion. XXX */
5346 case INITIALIZED:
5347 tp->group_address_0 = 0;
5348 tp->group_address[0] = 0;
5349 tp->group_address[1] = 0;
5350 tp->functional_address_0 = 0;
5351 tp->functional_address[0] = 0;
5352 tp->functional_address[1] = 0;
5353 smctr_open_tr(dev);
5354 break;
5355
5356 default:
5357 printk(KERN_INFO "%s: status change unknown %x\n",
5358 dev->name, tp->status);
5359 break;
5360 }
5361
5362 return (0);
5363}
5364
5365static int smctr_trc_send_packet(struct net_device *dev, FCBlock *fcb,
5366 __u16 queue)
5367{
5368 struct net_local *tp = netdev_priv(dev);
5369 int err = 0;
5370
5371 if(smctr_debug > 10)
5372 printk(KERN_DEBUG "%s: smctr_trc_send_packet\n", dev->name);
5373
5374 fcb->info = FCB_CHAIN_END | FCB_ENABLE_TFS;
5375 if(tp->num_tx_fcbs[queue] != 1)
5376 fcb->back_ptr->info = FCB_INTERRUPT_ENABLE | FCB_ENABLE_TFS;
5377
5378 if(tp->tx_queue_status[queue] == NOT_TRANSMITING)
5379 {
5380 tp->tx_queue_status[queue] = TRANSMITING;
5381 err = smctr_issue_resume_tx_fcb_cmd(dev, queue);
5382 }
5383
5384 return (err);
5385}
5386
5387static __u16 smctr_tx_complete(struct net_device *dev, __u16 queue)
5388{
5389 struct net_local *tp = netdev_priv(dev);
5390 __u16 status, err = 0;
5391 int cstatus;
5392
5393 if(smctr_debug > 10)
5394 printk(KERN_DEBUG "%s: smctr_tx_complete\n", dev->name);
5395
5396 while((status = tp->tx_fcb_end[queue]->frame_status) != SUCCESS)
5397 {
5398 if(status & 0x7e00 )
5399 {
5400 err = HARDWARE_FAILED;
5401 break;
5402 }
5403
5404 if((err = smctr_update_tx_chain(dev, tp->tx_fcb_end[queue],
5405 queue)) != SUCCESS)
5406 break;
5407
5408 smctr_disable_16bit(dev);
5409
5410 if(tp->mode_bits & UMAC)
5411 {
5412 if(!(status & (FCB_TX_STATUS_AR1 | FCB_TX_STATUS_AR2)))
5413 cstatus = NO_SUCH_DESTINATION;
5414 else
5415 {
5416 if(!(status & (FCB_TX_STATUS_CR1 | FCB_TX_STATUS_CR2)))
5417 cstatus = DEST_OUT_OF_RESOURCES;
5418 else
5419 {
5420 if(status & FCB_TX_STATUS_E)
5421 cstatus = MAX_COLLISIONS;
5422 else
5423 cstatus = SUCCESS;
5424 }
5425 }
5426 }
5427 else
5428 cstatus = SUCCESS;
5429
5430 if(queue == BUG_QUEUE)
5431 err = SUCCESS;
5432
5433 smctr_enable_16bit(dev);
5434 if(err != SUCCESS)
5435 break;
5436 }
5437
5438 return (err);
5439}
5440
5441static unsigned short smctr_tx_move_frame(struct net_device *dev,
5442 struct sk_buff *skb, __u8 *pbuff, unsigned int bytes)
5443{
5444 struct net_local *tp = netdev_priv(dev);
5445 unsigned int ram_usable;
5446 __u32 flen, len, offset = 0;
5447 __u8 *frag, *page;
5448
5449 if(smctr_debug > 10)
5450 printk(KERN_DEBUG "%s: smctr_tx_move_frame\n", dev->name);
5451
5452 ram_usable = ((unsigned int)tp->ram_usable) << 10;
5453 frag = skb->data;
5454 flen = skb->len;
5455
5456 while(flen > 0 && bytes > 0)
5457 {
5458 smctr_set_page(dev, pbuff);
5459
5460 offset = SMC_PAGE_OFFSET(pbuff);
5461
5462 if(offset + flen > ram_usable)
5463 len = ram_usable - offset;
5464 else
5465 len = flen;
5466
5467 if(len > bytes)
5468 len = bytes;
5469
5470 page = (char *) (offset + tp->ram_access);
5471 memcpy(page, frag, len);
5472
5473 flen -=len;
5474 bytes -= len;
5475 frag += len;
5476 pbuff += len;
5477 }
5478
5479 return (0);
5480}
5481
5482/* Update the error statistic counters for this adapter. */
5483static int smctr_update_err_stats(struct net_device *dev)
5484{
5485 struct net_local *tp = netdev_priv(dev);
5486 struct tr_statistics *tstat = &tp->MacStat;
5487
5488 if(tstat->internal_errors)
5489 tstat->internal_errors
5490 += *(tp->misc_command_data + 0) & 0x00ff;
5491
5492 if(tstat->line_errors)
5493 tstat->line_errors += *(tp->misc_command_data + 0) >> 8;
5494
5495 if(tstat->A_C_errors)
5496 tstat->A_C_errors += *(tp->misc_command_data + 1) & 0x00ff;
5497
5498 if(tstat->burst_errors)
5499 tstat->burst_errors += *(tp->misc_command_data + 1) >> 8;
5500
5501 if(tstat->abort_delimiters)
5502 tstat->abort_delimiters += *(tp->misc_command_data + 2) >> 8;
5503
5504 if(tstat->recv_congest_count)
5505 tstat->recv_congest_count
5506 += *(tp->misc_command_data + 3) & 0x00ff;
5507
5508 if(tstat->lost_frames)
5509 tstat->lost_frames
5510 += *(tp->misc_command_data + 3) >> 8;
5511
5512 if(tstat->frequency_errors)
5513 tstat->frequency_errors += *(tp->misc_command_data + 4) & 0x00ff;
5514
5515 if(tstat->frame_copied_errors)
5516 tstat->frame_copied_errors
5517 += *(tp->misc_command_data + 4) >> 8;
5518
5519 if(tstat->token_errors)
5520 tstat->token_errors += *(tp->misc_command_data + 5) >> 8;
5521
5522 return (0);
5523}
5524
5525static int smctr_update_rx_chain(struct net_device *dev, __u16 queue)
5526{
5527 struct net_local *tp = netdev_priv(dev);
5528 FCBlock *fcb;
5529 BDBlock *bdb;
5530 __u16 size, len;
5531
5532 fcb = tp->rx_fcb_curr[queue];
5533 len = fcb->frame_length;
5534
5535 fcb->frame_status = 0;
5536 fcb->info = FCB_CHAIN_END;
5537 fcb->back_ptr->info = FCB_WARNING;
5538
5539 tp->rx_fcb_curr[queue] = tp->rx_fcb_curr[queue]->next_ptr;
5540
5541 /* update RX BDBs */
5542 size = (len >> RX_BDB_SIZE_SHIFT);
5543 if(len & RX_DATA_BUFFER_SIZE_MASK)
5544 size += sizeof(BDBlock);
5545 size &= (~RX_BDB_SIZE_MASK);
5546
5547 /* check if wrap around */
5548 bdb = (BDBlock *)((__u32)(tp->rx_bdb_curr[queue]) + (__u32)(size));
5549 if((__u32)bdb >= (__u32)tp->rx_bdb_end[queue])
5550 {
5551 bdb = (BDBlock *)((__u32)(tp->rx_bdb_head[queue])
5552 + (__u32)(bdb) - (__u32)(tp->rx_bdb_end[queue]));
5553 }
5554
5555 bdb->back_ptr->info = BDB_CHAIN_END;
5556 tp->rx_bdb_curr[queue]->back_ptr->info = BDB_NOT_CHAIN_END;
5557 tp->rx_bdb_curr[queue] = bdb;
5558
5559 return (0);
5560}
5561
5562static int smctr_update_tx_chain(struct net_device *dev, FCBlock *fcb,
5563 __u16 queue)
5564{
5565 struct net_local *tp = netdev_priv(dev);
5566
5567 if(smctr_debug > 20)
5568 printk(KERN_DEBUG "smctr_update_tx_chain\n");
5569
5570 if(tp->num_tx_fcbs_used[queue] <= 0)
5571 return (HARDWARE_FAILED);
5572 else
5573 {
5574 if(tp->tx_buff_used[queue] < fcb->memory_alloc)
5575 {
5576 tp->tx_buff_used[queue] = 0;
5577 return (HARDWARE_FAILED);
5578 }
5579
5580 tp->tx_buff_used[queue] -= fcb->memory_alloc;
5581
5582 /* if all transmit buffer are cleared
5583 * need to set the tx_buff_curr[] to tx_buff_head[]
5584 * otherwise, tx buffer will be segregate and cannot
5585 * accommodate and buffer greater than (curr - head) and
5586 * (end - curr) since we do not allow wrap around allocation.
5587 */
5588 if(tp->tx_buff_used[queue] == 0)
5589 tp->tx_buff_curr[queue] = tp->tx_buff_head[queue];
5590
5591 tp->num_tx_fcbs_used[queue]--;
5592 fcb->frame_status = 0;
5593 tp->tx_fcb_end[queue] = fcb->next_ptr;
5594 netif_wake_queue(dev);
5595 return (0);
5596 }
5597}
5598
5599static int smctr_wait_cmd(struct net_device *dev)
5600{
5601 struct net_local *tp = netdev_priv(dev);
5602 unsigned int loop_count = 0x20000;
5603
5604 if(smctr_debug > 10)
5605 printk(KERN_DEBUG "%s: smctr_wait_cmd\n", dev->name);
5606
5607 while(loop_count)
5608 {
5609 if(tp->acb_head->cmd_done_status & ACB_COMMAND_DONE)
5610 break;
5611 udelay(1);
5612 loop_count--;
5613 }
5614
5615 if(loop_count == 0)
5616 return(HARDWARE_FAILED);
5617
5618 if(tp->acb_head->cmd_done_status & 0xff)
5619 return(HARDWARE_FAILED);
5620
5621 return (0);
5622}
5623
5624static int smctr_wait_while_cbusy(struct net_device *dev)
5625{
5626 struct net_local *tp = netdev_priv(dev);
5627 unsigned int timeout = 0x20000;
5628 int ioaddr = dev->base_addr;
5629 __u8 r;
5630
5631 if(tp->bic_type == BIC_585_CHIP)
5632 {
5633 while(timeout)
5634 {
5635 r = inb(ioaddr + HWR);
5636 if((r & HWR_CBUSY) == 0)
5637 break;
5638 timeout--;
5639 }
5640 }
5641 else
5642 {
5643 while(timeout)
5644 {
5645 r = inb(ioaddr + CSR);
5646 if((r & CSR_CBUSY) == 0)
5647 break;
5648 timeout--;
5649 }
5650 }
5651
5652 if(timeout)
5653 return (0);
5654 else
5655 return (HARDWARE_FAILED);
5656}
5657
5658#ifdef MODULE
5659
5660static struct net_device* dev_smctr[SMCTR_MAX_ADAPTERS];
5661static int io[SMCTR_MAX_ADAPTERS];
5662static int irq[SMCTR_MAX_ADAPTERS];
5663
5664MODULE_LICENSE("GPL");
5665
5666module_param_array(io, int, NULL, 0);
5667module_param_array(irq, int, NULL, 0);
5668module_param(ringspeed, int, 0);
5669
5670static struct net_device *setup_card(int n)
5671{
5672 struct net_device *dev = alloc_trdev(sizeof(struct net_local));
5673 int err;
5674
5675 if (!dev)
5676 return ERR_PTR(-ENOMEM);
5677
5678 dev->irq = irq[n];
5679 err = smctr_probe1(dev, io[n]);
5680 if (err)
5681 goto out;
5682
5683 err = register_netdev(dev);
5684 if (err)
5685 goto out1;
5686 return dev;
5687 out1:
5688#ifdef CONFIG_MCA_LEGACY
5689 { struct net_local *tp = netdev_priv(dev);
5690 if (tp->slot_num)
5691 mca_mark_as_unused(tp->slot_num);
5692 }
5693#endif
5694 release_region(dev->base_addr, SMCTR_IO_EXTENT);
5695 free_irq(dev->irq, dev);
5696out:
5697 free_netdev(dev);
5698 return ERR_PTR(err);
5699}
5700
5701
5702int init_module(void)
5703{
5704 int i, found = 0;
5705 struct net_device *dev;
5706
5707 for(i = 0; i < SMCTR_MAX_ADAPTERS; i++) {
5708 dev = io[0]? setup_card(i) : smctr_probe(-1);
5709 if (!IS_ERR(dev)) {
5710 ++found;
5711 dev_smctr[i] = dev;
5712 }
5713 }
5714
5715 return found ? 0 : -ENODEV;
5716}
5717
5718void cleanup_module(void)
5719{
5720 int i;
5721
5722 for(i = 0; i < SMCTR_MAX_ADAPTERS; i++) {
5723 struct net_device *dev = dev_smctr[i];
5724
5725 if (dev) {
5726
5727 unregister_netdev(dev);
5728#ifdef CONFIG_MCA_LEGACY
5729 { struct net_local *tp = netdev_priv(dev);
5730 if (tp->slot_num)
5731 mca_mark_as_unused(tp->slot_num);
5732 }
5733#endif
5734 release_region(dev->base_addr, SMCTR_IO_EXTENT);
5735 if (dev->irq)
5736 free_irq(dev->irq, dev);
5737
5738 free_netdev(dev);
5739 }
5740 }
5741}
5742#endif /* MODULE */
diff --git a/drivers/net/tokenring/smctr.h b/drivers/net/tokenring/smctr.h
new file mode 100644
index 000000000000..b306c7e4c793
--- /dev/null
+++ b/drivers/net/tokenring/smctr.h
@@ -0,0 +1,1588 @@
1/* smctr.h: SMC Token Ring driver header for Linux
2 *
3 * Authors:
4 * - Jay Schulist <jschlst@samba.org>
5 */
6
7#ifndef __LINUX_SMCTR_H
8#define __LINUX_SMCTR_H
9
10#ifdef __KERNEL__
11
12#define MAX_TX_QUEUE 10
13
14#define SMC_HEADER_SIZE 14
15
16#define SMC_PAGE_OFFSET(X) (((unsigned long)(X) - tp->ram_access) & tp->page_offset_mask)
17
18#define INIT 0x0D
19#define RQ_ATTCH 0x10
20#define RQ_STATE 0x0F
21#define RQ_ADDR 0x0E
22#define CHG_PARM 0x0C
23#define RSP 0x00
24#define TX_FORWARD 0x09
25
26#define AC_FC_DAT ((3<<13) | 1)
27#define DAT 0x07
28
29#define RPT_NEW_MON 0x25
30#define RPT_SUA_CHG 0x26
31#define RPT_ACTIVE_ERR 0x28
32#define RPT_NN_INCMP 0x27
33#define RPT_ERROR 0x29
34
35#define RQ_INIT 0x20
36#define RPT_ATTCH 0x24
37#define RPT_STATE 0x23
38#define RPT_ADDR 0x22
39
40#define POSITIVE_ACK 0x0001
41#define A_FRAME_WAS_FORWARDED 0x8888
42
43#define GROUP_ADDRESS 0x2B
44#define PHYSICAL_DROP 0x0B
45#define AUTHORIZED_ACCESS_PRIORITY 0x07
46#define AUTHORIZED_FUNCTION_CLASS 0x06
47#define FUNCTIONAL_ADDRESS 0x2C
48#define RING_STATION_STATUS 0x29
49#define TRANSMIT_STATUS_CODE 0x2A
50#define IBM_PASS_SOURCE_ADDR 0x01
51#define AC_FC_RPT_TX_FORWARD ((0<<13) | 0)
52#define AC_FC_RPT_STATE ((0<<13) | 0)
53#define AC_FC_RPT_ADDR ((0<<13) | 0)
54#define CORRELATOR 0x09
55
56#define POSITIVE_ACK 0x0001 /* */
57#define E_MAC_DATA_INCOMPLETE 0x8001 /* not used */
58#define E_VECTOR_LENGTH_ERROR 0x8002 /* */
59#define E_UNRECOGNIZED_VECTOR_ID 0x8003 /* */
60#define E_INAPPROPRIATE_SOURCE_CLASS 0x8004 /* */
61#define E_SUB_VECTOR_LENGTH_ERROR 0x8005 /* */
62#define E_TRANSMIT_FORWARD_INVALID 0x8006 /* def. by IBM */
63#define E_MISSING_SUB_VECTOR 0x8007 /* */
64#define E_SUB_VECTOR_UNKNOWN 0x8008 /* */
65#define E_MAC_HEADER_TOO_LONG 0x8009 /* */
66#define E_FUNCTION_DISABLED 0x800A /* not used */
67
68#define A_FRAME_WAS_FORWARDED 0x8888 /* used by send_TX_FORWARD */
69
70#define UPSTREAM_NEIGHBOR_ADDRESS 0x02
71#define LOCAL_RING_NUMBER 0x03
72#define ASSIGN_PHYSICAL_DROP 0x04
73#define ERROR_TIMER_VALUE 0x05
74#define AUTHORIZED_FUNCTION_CLASS 0x06
75#define AUTHORIZED_ACCESS_PRIORITY 0x07
76#define CORRELATOR 0x09
77#define PHYSICAL_DROP 0x0B
78#define RESPONSE_CODE 0x20
79#define ADDRESS_MODIFER 0x21
80#define PRODUCT_INSTANCE_ID 0x22
81#define RING_STATION_VERSION_NUMBER 0x23
82#define WRAP_DATA 0x26
83#define FRAME_FORWARD 0x27
84#define STATION_IDENTIFER 0x28
85#define RING_STATION_STATUS 0x29
86#define TRANSMIT_STATUS_CODE 0x2A
87#define GROUP_ADDRESS 0x2B
88#define FUNCTIONAL_ADDRESS 0x2C
89
90#define F_NO_SUB_VECTORS_FOUND 0x0000
91#define F_UPSTREAM_NEIGHBOR_ADDRESS 0x0001
92#define F_LOCAL_RING_NUMBER 0x0002
93#define F_ASSIGN_PHYSICAL_DROP 0x0004
94#define F_ERROR_TIMER_VALUE 0x0008
95#define F_AUTHORIZED_FUNCTION_CLASS 0x0010
96#define F_AUTHORIZED_ACCESS_PRIORITY 0x0020
97#define F_CORRELATOR 0x0040
98#define F_PHYSICAL_DROP 0x0080
99#define F_RESPONSE_CODE 0x0100
100#define F_PRODUCT_INSTANCE_ID 0x0200
101#define F_RING_STATION_VERSION_NUMBER 0x0400
102#define F_STATION_IDENTIFER 0x0800
103#define F_RING_STATION_STATUS 0x1000
104#define F_GROUP_ADDRESS 0x2000
105#define F_FUNCTIONAL_ADDRESS 0x4000
106#define F_FRAME_FORWARD 0x8000
107
108#define R_INIT 0x00
109#define R_RQ_ATTCH_STATE_ADDR 0x00
110#define R_CHG_PARM 0x00
111#define R_TX_FORWARD F_FRAME_FORWARD
112
113
114#define UPSTREAM_NEIGHBOR_ADDRESS 0x02
115#define ADDRESS_MODIFER 0x21
116#define RING_STATION_VERSION_NUMBER 0x23
117#define PRODUCT_INSTANCE_ID 0x22
118
119#define RPT_TX_FORWARD 0x2A
120
121#define AC_FC_INIT (3<<13) | 0 /* */
122#define AC_FC_RQ_INIT ((3<<13) | 0) /* */
123#define AC_FC_RQ_ATTCH (3<<13) | 0 /* DC = SC of rx frame */
124#define AC_FC_RQ_STATE (3<<13) | 0 /* DC = SC of rx frame */
125#define AC_FC_RQ_ADDR (3<<13) | 0 /* DC = SC of rx frame */
126#define AC_FC_CHG_PARM (3<<13) | 0 /* */
127#define AC_FC_RSP (0<<13) | 0 /* DC = SC of rx frame */
128#define AC_FC_RPT_ATTCH (0<<13) | 0
129
130#define S_UPSTREAM_NEIGHBOR_ADDRESS 6 + 2
131#define S_LOCAL_RING_NUMBER 2 + 2
132#define S_ASSIGN_PHYSICAL_DROP 4 + 2
133#define S_ERROR_TIMER_VALUE 2 + 2
134#define S_AUTHORIZED_FUNCTION_CLASS 2 + 2
135#define S_AUTHORIZED_ACCESS_PRIORITY 2 + 2
136#define S_CORRELATOR 2 + 2
137#define S_PHYSICAL_DROP 4 + 2
138#define S_RESPONSE_CODE 4 + 2
139#define S_ADDRESS_MODIFER 2 + 2
140#define S_PRODUCT_INSTANCE_ID 18 + 2
141#define S_RING_STATION_VERSION_NUMBER 10 + 2
142#define S_STATION_IDENTIFER 6 + 2
143#define S_RING_STATION_STATUS 6 + 2
144#define S_GROUP_ADDRESS 4 + 2
145#define S_FUNCTIONAL_ADDRESS 4 + 2
146#define S_FRAME_FORWARD 252 + 2
147#define S_TRANSMIT_STATUS_CODE 2 + 2
148
149#define ISB_IMC_RES0 0x0000 /* */
150#define ISB_IMC_MAC_TYPE_3 0x0001 /* MAC_ARC_INDICATE */
151#define ISB_IMC_MAC_ERROR_COUNTERS 0x0002 /* */
152#define ISB_IMC_RES1 0x0003 /* */
153#define ISB_IMC_MAC_TYPE_2 0x0004 /* QUE_MAC_INDICATE */
154#define ISB_IMC_TX_FRAME 0x0005 /* */
155#define ISB_IMC_END_OF_TX_QUEUE 0x0006 /* */
156#define ISB_IMC_NON_MAC_RX_RESOURCE 0x0007 /* */
157#define ISB_IMC_MAC_RX_RESOURCE 0x0008 /* */
158#define ISB_IMC_NON_MAC_RX_FRAME 0x0009 /* */
159#define ISB_IMC_MAC_RX_FRAME 0x000A /* */
160#define ISB_IMC_TRC_FIFO_STATUS 0x000B /* */
161#define ISB_IMC_COMMAND_STATUS 0x000C /* */
162#define ISB_IMC_MAC_TYPE_1 0x000D /* Self Removed */
163#define ISB_IMC_TRC_INTRNL_TST_STATUS 0x000E /* */
164#define ISB_IMC_RES2 0x000F /* */
165
166#define NON_MAC_RX_RESOURCE_BW 0x10 /* shifted right 8 bits */
167#define NON_MAC_RX_RESOURCE_FW 0x20 /* shifted right 8 bits */
168#define NON_MAC_RX_RESOURCE_BE 0x40 /* shifted right 8 bits */
169#define NON_MAC_RX_RESOURCE_FE 0x80 /* shifted right 8 bits */
170#define RAW_NON_MAC_RX_RESOURCE_BW 0x1000 /* */
171#define RAW_NON_MAC_RX_RESOURCE_FW 0x2000 /* */
172#define RAW_NON_MAC_RX_RESOURCE_BE 0x4000 /* */
173#define RAW_NON_MAC_RX_RESOURCE_FE 0x8000 /* */
174
175#define MAC_RX_RESOURCE_BW 0x10 /* shifted right 8 bits */
176#define MAC_RX_RESOURCE_FW 0x20 /* shifted right 8 bits */
177#define MAC_RX_RESOURCE_BE 0x40 /* shifted right 8 bits */
178#define MAC_RX_RESOURCE_FE 0x80 /* shifted right 8 bits */
179#define RAW_MAC_RX_RESOURCE_BW 0x1000 /* */
180#define RAW_MAC_RX_RESOURCE_FW 0x2000 /* */
181#define RAW_MAC_RX_RESOURCE_BE 0x4000 /* */
182#define RAW_MAC_RX_RESOURCE_FE 0x8000 /* */
183
184#define TRC_FIFO_STATUS_TX_UNDERRUN 0x40 /* shifted right 8 bits */
185#define TRC_FIFO_STATUS_RX_OVERRUN 0x80 /* shifted right 8 bits */
186#define RAW_TRC_FIFO_STATUS_TX_UNDERRUN 0x4000 /* */
187#define RAW_TRC_FIFO_STATUS_RX_OVERRUN 0x8000 /* */
188
189#define CSR_CLRTINT 0x08
190
191#define MSB(X) ((__u8)((__u16) X >> 8))
192#define LSB(X) ((__u8)((__u16) X & 0xff))
193
194#define AC_FC_LOBE_MEDIA_TEST ((3<<13) | 0)
195#define S_WRAP_DATA 248 + 2 /* 500 + 2 */
196#define WRAP_DATA 0x26
197#define LOBE_MEDIA_TEST 0x08
198
199/* Destination Class (dc) */
200
201#define DC_MASK 0xF0
202#define DC_RS 0x00
203#define DC_CRS 0x40
204#define DC_RPS 0x50
205#define DC_REM 0x60
206
207/* Source Classes (sc) */
208
209#define SC_MASK 0x0F
210#define SC_RS 0x00
211#define SC_CRS 0x04
212#define SC_RPS 0x05
213#define SC_REM 0x06
214
215#define PR 0x11
216#define PR_PAGE_MASK 0x0C000
217
218#define MICROCHANNEL 0x0008
219#define INTERFACE_CHIP 0x0010
220#define BOARD_16BIT 0x0040
221#define PAGED_RAM 0x0080
222#define WD8115TA (TOKEN_MEDIA | MICROCHANNEL | INTERFACE_CHIP | PAGED_RAM)
223#define WD8115T (TOKEN_MEDIA | INTERFACE_CHIP | BOARD_16BIT | PAGED_RAM)
224
225#define BRD_ID_8316 0x50
226
227#define r587_SER 0x001
228#define SER_DIN 0x80
229#define SER_DOUT 0x40
230#define SER_CLK 0x20
231#define SER_ECS 0x10
232#define SER_E806 0x08
233#define SER_PNP 0x04
234#define SER_BIO 0x02
235#define SER_16B 0x01
236
237#define r587_IDR 0x004
238#define IDR_IRQ_MASK 0x0F0
239#define IDR_DCS_MASK 0x007
240#define IDR_RWS 0x008
241
242
243#define r587_BIO 0x003
244#define BIO_ENB 0x080
245#define BIO_MASK 0x03F
246
247#define r587_PCR 0x005
248#define PCR_RAMS 0x040
249
250
251
252#define NUM_ADDR_BITS 8
253
254#define ISA_MAX_ADDRESS 0x00ffffff
255
256#define SMCTR_MAX_ADAPTERS 7
257
258#define MC_TABLE_ENTRIES 16
259
260#define MAXFRAGMENTS 32
261
262#define CHIP_REV_MASK 0x3000
263
264#define MAX_TX_QS 8
265#define NUM_TX_QS_USED 3
266
267#define MAX_RX_QS 2
268#define NUM_RX_QS_USED 2
269
270#define INTEL_DATA_FORMAT 0x4000
271#define INTEL_ADDRESS_POINTER_FORMAT 0x8000
272#define PAGE_POINTER(X) ((((unsigned long)(X) - tp->ram_access) & tp->page_offset_mask) + tp->ram_access)
273#define SWAP_WORDS(X) (((X & 0xFFFF) << 16) | (X >> 16))
274
275#define INTERFACE_CHIP 0x0010 /* Soft Config Adapter */
276#define ADVANCED_FEATURES 0x0020 /* Adv. netw. interface features */
277#define BOARD_16BIT 0x0040 /* 16 bit capability */
278#define PAGED_RAM 0x0080 /* Adapter has paged RAM */
279
280#define PAGED_ROM 0x0100 /* Adapter has paged ROM */
281
282#define RAM_SIZE_UNKNOWN 0x0000 /* Unknown RAM size */
283#define RAM_SIZE_0K 0x0001 /* 0K RAM */
284#define RAM_SIZE_8K 0x0002 /* 8k RAM */
285#define RAM_SIZE_16K 0x0003 /* 16k RAM */
286#define RAM_SIZE_32K 0x0004 /* 32k RAM */
287#define RAM_SIZE_64K 0x0005 /* 64k RAM */
288#define RAM_SIZE_RESERVED_6 0x0006 /* Reserved RAM size */
289#define RAM_SIZE_RESERVED_7 0x0007 /* Reserved RAM size */
290#define RAM_SIZE_MASK 0x0007 /* Isolates RAM Size */
291
292#define TOKEN_MEDIA 0x0005
293
294#define BID_REG_0 0x00
295#define BID_REG_1 0x01
296#define BID_REG_2 0x02
297#define BID_REG_3 0x03
298#define BID_REG_4 0x04
299#define BID_REG_5 0x05
300#define BID_REG_6 0x06
301#define BID_REG_7 0x07
302#define BID_LAR_0 0x08
303#define BID_LAR_1 0x09
304#define BID_LAR_2 0x0A
305#define BID_LAR_3 0x0B
306#define BID_LAR_4 0x0C
307#define BID_LAR_5 0x0D
308
309#define BID_BOARD_ID_BYTE 0x0E
310#define BID_CHCKSM_BYTE 0x0F
311#define BID_LAR_OFFSET 0x08
312
313#define BID_MSZ_583_BIT 0x08
314#define BID_SIXTEEN_BIT_BIT 0x01
315
316#define BID_BOARD_REV_MASK 0x1E
317
318#define BID_MEDIA_TYPE_BIT 0x01
319#define BID_SOFT_CONFIG_BIT 0x20
320#define BID_RAM_SIZE_BIT 0x40
321#define BID_BUS_TYPE_BIT 0x80
322
323#define BID_CR 0x10
324
325#define BID_TXP 0x04 /* Transmit Packet Command */
326
327#define BID_TCR_DIFF 0x0D /* Transmit Configuration Register */
328
329#define BID_TCR_VAL 0x18 /* Value to Test 8390 or 690 */
330#define BID_PS0 0x00 /* Register Page Select 0 */
331#define BID_PS1 0x40 /* Register Page Select 1 */
332#define BID_PS2 0x80 /* Register Page Select 2 */
333#define BID_PS_MASK 0x3F /* For Masking Off Page Select Bits */
334
335#define BID_EEPROM_0 0x08
336#define BID_EEPROM_1 0x09
337#define BID_EEPROM_2 0x0A
338#define BID_EEPROM_3 0x0B
339#define BID_EEPROM_4 0x0C
340#define BID_EEPROM_5 0x0D
341#define BID_EEPROM_6 0x0E
342#define BID_EEPROM_7 0x0F
343
344#define BID_OTHER_BIT 0x02
345#define BID_ICR_MASK 0x0C
346#define BID_EAR_MASK 0x0F
347#define BID_ENGR_PAGE 0x0A0
348#define BID_RLA 0x10
349#define BID_EA6 0x80
350#define BID_RECALL_DONE_MASK 0x10
351#define BID_BID_EEPROM_OVERRIDE 0xFFB0
352#define BID_EXTRA_EEPROM_OVERRIDE 0xFFD0
353#define BID_EEPROM_MEDIA_MASK 0x07
354#define BID_STARLAN_TYPE 0x00
355#define BID_ETHERNET_TYPE 0x01
356#define BID_TP_TYPE 0x02
357#define BID_EW_TYPE 0x03
358#define BID_TOKEN_RING_TYPE 0x04
359#define BID_UTP2_TYPE 0x05
360#define BID_EEPROM_IRQ_MASK 0x18
361#define BID_PRIMARY_IRQ 0x00
362#define BID_ALTERNATE_IRQ_1 0x08
363#define BID_ALTERNATE_IRQ_2 0x10
364#define BID_ALTERNATE_IRQ_3 0x18
365#define BID_EEPROM_RAM_SIZE_MASK 0xE0
366#define BID_EEPROM_RAM_SIZE_RES1 0x00
367#define BID_EEPROM_RAM_SIZE_RES2 0x20
368#define BID_EEPROM_RAM_SIZE_8K 0x40
369#define BID_EEPROM_RAM_SIZE_16K 0x60
370#define BID_EEPROM_RAM_SIZE_32K 0x80
371#define BID_EEPROM_RAM_SIZE_64K 0xA0
372#define BID_EEPROM_RAM_SIZE_RES3 0xC0
373#define BID_EEPROM_RAM_SIZE_RES4 0xE0
374#define BID_EEPROM_BUS_TYPE_MASK 0x07
375#define BID_EEPROM_BUS_TYPE_AT 0x00
376#define BID_EEPROM_BUS_TYPE_MCA 0x01
377#define BID_EEPROM_BUS_TYPE_EISA 0x02
378#define BID_EEPROM_BUS_TYPE_NEC 0x03
379#define BID_EEPROM_BUS_SIZE_MASK 0x18
380#define BID_EEPROM_BUS_SIZE_8BIT 0x00
381#define BID_EEPROM_BUS_SIZE_16BIT 0x08
382#define BID_EEPROM_BUS_SIZE_32BIT 0x10
383#define BID_EEPROM_BUS_SIZE_64BIT 0x18
384#define BID_EEPROM_BUS_MASTER 0x20
385#define BID_EEPROM_RAM_PAGING 0x40
386#define BID_EEPROM_ROM_PAGING 0x80
387#define BID_EEPROM_PAGING_MASK 0xC0
388#define BID_EEPROM_LOW_COST 0x08
389#define BID_EEPROM_IO_MAPPED 0x10
390#define BID_EEPROM_HMI 0x01
391#define BID_EEPROM_AUTO_MEDIA_DETECT 0x01
392#define BID_EEPROM_CHIP_REV_MASK 0x0C
393
394#define BID_EEPROM_LAN_ADDR 0x30
395
396#define BID_EEPROM_MEDIA_OPTION 0x54
397#define BID_EEPROM_MEDIA_UTP 0x01
398#define BID_EEPROM_4MB_RING 0x08
399#define BID_EEPROM_16MB_RING 0x10
400#define BID_EEPROM_MEDIA_STP 0x40
401
402#define BID_EEPROM_MISC_DATA 0x56
403#define BID_EEPROM_EARLY_TOKEN_RELEASE 0x02
404
405#define CNFG_ID_8003E 0x6fc0
406#define CNFG_ID_8003S 0x6fc1
407#define CNFG_ID_8003W 0x6fc2
408#define CNFG_ID_8115TRA 0x6ec6
409#define CNFG_ID_8013E 0x61C8
410#define CNFG_ID_8013W 0x61C9
411#define CNFG_ID_BISTRO03E 0xEFE5
412#define CNFG_ID_BISTRO13E 0xEFD5
413#define CNFG_ID_BISTRO13W 0xEFD4
414#define CNFG_MSR_583 0x0
415#define CNFG_ICR_583 0x1
416#define CNFG_IAR_583 0x2
417#define CNFG_BIO_583 0x3
418#define CNFG_EAR_583 0x3
419#define CNFG_IRR_583 0x4
420#define CNFG_LAAR_584 0x5
421#define CNFG_GP2 0x7
422#define CNFG_LAAR_MASK 0x1F
423#define CNFG_LAAR_ZWS 0x20
424#define CNFG_LAAR_L16E 0x40
425#define CNFG_ICR_IR2_584 0x04
426#define CNFG_ICR_MASK 0x08
427#define CNFG_ICR_MSZ 0x08
428#define CNFG_ICR_RLA 0x10
429#define CNFG_ICR_STO 0x80
430#define CNFG_IRR_IRQS 0x60
431#define CNFG_IRR_IEN 0x80
432#define CNFG_IRR_ZWS 0x01
433#define CNFG_GP2_BOOT_NIBBLE 0x0F
434#define CNFG_IRR_OUT2 0x04
435#define CNFG_IRR_OUT1 0x02
436
437#define CNFG_SIZE_8KB 8
438#define CNFG_SIZE_16KB 16
439#define CNFG_SIZE_32KB 32
440#define CNFG_SIZE_64KB 64
441#define CNFG_SIZE_128KB 128
442#define CNFG_SIZE_256KB 256
443#define ROM_DISABLE 0x0
444
445#define CNFG_SLOT_ENABLE_BIT 0x08
446
447#define CNFG_POS_CONTROL_REG 0x096
448#define CNFG_POS_REG0 0x100
449#define CNFG_POS_REG1 0x101
450#define CNFG_POS_REG2 0x102
451#define CNFG_POS_REG3 0x103
452#define CNFG_POS_REG4 0x104
453#define CNFG_POS_REG5 0x105
454
455#define CNFG_ADAPTER_TYPE_MASK 0x0e
456
457#define SLOT_16BIT 0x0008
458#define INTERFACE_5X3_CHIP 0x0000 /* 0000 = 583 or 593 chips */
459#define NIC_690_BIT 0x0010 /* NIC is 690 */
460#define ALTERNATE_IRQ_BIT 0x0020 /* Alternate IRQ is used */
461#define INTERFACE_584_CHIP 0x0040 /* 0001 = 584 chip */
462#define INTERFACE_594_CHIP 0x0080 /* 0010 = 594 chip */
463#define INTERFACE_585_CHIP 0x0100 /* 0100 = 585/790 chip */
464#define INTERFACE_CHIP_MASK 0x03C0 /* Isolates Intfc Chip Type */
465
466#define BOARD_16BIT 0x0040
467#define NODE_ADDR_CKSUM 0xEE
468#define BRD_ID_8115T 0x04
469
470#define NIC_825_BIT 0x0400 /* TRC 83C825 NIC */
471#define NIC_790_BIT 0x0800 /* NIC is 83C790 Ethernet */
472
473#define CHIP_REV_MASK 0x3000
474
475#define HWR_CBUSY 0x02
476#define HWR_CA 0x01
477
478#define MAC_QUEUE 0
479#define NON_MAC_QUEUE 1
480#define BUG_QUEUE 2 /* NO RECEIVE QUEUE, ONLY TX */
481
482#define NUM_MAC_TX_FCBS 8
483#define NUM_MAC_TX_BDBS NUM_MAC_TX_FCBS
484#define NUM_MAC_RX_FCBS 7
485#define NUM_MAC_RX_BDBS 8
486
487#define NUM_NON_MAC_TX_FCBS 6
488#define NUM_NON_MAC_TX_BDBS NUM_NON_MAC_TX_FCBS
489
490#define NUM_NON_MAC_RX_BDBS 0 /* CALCULATED DYNAMICALLY */
491
492#define NUM_BUG_TX_FCBS 8
493#define NUM_BUG_TX_BDBS NUM_BUG_TX_FCBS
494
495#define MAC_TX_BUFFER_MEMORY 1024
496#define NON_MAC_TX_BUFFER_MEMORY (20 * 1024)
497#define BUG_TX_BUFFER_MEMORY (NUM_BUG_TX_FCBS * 32)
498
499#define RX_BUFFER_MEMORY 0 /* CALCULATED DYNAMICALLY */
500#define RX_DATA_BUFFER_SIZE 256
501#define RX_BDB_SIZE_SHIFT 3 /* log2(RX_DATA_BUFFER_SIZE)-log2(sizeof(BDBlock)) */
502#define RX_BDB_SIZE_MASK (sizeof(BDBlock) - 1)
503#define RX_DATA_BUFFER_SIZE_MASK (RX_DATA_BUFFER_SIZE-1)
504
505#define NUM_OF_INTERRUPTS 0x20
506
507#define NOT_TRANSMITING 0
508#define TRANSMITING 1
509
510#define TRC_INTERRUPT_ENABLE_MASK 0x7FF6
511
512#define UCODE_VERSION 0x58
513
514#define UCODE_SIZE_OFFSET 0x0000 /* WORD */
515#define UCODE_CHECKSUM_OFFSET 0x0002 /* WORD */
516#define UCODE_VERSION_OFFSET 0x0004 /* BYTE */
517
518#define CS_RAM_SIZE 0X2000
519#define CS_RAM_CHECKSUM_OFFSET 0x1FFE /* WORD 1FFE(MSB)-1FFF(LSB)*/
520#define CS_RAM_VERSION_OFFSET 0x1FFC /* WORD 1FFC(MSB)-1FFD(LSB)*/
521
522#define MISC_DATA_SIZE 128
523#define NUM_OF_ACBS 1
524
525#define ACB_COMMAND_NOT_DONE 0x0000 /* Init, command not done */
526#define ACB_COMMAND_DONE 0x8000 /* TRC says command done */
527#define ACB_COMMAND_STATUS_MASK 0x00FF /* low byte is status */
528#define ACB_COMMAND_SUCCESSFUL 0x0000 /* means cmd was successful */
529#define ACB_NOT_CHAIN_END 0x0000 /* tell TRC more CBs in chain */
530#define ACB_CHAIN_END 0x8000 /* tell TRC last CB in chain */
531#define ACB_COMMAND_NO_INTERRUPT 0x0000 /* tell TRC no INT after CB */
532#define ACB_COMMAND_INTERRUPT 0x2000 /* tell TRC to INT after CB */
533#define ACB_SUB_CMD_NOP 0x0000
534#define ACB_CMD_HIC_NOP 0x0080
535#define ACB_CMD_MCT_NOP 0x0000
536#define ACB_CMD_MCT_TEST 0x0001
537#define ACB_CMD_HIC_TEST 0x0081
538#define ACB_CMD_INSERT 0x0002
539#define ACB_CMD_REMOVE 0x0003
540#define ACB_CMD_MCT_WRITE_VALUE 0x0004
541#define ACB_CMD_HIC_WRITE_VALUE 0x0084
542#define ACB_CMD_MCT_READ_VALUE 0x0005
543#define ACB_CMD_HIC_READ_VALUE 0x0085
544#define ACB_CMD_INIT_TX_RX 0x0086
545#define ACB_CMD_INIT_TRC_TIMERS 0x0006
546#define ACB_CMD_READ_TRC_STATUS 0x0007
547#define ACB_CMD_CHANGE_JOIN_STATE 0x0008
548#define ACB_CMD_RESERVED_9 0x0009
549#define ACB_CMD_RESERVED_A 0x000A
550#define ACB_CMD_RESERVED_B 0x000B
551#define ACB_CMD_RESERVED_C 0x000C
552#define ACB_CMD_RESERVED_D 0x000D
553#define ACB_CMD_RESERVED_E 0x000E
554#define ACB_CMD_RESERVED_F 0x000F
555
556#define TRC_MAC_REGISTERS_TEST 0x0000
557#define TRC_INTERNAL_LOOPBACK 0x0001
558#define TRC_TRI_LOOPBACK 0x0002
559#define TRC_INTERNAL_ROM_TEST 0x0003
560#define TRC_LOBE_MEDIA_TEST 0x0004
561#define TRC_ANALOG_TEST 0x0005
562#define TRC_HOST_INTERFACE_REG_TEST 0x0003
563
564#define TEST_DMA_1 0x0000
565#define TEST_DMA_2 0x0001
566#define TEST_MCT_ROM 0x0002
567#define HIC_INTERNAL_DIAG 0x0003
568
569#define ABORT_TRANSMIT_PRIORITY_0 0x0001
570#define ABORT_TRANSMIT_PRIORITY_1 0x0002
571#define ABORT_TRANSMIT_PRIORITY_2 0x0004
572#define ABORT_TRANSMIT_PRIORITY_3 0x0008
573#define ABORT_TRANSMIT_PRIORITY_4 0x0010
574#define ABORT_TRANSMIT_PRIORITY_5 0x0020
575#define ABORT_TRANSMIT_PRIORITY_6 0x0040
576#define ABORT_TRANSMIT_PRIORITY_7 0x0080
577
578#define TX_PENDING_PRIORITY_0 0x0001
579#define TX_PENDING_PRIORITY_1 0x0002
580#define TX_PENDING_PRIORITY_2 0x0004
581#define TX_PENDING_PRIORITY_3 0x0008
582#define TX_PENDING_PRIORITY_4 0x0010
583#define TX_PENDING_PRIORITY_5 0x0020
584#define TX_PENDING_PRIORITY_6 0x0040
585#define TX_PENDING_PRIORITY_7 0x0080
586
587#define FCB_FRAME_LENGTH 0x100
588#define FCB_COMMAND_DONE 0x8000 /* FCB Word 0 */
589#define FCB_NOT_CHAIN_END 0x0000 /* FCB Word 1 */
590#define FCB_CHAIN_END 0x8000
591#define FCB_NO_WARNING 0x0000
592#define FCB_WARNING 0x4000
593#define FCB_INTERRUPT_DISABLE 0x0000
594#define FCB_INTERRUPT_ENABLE 0x2000
595
596#define FCB_ENABLE_IMA 0x0008
597#define FCB_ENABLE_TES 0x0004 /* Guarantee Tx before Int */
598#define FCB_ENABLE_TFS 0x0002 /* Post Tx Frame Status */
599#define FCB_ENABLE_NTC 0x0001 /* No Tx CRC */
600
601#define FCB_TX_STATUS_CR2 0x0004
602#define FCB_TX_STATUS_AR2 0x0008
603#define FCB_TX_STATUS_CR1 0x0040
604#define FCB_TX_STATUS_AR1 0x0080
605#define FCB_TX_AC_BITS (FCB_TX_STATUS_AR1+FCB_TX_STATUS_AR2+FCB_TX_STATUS_CR1+FCB_TX_STATUS_CR2)
606#define FCB_TX_STATUS_E 0x0100
607
608#define FCB_RX_STATUS_ANY_ERROR 0x0001
609#define FCB_RX_STATUS_FCS_ERROR 0x0002
610
611#define FCB_RX_STATUS_IA_MATCHED 0x0400
612#define FCB_RX_STATUS_IGA_BSGA_MATCHED 0x0500
613#define FCB_RX_STATUS_FA_MATCHED 0x0600
614#define FCB_RX_STATUS_BA_MATCHED 0x0700
615#define FCB_RX_STATUS_DA_MATCHED 0x0400
616#define FCB_RX_STATUS_SOURCE_ROUTING 0x0800
617
618#define BDB_BUFFER_SIZE 0x100
619#define BDB_NOT_CHAIN_END 0x0000
620#define BDB_CHAIN_END 0x8000
621#define BDB_NO_WARNING 0x0000
622#define BDB_WARNING 0x4000
623
624#define ERROR_COUNTERS_CHANGED 0x0001
625#define TI_NDIS_RING_STATUS_CHANGED 0x0002
626#define UNA_CHANGED 0x0004
627#define READY_TO_SEND_RQ_INIT 0x0008
628
629#define SCGB_ADDRESS_POINTER_FORMAT INTEL_ADDRESS_POINTER_FORMAT
630#define SCGB_DATA_FORMAT INTEL_DATA_FORMAT
631#define SCGB_MULTI_WORD_CONTROL 0
632#define SCGB_BURST_LENGTH 0x000E /* DMA Burst Length */
633
634#define SCGB_CONFIG (INTEL_ADDRESS_POINTER_FORMAT+INTEL_DATA_FORMAT+SCGB_BURST_LENGTH)
635
636#define ISCP_BLOCK_SIZE 0x0A
637#define RAM_SIZE 0x10000
638#define INIT_SYS_CONFIG_PTR_OFFSET (RAM_SIZE-ISCP_BLOCK_SIZE)
639#define SCGP_BLOCK_OFFSET 0
640
641#define SCLB_NOT_VALID 0x0000 /* Initially, SCLB not valid */
642#define SCLB_VALID 0x8000 /* Host tells TRC SCLB valid */
643#define SCLB_PROCESSED 0x0000 /* TRC says SCLB processed */
644#define SCLB_RESUME_CONTROL_NOT_VALID 0x0000 /* Initially, RC not valid */
645#define SCLB_RESUME_CONTROL_VALID 0x4000 /* Host tells TRC RC valid */
646#define SCLB_IACK_CODE_NOT_VALID 0x0000 /* Initially, IACK not valid */
647#define SCLB_IACK_CODE_VALID 0x2000 /* Host tells TRC IACK valid */
648#define SCLB_CMD_NOP 0x0000
649#define SCLB_CMD_REMOVE 0x0001
650#define SCLB_CMD_SUSPEND_ACB_CHAIN 0x0002
651#define SCLB_CMD_SET_INTERRUPT_MASK 0x0003
652#define SCLB_CMD_CLEAR_INTERRUPT_MASK 0x0004
653#define SCLB_CMD_RESERVED_5 0x0005
654#define SCLB_CMD_RESERVED_6 0x0006
655#define SCLB_CMD_RESERVED_7 0x0007
656#define SCLB_CMD_RESERVED_8 0x0008
657#define SCLB_CMD_RESERVED_9 0x0009
658#define SCLB_CMD_RESERVED_A 0x000A
659#define SCLB_CMD_RESERVED_B 0x000B
660#define SCLB_CMD_RESERVED_C 0x000C
661#define SCLB_CMD_RESERVED_D 0x000D
662#define SCLB_CMD_RESERVED_E 0x000E
663#define SCLB_CMD_RESERVED_F 0x000F
664
665#define SCLB_RC_ACB 0x0001 /* Action Command Block Chain */
666#define SCLB_RC_RES0 0x0002 /* Always Zero */
667#define SCLB_RC_RES1 0x0004 /* Always Zero */
668#define SCLB_RC_RES2 0x0008 /* Always Zero */
669#define SCLB_RC_RX_MAC_FCB 0x0010 /* RX_MAC_FCB Chain */
670#define SCLB_RC_RX_MAC_BDB 0x0020 /* RX_MAC_BDB Chain */
671#define SCLB_RC_RX_NON_MAC_FCB 0x0040 /* RX_NON_MAC_FCB Chain */
672#define SCLB_RC_RX_NON_MAC_BDB 0x0080 /* RX_NON_MAC_BDB Chain */
673#define SCLB_RC_TFCB0 0x0100 /* TX Priority 0 FCB Chain */
674#define SCLB_RC_TFCB1 0x0200 /* TX Priority 1 FCB Chain */
675#define SCLB_RC_TFCB2 0x0400 /* TX Priority 2 FCB Chain */
676#define SCLB_RC_TFCB3 0x0800 /* TX Priority 3 FCB Chain */
677#define SCLB_RC_TFCB4 0x1000 /* TX Priority 4 FCB Chain */
678#define SCLB_RC_TFCB5 0x2000 /* TX Priority 5 FCB Chain */
679#define SCLB_RC_TFCB6 0x4000 /* TX Priority 6 FCB Chain */
680#define SCLB_RC_TFCB7 0x8000 /* TX Priority 7 FCB Chain */
681
682#define SCLB_IMC_RES0 0x0001 /* */
683#define SCLB_IMC_MAC_TYPE_3 0x0002 /* MAC_ARC_INDICATE */
684#define SCLB_IMC_MAC_ERROR_COUNTERS 0x0004 /* */
685#define SCLB_IMC_RES1 0x0008 /* */
686#define SCLB_IMC_MAC_TYPE_2 0x0010 /* QUE_MAC_INDICATE */
687#define SCLB_IMC_TX_FRAME 0x0020 /* */
688#define SCLB_IMC_END_OF_TX_QUEUE 0x0040 /* */
689#define SCLB_IMC_NON_MAC_RX_RESOURCE 0x0080 /* */
690#define SCLB_IMC_MAC_RX_RESOURCE 0x0100 /* */
691#define SCLB_IMC_NON_MAC_RX_FRAME 0x0200 /* */
692#define SCLB_IMC_MAC_RX_FRAME 0x0400 /* */
693#define SCLB_IMC_TRC_FIFO_STATUS 0x0800 /* */
694#define SCLB_IMC_COMMAND_STATUS 0x1000 /* */
695#define SCLB_IMC_MAC_TYPE_1 0x2000 /* Self Removed */
696#define SCLB_IMC_TRC_INTRNL_TST_STATUS 0x4000 /* */
697#define SCLB_IMC_RES2 0x8000 /* */
698
699#define DMA_TRIGGER 0x0004
700#define FREQ_16MB_BIT 0x0010
701#define THDREN 0x0020
702#define CFG0_RSV1 0x0040
703#define CFG0_RSV2 0x0080
704#define ETREN 0x0100
705#define RX_OWN_BIT 0x0200
706#define RXATMAC 0x0400
707#define PROMISCUOUS_BIT 0x0800
708#define USETPT 0x1000
709#define SAVBAD_BIT 0x2000
710#define ONEQUE 0x4000
711#define NO_AUTOREMOVE 0x8000
712
713#define RX_FCB_AREA_8316 0x00000000
714#define RX_BUFF_AREA_8316 0x00000000
715
716#define TRC_POINTER(X) ((unsigned long)(X) - tp->ram_access)
717#define RX_FCB_TRC_POINTER(X) ((unsigned long)(X) - tp->ram_access + RX_FCB_AREA_8316)
718#define RX_BUFF_TRC_POINTER(X) ((unsigned long)(X) - tp->ram_access + RX_BUFF_AREA_8316)
719
720// Offset 0: MSR - Memory Select Register
721//
722#define r587_MSR 0x000 // Register Offset
723//#define MSR_RST 0x080 // LAN Controller Reset
724#define MSR_MENB 0x040 // Shared Memory Enable
725#define MSR_RA18 0x020 // Ram Address bit 18 (583, 584, 587)
726#define MSR_RA17 0x010 // Ram Address bit 17 (583, 584, 585/790)
727#define MSR_RA16 0x008 // Ram Address bit 16 (583, 584, 585/790)
728#define MSR_RA15 0x004 // Ram Address bit 15 (583, 584, 585/790)
729#define MSR_RA14 0x002 // Ram Address bit 14 (583, 584, 585/790)
730#define MSR_RA13 0x001 // Ram Address bit 13 (583, 584, 585/790)
731
732#define MSR_MASK 0x03F // Mask for Address bits RA18-RA13 (583, 584, 587)
733
734#define MSR 0x00
735#define IRR 0x04
736#define HWR 0x04
737#define LAAR 0x05
738#define IMCCR 0x05
739#define LAR0 0x08
740#define BDID 0x0E // Adapter ID byte register offset
741#define CSR 0x10
742#define PR 0x11
743
744#define MSR_RST 0x80
745#define MSR_MEMB 0x40
746#define MSR_0WS 0x20
747
748#define FORCED_16BIT_MODE 0x0002
749
750#define INTERFRAME_SPACING_16 0x0003 /* 6 bytes */
751#define INTERFRAME_SPACING_4 0x0001 /* 2 bytes */
752#define MULTICAST_ADDRESS_BIT 0x0010
753#define NON_SRC_ROUTING_BIT 0x0020
754
755#define LOOPING_MODE_MASK 0x0007
756
757/*
758 * Decode firmware defines.
759 */
760#define SWAP_BYTES(X) ((X & 0xff) << 8) | (X >> 8)
761#define WEIGHT_OFFSET 5
762#define TREE_SIZE_OFFSET 9
763#define TREE_OFFSET 11
764
765/* The Huffman Encoding Tree is constructed of these nodes. */
766typedef struct {
767 __u8 llink; /* Short version of above node. */
768 __u8 tag;
769 __u8 info; /* This node is used on decodes. */
770 __u8 rlink;
771} DECODE_TREE_NODE;
772
773#define ROOT 0 /* Branch value. */
774#define LEAF 0 /* Tag field value. */
775#define BRANCH 1 /* Tag field value. */
776
777/*
778 * Multicast Table Structure
779 */
780typedef struct {
781 __u8 address[6];
782 __u8 instance_count;
783} McTable;
784
785/*
786 * Fragment Descriptor Definition
787 */
788typedef struct {
789 __u8 *fragment_ptr;
790 __u32 fragment_length;
791} FragmentStructure;
792
793/*
794 * Data Buffer Structure Definition
795 */
796typedef struct {
797 __u32 fragment_count;
798 FragmentStructure fragment_list[MAXFRAGMENTS];
799} DataBufferStructure;
800
801#pragma pack(1)
802typedef struct {
803 __u8 IType;
804 __u8 ISubtype;
805} Interrupt_Status_Word;
806
807#pragma pack(1)
808typedef struct BDBlockType {
809 __u16 info; /* 02 */
810 __u32 trc_next_ptr; /* 06 */
811 __u32 trc_data_block_ptr; /* 10 */
812 __u16 buffer_length; /* 12 */
813
814 __u16 *data_block_ptr; /* 16 */
815 struct BDBlockType *next_ptr; /* 20 */
816 struct BDBlockType *back_ptr; /* 24 */
817 __u8 filler[8]; /* 32 */
818} BDBlock;
819
820#pragma pack(1)
821typedef struct FCBlockType {
822 __u16 frame_status; /* 02 */
823 __u16 info; /* 04 */
824 __u32 trc_next_ptr; /* 08 */
825 __u32 trc_bdb_ptr; /* 12 */
826 __u16 frame_length; /* 14 */
827
828 BDBlock *bdb_ptr; /* 18 */
829 struct FCBlockType *next_ptr; /* 22 */
830 struct FCBlockType *back_ptr; /* 26 */
831 __u16 memory_alloc; /* 28 */
832 __u8 filler[4]; /* 32 */
833
834} FCBlock;
835
836#pragma pack(1)
837typedef struct SBlockType{
838 __u8 Internal_Error_Count;
839 __u8 Line_Error_Count;
840 __u8 AC_Error_Count;
841 __u8 Burst_Error_Count;
842 __u8 RESERVED_COUNTER_0;
843 __u8 AD_TRANS_Count;
844 __u8 RCV_Congestion_Count;
845 __u8 Lost_FR_Error_Count;
846 __u8 FREQ_Error_Count;
847 __u8 FR_Copied_Error_Count;
848 __u8 RESERVED_COUNTER_1;
849 __u8 Token_Error_Count;
850
851 __u16 TI_NDIS_Ring_Status;
852 __u16 BCN_Type;
853 __u16 Error_Code;
854 __u16 SA_of_Last_AMP_SMP[3];
855 __u16 UNA[3];
856 __u16 Ucode_Version_Number;
857 __u16 Status_CHG_Indicate;
858 __u16 RESERVED_STATUS_0;
859} SBlock;
860
861#pragma pack(1)
862typedef struct ACBlockType {
863 __u16 cmd_done_status; /* 02 */
864 __u16 cmd_info; /* 04 */
865 __u32 trc_next_ptr; /* 08 */
866 __u16 cmd; /* 10 */
867 __u16 subcmd; /* 12 */
868 __u16 data_offset_lo; /* 14 */
869 __u16 data_offset_hi; /* 16 */
870
871 struct ACBlockType *next_ptr; /* 20 */
872
873 __u8 filler[12]; /* 32 */
874} ACBlock;
875
876#define NUM_OF_INTERRUPTS 0x20
877
878#pragma pack(1)
879typedef struct {
880 Interrupt_Status_Word IStatus[NUM_OF_INTERRUPTS];
881} ISBlock;
882
883#pragma pack(1)
884typedef struct {
885 __u16 valid_command; /* 02 */
886 __u16 iack_code; /* 04 */
887 __u16 resume_control; /* 06 */
888 __u16 int_mask_control; /* 08 */
889 __u16 int_mask_state; /* 10 */
890
891 __u8 filler[6]; /* 16 */
892} SCLBlock;
893
894#pragma pack(1)
895typedef struct
896{
897 __u16 config; /* 02 */
898 __u32 trc_sclb_ptr; /* 06 */
899 __u32 trc_acb_ptr; /* 10 */
900 __u32 trc_isb_ptr; /* 14 */
901 __u16 isbsiz; /* 16 */
902
903 SCLBlock *sclb_ptr; /* 20 */
904 ACBlock *acb_ptr; /* 24 */
905 ISBlock *isb_ptr; /* 28 */
906
907 __u16 Non_Mac_Rx_Bdbs; /* 30 DEBUG */
908 __u8 filler[2]; /* 32 */
909
910} SCGBlock;
911
912#pragma pack(1)
913typedef struct
914{
915 __u32 trc_scgb_ptr;
916 SCGBlock *scgb_ptr;
917} ISCPBlock;
918#pragma pack()
919
920typedef struct net_local {
921 ISCPBlock *iscpb_ptr;
922 SCGBlock *scgb_ptr;
923 SCLBlock *sclb_ptr;
924 ISBlock *isb_ptr;
925
926 ACBlock *acb_head;
927 ACBlock *acb_curr;
928 ACBlock *acb_next;
929
930 __u8 adapter_name[12];
931
932 __u16 num_rx_bdbs [NUM_RX_QS_USED];
933 __u16 num_rx_fcbs [NUM_RX_QS_USED];
934
935 __u16 num_tx_bdbs [NUM_TX_QS_USED];
936 __u16 num_tx_fcbs [NUM_TX_QS_USED];
937
938 __u16 num_of_tx_buffs;
939
940 __u16 tx_buff_size [NUM_TX_QS_USED];
941 __u16 tx_buff_used [NUM_TX_QS_USED];
942 __u16 tx_queue_status [NUM_TX_QS_USED];
943
944 FCBlock *tx_fcb_head[NUM_TX_QS_USED];
945 FCBlock *tx_fcb_curr[NUM_TX_QS_USED];
946 FCBlock *tx_fcb_end[NUM_TX_QS_USED];
947 BDBlock *tx_bdb_head[NUM_TX_QS_USED];
948 __u16 *tx_buff_head[NUM_TX_QS_USED];
949 __u16 *tx_buff_end[NUM_TX_QS_USED];
950 __u16 *tx_buff_curr[NUM_TX_QS_USED];
951 __u16 num_tx_fcbs_used[NUM_TX_QS_USED];
952
953 FCBlock *rx_fcb_head[NUM_RX_QS_USED];
954 FCBlock *rx_fcb_curr[NUM_RX_QS_USED];
955 BDBlock *rx_bdb_head[NUM_RX_QS_USED];
956 BDBlock *rx_bdb_curr[NUM_RX_QS_USED];
957 BDBlock *rx_bdb_end[NUM_RX_QS_USED];
958 __u16 *rx_buff_head[NUM_RX_QS_USED];
959 __u16 *rx_buff_end[NUM_RX_QS_USED];
960
961 __u32 *ptr_local_ring_num;
962
963 __u32 sh_mem_used;
964
965 __u16 page_offset_mask;
966
967 __u16 authorized_function_classes;
968 __u16 authorized_access_priority;
969
970 __u16 num_acbs;
971 __u16 num_acbs_used;
972 __u16 acb_pending;
973
974 __u16 current_isb_index;
975
976 __u8 monitor_state;
977 __u8 monitor_state_ready;
978 __u16 ring_status;
979 __u8 ring_status_flags;
980 __u8 current_ring_status;
981 __u8 state;
982
983 __u8 join_state;
984
985 __u8 slot_num;
986 __u16 pos_id;
987
988 __u32 *ptr_una;
989 __u32 *ptr_bcn_type;
990 __u32 *ptr_tx_fifo_underruns;
991 __u32 *ptr_rx_fifo_underruns;
992 __u32 *ptr_rx_fifo_overruns;
993 __u32 *ptr_tx_fifo_overruns;
994 __u32 *ptr_tx_fcb_overruns;
995 __u32 *ptr_rx_fcb_overruns;
996 __u32 *ptr_tx_bdb_overruns;
997 __u32 *ptr_rx_bdb_overruns;
998
999 __u16 receive_queue_number;
1000
1001 __u8 rx_fifo_overrun_count;
1002 __u8 tx_fifo_overrun_count;
1003
1004 __u16 adapter_flags;
1005 __u16 adapter_flags1;
1006 __u16 *misc_command_data;
1007 __u16 max_packet_size;
1008
1009 __u16 config_word0;
1010 __u16 config_word1;
1011
1012 __u8 trc_mask;
1013
1014 __u16 source_ring_number;
1015 __u16 target_ring_number;
1016
1017 __u16 microcode_version;
1018
1019 __u16 bic_type;
1020 __u16 nic_type;
1021 __u16 board_id;
1022
1023 __u16 rom_size;
1024 __u32 rom_base;
1025 __u16 ram_size;
1026 __u16 ram_usable;
1027 __u32 ram_base;
1028 __u32 ram_access;
1029
1030 __u16 extra_info;
1031 __u16 mode_bits;
1032 __u16 media_menu;
1033 __u16 media_type;
1034 __u16 adapter_bus;
1035
1036 __u16 status;
1037 __u16 receive_mask;
1038
1039 __u16 group_address_0;
1040 __u16 group_address[2];
1041 __u16 functional_address_0;
1042 __u16 functional_address[2];
1043 __u16 bitwise_group_address[2];
1044
1045 __u8 *ptr_ucode;
1046
1047 __u8 cleanup;
1048
1049 struct sk_buff_head SendSkbQueue;
1050 __u16 QueueSkb;
1051
1052 struct tr_statistics MacStat; /* MAC statistics structure */
1053
1054 spinlock_t lock;
1055} NET_LOCAL;
1056
1057/************************************
1058 * SNMP-ON-BOARD Agent Link Structure
1059 ************************************/
1060
1061typedef struct {
1062 __u8 LnkSigStr[12]; /* signature string "SmcLinkTable" */
1063 __u8 LnkDrvTyp; /* 1=Redbox ODI, 2=ODI DOS, 3=ODI OS/2, 4=NDIS DOS */
1064 __u8 LnkFlg; /* 0 if no agent linked, 1 if agent linked */
1065 void *LnkNfo; /* routine which returns pointer to NIC info */
1066 void *LnkAgtRcv; /* pointer to agent receive trap entry */
1067 void *LnkAgtXmt; /* pointer to agent transmit trap
1068entry */
1069void *LnkGet; /* pointer to NIC receive data
1070copy routine */
1071 void *LnkSnd; /* pointer to NIC send routine
1072*/
1073 void *LnkRst; /* pointer to NIC driver reset
1074routine */
1075 void *LnkMib; /* pointer to MIB data base */
1076 void *LnkMibAct; /* pointer to MIB action routine list */
1077 __u16 LnkCntOffset; /* offset to error counters */
1078 __u16 LnkCntNum; /* number of error counters */
1079 __u16 LnkCntSize; /* size of error counters i.e. 32 = 32 bits */
1080 void *LnkISR; /* pointer to interrupt vector */
1081 __u8 LnkFrmTyp; /* 1=Ethernet, 2=Token Ring */
1082 __u8 LnkDrvVer1 ; /* driver major version */
1083 __u8 LnkDrvVer2 ; /* driver minor version */
1084} AgentLink;
1085
1086/*
1087 * Definitions for pcm_card_flags(bit_mapped)
1088 */
1089#define REG_COMPLETE 0x0001
1090#define INSERTED 0x0002
1091#define PCC_INSERTED 0x0004 /* 1=currently inserted, 0=cur removed */
1092
1093/*
1094 * Adapter RAM test patterns
1095 */
1096#define RAM_PATTERN_1 0x55AA
1097#define RAM_PATTERN_2 0x9249
1098#define RAM_PATTERN_3 0xDB6D
1099
1100/*
1101 * definitions for RAM test
1102 */
1103#define ROM_SIGNATURE 0xAA55
1104#define MIN_ROM_SIZE 0x2000
1105
1106/*
1107 * Return Codes
1108 */
1109#define SUCCESS 0x0000
1110#define ADAPTER_AND_CONFIG 0x0001
1111#define ADAPTER_NO_CONFIG 0x0002
1112#define NOT_MY_INTERRUPT 0x0003
1113#define FRAME_REJECTED 0x0004
1114#define EVENTS_DISABLED 0x0005
1115#define OUT_OF_RESOURCES 0x0006
1116#define INVALID_PARAMETER 0x0007
1117#define INVALID_FUNCTION 0x0008
1118#define INITIALIZE_FAILED 0x0009
1119#define CLOSE_FAILED 0x000A
1120#define MAX_COLLISIONS 0x000B
1121#define NO_SUCH_DESTINATION 0x000C
1122#define BUFFER_TOO_SMALL_ERROR 0x000D
1123#define ADAPTER_CLOSED 0x000E
1124#define UCODE_NOT_PRESENT 0x000F
1125#define FIFO_UNDERRUN 0x0010
1126#define DEST_OUT_OF_RESOURCES 0x0011
1127#define ADAPTER_NOT_INITIALIZED 0x0012
1128#define PENDING 0x0013
1129#define UCODE_PRESENT 0x0014
1130#define NOT_INIT_BY_BRIDGE 0x0015
1131
1132#define OPEN_FAILED 0x0080
1133#define HARDWARE_FAILED 0x0081
1134#define SELF_TEST_FAILED 0x0082
1135#define RAM_TEST_FAILED 0x0083
1136#define RAM_CONFLICT 0x0084
1137#define ROM_CONFLICT 0x0085
1138#define UNKNOWN_ADAPTER 0x0086
1139#define CONFIG_ERROR 0x0087
1140#define CONFIG_WARNING 0x0088
1141#define NO_FIXED_CNFG 0x0089
1142#define EEROM_CKSUM_ERROR 0x008A
1143#define ROM_SIGNATURE_ERROR 0x008B
1144#define ROM_CHECKSUM_ERROR 0x008C
1145#define ROM_SIZE_ERROR 0x008D
1146#define UNSUPPORTED_NIC_CHIP 0x008E
1147#define NIC_REG_ERROR 0x008F
1148#define BIC_REG_ERROR 0x0090
1149#define MICROCODE_TEST_ERROR 0x0091
1150#define LOBE_MEDIA_TEST_FAILED 0x0092
1151
1152#define ADAPTER_FOUND_LAN_CORRUPT 0x009B
1153
1154#define ADAPTER_NOT_FOUND 0xFFFF
1155
1156#define ILLEGAL_FUNCTION INVALID_FUNCTION
1157
1158/* Errors */
1159#define IO_BASE_INVALID 0x0001
1160#define IO_BASE_RANGE 0x0002
1161#define IRQ_INVALID 0x0004
1162#define IRQ_RANGE 0x0008
1163#define RAM_BASE_INVALID 0x0010
1164#define RAM_BASE_RANGE 0x0020
1165#define RAM_SIZE_RANGE 0x0040
1166#define MEDIA_INVALID 0x0800
1167
1168/* Warnings */
1169#define IRQ_MISMATCH 0x0080
1170#define RAM_BASE_MISMATCH 0x0100
1171#define RAM_SIZE_MISMATCH 0x0200
1172#define BUS_MODE_MISMATCH 0x0400
1173
1174#define RX_CRC_ERROR 0x01
1175#define RX_ALIGNMENT_ERROR 0x02
1176#define RX_HW_FAILED 0x80
1177
1178/*
1179 * Definitions for the field RING_STATUS_FLAGS
1180 */
1181#define RING_STATUS_CHANGED 0X01
1182#define MONITOR_STATE_CHANGED 0X02
1183#define JOIN_STATE_CHANGED 0X04
1184
1185/*
1186 * Definitions for the field JOIN_STATE
1187 */
1188#define JS_BYPASS_STATE 0x00
1189#define JS_LOBE_TEST_STATE 0x01
1190#define JS_DETECT_MONITOR_PRESENT_STATE 0x02
1191#define JS_AWAIT_NEW_MONITOR_STATE 0x03
1192#define JS_DUPLICATE_ADDRESS_TEST_STATE 0x04
1193#define JS_NEIGHBOR_NOTIFICATION_STATE 0x05
1194#define JS_REQUEST_INITIALIZATION_STATE 0x06
1195#define JS_JOIN_COMPLETE_STATE 0x07
1196#define JS_BYPASS_WAIT_STATE 0x08
1197
1198/*
1199 * Definitions for the field MONITOR_STATE
1200 */
1201#define MS_MONITOR_FSM_INACTIVE 0x00
1202#define MS_REPEAT_BEACON_STATE 0x01
1203#define MS_REPEAT_CLAIM_TOKEN_STATE 0x02
1204#define MS_TRANSMIT_CLAIM_TOKEN_STATE 0x03
1205#define MS_STANDBY_MONITOR_STATE 0x04
1206#define MS_TRANSMIT_BEACON_STATE 0x05
1207#define MS_ACTIVE_MONITOR_STATE 0x06
1208#define MS_TRANSMIT_RING_PURGE_STATE 0x07
1209#define MS_BEACON_TEST_STATE 0x09
1210
1211/*
1212 * Definitions for the bit-field RING_STATUS
1213 */
1214#define SIGNAL_LOSS 0x8000
1215#define HARD_ERROR 0x4000
1216#define SOFT_ERROR 0x2000
1217#define TRANSMIT_BEACON 0x1000
1218#define LOBE_WIRE_FAULT 0x0800
1219#define AUTO_REMOVAL_ERROR 0x0400
1220#define REMOVE_RECEIVED 0x0100
1221#define COUNTER_OVERFLOW 0x0080
1222#define SINGLE_STATION 0x0040
1223#define RING_RECOVERY 0x0020
1224
1225/*
1226 * Definitions for the field BUS_TYPE
1227 */
1228#define AT_BUS 0x00
1229#define MCA_BUS 0x01
1230#define EISA_BUS 0x02
1231#define PCI_BUS 0x03
1232#define PCMCIA_BUS 0x04
1233
1234/*
1235 * Definitions for adapter_flags
1236 */
1237#define RX_VALID_LOOKAHEAD 0x0001
1238#define FORCED_16BIT_MODE 0x0002
1239#define ADAPTER_DISABLED 0x0004
1240#define TRANSMIT_CHAIN_INT 0x0008
1241#define EARLY_RX_FRAME 0x0010
1242#define EARLY_TX 0x0020
1243#define EARLY_RX_COPY 0x0040
1244#define USES_PHYSICAL_ADDR 0x0080 /* Rsvd for DEC PCI and 9232 */
1245#define NEEDS_PHYSICAL_ADDR 0x0100 /* Reserved*/
1246#define RX_STATUS_PENDING 0x0200
1247#define ERX_DISABLED 0x0400 /* EARLY_RX_ENABLE rcv_mask */
1248#define ENABLE_TX_PENDING 0x0800
1249#define ENABLE_RX_PENDING 0x1000
1250#define PERM_CLOSE 0x2000
1251#define IO_MAPPED 0x4000 /* IOmapped bus interface 795 */
1252#define ETX_DISABLED 0x8000
1253
1254
1255/*
1256 * Definitions for adapter_flags1
1257 */
1258#define TX_PHY_RX_VIRT 0x0001
1259#define NEEDS_HOST_RAM 0x0002
1260#define NEEDS_MEDIA_TYPE 0x0004
1261#define EARLY_RX_DONE 0x0008
1262#define PNP_BOOT_BIT 0x0010 /* activates PnP & config on power-up */
1263 /* clear => regular PnP operation */
1264#define PNP_ENABLE 0x0020 /* regular PnP operation clear => */
1265 /* no PnP, overrides PNP_BOOT_BIT */
1266#define SATURN_ENABLE 0x0040
1267
1268#define ADAPTER_REMOVABLE 0x0080 /* adapter is hot swappable */
1269#define TX_PHY 0x0100 /* Uses physical address for tx bufs */
1270#define RX_PHY 0x0200 /* Uses physical address for rx bufs */
1271#define TX_VIRT 0x0400 /* Uses virtual addr for tx bufs */
1272#define RX_VIRT 0x0800
1273#define NEEDS_SERVICE 0x1000
1274
1275/*
1276 * Adapter Status Codes
1277 */
1278#define OPEN 0x0001
1279#define INITIALIZED 0x0002
1280#define CLOSED 0x0003
1281#define FAILED 0x0005
1282#define NOT_INITIALIZED 0x0006
1283#define IO_CONFLICT 0x0007
1284#define CARD_REMOVED 0x0008
1285#define CARD_INSERTED 0x0009
1286
1287/*
1288 * Mode Bit Definitions
1289 */
1290#define INTERRUPT_STATUS_BIT 0x8000 /* PC Interrupt Line: 0 = Not Enabled */
1291#define BOOT_STATUS_MASK 0x6000 /* Mask to isolate BOOT_STATUS */
1292#define BOOT_INHIBIT 0x0000 /* BOOT_STATUS is 'inhibited' */
1293#define BOOT_TYPE_1 0x2000 /* Unused BOOT_STATUS value */
1294#define BOOT_TYPE_2 0x4000 /* Unused BOOT_STATUS value */
1295#define BOOT_TYPE_3 0x6000 /* Unused BOOT_STATUS value */
1296#define ZERO_WAIT_STATE_MASK 0x1800 /* Mask to isolate Wait State flags */
1297#define ZERO_WAIT_STATE_8_BIT 0x1000 /* 0 = Disabled (Inserts Wait States) */
1298#define ZERO_WAIT_STATE_16_BIT 0x0800 /* 0 = Disabled (Inserts Wait States) */
1299#define LOOPING_MODE_MASK 0x0007
1300#define LOOPBACK_MODE_0 0x0000
1301#define LOOPBACK_MODE_1 0x0001
1302#define LOOPBACK_MODE_2 0x0002
1303#define LOOPBACK_MODE_3 0x0003
1304#define LOOPBACK_MODE_4 0x0004
1305#define LOOPBACK_MODE_5 0x0005
1306#define LOOPBACK_MODE_6 0x0006
1307#define LOOPBACK_MODE_7 0x0007
1308#define AUTO_MEDIA_DETECT 0x0008
1309#define MANUAL_CRC 0x0010
1310#define EARLY_TOKEN_REL 0x0020 /* Early Token Release for Token Ring */
1311#define UMAC 0x0040
1312#define UTP2_PORT 0x0080 /* For 8216T2, 0=port A, 1=Port B. */
1313#define BNC_10BT_INTERFACE 0x0600 /* BNC and UTP current media set */
1314#define UTP_INTERFACE 0x0500 /* Ethernet UTP Only. */
1315#define BNC_INTERFACE 0x0400
1316#define AUI_INTERFACE 0x0300
1317#define AUI_10BT_INTERFACE 0x0200
1318#define STARLAN_10_INTERFACE 0x0100
1319#define INTERFACE_TYPE_MASK 0x0700
1320
1321/*
1322 * Media Type Bit Definitions
1323 *
1324 * legend: TP = Twisted Pair
1325 * STP = Shielded twisted pair
1326 * UTP = Unshielded twisted pair
1327 */
1328
1329#define CNFG_MEDIA_TYPE_MASK 0x001e /* POS Register 3 Mask */
1330
1331#define MEDIA_S10 0x0000 /* Ethernet adapter, TP. */
1332#define MEDIA_AUI_UTP 0x0001 /* Ethernet adapter, AUI/UTP media */
1333#define MEDIA_BNC 0x0002 /* Ethernet adapter, BNC media. */
1334#define MEDIA_AUI 0x0003 /* Ethernet Adapter, AUI media. */
1335#define MEDIA_STP_16 0x0004 /* TokenRing adap, 16Mbit STP. */
1336#define MEDIA_STP_4 0x0005 /* TokenRing adap, 4Mbit STP. */
1337#define MEDIA_UTP_16 0x0006 /* TokenRing adap, 16Mbit UTP. */
1338#define MEDIA_UTP_4 0x0007 /* TokenRing adap, 4Mbit UTP. */
1339#define MEDIA_UTP 0x0008 /* Ethernet adapter, UTP media (no AUI)
1340*/
1341#define MEDIA_BNC_UTP 0x0010 /* Ethernet adapter, BNC/UTP media */
1342#define MEDIA_UTPFD 0x0011 /* Ethernet adapter, TP full duplex */
1343#define MEDIA_UTPNL 0x0012 /* Ethernet adapter, TP with link integrity test disabled */
1344#define MEDIA_AUI_BNC 0x0013 /* Ethernet adapter, AUI/BNC media */
1345#define MEDIA_AUI_BNC_UTP 0x0014 /* Ethernet adapter, AUI_BNC/UTP */
1346#define MEDIA_UTPA 0x0015 /* Ethernet UTP-10Mbps Ports A */
1347#define MEDIA_UTPB 0x0016 /* Ethernet UTP-10Mbps Ports B */
1348#define MEDIA_STP_16_UTP_16 0x0017 /* Token Ring STP-16Mbps/UTP-16Mbps */
1349#define MEDIA_STP_4_UTP_4 0x0018 /* Token Ring STP-4Mbps/UTP-4Mbps */
1350
1351#define MEDIA_STP100_UTP100 0x0020 /* Ethernet STP-100Mbps/UTP-100Mbps */
1352#define MEDIA_UTP100FD 0x0021 /* Ethernet UTP-100Mbps, full duplex */
1353#define MEDIA_UTP100 0x0022 /* Ethernet UTP-100Mbps */
1354
1355
1356#define MEDIA_UNKNOWN 0xFFFF /* Unknown adapter/media type */
1357
1358/*
1359 * Definitions for the field:
1360 * media_type2
1361 */
1362#define MEDIA_TYPE_MII 0x0001
1363#define MEDIA_TYPE_UTP 0x0002
1364#define MEDIA_TYPE_BNC 0x0004
1365#define MEDIA_TYPE_AUI 0x0008
1366#define MEDIA_TYPE_S10 0x0010
1367#define MEDIA_TYPE_AUTO_SENSE 0x1000
1368#define MEDIA_TYPE_AUTO_DETECT 0x4000
1369#define MEDIA_TYPE_AUTO_NEGOTIATE 0x8000
1370
1371/*
1372 * Definitions for the field:
1373 * line_speed
1374 */
1375#define LINE_SPEED_UNKNOWN 0x0000
1376#define LINE_SPEED_4 0x0001
1377#define LINE_SPEED_10 0x0002
1378#define LINE_SPEED_16 0x0004
1379#define LINE_SPEED_100 0x0008
1380#define LINE_SPEED_T4 0x0008 /* 100BaseT4 aliased for 9332BVT */
1381#define LINE_SPEED_FULL_DUPLEX 0x8000
1382
1383/*
1384 * Definitions for the field:
1385 * bic_type (Bus interface chip type)
1386 */
1387#define BIC_NO_CHIP 0x0000 /* Bus interface chip not implemented */
1388#define BIC_583_CHIP 0x0001 /* 83C583 bus interface chip */
1389#define BIC_584_CHIP 0x0002 /* 83C584 bus interface chip */
1390#define BIC_585_CHIP 0x0003 /* 83C585 bus interface chip */
1391#define BIC_593_CHIP 0x0004 /* 83C593 bus interface chip */
1392#define BIC_594_CHIP 0x0005 /* 83C594 bus interface chip */
1393#define BIC_564_CHIP 0x0006 /* PCMCIA Bus interface chip */
1394#define BIC_790_CHIP 0x0007 /* 83C790 bus i-face/Ethernet NIC chip */
1395#define BIC_571_CHIP 0x0008 /* 83C571 EISA bus master i-face */
1396#define BIC_587_CHIP 0x0009 /* Token Ring AT bus master i-face */
1397#define BIC_574_CHIP 0x0010 /* FEAST bus interface chip */
1398#define BIC_8432_CHIP 0x0011 /* 8432 bus i-face/Ethernet NIC(DEC PCI) */
1399#define BIC_9332_CHIP 0x0012 /* 9332 bus i-face/100Mbps Ether NIC(DEC PCI) */
1400#define BIC_8432E_CHIP 0x0013 /* 8432 Enhanced bus iface/Ethernet NIC(DEC) */
1401#define BIC_EPIC100_CHIP 0x0014 /* EPIC/100 10/100 Mbps Ethernet BIC/NIC */
1402#define BIC_C94_CHIP 0x0015 /* 91C94 bus i-face in PCMCIA mode */
1403#define BIC_X8020_CHIP 0x0016 /* Xilinx PCMCIA multi-func i-face */
1404
1405/*
1406 * Definitions for the field:
1407 * nic_type (Bus interface chip type)
1408 */
1409#define NIC_UNK_CHIP 0x0000 /* Unknown NIC chip */
1410#define NIC_8390_CHIP 0x0001 /* DP8390 Ethernet NIC */
1411#define NIC_690_CHIP 0x0002 /* 83C690 Ethernet NIC */
1412#define NIC_825_CHIP 0x0003 /* 83C825 Token Ring NIC */
1413/* #define NIC_???_CHIP 0x0004 */ /* Not used */
1414/* #define NIC_???_CHIP 0x0005 */ /* Not used */
1415/* #define NIC_???_CHIP 0x0006 */ /* Not used */
1416#define NIC_790_CHIP 0x0007 /* 83C790 bus i-face/Ethernet NIC chip */
1417#define NIC_C100_CHIP 0x0010 /* FEAST 100Mbps Ethernet NIC */
1418#define NIC_8432_CHIP 0x0011 /* 8432 bus i-face/Ethernet NIC(DEC PCI) */
1419#define NIC_9332_CHIP 0x0012 /* 9332 bus i-face/100Mbps Ether NIC(DEC PCI) */
1420#define NIC_8432E_CHIP 0x0013 /* 8432 enhanced bus iface/Ethernet NIC(DEC) */
1421#define NIC_EPIC100_CHIP 0x0014 /* EPIC/100 10/100 Mbps Ethernet BIC/NIC */
1422#define NIC_C94_CHIP 0x0015 /* 91C94 PC Card with multi func */
1423
1424/*
1425 * Definitions for the field:
1426 * adapter_type The adapter_type field describes the adapter/bus
1427 * configuration.
1428 */
1429#define BUS_ISA16_TYPE 0x0001 /* 16 bit adap in 16 bit (E)ISA slot */
1430#define BUS_ISA8_TYPE 0x0002 /* 8/16b adap in 8 bit XT/(E)ISA slot */
1431#define BUS_MCA_TYPE 0x0003 /* Micro Channel adapter */
1432
1433/*
1434 * Receive Mask definitions
1435 */
1436#define ACCEPT_MULTICAST 0x0001
1437#define ACCEPT_BROADCAST 0x0002
1438#define PROMISCUOUS_MODE 0x0004
1439#define ACCEPT_SOURCE_ROUTING 0x0008
1440#define ACCEPT_ERR_PACKETS 0x0010
1441#define ACCEPT_ATT_MAC_FRAMES 0x0020
1442#define ACCEPT_MULTI_PROM 0x0040
1443#define TRANSMIT_ONLY 0x0080
1444#define ACCEPT_EXT_MAC_FRAMES 0x0100
1445#define EARLY_RX_ENABLE 0x0200
1446#define PKT_SIZE_NOT_NEEDED 0x0400
1447#define ACCEPT_SOURCE_ROUTING_SPANNING 0x0808
1448
1449#define ACCEPT_ALL_MAC_FRAMES 0x0120
1450
1451/*
1452 * config_mode defs
1453 */
1454#define STORE_EEROM 0x0001 /* Store config in EEROM. */
1455#define STORE_REGS 0x0002 /* Store config in register set. */
1456
1457/*
1458 * equates for lmac_flags in adapter structure (Ethernet)
1459 */
1460#define MEM_DISABLE 0x0001
1461#define RX_STATUS_POLL 0x0002
1462#define USE_RE_BIT 0x0004
1463/*#define RESERVED 0x0008 */
1464/*#define RESERVED 0x0010 */
1465/*#define RESERVED 0x0020 */
1466/*#define RESERVED 0x0040 */
1467/*#define RESERVED 0x0080 */
1468/*#define RESERVED 0x0100 */
1469/*#define RESERVED 0x0200 */
1470/*#define RESERVED 0x0400 */
1471/*#define RESERVED 0x0800 */
1472/*#define RESERVED 0x1000 */
1473/*#define RESERVED 0x2000 */
1474/*#define RESERVED 0x4000 */
1475/*#define RESERVED 0x8000 */
1476
1477/* media_opts & media_set Fields bit defs for Ethernet ... */
1478#define MED_OPT_BNC 0x01
1479#define MED_OPT_UTP 0x02
1480#define MED_OPT_AUI 0x04
1481#define MED_OPT_10MB 0x08
1482#define MED_OPT_100MB 0x10
1483#define MED_OPT_S10 0x20
1484
1485/* media_opts & media_set Fields bit defs for Token Ring ... */
1486#define MED_OPT_4MB 0x08
1487#define MED_OPT_16MB 0x10
1488#define MED_OPT_STP 0x40
1489
1490#define MAX_8023_SIZE 1500 /* Max 802.3 size of frame. */
1491#define DEFAULT_ERX_VALUE 4 /* Number of 16-byte blocks for 790B early Rx. */
1492#define DEFAULT_ETX_VALUE 32 /* Number of bytes for 790B early Tx. */
1493#define DEFAULT_TX_RETRIES 3 /* Number of transmit retries */
1494#define LPBK_FRAME_SIZE 1024 /* Default loopback frame for Rx calibration test. */
1495#define MAX_LOOKAHEAD_SIZE 252 /* Max lookahead size for ethernet. */
1496
1497#define RW_MAC_STATE 0x1101
1498#define RW_SA_OF_LAST_AMP_OR_SMP 0x2803
1499#define RW_PHYSICAL_DROP_NUMBER 0x3B02
1500#define RW_UPSTREAM_NEIGHBOR_ADDRESS 0x3E03
1501#define RW_PRODUCT_INSTANCE_ID 0x4B09
1502
1503#define RW_TRC_STATUS_BLOCK 0x5412
1504
1505#define RW_MAC_ERROR_COUNTERS_NO_CLEAR 0x8006
1506#define RW_MAC_ERROR_COUNTER_CLEAR 0x7A06
1507#define RW_CONFIG_REGISTER_0 0xA001
1508#define RW_CONFIG_REGISTER_1 0xA101
1509#define RW_PRESCALE_TIMER_THRESHOLD 0xA201
1510#define RW_TPT_THRESHOLD 0xA301
1511#define RW_TQP_THRESHOLD 0xA401
1512#define RW_TNT_THRESHOLD 0xA501
1513#define RW_TBT_THRESHOLD 0xA601
1514#define RW_TSM_THRESHOLD 0xA701
1515#define RW_TAM_THRESHOLD 0xA801
1516#define RW_TBR_THRESHOLD 0xA901
1517#define RW_TER_THRESHOLD 0xAA01
1518#define RW_TGT_THRESHOLD 0xAB01
1519#define RW_THT_THRESHOLD 0xAC01
1520#define RW_TRR_THRESHOLD 0xAD01
1521#define RW_TVX_THRESHOLD 0xAE01
1522#define RW_INDIVIDUAL_MAC_ADDRESS 0xB003
1523
1524#define RW_INDIVIDUAL_GROUP_ADDRESS 0xB303 /* all of group addr */
1525#define RW_INDIVIDUAL_GROUP_ADDR_WORD_0 0xB301 /* 1st word of group addr */
1526#define RW_INDIVIDUAL_GROUP_ADDR 0xB402 /* 2nd-3rd word of group addr */
1527#define RW_FUNCTIONAL_ADDRESS 0xB603 /* all of functional addr */
1528#define RW_FUNCTIONAL_ADDR_WORD_0 0xB601 /* 1st word of func addr */
1529#define RW_FUNCTIONAL_ADDR 0xB702 /* 2nd-3rd word func addr */
1530
1531#define RW_BIT_SIGNIFICANT_GROUP_ADDR 0xB902
1532#define RW_SOURCE_RING_BRIDGE_NUMBER 0xBB01
1533#define RW_TARGET_RING_NUMBER 0xBC01
1534
1535#define RW_HIC_INTERRUPT_MASK 0xC601
1536
1537#define SOURCE_ROUTING_SPANNING_BITS 0x00C0 /* Spanning Tree Frames */
1538#define SOURCE_ROUTING_EXPLORER_BIT 0x0040 /* Explorer and Single Route */
1539
1540 /* write */
1541
1542#define CSR_MSK_ALL 0x80 // Bic 587 Only
1543#define CSR_MSKTINT 0x20
1544#define CSR_MSKCBUSY 0x10
1545#define CSR_CLRTINT 0x08
1546#define CSR_CLRCBUSY 0x04
1547#define CSR_WCSS 0x02
1548#define CSR_CA 0x01
1549
1550 /* read */
1551
1552#define CSR_TINT 0x20
1553#define CSR_CINT 0x10
1554#define CSR_TSTAT 0x08
1555#define CSR_CSTAT 0x04
1556#define CSR_FAULT 0x02
1557#define CSR_CBUSY 0x01
1558
1559#define LAAR_MEM16ENB 0x80
1560#define Zws16 0x20
1561
1562#define IRR_IEN 0x80
1563#define Zws8 0x01
1564
1565#define IMCCR_EIL 0x04
1566
1567typedef struct {
1568 __u8 ac; /* Access Control */
1569 __u8 fc; /* Frame Control */
1570 __u8 da[6]; /* Dest Addr */
1571 __u8 sa[6]; /* Source Addr */
1572
1573 __u16 vl; /* Vector Length */
1574 __u8 dc_sc; /* Dest/Source Class */
1575 __u8 vc; /* Vector Code */
1576 } MAC_HEADER;
1577
1578#define MAX_SUB_VECTOR_INFO (RX_DATA_BUFFER_SIZE - sizeof(MAC_HEADER) - 2)
1579
1580typedef struct
1581 {
1582 __u8 svl; /* Sub-vector Length */
1583 __u8 svi; /* Sub-vector Code */
1584 __u8 svv[MAX_SUB_VECTOR_INFO]; /* Sub-vector Info */
1585 } MAC_SUB_VECTOR;
1586
1587#endif /* __KERNEL__ */
1588#endif /* __LINUX_SMCTR_H */
diff --git a/drivers/net/tokenring/smctr_firmware.h b/drivers/net/tokenring/smctr_firmware.h
new file mode 100644
index 000000000000..53f2cbc817c9
--- /dev/null
+++ b/drivers/net/tokenring/smctr_firmware.h
@@ -0,0 +1,979 @@
1/*
2 * The firmware this driver downloads into the tokenring card is a
3 * separate program and is not GPL'd source code, even though the Linux
4 * side driver and the routine that loads this data into the card are.
5 *
6 * This firmware is licensed to you strictly for use in conjunction
7 * with the use of SMC TokenRing adapters. There is no waranty
8 * expressed or implied about its fitness for any purpose.
9 */
10
11/* smctr_firmware.h: SMC TokenRing driver firmware dump for Linux.
12 *
13 * Notes:
14 * - This is an 8K binary image. (MCT.BIN v6.3C1 03/01/95)
15 *
16 * Authors:
17 * - Jay Schulist <jschlst@samba.org>
18 */
19
20#include <linux/config.h>
21
22#if defined(CONFIG_SMCTR) || defined(CONFIG_SMCTR_MODULE)
23
24unsigned char smctr_code[] = {
25 0x0BC, 0x01D, 0x012, 0x03B, 0x063, 0x0B4, 0x0E9, 0x000,
26 0x000, 0x01F, 0x000, 0x001, 0x001, 0x000, 0x002, 0x005,
27 0x001, 0x000, 0x006, 0x003, 0x001, 0x000, 0x004, 0x009,
28 0x001, 0x000, 0x00A, 0x007, 0x001, 0x000, 0x008, 0x00B,
29 0x001, 0x000, 0x00C, 0x000, 0x000, 0x000, 0x000, 0x00F,
30 0x001, 0x000, 0x010, 0x00D, 0x001, 0x000, 0x00E, 0x013,
31 0x001, 0x000, 0x014, 0x011, 0x001, 0x000, 0x012, 0x000,
32 0x000, 0x005, 0x000, 0x015, 0x001, 0x000, 0x016, 0x019,
33 0x001, 0x000, 0x01A, 0x017, 0x001, 0x000, 0x018, 0x000,
34 0x000, 0x00E, 0x000, 0x000, 0x000, 0x001, 0x000, 0x000,
35 0x000, 0x004, 0x000, 0x01B, 0x001, 0x000, 0x01C, 0x000,
36 0x000, 0x007, 0x000, 0x000, 0x000, 0x00F, 0x000, 0x000,
37 0x000, 0x00B, 0x000, 0x01D, 0x001, 0x000, 0x01E, 0x000,
38 0x000, 0x008, 0x000, 0x000, 0x000, 0x002, 0x000, 0x000,
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215 0x009, 0x08A, 0x074, 0x02F, 0x07E, 0x041, 0x074, 0x01E,
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223 0x03A, 0x022, 0x0A0, 0x000, 0x06B, 0x0C1, 0x0D1, 0x054,
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227 0x036, 0x036, 0x065, 0x04F, 0x07A, 0x018, 0x055, 0x025,
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229 0x04C, 0x002, 0x06D, 0x03E, 0x071, 0x053, 0x0AF, 0x078,
230 0x0A9, 0x0D4, 0x0A6, 0x029, 0x0B1, 0x0BC, 0x0D9, 0x099,
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233 0x031, 0x0BC, 0x0D9, 0x099, 0x0B2, 0x08E, 0x066, 0x019,
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235 0x0C6, 0x0F5, 0x020, 0x0D3, 0x0E4, 0x07F, 0x04F, 0x09C,
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829 0x048, 0x0C8, 0x0D5, 0x047, 0x0D5, 0x015, 0x023, 0x023,
830 0x0E1, 0x017, 0x038, 0x034, 0x08C, 0x0BA, 0x04B, 0x07B,
831 0x0D4, 0x002, 0x0D2, 0x08C, 0x022, 0x0DC, 0x006, 0x0D5,
832 0x01F, 0x056, 0x01B, 0x032, 0x08C, 0x0A3, 0x05E, 0x071,
833 0x051, 0x01D, 0x020, 0x0CA, 0x026, 0x0A4, 0x031, 0x040,
834 0x0A9, 0x062, 0x0B0, 0x017, 0x0DF, 0x09E, 0x0F4, 0x0B7,
835 0x0C9, 0x040, 0x0C7, 0x078, 0x001, 0x081, 0x082, 0x0B8,
836 0x038, 0x039, 0x049, 0x01C, 0x026, 0x0C0, 0x05F, 0x070,
837 0x017, 0x0D4, 0x0AB, 0x0E1, 0x02A, 0x0F8, 0x04A, 0x0BE,
838 0x012, 0x0AF, 0x08F, 0x097, 0x04F, 0x0CB, 0x0A7, 0x001,
839 0x07D, 0x0DA, 0x080, 0x0AA, 0x091, 0x064, 0x07F, 0x04A,
840 0x081, 0x0D5, 0x022, 0x0C8, 0x0FE, 0x082, 0x080, 0x025,
841 0x048, 0x0B2, 0x03E, 0x0BB, 0x0DC, 0x035, 0x02E, 0x094,
842 0x007, 0x0E8, 0x08A, 0x09C, 0x003, 0x0E2, 0x04B, 0x0A5,
843 0x077, 0x0AB, 0x0B3, 0x032, 0x0E9, 0x04B, 0x0BD, 0x059,
844 0x086, 0x084, 0x097, 0x07A, 0x004, 0x0BA, 0x053, 0x0E1,
845 0x032, 0x0EF, 0x050, 0x0D4, 0x0E6, 0x035, 0x053, 0x0EB,
846 0x002, 0x09C, 0x0C7, 0x0D7, 0x07A, 0x0B3, 0x030, 0x0D2,
847 0x05D, 0x0EA, 0x002, 0x0E9, 0x044, 0x05D, 0x016, 0x028,
848 0x0C0, 0x02C, 0x0E0, 0x036, 0x091, 0x074, 0x045, 0x059,
849 0x018, 0x0D5, 0x04F, 0x0AC, 0x00A, 0x0C4, 0x035, 0x030,
850 0x08B, 0x038, 0x069, 0x02B, 0x0BD, 0x059, 0x098, 0x069,
851 0x02E, 0x0F5, 0x012, 0x0E9, 0x058, 0x067, 0x04A, 0x0EF,
852 0x050, 0x0D5, 0x08E, 0x03E, 0x01C, 0x0A4, 0x0B0, 0x0CE,
853 0x093, 0x021, 0x06E, 0x01A, 0x048, 0x01F, 0x0A2, 0x02A,
854 0x0C3, 0x00D, 0x057, 0x07A, 0x0B3, 0x00D, 0x009, 0x02E,
855 0x0F4, 0x043, 0x05D, 0x028, 0x08B, 0x083, 0x020, 0x092,
856 0x038, 0x04D, 0x080, 0x0BE, 0x0E0, 0x02F, 0x0AC, 0x017,
857 0x049, 0x0B3, 0x0A5, 0x082, 0x0E9, 0x03E, 0x0E9, 0x036,
858 0x074, 0x0E0, 0x02F, 0x0A6, 0x0CE, 0x09C, 0x005, 0x0F4,
859 0x0C2, 0x02C, 0x08C, 0x052, 0x057, 0x07A, 0x0D4, 0x08D,
860 0x048, 0x0FA, 0x0EF, 0x050, 0x0D5, 0x0AE, 0x035, 0x053,
861 0x0EB, 0x002, 0x086, 0x021, 0x0AA, 0x0EF, 0x056, 0x066,
862 0x01A, 0x04B, 0x0BD, 0x044, 0x0BA, 0x050, 0x0C4, 0x0E9,
863 0x053, 0x0EB, 0x002, 0x086, 0x081, 0x0F5, 0x0DE, 0x0A1,
864 0x0A8, 0x062, 0x01F, 0x05D, 0x0FE, 0x0A2, 0x05D, 0x029,
865 0x077, 0x0A8, 0x06A, 0x061, 0x08D, 0x040, 0x0FD, 0x011,
866 0x053, 0x00C, 0x06A, 0x0A7, 0x0D6, 0x005, 0x030, 0x0C7,
867 0x0D7, 0x07F, 0x0A9, 0x057, 0x04A, 0x05D, 0x0EB, 0x048,
868 0x01B, 0x00C, 0x07C, 0x08B, 0x09D, 0x08A, 0x053, 0x0EF,
869 0x066, 0x094, 0x0CA, 0x054, 0x0F5, 0x0A0, 0x0C6, 0x001,
870 0x06E, 0x003, 0x06A, 0x09F, 0x056, 0x076, 0x065, 0x032,
871 0x08B, 0x07B, 0x0D2, 0x0C5, 0x0A5, 0x060, 0x02F, 0x0AA,
872 0x07D, 0x065, 0x0A3, 0x000, 0x0B7, 0x001, 0x0B4, 0x0C8,
873 0x05A, 0x007, 0x08F, 0x0ED, 0x001, 0x0D5, 0x027, 0x091,
874 0x067, 0x001, 0x0B4, 0x08B, 0x09C, 0x054, 0x01C, 0x073,
875 0x0A8, 0x084, 0x05C, 0x0C1, 0x050, 0x0BF, 0x036, 0x056,
876 0x060, 0x0AB, 0x08C, 0x08B, 0x09C, 0x054, 0x01C, 0x073,
877 0x0A8, 0x084, 0x05C, 0x0C1, 0x050, 0x0BF, 0x036, 0x056,
878 0x06C, 0x005, 0x0F5, 0x053, 0x0D6, 0x0A2, 0x030, 0x00B,
879 0x029, 0x05B, 0x019, 0x0FC, 0x0F6, 0x094, 0x045, 0x0CF,
880 0x015, 0x00B, 0x0F3, 0x03C, 0x0B3, 0x02A, 0x07A, 0x0C5,
881 0x046, 0x001, 0x064, 0x08A, 0x031, 0x023, 0x09C, 0x00A,
882 0x05D, 0x0EA, 0x034, 0x033, 0x02E, 0x095, 0x0C7, 0x0CE,
883 0x02A, 0x04F, 0x0E6, 0x050, 0x020, 0x0B9, 0x031, 0x00C,
884 0x09B, 0x0EF, 0x039, 0x014, 0x045, 0x0CE, 0x045, 0x007,
885 0x01C, 0x0EA, 0x046, 0x087, 0x0AB, 0x01B, 0x036, 0x084,
886 0x0A7, 0x05E, 0x0AC, 0x096, 0x067, 0x052, 0x0B0, 0x017,
887 0x0DC, 0x0FE, 0x07B, 0x04A, 0x022, 0x0E7, 0x08A, 0x085,
888 0x0F9, 0x09E, 0x059, 0x097, 0x07A, 0x08D, 0x00C, 0x0CB,
889 0x0A5, 0x027, 0x0F3, 0x0A0, 0x044, 0x032, 0x060, 0x0B9,
890 0x037, 0x0DE, 0x072, 0x028, 0x08B, 0x09C, 0x08A, 0x00E,
891 0x039, 0x0D4, 0x08C, 0x005, 0x0F7, 0x0E7, 0x0B8, 0x02A,
892 0x0F9, 0x028, 0x018, 0x0EF, 0x000, 0x030, 0x030, 0x057,
893 0x007, 0x044, 0x00A, 0x050, 0x08F, 0x0F0, 0x073, 0x091,
894 0x041, 0x01F, 0x03A, 0x090, 0x045, 0x0C0, 0x0BB, 0x018,
895 0x0E1, 0x036, 0x002, 0x0FB, 0x0FB, 0x09E, 0x002, 0x0FA,
896 0x0EE, 0x0E7, 0x0F5, 0x0CF, 0x001, 0x07D, 0x010, 0x05C,
897 0x0F0, 0x017, 0x0D1, 0x005, 0x0CF, 0x001, 0x07D, 0x053,
898 0x0EB, 0x02D, 0x018, 0x005, 0x0B8, 0x00D, 0x0A6, 0x042,
899 0x0DC, 0x006, 0x0D3, 0x017, 0x035, 0x0A8, 0x08B, 0x09C,
900 0x00A, 0x00E, 0x039, 0x0D4, 0x00C, 0x0FE, 0x07B, 0x04A,
901 0x022, 0x0E6, 0x055, 0x00B, 0x0F3, 0x031, 0x0B3, 0x060,
902 0x02F, 0x0BC, 0x07C, 0x0E2, 0x0A4, 0x0FE, 0x065, 0x051,
903 0x017, 0x038, 0x014, 0x01C, 0x073, 0x0A8, 0x019, 0x0FC,
904 0x0F6, 0x094, 0x045, 0x0CC, 0x0AA, 0x017, 0x0E6, 0x063,
905 0x066, 0x00A, 0x0B8, 0x0CC, 0x085, 0x0A1, 0x058, 0x0F6,
906 0x0A2, 0x035, 0x048, 0x048, 0x07F, 0x04A, 0x089, 0x095,
907 0x021, 0x021, 0x0FD, 0x005, 0x002, 0x054, 0x09E, 0x045,
908 0x091, 0x00E, 0x03C, 0x005, 0x0F5, 0x007, 0x040, 0x055,
909 0x048, 0x052, 0x03E, 0x086, 0x0A0, 0x075, 0x048, 0x052,
910 0x03E, 0x0B5, 0x000, 0x04A, 0x09C, 0x000, 0x06B, 0x0C7,
911 0x0CE, 0x045, 0x027, 0x0F3, 0x02A, 0x084, 0x037, 0x035,
912 0x0DE, 0x0A0, 0x0AB, 0x023, 0x01A, 0x0AE, 0x0F5, 0x083,
913 0x059, 0x018, 0x0D7, 0x043, 0x0DE, 0x02A, 0x0D0, 0x094,
914 0x0EB, 0x0DE, 0x005, 0x03A, 0x095, 0x09F, 0x0CC, 0x0C3,
915 0x020, 0x045, 0x0CC, 0x0AA, 0x017, 0x0E6, 0x066, 0x0CC,
916 0x043, 0x026, 0x04F, 0x0E7, 0x041, 0x022, 0x02E, 0x070,
917 0x068, 0x038, 0x0E7, 0x053, 0x0E0, 0x02F, 0x0AB, 0x0BC,
918 0x012, 0x0D2, 0x0E9, 0x058, 0x00B, 0x0EA, 0x0A7, 0x0AD,
919 0x045, 0x0A1, 0x01F, 0x0C0, 0x05F, 0x078, 0x039, 0x0C8,
920 0x0A0, 0x08F, 0x09D, 0x048, 0x01C, 0x024, 0x0EE, 0x0C7,
921 0x080, 0x0BE, 0x0BA, 0x0F5, 0x06D, 0x066, 0x049, 0x077,
922 0x00D, 0x04E, 0x0A5, 0x030, 0x009, 0x0B4, 0x0F9, 0x0C5,
923 0x043, 0x00F, 0x038, 0x0A9, 0x03F, 0x09D, 0x002, 0x0FB,
924 0x0CE, 0x045, 0x011, 0x073, 0x091, 0x041, 0x0C7, 0x03A,
925 0x091, 0x09F, 0x0CF, 0x069, 0x044, 0x05C, 0x0F1, 0x050,
926 0x0BF, 0x033, 0x0CB, 0x032, 0x0A7, 0x0AC, 0x054, 0x090,
927 0x08D, 0x044, 0x08E, 0x070, 0x029, 0x077, 0x0A8, 0x0D0,
928 0x0CC, 0x0BA, 0x056, 0x0B0, 0x0B2, 0x09D, 0x08C, 0x086,
929 0x04C, 0x017, 0x026, 0x077, 0x026, 0x01C, 0x027, 0x01C,
930 0x024, 0x09E, 0x023, 0x061, 0x0BE, 0x08E, 0x012, 0x04F,
931 0x011, 0x087, 0x01C, 0x0EA, 0x05C, 0x005, 0x0F5, 0x0D7,
932 0x0B8, 0x06A, 0x075, 0x029, 0x077, 0x0AB, 0x00D, 0x099,
933 0x074, 0x0A5, 0x04F, 0x072, 0x0A0, 0x0AA, 0x04A, 0x0C6,
934 0x0F3, 0x066, 0x066, 0x0C6, 0x039, 0x082, 0x0AF, 0x075,
935 0x0A6, 0x06F, 0x014, 0x06B, 0x0CE, 0x005, 0x070, 0x073,
936 0x096, 0x082, 0x03E, 0x075, 0x028, 0x0E1, 0x03A, 0x0A7,
937 0x0AD, 0x044, 0x060, 0x016, 0x052, 0x0B6, 0x01D, 0x07A,
938 0x0B6, 0x0B3, 0x024, 0x0BB, 0x086, 0x0A7, 0x052, 0x098,
939 0x004, 0x0DA, 0x07C, 0x0E2, 0x0A1, 0x087, 0x09C, 0x055,
940 0x0F7, 0x09C, 0x0B5, 0x0AC, 0x02C, 0x095, 0x033, 0x0B9,
941 0x031, 0x005, 0x0D9, 0x053, 0x0D6, 0x0A2, 0x030, 0x00B,
942 0x029, 0x05B, 0x002, 0x02E, 0x061, 0x05A, 0x017, 0x0E6,
943 0x09C, 0x0B3, 0x02A, 0x07A, 0x0C5, 0x040, 0x021, 0x0A8,
944 0x091, 0x0CE, 0x005, 0x027, 0x0F3, 0x0A5, 0x088, 0x064,
945 0x0C1, 0x072, 0x065, 0x04F, 0x058, 0x014, 0x00C, 0x08D,
946 0x07E, 0x0F3, 0x081, 0x044, 0x05C, 0x0EF, 0x041, 0x0C7,
947 0x03A, 0x0BE, 0x002, 0x0FA, 0x0A9, 0x0EA, 0x0CE, 0x0CC,
948 0x0A9, 0x029, 0x053, 0x0D6, 0x0A2, 0x046, 0x047, 0x0DD,
949 0x07A, 0x0C0, 0x0A3, 0x000, 0x086, 0x0E2, 0x09B, 0x029,
950 0x078, 0x08B, 0x081, 0x009, 0x098, 0x070, 0x09B, 0x029,
951 0x079, 0x05D, 0x0D9, 0x072, 0x0ED, 0x094, 0x0BC, 0x0B9,
952 0x076, 0x013, 0x03B, 0x02A, 0x05D, 0x0B2, 0x097, 0x095,
953 0x02E, 0x0D9, 0x04B, 0x0CA, 0x07D, 0x05B, 0x059, 0x094,
954 0x0CA, 0x01C, 0x024, 0x0EE, 0x0C7, 0x094, 0x0BC, 0x0C0,
955 0x026, 0x0D3, 0x0E7, 0x015, 0x00C, 0x03C, 0x0E2, 0x0AC,
956 0x0FE, 0x07B, 0x04A, 0x022, 0x0E7, 0x08A, 0x085, 0x0F9,
957 0x09E, 0x059, 0x097, 0x07A, 0x08D, 0x00C, 0x0CB, 0x0A5,
958 0x027, 0x0F3, 0x0A0, 0x041, 0x072, 0x062, 0x019, 0x037,
959 0x0DE, 0x070, 0x028, 0x08B, 0x09C, 0x08A, 0x00E, 0x039,
960 0x0D4, 0x08D, 0x00F, 0x056, 0x036, 0x06D, 0x009, 0x04E,
961 0x0BD, 0x059, 0x02C, 0x0CE, 0x0A5, 0x06B, 0x00B, 0x022,
962 0x0D9, 0x09D, 0x0C9, 0x0B2, 0x097, 0x0BE, 0x0F3, 0x081,
963 0x04A, 0x07D, 0x065, 0x0A3, 0x000, 0x093, 0x08F, 0x067,
964 0x029, 0x078, 0x0C2, 0x04D, 0x0C1, 0x0D1, 0x006, 0x082,
965 0x031, 0x0AF, 0x007, 0x038, 0x034, 0x011, 0x0F3, 0x0A8,
966 0x02A, 0x09E, 0x0A8, 0x066, 0x01A, 0x0A4, 0x0A5, 0x04F,
967 0x05A, 0x00C, 0x011, 0x08F, 0x0AA, 0x07B, 0x0D0, 0x065,
968 0x049, 0x045, 0x0BD, 0x0E9, 0x062, 0x0D2, 0x0B1, 0x09E,
969 0x06C, 0x0CC, 0x0C6, 0x019, 0x087, 0x009, 0x0C3, 0x08E,
970 0x075, 0x041, 0x01F, 0x03A, 0x0A5, 0x013, 0x0D5, 0x055,
971 0x055, 0x055, 0x055, 0x055, 0x055, 0x055, 0x055, 0x055,
972 0x055, 0x055, 0x055, 0x055, 0x055, 0x055, 0x055, 0x055,
973 0x055, 0x055, 0x055, 0x055, 0x055, 0x055, 0x055, 0x055,
974 0x055, 0x055, 0x055, 0x055, 0x055, 0x055, 0x055, 0x055,
975 0x055, 0x055, 0x055, 0x055, 0x055, 0x055, 0x055, 0x055,
976 0x055, 0x055, 0x055, 0x05A, 0x0CC, 0x090
977 };
978
979#endif /* defined(CONFIG_SMCTR) || defined(CONFIG_SMCTR_MODULE) */
diff --git a/drivers/net/tokenring/tms380tr.c b/drivers/net/tokenring/tms380tr.c
new file mode 100644
index 000000000000..df43b449e429
--- /dev/null
+++ b/drivers/net/tokenring/tms380tr.c
@@ -0,0 +1,2410 @@
1/*
2 * tms380tr.c: A network driver library for Texas Instruments TMS380-based
3 * Token Ring Adapters.
4 *
5 * Originally sktr.c: Written 1997 by Christoph Goos
6 *
7 * A fine result of the Linux Systems Network Architecture Project.
8 * http://www.linux-sna.org
9 *
10 * This software may be used and distributed according to the terms
11 * of the GNU General Public License, incorporated herein by reference.
12 *
13 * The following modules are currently available for card support:
14 * - tmspci (Generic PCI card support)
15 * - abyss (Madge PCI support)
16 * - tmsisa (SysKonnect TR4/16 ISA)
17 *
18 * Sources:
19 * - The hardware related parts of this driver are take from
20 * the SysKonnect Token Ring driver for Windows NT.
21 * - I used the IBM Token Ring driver 'ibmtr.c' as a base for this
22 * driver, as well as the 'skeleton.c' driver by Donald Becker.
23 * - Also various other drivers in the linux source tree were taken
24 * as samples for some tasks.
25 * - TI TMS380 Second-Generation Token Ring User's Guide
26 * - TI datasheets for respective chips
27 * - David Hein at Texas Instruments
28 * - Various Madge employees
29 *
30 * Maintainer(s):
31 * JS Jay Schulist jschlst@samba.org
32 * CG Christoph Goos cgoos@syskonnect.de
33 * AF Adam Fritzler mid@auk.cx
34 * MLP Mike Phillips phillim@amtrak.com
35 * JF Jochen Friedrich jochen@scram.de
36 *
37 * Modification History:
38 * 29-Aug-97 CG Created
39 * 04-Apr-98 CG Fixed problems caused by tok_timer_check
40 * 10-Apr-98 CG Fixed lockups at cable disconnection
41 * 27-May-98 JS Formated to Linux Kernel Format
42 * 31-May-98 JS Hacked in PCI support
43 * 16-Jun-98 JS Modulized for multiple cards with one driver
44 * Sep-99 AF Renamed to tms380tr (supports more than SK's)
45 * 23-Sep-99 AF Added Compaq and Thomas-Conrad PCI support
46 * Fixed a bug causing double copies on PCI
47 * Fixed for new multicast stuff (2.2/2.3)
48 * 25-Sep-99 AF Uped TPL_NUM from 3 to 9
49 * Removed extraneous 'No free TPL'
50 * 22-Dec-99 AF Added Madge PCI Mk2 support and generalized
51 * parts of the initilization procedure.
52 * 30-Dec-99 AF Turned tms380tr into a library ala 8390.
53 * Madge support is provided in the abyss module
54 * Generic PCI support is in the tmspci module.
55 * 30-Nov-00 JF Updated PCI code to support IO MMU via
56 * pci_map_static(). Alpha uses this MMU for ISA
57 * as well.
58 * 14-Jan-01 JF Fix DMA on ifdown/ifup sequences. Some
59 * cleanup.
60 * 13-Jan-02 JF Add spinlock to fix race condition.
61 * 09-Nov-02 JF Fixed printks to not SPAM the console during
62 * normal operation.
63 * 30-Dec-02 JF Removed incorrect __init from
64 * tms380tr_init_card.
65 *
66 * To do:
67 * 1. Multi/Broadcast packet handling (this may have fixed itself)
68 * 2. Write a sktrisa module that includes the old ISA support (done)
69 * 3. Allow modules to load their own microcode
70 * 4. Speed up the BUD process -- freezing the kernel for 3+sec is
71 * quite unacceptable.
72 * 5. Still a few remaining stalls when the cable is unplugged.
73 */
74
75#ifdef MODULE
76static const char version[] = "tms380tr.c: v1.10 30/12/2002 by Christoph Goos, Adam Fritzler\n";
77#endif
78
79#include <linux/module.h>
80#include <linux/kernel.h>
81#include <linux/types.h>
82#include <linux/fcntl.h>
83#include <linux/interrupt.h>
84#include <linux/ptrace.h>
85#include <linux/ioport.h>
86#include <linux/in.h>
87#include <linux/slab.h>
88#include <linux/string.h>
89#include <linux/time.h>
90#include <linux/errno.h>
91#include <linux/init.h>
92#include <linux/pci.h>
93#include <linux/delay.h>
94#include <linux/netdevice.h>
95#include <linux/etherdevice.h>
96#include <linux/skbuff.h>
97#include <linux/trdevice.h>
98#include <linux/firmware.h>
99#include <linux/bitops.h>
100
101#include <asm/system.h>
102#include <asm/io.h>
103#include <asm/dma.h>
104#include <asm/irq.h>
105#include <asm/uaccess.h>
106
107#include "tms380tr.h" /* Our Stuff */
108
109/* Use 0 for production, 1 for verification, 2 for debug, and
110 * 3 for very verbose debug.
111 */
112#ifndef TMS380TR_DEBUG
113#define TMS380TR_DEBUG 0
114#endif
115static unsigned int tms380tr_debug = TMS380TR_DEBUG;
116
117static struct device tms_device;
118
119/* Index to functions, as function prototypes.
120 * Alphabetical by function name.
121 */
122
123/* "A" */
124/* "B" */
125static int tms380tr_bringup_diags(struct net_device *dev);
126/* "C" */
127static void tms380tr_cancel_tx_queue(struct net_local* tp);
128static int tms380tr_chipset_init(struct net_device *dev);
129static void tms380tr_chk_irq(struct net_device *dev);
130static void tms380tr_chk_outstanding_cmds(struct net_device *dev);
131static void tms380tr_chk_src_addr(unsigned char *frame, unsigned char *hw_addr);
132static unsigned char tms380tr_chk_ssb(struct net_local *tp, unsigned short IrqType);
133int tms380tr_close(struct net_device *dev);
134static void tms380tr_cmd_status_irq(struct net_device *dev);
135/* "D" */
136static void tms380tr_disable_interrupts(struct net_device *dev);
137#if TMS380TR_DEBUG > 0
138static void tms380tr_dump(unsigned char *Data, int length);
139#endif
140/* "E" */
141static void tms380tr_enable_interrupts(struct net_device *dev);
142static void tms380tr_exec_cmd(struct net_device *dev, unsigned short Command);
143static void tms380tr_exec_sifcmd(struct net_device *dev, unsigned int WriteValue);
144/* "F" */
145/* "G" */
146static struct net_device_stats *tms380tr_get_stats(struct net_device *dev);
147/* "H" */
148static int tms380tr_hardware_send_packet(struct sk_buff *skb,
149 struct net_device *dev);
150/* "I" */
151static int tms380tr_init_adapter(struct net_device *dev);
152static void tms380tr_init_ipb(struct net_local *tp);
153static void tms380tr_init_net_local(struct net_device *dev);
154static void tms380tr_init_opb(struct net_device *dev);
155/* "M" */
156/* "O" */
157int tms380tr_open(struct net_device *dev);
158static void tms380tr_open_adapter(struct net_device *dev);
159/* "P" */
160/* "R" */
161static void tms380tr_rcv_status_irq(struct net_device *dev);
162static int tms380tr_read_ptr(struct net_device *dev);
163static void tms380tr_read_ram(struct net_device *dev, unsigned char *Data,
164 unsigned short Address, int Length);
165static int tms380tr_reset_adapter(struct net_device *dev);
166static void tms380tr_reset_interrupt(struct net_device *dev);
167static void tms380tr_ring_status_irq(struct net_device *dev);
168/* "S" */
169static int tms380tr_send_packet(struct sk_buff *skb, struct net_device *dev);
170static void tms380tr_set_multicast_list(struct net_device *dev);
171static int tms380tr_set_mac_address(struct net_device *dev, void *addr);
172/* "T" */
173static void tms380tr_timer_chk(unsigned long data);
174static void tms380tr_timer_end_wait(unsigned long data);
175static void tms380tr_tx_status_irq(struct net_device *dev);
176/* "U" */
177static void tms380tr_update_rcv_stats(struct net_local *tp,
178 unsigned char DataPtr[], unsigned int Length);
179/* "W" */
180void tms380tr_wait(unsigned long time);
181static void tms380tr_write_rpl_status(RPL *rpl, unsigned int Status);
182static void tms380tr_write_tpl_status(TPL *tpl, unsigned int Status);
183
184#define SIFREADB(reg) (((struct net_local *)dev->priv)->sifreadb(dev, reg))
185#define SIFWRITEB(val, reg) (((struct net_local *)dev->priv)->sifwriteb(dev, val, reg))
186#define SIFREADW(reg) (((struct net_local *)dev->priv)->sifreadw(dev, reg))
187#define SIFWRITEW(val, reg) (((struct net_local *)dev->priv)->sifwritew(dev, val, reg))
188
189
190
191#if 0 /* TMS380TR_DEBUG > 0 */
192static int madgemc_sifprobe(struct net_device *dev)
193{
194 unsigned char old, chk1, chk2;
195
196 old = SIFREADB(SIFADR); /* Get the old SIFADR value */
197
198 chk1 = 0; /* Begin with check value 0 */
199 do {
200 madgemc_setregpage(dev, 0);
201 /* Write new SIFADR value */
202 SIFWRITEB(chk1, SIFADR);
203 chk2 = SIFREADB(SIFADR);
204 if (chk2 != chk1)
205 return -1;
206
207 madgemc_setregpage(dev, 1);
208 /* Read, invert and write */
209 chk2 = SIFREADB(SIFADD);
210 if (chk2 != chk1)
211 return -1;
212
213 madgemc_setregpage(dev, 0);
214 chk2 ^= 0x0FE;
215 SIFWRITEB(chk2, SIFADR);
216
217 /* Read, invert and compare */
218 madgemc_setregpage(dev, 1);
219 chk2 = SIFREADB(SIFADD);
220 madgemc_setregpage(dev, 0);
221 chk2 ^= 0x0FE;
222
223 if(chk1 != chk2)
224 return (-1); /* No adapter */
225 chk1 -= 2;
226 } while(chk1 != 0); /* Repeat 128 times (all byte values) */
227
228 madgemc_setregpage(dev, 0); /* sanity */
229 /* Restore the SIFADR value */
230 SIFWRITEB(old, SIFADR);
231
232 return (0);
233}
234#endif
235
236/*
237 * Open/initialize the board. This is called sometime after
238 * booting when the 'ifconfig' program is run.
239 *
240 * This routine should set everything up anew at each open, even
241 * registers that "should" only need to be set once at boot, so that
242 * there is non-reboot way to recover if something goes wrong.
243 */
244int tms380tr_open(struct net_device *dev)
245{
246 struct net_local *tp = netdev_priv(dev);
247 int err;
248
249 /* init the spinlock */
250 spin_lock_init(&tp->lock);
251 init_timer(&tp->timer);
252
253 /* Reset the hardware here. Don't forget to set the station address. */
254
255#ifdef CONFIG_ISA
256 if(dev->dma > 0)
257 {
258 unsigned long flags=claim_dma_lock();
259 disable_dma(dev->dma);
260 set_dma_mode(dev->dma, DMA_MODE_CASCADE);
261 enable_dma(dev->dma);
262 release_dma_lock(flags);
263 }
264#endif
265
266 err = tms380tr_chipset_init(dev);
267 if(err)
268 {
269 printk(KERN_INFO "%s: Chipset initialization error\n",
270 dev->name);
271 return (-1);
272 }
273
274 tp->timer.expires = jiffies + 30*HZ;
275 tp->timer.function = tms380tr_timer_end_wait;
276 tp->timer.data = (unsigned long)dev;
277 add_timer(&tp->timer);
278
279 printk(KERN_DEBUG "%s: Adapter RAM size: %dK\n",
280 dev->name, tms380tr_read_ptr(dev));
281
282 tms380tr_enable_interrupts(dev);
283 tms380tr_open_adapter(dev);
284
285 netif_start_queue(dev);
286
287 /* Wait for interrupt from hardware. If interrupt does not come,
288 * there will be a timeout from the timer.
289 */
290 tp->Sleeping = 1;
291 interruptible_sleep_on(&tp->wait_for_tok_int);
292 del_timer(&tp->timer);
293
294 /* If AdapterVirtOpenFlag is 1, the adapter is now open for use */
295 if(tp->AdapterVirtOpenFlag == 0)
296 {
297 tms380tr_disable_interrupts(dev);
298 return (-1);
299 }
300
301 tp->StartTime = jiffies;
302
303 /* Start function control timer */
304 tp->timer.expires = jiffies + 2*HZ;
305 tp->timer.function = tms380tr_timer_chk;
306 tp->timer.data = (unsigned long)dev;
307 add_timer(&tp->timer);
308
309 return (0);
310}
311
312/*
313 * Timeout function while waiting for event
314 */
315static void tms380tr_timer_end_wait(unsigned long data)
316{
317 struct net_device *dev = (struct net_device*)data;
318 struct net_local *tp = netdev_priv(dev);
319
320 if(tp->Sleeping)
321 {
322 tp->Sleeping = 0;
323 wake_up_interruptible(&tp->wait_for_tok_int);
324 }
325
326 return;
327}
328
329/*
330 * Initialize the chipset
331 */
332static int tms380tr_chipset_init(struct net_device *dev)
333{
334 struct net_local *tp = netdev_priv(dev);
335 int err;
336
337 tms380tr_init_ipb(tp);
338 tms380tr_init_opb(dev);
339 tms380tr_init_net_local(dev);
340
341 if(tms380tr_debug > 3)
342 printk(KERN_DEBUG "%s: Resetting adapter...\n", dev->name);
343 err = tms380tr_reset_adapter(dev);
344 if(err < 0)
345 return (-1);
346
347 if(tms380tr_debug > 3)
348 printk(KERN_DEBUG "%s: Bringup diags...\n", dev->name);
349 err = tms380tr_bringup_diags(dev);
350 if(err < 0)
351 return (-1);
352
353 if(tms380tr_debug > 3)
354 printk(KERN_DEBUG "%s: Init adapter...\n", dev->name);
355 err = tms380tr_init_adapter(dev);
356 if(err < 0)
357 return (-1);
358
359 if(tms380tr_debug > 3)
360 printk(KERN_DEBUG "%s: Done!\n", dev->name);
361 return (0);
362}
363
364/*
365 * Initializes the net_local structure.
366 */
367static void tms380tr_init_net_local(struct net_device *dev)
368{
369 struct net_local *tp = netdev_priv(dev);
370 int i;
371 dma_addr_t dmabuf;
372
373 tp->scb.CMD = 0;
374 tp->scb.Parm[0] = 0;
375 tp->scb.Parm[1] = 0;
376
377 tp->ssb.STS = 0;
378 tp->ssb.Parm[0] = 0;
379 tp->ssb.Parm[1] = 0;
380 tp->ssb.Parm[2] = 0;
381
382 tp->CMDqueue = 0;
383
384 tp->AdapterOpenFlag = 0;
385 tp->AdapterVirtOpenFlag = 0;
386 tp->ScbInUse = 0;
387 tp->OpenCommandIssued = 0;
388 tp->ReOpenInProgress = 0;
389 tp->HaltInProgress = 0;
390 tp->TransmitHaltScheduled = 0;
391 tp->LobeWireFaultLogged = 0;
392 tp->LastOpenStatus = 0;
393 tp->MaxPacketSize = DEFAULT_PACKET_SIZE;
394
395 /* Create circular chain of transmit lists */
396 for (i = 0; i < TPL_NUM; i++)
397 {
398 tp->Tpl[i].NextTPLAddr = htonl(((char *)(&tp->Tpl[(i+1) % TPL_NUM]) - (char *)tp) + tp->dmabuffer); /* DMA buffer may be MMU driven */
399 tp->Tpl[i].Status = 0;
400 tp->Tpl[i].FrameSize = 0;
401 tp->Tpl[i].FragList[0].DataCount = 0;
402 tp->Tpl[i].FragList[0].DataAddr = 0;
403 tp->Tpl[i].NextTPLPtr = &tp->Tpl[(i+1) % TPL_NUM];
404 tp->Tpl[i].MData = NULL;
405 tp->Tpl[i].TPLIndex = i;
406 tp->Tpl[i].DMABuff = 0;
407 tp->Tpl[i].BusyFlag = 0;
408 }
409
410 tp->TplFree = tp->TplBusy = &tp->Tpl[0];
411
412 /* Create circular chain of receive lists */
413 for (i = 0; i < RPL_NUM; i++)
414 {
415 tp->Rpl[i].NextRPLAddr = htonl(((char *)(&tp->Rpl[(i+1) % RPL_NUM]) - (char *)tp) + tp->dmabuffer); /* DMA buffer may be MMU driven */
416 tp->Rpl[i].Status = (RX_VALID | RX_START_FRAME | RX_END_FRAME | RX_FRAME_IRQ);
417 tp->Rpl[i].FrameSize = 0;
418 tp->Rpl[i].FragList[0].DataCount = cpu_to_be16((unsigned short)tp->MaxPacketSize);
419
420 /* Alloc skb and point adapter to data area */
421 tp->Rpl[i].Skb = dev_alloc_skb(tp->MaxPacketSize);
422 tp->Rpl[i].DMABuff = 0;
423
424 /* skb == NULL ? then use local buffer */
425 if(tp->Rpl[i].Skb == NULL)
426 {
427 tp->Rpl[i].SkbStat = SKB_UNAVAILABLE;
428 tp->Rpl[i].FragList[0].DataAddr = htonl(((char *)tp->LocalRxBuffers[i] - (char *)tp) + tp->dmabuffer);
429 tp->Rpl[i].MData = tp->LocalRxBuffers[i];
430 }
431 else /* SKB != NULL */
432 {
433 tp->Rpl[i].Skb->dev = dev;
434 skb_put(tp->Rpl[i].Skb, tp->MaxPacketSize);
435
436 /* data unreachable for DMA ? then use local buffer */
437 dmabuf = pci_map_single(tp->pdev, tp->Rpl[i].Skb->data, tp->MaxPacketSize, PCI_DMA_FROMDEVICE);
438 if(tp->dmalimit && (dmabuf + tp->MaxPacketSize > tp->dmalimit))
439 {
440 tp->Rpl[i].SkbStat = SKB_DATA_COPY;
441 tp->Rpl[i].FragList[0].DataAddr = htonl(((char *)tp->LocalRxBuffers[i] - (char *)tp) + tp->dmabuffer);
442 tp->Rpl[i].MData = tp->LocalRxBuffers[i];
443 }
444 else /* DMA directly in skb->data */
445 {
446 tp->Rpl[i].SkbStat = SKB_DMA_DIRECT;
447 tp->Rpl[i].FragList[0].DataAddr = htonl(dmabuf);
448 tp->Rpl[i].MData = tp->Rpl[i].Skb->data;
449 tp->Rpl[i].DMABuff = dmabuf;
450 }
451 }
452
453 tp->Rpl[i].NextRPLPtr = &tp->Rpl[(i+1) % RPL_NUM];
454 tp->Rpl[i].RPLIndex = i;
455 }
456
457 tp->RplHead = &tp->Rpl[0];
458 tp->RplTail = &tp->Rpl[RPL_NUM-1];
459 tp->RplTail->Status = (RX_START_FRAME | RX_END_FRAME | RX_FRAME_IRQ);
460
461 return;
462}
463
464/*
465 * Initializes the initialisation parameter block.
466 */
467static void tms380tr_init_ipb(struct net_local *tp)
468{
469 tp->ipb.Init_Options = BURST_MODE;
470 tp->ipb.CMD_Status_IV = 0;
471 tp->ipb.TX_IV = 0;
472 tp->ipb.RX_IV = 0;
473 tp->ipb.Ring_Status_IV = 0;
474 tp->ipb.SCB_Clear_IV = 0;
475 tp->ipb.Adapter_CHK_IV = 0;
476 tp->ipb.RX_Burst_Size = BURST_SIZE;
477 tp->ipb.TX_Burst_Size = BURST_SIZE;
478 tp->ipb.DMA_Abort_Thrhld = DMA_RETRIES;
479 tp->ipb.SCB_Addr = 0;
480 tp->ipb.SSB_Addr = 0;
481
482 return;
483}
484
485/*
486 * Initializes the open parameter block.
487 */
488static void tms380tr_init_opb(struct net_device *dev)
489{
490 struct net_local *tp;
491 unsigned long Addr;
492 unsigned short RplSize = RPL_SIZE;
493 unsigned short TplSize = TPL_SIZE;
494 unsigned short BufferSize = BUFFER_SIZE;
495 int i;
496
497 tp = netdev_priv(dev);
498
499 tp->ocpl.OPENOptions = 0;
500 tp->ocpl.OPENOptions |= ENABLE_FULL_DUPLEX_SELECTION;
501 tp->ocpl.FullDuplex = 0;
502 tp->ocpl.FullDuplex |= OPEN_FULL_DUPLEX_OFF;
503
504 /*
505 * Set node address
506 *
507 * We go ahead and put it in the OPB even though on
508 * most of the generic adapters this isn't required.
509 * Its simpler this way. -- ASF
510 */
511 for (i=0;i<6;i++)
512 tp->ocpl.NodeAddr[i] = ((unsigned char *)dev->dev_addr)[i];
513
514 tp->ocpl.GroupAddr = 0;
515 tp->ocpl.FunctAddr = 0;
516 tp->ocpl.RxListSize = cpu_to_be16((unsigned short)RplSize);
517 tp->ocpl.TxListSize = cpu_to_be16((unsigned short)TplSize);
518 tp->ocpl.BufSize = cpu_to_be16((unsigned short)BufferSize);
519 tp->ocpl.Reserved = 0;
520 tp->ocpl.TXBufMin = TX_BUF_MIN;
521 tp->ocpl.TXBufMax = TX_BUF_MAX;
522
523 Addr = htonl(((char *)tp->ProductID - (char *)tp) + tp->dmabuffer);
524
525 tp->ocpl.ProdIDAddr[0] = LOWORD(Addr);
526 tp->ocpl.ProdIDAddr[1] = HIWORD(Addr);
527
528 return;
529}
530
531/*
532 * Send OPEN command to adapter
533 */
534static void tms380tr_open_adapter(struct net_device *dev)
535{
536 struct net_local *tp = netdev_priv(dev);
537
538 if(tp->OpenCommandIssued)
539 return;
540
541 tp->OpenCommandIssued = 1;
542 tms380tr_exec_cmd(dev, OC_OPEN);
543
544 return;
545}
546
547/*
548 * Clear the adapter's interrupt flag. Clear system interrupt enable
549 * (SINTEN): disable adapter to system interrupts.
550 */
551static void tms380tr_disable_interrupts(struct net_device *dev)
552{
553 SIFWRITEB(0, SIFACL);
554
555 return;
556}
557
558/*
559 * Set the adapter's interrupt flag. Set system interrupt enable
560 * (SINTEN): enable adapter to system interrupts.
561 */
562static void tms380tr_enable_interrupts(struct net_device *dev)
563{
564 SIFWRITEB(ACL_SINTEN, SIFACL);
565
566 return;
567}
568
569/*
570 * Put command in command queue, try to execute it.
571 */
572static void tms380tr_exec_cmd(struct net_device *dev, unsigned short Command)
573{
574 struct net_local *tp = netdev_priv(dev);
575
576 tp->CMDqueue |= Command;
577 tms380tr_chk_outstanding_cmds(dev);
578
579 return;
580}
581
582static void tms380tr_timeout(struct net_device *dev)
583{
584 /*
585 * If we get here, some higher level has decided we are broken.
586 * There should really be a "kick me" function call instead.
587 *
588 * Resetting the token ring adapter takes a long time so just
589 * fake transmission time and go on trying. Our own timeout
590 * routine is in tms380tr_timer_chk()
591 */
592 dev->trans_start = jiffies;
593 netif_wake_queue(dev);
594}
595
596/*
597 * Gets skb from system, queues it and checks if it can be sent
598 */
599static int tms380tr_send_packet(struct sk_buff *skb, struct net_device *dev)
600{
601 struct net_local *tp = netdev_priv(dev);
602 int err;
603
604 err = tms380tr_hardware_send_packet(skb, dev);
605 if(tp->TplFree->NextTPLPtr->BusyFlag)
606 netif_stop_queue(dev);
607 return (err);
608}
609
610/*
611 * Move frames into adapter tx queue
612 */
613static int tms380tr_hardware_send_packet(struct sk_buff *skb, struct net_device *dev)
614{
615 TPL *tpl;
616 short length;
617 unsigned char *buf;
618 unsigned long flags;
619 int i;
620 dma_addr_t dmabuf, newbuf;
621 struct net_local *tp = netdev_priv(dev);
622
623 /* Try to get a free TPL from the chain.
624 *
625 * NOTE: We *must* always leave one unused TPL in the chain,
626 * because otherwise the adapter might send frames twice.
627 */
628 spin_lock_irqsave(&tp->lock, flags);
629 if(tp->TplFree->NextTPLPtr->BusyFlag) { /* No free TPL */
630 if (tms380tr_debug > 0)
631 printk(KERN_DEBUG "%s: No free TPL\n", dev->name);
632 spin_unlock_irqrestore(&tp->lock, flags);
633 return 1;
634 }
635
636 dmabuf = 0;
637
638 /* Is buffer reachable for Busmaster-DMA? */
639
640 length = skb->len;
641 dmabuf = pci_map_single(tp->pdev, skb->data, length, PCI_DMA_TODEVICE);
642 if(tp->dmalimit && (dmabuf + length > tp->dmalimit)) {
643 /* Copy frame to local buffer */
644 pci_unmap_single(tp->pdev, dmabuf, length, PCI_DMA_TODEVICE);
645 dmabuf = 0;
646 i = tp->TplFree->TPLIndex;
647 buf = tp->LocalTxBuffers[i];
648 memcpy(buf, skb->data, length);
649 newbuf = ((char *)buf - (char *)tp) + tp->dmabuffer;
650 }
651 else {
652 /* Send direct from skb->data */
653 newbuf = dmabuf;
654 buf = skb->data;
655 }
656 /* Source address in packet? */
657 tms380tr_chk_src_addr(buf, dev->dev_addr);
658 tp->LastSendTime = jiffies;
659 tpl = tp->TplFree; /* Get the "free" TPL */
660 tpl->BusyFlag = 1; /* Mark TPL as busy */
661 tp->TplFree = tpl->NextTPLPtr;
662
663 /* Save the skb for delayed return of skb to system */
664 tpl->Skb = skb;
665 tpl->DMABuff = dmabuf;
666 tpl->FragList[0].DataCount = cpu_to_be16((unsigned short)length);
667 tpl->FragList[0].DataAddr = htonl(newbuf);
668
669 /* Write the data length in the transmit list. */
670 tpl->FrameSize = cpu_to_be16((unsigned short)length);
671 tpl->MData = buf;
672
673 /* Transmit the frame and set the status values. */
674 tms380tr_write_tpl_status(tpl, TX_VALID | TX_START_FRAME
675 | TX_END_FRAME | TX_PASS_SRC_ADDR
676 | TX_FRAME_IRQ);
677
678 /* Let adapter send the frame. */
679 tms380tr_exec_sifcmd(dev, CMD_TX_VALID);
680 spin_unlock_irqrestore(&tp->lock, flags);
681
682 return 0;
683}
684
685/*
686 * Write the given value to the 'Status' field of the specified TPL.
687 * NOTE: This function should be used whenever the status of any TPL must be
688 * modified by the driver, because the compiler may otherwise change the
689 * order of instructions such that writing the TPL status may be executed at
690 * an undesireable time. When this function is used, the status is always
691 * written when the function is called.
692 */
693static void tms380tr_write_tpl_status(TPL *tpl, unsigned int Status)
694{
695 tpl->Status = Status;
696}
697
698static void tms380tr_chk_src_addr(unsigned char *frame, unsigned char *hw_addr)
699{
700 unsigned char SRBit;
701
702 if((((unsigned long)frame[8]) & ~0x80) != 0) /* Compare 4 bytes */
703 return;
704 if((unsigned short)frame[12] != 0) /* Compare 2 bytes */
705 return;
706
707 SRBit = frame[8] & 0x80;
708 memcpy(&frame[8], hw_addr, 6);
709 frame[8] |= SRBit;
710
711 return;
712}
713
714/*
715 * The timer routine: Check if adapter still open and working, reopen if not.
716 */
717static void tms380tr_timer_chk(unsigned long data)
718{
719 struct net_device *dev = (struct net_device*)data;
720 struct net_local *tp = netdev_priv(dev);
721
722 if(tp->HaltInProgress)
723 return;
724
725 tms380tr_chk_outstanding_cmds(dev);
726 if(time_before(tp->LastSendTime + SEND_TIMEOUT, jiffies)
727 && (tp->TplFree != tp->TplBusy))
728 {
729 /* Anything to send, but stalled too long */
730 tp->LastSendTime = jiffies;
731 tms380tr_exec_cmd(dev, OC_CLOSE); /* Does reopen automatically */
732 }
733
734 tp->timer.expires = jiffies + 2*HZ;
735 add_timer(&tp->timer);
736
737 if(tp->AdapterOpenFlag || tp->ReOpenInProgress)
738 return;
739 tp->ReOpenInProgress = 1;
740 tms380tr_open_adapter(dev);
741
742 return;
743}
744
745/*
746 * The typical workload of the driver: Handle the network interface interrupts.
747 */
748irqreturn_t tms380tr_interrupt(int irq, void *dev_id, struct pt_regs *regs)
749{
750 struct net_device *dev = dev_id;
751 struct net_local *tp;
752 unsigned short irq_type;
753 int handled = 0;
754
755 if(dev == NULL) {
756 printk(KERN_INFO "%s: irq %d for unknown device.\n", dev->name, irq);
757 return IRQ_NONE;
758 }
759
760 tp = netdev_priv(dev);
761
762 irq_type = SIFREADW(SIFSTS);
763
764 while(irq_type & STS_SYSTEM_IRQ) {
765 handled = 1;
766 irq_type &= STS_IRQ_MASK;
767
768 if(!tms380tr_chk_ssb(tp, irq_type)) {
769 printk(KERN_DEBUG "%s: DATA LATE occurred\n", dev->name);
770 break;
771 }
772
773 switch(irq_type) {
774 case STS_IRQ_RECEIVE_STATUS:
775 tms380tr_reset_interrupt(dev);
776 tms380tr_rcv_status_irq(dev);
777 break;
778
779 case STS_IRQ_TRANSMIT_STATUS:
780 /* Check if TRANSMIT.HALT command is complete */
781 if(tp->ssb.Parm[0] & COMMAND_COMPLETE) {
782 tp->TransmitCommandActive = 0;
783 tp->TransmitHaltScheduled = 0;
784
785 /* Issue a new transmit command. */
786 tms380tr_exec_cmd(dev, OC_TRANSMIT);
787 }
788
789 tms380tr_reset_interrupt(dev);
790 tms380tr_tx_status_irq(dev);
791 break;
792
793 case STS_IRQ_COMMAND_STATUS:
794 /* The SSB contains status of last command
795 * other than receive/transmit.
796 */
797 tms380tr_cmd_status_irq(dev);
798 break;
799
800 case STS_IRQ_SCB_CLEAR:
801 /* The SCB is free for another command. */
802 tp->ScbInUse = 0;
803 tms380tr_chk_outstanding_cmds(dev);
804 break;
805
806 case STS_IRQ_RING_STATUS:
807 tms380tr_ring_status_irq(dev);
808 break;
809
810 case STS_IRQ_ADAPTER_CHECK:
811 tms380tr_chk_irq(dev);
812 break;
813
814 case STS_IRQ_LLC_STATUS:
815 printk(KERN_DEBUG "tms380tr: unexpected LLC status IRQ\n");
816 break;
817
818 case STS_IRQ_TIMER:
819 printk(KERN_DEBUG "tms380tr: unexpected Timer IRQ\n");
820 break;
821
822 case STS_IRQ_RECEIVE_PENDING:
823 printk(KERN_DEBUG "tms380tr: unexpected Receive Pending IRQ\n");
824 break;
825
826 default:
827 printk(KERN_DEBUG "Unknown Token Ring IRQ (0x%04x)\n", irq_type);
828 break;
829 }
830
831 /* Reset system interrupt if not already done. */
832 if(irq_type != STS_IRQ_TRANSMIT_STATUS
833 && irq_type != STS_IRQ_RECEIVE_STATUS) {
834 tms380tr_reset_interrupt(dev);
835 }
836
837 irq_type = SIFREADW(SIFSTS);
838 }
839
840 return IRQ_RETVAL(handled);
841}
842
843/*
844 * Reset the INTERRUPT SYSTEM bit and issue SSB CLEAR command.
845 */
846static void tms380tr_reset_interrupt(struct net_device *dev)
847{
848 struct net_local *tp = netdev_priv(dev);
849 SSB *ssb = &tp->ssb;
850
851 /*
852 * [Workaround for "Data Late"]
853 * Set all fields of the SSB to well-defined values so we can
854 * check if the adapter has written the SSB.
855 */
856
857 ssb->STS = (unsigned short) -1;
858 ssb->Parm[0] = (unsigned short) -1;
859 ssb->Parm[1] = (unsigned short) -1;
860 ssb->Parm[2] = (unsigned short) -1;
861
862 /* Free SSB by issuing SSB_CLEAR command after reading IRQ code
863 * and clear STS_SYSTEM_IRQ bit: enable adapter for further interrupts.
864 */
865 tms380tr_exec_sifcmd(dev, CMD_SSB_CLEAR | CMD_CLEAR_SYSTEM_IRQ);
866
867 return;
868}
869
870/*
871 * Check if the SSB has actually been written by the adapter.
872 */
873static unsigned char tms380tr_chk_ssb(struct net_local *tp, unsigned short IrqType)
874{
875 SSB *ssb = &tp->ssb; /* The address of the SSB. */
876
877 /* C 0 1 2 INTERRUPT CODE
878 * - - - - --------------
879 * 1 1 1 1 TRANSMIT STATUS
880 * 1 1 1 1 RECEIVE STATUS
881 * 1 ? ? 0 COMMAND STATUS
882 * 0 0 0 0 SCB CLEAR
883 * 1 1 0 0 RING STATUS
884 * 0 0 0 0 ADAPTER CHECK
885 *
886 * 0 = SSB field not affected by interrupt
887 * 1 = SSB field is affected by interrupt
888 *
889 * C = SSB ADDRESS +0: COMMAND
890 * 0 = SSB ADDRESS +2: STATUS 0
891 * 1 = SSB ADDRESS +4: STATUS 1
892 * 2 = SSB ADDRESS +6: STATUS 2
893 */
894
895 /* Check if this interrupt does use the SSB. */
896
897 if(IrqType != STS_IRQ_TRANSMIT_STATUS
898 && IrqType != STS_IRQ_RECEIVE_STATUS
899 && IrqType != STS_IRQ_COMMAND_STATUS
900 && IrqType != STS_IRQ_RING_STATUS)
901 {
902 return (1); /* SSB not involved. */
903 }
904
905 /* Note: All fields of the SSB have been set to all ones (-1) after it
906 * has last been used by the software (see DriverIsr()).
907 *
908 * Check if the affected SSB fields are still unchanged.
909 */
910
911 if(ssb->STS == (unsigned short) -1)
912 return (0); /* Command field not yet available. */
913 if(IrqType == STS_IRQ_COMMAND_STATUS)
914 return (1); /* Status fields not always affected. */
915 if(ssb->Parm[0] == (unsigned short) -1)
916 return (0); /* Status 1 field not yet available. */
917 if(IrqType == STS_IRQ_RING_STATUS)
918 return (1); /* Status 2 & 3 fields not affected. */
919
920 /* Note: At this point, the interrupt is either TRANSMIT or RECEIVE. */
921 if(ssb->Parm[1] == (unsigned short) -1)
922 return (0); /* Status 2 field not yet available. */
923 if(ssb->Parm[2] == (unsigned short) -1)
924 return (0); /* Status 3 field not yet available. */
925
926 return (1); /* All SSB fields have been written by the adapter. */
927}
928
929/*
930 * Evaluates the command results status in the SSB status field.
931 */
932static void tms380tr_cmd_status_irq(struct net_device *dev)
933{
934 struct net_local *tp = netdev_priv(dev);
935 unsigned short ssb_cmd, ssb_parm_0;
936 unsigned short ssb_parm_1;
937 char *open_err = "Open error -";
938 char *code_err = "Open code -";
939
940 /* Copy the ssb values to local variables */
941 ssb_cmd = tp->ssb.STS;
942 ssb_parm_0 = tp->ssb.Parm[0];
943 ssb_parm_1 = tp->ssb.Parm[1];
944
945 if(ssb_cmd == OPEN)
946 {
947 tp->Sleeping = 0;
948 if(!tp->ReOpenInProgress)
949 wake_up_interruptible(&tp->wait_for_tok_int);
950
951 tp->OpenCommandIssued = 0;
952 tp->ScbInUse = 0;
953
954 if((ssb_parm_0 & 0x00FF) == GOOD_COMPLETION)
955 {
956 /* Success, the adapter is open. */
957 tp->LobeWireFaultLogged = 0;
958 tp->AdapterOpenFlag = 1;
959 tp->AdapterVirtOpenFlag = 1;
960 tp->TransmitCommandActive = 0;
961 tms380tr_exec_cmd(dev, OC_TRANSMIT);
962 tms380tr_exec_cmd(dev, OC_RECEIVE);
963
964 if(tp->ReOpenInProgress)
965 tp->ReOpenInProgress = 0;
966
967 return;
968 }
969 else /* The adapter did not open. */
970 {
971 if(ssb_parm_0 & NODE_ADDR_ERROR)
972 printk(KERN_INFO "%s: Node address error\n",
973 dev->name);
974 if(ssb_parm_0 & LIST_SIZE_ERROR)
975 printk(KERN_INFO "%s: List size error\n",
976 dev->name);
977 if(ssb_parm_0 & BUF_SIZE_ERROR)
978 printk(KERN_INFO "%s: Buffer size error\n",
979 dev->name);
980 if(ssb_parm_0 & TX_BUF_COUNT_ERROR)
981 printk(KERN_INFO "%s: Tx buffer count error\n",
982 dev->name);
983 if(ssb_parm_0 & INVALID_OPEN_OPTION)
984 printk(KERN_INFO "%s: Invalid open option\n",
985 dev->name);
986 if(ssb_parm_0 & OPEN_ERROR)
987 {
988 /* Show the open phase. */
989 switch(ssb_parm_0 & OPEN_PHASES_MASK)
990 {
991 case LOBE_MEDIA_TEST:
992 if(!tp->LobeWireFaultLogged)
993 {
994 tp->LobeWireFaultLogged = 1;
995 printk(KERN_INFO "%s: %s Lobe wire fault (check cable !).\n", dev->name, open_err);
996 }
997 tp->ReOpenInProgress = 1;
998 tp->AdapterOpenFlag = 0;
999 tp->AdapterVirtOpenFlag = 1;
1000 tms380tr_open_adapter(dev);
1001 return;
1002
1003 case PHYSICAL_INSERTION:
1004 printk(KERN_INFO "%s: %s Physical insertion.\n", dev->name, open_err);
1005 break;
1006
1007 case ADDRESS_VERIFICATION:
1008 printk(KERN_INFO "%s: %s Address verification.\n", dev->name, open_err);
1009 break;
1010
1011 case PARTICIPATION_IN_RING_POLL:
1012 printk(KERN_INFO "%s: %s Participation in ring poll.\n", dev->name, open_err);
1013 break;
1014
1015 case REQUEST_INITIALISATION:
1016 printk(KERN_INFO "%s: %s Request initialisation.\n", dev->name, open_err);
1017 break;
1018
1019 case FULLDUPLEX_CHECK:
1020 printk(KERN_INFO "%s: %s Full duplex check.\n", dev->name, open_err);
1021 break;
1022
1023 default:
1024 printk(KERN_INFO "%s: %s Unknown open phase\n", dev->name, open_err);
1025 break;
1026 }
1027
1028 /* Show the open errors. */
1029 switch(ssb_parm_0 & OPEN_ERROR_CODES_MASK)
1030 {
1031 case OPEN_FUNCTION_FAILURE:
1032 printk(KERN_INFO "%s: %s OPEN_FUNCTION_FAILURE", dev->name, code_err);
1033 tp->LastOpenStatus =
1034 OPEN_FUNCTION_FAILURE;
1035 break;
1036
1037 case OPEN_SIGNAL_LOSS:
1038 printk(KERN_INFO "%s: %s OPEN_SIGNAL_LOSS\n", dev->name, code_err);
1039 tp->LastOpenStatus =
1040 OPEN_SIGNAL_LOSS;
1041 break;
1042
1043 case OPEN_TIMEOUT:
1044 printk(KERN_INFO "%s: %s OPEN_TIMEOUT\n", dev->name, code_err);
1045 tp->LastOpenStatus =
1046 OPEN_TIMEOUT;
1047 break;
1048
1049 case OPEN_RING_FAILURE:
1050 printk(KERN_INFO "%s: %s OPEN_RING_FAILURE\n", dev->name, code_err);
1051 tp->LastOpenStatus =
1052 OPEN_RING_FAILURE;
1053 break;
1054
1055 case OPEN_RING_BEACONING:
1056 printk(KERN_INFO "%s: %s OPEN_RING_BEACONING\n", dev->name, code_err);
1057 tp->LastOpenStatus =
1058 OPEN_RING_BEACONING;
1059 break;
1060
1061 case OPEN_DUPLICATE_NODEADDR:
1062 printk(KERN_INFO "%s: %s OPEN_DUPLICATE_NODEADDR\n", dev->name, code_err);
1063 tp->LastOpenStatus =
1064 OPEN_DUPLICATE_NODEADDR;
1065 break;
1066
1067 case OPEN_REQUEST_INIT:
1068 printk(KERN_INFO "%s: %s OPEN_REQUEST_INIT\n", dev->name, code_err);
1069 tp->LastOpenStatus =
1070 OPEN_REQUEST_INIT;
1071 break;
1072
1073 case OPEN_REMOVE_RECEIVED:
1074 printk(KERN_INFO "%s: %s OPEN_REMOVE_RECEIVED", dev->name, code_err);
1075 tp->LastOpenStatus =
1076 OPEN_REMOVE_RECEIVED;
1077 break;
1078
1079 case OPEN_FULLDUPLEX_SET:
1080 printk(KERN_INFO "%s: %s OPEN_FULLDUPLEX_SET\n", dev->name, code_err);
1081 tp->LastOpenStatus =
1082 OPEN_FULLDUPLEX_SET;
1083 break;
1084
1085 default:
1086 printk(KERN_INFO "%s: %s Unknown open err code", dev->name, code_err);
1087 tp->LastOpenStatus =
1088 OPEN_FUNCTION_FAILURE;
1089 break;
1090 }
1091 }
1092
1093 tp->AdapterOpenFlag = 0;
1094 tp->AdapterVirtOpenFlag = 0;
1095
1096 return;
1097 }
1098 }
1099 else
1100 {
1101 if(ssb_cmd != READ_ERROR_LOG)
1102 return;
1103
1104 /* Add values from the error log table to the MAC
1105 * statistics counters and update the errorlogtable
1106 * memory.
1107 */
1108 tp->MacStat.line_errors += tp->errorlogtable.Line_Error;
1109 tp->MacStat.burst_errors += tp->errorlogtable.Burst_Error;
1110 tp->MacStat.A_C_errors += tp->errorlogtable.ARI_FCI_Error;
1111 tp->MacStat.lost_frames += tp->errorlogtable.Lost_Frame_Error;
1112 tp->MacStat.recv_congest_count += tp->errorlogtable.Rx_Congest_Error;
1113 tp->MacStat.rx_errors += tp->errorlogtable.Rx_Congest_Error;
1114 tp->MacStat.frame_copied_errors += tp->errorlogtable.Frame_Copied_Error;
1115 tp->MacStat.token_errors += tp->errorlogtable.Token_Error;
1116 tp->MacStat.dummy1 += tp->errorlogtable.DMA_Bus_Error;
1117 tp->MacStat.dummy1 += tp->errorlogtable.DMA_Parity_Error;
1118 tp->MacStat.abort_delimiters += tp->errorlogtable.AbortDelimeters;
1119 tp->MacStat.frequency_errors += tp->errorlogtable.Frequency_Error;
1120 tp->MacStat.internal_errors += tp->errorlogtable.Internal_Error;
1121 }
1122
1123 return;
1124}
1125
1126/*
1127 * The inverse routine to tms380tr_open().
1128 */
1129int tms380tr_close(struct net_device *dev)
1130{
1131 struct net_local *tp = netdev_priv(dev);
1132 netif_stop_queue(dev);
1133
1134 del_timer(&tp->timer);
1135
1136 /* Flush the Tx and disable Rx here. */
1137
1138 tp->HaltInProgress = 1;
1139 tms380tr_exec_cmd(dev, OC_CLOSE);
1140 tp->timer.expires = jiffies + 1*HZ;
1141 tp->timer.function = tms380tr_timer_end_wait;
1142 tp->timer.data = (unsigned long)dev;
1143 add_timer(&tp->timer);
1144
1145 tms380tr_enable_interrupts(dev);
1146
1147 tp->Sleeping = 1;
1148 interruptible_sleep_on(&tp->wait_for_tok_int);
1149 tp->TransmitCommandActive = 0;
1150
1151 del_timer(&tp->timer);
1152 tms380tr_disable_interrupts(dev);
1153
1154#ifdef CONFIG_ISA
1155 if(dev->dma > 0)
1156 {
1157 unsigned long flags=claim_dma_lock();
1158 disable_dma(dev->dma);
1159 release_dma_lock(flags);
1160 }
1161#endif
1162
1163 SIFWRITEW(0xFF00, SIFCMD);
1164#if 0
1165 if(dev->dma > 0) /* what the? */
1166 SIFWRITEB(0xff, POSREG);
1167#endif
1168 tms380tr_cancel_tx_queue(tp);
1169
1170 return (0);
1171}
1172
1173/*
1174 * Get the current statistics. This may be called with the card open
1175 * or closed.
1176 */
1177static struct net_device_stats *tms380tr_get_stats(struct net_device *dev)
1178{
1179 struct net_local *tp = netdev_priv(dev);
1180
1181 return ((struct net_device_stats *)&tp->MacStat);
1182}
1183
1184/*
1185 * Set or clear the multicast filter for this adapter.
1186 */
1187static void tms380tr_set_multicast_list(struct net_device *dev)
1188{
1189 struct net_local *tp = netdev_priv(dev);
1190 unsigned int OpenOptions;
1191
1192 OpenOptions = tp->ocpl.OPENOptions &
1193 ~(PASS_ADAPTER_MAC_FRAMES
1194 | PASS_ATTENTION_FRAMES
1195 | PASS_BEACON_MAC_FRAMES
1196 | COPY_ALL_MAC_FRAMES
1197 | COPY_ALL_NON_MAC_FRAMES);
1198
1199 tp->ocpl.FunctAddr = 0;
1200
1201 if(dev->flags & IFF_PROMISC)
1202 /* Enable promiscuous mode */
1203 OpenOptions |= COPY_ALL_NON_MAC_FRAMES |
1204 COPY_ALL_MAC_FRAMES;
1205 else
1206 {
1207 if(dev->flags & IFF_ALLMULTI)
1208 {
1209 /* Disable promiscuous mode, use normal mode. */
1210 tp->ocpl.FunctAddr = 0xFFFFFFFF;
1211 }
1212 else
1213 {
1214 int i;
1215 struct dev_mc_list *mclist = dev->mc_list;
1216 for (i=0; i< dev->mc_count; i++)
1217 {
1218 ((char *)(&tp->ocpl.FunctAddr))[0] |=
1219 mclist->dmi_addr[2];
1220 ((char *)(&tp->ocpl.FunctAddr))[1] |=
1221 mclist->dmi_addr[3];
1222 ((char *)(&tp->ocpl.FunctAddr))[2] |=
1223 mclist->dmi_addr[4];
1224 ((char *)(&tp->ocpl.FunctAddr))[3] |=
1225 mclist->dmi_addr[5];
1226 mclist = mclist->next;
1227 }
1228 }
1229 tms380tr_exec_cmd(dev, OC_SET_FUNCT_ADDR);
1230 }
1231
1232 tp->ocpl.OPENOptions = OpenOptions;
1233 tms380tr_exec_cmd(dev, OC_MODIFY_OPEN_PARMS);
1234 return;
1235}
1236
1237/*
1238 * Wait for some time (microseconds)
1239 */
1240void tms380tr_wait(unsigned long time)
1241{
1242#if 0
1243 long tmp;
1244
1245 tmp = jiffies + time/(1000000/HZ);
1246 do {
1247 current->state = TASK_INTERRUPTIBLE;
1248 tmp = schedule_timeout(tmp);
1249 } while(time_after(tmp, jiffies));
1250#else
1251 udelay(time);
1252#endif
1253 return;
1254}
1255
1256/*
1257 * Write a command value to the SIFCMD register
1258 */
1259static void tms380tr_exec_sifcmd(struct net_device *dev, unsigned int WriteValue)
1260{
1261 unsigned short cmd;
1262 unsigned short SifStsValue;
1263 unsigned long loop_counter;
1264
1265 WriteValue = ((WriteValue ^ CMD_SYSTEM_IRQ) | CMD_INTERRUPT_ADAPTER);
1266 cmd = (unsigned short)WriteValue;
1267 loop_counter = 0,5 * 800000;
1268 do {
1269 SifStsValue = SIFREADW(SIFSTS);
1270 } while((SifStsValue & CMD_INTERRUPT_ADAPTER) && loop_counter--);
1271 SIFWRITEW(cmd, SIFCMD);
1272
1273 return;
1274}
1275
1276/*
1277 * Processes adapter hardware reset, halts adapter and downloads firmware,
1278 * clears the halt bit.
1279 */
1280static int tms380tr_reset_adapter(struct net_device *dev)
1281{
1282 struct net_local *tp = netdev_priv(dev);
1283 unsigned short *fw_ptr;
1284 unsigned short count, c, count2;
1285 const struct firmware *fw_entry = NULL;
1286
1287 strncpy(tms_device.bus_id,dev->name, BUS_ID_SIZE);
1288
1289 if (request_firmware(&fw_entry, "tms380tr.bin", &tms_device) != 0) {
1290 printk(KERN_ALERT "%s: firmware %s is missing, cannot start.\n",
1291 dev->name, "tms380tr.bin");
1292 return (-1);
1293 }
1294
1295 fw_ptr = (unsigned short *)fw_entry->data;
1296 count2 = fw_entry->size / 2;
1297
1298 /* Hardware adapter reset */
1299 SIFWRITEW(ACL_ARESET, SIFACL);
1300 tms380tr_wait(40);
1301
1302 c = SIFREADW(SIFACL);
1303 tms380tr_wait(20);
1304
1305 if(dev->dma == 0) /* For PCI adapters */
1306 {
1307 c &= ~(ACL_NSELOUT0 | ACL_NSELOUT1); /* Clear bits */
1308 if(tp->setnselout)
1309 c |= (*tp->setnselout)(dev);
1310 }
1311
1312 /* In case a command is pending - forget it */
1313 tp->ScbInUse = 0;
1314
1315 c &= ~ACL_ARESET; /* Clear adapter reset bit */
1316 c |= ACL_CPHALT; /* Halt adapter CPU, allow download */
1317 c |= ACL_BOOT;
1318 c |= ACL_SINTEN;
1319 c &= ~ACL_PSDMAEN; /* Clear pseudo dma bit */
1320 SIFWRITEW(c, SIFACL);
1321 tms380tr_wait(40);
1322
1323 count = 0;
1324 /* Download firmware via DIO interface: */
1325 do {
1326 if (count2 < 3) continue;
1327
1328 /* Download first address part */
1329 SIFWRITEW(*fw_ptr, SIFADX);
1330 fw_ptr++;
1331 count2--;
1332 /* Download second address part */
1333 SIFWRITEW(*fw_ptr, SIFADD);
1334 fw_ptr++;
1335 count2--;
1336
1337 if((count = *fw_ptr) != 0) /* Load loop counter */
1338 {
1339 fw_ptr++; /* Download block data */
1340 count2--;
1341 if (count > count2) continue;
1342
1343 for(; count > 0; count--)
1344 {
1345 SIFWRITEW(*fw_ptr, SIFINC);
1346 fw_ptr++;
1347 count2--;
1348 }
1349 }
1350 else /* Stop, if last block downloaded */
1351 {
1352 c = SIFREADW(SIFACL);
1353 c &= (~ACL_CPHALT | ACL_SINTEN);
1354
1355 /* Clear CPHALT and start BUD */
1356 SIFWRITEW(c, SIFACL);
1357 if (fw_entry)
1358 release_firmware(fw_entry);
1359 return (1);
1360 }
1361 } while(count == 0);
1362
1363 if (fw_entry)
1364 release_firmware(fw_entry);
1365 printk(KERN_INFO "%s: Adapter Download Failed\n", dev->name);
1366 return (-1);
1367}
1368
1369/*
1370 * Starts bring up diagnostics of token ring adapter and evaluates
1371 * diagnostic results.
1372 */
1373static int tms380tr_bringup_diags(struct net_device *dev)
1374{
1375 int loop_cnt, retry_cnt;
1376 unsigned short Status;
1377
1378 tms380tr_wait(HALF_SECOND);
1379 tms380tr_exec_sifcmd(dev, EXEC_SOFT_RESET);
1380 tms380tr_wait(HALF_SECOND);
1381
1382 retry_cnt = BUD_MAX_RETRIES; /* maximal number of retrys */
1383
1384 do {
1385 retry_cnt--;
1386 if(tms380tr_debug > 3)
1387 printk(KERN_DEBUG "BUD-Status: ");
1388 loop_cnt = BUD_MAX_LOOPCNT; /* maximum: three seconds*/
1389 do { /* Inspect BUD results */
1390 loop_cnt--;
1391 tms380tr_wait(HALF_SECOND);
1392 Status = SIFREADW(SIFSTS);
1393 Status &= STS_MASK;
1394
1395 if(tms380tr_debug > 3)
1396 printk(KERN_DEBUG " %04X \n", Status);
1397 /* BUD successfully completed */
1398 if(Status == STS_INITIALIZE)
1399 return (1);
1400 /* Unrecoverable hardware error, BUD not completed? */
1401 } while((loop_cnt > 0) && ((Status & (STS_ERROR | STS_TEST))
1402 != (STS_ERROR | STS_TEST)));
1403
1404 /* Error preventing completion of BUD */
1405 if(retry_cnt > 0)
1406 {
1407 printk(KERN_INFO "%s: Adapter Software Reset.\n",
1408 dev->name);
1409 tms380tr_exec_sifcmd(dev, EXEC_SOFT_RESET);
1410 tms380tr_wait(HALF_SECOND);
1411 }
1412 } while(retry_cnt > 0);
1413
1414 Status = SIFREADW(SIFSTS);
1415
1416 printk(KERN_INFO "%s: Hardware error\n", dev->name);
1417 /* Hardware error occurred! */
1418 Status &= 0x001f;
1419 if (Status & 0x0010)
1420 printk(KERN_INFO "%s: BUD Error: Timeout\n", dev->name);
1421 else if ((Status & 0x000f) > 6)
1422 printk(KERN_INFO "%s: BUD Error: Illegal Failure\n", dev->name);
1423 else
1424 printk(KERN_INFO "%s: Bring Up Diagnostics Error (%04X) occurred\n", dev->name, Status & 0x000f);
1425
1426 return (-1);
1427}
1428
1429/*
1430 * Copy initialisation data to adapter memory, beginning at address
1431 * 1:0A00; Starting DMA test and evaluating result bits.
1432 */
1433static int tms380tr_init_adapter(struct net_device *dev)
1434{
1435 struct net_local *tp = netdev_priv(dev);
1436
1437 const unsigned char SCB_Test[6] = {0x00, 0x00, 0xC1, 0xE2, 0xD4, 0x8B};
1438 const unsigned char SSB_Test[8] = {0xFF, 0xFF, 0xD1, 0xD7,
1439 0xC5, 0xD9, 0xC3, 0xD4};
1440 void *ptr = (void *)&tp->ipb;
1441 unsigned short *ipb_ptr = (unsigned short *)ptr;
1442 unsigned char *cb_ptr = (unsigned char *) &tp->scb;
1443 unsigned char *sb_ptr = (unsigned char *) &tp->ssb;
1444 unsigned short Status;
1445 int i, loop_cnt, retry_cnt;
1446
1447 /* Normalize: byte order low/high, word order high/low! (only IPB!) */
1448 tp->ipb.SCB_Addr = SWAPW(((char *)&tp->scb - (char *)tp) + tp->dmabuffer);
1449 tp->ipb.SSB_Addr = SWAPW(((char *)&tp->ssb - (char *)tp) + tp->dmabuffer);
1450
1451 if(tms380tr_debug > 3)
1452 {
1453 printk(KERN_DEBUG "%s: buffer (real): %lx\n", dev->name, (long) &tp->scb);
1454 printk(KERN_DEBUG "%s: buffer (virt): %lx\n", dev->name, (long) ((char *)&tp->scb - (char *)tp) + (long) tp->dmabuffer);
1455 printk(KERN_DEBUG "%s: buffer (DMA) : %lx\n", dev->name, (long) tp->dmabuffer);
1456 printk(KERN_DEBUG "%s: buffer (tp) : %lx\n", dev->name, (long) tp);
1457 }
1458 /* Maximum: three initialization retries */
1459 retry_cnt = INIT_MAX_RETRIES;
1460
1461 do {
1462 retry_cnt--;
1463
1464 /* Transfer initialization block */
1465 SIFWRITEW(0x0001, SIFADX);
1466
1467 /* To address 0001:0A00 of adapter RAM */
1468 SIFWRITEW(0x0A00, SIFADD);
1469
1470 /* Write 11 words to adapter RAM */
1471 for(i = 0; i < 11; i++)
1472 SIFWRITEW(ipb_ptr[i], SIFINC);
1473
1474 /* Execute SCB adapter command */
1475 tms380tr_exec_sifcmd(dev, CMD_EXECUTE);
1476
1477 loop_cnt = INIT_MAX_LOOPCNT; /* Maximum: 11 seconds */
1478
1479 /* While remaining retries, no error and not completed */
1480 do {
1481 Status = 0;
1482 loop_cnt--;
1483 tms380tr_wait(HALF_SECOND);
1484
1485 /* Mask interesting status bits */
1486 Status = SIFREADW(SIFSTS);
1487 Status &= STS_MASK;
1488 } while(((Status &(STS_INITIALIZE | STS_ERROR | STS_TEST)) != 0)
1489 && ((Status & STS_ERROR) == 0) && (loop_cnt != 0));
1490
1491 if((Status & (STS_INITIALIZE | STS_ERROR | STS_TEST)) == 0)
1492 {
1493 /* Initialization completed without error */
1494 i = 0;
1495 do { /* Test if contents of SCB is valid */
1496 if(SCB_Test[i] != *(cb_ptr + i))
1497 {
1498 printk(KERN_INFO "%s: DMA failed\n", dev->name);
1499 /* DMA data error: wrong data in SCB */
1500 return (-1);
1501 }
1502 i++;
1503 } while(i < 6);
1504
1505 i = 0;
1506 do { /* Test if contents of SSB is valid */
1507 if(SSB_Test[i] != *(sb_ptr + i))
1508 /* DMA data error: wrong data in SSB */
1509 return (-1);
1510 i++;
1511 } while (i < 8);
1512
1513 return (1); /* Adapter successfully initialized */
1514 }
1515 else
1516 {
1517 if((Status & STS_ERROR) != 0)
1518 {
1519 /* Initialization error occurred */
1520 Status = SIFREADW(SIFSTS);
1521 Status &= STS_ERROR_MASK;
1522 /* ShowInitialisationErrorCode(Status); */
1523 printk(KERN_INFO "%s: Status error: %d\n", dev->name, Status);
1524 return (-1); /* Unrecoverable error */
1525 }
1526 else
1527 {
1528 if(retry_cnt > 0)
1529 {
1530 /* Reset adapter and try init again */
1531 tms380tr_exec_sifcmd(dev, EXEC_SOFT_RESET);
1532 tms380tr_wait(HALF_SECOND);
1533 }
1534 }
1535 }
1536 } while(retry_cnt > 0);
1537
1538 printk(KERN_INFO "%s: Retry exceeded\n", dev->name);
1539 return (-1);
1540}
1541
1542/*
1543 * Check for outstanding commands in command queue and tries to execute
1544 * command immediately. Corresponding command flag in command queue is cleared.
1545 */
1546static void tms380tr_chk_outstanding_cmds(struct net_device *dev)
1547{
1548 struct net_local *tp = netdev_priv(dev);
1549 unsigned long Addr = 0;
1550
1551 if(tp->CMDqueue == 0)
1552 return; /* No command execution */
1553
1554 /* If SCB in use: no command */
1555 if(tp->ScbInUse == 1)
1556 return;
1557
1558 /* Check if adapter is opened, avoiding COMMAND_REJECT
1559 * interrupt by the adapter!
1560 */
1561 if(tp->AdapterOpenFlag == 0)
1562 {
1563 if(tp->CMDqueue & OC_OPEN)
1564 {
1565 /* Execute OPEN command */
1566 tp->CMDqueue ^= OC_OPEN;
1567
1568 Addr = htonl(((char *)&tp->ocpl - (char *)tp) + tp->dmabuffer);
1569 tp->scb.Parm[0] = LOWORD(Addr);
1570 tp->scb.Parm[1] = HIWORD(Addr);
1571 tp->scb.CMD = OPEN;
1572 }
1573 else
1574 /* No OPEN command queued, but adapter closed. Note:
1575 * We'll try to re-open the adapter in DriverPoll()
1576 */
1577 return; /* No adapter command issued */
1578 }
1579 else
1580 {
1581 /* Adapter is open; evaluate command queue: try to execute
1582 * outstanding commands (depending on priority!) CLOSE
1583 * command queued
1584 */
1585 if(tp->CMDqueue & OC_CLOSE)
1586 {
1587 tp->CMDqueue ^= OC_CLOSE;
1588 tp->AdapterOpenFlag = 0;
1589 tp->scb.Parm[0] = 0; /* Parm[0], Parm[1] are ignored */
1590 tp->scb.Parm[1] = 0; /* but should be set to zero! */
1591 tp->scb.CMD = CLOSE;
1592 if(!tp->HaltInProgress)
1593 tp->CMDqueue |= OC_OPEN; /* re-open adapter */
1594 else
1595 tp->CMDqueue = 0; /* no more commands */
1596 }
1597 else
1598 {
1599 if(tp->CMDqueue & OC_RECEIVE)
1600 {
1601 tp->CMDqueue ^= OC_RECEIVE;
1602 Addr = htonl(((char *)tp->RplHead - (char *)tp) + tp->dmabuffer);
1603 tp->scb.Parm[0] = LOWORD(Addr);
1604 tp->scb.Parm[1] = HIWORD(Addr);
1605 tp->scb.CMD = RECEIVE;
1606 }
1607 else
1608 {
1609 if(tp->CMDqueue & OC_TRANSMIT_HALT)
1610 {
1611 /* NOTE: TRANSMIT.HALT must be checked
1612 * before TRANSMIT.
1613 */
1614 tp->CMDqueue ^= OC_TRANSMIT_HALT;
1615 tp->scb.CMD = TRANSMIT_HALT;
1616
1617 /* Parm[0] and Parm[1] are ignored
1618 * but should be set to zero!
1619 */
1620 tp->scb.Parm[0] = 0;
1621 tp->scb.Parm[1] = 0;
1622 }
1623 else
1624 {
1625 if(tp->CMDqueue & OC_TRANSMIT)
1626 {
1627 /* NOTE: TRANSMIT must be
1628 * checked after TRANSMIT.HALT
1629 */
1630 if(tp->TransmitCommandActive)
1631 {
1632 if(!tp->TransmitHaltScheduled)
1633 {
1634 tp->TransmitHaltScheduled = 1;
1635 tms380tr_exec_cmd(dev, OC_TRANSMIT_HALT) ;
1636 }
1637 tp->TransmitCommandActive = 0;
1638 return;
1639 }
1640
1641 tp->CMDqueue ^= OC_TRANSMIT;
1642 tms380tr_cancel_tx_queue(tp);
1643 Addr = htonl(((char *)tp->TplBusy - (char *)tp) + tp->dmabuffer);
1644 tp->scb.Parm[0] = LOWORD(Addr);
1645 tp->scb.Parm[1] = HIWORD(Addr);
1646 tp->scb.CMD = TRANSMIT;
1647 tp->TransmitCommandActive = 1;
1648 }
1649 else
1650 {
1651 if(tp->CMDqueue & OC_MODIFY_OPEN_PARMS)
1652 {
1653 tp->CMDqueue ^= OC_MODIFY_OPEN_PARMS;
1654 tp->scb.Parm[0] = tp->ocpl.OPENOptions; /* new OPEN options*/
1655 tp->scb.Parm[0] |= ENABLE_FULL_DUPLEX_SELECTION;
1656 tp->scb.Parm[1] = 0; /* is ignored but should be zero */
1657 tp->scb.CMD = MODIFY_OPEN_PARMS;
1658 }
1659 else
1660 {
1661 if(tp->CMDqueue & OC_SET_FUNCT_ADDR)
1662 {
1663 tp->CMDqueue ^= OC_SET_FUNCT_ADDR;
1664 tp->scb.Parm[0] = LOWORD(tp->ocpl.FunctAddr);
1665 tp->scb.Parm[1] = HIWORD(tp->ocpl.FunctAddr);
1666 tp->scb.CMD = SET_FUNCT_ADDR;
1667 }
1668 else
1669 {
1670 if(tp->CMDqueue & OC_SET_GROUP_ADDR)
1671 {
1672 tp->CMDqueue ^= OC_SET_GROUP_ADDR;
1673 tp->scb.Parm[0] = LOWORD(tp->ocpl.GroupAddr);
1674 tp->scb.Parm[1] = HIWORD(tp->ocpl.GroupAddr);
1675 tp->scb.CMD = SET_GROUP_ADDR;
1676 }
1677 else
1678 {
1679 if(tp->CMDqueue & OC_READ_ERROR_LOG)
1680 {
1681 tp->CMDqueue ^= OC_READ_ERROR_LOG;
1682 Addr = htonl(((char *)&tp->errorlogtable - (char *)tp) + tp->dmabuffer);
1683 tp->scb.Parm[0] = LOWORD(Addr);
1684 tp->scb.Parm[1] = HIWORD(Addr);
1685 tp->scb.CMD = READ_ERROR_LOG;
1686 }
1687 else
1688 {
1689 printk(KERN_WARNING "CheckForOutstandingCommand: unknown Command\n");
1690 tp->CMDqueue = 0;
1691 return;
1692 }
1693 }
1694 }
1695 }
1696 }
1697 }
1698 }
1699 }
1700 }
1701
1702 tp->ScbInUse = 1; /* Set semaphore: SCB in use. */
1703
1704 /* Execute SCB and generate IRQ when done. */
1705 tms380tr_exec_sifcmd(dev, CMD_EXECUTE | CMD_SCB_REQUEST);
1706
1707 return;
1708}
1709
1710/*
1711 * IRQ conditions: signal loss on the ring, transmit or receive of beacon
1712 * frames (disabled if bit 1 of OPEN option is set); report error MAC
1713 * frame transmit (disabled if bit 2 of OPEN option is set); open or short
1714 * circuit fault on the lobe is detected; remove MAC frame received;
1715 * error counter overflow (255); opened adapter is the only station in ring.
1716 * After some of the IRQs the adapter is closed!
1717 */
1718static void tms380tr_ring_status_irq(struct net_device *dev)
1719{
1720 struct net_local *tp = netdev_priv(dev);
1721
1722 tp->CurrentRingStatus = be16_to_cpu((unsigned short)tp->ssb.Parm[0]);
1723
1724 /* First: fill up statistics */
1725 if(tp->ssb.Parm[0] & SIGNAL_LOSS)
1726 {
1727 printk(KERN_INFO "%s: Signal Loss\n", dev->name);
1728 tp->MacStat.line_errors++;
1729 }
1730
1731 /* Adapter is closed, but initialized */
1732 if(tp->ssb.Parm[0] & LOBE_WIRE_FAULT)
1733 {
1734 printk(KERN_INFO "%s: Lobe Wire Fault, Reopen Adapter\n",
1735 dev->name);
1736 tp->MacStat.line_errors++;
1737 }
1738
1739 if(tp->ssb.Parm[0] & RING_RECOVERY)
1740 printk(KERN_INFO "%s: Ring Recovery\n", dev->name);
1741
1742 /* Counter overflow: read error log */
1743 if(tp->ssb.Parm[0] & COUNTER_OVERFLOW)
1744 {
1745 printk(KERN_INFO "%s: Counter Overflow\n", dev->name);
1746 tms380tr_exec_cmd(dev, OC_READ_ERROR_LOG);
1747 }
1748
1749 /* Adapter is closed, but initialized */
1750 if(tp->ssb.Parm[0] & REMOVE_RECEIVED)
1751 printk(KERN_INFO "%s: Remove Received, Reopen Adapter\n",
1752 dev->name);
1753
1754 /* Adapter is closed, but initialized */
1755 if(tp->ssb.Parm[0] & AUTO_REMOVAL_ERROR)
1756 printk(KERN_INFO "%s: Auto Removal Error, Reopen Adapter\n",
1757 dev->name);
1758
1759 if(tp->ssb.Parm[0] & HARD_ERROR)
1760 printk(KERN_INFO "%s: Hard Error\n", dev->name);
1761
1762 if(tp->ssb.Parm[0] & SOFT_ERROR)
1763 printk(KERN_INFO "%s: Soft Error\n", dev->name);
1764
1765 if(tp->ssb.Parm[0] & TRANSMIT_BEACON)
1766 printk(KERN_INFO "%s: Transmit Beacon\n", dev->name);
1767
1768 if(tp->ssb.Parm[0] & SINGLE_STATION)
1769 printk(KERN_INFO "%s: Single Station\n", dev->name);
1770
1771 /* Check if adapter has been closed */
1772 if(tp->ssb.Parm[0] & ADAPTER_CLOSED)
1773 {
1774 printk(KERN_INFO "%s: Adapter closed (Reopening),"
1775 "CurrentRingStat %x\n",
1776 dev->name, tp->CurrentRingStatus);
1777 tp->AdapterOpenFlag = 0;
1778 tms380tr_open_adapter(dev);
1779 }
1780
1781 return;
1782}
1783
1784/*
1785 * Issued if adapter has encountered an unrecoverable hardware
1786 * or software error.
1787 */
1788static void tms380tr_chk_irq(struct net_device *dev)
1789{
1790 int i;
1791 unsigned short AdapterCheckBlock[4];
1792 struct net_local *tp = netdev_priv(dev);
1793
1794 tp->AdapterOpenFlag = 0; /* Adapter closed now */
1795
1796 /* Page number of adapter memory */
1797 SIFWRITEW(0x0001, SIFADX);
1798 /* Address offset */
1799 SIFWRITEW(CHECKADDR, SIFADR);
1800
1801 /* Reading 8 byte adapter check block. */
1802 for(i = 0; i < 4; i++)
1803 AdapterCheckBlock[i] = SIFREADW(SIFINC);
1804
1805 if(tms380tr_debug > 3)
1806 {
1807 printk(KERN_DEBUG "%s: AdapterCheckBlock: ", dev->name);
1808 for (i = 0; i < 4; i++)
1809 printk("%04X", AdapterCheckBlock[i]);
1810 printk("\n");
1811 }
1812
1813 switch(AdapterCheckBlock[0])
1814 {
1815 case DIO_PARITY:
1816 printk(KERN_INFO "%s: DIO parity error\n", dev->name);
1817 break;
1818
1819 case DMA_READ_ABORT:
1820 printk(KERN_INFO "%s DMA read operation aborted:\n",
1821 dev->name);
1822 switch (AdapterCheckBlock[1])
1823 {
1824 case 0:
1825 printk(KERN_INFO "Timeout\n");
1826 printk(KERN_INFO "Address: %04X %04X\n",
1827 AdapterCheckBlock[2],
1828 AdapterCheckBlock[3]);
1829 break;
1830
1831 case 1:
1832 printk(KERN_INFO "Parity error\n");
1833 printk(KERN_INFO "Address: %04X %04X\n",
1834 AdapterCheckBlock[2],
1835 AdapterCheckBlock[3]);
1836 break;
1837
1838 case 2:
1839 printk(KERN_INFO "Bus error\n");
1840 printk(KERN_INFO "Address: %04X %04X\n",
1841 AdapterCheckBlock[2],
1842 AdapterCheckBlock[3]);
1843 break;
1844
1845 default:
1846 printk(KERN_INFO "Unknown error.\n");
1847 break;
1848 }
1849 break;
1850
1851 case DMA_WRITE_ABORT:
1852 printk(KERN_INFO "%s: DMA write operation aborted: \n",
1853 dev->name);
1854 switch (AdapterCheckBlock[1])
1855 {
1856 case 0:
1857 printk(KERN_INFO "Timeout\n");
1858 printk(KERN_INFO "Address: %04X %04X\n",
1859 AdapterCheckBlock[2],
1860 AdapterCheckBlock[3]);
1861 break;
1862
1863 case 1:
1864 printk(KERN_INFO "Parity error\n");
1865 printk(KERN_INFO "Address: %04X %04X\n",
1866 AdapterCheckBlock[2],
1867 AdapterCheckBlock[3]);
1868 break;
1869
1870 case 2:
1871 printk(KERN_INFO "Bus error\n");
1872 printk(KERN_INFO "Address: %04X %04X\n",
1873 AdapterCheckBlock[2],
1874 AdapterCheckBlock[3]);
1875 break;
1876
1877 default:
1878 printk(KERN_INFO "Unknown error.\n");
1879 break;
1880 }
1881 break;
1882
1883 case ILLEGAL_OP_CODE:
1884 printk(KERN_INFO "%s: Illegal operation code in firmware\n",
1885 dev->name);
1886 /* Parm[0-3]: adapter internal register R13-R15 */
1887 break;
1888
1889 case PARITY_ERRORS:
1890 printk(KERN_INFO "%s: Adapter internal bus parity error\n",
1891 dev->name);
1892 /* Parm[0-3]: adapter internal register R13-R15 */
1893 break;
1894
1895 case RAM_DATA_ERROR:
1896 printk(KERN_INFO "%s: RAM data error\n", dev->name);
1897 /* Parm[0-1]: MSW/LSW address of RAM location. */
1898 break;
1899
1900 case RAM_PARITY_ERROR:
1901 printk(KERN_INFO "%s: RAM parity error\n", dev->name);
1902 /* Parm[0-1]: MSW/LSW address of RAM location. */
1903 break;
1904
1905 case RING_UNDERRUN:
1906 printk(KERN_INFO "%s: Internal DMA underrun detected\n",
1907 dev->name);
1908 break;
1909
1910 case INVALID_IRQ:
1911 printk(KERN_INFO "%s: Unrecognized interrupt detected\n",
1912 dev->name);
1913 /* Parm[0-3]: adapter internal register R13-R15 */
1914 break;
1915
1916 case INVALID_ERROR_IRQ:
1917 printk(KERN_INFO "%s: Unrecognized error interrupt detected\n",
1918 dev->name);
1919 /* Parm[0-3]: adapter internal register R13-R15 */
1920 break;
1921
1922 case INVALID_XOP:
1923 printk(KERN_INFO "%s: Unrecognized XOP request detected\n",
1924 dev->name);
1925 /* Parm[0-3]: adapter internal register R13-R15 */
1926 break;
1927
1928 default:
1929 printk(KERN_INFO "%s: Unknown status", dev->name);
1930 break;
1931 }
1932
1933 if(tms380tr_chipset_init(dev) == 1)
1934 {
1935 /* Restart of firmware successful */
1936 tp->AdapterOpenFlag = 1;
1937 }
1938
1939 return;
1940}
1941
1942/*
1943 * Internal adapter pointer to RAM data are copied from adapter into
1944 * host system.
1945 */
1946static int tms380tr_read_ptr(struct net_device *dev)
1947{
1948 struct net_local *tp = netdev_priv(dev);
1949 unsigned short adapterram;
1950
1951 tms380tr_read_ram(dev, (unsigned char *)&tp->intptrs.BurnedInAddrPtr,
1952 ADAPTER_INT_PTRS, 16);
1953 tms380tr_read_ram(dev, (unsigned char *)&adapterram,
1954 cpu_to_be16((unsigned short)tp->intptrs.AdapterRAMPtr), 2);
1955 return be16_to_cpu(adapterram);
1956}
1957
1958/*
1959 * Reads a number of bytes from adapter to system memory.
1960 */
1961static void tms380tr_read_ram(struct net_device *dev, unsigned char *Data,
1962 unsigned short Address, int Length)
1963{
1964 int i;
1965 unsigned short old_sifadx, old_sifadr, InWord;
1966
1967 /* Save the current values */
1968 old_sifadx = SIFREADW(SIFADX);
1969 old_sifadr = SIFREADW(SIFADR);
1970
1971 /* Page number of adapter memory */
1972 SIFWRITEW(0x0001, SIFADX);
1973 /* Address offset in adapter RAM */
1974 SIFWRITEW(Address, SIFADR);
1975
1976 /* Copy len byte from adapter memory to system data area. */
1977 i = 0;
1978 for(;;)
1979 {
1980 InWord = SIFREADW(SIFINC);
1981
1982 *(Data + i) = HIBYTE(InWord); /* Write first byte */
1983 if(++i == Length) /* All is done break */
1984 break;
1985
1986 *(Data + i) = LOBYTE(InWord); /* Write second byte */
1987 if (++i == Length) /* All is done break */
1988 break;
1989 }
1990
1991 /* Restore original values */
1992 SIFWRITEW(old_sifadx, SIFADX);
1993 SIFWRITEW(old_sifadr, SIFADR);
1994
1995 return;
1996}
1997
1998/*
1999 * Cancel all queued packets in the transmission queue.
2000 */
2001static void tms380tr_cancel_tx_queue(struct net_local* tp)
2002{
2003 TPL *tpl;
2004
2005 /*
2006 * NOTE: There must not be an active TRANSMIT command pending, when
2007 * this function is called.
2008 */
2009 if(tp->TransmitCommandActive)
2010 return;
2011
2012 for(;;)
2013 {
2014 tpl = tp->TplBusy;
2015 if(!tpl->BusyFlag)
2016 break;
2017 /* "Remove" TPL from busy list. */
2018 tp->TplBusy = tpl->NextTPLPtr;
2019 tms380tr_write_tpl_status(tpl, 0); /* Clear VALID bit */
2020 tpl->BusyFlag = 0; /* "free" TPL */
2021
2022 printk(KERN_INFO "Cancel tx (%08lXh).\n", (unsigned long)tpl);
2023 if (tpl->DMABuff)
2024 pci_unmap_single(tp->pdev, tpl->DMABuff, tpl->Skb->len, PCI_DMA_TODEVICE);
2025 dev_kfree_skb_any(tpl->Skb);
2026 }
2027
2028 return;
2029}
2030
2031/*
2032 * This function is called whenever a transmit interrupt is generated by the
2033 * adapter. For a command complete interrupt, it is checked if we have to
2034 * issue a new transmit command or not.
2035 */
2036static void tms380tr_tx_status_irq(struct net_device *dev)
2037{
2038 struct net_local *tp = netdev_priv(dev);
2039 unsigned char HighByte, HighAc, LowAc;
2040 TPL *tpl;
2041
2042 /* NOTE: At this point the SSB from TRANSMIT STATUS is no longer
2043 * available, because the CLEAR SSB command has already been issued.
2044 *
2045 * Process all complete transmissions.
2046 */
2047
2048 for(;;)
2049 {
2050 tpl = tp->TplBusy;
2051 if(!tpl->BusyFlag || (tpl->Status
2052 & (TX_VALID | TX_FRAME_COMPLETE))
2053 != TX_FRAME_COMPLETE)
2054 {
2055 break;
2056 }
2057
2058 /* "Remove" TPL from busy list. */
2059 tp->TplBusy = tpl->NextTPLPtr ;
2060
2061 /* Check the transmit status field only for directed frames*/
2062 if(DIRECTED_FRAME(tpl) && (tpl->Status & TX_ERROR) == 0)
2063 {
2064 HighByte = GET_TRANSMIT_STATUS_HIGH_BYTE(tpl->Status);
2065 HighAc = GET_FRAME_STATUS_HIGH_AC(HighByte);
2066 LowAc = GET_FRAME_STATUS_LOW_AC(HighByte);
2067
2068 if((HighAc != LowAc) || (HighAc == AC_NOT_RECOGNIZED))
2069 {
2070 printk(KERN_DEBUG "%s: (DA=%08lX not recognized)\n",
2071 dev->name,
2072 *(unsigned long *)&tpl->MData[2+2]);
2073 }
2074 else
2075 {
2076 if(tms380tr_debug > 3)
2077 printk(KERN_DEBUG "%s: Directed frame tx'd\n",
2078 dev->name);
2079 }
2080 }
2081 else
2082 {
2083 if(!DIRECTED_FRAME(tpl))
2084 {
2085 if(tms380tr_debug > 3)
2086 printk(KERN_DEBUG "%s: Broadcast frame tx'd\n",
2087 dev->name);
2088 }
2089 }
2090
2091 tp->MacStat.tx_packets++;
2092 if (tpl->DMABuff)
2093 pci_unmap_single(tp->pdev, tpl->DMABuff, tpl->Skb->len, PCI_DMA_TODEVICE);
2094 dev_kfree_skb_irq(tpl->Skb);
2095 tpl->BusyFlag = 0; /* "free" TPL */
2096 }
2097
2098 if(!tp->TplFree->NextTPLPtr->BusyFlag)
2099 netif_wake_queue(dev);
2100 return;
2101}
2102
2103/*
2104 * Called if a frame receive interrupt is generated by the adapter.
2105 * Check if the frame is valid and indicate it to system.
2106 */
2107static void tms380tr_rcv_status_irq(struct net_device *dev)
2108{
2109 struct net_local *tp = netdev_priv(dev);
2110 unsigned char *ReceiveDataPtr;
2111 struct sk_buff *skb;
2112 unsigned int Length, Length2;
2113 RPL *rpl;
2114 RPL *SaveHead;
2115 dma_addr_t dmabuf;
2116
2117 /* NOTE: At this point the SSB from RECEIVE STATUS is no longer
2118 * available, because the CLEAR SSB command has already been issued.
2119 *
2120 * Process all complete receives.
2121 */
2122
2123 for(;;)
2124 {
2125 rpl = tp->RplHead;
2126 if(rpl->Status & RX_VALID)
2127 break; /* RPL still in use by adapter */
2128
2129 /* Forward RPLHead pointer to next list. */
2130 SaveHead = tp->RplHead;
2131 tp->RplHead = rpl->NextRPLPtr;
2132
2133 /* Get the frame size (Byte swap for Intel).
2134 * Do this early (see workaround comment below)
2135 */
2136 Length = be16_to_cpu((unsigned short)rpl->FrameSize);
2137
2138 /* Check if the Frame_Start, Frame_End and
2139 * Frame_Complete bits are set.
2140 */
2141 if((rpl->Status & VALID_SINGLE_BUFFER_FRAME)
2142 == VALID_SINGLE_BUFFER_FRAME)
2143 {
2144 ReceiveDataPtr = rpl->MData;
2145
2146 /* Workaround for delayed write of FrameSize on ISA
2147 * (FrameSize is false but valid-bit is reset)
2148 * Frame size is set to zero when the RPL is freed.
2149 * Length2 is there because there have also been
2150 * cases where the FrameSize was partially written
2151 */
2152 Length2 = be16_to_cpu((unsigned short)rpl->FrameSize);
2153
2154 if(Length == 0 || Length != Length2)
2155 {
2156 tp->RplHead = SaveHead;
2157 break; /* Return to tms380tr_interrupt */
2158 }
2159 tms380tr_update_rcv_stats(tp,ReceiveDataPtr,Length);
2160
2161 if(tms380tr_debug > 3)
2162 printk(KERN_DEBUG "%s: Packet Length %04X (%d)\n",
2163 dev->name, Length, Length);
2164
2165 /* Indicate the received frame to system the
2166 * adapter does the Source-Routing padding for
2167 * us. See: OpenOptions in tms380tr_init_opb()
2168 */
2169 skb = rpl->Skb;
2170 if(rpl->SkbStat == SKB_UNAVAILABLE)
2171 {
2172 /* Try again to allocate skb */
2173 skb = dev_alloc_skb(tp->MaxPacketSize);
2174 if(skb == NULL)
2175 {
2176 /* Update Stats ?? */
2177 }
2178 else
2179 {
2180 skb->dev = dev;
2181 skb_put(skb, tp->MaxPacketSize);
2182 rpl->SkbStat = SKB_DATA_COPY;
2183 ReceiveDataPtr = rpl->MData;
2184 }
2185 }
2186
2187 if(skb && (rpl->SkbStat == SKB_DATA_COPY
2188 || rpl->SkbStat == SKB_DMA_DIRECT))
2189 {
2190 if(rpl->SkbStat == SKB_DATA_COPY)
2191 memcpy(skb->data, ReceiveDataPtr, Length);
2192
2193 /* Deliver frame to system */
2194 rpl->Skb = NULL;
2195 skb_trim(skb,Length);
2196 skb->protocol = tr_type_trans(skb,dev);
2197 netif_rx(skb);
2198 dev->last_rx = jiffies;
2199 }
2200 }
2201 else /* Invalid frame */
2202 {
2203 if(rpl->Skb != NULL)
2204 dev_kfree_skb_irq(rpl->Skb);
2205
2206 /* Skip list. */
2207 if(rpl->Status & RX_START_FRAME)
2208 /* Frame start bit is set -> overflow. */
2209 tp->MacStat.rx_errors++;
2210 }
2211 if (rpl->DMABuff)
2212 pci_unmap_single(tp->pdev, rpl->DMABuff, tp->MaxPacketSize, PCI_DMA_TODEVICE);
2213 rpl->DMABuff = 0;
2214
2215 /* Allocate new skb for rpl */
2216 rpl->Skb = dev_alloc_skb(tp->MaxPacketSize);
2217 /* skb == NULL ? then use local buffer */
2218 if(rpl->Skb == NULL)
2219 {
2220 rpl->SkbStat = SKB_UNAVAILABLE;
2221 rpl->FragList[0].DataAddr = htonl(((char *)tp->LocalRxBuffers[rpl->RPLIndex] - (char *)tp) + tp->dmabuffer);
2222 rpl->MData = tp->LocalRxBuffers[rpl->RPLIndex];
2223 }
2224 else /* skb != NULL */
2225 {
2226 rpl->Skb->dev = dev;
2227 skb_put(rpl->Skb, tp->MaxPacketSize);
2228
2229 /* Data unreachable for DMA ? then use local buffer */
2230 dmabuf = pci_map_single(tp->pdev, rpl->Skb->data, tp->MaxPacketSize, PCI_DMA_FROMDEVICE);
2231 if(tp->dmalimit && (dmabuf + tp->MaxPacketSize > tp->dmalimit))
2232 {
2233 rpl->SkbStat = SKB_DATA_COPY;
2234 rpl->FragList[0].DataAddr = htonl(((char *)tp->LocalRxBuffers[rpl->RPLIndex] - (char *)tp) + tp->dmabuffer);
2235 rpl->MData = tp->LocalRxBuffers[rpl->RPLIndex];
2236 }
2237 else
2238 {
2239 /* DMA directly in skb->data */
2240 rpl->SkbStat = SKB_DMA_DIRECT;
2241 rpl->FragList[0].DataAddr = htonl(dmabuf);
2242 rpl->MData = rpl->Skb->data;
2243 rpl->DMABuff = dmabuf;
2244 }
2245 }
2246
2247 rpl->FragList[0].DataCount = cpu_to_be16((unsigned short)tp->MaxPacketSize);
2248 rpl->FrameSize = 0;
2249
2250 /* Pass the last RPL back to the adapter */
2251 tp->RplTail->FrameSize = 0;
2252
2253 /* Reset the CSTAT field in the list. */
2254 tms380tr_write_rpl_status(tp->RplTail, RX_VALID | RX_FRAME_IRQ);
2255
2256 /* Current RPL becomes last one in list. */
2257 tp->RplTail = tp->RplTail->NextRPLPtr;
2258
2259 /* Inform adapter about RPL valid. */
2260 tms380tr_exec_sifcmd(dev, CMD_RX_VALID);
2261 }
2262
2263 return;
2264}
2265
2266/*
2267 * This function should be used whenever the status of any RPL must be
2268 * modified by the driver, because the compiler may otherwise change the
2269 * order of instructions such that writing the RPL status may be executed
2270 * at an undesireable time. When this function is used, the status is
2271 * always written when the function is called.
2272 */
2273static void tms380tr_write_rpl_status(RPL *rpl, unsigned int Status)
2274{
2275 rpl->Status = Status;
2276
2277 return;
2278}
2279
2280/*
2281 * The function updates the statistic counters in mac->MacStat.
2282 * It differtiates between directed and broadcast/multicast ( ==functional)
2283 * frames.
2284 */
2285static void tms380tr_update_rcv_stats(struct net_local *tp, unsigned char DataPtr[],
2286 unsigned int Length)
2287{
2288 tp->MacStat.rx_packets++;
2289 tp->MacStat.rx_bytes += Length;
2290
2291 /* Test functional bit */
2292 if(DataPtr[2] & GROUP_BIT)
2293 tp->MacStat.multicast++;
2294
2295 return;
2296}
2297
2298static int tms380tr_set_mac_address(struct net_device *dev, void *addr)
2299{
2300 struct net_local *tp = netdev_priv(dev);
2301 struct sockaddr *saddr = addr;
2302
2303 if (tp->AdapterOpenFlag || tp->AdapterVirtOpenFlag) {
2304 printk(KERN_WARNING "%s: Cannot set MAC/LAA address while card is open\n", dev->name);
2305 return -EIO;
2306 }
2307 memcpy(dev->dev_addr, saddr->sa_data, dev->addr_len);
2308 return 0;
2309}
2310
2311#if TMS380TR_DEBUG > 0
2312/*
2313 * Dump Packet (data)
2314 */
2315static void tms380tr_dump(unsigned char *Data, int length)
2316{
2317 int i, j;
2318
2319 for (i = 0, j = 0; i < length / 8; i++, j += 8)
2320 {
2321 printk(KERN_DEBUG "%02x %02x %02x %02x %02x %02x %02x %02x\n",
2322 Data[j+0],Data[j+1],Data[j+2],Data[j+3],
2323 Data[j+4],Data[j+5],Data[j+6],Data[j+7]);
2324 }
2325
2326 return;
2327}
2328#endif
2329
2330void tmsdev_term(struct net_device *dev)
2331{
2332 struct net_local *tp;
2333
2334 tp = netdev_priv(dev);
2335 pci_unmap_single(tp->pdev, tp->dmabuffer, sizeof(struct net_local),
2336 PCI_DMA_BIDIRECTIONAL);
2337}
2338
2339int tmsdev_init(struct net_device *dev, unsigned long dmalimit,
2340 struct pci_dev *pdev)
2341{
2342 struct net_local *tms_local;
2343
2344 memset(dev->priv, 0, sizeof(struct net_local));
2345 tms_local = netdev_priv(dev);
2346 init_waitqueue_head(&tms_local->wait_for_tok_int);
2347 tms_local->dmalimit = dmalimit;
2348 tms_local->pdev = pdev;
2349 tms_local->dmabuffer = pci_map_single(pdev, (void *)tms_local,
2350 sizeof(struct net_local), PCI_DMA_BIDIRECTIONAL);
2351 if (tms_local->dmabuffer + sizeof(struct net_local) > dmalimit)
2352 {
2353 printk(KERN_INFO "%s: Memory not accessible for DMA\n",
2354 dev->name);
2355 tmsdev_term(dev);
2356 return -ENOMEM;
2357 }
2358
2359 /* These can be overridden by the card driver if needed */
2360 dev->open = tms380tr_open;
2361 dev->stop = tms380tr_close;
2362 dev->do_ioctl = NULL;
2363 dev->hard_start_xmit = tms380tr_send_packet;
2364 dev->tx_timeout = tms380tr_timeout;
2365 dev->watchdog_timeo = HZ;
2366 dev->get_stats = tms380tr_get_stats;
2367 dev->set_multicast_list = &tms380tr_set_multicast_list;
2368 dev->set_mac_address = tms380tr_set_mac_address;
2369
2370 return 0;
2371}
2372
2373#ifdef MODULE
2374
2375EXPORT_SYMBOL(tms380tr_open);
2376EXPORT_SYMBOL(tms380tr_close);
2377EXPORT_SYMBOL(tms380tr_interrupt);
2378EXPORT_SYMBOL(tmsdev_init);
2379EXPORT_SYMBOL(tmsdev_term);
2380EXPORT_SYMBOL(tms380tr_wait);
2381
2382struct module *TMS380_module = NULL;
2383
2384int init_module(void)
2385{
2386 printk(KERN_DEBUG "%s", version);
2387
2388 TMS380_module = &__this_module;
2389 return 0;
2390}
2391
2392void cleanup_module(void)
2393{
2394 TMS380_module = NULL;
2395}
2396#endif
2397
2398MODULE_LICENSE("GPL");
2399
2400
2401/*
2402 * Local variables:
2403 * compile-command: "gcc -DMODVERSIONS -DMODULE -D__KERNEL__ -Wall -Wstrict-prototypes -O6 -fomit-frame-pointer -I/usr/src/linux/drivers/net/tokenring/ -c tms380tr.c"
2404 * alt-compile-command: "gcc -DMODULE -D__KERNEL__ -Wall -Wstrict-prototypes -O6 -fomit-frame-pointer -I/usr/src/linux/drivers/net/tokenring/ -c tms380tr.c"
2405 * c-set-style "K&R"
2406 * c-indent-level: 8
2407 * c-basic-offset: 8
2408 * tab-width: 8
2409 * End:
2410 */
diff --git a/drivers/net/tokenring/tms380tr.h b/drivers/net/tokenring/tms380tr.h
new file mode 100644
index 000000000000..f2c5ba0f37a5
--- /dev/null
+++ b/drivers/net/tokenring/tms380tr.h
@@ -0,0 +1,1141 @@
1/*
2 * tms380tr.h: TI TMS380 Token Ring driver for Linux
3 *
4 * Authors:
5 * - Christoph Goos <cgoos@syskonnect.de>
6 * - Adam Fritzler <mid@auk.cx>
7 */
8
9#ifndef __LINUX_TMS380TR_H
10#define __LINUX_TMS380TR_H
11
12#ifdef __KERNEL__
13
14#include <linux/interrupt.h>
15
16/* module prototypes */
17int tms380tr_open(struct net_device *dev);
18int tms380tr_close(struct net_device *dev);
19irqreturn_t tms380tr_interrupt(int irq, void *dev_id, struct pt_regs *regs);
20int tmsdev_init(struct net_device *dev, unsigned long dmalimit,
21 struct pci_dev *pdev);
22void tmsdev_term(struct net_device *dev);
23void tms380tr_wait(unsigned long time);
24
25#define TMS380TR_MAX_ADAPTERS 7
26
27#define SEND_TIMEOUT 10*HZ
28
29#define TR_RCF_LONGEST_FRAME_MASK 0x0070
30#define TR_RCF_FRAME4K 0x0030
31
32/*------------------------------------------------------------------*/
33/* Bit order for adapter communication with DMA */
34/* -------------------------------------------------------------- */
35/* Bit 8 | 9| 10| 11|| 12| 13| 14| 15|| 0| 1| 2| 3|| 4| 5| 6| 7| */
36/* -------------------------------------------------------------- */
37/* The bytes in a word must be byte swapped. Also, if a double */
38/* word is used for storage, then the words, as well as the bytes, */
39/* must be swapped. */
40/* Bit order for adapter communication with DIO */
41/* -------------------------------------------------------------- */
42/* Bit 0 | 1| 2| 3|| 4| 5| 6| 7|| 8| 9| 10| 11|| 12| 13| 14| 15| */
43/* -------------------------------------------------------------- */
44/*------------------------------------------------------------------*/
45
46/* Swap words of a long. */
47#define SWAPW(x) (((x) << 16) | ((x) >> 16))
48
49/* Get the low byte of a word. */
50#define LOBYTE(w) ((unsigned char)(w))
51
52/* Get the high byte of a word. */
53#define HIBYTE(w) ((unsigned char)((unsigned short)(w) >> 8))
54
55/* Get the low word of a long. */
56#define LOWORD(l) ((unsigned short)(l))
57
58/* Get the high word of a long. */
59#define HIWORD(l) ((unsigned short)((unsigned long)(l) >> 16))
60
61
62
63/* Token ring adapter I/O addresses for normal mode. */
64
65/*
66 * The SIF registers. Common to all adapters.
67 */
68/* Basic SIF (SRSX = 0) */
69#define SIFDAT 0x00 /* SIF/DMA data. */
70#define SIFINC 0x02 /* IO Word data with auto increment. */
71#define SIFINH 0x03 /* IO Byte data with auto increment. */
72#define SIFADR 0x04 /* SIF/DMA Address. */
73#define SIFCMD 0x06 /* SIF Command. */
74#define SIFSTS 0x06 /* SIF Status. */
75
76/* "Extended" SIF (SRSX = 1) */
77#define SIFACL 0x08 /* SIF Adapter Control Register. */
78#define SIFADD 0x0a /* SIF/DMA Address. -- 0x0a */
79#define SIFADX 0x0c /* 0x0c */
80#define DMALEN 0x0e /* SIF DMA length. -- 0x0e */
81
82/*
83 * POS Registers. Only for ISA Adapters.
84 */
85#define POSREG 0x10 /* Adapter Program Option Select (POS)
86 * Register: base IO address + 16 byte.
87 */
88#define POSREG_2 24L /* only for TR4/16+ adapter
89 * base IO address + 24 byte. -- 0x18
90 */
91
92/* SIFCMD command codes (high-low) */
93#define CMD_INTERRUPT_ADAPTER 0x8000 /* Cause internal adapter interrupt */
94#define CMD_ADAPTER_RESET 0x4000 /* Hardware reset of adapter */
95#define CMD_SSB_CLEAR 0x2000 /* Acknowledge to adapter to
96 * system interrupts.
97 */
98#define CMD_EXECUTE 0x1000 /* Execute SCB command */
99#define CMD_SCB_REQUEST 0x0800 /* Request adapter to interrupt
100 * system when SCB is available for
101 * another command.
102 */
103#define CMD_RX_CONTINUE 0x0400 /* Continue receive after odd pointer
104 * stop. (odd pointer receive method)
105 */
106#define CMD_RX_VALID 0x0200 /* Now actual RPL is valid. */
107#define CMD_TX_VALID 0x0100 /* Now actual TPL is valid. (valid
108 * bit receive/transmit method)
109 */
110#define CMD_SYSTEM_IRQ 0x0080 /* Adapter-to-attached-system
111 * interrupt is reset.
112 */
113#define CMD_CLEAR_SYSTEM_IRQ 0x0080 /* Clear SYSTEM_INTERRUPT bit.
114 * (write: 1=ignore, 0=reset)
115 */
116#define EXEC_SOFT_RESET 0xFF00 /* adapter soft reset. (restart
117 * adapter after hardware reset)
118 */
119
120
121/* ACL commands (high-low) */
122#define ACL_SWHLDA 0x0800 /* Software hold acknowledge. */
123#define ACL_SWDDIR 0x0400 /* Data transfer direction. */
124#define ACL_SWHRQ 0x0200 /* Pseudo DMA operation. */
125#define ACL_PSDMAEN 0x0100 /* Enable pseudo system DMA. */
126#define ACL_ARESET 0x0080 /* Adapter hardware reset command.
127 * (held in reset condition as
128 * long as bit is set)
129 */
130#define ACL_CPHALT 0x0040 /* Communication processor halt.
131 * (can only be set while ACL_ARESET
132 * bit is set; prevents adapter
133 * processor from executing code while
134 * downloading firmware)
135 */
136#define ACL_BOOT 0x0020
137#define ACL_SINTEN 0x0008 /* System interrupt enable/disable
138 * (1/0): can be written if ACL_ARESET
139 * is zero.
140 */
141#define ACL_PEN 0x0004
142
143#define ACL_NSELOUT0 0x0002
144#define ACL_NSELOUT1 0x0001 /* NSELOUTx have a card-specific
145 * meaning for setting ring speed.
146 */
147
148#define PS_DMA_MASK (ACL_SWHRQ | ACL_PSDMAEN)
149
150
151/* SIFSTS register return codes (high-low) */
152#define STS_SYSTEM_IRQ 0x0080 /* Adapter-to-attached-system
153 * interrupt is valid.
154 */
155#define STS_INITIALIZE 0x0040 /* INITIALIZE status. (ready to
156 * initialize)
157 */
158#define STS_TEST 0x0020 /* TEST status. (BUD not completed) */
159#define STS_ERROR 0x0010 /* ERROR status. (unrecoverable
160 * HW error occurred)
161 */
162#define STS_MASK 0x00F0 /* Mask interesting status bits. */
163#define STS_ERROR_MASK 0x000F /* Get Error Code by masking the
164 * interrupt code bits.
165 */
166#define ADAPTER_INT_PTRS 0x0A00 /* Address offset of adapter internal
167 * pointers 01:0a00 (high-low) have to
168 * be read after init and before open.
169 */
170
171
172/* Interrupt Codes (only MAC IRQs) */
173#define STS_IRQ_ADAPTER_CHECK 0x0000 /* unrecoverable hardware or
174 * software error.
175 */
176#define STS_IRQ_RING_STATUS 0x0004 /* SSB is updated with ring status. */
177#define STS_IRQ_LLC_STATUS 0x0005 /* Not used in MAC-only microcode */
178#define STS_IRQ_SCB_CLEAR 0x0006 /* SCB clear, following an
179 * SCB_REQUEST IRQ.
180 */
181#define STS_IRQ_TIMER 0x0007 /* Not normally used in MAC ucode */
182#define STS_IRQ_COMMAND_STATUS 0x0008 /* SSB is updated with command
183 * status.
184 */
185#define STS_IRQ_RECEIVE_STATUS 0x000A /* SSB is updated with receive
186 * status.
187 */
188#define STS_IRQ_TRANSMIT_STATUS 0x000C /* SSB is updated with transmit
189 * status
190 */
191#define STS_IRQ_RECEIVE_PENDING 0x000E /* Not used in MAC-only microcode */
192#define STS_IRQ_MASK 0x000F /* = STS_ERROR_MASK. */
193
194
195/* TRANSMIT_STATUS completion code: (SSB.Parm[0]) */
196#define COMMAND_COMPLETE 0x0080 /* TRANSMIT command completed
197 * (avoid this!) issue another transmit
198 * to send additional frames.
199 */
200#define FRAME_COMPLETE 0x0040 /* Frame has been transmitted;
201 * INTERRUPT_FRAME bit was set in the
202 * CSTAT request; indication of possibly
203 * more than one frame transmissions!
204 * SSB.Parm[0-1]: 32 bit pointer to
205 * TPL of last frame.
206 */
207#define LIST_ERROR 0x0020 /* Error in one of the TPLs that
208 * compose the frame; TRANSMIT
209 * terminated; Parm[1-2]: 32bit pointer
210 * to TPL which starts the error
211 * frame; error details in bits 8-13.
212 * (14?)
213 */
214#define FRAME_SIZE_ERROR 0x8000 /* FRAME_SIZE does not equal the sum of
215 * the valid DATA_COUNT fields;
216 * FRAME_SIZE less than header plus
217 * information field. (15 bytes +
218 * routing field) Or if FRAME_SIZE
219 * was specified as zero in one list.
220 */
221#define TX_THRESHOLD 0x4000 /* FRAME_SIZE greater than (BUFFER_SIZE
222 * - 9) * TX_BUF_MAX.
223 */
224#define ODD_ADDRESS 0x2000 /* Odd forward pointer value is
225 * read on a list without END_FRAME
226 * indication.
227 */
228#define FRAME_ERROR 0x1000 /* START_FRAME bit (not) anticipated,
229 * but (not) set.
230 */
231#define ACCESS_PRIORITY_ERROR 0x0800 /* Access priority requested has not
232 * been allowed.
233 */
234#define UNENABLED_MAC_FRAME 0x0400 /* MAC frame has source class of zero
235 * or MAC frame PCF ATTN field is
236 * greater than one.
237 */
238#define ILLEGAL_FRAME_FORMAT 0x0200 /* Bit 0 or FC field was set to one. */
239
240
241/*
242 * Since we need to support some functions even if the adapter is in a
243 * CLOSED state, we have a (pseudo-) command queue which holds commands
244 * that are outstandig to be executed.
245 *
246 * Each time a command completes, an interrupt occurs and the next
247 * command is executed. The command queue is actually a simple word with
248 * a bit for each outstandig command. Therefore the commands will not be
249 * executed in the order they have been queued.
250 *
251 * The following defines the command code bits and the command queue:
252 */
253#define OC_OPEN 0x0001 /* OPEN command */
254#define OC_TRANSMIT 0x0002 /* TRANSMIT command */
255#define OC_TRANSMIT_HALT 0x0004 /* TRANSMIT_HALT command */
256#define OC_RECEIVE 0x0008 /* RECEIVE command */
257#define OC_CLOSE 0x0010 /* CLOSE command */
258#define OC_SET_GROUP_ADDR 0x0020 /* SET_GROUP_ADDR command */
259#define OC_SET_FUNCT_ADDR 0x0040 /* SET_FUNCT_ADDR command */
260#define OC_READ_ERROR_LOG 0x0080 /* READ_ERROR_LOG command */
261#define OC_READ_ADAPTER 0x0100 /* READ_ADAPTER command */
262#define OC_MODIFY_OPEN_PARMS 0x0400 /* MODIFY_OPEN_PARMS command */
263#define OC_RESTORE_OPEN_PARMS 0x0800 /* RESTORE_OPEN_PARMS command */
264#define OC_SET_FIRST_16_GROUP 0x1000 /* SET_FIRST_16_GROUP command */
265#define OC_SET_BRIDGE_PARMS 0x2000 /* SET_BRIDGE_PARMS command */
266#define OC_CONFIG_BRIDGE_PARMS 0x4000 /* CONFIG_BRIDGE_PARMS command */
267
268#define OPEN 0x0300 /* C: open command. S: completion. */
269#define TRANSMIT 0x0400 /* C: transmit command. S: completion
270 * status. (reject: COMMAND_REJECT if
271 * adapter not opened, TRANSMIT already
272 * issued or address passed in the SCB
273 * not word aligned)
274 */
275#define TRANSMIT_HALT 0x0500 /* C: interrupt TX TPL chain; if no
276 * TRANSMIT command issued, the command
277 * is ignored (completion with TRANSMIT
278 * status (0x0400)!)
279 */
280#define RECEIVE 0x0600 /* C: receive command. S: completion
281 * status. (reject: COMMAND_REJECT if
282 * adapter not opened, RECEIVE already
283 * issued or address passed in the SCB
284 * not word aligned)
285 */
286#define CLOSE 0x0700 /* C: close adapter. S: completion.
287 * (COMMAND_REJECT if adapter not open)
288 */
289#define SET_GROUP_ADDR 0x0800 /* C: alter adapter group address after
290 * OPEN. S: completion. (COMMAND_REJECT
291 * if adapter not open)
292 */
293#define SET_FUNCT_ADDR 0x0900 /* C: alter adapter functional address
294 * after OPEN. S: completion.
295 * (COMMAND_REJECT if adapter not open)
296 */
297#define READ_ERROR_LOG 0x0A00 /* C: read adapter error counters.
298 * S: completion. (command ignored
299 * if adapter not open!)
300 */
301#define READ_ADAPTER 0x0B00 /* C: read data from adapter memory.
302 * (important: after init and before
303 * open!) S: completion. (ADAPTER_CHECK
304 * interrupt if undefined storage area
305 * read)
306 */
307#define MODIFY_OPEN_PARMS 0x0D00 /* C: modify some adapter operational
308 * parameters. (bit correspondend to
309 * WRAP_INTERFACE is ignored)
310 * S: completion. (reject:
311 * COMMAND_REJECT)
312 */
313#define RESTORE_OPEN_PARMS 0x0E00 /* C: modify some adapter operational
314 * parameters. (bit correspondend
315 * to WRAP_INTERFACE is ignored)
316 * S: completion. (reject:
317 * COMMAND_REJECT)
318 */
319#define SET_FIRST_16_GROUP 0x0F00 /* C: alter the first two bytes in
320 * adapter group address.
321 * S: completion. (reject:
322 * COMMAND_REJECT)
323 */
324#define SET_BRIDGE_PARMS 0x1000 /* C: values and conditions for the
325 * adapter hardware to use when frames
326 * are copied for forwarding.
327 * S: completion. (reject:
328 * COMMAND_REJECT)
329 */
330#define CONFIG_BRIDGE_PARMS 0x1100 /* C: ..
331 * S: completion. (reject:
332 * COMMAND_REJECT)
333 */
334
335#define SPEED_4 4
336#define SPEED_16 16 /* Default transmission speed */
337
338
339/* Initialization Parameter Block (IPB); word alignment necessary! */
340#define BURST_SIZE 0x0018 /* Default burst size */
341#define BURST_MODE 0x9F00 /* Burst mode enable */
342#define DMA_RETRIES 0x0505 /* Magic DMA retry number... */
343
344#define CYCLE_TIME 3 /* Default AT-bus cycle time: 500 ns
345 * (later adapter version: fix cycle time!)
346 */
347#define LINE_SPEED_BIT 0x80
348
349/* Macro definition for the wait function. */
350#define ONE_SECOND_TICKS 1000000
351#define HALF_SECOND (ONE_SECOND_TICKS / 2)
352#define ONE_SECOND (ONE_SECOND_TICKS)
353#define TWO_SECONDS (ONE_SECOND_TICKS * 2)
354#define THREE_SECONDS (ONE_SECOND_TICKS * 3)
355#define FOUR_SECONDS (ONE_SECOND_TICKS * 4)
356#define FIVE_SECONDS (ONE_SECOND_TICKS * 5)
357
358#define BUFFER_SIZE 2048 /* Buffers on Adapter */
359
360#pragma pack(1)
361typedef struct {
362 unsigned short Init_Options; /* Initialize with burst mode;
363 * LLC disabled. (MAC only)
364 */
365
366 /* Interrupt vectors the adapter places on attached system bus. */
367 u_int8_t CMD_Status_IV; /* Interrupt vector: command status. */
368 u_int8_t TX_IV; /* Interrupt vector: transmit. */
369 u_int8_t RX_IV; /* Interrupt vector: receive. */
370 u_int8_t Ring_Status_IV; /* Interrupt vector: ring status. */
371 u_int8_t SCB_Clear_IV; /* Interrupt vector: SCB clear. */
372 u_int8_t Adapter_CHK_IV; /* Interrupt vector: adapter check. */
373
374 u_int16_t RX_Burst_Size; /* Max. number of transfer cycles. */
375 u_int16_t TX_Burst_Size; /* During DMA burst; even value! */
376 u_int16_t DMA_Abort_Thrhld; /* Number of DMA retries. */
377
378 u_int32_t SCB_Addr; /* SCB address: even, word aligned, high-low */
379 u_int32_t SSB_Addr; /* SSB address: even, word aligned, high-low */
380} IPB, *IPB_Ptr;
381#pragma pack()
382
383/*
384 * OPEN Command Parameter List (OCPL) (can be reused, if the adapter has to
385 * be reopened)
386 */
387#define BUFFER_SIZE 2048 /* Buffers on Adapter. */
388#define TPL_SIZE 8+6*TX_FRAG_NUM /* Depending on fragments per TPL. */
389#define RPL_SIZE 14 /* (with TI firmware v2.26 handling
390 * up to nine fragments possible)
391 */
392#define TX_BUF_MIN 20 /* ??? (Stephan: calculation with */
393#define TX_BUF_MAX 40 /* BUFFER_SIZE and MAX_FRAME_SIZE) ???
394 */
395#define DISABLE_EARLY_TOKEN_RELEASE 0x1000
396
397/* OPEN Options (high-low) */
398#define WRAP_INTERFACE 0x0080 /* Inserting omitted for test
399 * purposes; transmit data appears
400 * as receive data. (useful for
401 * testing; change: CLOSE necessary)
402 */
403#define DISABLE_HARD_ERROR 0x0040 /* On HARD_ERROR & TRANSMIT_BEACON
404 * no RING.STATUS interrupt.
405 */
406#define DISABLE_SOFT_ERROR 0x0020 /* On SOFT_ERROR, no RING.STATUS
407 * interrupt.
408 */
409#define PASS_ADAPTER_MAC_FRAMES 0x0010 /* Passing unsupported MAC frames
410 * to system.
411 */
412#define PASS_ATTENTION_FRAMES 0x0008 /* All changed attention MAC frames are
413 * passed to the system.
414 */
415#define PAD_ROUTING_FIELD 0x0004 /* Routing field is padded to 18
416 * bytes.
417 */
418#define FRAME_HOLD 0x0002 /*Adapter waits for entire frame before
419 * initiating DMA transfer; otherwise:
420 * DMA transfer initiation if internal
421 * buffer filled.
422 */
423#define CONTENDER 0x0001 /* Adapter participates in the monitor
424 * contention process.
425 */
426#define PASS_BEACON_MAC_FRAMES 0x8000 /* Adapter passes beacon MAC frames
427 * to the system.
428 */
429#define EARLY_TOKEN_RELEASE 0x1000 /* Only valid in 16 Mbps operation;
430 * 0 = ETR. (no effect in 4 Mbps
431 * operation)
432 */
433#define COPY_ALL_MAC_FRAMES 0x0400 /* All MAC frames are copied to
434 * the system. (after OPEN: duplicate
435 * address test (DAT) MAC frame is
436 * first received frame copied to the
437 * system)
438 */
439#define COPY_ALL_NON_MAC_FRAMES 0x0200 /* All non MAC frames are copied to
440 * the system.
441 */
442#define PASS_FIRST_BUF_ONLY 0x0100 /* Passes only first internal buffer
443 * of each received frame; FrameSize
444 * of RPLs must contain internal
445 * BUFFER_SIZE bits for promiscous mode.
446 */
447#define ENABLE_FULL_DUPLEX_SELECTION 0x2000
448 /* Enable the use of full-duplex
449 * settings with bits in byte 22 in
450 * ocpl. (new feature in firmware
451 * version 3.09)
452 */
453
454/* Full-duplex settings */
455#define OPEN_FULL_DUPLEX_OFF 0x0000
456#define OPEN_FULL_DUPLEX_ON 0x00c0
457#define OPEN_FULL_DUPLEX_AUTO 0x0080
458
459#define PROD_ID_SIZE 18 /* Length of product ID. */
460
461#define TX_FRAG_NUM 3 /* Number of fragments used in one TPL. */
462#define TX_MORE_FRAGMENTS 0x8000 /* Bit set in DataCount to indicate more
463 * fragments following.
464 */
465
466/* XXX is there some better way to do this? */
467#define ISA_MAX_ADDRESS 0x00ffffff
468#define PCI_MAX_ADDRESS 0xffffffff
469
470#pragma pack(1)
471typedef struct {
472 u_int16_t OPENOptions;
473 u_int8_t NodeAddr[6]; /* Adapter node address; use ROM
474 * address
475 */
476 u_int32_t GroupAddr; /* Multicast: high order
477 * bytes = 0xC000
478 */
479 u_int32_t FunctAddr; /* High order bytes = 0xC000 */
480 u_int16_t RxListSize; /* RPL size: 0 (=26), 14, 20 or
481 * 26 bytes read by the adapter.
482 * (Depending on the number of
483 * fragments/list)
484 */
485 u_int16_t TxListSize; /* TPL size */
486 u_int16_t BufSize; /* Is automatically rounded up to the
487 * nearest nK boundary.
488 */
489 u_int16_t FullDuplex;
490 u_int16_t Reserved;
491 u_int8_t TXBufMin; /* Number of adapter buffers reserved
492 * for transmission a minimum of 2
493 * buffers must be allocated.
494 */
495 u_int8_t TXBufMax; /* Maximum number of adapter buffers
496 * for transmit; a minimum of 2 buffers
497 * must be available for receive.
498 * Default: 6
499 */
500 u_int16_t ProdIDAddr[2];/* Pointer to product ID. */
501} OPB, *OPB_Ptr;
502#pragma pack()
503
504/*
505 * SCB: adapter commands enabled by the host system started by writing
506 * CMD_INTERRUPT_ADAPTER | CMD_EXECUTE (|SCB_REQUEST) to the SIFCMD IO
507 * register. (special case: | CMD_SYSTEM_IRQ for initialization)
508 */
509#pragma pack(1)
510typedef struct {
511 u_int16_t CMD; /* Command code */
512 u_int16_t Parm[2]; /* Pointer to Command Parameter Block */
513} SCB; /* System Command Block (32 bit physical address; big endian)*/
514#pragma pack()
515
516/*
517 * SSB: adapter command return status can be evaluated after COMMAND_STATUS
518 * adapter to system interrupt after reading SSB, the availability of the SSB
519 * has to be told the adapter by writing CMD_INTERRUPT_ADAPTER | CMD_SSB_CLEAR
520 * in the SIFCMD IO register.
521 */
522#pragma pack(1)
523typedef struct {
524 u_int16_t STS; /* Status code */
525 u_int16_t Parm[3]; /* Parameter or pointer to Status Parameter
526 * Block.
527 */
528} SSB; /* System Status Block (big endian - physical address) */
529#pragma pack()
530
531typedef struct {
532 unsigned short BurnedInAddrPtr; /* Pointer to adapter burned in
533 * address. (BIA)
534 */
535 unsigned short SoftwareLevelPtr;/* Pointer to software level data. */
536 unsigned short AdapterAddrPtr; /* Pointer to adapter addresses. */
537 unsigned short AdapterParmsPtr; /* Pointer to adapter parameters. */
538 unsigned short MACBufferPtr; /* Pointer to MAC buffer. (internal) */
539 unsigned short LLCCountersPtr; /* Pointer to LLC counters. */
540 unsigned short SpeedFlagPtr; /* Pointer to data rate flag.
541 * (4/16 Mbps)
542 */
543 unsigned short AdapterRAMPtr; /* Pointer to adapter RAM found. (KB) */
544} INTPTRS; /* Adapter internal pointers */
545
546#pragma pack(1)
547typedef struct {
548 u_int8_t Line_Error; /* Line error: code violation in
549 * frame or in a token, or FCS error.
550 */
551 u_int8_t Internal_Error; /* IBM specific. (Reserved_1) */
552 u_int8_t Burst_Error;
553 u_int8_t ARI_FCI_Error; /* ARI/FCI bit zero in AMP or
554 * SMP MAC frame.
555 */
556 u_int8_t AbortDelimeters; /* IBM specific. (Reserved_2) */
557 u_int8_t Reserved_3;
558 u_int8_t Lost_Frame_Error; /* Receive of end of transmitted
559 * frame failed.
560 */
561 u_int8_t Rx_Congest_Error; /* Adapter in repeat mode has not
562 * enough buffer space to copy incoming
563 * frame.
564 */
565 u_int8_t Frame_Copied_Error; /* ARI bit not zero in frame
566 * addressed to adapter.
567 */
568 u_int8_t Frequency_Error; /* IBM specific. (Reserved_4) */
569 u_int8_t Token_Error; /* (active only in monitor station) */
570 u_int8_t Reserved_5;
571 u_int8_t DMA_Bus_Error; /* DMA bus errors not exceeding the
572 * abort thresholds.
573 */
574 u_int8_t DMA_Parity_Error; /* DMA parity errors not exceeding
575 * the abort thresholds.
576 */
577} ERRORTAB; /* Adapter error counters */
578#pragma pack()
579
580
581/*--------------------- Send and Receive definitions -------------------*/
582#pragma pack(1)
583typedef struct {
584 u_int16_t DataCount; /* Value 0, even and odd values are
585 * permitted; value is unaltered most
586 * significant bit set: following
587 * fragments last fragment: most
588 * significant bit is not evaluated.
589 * (???)
590 */
591 u_int32_t DataAddr; /* Pointer to frame data fragment;
592 * even or odd.
593 */
594} Fragment;
595#pragma pack()
596
597#define MAX_FRAG_NUMBERS 9 /* Maximal number of fragments possible to use
598 * in one RPL/TPL. (depending on TI firmware
599 * version)
600 */
601
602/*
603 * AC (1), FC (1), Dst (6), Src (6), RIF (18), Data (4472) = 4504
604 * The packet size can be one of the follows: 548, 1502, 2084, 4504, 8176,
605 * 11439, 17832. Refer to TMS380 Second Generation Token Ring User's Guide
606 * Page 2-27.
607 */
608#define HEADER_SIZE (1 + 1 + 6 + 6)
609#define SRC_SIZE 18
610#define MIN_DATA_SIZE 516
611#define DEFAULT_DATA_SIZE 4472
612#define MAX_DATA_SIZE 17800
613
614#define DEFAULT_PACKET_SIZE (HEADER_SIZE + SRC_SIZE + DEFAULT_DATA_SIZE)
615#define MIN_PACKET_SIZE (HEADER_SIZE + SRC_SIZE + MIN_DATA_SIZE)
616#define MAX_PACKET_SIZE (HEADER_SIZE + SRC_SIZE + MAX_DATA_SIZE)
617
618/*
619 * Macros to deal with the frame status field.
620 */
621#define AC_NOT_RECOGNIZED 0x00
622#define GROUP_BIT 0x80
623#define GET_TRANSMIT_STATUS_HIGH_BYTE(Ts) ((unsigned char)((Ts) >> 8))
624#define GET_FRAME_STATUS_HIGH_AC(Fs) ((unsigned char)(((Fs) & 0xC0) >> 6))
625#define GET_FRAME_STATUS_LOW_AC(Fs) ((unsigned char)(((Fs) & 0x0C) >> 2))
626#define DIRECTED_FRAME(Context) (!((Context)->MData[2] & GROUP_BIT))
627
628
629/*--------------------- Send Functions ---------------------------------*/
630/* define TX_CSTAT _REQUEST (R) and _COMPLETE (C) values (high-low) */
631
632#define TX_VALID 0x0080 /* R: set via TRANSMIT.VALID interrupt.
633 * C: always reset to zero!
634 */
635#define TX_FRAME_COMPLETE 0x0040 /* R: must be reset to zero.
636 * C: set to one.
637 */
638#define TX_START_FRAME 0x0020 /* R: start of a frame: 1
639 * C: unchanged.
640 */
641#define TX_END_FRAME 0x0010 /* R: end of a frame: 1
642 * C: unchanged.
643 */
644#define TX_FRAME_IRQ 0x0008 /* R: request interrupt generation
645 * after transmission.
646 * C: unchanged.
647 */
648#define TX_ERROR 0x0004 /* R: reserved.
649 * C: set to one if Error occurred.
650 */
651#define TX_INTERFRAME_WAIT 0x0004
652#define TX_PASS_CRC 0x0002 /* R: set if CRC value is already
653 * calculated. (valid only in
654 * FRAME_START TPL)
655 * C: unchanged.
656 */
657#define TX_PASS_SRC_ADDR 0x0001 /* R: adapter uses explicit frame
658 * source address and does not overwrite
659 * with the adapter node address.
660 * (valid only in FRAME_START TPL)
661 *
662 * C: unchanged.
663 */
664#define TX_STRIP_FS 0xFF00 /* R: reserved.
665 * C: if no Transmission Error,
666 * field contains copy of FS byte after
667 * stripping of frame.
668 */
669
670/*
671 * Structure of Transmit Parameter Lists (TPLs) (only one frame every TPL,
672 * but possibly multiple TPLs for one frame) the length of the TPLs has to be
673 * initialized in the OPL. (OPEN parameter list)
674 */
675#define TPL_NUM 3 /* Number of Transmit Parameter Lists.
676 * !! MUST BE >= 3 !!
677 */
678
679#pragma pack(1)
680typedef struct s_TPL TPL;
681
682struct s_TPL { /* Transmit Parameter List (align on even word boundaries) */
683 u_int32_t NextTPLAddr; /* Pointer to next TPL in chain; if
684 * pointer is odd: this is the last
685 * TPL. Pointing to itself can cause
686 * problems!
687 */
688 volatile u_int16_t Status; /* Initialized by the adapter:
689 * CSTAT_REQUEST important: update least
690 * significant bit first! Set by the
691 * adapter: CSTAT_COMPLETE status.
692 */
693 u_int16_t FrameSize; /* Number of bytes to be transmitted
694 * as a frame including AC/FC,
695 * Destination, Source, Routing field
696 * not including CRC, FS, End Delimiter
697 * (valid only if START_FRAME bit in
698 * CSTAT nonzero) must not be zero in
699 * any list; maximum value: (BUFFER_SIZE
700 * - 8) * TX_BUF_MAX sum of DataCount
701 * values in FragmentList must equal
702 * Frame_Size value in START_FRAME TPL!
703 * frame data fragment list.
704 */
705
706 /* TPL/RPL size in OPEN parameter list depending on maximal
707 * numbers of fragments used in one parameter list.
708 */
709 Fragment FragList[TX_FRAG_NUM]; /* Maximum: nine frame fragments in one
710 * TPL actual version of firmware: 9
711 * fragments possible.
712 */
713#pragma pack()
714
715 /* Special proprietary data and precalculations */
716
717 TPL *NextTPLPtr; /* Pointer to next TPL in chain. */
718 unsigned char *MData;
719 struct sk_buff *Skb;
720 unsigned char TPLIndex;
721 volatile unsigned char BusyFlag;/* Flag: TPL busy? */
722 dma_addr_t DMABuff; /* DMA IO bus address from pci_map */
723};
724
725/* ---------------------Receive Functions-------------------------------*
726 * define RECEIVE_CSTAT_REQUEST (R) and RECEIVE_CSTAT_COMPLETE (C) values.
727 * (high-low)
728 */
729#define RX_VALID 0x0080 /* R: set; tell adapter with
730 * RECEIVE.VALID interrupt.
731 * C: reset to zero.
732 */
733#define RX_FRAME_COMPLETE 0x0040 /* R: must be reset to zero,
734 * C: set to one.
735 */
736#define RX_START_FRAME 0x0020 /* R: must be reset to zero.
737 * C: set to one on the list.
738 */
739#define RX_END_FRAME 0x0010 /* R: must be reset to zero.
740 * C: set to one on the list
741 * that ends the frame.
742 */
743#define RX_FRAME_IRQ 0x0008 /* R: request interrupt generation
744 * after receive.
745 * C: unchanged.
746 */
747#define RX_INTERFRAME_WAIT 0x0004 /* R: after receiving a frame:
748 * interrupt and wait for a
749 * RECEIVE.CONTINUE.
750 * C: unchanged.
751 */
752#define RX_PASS_CRC 0x0002 /* R: if set, the adapter includes
753 * the CRC in data passed. (last four
754 * bytes; valid only if FRAME_START is
755 * set)
756 * C: set, if CRC is included in
757 * received data.
758 */
759#define RX_PASS_SRC_ADDR 0x0001 /* R: adapter uses explicit frame
760 * source address and does not
761 * overwrite with the adapter node
762 * address. (valid only if FRAME_START
763 * is set)
764 * C: unchanged.
765 */
766#define RX_RECEIVE_FS 0xFC00 /* R: reserved; must be reset to zero.
767 * C: on lists with START_FRAME, field
768 * contains frame status field from
769 * received frame; otherwise cleared.
770 */
771#define RX_ADDR_MATCH 0x0300 /* R: reserved; must be reset to zero.
772 * C: address match code mask.
773 */
774#define RX_STATUS_MASK 0x00FF /* Mask for receive status bits. */
775
776#define RX_INTERN_ADDR_MATCH 0x0100 /* C: internally address match. */
777#define RX_EXTERN_ADDR_MATCH 0x0200 /* C: externally matched via
778 * XMATCH/XFAIL interface.
779 */
780#define RX_INTEXT_ADDR_MATCH 0x0300 /* C: internally and externally
781 * matched.
782 */
783#define RX_READY (RX_VALID | RX_FRAME_IRQ) /* Ready for receive. */
784
785/* Constants for Command Status Interrupt.
786 * COMMAND_REJECT status field bit functions (SSB.Parm[0])
787 */
788#define ILLEGAL_COMMAND 0x0080 /* Set if an unknown command
789 * is issued to the adapter
790 */
791#define ADDRESS_ERROR 0x0040 /* Set if any address field in
792 * the SCB is odd. (not word aligned)
793 */
794#define ADAPTER_OPEN 0x0020 /* Command issued illegal with
795 * open adapter.
796 */
797#define ADAPTER_CLOSE 0x0010 /* Command issued illegal with
798 * closed adapter.
799 */
800#define SAME_COMMAND 0x0008 /* Command issued with same command
801 * already executing.
802 */
803
804/* OPEN_COMPLETION values (SSB.Parm[0], MSB) */
805#define NODE_ADDR_ERROR 0x0040 /* Wrong address or BIA read
806 * zero address.
807 */
808#define LIST_SIZE_ERROR 0x0020 /* If List_Size value not in 0,
809 * 14, 20, 26.
810 */
811#define BUF_SIZE_ERROR 0x0010 /* Not enough available memory for
812 * two buffers.
813 */
814#define TX_BUF_COUNT_ERROR 0x0004 /* Remaining receive buffers less than
815 * two.
816 */
817#define OPEN_ERROR 0x0002 /* Error during ring insertion; more
818 * information in bits 8-15.
819 */
820
821/* Standard return codes */
822#define GOOD_COMPLETION 0x0080 /* =OPEN_SUCCESSFULL */
823#define INVALID_OPEN_OPTION 0x0001 /* OPEN options are not supported by
824 * the adapter.
825 */
826
827/* OPEN phases; details of OPEN_ERROR (SSB.Parm[0], LSB) */
828#define OPEN_PHASES_MASK 0xF000 /* Check only the bits 8-11. */
829#define LOBE_MEDIA_TEST 0x1000
830#define PHYSICAL_INSERTION 0x2000
831#define ADDRESS_VERIFICATION 0x3000
832#define PARTICIPATION_IN_RING_POLL 0x4000
833#define REQUEST_INITIALISATION 0x5000
834#define FULLDUPLEX_CHECK 0x6000
835
836/* OPEN error codes; details of OPEN_ERROR (SSB.Parm[0], LSB) */
837#define OPEN_ERROR_CODES_MASK 0x0F00 /* Check only the bits 12-15. */
838#define OPEN_FUNCTION_FAILURE 0x0100 /* Unable to transmit to itself or
839 * frames received before insertion.
840 */
841#define OPEN_SIGNAL_LOSS 0x0200 /* Signal loss condition detected at
842 * receiver.
843 */
844#define OPEN_TIMEOUT 0x0500 /* Insertion timer expired before
845 * logical insertion.
846 */
847#define OPEN_RING_FAILURE 0x0600 /* Unable to receive own ring purge
848 * MAC frames.
849 */
850#define OPEN_RING_BEACONING 0x0700 /* Beacon MAC frame received after
851 * ring insertion.
852 */
853#define OPEN_DUPLICATE_NODEADDR 0x0800 /* Other station in ring found
854 * with the same address.
855 */
856#define OPEN_REQUEST_INIT 0x0900 /* RPS present but does not respond. */
857#define OPEN_REMOVE_RECEIVED 0x0A00 /* Adapter received a remove adapter
858 * MAC frame.
859 */
860#define OPEN_FULLDUPLEX_SET 0x0D00 /* Got this with full duplex on when
861 * trying to connect to a normal ring.
862 */
863
864/* SET_BRIDGE_PARMS return codes: */
865#define BRIDGE_INVALID_MAX_LEN 0x4000 /* MAX_ROUTING_FIELD_LENGTH odd,
866 * less than 6 or > 30.
867 */
868#define BRIDGE_INVALID_SRC_RING 0x2000 /* SOURCE_RING number zero, too large
869 * or = TARGET_RING.
870 */
871#define BRIDGE_INVALID_TRG_RING 0x1000 /* TARGET_RING number zero, too large
872 * or = SOURCE_RING.
873 */
874#define BRIDGE_INVALID_BRDGE_NO 0x0800 /* BRIDGE_NUMBER too large. */
875#define BRIDGE_INVALID_OPTIONS 0x0400 /* Invalid bridge options. */
876#define BRIDGE_DIAGS_FAILED 0x0200 /* Diagnostics of TMS380SRA failed. */
877#define BRIDGE_NO_SRA 0x0100 /* The TMS380SRA does not exist in HW
878 * configuration.
879 */
880
881/*
882 * Bring Up Diagnostics error codes.
883 */
884#define BUD_INITIAL_ERROR 0x0
885#define BUD_CHECKSUM_ERROR 0x1
886#define BUD_ADAPTER_RAM_ERROR 0x2
887#define BUD_INSTRUCTION_ERROR 0x3
888#define BUD_CONTEXT_ERROR 0x4
889#define BUD_PROTOCOL_ERROR 0x5
890#define BUD_INTERFACE_ERROR 0x6
891
892/* BUD constants */
893#define BUD_MAX_RETRIES 3
894#define BUD_MAX_LOOPCNT 6
895#define BUD_TIMEOUT 3000
896
897/* Initialization constants */
898#define INIT_MAX_RETRIES 3 /* Maximum three retries. */
899#define INIT_MAX_LOOPCNT 22 /* Maximum loop counts. */
900
901/* RING STATUS field values (high/low) */
902#define SIGNAL_LOSS 0x0080 /* Loss of signal on the ring
903 * detected.
904 */
905#define HARD_ERROR 0x0040 /* Transmitting or receiving beacon
906 * frames.
907 */
908#define SOFT_ERROR 0x0020 /* Report error MAC frame
909 * transmitted.
910 */
911#define TRANSMIT_BEACON 0x0010 /* Transmitting beacon frames on the
912 * ring.
913 */
914#define LOBE_WIRE_FAULT 0x0008 /* Open or short circuit in the
915 * cable to concentrator; adapter
916 * closed.
917 */
918#define AUTO_REMOVAL_ERROR 0x0004 /* Lobe wrap test failed, deinserted;
919 * adapter closed.
920 */
921#define REMOVE_RECEIVED 0x0001 /* Received a remove ring station MAC
922 * MAC frame request; adapter closed.
923 */
924#define COUNTER_OVERFLOW 0x8000 /* Overflow of one of the adapters
925 * error counters; READ.ERROR.LOG.
926 */
927#define SINGLE_STATION 0x4000 /* Adapter is the only station on the
928 * ring.
929 */
930#define RING_RECOVERY 0x2000 /* Claim token MAC frames on the ring;
931 * reset after ring purge frame.
932 */
933
934#define ADAPTER_CLOSED (LOBE_WIRE_FAULT | AUTO_REMOVAL_ERROR |\
935 REMOVE_RECEIVED)
936
937/* Adapter_check_block.Status field bit assignments: */
938#define DIO_PARITY 0x8000 /* Adapter detects bad parity
939 * through direct I/O access.
940 */
941#define DMA_READ_ABORT 0x4000 /* Aborting DMA read operation
942 * from system Parm[0]: 0=timeout,
943 * 1=parity error, 2=bus error;
944 * Parm[1]: 32 bit pointer to host
945 * system address at failure.
946 */
947#define DMA_WRITE_ABORT 0x2000 /* Aborting DMA write operation
948 * to system. (parameters analogous to
949 * DMA_READ_ABORT)
950 */
951#define ILLEGAL_OP_CODE 0x1000 /* Illegal operation code in the
952 * the adapters firmware Parm[0]-2:
953 * communications processor registers
954 * R13-R15.
955 */
956#define PARITY_ERRORS 0x0800 /* Adapter detects internal bus
957 * parity error.
958 */
959#define RAM_DATA_ERROR 0x0080 /* Valid only during RAM testing;
960 * RAM data error Parm[0-1]: 32 bit
961 * pointer to RAM location.
962 */
963#define RAM_PARITY_ERROR 0x0040 /* Valid only during RAM testing;
964 * RAM parity error Parm[0-1]: 32 bit
965 * pointer to RAM location.
966 */
967#define RING_UNDERRUN 0x0020 /* Internal DMA underrun when
968 * transmitting onto ring.
969 */
970#define INVALID_IRQ 0x0008 /* Unrecognized interrupt generated
971 * internal to adapter Parm[0-2]:
972 * adapter register R13-R15.
973 */
974#define INVALID_ERROR_IRQ 0x0004 /* Unrecognized error interrupt
975 * generated Parm[0-2]: adapter register
976 * R13-R15.
977 */
978#define INVALID_XOP 0x0002 /* Unrecognized XOP request in
979 * communication processor Parm[0-2]:
980 * adapter register R13-R15.
981 */
982#define CHECKADDR 0x05E0 /* Adapter check status information
983 * address offset.
984 */
985#define ROM_PAGE_0 0x0000 /* Adapter ROM page 0. */
986
987/*
988 * RECEIVE.STATUS interrupt result SSB values: (high-low)
989 * (RECEIVE_COMPLETE field bit definitions in SSB.Parm[0])
990 */
991#define RX_COMPLETE 0x0080 /* SSB.Parm[0]; SSB.Parm[1]: 32
992 * bit pointer to last RPL.
993 */
994#define RX_SUSPENDED 0x0040 /* SSB.Parm[0]; SSB.Parm[1]: 32
995 * bit pointer to RPL with odd
996 * forward pointer.
997 */
998
999/* Valid receive CSTAT: */
1000#define RX_FRAME_CONTROL_BITS (RX_VALID | RX_START_FRAME | RX_END_FRAME | \
1001 RX_FRAME_COMPLETE)
1002#define VALID_SINGLE_BUFFER_FRAME (RX_START_FRAME | RX_END_FRAME | \
1003 RX_FRAME_COMPLETE)
1004
1005typedef enum SKB_STAT SKB_STAT;
1006enum SKB_STAT {
1007 SKB_UNAVAILABLE,
1008 SKB_DMA_DIRECT,
1009 SKB_DATA_COPY
1010};
1011
1012/* Receive Parameter List (RPL) The length of the RPLs has to be initialized
1013 * in the OPL. (OPEN parameter list)
1014 */
1015#define RPL_NUM 3
1016
1017#define RX_FRAG_NUM 1 /* Maximal number of used fragments in one RPL.
1018 * (up to firmware v2.24: 3, now: up to 9)
1019 */
1020
1021#pragma pack(1)
1022typedef struct s_RPL RPL;
1023struct s_RPL { /* Receive Parameter List */
1024 u_int32_t NextRPLAddr; /* Pointer to next RPL in chain
1025 * (normalized = physical 32 bit
1026 * address) if pointer is odd: this
1027 * is last RPL. Pointing to itself can
1028 * cause problems!
1029 */
1030 volatile u_int16_t Status; /* Set by creation of Receive Parameter
1031 * List RECEIVE_CSTAT_COMPLETE set by
1032 * adapter in lists that start or end
1033 * a frame.
1034 */
1035 volatile u_int16_t FrameSize; /* Number of bytes received as a
1036 * frame including AC/FC, Destination,
1037 * Source, Routing field not including
1038 * CRC, FS (Frame Status), End Delimiter
1039 * (valid only if START_FRAME bit in
1040 * CSTAT nonzero) must not be zero in
1041 * any list; maximum value: (BUFFER_SIZE
1042 * - 8) * TX_BUF_MAX sum of DataCount
1043 * values in FragmentList must equal
1044 * Frame_Size value in START_FRAME TPL!
1045 * frame data fragment list
1046 */
1047
1048 /* TPL/RPL size in OPEN parameter list depending on maximal numbers
1049 * of fragments used in one parameter list.
1050 */
1051 Fragment FragList[RX_FRAG_NUM]; /* Maximum: nine frame fragments in
1052 * one TPL. Actual version of firmware:
1053 * 9 fragments possible.
1054 */
1055#pragma pack()
1056
1057 /* Special proprietary data and precalculations. */
1058 RPL *NextRPLPtr; /* Logical pointer to next RPL in chain. */
1059 unsigned char *MData;
1060 struct sk_buff *Skb;
1061 SKB_STAT SkbStat;
1062 int RPLIndex;
1063 dma_addr_t DMABuff; /* DMA IO bus address from pci_map */
1064};
1065
1066/* Information that need to be kept for each board. */
1067typedef struct net_local {
1068#pragma pack(1)
1069 IPB ipb; /* Initialization Parameter Block. */
1070 SCB scb; /* System Command Block: system to adapter
1071 * communication.
1072 */
1073 SSB ssb; /* System Status Block: adapter to system
1074 * communication.
1075 */
1076 OPB ocpl; /* Open Options Parameter Block. */
1077
1078 ERRORTAB errorlogtable; /* Adapter statistic error counters.
1079 * (read from adapter memory)
1080 */
1081 unsigned char ProductID[PROD_ID_SIZE + 1]; /* Product ID */
1082#pragma pack()
1083
1084 TPL Tpl[TPL_NUM];
1085 TPL *TplFree;
1086 TPL *TplBusy;
1087 unsigned char LocalTxBuffers[TPL_NUM][DEFAULT_PACKET_SIZE];
1088
1089 RPL Rpl[RPL_NUM];
1090 RPL *RplHead;
1091 RPL *RplTail;
1092 unsigned char LocalRxBuffers[RPL_NUM][DEFAULT_PACKET_SIZE];
1093
1094 struct pci_dev *pdev;
1095 int DataRate;
1096 unsigned char ScbInUse;
1097 unsigned short CMDqueue;
1098
1099 unsigned long AdapterOpenFlag:1;
1100 unsigned long AdapterVirtOpenFlag:1;
1101 unsigned long OpenCommandIssued:1;
1102 unsigned long TransmitCommandActive:1;
1103 unsigned long TransmitHaltScheduled:1;
1104 unsigned long HaltInProgress:1;
1105 unsigned long LobeWireFaultLogged:1;
1106 unsigned long ReOpenInProgress:1;
1107 unsigned long Sleeping:1;
1108
1109 unsigned long LastOpenStatus;
1110 unsigned short CurrentRingStatus;
1111 unsigned long MaxPacketSize;
1112
1113 unsigned long StartTime;
1114 unsigned long LastSendTime;
1115
1116 struct tr_statistics MacStat; /* MAC statistics structure */
1117
1118 unsigned long dmalimit; /* the max DMA address (ie, ISA) */
1119 dma_addr_t dmabuffer; /* the DMA bus address corresponding to
1120 priv. Might be different from virt_to_bus()
1121 for architectures with IO MMU (Alpha) */
1122
1123 struct timer_list timer;
1124
1125 wait_queue_head_t wait_for_tok_int;
1126
1127 INTPTRS intptrs; /* Internal adapter pointer. Must be read
1128 * before OPEN command.
1129 */
1130 unsigned short (*setnselout)(struct net_device *);
1131 unsigned short (*sifreadb)(struct net_device *, unsigned short);
1132 void (*sifwriteb)(struct net_device *, unsigned short, unsigned short);
1133 unsigned short (*sifreadw)(struct net_device *, unsigned short);
1134 void (*sifwritew)(struct net_device *, unsigned short, unsigned short);
1135
1136 spinlock_t lock; /* SMP protection */
1137 void *tmspriv;
1138} NET_LOCAL;
1139
1140#endif /* __KERNEL__ */
1141#endif /* __LINUX_TMS380TR_H */
diff --git a/drivers/net/tokenring/tmspci.c b/drivers/net/tokenring/tmspci.c
new file mode 100644
index 000000000000..37ddb5c2bec3
--- /dev/null
+++ b/drivers/net/tokenring/tmspci.c
@@ -0,0 +1,267 @@
1/*
2 * tmspci.c: A generic network driver for TMS380-based PCI token ring cards.
3 *
4 * Written 1999 by Adam Fritzler
5 *
6 * This software may be used and distributed according to the terms
7 * of the GNU General Public License, incorporated herein by reference.
8 *
9 * This driver module supports the following cards:
10 * - SysKonnect TR4/16(+) PCI (SK-4590)
11 * - SysKonnect TR4/16 PCI (SK-4591)
12 * - Compaq TR 4/16 PCI
13 * - Thomas-Conrad TC4048 4/16 PCI
14 * - 3Com 3C339 Token Link Velocity
15 *
16 * Maintainer(s):
17 * AF Adam Fritzler mid@auk.cx
18 *
19 * Modification History:
20 * 30-Dec-99 AF Split off from the tms380tr driver.
21 * 22-Jan-00 AF Updated to use indirect read/writes
22 * 23-Nov-00 JG New PCI API, cleanups
23 *
24 * TODO:
25 * 1. See if we can use MMIO instead of port accesses
26 *
27 */
28
29#include <linux/module.h>
30#include <linux/kernel.h>
31#include <linux/errno.h>
32#include <linux/pci.h>
33#include <linux/init.h>
34#include <linux/netdevice.h>
35#include <linux/trdevice.h>
36
37#include <asm/system.h>
38#include <asm/io.h>
39#include <asm/irq.h>
40
41#include "tms380tr.h"
42
43static char version[] __devinitdata =
44"tmspci.c: v1.02 23/11/2000 by Adam Fritzler\n";
45
46#define TMS_PCI_IO_EXTENT 32
47
48struct card_info {
49 unsigned char nselout[2]; /* NSELOUT vals for 4mb([0]) and 16mb([1]) */
50 char *name;
51};
52
53static struct card_info card_info_table[] = {
54 { {0x03, 0x01}, "Compaq 4/16 TR PCI"},
55 { {0x03, 0x01}, "SK NET TR 4/16 PCI"},
56 { {0x03, 0x01}, "Thomas-Conrad TC4048 PCI 4/16"},
57 { {0x03, 0x01}, "3Com Token Link Velocity"},
58};
59
60static struct pci_device_id tmspci_pci_tbl[] = {
61 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_TOKENRING, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
62 { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_TR, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
63 { PCI_VENDOR_ID_TCONRAD, PCI_DEVICE_ID_TCONRAD_TOKENRING, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
64 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C339, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
65 { } /* Terminating entry */
66};
67MODULE_DEVICE_TABLE(pci, tmspci_pci_tbl);
68
69MODULE_LICENSE("GPL");
70
71static void tms_pci_read_eeprom(struct net_device *dev);
72static unsigned short tms_pci_setnselout_pins(struct net_device *dev);
73
74static unsigned short tms_pci_sifreadb(struct net_device *dev, unsigned short reg)
75{
76 return inb(dev->base_addr + reg);
77}
78
79static unsigned short tms_pci_sifreadw(struct net_device *dev, unsigned short reg)
80{
81 return inw(dev->base_addr + reg);
82}
83
84static void tms_pci_sifwriteb(struct net_device *dev, unsigned short val, unsigned short reg)
85{
86 outb(val, dev->base_addr + reg);
87}
88
89static void tms_pci_sifwritew(struct net_device *dev, unsigned short val, unsigned short reg)
90{
91 outw(val, dev->base_addr + reg);
92}
93
94static int __devinit tms_pci_attach(struct pci_dev *pdev, const struct pci_device_id *ent)
95{
96 static int versionprinted;
97 struct net_device *dev;
98 struct net_local *tp;
99 int i, ret;
100 unsigned int pci_irq_line;
101 unsigned long pci_ioaddr;
102 struct card_info *cardinfo = &card_info_table[ent->driver_data];
103
104 if (versionprinted++ == 0)
105 printk("%s", version);
106
107 if (pci_enable_device(pdev))
108 return -EIO;
109
110 /* Remove I/O space marker in bit 0. */
111 pci_irq_line = pdev->irq;
112 pci_ioaddr = pci_resource_start (pdev, 0);
113
114 /* At this point we have found a valid card. */
115 dev = alloc_trdev(sizeof(struct net_local));
116 if (!dev)
117 return -ENOMEM;
118 SET_MODULE_OWNER(dev);
119
120 if (!request_region(pci_ioaddr, TMS_PCI_IO_EXTENT, dev->name)) {
121 ret = -EBUSY;
122 goto err_out_trdev;
123 }
124
125 ret = request_irq(pdev->irq, tms380tr_interrupt, SA_SHIRQ,
126 dev->name, dev);
127 if (ret)
128 goto err_out_region;
129
130 dev->base_addr = pci_ioaddr;
131 dev->irq = pci_irq_line;
132 dev->dma = 0;
133
134 printk("%s: %s\n", dev->name, cardinfo->name);
135 printk("%s: IO: %#4lx IRQ: %d\n",
136 dev->name, dev->base_addr, dev->irq);
137
138 tms_pci_read_eeprom(dev);
139
140 printk("%s: Ring Station Address: ", dev->name);
141 printk("%2.2x", dev->dev_addr[0]);
142 for (i = 1; i < 6; i++)
143 printk(":%2.2x", dev->dev_addr[i]);
144 printk("\n");
145
146 ret = tmsdev_init(dev, PCI_MAX_ADDRESS, pdev);
147 if (ret) {
148 printk("%s: unable to get memory for dev->priv.\n", dev->name);
149 goto err_out_irq;
150 }
151
152 tp = dev->priv;
153 tp->setnselout = tms_pci_setnselout_pins;
154
155 tp->sifreadb = tms_pci_sifreadb;
156 tp->sifreadw = tms_pci_sifreadw;
157 tp->sifwriteb = tms_pci_sifwriteb;
158 tp->sifwritew = tms_pci_sifwritew;
159
160 memcpy(tp->ProductID, cardinfo->name, PROD_ID_SIZE + 1);
161
162 tp->tmspriv = cardinfo;
163
164 dev->open = tms380tr_open;
165 dev->stop = tms380tr_close;
166 pci_set_drvdata(pdev, dev);
167 SET_NETDEV_DEV(dev, &pdev->dev);
168
169 ret = register_netdev(dev);
170 if (ret)
171 goto err_out_tmsdev;
172
173 return 0;
174
175err_out_tmsdev:
176 pci_set_drvdata(pdev, NULL);
177 tmsdev_term(dev);
178err_out_irq:
179 free_irq(pdev->irq, dev);
180err_out_region:
181 release_region(pci_ioaddr, TMS_PCI_IO_EXTENT);
182err_out_trdev:
183 free_netdev(dev);
184 return ret;
185}
186
187/*
188 * Reads MAC address from adapter RAM, which should've read it from
189 * the onboard ROM.
190 *
191 * Calling this on a board that does not support it can be a very
192 * dangerous thing. The Madge board, for instance, will lock your
193 * machine hard when this is called. Luckily, its supported in a
194 * separate driver. --ASF
195 */
196static void tms_pci_read_eeprom(struct net_device *dev)
197{
198 int i;
199
200 /* Address: 0000:0000 */
201 tms_pci_sifwritew(dev, 0, SIFADX);
202 tms_pci_sifwritew(dev, 0, SIFADR);
203
204 /* Read six byte MAC address data */
205 dev->addr_len = 6;
206 for(i = 0; i < 6; i++)
207 dev->dev_addr[i] = tms_pci_sifreadw(dev, SIFINC) >> 8;
208}
209
210static unsigned short tms_pci_setnselout_pins(struct net_device *dev)
211{
212 unsigned short val = 0;
213 struct net_local *tp = dev->priv;
214 struct card_info *cardinfo = tp->tmspriv;
215
216 if(tp->DataRate == SPEED_4)
217 val |= cardinfo->nselout[0]; /* Set 4Mbps */
218 else
219 val |= cardinfo->nselout[1]; /* Set 16Mbps */
220 return val;
221}
222
223static void __devexit tms_pci_detach (struct pci_dev *pdev)
224{
225 struct net_device *dev = pci_get_drvdata(pdev);
226
227 if (!dev)
228 BUG();
229 unregister_netdev(dev);
230 release_region(dev->base_addr, TMS_PCI_IO_EXTENT);
231 free_irq(dev->irq, dev);
232 tmsdev_term(dev);
233 free_netdev(dev);
234 pci_set_drvdata(pdev, NULL);
235}
236
237static struct pci_driver tms_pci_driver = {
238 .name = "tmspci",
239 .id_table = tmspci_pci_tbl,
240 .probe = tms_pci_attach,
241 .remove = __devexit_p(tms_pci_detach),
242};
243
244static int __init tms_pci_init (void)
245{
246 return pci_register_driver(&tms_pci_driver);
247}
248
249static void __exit tms_pci_rmmod (void)
250{
251 pci_unregister_driver (&tms_pci_driver);
252}
253
254module_init(tms_pci_init);
255module_exit(tms_pci_rmmod);
256
257
258/*
259 * Local variables:
260 * compile-command: "gcc -DMODVERSIONS -DMODULE -D__KERNEL__ -Wall -Wstrict-prototypes -O6 -fomit-frame-pointer -I/usr/src/linux/drivers/net/tokenring/ -c tmspci.c"
261 * alt-compile-command: "gcc -DMODULE -D__KERNEL__ -Wall -Wstrict-prototypes -O6 -fomit-frame-pointer -I/usr/src/linux/drivers/net/tokenring/ -c tmspci.c"
262 * c-set-style "K&R"
263 * c-indent-level: 8
264 * c-basic-offset: 8
265 * tab-width: 8
266 * End:
267 */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 03:59:50 -0500