1 files changed, 76 insertions, 3 deletions

diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 3938eb35ce8c..c1075a73d66c 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -138,6 +138,8 @@
 #define   CHIPREV_5704_BX                0x21
 #define   CHIPREV_5750_AX                0x40
 #define   CHIPREV_5750_BX                0x41
+#define   CHIPREV_5784_AX                0x57840
+#define   CHIPREV_5761_AX                0x57610
 #define  GET_METAL_REV(CHIP_REV_ID)     ((CHIP_REV_ID) & 0xff)
 #define   METAL_REV_A0                   0x00
 #define   METAL_REV_A1                   0x01
@@ -866,6 +868,7 @@
 #define  CPMU_CTRL_LINK_IDLE_MODE        0x00000200
 #define  CPMU_CTRL_LINK_AWARE_MODE       0x00000400
 #define  CPMU_CTRL_LINK_SPEED_MODE       0x00004000
+#define  CPMU_CTRL_GPHY_10MB_RXONLY      0x00010000
 #define TG3_CPMU_LSPD_10MB_CLK          0x00003604
 #define  CPMU_LSPD_10MB_MACCLK_MASK      0x001f0000
 #define  CPMU_LSPD_10MB_MACCLK_6_25      0x00130000
@@ -1559,7 +1562,24 @@
 /* 0x702c unused */
 
 #define NVRAM_ADDR_LOCKOUT              0x00007030
-/* 0x7034 --> 0x7c00 unused */
+/* 0x7034 --> 0x7500 unused */
+
+#define OTP_MODE                        0x00007500
+#define OTP_MODE_OTP_THRU_GRC            0x00000001
+#define OTP_CTRL                        0x00007504
+#define OTP_CTRL_OTP_PROG_ENABLE         0x00200000
+#define OTP_CTRL_OTP_CMD_READ            0x00000000
+#define OTP_CTRL_OTP_CMD_INIT            0x00000008
+#define OTP_CTRL_OTP_CMD_START           0x00000001
+#define OTP_STATUS                      0x00007508
+#define OTP_STATUS_CMD_DONE              0x00000001
+#define OTP_ADDRESS                     0x0000750c
+#define OTP_ADDRESS_MAGIC1               0x000000a0
+#define OTP_ADDRESS_MAGIC2               0x00000080
+/* 0x7510 unused */
+
+#define OTP_READ_DATA                   0x00007514
+/* 0x7518 --> 0x7c04 unused */
 
 #define PCIE_TRANSACTION_CFG            0x00007c04
 #define PCIE_TRANS_CFG_1SHOT_MSI         0x20000000
@@ -1568,6 +1588,28 @@
 #define PCIE_PWR_MGMT_THRESH            0x00007d28
 #define PCIE_PWR_MGMT_L1_THRESH_MSK      0x0000ff00
 
+
+/* OTP bit definitions */
+#define TG3_OTP_AGCTGT_MASK             0x000000e0
+#define TG3_OTP_AGCTGT_SHIFT            1
+#define TG3_OTP_HPFFLTR_MASK            0x00000300
+#define TG3_OTP_HPFFLTR_SHIFT           1
+#define TG3_OTP_HPFOVER_MASK            0x00000400
+#define TG3_OTP_HPFOVER_SHIFT           1
+#define TG3_OTP_LPFDIS_MASK             0x00000800
+#define TG3_OTP_LPFDIS_SHIFT            11
+#define TG3_OTP_VDAC_MASK               0xff000000
+#define TG3_OTP_VDAC_SHIFT              24
+#define TG3_OTP_10BTAMP_MASK            0x0000f000
+#define TG3_OTP_10BTAMP_SHIFT           8
+#define TG3_OTP_ROFF_MASK               0x00e00000
+#define TG3_OTP_ROFF_SHIFT              11
+#define TG3_OTP_RCOFF_MASK              0x001c0000
+#define TG3_OTP_RCOFF_SHIFT             16
+
+#define TG3_OTP_DEFAULT                 0x286c1640
+
+
 #define TG3_EEPROM_MAGIC                0x669955aa
 #define TG3_EEPROM_MAGIC_FW             0xa5000000
 #define TG3_EEPROM_MAGIC_FW_MSK         0xff000000
@@ -1705,15 +1747,31 @@
 
 #define MII_TG3_DSP_RW_PORT             0x15 /* DSP coefficient read/write port */
 
-#define MII_TG3_DSP_ADDRESS             0x17 /* DSP address register */
 #define MII_TG3_EPHY_PTEST              0x17 /* 5906 PHY register */
+#define MII_TG3_DSP_ADDRESS             0x17 /* DSP address register */
+
+#define MII_TG3_DSP_TAP1                0x0001
+#define  MII_TG3_DSP_TAP1_AGCTGT_DFLT   0x0007
+#define MII_TG3_DSP_AADJ1CH0            0x001f
+#define MII_TG3_DSP_AADJ1CH3            0x601f
+#define  MII_TG3_DSP_AADJ1CH3_ADCCKADJ  0x0002
+#define MII_TG3_DSP_EXP8                0x0708
+#define  MII_TG3_DSP_EXP8_REJ2MHz       0x0001
+#define  MII_TG3_DSP_EXP8_AEDW          0x0200
+#define MII_TG3_DSP_EXP75               0x0f75
+#define MII_TG3_DSP_EXP96               0x0f96
+#define MII_TG3_DSP_EXP97               0x0f97
 
 #define MII_TG3_AUX_CTRL                0x18 /* auxilliary control register */
 
 #define MII_TG3_AUXCTL_MISC_WREN        0x8000
 #define MII_TG3_AUXCTL_MISC_FORCE_AMDIX 0x0200
 #define MII_TG3_AUXCTL_MISC_RDSEL_MISC  0x7000
-#define MII_TG3_AUXCTL_SHDWSEL_MISC             0x0007
+#define MII_TG3_AUXCTL_SHDWSEL_MISC     0x0007
+
+#define MII_TG3_AUXCTL_ACTL_SMDSP_ENA   0x0800
+#define MII_TG3_AUXCTL_ACTL_TX_6DB      0x0400
+#define MII_TG3_AUXCTL_SHDWSEL_AUXCTL   0x0000
 
 #define MII_TG3_AUX_STAT                0x19 /* auxilliary status register */
 #define MII_TG3_AUX_STAT_LPASS          0x0004
@@ -1743,6 +1801,20 @@
 #define MII_TG3_INT_DUPLEXCHG           0x0008
 #define MII_TG3_INT_ANEG_PAGE_RX        0x0400
 
+#define MII_TG3_MISC_SHDW               0x1c
+#define MII_TG3_MISC_SHDW_WREN          0x8000
+#define MII_TG3_MISC_SHDW_SCR5_SEL      0x1400
+#define MII_TG3_MISC_SHDW_APD_SEL       0x2800
+
+#define MII_TG3_MISC_SHDW_SCR5_C125OE   0x0001
+#define MII_TG3_MISC_SHDW_SCR5_DLLAPD   0x0002
+#define MII_TG3_MISC_SHDW_SCR5_SDTL     0x0004
+#define MII_TG3_MISC_SHDW_SCR5_DLPTLM   0x0008
+#define MII_TG3_MISC_SHDW_SCR5_LPED     0x0010
+
+#define MII_TG3_MISC_SHDW_APD_WKTM_84MS 0x0001
+#define MII_TG3_MISC_SHDW_APD_ENABLE    0x0020
+
 #define MII_TG3_EPHY_TEST               0x1f /* 5906 PHY register */
 #define MII_TG3_EPHY_SHADOW_EN          0x80
 
@@ -2473,6 +2545,7 @@ struct tg3 {
 #define PHY_REV_BCM5411_X0              0x1 /* Found on Netgear GA302T */
 
         u32                             led_ctrl;
+        u32                             phy_otp;
         u16                             pci_cmd;
 
         char                            board_part_number[24];