1 files changed, 23 insertions, 2 deletions

diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 8a167912902b..e7f6214a1680 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -1206,14 +1206,18 @@
 #define  DEFAULT_MB_MACRX_LOW_WATER       0x00000020
 #define  DEFAULT_MB_MACRX_LOW_WATER_5705  0x00000010
 #define  DEFAULT_MB_MACRX_LOW_WATER_5906  0x00000004
+#define  DEFAULT_MB_MACRX_LOW_WATER_57765 0x0000002a
 #define  DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098
 #define  DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780 0x0000004b
+#define  DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765 0x0000007e
 #define BUFMGR_MB_HIGH_WATER            0x00004418
 #define  DEFAULT_MB_HIGH_WATER           0x00000060
 #define  DEFAULT_MB_HIGH_WATER_5705      0x00000060
 #define  DEFAULT_MB_HIGH_WATER_5906      0x00000010
+#define  DEFAULT_MB_HIGH_WATER_57765     0x000000a0
 #define  DEFAULT_MB_HIGH_WATER_JUMBO     0x0000017c
 #define  DEFAULT_MB_HIGH_WATER_JUMBO_5780 0x00000096
+#define  DEFAULT_MB_HIGH_WATER_JUMBO_57765 0x000000ea
 #define BUFMGR_RX_MB_ALLOC_REQ          0x0000441c
 #define  BUFMGR_MB_ALLOC_BIT             0x10000000
 #define BUFMGR_RX_MB_ALLOC_RESP         0x00004420
@@ -1543,6 +1547,8 @@
 #define  GRC_MODE_HOST_SENDBDS          0x00020000
 #define  GRC_MODE_NO_TX_PHDR_CSUM       0x00100000
 #define  GRC_MODE_NVRAM_WR_ENABLE       0x00200000
+#define  GRC_MODE_PCIE_TL_SEL           0x00000000
+#define  GRC_MODE_PCIE_PL_SEL           0x00400000
 #define  GRC_MODE_NO_RX_PHDR_CSUM       0x00800000
 #define  GRC_MODE_IRQ_ON_TX_CPU_ATTN    0x01000000
 #define  GRC_MODE_IRQ_ON_RX_CPU_ATTN    0x02000000
@@ -1550,7 +1556,13 @@
 #define  GRC_MODE_IRQ_ON_DMA_ATTN       0x08000000
 #define  GRC_MODE_IRQ_ON_FLOW_ATTN      0x10000000
 #define  GRC_MODE_4X_NIC_SEND_RINGS     0x20000000
+#define  GRC_MODE_PCIE_DL_SEL           0x20000000
 #define  GRC_MODE_MCAST_FRM_ENABLE      0x40000000
+#define  GRC_MODE_PCIE_HI_1K_EN         0x80000000
+#define  GRC_MODE_PCIE_PORT_MASK        (GRC_MODE_PCIE_TL_SEL | \
+                                         GRC_MODE_PCIE_PL_SEL | \
+                                         GRC_MODE_PCIE_DL_SEL | \
+                                         GRC_MODE_PCIE_HI_1K_EN)
 #define GRC_MISC_CFG                    0x00006804
 #define  GRC_MISC_CFG_CORECLK_RESET     0x00000001
 #define  GRC_MISC_CFG_PRESCALAR_MASK    0x000000fe
@@ -1804,6 +1816,11 @@
 /* 0x7e74 --> 0x8000 unused */
 
 
+/* Alternate PCIE definitions */
+#define TG3_PCIE_TLDLPL_PORT            0x00007c00
+#define TG3_PCIE_PL_LO_PHYCTL1           0x00000004
+#define TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN         0x00001000
+
 /* OTP bit definitions */
 #define TG3_OTP_AGCTGT_MASK             0x000000e0
 #define TG3_OTP_AGCTGT_SHIFT            1
@@ -2812,6 +2829,7 @@ struct tg3 {
 #define TG3_FLG3_40BIT_DMA_LIMIT_BUG    0x00100000
 #define TG3_FLG3_SHORT_DMA_BUG          0x00200000
 #define TG3_FLG3_USE_JUMBO_BDFLAG       0x00400000
+#define TG3_FLG3_L1PLLPD_EN             0x00800000
 
         struct timer_list               timer;
         u16                             timer_counter;
@@ -2878,7 +2896,9 @@ struct tg3 {
 #define PHY_ID_BCM5756                  0xbc050ed0
 #define PHY_ID_BCM5784                  0xbc050fa0
 #define PHY_ID_BCM5761                  0xbc050fd0
-#define PHY_ID_BCM5717                  0x5c0d8a00
+#define PHY_ID_BCM5718C                 0x5c0d8a00
+#define PHY_ID_BCM5718S                 0xbc050ff0
+#define PHY_ID_BCM57765                 0x5c0d8a40
 #define PHY_ID_BCM5906                  0xdc00ac40
 #define PHY_ID_BCM8002                  0x60010140
 #define PHY_ID_INVALID                  0xffffffff
@@ -2921,7 +2941,8 @@ struct tg3 {
          (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \
          (X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM5756 || \
          (X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM5761 || \
-         (X) == PHY_ID_BCM5717 || (X) == PHY_ID_BCM8002)
+         (X) == PHY_ID_BCM5718C || (X) == PHY_ID_BCM5718S || \
+         (X) == PHY_ID_BCM57765 || (X) == PHY_ID_BCM8002)
 
         struct tg3_hw_stats             *hw_stats;
         dma_addr_t                      stats_mapping;