1 files changed, 76 insertions, 23 deletions

diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index bab7940158e6..cd30889650f8 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -46,10 +46,15 @@
 #define  TG3PCI_DEVICE_TIGON3_57788      0x1691
 #define  TG3PCI_DEVICE_TIGON3_5785_G     0x1699 /* GPHY */
 #define  TG3PCI_DEVICE_TIGON3_5785_F     0x16a0 /* 10/100 only */
-#define  TG3PCI_DEVICE_TIGON3_5717C      0x1655
-#define  TG3PCI_DEVICE_TIGON3_5717S      0x1656
-#define  TG3PCI_DEVICE_TIGON3_5718C      0x1665
-#define  TG3PCI_DEVICE_TIGON3_5718S      0x1666
+#define  TG3PCI_DEVICE_TIGON3_5717       0x1655
+#define  TG3PCI_DEVICE_TIGON3_5718       0x1656
+#define  TG3PCI_DEVICE_TIGON3_5724       0x165c
+#define  TG3PCI_DEVICE_TIGON3_57781      0x16b1
+#define  TG3PCI_DEVICE_TIGON3_57785      0x16b5
+#define  TG3PCI_DEVICE_TIGON3_57761      0x16b0
+#define  TG3PCI_DEVICE_TIGON3_57765      0x16b4
+#define  TG3PCI_DEVICE_TIGON3_57791      0x16b2
+#define  TG3PCI_DEVICE_TIGON3_57795      0x16b6
 /* 0x04 --> 0x64 unused */
 #define TG3PCI_MSI_DATA                 0x00000064
 /* 0x66 --> 0x68 unused */
@@ -103,6 +108,7 @@
 #define  CHIPREV_ID_5906_A1              0xc001
 #define  CHIPREV_ID_57780_A0             0x57780000
 #define  CHIPREV_ID_57780_A1             0x57780001
+#define  CHIPREV_ID_5717_A0              0x05717000
 #define  GET_ASIC_REV(CHIP_REV_ID)      ((CHIP_REV_ID) >> 12)
 #define   ASIC_REV_5700                  0x07
 #define   ASIC_REV_5701                  0x00
@@ -122,6 +128,7 @@
 #define   ASIC_REV_5785                  0x5785
 #define   ASIC_REV_57780                 0x57780
 #define   ASIC_REV_5717                  0x5717
+#define   ASIC_REV_57765                 0x57785
 #define  GET_CHIP_REV(CHIP_REV_ID)      ((CHIP_REV_ID) >> 8)
 #define   CHIPREV_5700_AX                0x70
 #define   CHIPREV_5700_BX                0x71
@@ -141,8 +148,7 @@
 #define   METAL_REV_B1                   0x01
 #define   METAL_REV_B2                   0x02
 #define TG3PCI_DMA_RW_CTRL              0x0000006c
-#define  DMA_RWCTRL_MIN_DMA              0x000000ff
-#define  DMA_RWCTRL_MIN_DMA_SHIFT        0
+#define  DMA_RWCTRL_DIS_CACHE_ALIGNMENT  0x00000001
 #define  DMA_RWCTRL_READ_BNDRY_MASK      0x00000700
 #define  DMA_RWCTRL_READ_BNDRY_DISAB     0x00000000
 #define  DMA_RWCTRL_READ_BNDRY_16        0x00000100
@@ -221,6 +227,7 @@
 /* 0xc0 --> 0xf4 unused */
 
 #define TG3PCI_GEN2_PRODID_ASICREV      0x000000f4
+#define TG3PCI_GEN15_PRODID_ASICREV     0x000000fc
 /* 0xf8 --> 0x200 unused */
 
 #define TG3_CORR_ERR_STAT               0x00000110
@@ -242,7 +249,11 @@
 #define MAILBOX_GENERAL_7               0x00000258 /* 64-bit */
 #define MAILBOX_RELOAD_STAT             0x00000260 /* 64-bit */
 #define MAILBOX_RCV_STD_PROD_IDX        0x00000268 /* 64-bit */
+#define TG3_RX_STD_PROD_IDX_REG         (MAILBOX_RCV_STD_PROD_IDX + \
+                                         TG3_64BIT_REG_LOW)
 #define MAILBOX_RCV_JUMBO_PROD_IDX      0x00000270 /* 64-bit */
+#define TG3_RX_JMB_PROD_IDX_REG         (MAILBOX_RCV_JUMBO_PROD_IDX + \
+                                         TG3_64BIT_REG_LOW)
 #define MAILBOX_RCV_MINI_PROD_IDX       0x00000278 /* 64-bit */
 #define MAILBOX_RCVRET_CON_IDX_0        0x00000280 /* 64-bit */
 #define MAILBOX_RCVRET_CON_IDX_1        0x00000288 /* 64-bit */
@@ -1264,8 +1275,9 @@
 #define  WDMAC_MODE_FIFOURUN_ENAB        0x00000080
 #define  WDMAC_MODE_FIFOOREAD_ENAB       0x00000100
 #define  WDMAC_MODE_LNGREAD_ENAB         0x00000200
-#define  WDMAC_MODE_RX_ACCEL             0x00000400
+#define  WDMAC_MODE_RX_ACCEL             0x00000400
 #define  WDMAC_MODE_STATUS_TAG_FIX       0x20000000
+#define  WDMAC_MODE_BURST_ALL_DATA       0xc0000000
 #define WDMAC_STATUS                    0x00004c04
 #define  WDMAC_STATUS_TGTABORT           0x00000004
 #define  WDMAC_STATUS_MSTABORT           0x00000008
@@ -1809,6 +1821,11 @@
 
 #define TG3_OTP_DEFAULT                 0x286c1640
 
+
+/* Hardware Legacy NVRAM layout */
+#define TG3_NVM_VPD_OFF                 0x100
+#define TG3_NVM_VPD_LEN                 256
+
 /* Hardware Selfboot NVRAM layout */
 #define TG3_NVM_HWSB_CFG1               0x00000004
 #define  TG3_NVM_HWSB_CFG1_MAJMSK       0xf8000000
@@ -1953,10 +1970,34 @@
 #define  NIC_SRAM_MBUF_POOL_BASE5705    0x00010000
 #define  NIC_SRAM_MBUF_POOL_SIZE5705    0x0000e000
 
+
 /* Currently this is fixed. */
-#define PHY_ADDR                0x01
+#define TG3_PHY_PCIE_ADDR               0x00
+#define TG3_PHY_MII_ADDR                0x01
+
+
+/*** Tigon3 specific PHY PCIE registers. ***/
+
+#define TG3_PCIEPHY_BLOCK_ADDR          0x1f
+#define  TG3_PCIEPHY_XGXS_BLK1          0x0801
+#define  TG3_PCIEPHY_TXB_BLK            0x0861
+#define  TG3_PCIEPHY_BLOCK_SHIFT        4
+
+/* TG3_PCIEPHY_TXB_BLK */
+#define TG3_PCIEPHY_TX0CTRL1            0x15
+#define  TG3_PCIEPHY_TX0CTRL1_TXOCM     0x0003
+#define  TG3_PCIEPHY_TX0CTRL1_RDCTL     0x0008
+#define  TG3_PCIEPHY_TX0CTRL1_TXCMV     0x0030
+#define  TG3_PCIEPHY_TX0CTRL1_TKSEL     0x0040
+#define  TG3_PCIEPHY_TX0CTRL1_NB_EN     0x0400
 
-/* Tigon3 specific PHY MII registers. */
+/* TG3_PCIEPHY_XGXS_BLK1 */
+#define TG3_PCIEPHY_PWRMGMT4            0x1a
+#define TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN 0x0038
+#define TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN  0x4000
+
+
+/*** Tigon3 specific PHY MII registers. ***/
 #define  TG3_BMCR_SPEED1000             0x0040
 
 #define MII_TG3_CTRL                    0x09 /* 1000-baseT control register */
@@ -2055,6 +2096,9 @@
 #define MII_TG3_FET_SHDW_MISCCTRL       0x10
 #define  MII_TG3_FET_SHDW_MISCCTRL_MDIX 0x4000
 
+#define MII_TG3_FET_SHDW_AUXMODE4       0x1a
+#define MII_TG3_FET_SHDW_AUXMODE4_SBPD  0x0008
+
 #define MII_TG3_FET_SHDW_AUXSTAT2       0x1b
 #define  MII_TG3_FET_SHDW_AUXSTAT2_APD  0x0020
 
@@ -2410,10 +2454,6 @@ struct ring_info {
         DECLARE_PCI_UNMAP_ADDR(mapping)
 };
 
-struct tx_ring_info {
-        struct sk_buff                  *skb;
-};
-
 struct tg3_config_info {
         u32                             flags;
 };
@@ -2542,8 +2582,10 @@ struct tg3_ethtool_stats {
 };
 
 struct tg3_rx_prodring_set {
-        u32                             rx_std_ptr;
-        u32                             rx_jmb_ptr;
+        u32                             rx_std_prod_idx;
+        u32                             rx_std_cons_idx;
+        u32                             rx_jmb_prod_idx;
+        u32                             rx_jmb_cons_idx;
         struct tg3_rx_buffer_desc       *rx_std;
         struct tg3_ext_rx_buffer_desc   *rx_jmb;
         struct ring_info                *rx_std_buffers;
@@ -2571,10 +2613,11 @@ struct tg3_napi {
         u32                             consmbox;
         u32                             rx_rcb_ptr;
         u16                             *rx_rcb_prod_idx;
+        struct tg3_rx_prodring_set      *prodring;
 
         struct tg3_rx_buffer_desc       *rx_rcb;
         struct tg3_tx_buffer_desc       *tx_ring;
-        struct tx_ring_info             *tx_buffers;
+        struct ring_info                *tx_buffers;
 
         dma_addr_t                      status_mapping;
         dma_addr_t                      rx_rcb_mapping;
@@ -2654,7 +2697,7 @@ struct tg3 {
         struct vlan_group               *vlgrp;
 #endif
 
-        struct tg3_rx_prodring_set      prodring[1];
+        struct tg3_rx_prodring_set      prodring[TG3_IRQ_MAX_VECS - 1];
 
 
         /* begin "everything else" cacheline(s) section */
@@ -2725,7 +2768,7 @@ struct tg3 {
 #define TG3_FLG2_SERDES_PREEMPHASIS     0x00020000
 #define TG3_FLG2_5705_PLUS              0x00040000
 #define TG3_FLG2_5750_PLUS              0x00080000
-#define TG3_FLG2_PROTECTED_NVRAM        0x00100000
+#define TG3_FLG2_HW_TSO_3               0x00100000
 #define TG3_FLG2_USING_MSI              0x00200000
 #define TG3_FLG2_USING_MSIX             0x00400000
 #define TG3_FLG2_USING_MSI_OR_MSIX      (TG3_FLG2_USING_MSI | \
@@ -2737,7 +2780,9 @@ struct tg3 {
 #define TG3_FLG2_ICH_WORKAROUND         0x02000000
 #define TG3_FLG2_5780_CLASS             0x04000000
 #define TG3_FLG2_HW_TSO_2               0x08000000
-#define TG3_FLG2_HW_TSO                 (TG3_FLG2_HW_TSO_1 | TG3_FLG2_HW_TSO_2)
+#define TG3_FLG2_HW_TSO                 (TG3_FLG2_HW_TSO_1 | \
+                                         TG3_FLG2_HW_TSO_2 | \
+                                         TG3_FLG2_HW_TSO_3)
 #define TG3_FLG2_1SHOT_MSI              0x10000000
 #define TG3_FLG2_PHY_JITTER_BUG         0x20000000
 #define TG3_FLG2_NO_FWARE_REPORTED      0x40000000
@@ -2745,6 +2790,7 @@ struct tg3 {
         u32                             tg3_flags3;
 #define TG3_FLG3_NO_NVRAM_ADDR_TRANS    0x00000001
 #define TG3_FLG3_ENABLE_APE             0x00000002
+#define TG3_FLG3_PROTECTED_NVRAM        0x00000004
 #define TG3_FLG3_5701_DMA_BUG           0x00000008
 #define TG3_FLG3_USE_PHYLIB             0x00000010
 #define TG3_FLG3_MDIOBUS_INITED         0x00000020
@@ -2756,9 +2802,13 @@ struct tg3 {
 #define TG3_FLG3_PHY_ENABLE_APD         0x00001000
 #define TG3_FLG3_5755_PLUS              0x00002000
 #define TG3_FLG3_NO_NVRAM               0x00004000
-#define TG3_FLG3_TOGGLE_10_100_L1PLLPD  0x00008000
 #define TG3_FLG3_PHY_IS_FET             0x00010000
 #define TG3_FLG3_ENABLE_RSS             0x00020000
+#define TG3_FLG3_ENABLE_TSS             0x00040000
+#define TG3_FLG3_4G_DMA_BNDRY_BUG       0x00080000
+#define TG3_FLG3_40BIT_DMA_LIMIT_BUG    0x00100000
+#define TG3_FLG3_SHORT_DMA_BUG          0x00200000
+#define TG3_FLG3_USE_JUMBO_BDFLAG       0x00400000
 
         struct timer_list               timer;
         u16                             timer_counter;
@@ -2825,6 +2875,7 @@ struct tg3 {
 #define PHY_ID_BCM5756                  0xbc050ed0
 #define PHY_ID_BCM5784                  0xbc050fa0
 #define PHY_ID_BCM5761                  0xbc050fd0
+#define PHY_ID_BCM5717                  0x5c0d8a00
 #define PHY_ID_BCM5906                  0xdc00ac40
 #define PHY_ID_BCM8002                  0x60010140
 #define PHY_ID_INVALID                  0xffffffff
@@ -2834,6 +2885,7 @@ struct tg3 {
 #define PHY_REV_BCM5401_C0              0x6
 #define PHY_REV_BCM5411_X0              0x1 /* Found on Netgear GA302T */
 #define TG3_PHY_ID_BCM50610             0x143bd60
+#define TG3_PHY_ID_BCM50610M    0x143bd70
 #define TG3_PHY_ID_BCMAC131             0x143bc70
 #define TG3_PHY_ID_RTL8211C             0x001cc910
 #define TG3_PHY_ID_RTL8201E             0x00008200
@@ -2846,8 +2898,9 @@ struct tg3 {
         u32                             led_ctrl;
         u32                             phy_otp;
 
-        char                            board_part_number[24];
-#define TG3_VER_SIZE 32
+#define TG3_BPN_SIZE                    24
+        char                            board_part_number[TG3_BPN_SIZE];
+#define TG3_VER_SIZE                    ETHTOOL_FWVERS_LEN
         char                            fw_ver[TG3_VER_SIZE];
         u32                             nic_sram_data_cfg;
         u32                             pci_clock_ctrl;
@@ -2865,7 +2918,7 @@ struct tg3 {
          (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \
          (X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM5756 || \
          (X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM5761 || \
-         (X) == PHY_ID_BCM8002)
+         (X) == PHY_ID_BCM5717 || (X) == PHY_ID_BCM8002)
 
         struct tg3_hw_stats             *hw_stats;
         dma_addr_t                      stats_mapping;