aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/tg3.h
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/net/tg3.h')
-rw-r--r--drivers/net/tg3.h5
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 8209da5dd15f..ba2c98711c88 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -125,6 +125,7 @@
125#define CHIPREV_ID_5750_A0 0x4000 125#define CHIPREV_ID_5750_A0 0x4000
126#define CHIPREV_ID_5750_A1 0x4001 126#define CHIPREV_ID_5750_A1 0x4001
127#define CHIPREV_ID_5750_A3 0x4003 127#define CHIPREV_ID_5750_A3 0x4003
128#define CHIPREV_ID_5750_C2 0x4202
128#define CHIPREV_ID_5752_A0_HW 0x5000 129#define CHIPREV_ID_5752_A0_HW 0x5000
129#define CHIPREV_ID_5752_A0 0x6000 130#define CHIPREV_ID_5752_A0 0x6000
130#define CHIPREV_ID_5752_A1 0x6001 131#define CHIPREV_ID_5752_A1 0x6001
@@ -760,6 +761,7 @@
760#define RCVLPC_STATSCTRL_ENABLE 0x00000001 761#define RCVLPC_STATSCTRL_ENABLE 0x00000001
761#define RCVLPC_STATSCTRL_FASTUPD 0x00000002 762#define RCVLPC_STATSCTRL_FASTUPD 0x00000002
762#define RCVLPC_STATS_ENABLE 0x00002018 763#define RCVLPC_STATS_ENABLE 0x00002018
764#define RCVLPC_STATSENAB_DACK_FIX 0x00040000
763#define RCVLPC_STATSENAB_LNGBRST_RFIX 0x00400000 765#define RCVLPC_STATSENAB_LNGBRST_RFIX 0x00400000
764#define RCVLPC_STATS_INCMASK 0x0000201c 766#define RCVLPC_STATS_INCMASK 0x0000201c
765/* 0x2020 --> 0x2100 unused */ 767/* 0x2020 --> 0x2100 unused */
@@ -2137,6 +2139,7 @@ struct tg3 {
2137 struct tg3_rx_buffer_desc *rx_std; 2139 struct tg3_rx_buffer_desc *rx_std;
2138 struct ring_info *rx_std_buffers; 2140 struct ring_info *rx_std_buffers;
2139 dma_addr_t rx_std_mapping; 2141 dma_addr_t rx_std_mapping;
2142 u32 rx_std_max_post;
2140 2143
2141 struct tg3_rx_buffer_desc *rx_jumbo; 2144 struct tg3_rx_buffer_desc *rx_jumbo;
2142 struct ring_info *rx_jumbo_buffers; 2145 struct ring_info *rx_jumbo_buffers;
@@ -2191,7 +2194,7 @@ struct tg3 {
2191#define TG3_FLAG_INIT_COMPLETE 0x80000000 2194#define TG3_FLAG_INIT_COMPLETE 0x80000000
2192 u32 tg3_flags2; 2195 u32 tg3_flags2;
2193#define TG3_FLG2_RESTART_TIMER 0x00000001 2196#define TG3_FLG2_RESTART_TIMER 0x00000001
2194/* 0x00000002 available */ 2197#define TG3_FLG2_HW_TSO_1_BUG 0x00000002
2195#define TG3_FLG2_NO_ETH_WIRE_SPEED 0x00000004 2198#define TG3_FLG2_NO_ETH_WIRE_SPEED 0x00000004
2196#define TG3_FLG2_IS_5788 0x00000008 2199#define TG3_FLG2_IS_5788 0x00000008
2197#define TG3_FLG2_MAX_RXPEND_64 0x00000010 2200#define TG3_FLG2_MAX_RXPEND_64 0x00000010