diff options
Diffstat (limited to 'drivers/net/tg3.h')
| -rw-r--r-- | drivers/net/tg3.h | 38 |
1 files changed, 5 insertions, 33 deletions
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index 814d82b934db..8936edfb0438 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h | |||
| @@ -44,26 +44,7 @@ | |||
| 44 | #define TG3PCI_DEVICE_TIGON3_57760 0x1690 | 44 | #define TG3PCI_DEVICE_TIGON3_57760 0x1690 |
| 45 | #define TG3PCI_DEVICE_TIGON3_57790 0x1694 | 45 | #define TG3PCI_DEVICE_TIGON3_57790 0x1694 |
| 46 | #define TG3PCI_DEVICE_TIGON3_57720 0x168c | 46 | #define TG3PCI_DEVICE_TIGON3_57720 0x168c |
| 47 | #define TG3PCI_COMMAND 0x00000004 | 47 | /* 0x04 --> 0x64 unused */ |
| 48 | #define TG3PCI_STATUS 0x00000006 | ||
| 49 | #define TG3PCI_CCREVID 0x00000008 | ||
| 50 | #define TG3PCI_CACHELINESZ 0x0000000c | ||
| 51 | #define TG3PCI_LATTIMER 0x0000000d | ||
| 52 | #define TG3PCI_HEADERTYPE 0x0000000e | ||
| 53 | #define TG3PCI_BIST 0x0000000f | ||
| 54 | #define TG3PCI_BASE0_LOW 0x00000010 | ||
| 55 | #define TG3PCI_BASE0_HIGH 0x00000014 | ||
| 56 | /* 0x18 --> 0x2c unused */ | ||
| 57 | #define TG3PCI_SUBSYSVENID 0x0000002c | ||
| 58 | #define TG3PCI_SUBSYSID 0x0000002e | ||
| 59 | #define TG3PCI_ROMADDR 0x00000030 | ||
| 60 | #define TG3PCI_CAPLIST 0x00000034 | ||
| 61 | /* 0x35 --> 0x3c unused */ | ||
| 62 | #define TG3PCI_IRQ_LINE 0x0000003c | ||
| 63 | #define TG3PCI_IRQ_PIN 0x0000003d | ||
| 64 | #define TG3PCI_MIN_GNT 0x0000003e | ||
| 65 | #define TG3PCI_MAX_LAT 0x0000003f | ||
| 66 | /* 0x40 --> 0x64 unused */ | ||
| 67 | #define TG3PCI_MSI_DATA 0x00000064 | 48 | #define TG3PCI_MSI_DATA 0x00000064 |
| 68 | /* 0x66 --> 0x68 unused */ | 49 | /* 0x66 --> 0x68 unused */ |
| 69 | #define TG3PCI_MISC_HOST_CTRL 0x00000068 | 50 | #define TG3PCI_MISC_HOST_CTRL 0x00000068 |
| @@ -114,10 +95,6 @@ | |||
| 114 | #define CHIPREV_ID_5752_A1 0x6001 | 95 | #define CHIPREV_ID_5752_A1 0x6001 |
| 115 | #define CHIPREV_ID_5714_A2 0x9002 | 96 | #define CHIPREV_ID_5714_A2 0x9002 |
| 116 | #define CHIPREV_ID_5906_A1 0xc001 | 97 | #define CHIPREV_ID_5906_A1 0xc001 |
| 117 | #define CHIPREV_ID_5784_A0 0x5784000 | ||
| 118 | #define CHIPREV_ID_5784_A1 0x5784001 | ||
| 119 | #define CHIPREV_ID_5761_A0 0x5761000 | ||
| 120 | #define CHIPREV_ID_5761_A1 0x5761001 | ||
| 121 | #define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12) | 98 | #define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12) |
| 122 | #define ASIC_REV_5700 0x07 | 99 | #define ASIC_REV_5700 0x07 |
| 123 | #define ASIC_REV_5701 0x00 | 100 | #define ASIC_REV_5701 0x00 |
| @@ -1946,12 +1923,6 @@ | |||
| 1946 | #define MII_TG3_ISTAT 0x1a /* IRQ status register */ | 1923 | #define MII_TG3_ISTAT 0x1a /* IRQ status register */ |
| 1947 | #define MII_TG3_IMASK 0x1b /* IRQ mask register */ | 1924 | #define MII_TG3_IMASK 0x1b /* IRQ mask register */ |
| 1948 | 1925 | ||
| 1949 | #define MII_TG3_MISC_SHDW 0x1c | ||
| 1950 | #define MII_TG3_MISC_SHDW_WREN 0x8000 | ||
| 1951 | #define MII_TG3_MISC_SHDW_APD_SEL 0x2800 | ||
| 1952 | |||
| 1953 | #define MII_TG3_MISC_SHDW_APD_WKTM_84MS 0x0001 | ||
| 1954 | |||
| 1955 | /* ISTAT/IMASK event bits */ | 1926 | /* ISTAT/IMASK event bits */ |
| 1956 | #define MII_TG3_INT_LINKCHG 0x0002 | 1927 | #define MII_TG3_INT_LINKCHG 0x0002 |
| 1957 | #define MII_TG3_INT_SPEEDCHG 0x0004 | 1928 | #define MII_TG3_INT_SPEEDCHG 0x0004 |
| @@ -1960,7 +1931,9 @@ | |||
| 1960 | 1931 | ||
| 1961 | #define MII_TG3_MISC_SHDW 0x1c | 1932 | #define MII_TG3_MISC_SHDW 0x1c |
| 1962 | #define MII_TG3_MISC_SHDW_WREN 0x8000 | 1933 | #define MII_TG3_MISC_SHDW_WREN 0x8000 |
| 1963 | #define MII_TG3_MISC_SHDW_SCR5_SEL 0x1400 | 1934 | |
| 1935 | #define MII_TG3_MISC_SHDW_APD_WKTM_84MS 0x0001 | ||
| 1936 | #define MII_TG3_MISC_SHDW_APD_ENABLE 0x0020 | ||
| 1964 | #define MII_TG3_MISC_SHDW_APD_SEL 0x2800 | 1937 | #define MII_TG3_MISC_SHDW_APD_SEL 0x2800 |
| 1965 | 1938 | ||
| 1966 | #define MII_TG3_MISC_SHDW_SCR5_C125OE 0x0001 | 1939 | #define MII_TG3_MISC_SHDW_SCR5_C125OE 0x0001 |
| @@ -1968,9 +1941,8 @@ | |||
| 1968 | #define MII_TG3_MISC_SHDW_SCR5_SDTL 0x0004 | 1941 | #define MII_TG3_MISC_SHDW_SCR5_SDTL 0x0004 |
| 1969 | #define MII_TG3_MISC_SHDW_SCR5_DLPTLM 0x0008 | 1942 | #define MII_TG3_MISC_SHDW_SCR5_DLPTLM 0x0008 |
| 1970 | #define MII_TG3_MISC_SHDW_SCR5_LPED 0x0010 | 1943 | #define MII_TG3_MISC_SHDW_SCR5_LPED 0x0010 |
| 1944 | #define MII_TG3_MISC_SHDW_SCR5_SEL 0x1400 | ||
| 1971 | 1945 | ||
| 1972 | #define MII_TG3_MISC_SHDW_APD_WKTM_84MS 0x0001 | ||
| 1973 | #define MII_TG3_MISC_SHDW_APD_ENABLE 0x0020 | ||
| 1974 | 1946 | ||
| 1975 | #define MII_TG3_EPHY_TEST 0x1f /* 5906 PHY register */ | 1947 | #define MII_TG3_EPHY_TEST 0x1f /* 5906 PHY register */ |
| 1976 | #define MII_TG3_EPHY_SHADOW_EN 0x80 | 1948 | #define MII_TG3_EPHY_SHADOW_EN 0x80 |