diff options
Diffstat (limited to 'drivers/net/tg3.h')
-rw-r--r-- | drivers/net/tg3.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index dcdfc084966c..4d334cf5a243 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h | |||
@@ -1150,6 +1150,9 @@ | |||
1150 | #define VCPU_STATUS_INIT_DONE 0x04000000 | 1150 | #define VCPU_STATUS_INIT_DONE 0x04000000 |
1151 | #define VCPU_STATUS_DRV_RESET 0x08000000 | 1151 | #define VCPU_STATUS_DRV_RESET 0x08000000 |
1152 | 1152 | ||
1153 | #define VCPU_CFGSHDW 0x00005104 | ||
1154 | #define VCPU_CFGSHDW_ASPM_DBNC 0x00001000 | ||
1155 | |||
1153 | /* Mailboxes */ | 1156 | /* Mailboxes */ |
1154 | #define GRCMBOX_BASE 0x00005600 | 1157 | #define GRCMBOX_BASE 0x00005600 |
1155 | #define GRCMBOX_INTERRUPT_0 0x00005800 /* 64-bit */ | 1158 | #define GRCMBOX_INTERRUPT_0 0x00005800 /* 64-bit */ |
@@ -1507,6 +1510,8 @@ | |||
1507 | #define PCIE_TRANS_CFG_1SHOT_MSI 0x20000000 | 1510 | #define PCIE_TRANS_CFG_1SHOT_MSI 0x20000000 |
1508 | #define PCIE_TRANS_CFG_LOM 0x00000020 | 1511 | #define PCIE_TRANS_CFG_LOM 0x00000020 |
1509 | 1512 | ||
1513 | #define PCIE_PWR_MGMT_THRESH 0x00007d28 | ||
1514 | #define PCIE_PWR_MGMT_L1_THRESH_MSK 0x0000ff00 | ||
1510 | 1515 | ||
1511 | #define TG3_EEPROM_MAGIC 0x669955aa | 1516 | #define TG3_EEPROM_MAGIC 0x669955aa |
1512 | #define TG3_EEPROM_MAGIC_FW 0xa5000000 | 1517 | #define TG3_EEPROM_MAGIC_FW 0xa5000000 |
@@ -1593,6 +1598,9 @@ | |||
1593 | #define SHASTA_EXT_LED_MAC 0x00010000 | 1598 | #define SHASTA_EXT_LED_MAC 0x00010000 |
1594 | #define SHASTA_EXT_LED_COMBO 0x00018000 | 1599 | #define SHASTA_EXT_LED_COMBO 0x00018000 |
1595 | 1600 | ||
1601 | #define NIC_SRAM_DATA_CFG_3 0x00000d3c | ||
1602 | #define NIC_SRAM_ASPM_DEBOUNCE 0x00000002 | ||
1603 | |||
1596 | #define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000 | 1604 | #define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000 |
1597 | 1605 | ||
1598 | #define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000 | 1606 | #define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000 |
@@ -2200,6 +2208,7 @@ struct tg3 { | |||
2200 | #define TG3_FLAG_USE_LINKCHG_REG 0x00000008 | 2208 | #define TG3_FLAG_USE_LINKCHG_REG 0x00000008 |
2201 | #define TG3_FLAG_USE_MI_INTERRUPT 0x00000010 | 2209 | #define TG3_FLAG_USE_MI_INTERRUPT 0x00000010 |
2202 | #define TG3_FLAG_ENABLE_ASF 0x00000020 | 2210 | #define TG3_FLAG_ENABLE_ASF 0x00000020 |
2211 | #define TG3_FLAG_ASPM_WORKAROUND 0x00000040 | ||
2203 | #define TG3_FLAG_POLL_SERDES 0x00000080 | 2212 | #define TG3_FLAG_POLL_SERDES 0x00000080 |
2204 | #define TG3_FLAG_MBOX_WRITE_REORDER 0x00000100 | 2213 | #define TG3_FLAG_MBOX_WRITE_REORDER 0x00000100 |
2205 | #define TG3_FLAG_PCIX_TARGET_HWBUG 0x00000200 | 2214 | #define TG3_FLAG_PCIX_TARGET_HWBUG 0x00000200 |
@@ -2288,6 +2297,7 @@ struct tg3 { | |||
2288 | u32 grc_local_ctrl; | 2297 | u32 grc_local_ctrl; |
2289 | u32 dma_rwctrl; | 2298 | u32 dma_rwctrl; |
2290 | u32 coalesce_mode; | 2299 | u32 coalesce_mode; |
2300 | u32 pwrmgmt_thresh; | ||
2291 | 2301 | ||
2292 | /* PCI block */ | 2302 | /* PCI block */ |
2293 | u16 pci_chip_rev_id; | 2303 | u16 pci_chip_rev_id; |