diff options
Diffstat (limited to 'drivers/net/tg3.h')
-rw-r--r-- | drivers/net/tg3.h | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index d515ed23841b..4d334cf5a243 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h | |||
@@ -131,6 +131,7 @@ | |||
131 | #define CHIPREV_ID_5752_A0_HW 0x5000 | 131 | #define CHIPREV_ID_5752_A0_HW 0x5000 |
132 | #define CHIPREV_ID_5752_A0 0x6000 | 132 | #define CHIPREV_ID_5752_A0 0x6000 |
133 | #define CHIPREV_ID_5752_A1 0x6001 | 133 | #define CHIPREV_ID_5752_A1 0x6001 |
134 | #define CHIPREV_ID_5714_A2 0x9002 | ||
134 | #define CHIPREV_ID_5906_A1 0xc001 | 135 | #define CHIPREV_ID_5906_A1 0xc001 |
135 | #define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12) | 136 | #define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12) |
136 | #define ASIC_REV_5700 0x07 | 137 | #define ASIC_REV_5700 0x07 |
@@ -1149,6 +1150,9 @@ | |||
1149 | #define VCPU_STATUS_INIT_DONE 0x04000000 | 1150 | #define VCPU_STATUS_INIT_DONE 0x04000000 |
1150 | #define VCPU_STATUS_DRV_RESET 0x08000000 | 1151 | #define VCPU_STATUS_DRV_RESET 0x08000000 |
1151 | 1152 | ||
1153 | #define VCPU_CFGSHDW 0x00005104 | ||
1154 | #define VCPU_CFGSHDW_ASPM_DBNC 0x00001000 | ||
1155 | |||
1152 | /* Mailboxes */ | 1156 | /* Mailboxes */ |
1153 | #define GRCMBOX_BASE 0x00005600 | 1157 | #define GRCMBOX_BASE 0x00005600 |
1154 | #define GRCMBOX_INTERRUPT_0 0x00005800 /* 64-bit */ | 1158 | #define GRCMBOX_INTERRUPT_0 0x00005800 /* 64-bit */ |
@@ -1506,6 +1510,8 @@ | |||
1506 | #define PCIE_TRANS_CFG_1SHOT_MSI 0x20000000 | 1510 | #define PCIE_TRANS_CFG_1SHOT_MSI 0x20000000 |
1507 | #define PCIE_TRANS_CFG_LOM 0x00000020 | 1511 | #define PCIE_TRANS_CFG_LOM 0x00000020 |
1508 | 1512 | ||
1513 | #define PCIE_PWR_MGMT_THRESH 0x00007d28 | ||
1514 | #define PCIE_PWR_MGMT_L1_THRESH_MSK 0x0000ff00 | ||
1509 | 1515 | ||
1510 | #define TG3_EEPROM_MAGIC 0x669955aa | 1516 | #define TG3_EEPROM_MAGIC 0x669955aa |
1511 | #define TG3_EEPROM_MAGIC_FW 0xa5000000 | 1517 | #define TG3_EEPROM_MAGIC_FW 0xa5000000 |
@@ -1592,6 +1598,9 @@ | |||
1592 | #define SHASTA_EXT_LED_MAC 0x00010000 | 1598 | #define SHASTA_EXT_LED_MAC 0x00010000 |
1593 | #define SHASTA_EXT_LED_COMBO 0x00018000 | 1599 | #define SHASTA_EXT_LED_COMBO 0x00018000 |
1594 | 1600 | ||
1601 | #define NIC_SRAM_DATA_CFG_3 0x00000d3c | ||
1602 | #define NIC_SRAM_ASPM_DEBOUNCE 0x00000002 | ||
1603 | |||
1595 | #define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000 | 1604 | #define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000 |
1596 | 1605 | ||
1597 | #define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000 | 1606 | #define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000 |
@@ -2199,7 +2208,7 @@ struct tg3 { | |||
2199 | #define TG3_FLAG_USE_LINKCHG_REG 0x00000008 | 2208 | #define TG3_FLAG_USE_LINKCHG_REG 0x00000008 |
2200 | #define TG3_FLAG_USE_MI_INTERRUPT 0x00000010 | 2209 | #define TG3_FLAG_USE_MI_INTERRUPT 0x00000010 |
2201 | #define TG3_FLAG_ENABLE_ASF 0x00000020 | 2210 | #define TG3_FLAG_ENABLE_ASF 0x00000020 |
2202 | #define TG3_FLAG_5701_REG_WRITE_BUG 0x00000040 | 2211 | #define TG3_FLAG_ASPM_WORKAROUND 0x00000040 |
2203 | #define TG3_FLAG_POLL_SERDES 0x00000080 | 2212 | #define TG3_FLAG_POLL_SERDES 0x00000080 |
2204 | #define TG3_FLAG_MBOX_WRITE_REORDER 0x00000100 | 2213 | #define TG3_FLAG_MBOX_WRITE_REORDER 0x00000100 |
2205 | #define TG3_FLAG_PCIX_TARGET_HWBUG 0x00000200 | 2214 | #define TG3_FLAG_PCIX_TARGET_HWBUG 0x00000200 |
@@ -2215,14 +2224,14 @@ struct tg3 { | |||
2215 | #define TG3_FLAG_PCI_32BIT 0x00080000 | 2224 | #define TG3_FLAG_PCI_32BIT 0x00080000 |
2216 | #define TG3_FLAG_SRAM_USE_CONFIG 0x00100000 | 2225 | #define TG3_FLAG_SRAM_USE_CONFIG 0x00100000 |
2217 | #define TG3_FLAG_TX_RECOVERY_PENDING 0x00200000 | 2226 | #define TG3_FLAG_TX_RECOVERY_PENDING 0x00200000 |
2218 | #define TG3_FLAG_SERDES_WOL_CAP 0x00400000 | 2227 | #define TG3_FLAG_WOL_CAP 0x00400000 |
2219 | #define TG3_FLAG_JUMBO_RING_ENABLE 0x00800000 | 2228 | #define TG3_FLAG_JUMBO_RING_ENABLE 0x00800000 |
2220 | #define TG3_FLAG_10_100_ONLY 0x01000000 | 2229 | #define TG3_FLAG_10_100_ONLY 0x01000000 |
2221 | #define TG3_FLAG_PAUSE_AUTONEG 0x02000000 | 2230 | #define TG3_FLAG_PAUSE_AUTONEG 0x02000000 |
2222 | #define TG3_FLAG_IN_RESET_TASK 0x04000000 | 2231 | #define TG3_FLAG_IN_RESET_TASK 0x04000000 |
2223 | #define TG3_FLAG_40BIT_DMA_BUG 0x08000000 | 2232 | #define TG3_FLAG_40BIT_DMA_BUG 0x08000000 |
2224 | #define TG3_FLAG_BROKEN_CHECKSUMS 0x10000000 | 2233 | #define TG3_FLAG_BROKEN_CHECKSUMS 0x10000000 |
2225 | #define TG3_FLAG_GOT_SERDES_FLOWCTL 0x20000000 | 2234 | #define TG3_FLAG_SUPPORT_MSI 0x20000000 |
2226 | #define TG3_FLAG_CHIP_RESETTING 0x40000000 | 2235 | #define TG3_FLAG_CHIP_RESETTING 0x40000000 |
2227 | #define TG3_FLAG_INIT_COMPLETE 0x80000000 | 2236 | #define TG3_FLAG_INIT_COMPLETE 0x80000000 |
2228 | u32 tg3_flags2; | 2237 | u32 tg3_flags2; |
@@ -2288,6 +2297,7 @@ struct tg3 { | |||
2288 | u32 grc_local_ctrl; | 2297 | u32 grc_local_ctrl; |
2289 | u32 dma_rwctrl; | 2298 | u32 dma_rwctrl; |
2290 | u32 coalesce_mode; | 2299 | u32 coalesce_mode; |
2300 | u32 pwrmgmt_thresh; | ||
2291 | 2301 | ||
2292 | /* PCI block */ | 2302 | /* PCI block */ |
2293 | u16 pci_chip_rev_id; | 2303 | u16 pci_chip_rev_id; |