diff options
Diffstat (limited to 'drivers/net/tg3.h')
-rw-r--r-- | drivers/net/tg3.h | 28 |
1 files changed, 24 insertions, 4 deletions
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index feed13dc8719..2f5e00c96016 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h | |||
@@ -24,6 +24,8 @@ | |||
24 | 24 | ||
25 | #define RX_COPY_THRESHOLD 256 | 25 | #define RX_COPY_THRESHOLD 256 |
26 | 26 | ||
27 | #define TG3_RX_INTERNAL_RING_SZ_5906 32 | ||
28 | |||
27 | #define RX_STD_MAX_SIZE 1536 | 29 | #define RX_STD_MAX_SIZE 1536 |
28 | #define RX_STD_MAX_SIZE_5705 512 | 30 | #define RX_STD_MAX_SIZE_5705 512 |
29 | #define RX_JUMBO_MAX_SIZE 0xdeadbeef /* XXX */ | 31 | #define RX_JUMBO_MAX_SIZE 0xdeadbeef /* XXX */ |
@@ -129,6 +131,7 @@ | |||
129 | #define CHIPREV_ID_5752_A0_HW 0x5000 | 131 | #define CHIPREV_ID_5752_A0_HW 0x5000 |
130 | #define CHIPREV_ID_5752_A0 0x6000 | 132 | #define CHIPREV_ID_5752_A0 0x6000 |
131 | #define CHIPREV_ID_5752_A1 0x6001 | 133 | #define CHIPREV_ID_5752_A1 0x6001 |
134 | #define CHIPREV_ID_5906_A1 0xc001 | ||
132 | #define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12) | 135 | #define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12) |
133 | #define ASIC_REV_5700 0x07 | 136 | #define ASIC_REV_5700 0x07 |
134 | #define ASIC_REV_5701 0x00 | 137 | #define ASIC_REV_5701 0x00 |
@@ -141,6 +144,7 @@ | |||
141 | #define ASIC_REV_5714 0x09 | 144 | #define ASIC_REV_5714 0x09 |
142 | #define ASIC_REV_5755 0x0a | 145 | #define ASIC_REV_5755 0x0a |
143 | #define ASIC_REV_5787 0x0b | 146 | #define ASIC_REV_5787 0x0b |
147 | #define ASIC_REV_5906 0x0c | ||
144 | #define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8) | 148 | #define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8) |
145 | #define CHIPREV_5700_AX 0x70 | 149 | #define CHIPREV_5700_AX 0x70 |
146 | #define CHIPREV_5700_BX 0x71 | 150 | #define CHIPREV_5700_BX 0x71 |
@@ -646,7 +650,8 @@ | |||
646 | #define SNDDATAI_SCTRL_FORCE_ZERO 0x00000010 | 650 | #define SNDDATAI_SCTRL_FORCE_ZERO 0x00000010 |
647 | #define SNDDATAI_STATSENAB 0x00000c0c | 651 | #define SNDDATAI_STATSENAB 0x00000c0c |
648 | #define SNDDATAI_STATSINCMASK 0x00000c10 | 652 | #define SNDDATAI_STATSINCMASK 0x00000c10 |
649 | /* 0xc14 --> 0xc80 unused */ | 653 | #define ISO_PKT_TX 0x00000c20 |
654 | /* 0xc24 --> 0xc80 unused */ | ||
650 | #define SNDDATAI_COS_CNT_0 0x00000c80 | 655 | #define SNDDATAI_COS_CNT_0 0x00000c80 |
651 | #define SNDDATAI_COS_CNT_1 0x00000c84 | 656 | #define SNDDATAI_COS_CNT_1 0x00000c84 |
652 | #define SNDDATAI_COS_CNT_2 0x00000c88 | 657 | #define SNDDATAI_COS_CNT_2 0x00000c88 |
@@ -997,11 +1002,13 @@ | |||
997 | #define BUFMGR_MB_MACRX_LOW_WATER 0x00004414 | 1002 | #define BUFMGR_MB_MACRX_LOW_WATER 0x00004414 |
998 | #define DEFAULT_MB_MACRX_LOW_WATER 0x00000020 | 1003 | #define DEFAULT_MB_MACRX_LOW_WATER 0x00000020 |
999 | #define DEFAULT_MB_MACRX_LOW_WATER_5705 0x00000010 | 1004 | #define DEFAULT_MB_MACRX_LOW_WATER_5705 0x00000010 |
1005 | #define DEFAULT_MB_MACRX_LOW_WATER_5906 0x00000004 | ||
1000 | #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098 | 1006 | #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098 |
1001 | #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780 0x0000004b | 1007 | #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780 0x0000004b |
1002 | #define BUFMGR_MB_HIGH_WATER 0x00004418 | 1008 | #define BUFMGR_MB_HIGH_WATER 0x00004418 |
1003 | #define DEFAULT_MB_HIGH_WATER 0x00000060 | 1009 | #define DEFAULT_MB_HIGH_WATER 0x00000060 |
1004 | #define DEFAULT_MB_HIGH_WATER_5705 0x00000060 | 1010 | #define DEFAULT_MB_HIGH_WATER_5705 0x00000060 |
1011 | #define DEFAULT_MB_HIGH_WATER_5906 0x00000010 | ||
1005 | #define DEFAULT_MB_HIGH_WATER_JUMBO 0x0000017c | 1012 | #define DEFAULT_MB_HIGH_WATER_JUMBO 0x0000017c |
1006 | #define DEFAULT_MB_HIGH_WATER_JUMBO_5780 0x00000096 | 1013 | #define DEFAULT_MB_HIGH_WATER_JUMBO_5780 0x00000096 |
1007 | #define BUFMGR_RX_MB_ALLOC_REQ 0x0000441c | 1014 | #define BUFMGR_RX_MB_ALLOC_REQ 0x0000441c |
@@ -1138,7 +1145,12 @@ | |||
1138 | #define TX_CPU_STATE 0x00005404 | 1145 | #define TX_CPU_STATE 0x00005404 |
1139 | #define TX_CPU_PGMCTR 0x0000541c | 1146 | #define TX_CPU_PGMCTR 0x0000541c |
1140 | 1147 | ||
1148 | #define VCPU_STATUS 0x00005100 | ||
1149 | #define VCPU_STATUS_INIT_DONE 0x04000000 | ||
1150 | #define VCPU_STATUS_DRV_RESET 0x08000000 | ||
1151 | |||
1141 | /* Mailboxes */ | 1152 | /* Mailboxes */ |
1153 | #define GRCMBOX_BASE 0x00005600 | ||
1142 | #define GRCMBOX_INTERRUPT_0 0x00005800 /* 64-bit */ | 1154 | #define GRCMBOX_INTERRUPT_0 0x00005800 /* 64-bit */ |
1143 | #define GRCMBOX_INTERRUPT_1 0x00005808 /* 64-bit */ | 1155 | #define GRCMBOX_INTERRUPT_1 0x00005808 /* 64-bit */ |
1144 | #define GRCMBOX_INTERRUPT_2 0x00005810 /* 64-bit */ | 1156 | #define GRCMBOX_INTERRUPT_2 0x00005810 /* 64-bit */ |
@@ -1398,7 +1410,10 @@ | |||
1398 | #define GRC_EEPROM_CTRL 0x00006840 | 1410 | #define GRC_EEPROM_CTRL 0x00006840 |
1399 | #define GRC_MDI_CTRL 0x00006844 | 1411 | #define GRC_MDI_CTRL 0x00006844 |
1400 | #define GRC_SEEPROM_DELAY 0x00006848 | 1412 | #define GRC_SEEPROM_DELAY 0x00006848 |
1401 | /* 0x684c --> 0x6c00 unused */ | 1413 | /* 0x684c --> 0x6890 unused */ |
1414 | #define GRC_VCPU_EXT_CTRL 0x00006890 | ||
1415 | #define GRC_VCPU_EXT_CTRL_HALT_CPU 0x00400000 | ||
1416 | #define GRC_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000 | ||
1402 | #define GRC_FASTBOOT_PC 0x00006894 /* 5752, 5755, 5787 */ | 1417 | #define GRC_FASTBOOT_PC 0x00006894 /* 5752, 5755, 5787 */ |
1403 | 1418 | ||
1404 | /* 0x6c00 --> 0x7000 unused */ | 1419 | /* 0x6c00 --> 0x7000 unused */ |
@@ -1485,7 +1500,11 @@ | |||
1485 | #define NVRAM_WRITE1 0x00007028 | 1500 | #define NVRAM_WRITE1 0x00007028 |
1486 | /* 0x702c --> 0x7400 unused */ | 1501 | /* 0x702c --> 0x7400 unused */ |
1487 | 1502 | ||
1488 | /* 0x7400 --> 0x8000 unused */ | 1503 | /* 0x7400 --> 0x7c00 unused */ |
1504 | #define PCIE_TRANSACTION_CFG 0x00007c04 | ||
1505 | #define PCIE_TRANS_CFG_1SHOT_MSI 0x20000000 | ||
1506 | #define PCIE_TRANS_CFG_LOM 0x00000020 | ||
1507 | |||
1489 | 1508 | ||
1490 | #define TG3_EEPROM_MAGIC 0x669955aa | 1509 | #define TG3_EEPROM_MAGIC 0x669955aa |
1491 | 1510 | ||
@@ -2283,6 +2302,7 @@ struct tg3 { | |||
2283 | #define PHY_ID_BCM5755 0xbc050cc0 | 2302 | #define PHY_ID_BCM5755 0xbc050cc0 |
2284 | #define PHY_ID_BCM5787 0xbc050ce0 | 2303 | #define PHY_ID_BCM5787 0xbc050ce0 |
2285 | #define PHY_ID_BCM5756 0xbc050ed0 | 2304 | #define PHY_ID_BCM5756 0xbc050ed0 |
2305 | #define PHY_ID_BCM5906 0xdc00ac40 | ||
2286 | #define PHY_ID_BCM8002 0x60010140 | 2306 | #define PHY_ID_BCM8002 0x60010140 |
2287 | #define PHY_ID_INVALID 0xffffffff | 2307 | #define PHY_ID_INVALID 0xffffffff |
2288 | #define PHY_ID_REV_MASK 0x0000000f | 2308 | #define PHY_ID_REV_MASK 0x0000000f |
@@ -2310,7 +2330,7 @@ struct tg3 { | |||
2310 | (X) == PHY_ID_BCM5752 || (X) == PHY_ID_BCM5714 || \ | 2330 | (X) == PHY_ID_BCM5752 || (X) == PHY_ID_BCM5714 || \ |
2311 | (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \ | 2331 | (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \ |
2312 | (X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM5756 || \ | 2332 | (X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM5756 || \ |
2313 | (X) == PHY_ID_BCM8002) | 2333 | (X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM8002) |
2314 | 2334 | ||
2315 | struct tg3_hw_stats *hw_stats; | 2335 | struct tg3_hw_stats *hw_stats; |
2316 | dma_addr_t stats_mapping; | 2336 | dma_addr_t stats_mapping; |