1 files changed, 43 insertions, 1 deletions

diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 1d5b2a3dd29d..da18fb220712 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -109,6 +109,9 @@
 #define  CHIPREV_ID_5714_A2              0x9002
 #define  CHIPREV_ID_5906_A1              0xc001
 #define  CHIPREV_ID_5784_A0              0x5784000
+#define  CHIPREV_ID_5784_A1              0x5784001
+#define  CHIPREV_ID_5761_A0              0x5761000
+#define  CHIPREV_ID_5761_A1              0x5761001
 #define  GET_ASIC_REV(CHIP_REV_ID)      ((CHIP_REV_ID) >> 12)
 #define   ASIC_REV_5700                  0x07
 #define   ASIC_REV_5701                  0x00
@@ -856,7 +859,31 @@
 #define  CPMU_CTRL_LINK_IDLE_MODE        0x00000200
 #define  CPMU_CTRL_LINK_AWARE_MODE       0x00000400
 #define  CPMU_CTRL_LINK_SPEED_MODE       0x00004000
-/* 0x3604 --> 0x365c unused */
+#define TG3_CPMU_LSPD_10MB_CLK          0x00003604
+#define  CPMU_LSPD_10MB_MACCLK_MASK      0x001f0000
+#define  CPMU_LSPD_10MB_MACCLK_6_25      0x00130000
+/* 0x3608 --> 0x360c unused */
+
+#define TG3_CPMU_LSPD_1000MB_CLK        0x0000360c
+#define  CPMU_LSPD_1000MB_MACCLK_62_5    0x00000000
+#define  CPMU_LSPD_1000MB_MACCLK_12_5    0x00110000
+#define  CPMU_LSPD_1000MB_MACCLK_MASK    0x001f0000
+#define TG3_CPMU_LNK_AWARE_PWRMD        0x00003610
+#define  CPMU_LNK_AWARE_MACCLK_MASK      0x001f0000
+#define  CPMU_LNK_AWARE_MACCLK_6_25      0x00130000
+/* 0x3614 --> 0x361c unused */
+
+#define TG3_CPMU_HST_ACC                0x0000361c
+#define  CPMU_HST_ACC_MACCLK_MASK        0x001f0000
+#define  CPMU_HST_ACC_MACCLK_6_25        0x00130000
+/* 0x3620 --> 0x3630 unused */
+
+#define TG3_CPMU_CLCK_STAT              0x00003630
+#define  CPMU_CLCK_STAT_MAC_CLCK_MASK    0x001f0000
+#define  CPMU_CLCK_STAT_MAC_CLCK_62_5    0x00000000
+#define  CPMU_CLCK_STAT_MAC_CLCK_12_5    0x00110000
+#define  CPMU_CLCK_STAT_MAC_CLCK_6_25    0x00130000
+/* 0x3634 --> 0x365c unused */
 
 #define TG3_CPMU_MUTEX_REQ              0x0000365c
 #define  CPMU_MUTEX_REQ_DRIVER           0x00001000
@@ -1537,6 +1564,12 @@
 #define TG3_EEPROM_MAGIC                0x669955aa
 #define TG3_EEPROM_MAGIC_FW             0xa5000000
 #define TG3_EEPROM_MAGIC_FW_MSK         0xff000000
+#define TG3_EEPROM_SB_FORMAT_MASK       0x00e00000
+#define TG3_EEPROM_SB_FORMAT_1          0x00200000
+#define TG3_EEPROM_SB_REVISION_MASK     0x001f0000
+#define TG3_EEPROM_SB_REVISION_0        0x00000000
+#define TG3_EEPROM_SB_REVISION_2        0x00020000
+#define TG3_EEPROM_SB_REVISION_3        0x00030000
 #define TG3_EEPROM_MAGIC_HW             0xabcd
 #define TG3_EEPROM_MAGIC_HW_MSK         0xffff
 
@@ -1691,6 +1724,12 @@
 #define MII_TG3_ISTAT                   0x1a /* IRQ status register */
 #define MII_TG3_IMASK                   0x1b /* IRQ mask register */
 
+#define MII_TG3_MISC_SHDW               0x1c
+#define MII_TG3_MISC_SHDW_WREN          0x8000
+#define MII_TG3_MISC_SHDW_APD_SEL       0x2800
+
+#define MII_TG3_MISC_SHDW_APD_WKTM_84MS 0x0001
+
 /* ISTAT/IMASK event bits */
 #define MII_TG3_INT_LINKCHG             0x0002
 #define MII_TG3_INT_SPEEDCHG            0x0004
@@ -1747,6 +1786,8 @@
 /* APE convenience enumerations. */
 #define TG3_APE_LOCK_MEM                4
 
+#define TG3_EEPROM_SB_F1R2_MBA_OFF      0x10
+
 
 /* There are two ways to manage the TX descriptors on the tigon3.
  * Either the descriptors are in host DMA'able memory, or they
@@ -2352,6 +2393,7 @@ struct tg3 {
         u32                             tg3_flags3;
 #define TG3_FLG3_NO_NVRAM_ADDR_TRANS    0x00000001
 #define TG3_FLG3_ENABLE_APE             0x00000002
+#define TG3_FLG3_5761_5784_AX_FIXES     0x00000004
 
         struct timer_list               timer;
         u16                             timer_counter;